repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
pgavin/carpe | hdl/tech/inferred/syncram_banked_1r1w_inferred-rtl.vhdl | 1 | 2,388 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
architecture rtl of syncram_banked_1r1w_inferred is
constant banks : natural := 2**log2_banks;
type bank_data_type is array(banks-1 downto 0) of std_ulogic_vector(word_bits-1 downto 0);
type comb_type is record
bank_re : std_ulogic_vector(banks-1 downto 0);
bank_we : std_ulogic_vector(banks-1 downto 0);
bank_rdata, bank_wdata : bank_data_type;
end record;
signal c : comb_type;
begin
bank_loop : for n in 0 to banks-1 generate
c.bank_we(n) <= we and wbanken(n);
c.bank_re(n) <= re and rbanken(n);
word_bit_loop : for m in word_bits-1 downto 0 generate
c.bank_wdata(n)(m) <= wdata(n, m);
rdata(n, m) <= c.bank_rdata(n)(m);
end generate;
syncram : entity work.syncram_1r1w(rtl)
generic map (
addr_bits => addr_bits,
data_bits => word_bits,
write_first => write_first
)
port map (
clk => clk,
we => c.bank_we(n),
waddr => waddr,
wdata => c.bank_wdata(n),
re => c.bank_re(n),
raddr => raddr,
rdata => c.bank_rdata(n)
);
end generate;
end;
| apache-2.0 | 7c765c13dcca36465a251fd65ba4541b | 0.519263 | 4.117241 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_0_0/synth/system_vga_nmsuppression_0_0.vhd | 2 | 4,831 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_nmsuppression:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_nmsuppression_0_0 IS
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_nmsuppression_0_0;
ARCHITECTURE system_vga_nmsuppression_0_0_arch OF system_vga_nmsuppression_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_nmsuppression_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_nmsuppression IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
enable : IN STD_LOGIC;
active : IN STD_LOGIC;
x_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
x_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_nmsuppression;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_nmsuppression_0_0_arch: ARCHITECTURE IS "vga_nmsuppression,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_nmsuppression_0_0_arch : ARCHITECTURE IS "system_vga_nmsuppression_0_0,vga_nmsuppression,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_nmsuppression_0_0_arch: ARCHITECTURE IS "system_vga_nmsuppression_0_0,vga_nmsuppression,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_nmsuppression,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_nmsuppression
GENERIC MAP (
ROW_WIDTH => 5
)
PORT MAP (
clk => clk,
enable => enable,
active => active,
x_addr_in => x_addr_in,
y_addr_in => y_addr_in,
hessian_in => hessian_in,
x_addr_out => x_addr_out,
y_addr_out => y_addr_out,
hessian_out => hessian_out
);
END system_vga_nmsuppression_0_0_arch;
| mit | a4bd4c08ad637f9b19837859d0cfc651 | 0.721176 | 3.591822 | false | false | false | false |
loa-org/loa-hdl | modules/peripheral_register/tb/double_buffering_tb.vhd | 2 | 5,226 | -------------------------------------------------------------------------------
-- Title : Testbench for design "double_buffering"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity double_buffering_tb is
end entity double_buffering_tb;
-------------------------------------------------------------------------------
architecture tb of double_buffering_tb is
-- component ports
signal ready_p : std_logic := '0';
signal enable_p : std_logic := '0';
signal irq_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal bank_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : double_buffering
port map (
ready_p => ready_p,
enable_p => enable_p,
irq_p => irq_p,
ack_p => ack_p,
bank_p => bank_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
-------------------------------------------------------------------------
-- Scenario 1: normal operation, STM acknowledges in time
-------------------------------------------------------------------------
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- wait until STM reacts
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-- STM acknowledges, asynchronously
wait for 3.39 ns;
ack_p <= '1';
wait for 38.3 ns;
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 2: ACK is still high when ready goes high again
-------------------------------------------------------------------------
-- Expected behaviour: keep IRQ high. Only rising edges of ready_p reset
-- the IRQ signal.
ack_p <= '1';
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- wait until STM reacts
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '0';
wait until clk = '0';
ack_p <= '1';
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 3: STM does not read data fast enough
-------------------------------------------------------------------------
-- Expected behaviour: IRQ is kept high, no bank change.
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- new data comes in 10 clock cycles
for ii in 0 to 10 loop
wait until clk = '0';
end loop; -- ii
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '1';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 4: Ready_p high very long
-------------------------------------------------------------------------
ready_p <= '0';
wait until clk = '0';
ready_p <= '1';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
ready_p <= '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration double_buffering_tb_tb_cfg of double_buffering_tb is
for tb
end for;
end double_buffering_tb_tb_cfg;
-------------------------------------------------------------------------------
| bsd-3-clause | e1825187c7aab3bd5a7046a45813d352 | 0.376961 | 4.678603 | false | false | false | false |
loa-org/loa-hdl | modules/motor_control/tb/symmetric_pwm_tb.vhd | 2 | 1,171 | library ieee;
use ieee.std_logic_1164.all;
entity symmetric_pwm_tb is
end symmetric_pwm_tb;
use work.symmetric_pwm_pkg.all;
architecture behavior of symmetric_pwm_tb is
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(7 downto 0) := (others => '0');
signal pwm : std_logic;
signal underflow : std_logic; -- Center of the 'on'-periode
signal overflow : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
reset <= '1', '0' after 50 ns; -- erzeugt Resetsignal
tb : process
begin
wait until falling_edge(reset);
value <= x"7F";
wait for 100 us;
value <= x"01";
wait for 100 us;
value <= x"FE";
wait for 100 us;
value <= x"00";
wait for 100 us;
value <= x"FF";
wait for 100 us;
end process;
uut : symmetric_pwm
generic map (
WIDTH => 8)
port map (
clk_en_p => clk_en,
value_p => value,
pwm_p => pwm,
underflow_p => underflow,
overflow_p => overflow,
reset => reset,
clk => clk);
end;
| bsd-3-clause | 98cd1a8d29245cfdd74f48193f220864 | 0.557643 | 3.31728 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/sim/system_util_vector_logic_0_0.vhd | 3 | 3,427 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY system_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_vector_logic_0_0;
ARCHITECTURE system_util_vector_logic_0_0_arch OF system_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "and",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END system_util_vector_logic_0_0_arch;
| mit | cb5f7a14e73dd37b4e54ba996d6f2c09 | 0.725708 | 3.93908 | false | false | false | false |
Bluetouffe/VHDL | Porte_AND/porteAND_tb.vhd | 2 | 1,025 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:58:21 01/15/2015
-- Design Name:
-- Module Name: porteAND_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--Testbench
library ieee;
use ieee.std_logic_1164.all;
entity tb_porteAND is
end tb_porteAND;
architecture archi of tb_porteAND is
signal entree1, entree2, sortie : std_logic;
component porteAND
port (a,b: in std_logic;
s: out std_logic);
end component;
begin
uut: porteAND port map (a => entree1, b => entree2, s => sortie);
stimuli:process
begin
entree1<='0';
entree2<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end archi;
----------------------------------
| gpl-2.0 | 14ff5c6278a432a7e1320e37d77862f3 | 0.542439 | 3.203125 | false | false | false | false |
pgavin/carpe | hdl/cpu/mmu/inst/pass/cpu_mmu_inst_pass-rtl.vhdl | 1 | 2,877 | -- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
use work.cpu_types_pkg.all;
use work.cpu_mmu_inst_types_pkg.all;
architecture rtl of cpu_mmu_inst_pass is
type reg_type is record
mmuen : std_ulogic;
vpn : cpu_vpn_type;
end record;
signal r, r_next : reg_type;
type comb_type is record
ppn : cpu_ppn_type;
end record;
signal c : comb_type;
begin
ppn_large_vpn_gen : if cpu_ppn_bits > 0 and cpu_ppn_bits <= cpu_vpn_bits generate
bit_loop : for n in cpu_ppn_bits-1 downto 0 generate
c.ppn(n) <= r.vpn(n);
end generate;
end generate;
ppn_small_vpn_gen : if cpu_ppn_bits > 0 and cpu_ppn_bits > cpu_vpn_bits generate
c.ppn(cpu_ppn_bits-1 downto cpu_vpn_bits) <= (others => '0');
c.ppn(cpu_vpn_bits-1 downto 0) <= r.vpn;
end generate;
r_next <= (
mmuen => cpu_mmu_inst_pass_ctrl_in.mmuen,
vpn => cpu_mmu_inst_pass_dp_in.vpn
);
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '0' =>
r <= (
mmuen => '0',
vpn => (others => 'X')
);
when '1' =>
r <= r_next;
when others =>
r <= (
mmuen => 'X',
vpn => (others => 'X')
);
end case;
end if;
end process;
--cpu_mmu_inst_pass_ctrl_out <= (
-- );
cpu_mmu_inst_pass_ctrl_out <= (
ready => '1',
result => (
cpu_mmu_inst_result_code_index_valid => not r.mmuen,
cpu_mmu_inst_result_code_index_error => '0',
cpu_mmu_inst_result_code_index_tlbmiss => r.mmuen,
cpu_mmu_inst_result_code_index_pf => '0'
)
);
cpu_mmu_inst_pass_dp_out <= (
ppn => c.ppn
);
end;
| apache-2.0 | 9f119da468b46cbb47f6a234cf0c91b7 | 0.505735 | 3.746094 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/synth/system_rgb565_to_rgb888_0_0.vhd | 2 | 3,795 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
| mit | a3d066f7d5cee1213dca0d6a4c569995 | 0.74809 | 3.709677 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl | 1 | 4,337 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 01:41:24 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_pll_0_0/system_vga_pll_0_0_sim_netlist.vhdl
-- Design : system_vga_pll_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0_vga_pll is
port (
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC;
clk_100 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_pll_0_0_vga_pll : entity is "vga_pll";
end system_vga_pll_0_0_vga_pll;
architecture STRUCTURE of system_vga_pll_0_0_vga_pll is
signal \^clk_12_5\ : STD_LOGIC;
signal clk_12_5_s_i_1_n_0 : STD_LOGIC;
signal \^clk_25\ : STD_LOGIC;
signal clk_25_s_i_1_n_0 : STD_LOGIC;
signal \^clk_50\ : STD_LOGIC;
signal \^clk_6_25\ : STD_LOGIC;
signal clk_6_25_s_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
begin
clk_12_5 <= \^clk_12_5\;
clk_25 <= \^clk_25\;
clk_50 <= \^clk_50\;
clk_6_25 <= \^clk_6_25\;
clk_12_5_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_12_5\,
O => clk_12_5_s_i_1_n_0
);
clk_12_5_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_25\,
CE => '1',
D => clk_12_5_s_i_1_n_0,
Q => \^clk_12_5\,
R => '0'
);
clk_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_25\,
O => clk_25_s_i_1_n_0
);
clk_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_50\,
CE => '1',
D => clk_25_s_i_1_n_0,
Q => \^clk_25\,
R => '0'
);
clk_50_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_50\,
O => p_0_in
);
clk_50_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_100,
CE => '1',
D => p_0_in,
Q => \^clk_50\,
R => '0'
);
clk_6_25_s_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^clk_6_25\,
O => clk_6_25_s_i_1_n_0
);
clk_6_25_s_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^clk_6_25\,
CE => '1',
D => clk_6_25_s_i_1_n_0,
Q => \^clk_6_25\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_pll_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_pll_0_0 : entity is "system_vga_pll_0_0,vga_pll,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_pll_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_pll_0_0 : entity is "vga_pll,Vivado 2016.4";
end system_vga_pll_0_0;
architecture STRUCTURE of system_vga_pll_0_0 is
begin
U0: entity work.system_vga_pll_0_0_vga_pll
port map (
clk_100 => clk_100,
clk_12_5 => clk_12_5,
clk_25 => clk_25,
clk_50 => clk_50,
clk_6_25 => clk_6_25
);
end STRUCTURE;
| mit | d82d0cd32dd44b7b196b66de4723d6f2 | 0.554761 | 2.924477 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/system_rgb888_to_rgb565_0_0_sim_netlist.vhdl | 1 | 2,187 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 17:42:47 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_rgb888_to_rgb565_0_0 -prefix
-- system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_rgb565_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_rgb565_0_0 : entity is "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_rgb565_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_rgb565_0_0 : entity is "rgb888_to_rgb565,Vivado 2016.4";
end system_rgb888_to_rgb565_0_0;
architecture STRUCTURE of system_rgb888_to_rgb565_0_0 is
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\^rgb_888\(23 downto 19) <= rgb_888(23 downto 19);
\^rgb_888\(15 downto 10) <= rgb_888(15 downto 10);
\^rgb_888\(7 downto 3) <= rgb_888(7 downto 3);
rgb_565(15 downto 11) <= \^rgb_888\(23 downto 19);
rgb_565(10 downto 5) <= \^rgb_888\(15 downto 10);
rgb_565(4 downto 0) <= \^rgb_888\(7 downto 3);
end STRUCTURE;
| mit | 17b116f4295d8d475648a109adf24d37 | 0.647462 | 3.449527 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/system_vga_buffer_0_0_sim_netlist.vhdl | 4 | 13,896 | -- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 22 13:46:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_buffer_0_0 -prefix
-- system_vga_buffer_0_0_ system_vga_buffer_0_0_sim_netlist.vhdl
-- Design : system_vga_buffer_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_0_0_vga_buffer is
port (
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_buffer_0_0_vga_buffer;
architecture STRUCTURE of system_vga_buffer_0_0_vga_buffer is
signal addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_data_reg_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 24 );
signal NLW_data_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of data_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of data_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of data_reg : label is 24576;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of data_reg : label is "data";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of data_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of data_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of data_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of data_reg : label is 23;
begin
\addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(0),
Q => addr_r(0),
R => '0'
);
\addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(1),
Q => addr_r(1),
R => '0'
);
\addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(2),
Q => addr_r(2),
R => '0'
);
\addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(3),
Q => addr_r(3),
R => '0'
);
\addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(4),
Q => addr_r(4),
R => '0'
);
\addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(5),
Q => addr_r(5),
R => '0'
);
\addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(6),
Q => addr_r(6),
R => '0'
);
\addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(7),
Q => addr_r(7),
R => '0'
);
\addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(8),
Q => addr_r(8),
R => '0'
);
\addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(9),
Q => addr_r(9),
R => '0'
);
\addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(0),
Q => addr_w(0),
R => '0'
);
\addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(1),
Q => addr_w(1),
R => '0'
);
\addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(2),
Q => addr_w(2),
R => '0'
);
\addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(3),
Q => addr_w(3),
R => '0'
);
\addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(4),
Q => addr_w(4),
R => '0'
);
\addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(5),
Q => addr_w(5),
R => '0'
);
\addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(6),
Q => addr_w(6),
R => '0'
);
\addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(7),
Q => addr_w(7),
R => '0'
);
\addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(8),
Q => addr_w(8),
R => '0'
);
\addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(9),
Q => addr_w(9),
R => '0'
);
\c_addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(0),
Q => c_addr_r(0),
R => '0'
);
\c_addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(1),
Q => c_addr_r(1),
R => '0'
);
\c_addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(2),
Q => c_addr_r(2),
R => '0'
);
\c_addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(3),
Q => c_addr_r(3),
R => '0'
);
\c_addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(4),
Q => c_addr_r(4),
R => '0'
);
\c_addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(5),
Q => c_addr_r(5),
R => '0'
);
\c_addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(6),
Q => c_addr_r(6),
R => '0'
);
\c_addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(7),
Q => c_addr_r(7),
R => '0'
);
\c_addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(8),
Q => c_addr_r(8),
R => '0'
);
\c_addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(9),
Q => c_addr_r(9),
R => '0'
);
\c_addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(0),
Q => c_addr_w(0),
R => '0'
);
\c_addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(1),
Q => c_addr_w(1),
R => '0'
);
\c_addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(2),
Q => c_addr_w(2),
R => '0'
);
\c_addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(3),
Q => c_addr_w(3),
R => '0'
);
\c_addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(4),
Q => c_addr_w(4),
R => '0'
);
\c_addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(5),
Q => c_addr_w(5),
R => '0'
);
\c_addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(6),
Q => c_addr_w(6),
R => '0'
);
\c_addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(7),
Q => c_addr_w(7),
R => '0'
);
\c_addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(8),
Q => c_addr_w(8),
R => '0'
);
\c_addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(9),
Q => c_addr_w(9),
R => '0'
);
data_reg: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addr_w(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => addr_r(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_DBITERR_UNCONNECTED,
DIADI(31 downto 24) => B"00000000",
DIADI(23 downto 0) => data_w(23 downto 0),
DIBDI(31 downto 0) => B"00000000111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => NLW_data_reg_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 24) => NLW_data_reg_DOBDO_UNCONNECTED(31 downto 24),
DOBDO(23 downto 0) => data_r(23 downto 0),
DOPADOP(3 downto 0) => NLW_data_reg_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_data_reg_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_data_reg_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_buffer_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_buffer_0_0 : entity is "system_vga_buffer_0_0,vga_buffer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_buffer_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_buffer_0_0 : entity is "vga_buffer,Vivado 2016.4";
end system_vga_buffer_0_0;
architecture STRUCTURE of system_vga_buffer_0_0 is
begin
U0: entity work.system_vga_buffer_0_0_vga_buffer
port map (
clk_r => clk_r,
clk_w => clk_w,
data_r(23 downto 0) => data_r(23 downto 0),
data_w(23 downto 0) => data_w(23 downto 0),
wen => wen,
x_addr_r(9 downto 0) => x_addr_r(9 downto 0),
x_addr_w(9 downto 0) => x_addr_w(9 downto 0)
);
end STRUCTURE;
| mit | daa8127a7bdec8c47bb7a7dee2c5eda0 | 0.526554 | 3.014317 | false | false | false | false |
ashikpoojari/Hardware-Security | DES CryptoCore/src/s5.vhd | 2 | 3,979 | library ieee;
use ieee.std_logic_1164.all;
entity s5 is port
(clk: in std_logic;
b : in std_logic_vector(1 to 6);
so : out std_logic_vector(1 to 4)
);
end s5;
architecture behaviour of s5 is
begin
process(b,clk)
begin
case b is
when "000000"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "000010"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "000100"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "000110"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "001000"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001010"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "001100"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "001110"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "010000"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "010010"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010100"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "010110"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "011000"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "011010"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "011100"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "011110"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "000001"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "000011"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "000101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "000111"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "001001"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "001011"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "001101"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "001111"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "010001"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "010011"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "010101"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "010111"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "011001"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "011011"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "011101"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "011111"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "100000"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "100010"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "100100"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "100110"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "101000"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "101010"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "101100"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "101110"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "110000"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "110010"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "110100"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "110110"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when "111000"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "111010"=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
when "111100"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "111110"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "100001"=> so<=To_StdLogicVector(Bit_Vector'(x"B"));
when "100011"=> so<=To_StdLogicVector(Bit_Vector'(x"8"));
when "100101"=> so<=To_StdLogicVector(Bit_Vector'(x"C"));
when "100111"=> so<=To_StdLogicVector(Bit_Vector'(x"7"));
when "101001"=> so<=To_StdLogicVector(Bit_Vector'(x"1"));
when "101011"=> so<=To_StdLogicVector(Bit_Vector'(x"E"));
when "101101"=> so<=To_StdLogicVector(Bit_Vector'(x"2"));
when "101111"=> so<=To_StdLogicVector(Bit_Vector'(x"D"));
when "110001"=> so<=To_StdLogicVector(Bit_Vector'(x"6"));
when "110011"=> so<=To_StdLogicVector(Bit_Vector'(x"F"));
when "110101"=> so<=To_StdLogicVector(Bit_Vector'(x"0"));
when "110111"=> so<=To_StdLogicVector(Bit_Vector'(x"9"));
when "111001"=> so<=To_StdLogicVector(Bit_Vector'(x"A"));
when "111011"=> so<=To_StdLogicVector(Bit_Vector'(x"4"));
when "111101"=> so<=To_StdLogicVector(Bit_Vector'(x"5"));
when others=> so<=To_StdLogicVector(Bit_Vector'(x"3"));
end case;
end process;
end; | mit | 4aa51bdb1cc1b44e7d8c06b9be7061ed | 0.673536 | 3.030465 | false | false | false | false |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/synth/system_rgb565_to_rgb888_0_0.vhd | 5 | 3,988 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
| mit | bf55f6230a6a31197052ef110d87f39d | 0.74323 | 3.689177 | false | false | false | false |
alvieboy/xtc-base | regbank_4r_2w.vhd | 1 | 5,858 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity regbank_4r_2w is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw1_wr: in std_logic_vector(31 downto 0);
rbw1_we: in std_logic;
rbw1_en: in std_logic;
rbw2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw2_wr: in std_logic_vector(31 downto 0);
rbw2_we: in std_logic;
rbw2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end entity regbank_4r_2w;
architecture behave of regbank_4r_2w is
component mux1_16 is
port (
i: in std_logic_vector(15 downto 0);
sel: in std_logic_vector(3 downto 0);
o: out std_logic
);
end component mux1_16;
--type sbtype is array(0 to 7) of std_logic;
--shared variable scoreboard: sbtype := (others => '0');
signal scoreboard: std_logic_vector((2**ADDRESS_BITS)-1 downto 0);
signal src1,src2,src3,src4: std_logic;
signal src1_sel,src2_sel,src3_sel,src4_sel: std_logic;
signal w1,w2: std_logic;
signal b1_rd_1, b1_rd_2, b1_rd_3, b1_rd_4: std_logic_vector(31 downto 0);
signal b2_rd_1, b2_rd_2, b2_rd_3, b2_rd_4: std_logic_vector(31 downto 0);
signal rb1_addr_q: std_logic_vector(ADDRESS_BITS-1 downto 0);
signal rb2_addr_q: std_logic_vector(ADDRESS_BITS-1 downto 0);
signal rb3_addr_q: std_logic_vector(ADDRESS_BITS-1 downto 0);
signal rb4_addr_q: std_logic_vector(ADDRESS_BITS-1 downto 0);
signal same_address: boolean;
signal dbg_do0, dbg_do1: std_logic_vector(31 downto 0);
begin
-- Write ports
w1 <= rbw1_en and rbw1_we;
w2 <= rbw2_en and rbw2_we;
m1: mux1_16 port map ( i => scoreboard, sel => rb1_addr_q, o => src1 );
m2: mux1_16 port map ( i => scoreboard, sel => rb2_addr_q, o => src2 );
m3: mux1_16 port map ( i => scoreboard, sel => rb3_addr_q, o => src3 );
m4: mux1_16 port map ( i => scoreboard, sel => rb4_addr_q, o => src4 );
same_address<=true when rbw1_addr=rbw2_addr else false;
process(clk)
begin
if rising_edge(clk) then
if w1='1' and w2='0' then
scoreboard( conv_integer(rbw1_addr) ) <= '0';
elsif w1='0' and w2='1' then
scoreboard( conv_integer(rbw2_addr) ) <= '1';
elsif w1='1' and w2='1' then
if same_address then
scoreboard( conv_integer(rbw1_addr) ) <= 'X';
else
scoreboard( conv_integer(rbw1_addr) ) <= '0';
scoreboard( conv_integer(rbw2_addr) ) <= '1';
end if;
else
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if rb1_en='1' then
--src1 <= src1_sel;
rb1_addr_q <= rb1_addr;
end if;
if rb2_en='1' then
--src2 <= src2_sel;
rb2_addr_q <= rb2_addr;
end if;
if rb3_en='1' then
--src3 <= src3_sel;
rb3_addr_q <= rb3_addr;
end if;
if rb4_en='1' then
rb4_addr_q <= rb4_addr;
--src4 <= src4_sel;
end if;
end if;
end process;
-- Register banks
rb1: entity work.regbank_5p
generic map (
ADDRESS_BITS => ADDRESS_BITS
)
port map (
clk => clk,
rb1_addr => rb1_addr,
rb1_en => rb1_en,
rb1_rd => b1_rd_1,
rb2_addr => rb2_addr,
rb2_en => rb2_en,
rb2_rd => b1_rd_2,
rb3_addr => rb3_addr,
rb3_en => rb3_en,
rb3_rd => b1_rd_3,
rb4_addr => rb4_addr,
rb4_en => rb4_en,
rb4_rd => b1_rd_4,
rbw_addr => rbw1_addr,
rbw_wr => rbw1_wr,
rbw_we => rbw1_we,
rbw_en => rbw1_en,
dbg_addr => dbg_addr,
dbg_do => dbg_do0
);
rb2: entity work.regbank_5p
generic map (
ADDRESS_BITS => ADDRESS_BITS
)
port map (
clk => clk,
rb1_addr => rb1_addr,
rb1_en => rb1_en,
rb1_rd => b2_rd_1,
rb2_addr => rb2_addr,
rb2_en => rb2_en,
rb2_rd => b2_rd_2,
rb3_addr => rb3_addr,
rb3_en => rb3_en,
rb3_rd => b2_rd_3,
rb4_addr => rb4_addr,
rb4_en => rb4_en,
rb4_rd => b2_rd_4,
rbw_addr => rbw2_addr,
rbw_wr => rbw2_wr,
rbw_we => rbw2_we,
rbw_en => rbw2_en,
dbg_addr => dbg_addr,
dbg_do => dbg_do1
);
-- Selectors
dbg_do <= dbg_do0 when src1='0' else dbg_do1;
rb1_rd <= b1_rd_1 when src1='0' else b2_rd_1;
rb2_rd <= b1_rd_2 when src2='0' else b2_rd_2;
rb3_rd <= b1_rd_3 when src3='0' else b2_rd_3;
rb4_rd <= b1_rd_4 when src4='0' else b2_rd_4;
-- debugging
-- synthesis translate_off
process(clk)
begin
if rising_edge(clk) then
if rbw1_we='1' and rbw1_en='1' then
--report " > (A)RegW r" & str(conv_integer(rbw1_addr)) & ", val 0x" & hstr(rbw1_wr);
end if;
if rbw2_we='1' and rbw2_en='1' then
--report " > (B)RegW r" & str(conv_integer(rbw2_addr)) & ", val 0x" & hstr(rbw2_wr);
end if;
end if;
end process;
-- synthesis translate_on
end behave;
| bsd-3-clause | 44768031a298c6db3042e9f5bd33b7c1 | 0.574599 | 2.655485 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/max_atoms.vhd | 1 | 88,232 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package max_atom_pack is
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
end max_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body max_atom_pack is
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 35 loop
if ((list(i) = '0') or (list(i) = 'L')) then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
end max_atom_pack;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for MAX Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- MAX7K_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_asynch_io is
generic ( operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
weak_pull_up : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01);
port ( datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
padio : inout STD_LOGIC;
dataout : out STD_LOGIC);
attribute VITAL_LEVEL0 of max_asynch_io : entity is TRUE;
end max_asynch_io;
architecture behave of max_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable tmp_dataout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
tmp_dataout := padio_ipd;
if ( padio_ipd = 'Z') then
if (prev_value = '1') then
tmp_dataout := 'H';
elsif (prev_value = '0') then
tmp_dataout := 'L';
end if;
end if;
prev_value := padio_ipd;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
if (prev_value = 'L') then
prev_value := 'L';
elsif (prev_value = 'H') then
prev_value := 'H';
else
prev_value := 'W';
end if;
end if;
tmp_padio := prev_value;
else
if (now <= 1 ps) then
tmp_padio := '0';
prev_value := 'L';
else
tmp_padio := 'X';
prev_value := 'W';
end if;
end if; -- end oe_in
if ( operation_mode = "bidir") then
if ((padio_ipd /= '1') and (padio_ipd /= '0')and (padio_ipd /= 'X')) then
tmp_dataout := prev_value;
else
tmp_dataout := to_x01z(padio_ipd);
end if;
else
tmp_dataout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_dataout := padio_ipd;
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_dataout = 'Z') then
tmp_dataout := 'H';
end if;
end if;
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_dataout := padio_ipd;
if (weak_pull_up = "true") then
if (tmp_dataout = 'Z') then
tmp_dataout := 'H';
end if;
end if;
else
tmp_dataout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
end if;
else
tmp_padio := datain_ipd;
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
if (weak_pull_up = "true") then
if (tmp_padio = 'Z') then
tmp_padio := 'H';
end if;
end if;
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- MAX_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
use work.max_asynch_io;
entity max_io is
generic ( operation_mode : string := "input";
open_drain_output :string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in std_logic := '0';
oe : in std_logic := '1';
devoe : in std_logic := '0';
dataout : out std_logic;
padio : inout std_logic);
end max_io;
architecture structure of max_io is
signal data_out : std_logic;
component max_asynch_io
generic ( operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '0';
padio : inout STD_LOGIC;
dataout: out STD_LOGIC);
end component;
begin
asynch_inst: max_asynch_io
generic map ( operation_mode => operation_mode,
bus_hold => bus_hold,
open_drain_output => open_drain_output,
weak_pull_up => weak_pull_up)
port map ( datain => datain,
oe => oe,
padio => padio,
dataout => data_out);
dataout <= data_out;
end structure;
--
-- MAX MCELL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_asynch_mcell is
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pterm0_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pxor_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_combout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_fpin_regin : VitalDelayType01 := DefPropDelay01;
tpd_pxor_regin : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_regin : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_pexpout : VitalDelayType01 := DefPropDelay01;
tipd_pterm0 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm1 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm2 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm3 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm4 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm5 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pxor : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_fpin : VitalDelayType01 := DefPropDelay01;
tipd_pexpin : VitalDelayType01 := DefPropDelay01);
port ( pterm0 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm1 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm2 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm3 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm4 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm5 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
fpin : in std_logic := '1';
pxor : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pexpin : in std_logic := '0';
fbkin : in std_logic;
combout : out std_logic;
regin : out std_logic;
pexpout : out std_logic );
attribute VITAL_LEVEL0 of max_asynch_mcell : entity is TRUE;
end max_asynch_mcell;
architecture vital_mcell of max_asynch_mcell is
attribute VITAL_LEVEL0 of vital_mcell : architecture is TRUE;
signal pterm0_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm1_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm2_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm3_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm4_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pterm5_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal fpin_ipd :std_ulogic := 'U';
signal pxor_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pexpin_ipd :std_ulogic := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (pterm0_ipd(0), pterm0(0), tipd_pterm0(0));
VitalWireDelay (pterm0_ipd(1), pterm0(1), tipd_pterm0(1));
VitalWireDelay (pterm0_ipd(2), pterm0(2), tipd_pterm0(2));
VitalWireDelay (pterm0_ipd(3), pterm0(3), tipd_pterm0(3));
VitalWireDelay (pterm0_ipd(4), pterm0(4), tipd_pterm0(4));
VitalWireDelay (pterm0_ipd(5), pterm0(5), tipd_pterm0(5));
VitalWireDelay (pterm0_ipd(6), pterm0(6), tipd_pterm0(6));
VitalWireDelay (pterm0_ipd(7), pterm0(7), tipd_pterm0(7));
VitalWireDelay (pterm0_ipd(8), pterm0(8), tipd_pterm0(8));
VitalWireDelay (pterm0_ipd(9), pterm0(9), tipd_pterm0(9));
VitalWireDelay (pterm0_ipd(10), pterm0(10), tipd_pterm0(10));
VitalWireDelay (pterm0_ipd(11), pterm0(11), tipd_pterm0(11));
VitalWireDelay (pterm0_ipd(12), pterm0(12), tipd_pterm0(12));
VitalWireDelay (pterm0_ipd(13), pterm0(13), tipd_pterm0(13));
VitalWireDelay (pterm0_ipd(14), pterm0(14), tipd_pterm0(14));
VitalWireDelay (pterm0_ipd(15), pterm0(15), tipd_pterm0(15));
VitalWireDelay (pterm0_ipd(16), pterm0(16), tipd_pterm0(16));
VitalWireDelay (pterm0_ipd(17), pterm0(17), tipd_pterm0(17));
VitalWireDelay (pterm0_ipd(18), pterm0(18), tipd_pterm0(18));
VitalWireDelay (pterm0_ipd(19), pterm0(19), tipd_pterm0(19));
VitalWireDelay (pterm0_ipd(20), pterm0(20), tipd_pterm0(20));
VitalWireDelay (pterm0_ipd(21), pterm0(21), tipd_pterm0(21));
VitalWireDelay (pterm0_ipd(22), pterm0(22), tipd_pterm0(22));
VitalWireDelay (pterm0_ipd(23), pterm0(23), tipd_pterm0(23));
VitalWireDelay (pterm0_ipd(24), pterm0(24), tipd_pterm0(24));
VitalWireDelay (pterm0_ipd(25), pterm0(25), tipd_pterm0(25));
VitalWireDelay (pterm0_ipd(26), pterm0(26), tipd_pterm0(26));
VitalWireDelay (pterm0_ipd(27), pterm0(27), tipd_pterm0(27));
VitalWireDelay (pterm0_ipd(28), pterm0(28), tipd_pterm0(28));
VitalWireDelay (pterm0_ipd(29), pterm0(29), tipd_pterm0(29));
VitalWireDelay (pterm0_ipd(30), pterm0(30), tipd_pterm0(30));
VitalWireDelay (pterm0_ipd(31), pterm0(31), tipd_pterm0(31));
VitalWireDelay (pterm0_ipd(32), pterm0(32), tipd_pterm0(32));
VitalWireDelay (pterm0_ipd(33), pterm0(33), tipd_pterm0(33));
VitalWireDelay (pterm0_ipd(34), pterm0(34), tipd_pterm0(34));
VitalWireDelay (pterm0_ipd(35), pterm0(35), tipd_pterm0(35));
VitalWireDelay (pterm0_ipd(36), pterm0(36), tipd_pterm0(36));
VitalWireDelay (pterm0_ipd(37), pterm0(37), tipd_pterm0(37));
VitalWireDelay (pterm0_ipd(38), pterm0(38), tipd_pterm0(38));
VitalWireDelay (pterm0_ipd(39), pterm0(39), tipd_pterm0(39));
VitalWireDelay (pterm0_ipd(40), pterm0(40), tipd_pterm0(40));
VitalWireDelay (pterm0_ipd(41), pterm0(41), tipd_pterm0(41));
VitalWireDelay (pterm0_ipd(42), pterm0(42), tipd_pterm0(42));
VitalWireDelay (pterm0_ipd(43), pterm0(43), tipd_pterm0(43));
VitalWireDelay (pterm0_ipd(44), pterm0(44), tipd_pterm0(44));
VitalWireDelay (pterm0_ipd(45), pterm0(45), tipd_pterm0(45));
VitalWireDelay (pterm0_ipd(46), pterm0(46), tipd_pterm0(46));
VitalWireDelay (pterm0_ipd(47), pterm0(47), tipd_pterm0(47));
VitalWireDelay (pterm0_ipd(48), pterm0(48), tipd_pterm0(48));
VitalWireDelay (pterm0_ipd(49), pterm0(49), tipd_pterm0(49));
VitalWireDelay (pterm0_ipd(50), pterm0(50), tipd_pterm0(50));
VitalWireDelay (pterm0_ipd(51), pterm0(51), tipd_pterm0(51));
VitalWireDelay (pterm1_ipd(0), pterm1(0), tipd_pterm1(0));
VitalWireDelay (pterm1_ipd(1), pterm1(1), tipd_pterm1(1));
VitalWireDelay (pterm1_ipd(2), pterm1(2), tipd_pterm1(2));
VitalWireDelay (pterm1_ipd(3), pterm1(3), tipd_pterm1(3));
VitalWireDelay (pterm1_ipd(4), pterm1(4), tipd_pterm1(4));
VitalWireDelay (pterm1_ipd(5), pterm1(5), tipd_pterm1(5));
VitalWireDelay (pterm1_ipd(6), pterm1(6), tipd_pterm1(6));
VitalWireDelay (pterm1_ipd(7), pterm1(7), tipd_pterm1(7));
VitalWireDelay (pterm1_ipd(8), pterm1(8), tipd_pterm1(8));
VitalWireDelay (pterm1_ipd(9), pterm1(9), tipd_pterm1(9));
VitalWireDelay (pterm1_ipd(10), pterm1(10), tipd_pterm1(10));
VitalWireDelay (pterm1_ipd(11), pterm1(11), tipd_pterm1(11));
VitalWireDelay (pterm1_ipd(12), pterm1(12), tipd_pterm1(12));
VitalWireDelay (pterm1_ipd(13), pterm1(13), tipd_pterm1(13));
VitalWireDelay (pterm1_ipd(14), pterm1(14), tipd_pterm1(14));
VitalWireDelay (pterm1_ipd(15), pterm1(15), tipd_pterm1(15));
VitalWireDelay (pterm1_ipd(16), pterm1(16), tipd_pterm1(16));
VitalWireDelay (pterm1_ipd(17), pterm1(17), tipd_pterm1(17));
VitalWireDelay (pterm1_ipd(18), pterm1(18), tipd_pterm1(18));
VitalWireDelay (pterm1_ipd(19), pterm1(19), tipd_pterm1(19));
VitalWireDelay (pterm1_ipd(20), pterm1(20), tipd_pterm1(20));
VitalWireDelay (pterm1_ipd(21), pterm1(21), tipd_pterm1(21));
VitalWireDelay (pterm1_ipd(22), pterm1(22), tipd_pterm1(22));
VitalWireDelay (pterm1_ipd(23), pterm1(23), tipd_pterm1(23));
VitalWireDelay (pterm1_ipd(24), pterm1(24), tipd_pterm1(24));
VitalWireDelay (pterm1_ipd(25), pterm1(25), tipd_pterm1(25));
VitalWireDelay (pterm1_ipd(26), pterm1(26), tipd_pterm1(26));
VitalWireDelay (pterm1_ipd(27), pterm1(27), tipd_pterm1(27));
VitalWireDelay (pterm1_ipd(28), pterm1(28), tipd_pterm1(28));
VitalWireDelay (pterm1_ipd(29), pterm1(29), tipd_pterm1(29));
VitalWireDelay (pterm1_ipd(30), pterm1(30), tipd_pterm1(30));
VitalWireDelay (pterm1_ipd(31), pterm1(31), tipd_pterm1(31));
VitalWireDelay (pterm1_ipd(32), pterm1(32), tipd_pterm1(32));
VitalWireDelay (pterm1_ipd(33), pterm1(33), tipd_pterm1(33));
VitalWireDelay (pterm1_ipd(34), pterm1(34), tipd_pterm1(34));
VitalWireDelay (pterm1_ipd(35), pterm1(35), tipd_pterm1(35));
VitalWireDelay (pterm1_ipd(36), pterm1(36), tipd_pterm1(36));
VitalWireDelay (pterm1_ipd(37), pterm1(37), tipd_pterm1(37));
VitalWireDelay (pterm1_ipd(38), pterm1(38), tipd_pterm1(38));
VitalWireDelay (pterm1_ipd(39), pterm1(39), tipd_pterm1(39));
VitalWireDelay (pterm1_ipd(40), pterm1(40), tipd_pterm1(40));
VitalWireDelay (pterm1_ipd(41), pterm1(41), tipd_pterm1(41));
VitalWireDelay (pterm1_ipd(42), pterm1(42), tipd_pterm1(42));
VitalWireDelay (pterm1_ipd(43), pterm1(43), tipd_pterm1(43));
VitalWireDelay (pterm1_ipd(44), pterm1(44), tipd_pterm1(44));
VitalWireDelay (pterm1_ipd(45), pterm1(45), tipd_pterm1(45));
VitalWireDelay (pterm1_ipd(46), pterm1(46), tipd_pterm1(46));
VitalWireDelay (pterm1_ipd(47), pterm1(47), tipd_pterm1(47));
VitalWireDelay (pterm1_ipd(48), pterm1(48), tipd_pterm1(48));
VitalWireDelay (pterm1_ipd(49), pterm1(49), tipd_pterm1(49));
VitalWireDelay (pterm1_ipd(50), pterm1(50), tipd_pterm1(50));
VitalWireDelay (pterm1_ipd(51), pterm1(51), tipd_pterm1(51));
VitalWireDelay (pterm2_ipd(0), pterm2(0), tipd_pterm2(0));
VitalWireDelay (pterm2_ipd(1), pterm2(1), tipd_pterm2(1));
VitalWireDelay (pterm2_ipd(2), pterm2(2), tipd_pterm2(2));
VitalWireDelay (pterm2_ipd(3), pterm2(3), tipd_pterm2(3));
VitalWireDelay (pterm2_ipd(4), pterm2(4), tipd_pterm2(4));
VitalWireDelay (pterm2_ipd(5), pterm2(5), tipd_pterm2(5));
VitalWireDelay (pterm2_ipd(6), pterm2(6), tipd_pterm2(6));
VitalWireDelay (pterm2_ipd(7), pterm2(7), tipd_pterm2(7));
VitalWireDelay (pterm2_ipd(8), pterm2(8), tipd_pterm2(8));
VitalWireDelay (pterm2_ipd(9), pterm2(9), tipd_pterm2(9));
VitalWireDelay (pterm2_ipd(10), pterm2(10), tipd_pterm2(10));
VitalWireDelay (pterm2_ipd(11), pterm2(11), tipd_pterm2(11));
VitalWireDelay (pterm2_ipd(12), pterm2(12), tipd_pterm2(12));
VitalWireDelay (pterm2_ipd(13), pterm2(13), tipd_pterm2(13));
VitalWireDelay (pterm2_ipd(14), pterm2(14), tipd_pterm2(14));
VitalWireDelay (pterm2_ipd(15), pterm2(15), tipd_pterm2(15));
VitalWireDelay (pterm2_ipd(16), pterm2(16), tipd_pterm2(16));
VitalWireDelay (pterm2_ipd(17), pterm2(17), tipd_pterm2(17));
VitalWireDelay (pterm2_ipd(18), pterm2(18), tipd_pterm2(18));
VitalWireDelay (pterm2_ipd(19), pterm2(19), tipd_pterm2(19));
VitalWireDelay (pterm2_ipd(20), pterm2(20), tipd_pterm2(20));
VitalWireDelay (pterm2_ipd(21), pterm2(21), tipd_pterm2(21));
VitalWireDelay (pterm2_ipd(22), pterm2(22), tipd_pterm2(22));
VitalWireDelay (pterm2_ipd(23), pterm2(23), tipd_pterm2(23));
VitalWireDelay (pterm2_ipd(24), pterm2(24), tipd_pterm2(24));
VitalWireDelay (pterm2_ipd(25), pterm2(25), tipd_pterm2(25));
VitalWireDelay (pterm2_ipd(26), pterm2(26), tipd_pterm2(26));
VitalWireDelay (pterm2_ipd(27), pterm2(27), tipd_pterm2(27));
VitalWireDelay (pterm2_ipd(28), pterm2(28), tipd_pterm2(28));
VitalWireDelay (pterm2_ipd(29), pterm2(29), tipd_pterm2(29));
VitalWireDelay (pterm2_ipd(30), pterm2(30), tipd_pterm2(30));
VitalWireDelay (pterm2_ipd(31), pterm2(31), tipd_pterm2(31));
VitalWireDelay (pterm2_ipd(32), pterm2(32), tipd_pterm2(32));
VitalWireDelay (pterm2_ipd(33), pterm2(33), tipd_pterm2(33));
VitalWireDelay (pterm2_ipd(34), pterm2(34), tipd_pterm2(34));
VitalWireDelay (pterm2_ipd(35), pterm2(35), tipd_pterm2(35));
VitalWireDelay (pterm2_ipd(36), pterm2(36), tipd_pterm2(36));
VitalWireDelay (pterm2_ipd(37), pterm2(37), tipd_pterm2(37));
VitalWireDelay (pterm2_ipd(38), pterm2(38), tipd_pterm2(38));
VitalWireDelay (pterm2_ipd(39), pterm2(39), tipd_pterm2(39));
VitalWireDelay (pterm2_ipd(40), pterm2(40), tipd_pterm2(40));
VitalWireDelay (pterm2_ipd(41), pterm2(41), tipd_pterm2(41));
VitalWireDelay (pterm2_ipd(42), pterm2(42), tipd_pterm2(42));
VitalWireDelay (pterm2_ipd(43), pterm2(43), tipd_pterm2(43));
VitalWireDelay (pterm2_ipd(44), pterm2(44), tipd_pterm2(44));
VitalWireDelay (pterm2_ipd(45), pterm2(45), tipd_pterm2(45));
VitalWireDelay (pterm2_ipd(46), pterm2(46), tipd_pterm2(46));
VitalWireDelay (pterm2_ipd(47), pterm2(47), tipd_pterm2(47));
VitalWireDelay (pterm2_ipd(48), pterm2(48), tipd_pterm2(48));
VitalWireDelay (pterm2_ipd(49), pterm2(49), tipd_pterm2(49));
VitalWireDelay (pterm2_ipd(50), pterm2(50), tipd_pterm2(50));
VitalWireDelay (pterm2_ipd(51), pterm2(51), tipd_pterm2(51));
VitalWireDelay (pterm3_ipd(0), pterm3(0), tipd_pterm3(0));
VitalWireDelay (pterm3_ipd(1), pterm3(1), tipd_pterm3(1));
VitalWireDelay (pterm3_ipd(2), pterm3(2), tipd_pterm3(2));
VitalWireDelay (pterm3_ipd(3), pterm3(3), tipd_pterm3(3));
VitalWireDelay (pterm3_ipd(4), pterm3(4), tipd_pterm3(4));
VitalWireDelay (pterm3_ipd(5), pterm3(5), tipd_pterm3(5));
VitalWireDelay (pterm3_ipd(6), pterm3(6), tipd_pterm3(6));
VitalWireDelay (pterm3_ipd(7), pterm3(7), tipd_pterm3(7));
VitalWireDelay (pterm3_ipd(8), pterm3(8), tipd_pterm3(8));
VitalWireDelay (pterm3_ipd(9), pterm3(9), tipd_pterm3(9));
VitalWireDelay (pterm3_ipd(10), pterm3(10), tipd_pterm3(10));
VitalWireDelay (pterm3_ipd(11), pterm3(11), tipd_pterm3(11));
VitalWireDelay (pterm3_ipd(12), pterm3(12), tipd_pterm3(12));
VitalWireDelay (pterm3_ipd(13), pterm3(13), tipd_pterm3(13));
VitalWireDelay (pterm3_ipd(14), pterm3(14), tipd_pterm3(14));
VitalWireDelay (pterm3_ipd(15), pterm3(15), tipd_pterm3(15));
VitalWireDelay (pterm3_ipd(16), pterm3(16), tipd_pterm3(16));
VitalWireDelay (pterm3_ipd(17), pterm3(17), tipd_pterm3(17));
VitalWireDelay (pterm3_ipd(18), pterm3(18), tipd_pterm3(18));
VitalWireDelay (pterm3_ipd(19), pterm3(19), tipd_pterm3(19));
VitalWireDelay (pterm3_ipd(20), pterm3(20), tipd_pterm3(20));
VitalWireDelay (pterm3_ipd(21), pterm3(21), tipd_pterm3(21));
VitalWireDelay (pterm3_ipd(22), pterm3(22), tipd_pterm3(22));
VitalWireDelay (pterm3_ipd(23), pterm3(23), tipd_pterm3(23));
VitalWireDelay (pterm3_ipd(24), pterm3(24), tipd_pterm3(24));
VitalWireDelay (pterm3_ipd(25), pterm3(25), tipd_pterm3(25));
VitalWireDelay (pterm3_ipd(26), pterm3(26), tipd_pterm3(26));
VitalWireDelay (pterm3_ipd(27), pterm3(27), tipd_pterm3(27));
VitalWireDelay (pterm3_ipd(28), pterm3(28), tipd_pterm3(28));
VitalWireDelay (pterm3_ipd(29), pterm3(29), tipd_pterm3(29));
VitalWireDelay (pterm3_ipd(30), pterm3(30), tipd_pterm3(30));
VitalWireDelay (pterm3_ipd(31), pterm3(31), tipd_pterm3(31));
VitalWireDelay (pterm3_ipd(32), pterm3(32), tipd_pterm3(32));
VitalWireDelay (pterm3_ipd(33), pterm3(33), tipd_pterm3(33));
VitalWireDelay (pterm3_ipd(34), pterm3(34), tipd_pterm3(34));
VitalWireDelay (pterm3_ipd(35), pterm3(35), tipd_pterm3(35));
VitalWireDelay (pterm3_ipd(36), pterm3(36), tipd_pterm3(36));
VitalWireDelay (pterm3_ipd(37), pterm3(37), tipd_pterm3(37));
VitalWireDelay (pterm3_ipd(38), pterm3(38), tipd_pterm3(38));
VitalWireDelay (pterm3_ipd(39), pterm3(39), tipd_pterm3(39));
VitalWireDelay (pterm3_ipd(40), pterm3(40), tipd_pterm3(40));
VitalWireDelay (pterm3_ipd(41), pterm3(41), tipd_pterm3(41));
VitalWireDelay (pterm3_ipd(42), pterm3(42), tipd_pterm3(42));
VitalWireDelay (pterm3_ipd(43), pterm3(43), tipd_pterm3(43));
VitalWireDelay (pterm3_ipd(44), pterm3(44), tipd_pterm3(44));
VitalWireDelay (pterm3_ipd(45), pterm3(45), tipd_pterm3(45));
VitalWireDelay (pterm3_ipd(46), pterm3(46), tipd_pterm3(46));
VitalWireDelay (pterm3_ipd(47), pterm3(47), tipd_pterm3(47));
VitalWireDelay (pterm3_ipd(48), pterm3(48), tipd_pterm3(48));
VitalWireDelay (pterm3_ipd(49), pterm3(49), tipd_pterm3(49));
VitalWireDelay (pterm3_ipd(50), pterm3(50), tipd_pterm3(50));
VitalWireDelay (pterm3_ipd(51), pterm3(51), tipd_pterm3(51));
VitalWireDelay (pterm4_ipd(0), pterm4(0), tipd_pterm4(0));
VitalWireDelay (pterm4_ipd(1), pterm4(1), tipd_pterm4(1));
VitalWireDelay (pterm4_ipd(2), pterm4(2), tipd_pterm4(2));
VitalWireDelay (pterm4_ipd(3), pterm4(3), tipd_pterm4(3));
VitalWireDelay (pterm4_ipd(4), pterm4(4), tipd_pterm4(4));
VitalWireDelay (pterm4_ipd(5), pterm4(5), tipd_pterm4(5));
VitalWireDelay (pterm4_ipd(6), pterm4(6), tipd_pterm4(6));
VitalWireDelay (pterm4_ipd(7), pterm4(7), tipd_pterm4(7));
VitalWireDelay (pterm4_ipd(8), pterm4(8), tipd_pterm4(8));
VitalWireDelay (pterm4_ipd(9), pterm4(9), tipd_pterm4(9));
VitalWireDelay (pterm4_ipd(10), pterm4(10), tipd_pterm4(10));
VitalWireDelay (pterm4_ipd(11), pterm4(11), tipd_pterm4(11));
VitalWireDelay (pterm4_ipd(12), pterm4(12), tipd_pterm4(12));
VitalWireDelay (pterm4_ipd(13), pterm4(13), tipd_pterm4(13));
VitalWireDelay (pterm4_ipd(14), pterm4(14), tipd_pterm4(14));
VitalWireDelay (pterm4_ipd(15), pterm4(15), tipd_pterm4(15));
VitalWireDelay (pterm4_ipd(16), pterm4(16), tipd_pterm4(16));
VitalWireDelay (pterm4_ipd(17), pterm4(17), tipd_pterm4(17));
VitalWireDelay (pterm4_ipd(18), pterm4(18), tipd_pterm4(18));
VitalWireDelay (pterm4_ipd(19), pterm4(19), tipd_pterm4(19));
VitalWireDelay (pterm4_ipd(20), pterm4(20), tipd_pterm4(20));
VitalWireDelay (pterm4_ipd(21), pterm4(21), tipd_pterm4(21));
VitalWireDelay (pterm4_ipd(22), pterm4(22), tipd_pterm4(22));
VitalWireDelay (pterm4_ipd(23), pterm4(23), tipd_pterm4(23));
VitalWireDelay (pterm4_ipd(24), pterm4(24), tipd_pterm4(24));
VitalWireDelay (pterm4_ipd(25), pterm4(25), tipd_pterm4(25));
VitalWireDelay (pterm4_ipd(26), pterm4(26), tipd_pterm4(26));
VitalWireDelay (pterm4_ipd(27), pterm4(27), tipd_pterm4(27));
VitalWireDelay (pterm4_ipd(28), pterm4(28), tipd_pterm4(28));
VitalWireDelay (pterm4_ipd(29), pterm4(29), tipd_pterm4(29));
VitalWireDelay (pterm4_ipd(30), pterm4(30), tipd_pterm4(30));
VitalWireDelay (pterm4_ipd(31), pterm4(31), tipd_pterm4(31));
VitalWireDelay (pterm4_ipd(32), pterm4(32), tipd_pterm4(32));
VitalWireDelay (pterm4_ipd(33), pterm4(33), tipd_pterm4(33));
VitalWireDelay (pterm4_ipd(34), pterm4(34), tipd_pterm4(34));
VitalWireDelay (pterm4_ipd(35), pterm4(35), tipd_pterm4(35));
VitalWireDelay (pterm4_ipd(36), pterm4(36), tipd_pterm4(36));
VitalWireDelay (pterm4_ipd(37), pterm4(37), tipd_pterm4(37));
VitalWireDelay (pterm4_ipd(38), pterm4(38), tipd_pterm4(38));
VitalWireDelay (pterm4_ipd(39), pterm4(39), tipd_pterm4(39));
VitalWireDelay (pterm4_ipd(40), pterm4(40), tipd_pterm4(40));
VitalWireDelay (pterm4_ipd(41), pterm4(41), tipd_pterm4(41));
VitalWireDelay (pterm4_ipd(42), pterm4(42), tipd_pterm4(42));
VitalWireDelay (pterm4_ipd(43), pterm4(43), tipd_pterm4(43));
VitalWireDelay (pterm4_ipd(44), pterm4(44), tipd_pterm4(44));
VitalWireDelay (pterm4_ipd(45), pterm4(45), tipd_pterm4(45));
VitalWireDelay (pterm4_ipd(46), pterm4(46), tipd_pterm4(46));
VitalWireDelay (pterm4_ipd(47), pterm4(47), tipd_pterm4(47));
VitalWireDelay (pterm4_ipd(48), pterm4(48), tipd_pterm4(48));
VitalWireDelay (pterm4_ipd(49), pterm4(49), tipd_pterm4(49));
VitalWireDelay (pterm4_ipd(50), pterm4(50), tipd_pterm4(50));
VitalWireDelay (pterm4_ipd(51), pterm4(51), tipd_pterm4(51));
VitalWireDelay (pterm5_ipd(0), pterm5(0), tipd_pterm5(0));
VitalWireDelay (pterm5_ipd(1), pterm5(1), tipd_pterm5(1));
VitalWireDelay (pterm5_ipd(2), pterm5(2), tipd_pterm5(2));
VitalWireDelay (pterm5_ipd(3), pterm5(3), tipd_pterm5(3));
VitalWireDelay (pterm5_ipd(4), pterm5(4), tipd_pterm5(4));
VitalWireDelay (pterm5_ipd(5), pterm5(5), tipd_pterm5(5));
VitalWireDelay (pterm5_ipd(6), pterm5(6), tipd_pterm5(6));
VitalWireDelay (pterm5_ipd(7), pterm5(7), tipd_pterm5(7));
VitalWireDelay (pterm5_ipd(8), pterm5(8), tipd_pterm5(8));
VitalWireDelay (pterm5_ipd(9), pterm5(9), tipd_pterm5(9));
VitalWireDelay (pterm5_ipd(10), pterm5(10), tipd_pterm5(10));
VitalWireDelay (pterm5_ipd(11), pterm5(11), tipd_pterm5(11));
VitalWireDelay (pterm5_ipd(12), pterm5(12), tipd_pterm5(12));
VitalWireDelay (pterm5_ipd(13), pterm5(13), tipd_pterm5(13));
VitalWireDelay (pterm5_ipd(14), pterm5(14), tipd_pterm5(14));
VitalWireDelay (pterm5_ipd(15), pterm5(15), tipd_pterm5(15));
VitalWireDelay (pterm5_ipd(16), pterm5(16), tipd_pterm5(16));
VitalWireDelay (pterm5_ipd(17), pterm5(17), tipd_pterm5(17));
VitalWireDelay (pterm5_ipd(18), pterm5(18), tipd_pterm5(18));
VitalWireDelay (pterm5_ipd(19), pterm5(19), tipd_pterm5(19));
VitalWireDelay (pterm5_ipd(20), pterm5(20), tipd_pterm5(20));
VitalWireDelay (pterm5_ipd(21), pterm5(21), tipd_pterm5(21));
VitalWireDelay (pterm5_ipd(22), pterm5(22), tipd_pterm5(22));
VitalWireDelay (pterm5_ipd(23), pterm5(23), tipd_pterm5(23));
VitalWireDelay (pterm5_ipd(24), pterm5(24), tipd_pterm5(24));
VitalWireDelay (pterm5_ipd(25), pterm5(25), tipd_pterm5(25));
VitalWireDelay (pterm5_ipd(26), pterm5(26), tipd_pterm5(26));
VitalWireDelay (pterm5_ipd(27), pterm5(27), tipd_pterm5(27));
VitalWireDelay (pterm5_ipd(28), pterm5(28), tipd_pterm5(28));
VitalWireDelay (pterm5_ipd(29), pterm5(29), tipd_pterm5(29));
VitalWireDelay (pterm5_ipd(30), pterm5(30), tipd_pterm5(30));
VitalWireDelay (pterm5_ipd(31), pterm5(31), tipd_pterm5(31));
VitalWireDelay (pterm5_ipd(32), pterm5(32), tipd_pterm5(32));
VitalWireDelay (pterm5_ipd(33), pterm5(33), tipd_pterm5(33));
VitalWireDelay (pterm5_ipd(34), pterm5(34), tipd_pterm5(34));
VitalWireDelay (pterm5_ipd(35), pterm5(35), tipd_pterm5(35));
VitalWireDelay (pterm5_ipd(36), pterm5(36), tipd_pterm5(36));
VitalWireDelay (pterm5_ipd(37), pterm5(37), tipd_pterm5(37));
VitalWireDelay (pterm5_ipd(38), pterm5(38), tipd_pterm5(38));
VitalWireDelay (pterm5_ipd(39), pterm5(39), tipd_pterm5(39));
VitalWireDelay (pterm5_ipd(40), pterm5(40), tipd_pterm5(40));
VitalWireDelay (pterm5_ipd(41), pterm5(41), tipd_pterm5(41));
VitalWireDelay (pterm5_ipd(42), pterm5(42), tipd_pterm5(42));
VitalWireDelay (pterm5_ipd(43), pterm5(43), tipd_pterm5(43));
VitalWireDelay (pterm5_ipd(44), pterm5(44), tipd_pterm5(44));
VitalWireDelay (pterm5_ipd(45), pterm5(45), tipd_pterm5(45));
VitalWireDelay (pterm5_ipd(46), pterm5(46), tipd_pterm5(46));
VitalWireDelay (pterm5_ipd(47), pterm5(47), tipd_pterm5(47));
VitalWireDelay (pterm5_ipd(48), pterm5(48), tipd_pterm5(48));
VitalWireDelay (pterm5_ipd(49), pterm5(49), tipd_pterm5(49));
VitalWireDelay (pterm5_ipd(50), pterm5(50), tipd_pterm5(50));
VitalWireDelay (pterm5_ipd(51), pterm5(51), tipd_pterm5(51));
VitalWireDelay (pxor_ipd(0), pxor(0), tipd_pxor(0));
VitalWireDelay (pxor_ipd(1), pxor(1), tipd_pxor(1));
VitalWireDelay (pxor_ipd(2), pxor(2), tipd_pxor(2));
VitalWireDelay (pxor_ipd(3), pxor(3), tipd_pxor(3));
VitalWireDelay (pxor_ipd(4), pxor(4), tipd_pxor(4));
VitalWireDelay (pxor_ipd(5), pxor(5), tipd_pxor(5));
VitalWireDelay (pxor_ipd(6), pxor(6), tipd_pxor(6));
VitalWireDelay (pxor_ipd(7), pxor(7), tipd_pxor(7));
VitalWireDelay (pxor_ipd(8), pxor(8), tipd_pxor(8));
VitalWireDelay (pxor_ipd(9), pxor(9), tipd_pxor(9));
VitalWireDelay (pxor_ipd(10), pxor(10), tipd_pxor(10));
VitalWireDelay (pxor_ipd(11), pxor(11), tipd_pxor(11));
VitalWireDelay (pxor_ipd(12), pxor(12), tipd_pxor(12));
VitalWireDelay (pxor_ipd(13), pxor(13), tipd_pxor(13));
VitalWireDelay (pxor_ipd(14), pxor(14), tipd_pxor(14));
VitalWireDelay (pxor_ipd(15), pxor(15), tipd_pxor(15));
VitalWireDelay (pxor_ipd(16), pxor(16), tipd_pxor(16));
VitalWireDelay (pxor_ipd(17), pxor(17), tipd_pxor(17));
VitalWireDelay (pxor_ipd(18), pxor(18), tipd_pxor(18));
VitalWireDelay (pxor_ipd(19), pxor(19), tipd_pxor(19));
VitalWireDelay (pxor_ipd(20), pxor(20), tipd_pxor(20));
VitalWireDelay (pxor_ipd(21), pxor(21), tipd_pxor(21));
VitalWireDelay (pxor_ipd(22), pxor(22), tipd_pxor(22));
VitalWireDelay (pxor_ipd(23), pxor(23), tipd_pxor(23));
VitalWireDelay (pxor_ipd(24), pxor(24), tipd_pxor(24));
VitalWireDelay (pxor_ipd(25), pxor(25), tipd_pxor(25));
VitalWireDelay (pxor_ipd(26), pxor(26), tipd_pxor(26));
VitalWireDelay (pxor_ipd(27), pxor(27), tipd_pxor(27));
VitalWireDelay (pxor_ipd(28), pxor(28), tipd_pxor(28));
VitalWireDelay (pxor_ipd(29), pxor(29), tipd_pxor(29));
VitalWireDelay (pxor_ipd(30), pxor(30), tipd_pxor(30));
VitalWireDelay (pxor_ipd(31), pxor(31), tipd_pxor(31));
VitalWireDelay (pxor_ipd(32), pxor(32), tipd_pxor(32));
VitalWireDelay (pxor_ipd(33), pxor(33), tipd_pxor(33));
VitalWireDelay (pxor_ipd(34), pxor(34), tipd_pxor(34));
VitalWireDelay (pxor_ipd(35), pxor(35), tipd_pxor(35));
VitalWireDelay (pxor_ipd(36), pxor(36), tipd_pxor(36));
VitalWireDelay (pxor_ipd(37), pxor(37), tipd_pxor(37));
VitalWireDelay (pxor_ipd(38), pxor(38), tipd_pxor(38));
VitalWireDelay (pxor_ipd(39), pxor(39), tipd_pxor(39));
VitalWireDelay (pxor_ipd(40), pxor(40), tipd_pxor(40));
VitalWireDelay (pxor_ipd(41), pxor(41), tipd_pxor(41));
VitalWireDelay (pxor_ipd(42), pxor(42), tipd_pxor(42));
VitalWireDelay (pxor_ipd(43), pxor(43), tipd_pxor(43));
VitalWireDelay (pxor_ipd(44), pxor(44), tipd_pxor(44));
VitalWireDelay (pxor_ipd(45), pxor(45), tipd_pxor(45));
VitalWireDelay (pxor_ipd(46), pxor(46), tipd_pxor(46));
VitalWireDelay (pxor_ipd(47), pxor(47), tipd_pxor(47));
VitalWireDelay (pxor_ipd(48), pxor(48), tipd_pxor(48));
VitalWireDelay (pxor_ipd(49), pxor(49), tipd_pxor(49));
VitalWireDelay (pxor_ipd(50), pxor(50), tipd_pxor(50));
VitalWireDelay (pxor_ipd(51), pxor(51), tipd_pxor(51));
VitalWireDelay (pexpin_ipd, pexpin, tipd_pexpin);
VitalWireDelay (fpin_ipd, fpin, tipd_fpin);
end block;
VITALtiming : process(pterm0_ipd, pterm1_ipd, pterm2_ipd, pterm3_ipd, pterm4_ipd, pterm5_ipd, pxor_ipd, pexpin_ipd, fbkin, fpin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable pexpout_VitalGlitchData : VitalGlitchDataType;
variable tmp_comb, tmp_pexpout : std_logic;
begin
if (pexp_mode = "off") then
if (operation_mode = "normal") then
if (register_mode = "tff") then
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor fbkin;
else
tmp_comb := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
end if;
elsif (operation_mode = "invert") then
if (register_mode = "tff") then
tmp_comb := (((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd)) xor (not(fbkin));
else
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor '1';
end if;
elsif (operation_mode = "xor") then
tmp_comb := ((product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd) xor product(pxor_ipd);
elsif (operation_mode = "vcc") then
if (register_mode = "tff") then
tmp_comb := '1' xor fbkin;
else
tmp_comb := fpin_ipd;
end if;
else
tmp_comb := 'Z';
tmp_pexpout := 'Z';
end if;
elsif (pexp_mode = "on") then
if (operation_mode = "normal") then
if (register_mode = "tff") then
tmp_comb := (product (pterm5_ipd)) xor fbkin;
else
tmp_comb := product (pterm5_ipd);
end if;
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
elsif (operation_mode = "invert") then
if (register_mode = "tff") then
tmp_comb := (product(pterm5_ipd)) xor (not(fbkin));
else
tmp_comb := (product(pterm5_ipd)) xor '1';
end if;
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
elsif (operation_mode = "xor") then
tmp_pexpout := (product(pterm0_ipd) or product(pterm1_ipd) or product(pterm2_ipd) or product(pterm3_ipd) or product(pterm4_ipd)) or pexpin_ipd;
tmp_comb := (product(pterm5_ipd)) xor (product(pxor_ipd));
elsif (operation_mode = "vcc") then
if (register_mode = "tff") then
tmp_comb := '1' xor fbkin;
else
tmp_comb := fpin_ipd;
end if;
tmp_pexpout := (product(pterm0) or product(pterm1) or product(pterm2) or product(pterm3) or product(pterm4)) or pexpin_ipd;
else
tmp_comb := 'Z';
tmp_pexpout := 'Z';
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_comb,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_combout(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_combout(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_combout(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_combout(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_combout(0), TRUE),
6 => (pterm5_ipd'last_event, tpd_pterm5_combout(0), TRUE),
7 => (pxor_ipd'last_event, tpd_pxor_combout(0), TRUE),
8 => (pexpin_ipd'last_event, tpd_pexpin_combout, TRUE),
9 => (fbkin'last_event, tpd_fbkin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => pexpout,
OutSignalName => "PEXPOUT",
OutTemp => tmp_pexpout,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_pexpout(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_pexpout(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_pexpout(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_pexpout(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_pexpout(0), TRUE),
6 => (pexpin_ipd'last_event, tpd_pexpin_pexpout, TRUE),
7 => (fbkin'last_event, tpd_fbkin_pexpout, TRUE)),
GlitchData => pexpout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_comb,
Paths => (1 => (pterm0_ipd'last_event, tpd_pterm0_regin(0), TRUE),
2 => (pterm1_ipd'last_event, tpd_pterm1_regin(0), TRUE),
3 => (pterm2_ipd'last_event, tpd_pterm2_regin(0), TRUE),
4 => (pterm3_ipd'last_event, tpd_pterm3_regin(0), TRUE),
5 => (pterm4_ipd'last_event, tpd_pterm4_regin(0), TRUE),
6 => (pterm5_ipd'last_event, tpd_pterm5_regin(0), TRUE),
7 => (fpin_ipd'last_event, tpd_fpin_regin, TRUE),
8 => (pxor_ipd'last_event, tpd_pxor_regin(0), TRUE),
9 => (pexpin_ipd'last_event, tpd_pexpin_regin, TRUE),
10 => (fbkin'last_event, tpd_fbkin_regin, TRUE)),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_mcell;
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_mcell_register is
generic ( operation_mode : string := "normal";
power_up : string := "low";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pclk_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pclk_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tipd_pclk : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pena : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_paclr : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_papre : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01);
port ( datain : in std_logic;
clk : in std_logic;
aclr : in std_logic := '0';
pclk : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pena : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
paclr : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
papre : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
regout : out std_logic;
fbkout : out std_logic);
attribute VITAL_LEVEL0 of max_mcell_register : entity is TRUE;
end max_mcell_register;
architecture vital_mcell_reg of max_mcell_register is
attribute VITAL_LEVEL0 of vital_mcell_reg : architecture is TRUE;
signal pclk_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal pena_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal paclr_ipd :std_logic_vector(51 downto 0) := (OTHERS => 'U');
signal papre_ipd :std_logic_vector(51 downto 0) := (OTHERS => '0');
signal clk_ipd :std_ulogic := 'U';
signal aclr_ipd :std_ulogic := 'U';
signal ena_ipd :std_ulogic := '1';
signal ptermclk :std_ulogic := '0';
signal penable :std_ulogic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (pclk_ipd(0), pclk(0), tipd_pclk(0));
VitalWireDelay (pclk_ipd(1), pclk(1), tipd_pclk(1));
VitalWireDelay (pclk_ipd(2), pclk(2), tipd_pclk(2));
VitalWireDelay (pclk_ipd(3), pclk(3), tipd_pclk(3));
VitalWireDelay (pclk_ipd(4), pclk(4), tipd_pclk(4));
VitalWireDelay (pclk_ipd(5), pclk(5), tipd_pclk(5));
VitalWireDelay (pclk_ipd(6), pclk(6), tipd_pclk(6));
VitalWireDelay (pclk_ipd(7), pclk(7), tipd_pclk(7));
VitalWireDelay (pclk_ipd(8), pclk(8), tipd_pclk(8));
VitalWireDelay (pclk_ipd(9), pclk(9), tipd_pclk(9));
VitalWireDelay (pclk_ipd(10), pclk(10), tipd_pclk(10));
VitalWireDelay (pclk_ipd(11), pclk(11), tipd_pclk(11));
VitalWireDelay (pclk_ipd(12), pclk(12), tipd_pclk(12));
VitalWireDelay (pclk_ipd(13), pclk(13), tipd_pclk(13));
VitalWireDelay (pclk_ipd(14), pclk(14), tipd_pclk(14));
VitalWireDelay (pclk_ipd(15), pclk(15), tipd_pclk(15));
VitalWireDelay (pclk_ipd(16), pclk(16), tipd_pclk(16));
VitalWireDelay (pclk_ipd(17), pclk(17), tipd_pclk(17));
VitalWireDelay (pclk_ipd(18), pclk(18), tipd_pclk(18));
VitalWireDelay (pclk_ipd(19), pclk(19), tipd_pclk(19));
VitalWireDelay (pclk_ipd(20), pclk(20), tipd_pclk(20));
VitalWireDelay (pclk_ipd(21), pclk(21), tipd_pclk(21));
VitalWireDelay (pclk_ipd(22), pclk(22), tipd_pclk(22));
VitalWireDelay (pclk_ipd(23), pclk(23), tipd_pclk(23));
VitalWireDelay (pclk_ipd(24), pclk(24), tipd_pclk(24));
VitalWireDelay (pclk_ipd(25), pclk(25), tipd_pclk(25));
VitalWireDelay (pclk_ipd(26), pclk(26), tipd_pclk(26));
VitalWireDelay (pclk_ipd(27), pclk(27), tipd_pclk(27));
VitalWireDelay (pclk_ipd(28), pclk(28), tipd_pclk(28));
VitalWireDelay (pclk_ipd(29), pclk(29), tipd_pclk(29));
VitalWireDelay (pclk_ipd(30), pclk(30), tipd_pclk(30));
VitalWireDelay (pclk_ipd(31), pclk(31), tipd_pclk(31));
VitalWireDelay (pclk_ipd(32), pclk(32), tipd_pclk(32));
VitalWireDelay (pclk_ipd(33), pclk(33), tipd_pclk(33));
VitalWireDelay (pclk_ipd(34), pclk(34), tipd_pclk(34));
VitalWireDelay (pclk_ipd(35), pclk(35), tipd_pclk(35));
VitalWireDelay (pclk_ipd(36), pclk(36), tipd_pclk(36));
VitalWireDelay (pclk_ipd(37), pclk(37), tipd_pclk(37));
VitalWireDelay (pclk_ipd(38), pclk(38), tipd_pclk(38));
VitalWireDelay (pclk_ipd(39), pclk(39), tipd_pclk(39));
VitalWireDelay (pclk_ipd(40), pclk(40), tipd_pclk(40));
VitalWireDelay (pclk_ipd(41), pclk(41), tipd_pclk(41));
VitalWireDelay (pclk_ipd(42), pclk(42), tipd_pclk(42));
VitalWireDelay (pclk_ipd(43), pclk(43), tipd_pclk(43));
VitalWireDelay (pclk_ipd(44), pclk(44), tipd_pclk(44));
VitalWireDelay (pclk_ipd(45), pclk(45), tipd_pclk(45));
VitalWireDelay (pclk_ipd(46), pclk(46), tipd_pclk(46));
VitalWireDelay (pclk_ipd(47), pclk(47), tipd_pclk(47));
VitalWireDelay (pclk_ipd(48), pclk(48), tipd_pclk(48));
VitalWireDelay (pclk_ipd(49), pclk(49), tipd_pclk(49));
VitalWireDelay (pclk_ipd(50), pclk(50), tipd_pclk(50));
VitalWireDelay (pclk_ipd(51), pclk(51), tipd_pclk(51));
VitalWireDelay (pena_ipd(0), pena(0), tipd_pena(0));
VitalWireDelay (pena_ipd(1), pena(1), tipd_pena(1));
VitalWireDelay (pena_ipd(2), pena(2), tipd_pena(2));
VitalWireDelay (pena_ipd(3), pena(3), tipd_pena(3));
VitalWireDelay (pena_ipd(4), pena(4), tipd_pena(4));
VitalWireDelay (pena_ipd(5), pena(5), tipd_pena(5));
VitalWireDelay (pena_ipd(6), pena(6), tipd_pena(6));
VitalWireDelay (pena_ipd(7), pena(7), tipd_pena(7));
VitalWireDelay (pena_ipd(8), pena(8), tipd_pena(8));
VitalWireDelay (pena_ipd(9), pena(9), tipd_pena(9));
VitalWireDelay (pena_ipd(10), pena(10), tipd_pena(10));
VitalWireDelay (pena_ipd(11), pena(11), tipd_pena(11));
VitalWireDelay (pena_ipd(12), pena(12), tipd_pena(12));
VitalWireDelay (pena_ipd(13), pena(13), tipd_pena(13));
VitalWireDelay (pena_ipd(14), pena(14), tipd_pena(14));
VitalWireDelay (pena_ipd(15), pena(15), tipd_pena(15));
VitalWireDelay (pena_ipd(16), pena(16), tipd_pena(16));
VitalWireDelay (pena_ipd(17), pena(17), tipd_pena(17));
VitalWireDelay (pena_ipd(18), pena(18), tipd_pena(18));
VitalWireDelay (pena_ipd(19), pena(19), tipd_pena(19));
VitalWireDelay (pena_ipd(20), pena(20), tipd_pena(20));
VitalWireDelay (pena_ipd(21), pena(21), tipd_pena(21));
VitalWireDelay (pena_ipd(22), pena(22), tipd_pena(22));
VitalWireDelay (pena_ipd(23), pena(23), tipd_pena(23));
VitalWireDelay (pena_ipd(24), pena(24), tipd_pena(24));
VitalWireDelay (pena_ipd(25), pena(25), tipd_pena(25));
VitalWireDelay (pena_ipd(26), pena(26), tipd_pena(26));
VitalWireDelay (pena_ipd(27), pena(27), tipd_pena(27));
VitalWireDelay (pena_ipd(28), pena(28), tipd_pena(28));
VitalWireDelay (pena_ipd(29), pena(29), tipd_pena(29));
VitalWireDelay (pena_ipd(30), pena(30), tipd_pena(30));
VitalWireDelay (pena_ipd(31), pena(31), tipd_pena(31));
VitalWireDelay (pena_ipd(32), pena(32), tipd_pena(32));
VitalWireDelay (pena_ipd(33), pena(33), tipd_pena(33));
VitalWireDelay (pena_ipd(34), pena(34), tipd_pena(34));
VitalWireDelay (pena_ipd(35), pena(35), tipd_pena(35));
VitalWireDelay (pena_ipd(36), pena(36), tipd_pena(36));
VitalWireDelay (pena_ipd(37), pena(37), tipd_pena(37));
VitalWireDelay (pena_ipd(38), pena(38), tipd_pena(38));
VitalWireDelay (pena_ipd(39), pena(39), tipd_pena(39));
VitalWireDelay (pena_ipd(40), pena(40), tipd_pena(40));
VitalWireDelay (pena_ipd(41), pena(41), tipd_pena(41));
VitalWireDelay (pena_ipd(42), pena(42), tipd_pena(42));
VitalWireDelay (pena_ipd(43), pena(43), tipd_pena(43));
VitalWireDelay (pena_ipd(44), pena(44), tipd_pena(44));
VitalWireDelay (pena_ipd(45), pena(45), tipd_pena(45));
VitalWireDelay (pena_ipd(46), pena(46), tipd_pena(46));
VitalWireDelay (pena_ipd(47), pena(47), tipd_pena(47));
VitalWireDelay (pena_ipd(48), pena(48), tipd_pena(48));
VitalWireDelay (pena_ipd(49), pena(49), tipd_pena(49));
VitalWireDelay (pena_ipd(50), pena(50), tipd_pena(50));
VitalWireDelay (pena_ipd(51), pena(51), tipd_pena(51));
VitalWireDelay (paclr_ipd(0), paclr(0), tipd_paclr(0));
VitalWireDelay (paclr_ipd(1), paclr(1), tipd_paclr(1));
VitalWireDelay (paclr_ipd(2), paclr(2), tipd_paclr(2));
VitalWireDelay (paclr_ipd(3), paclr(3), tipd_paclr(3));
VitalWireDelay (paclr_ipd(4), paclr(4), tipd_paclr(4));
VitalWireDelay (paclr_ipd(5), paclr(5), tipd_paclr(5));
VitalWireDelay (paclr_ipd(6), paclr(6), tipd_paclr(6));
VitalWireDelay (paclr_ipd(7), paclr(7), tipd_paclr(7));
VitalWireDelay (paclr_ipd(8), paclr(8), tipd_paclr(8));
VitalWireDelay (paclr_ipd(9), paclr(9), tipd_paclr(9));
VitalWireDelay (paclr_ipd(10), paclr(10), tipd_paclr(10));
VitalWireDelay (paclr_ipd(11), paclr(11), tipd_paclr(11));
VitalWireDelay (paclr_ipd(12), paclr(12), tipd_paclr(12));
VitalWireDelay (paclr_ipd(13), paclr(13), tipd_paclr(13));
VitalWireDelay (paclr_ipd(14), paclr(14), tipd_paclr(14));
VitalWireDelay (paclr_ipd(15), paclr(15), tipd_paclr(15));
VitalWireDelay (paclr_ipd(16), paclr(16), tipd_paclr(16));
VitalWireDelay (paclr_ipd(17), paclr(17), tipd_paclr(17));
VitalWireDelay (paclr_ipd(18), paclr(18), tipd_paclr(18));
VitalWireDelay (paclr_ipd(19), paclr(19), tipd_paclr(19));
VitalWireDelay (paclr_ipd(20), paclr(20), tipd_paclr(20));
VitalWireDelay (paclr_ipd(21), paclr(21), tipd_paclr(21));
VitalWireDelay (paclr_ipd(22), paclr(22), tipd_paclr(22));
VitalWireDelay (paclr_ipd(23), paclr(23), tipd_paclr(23));
VitalWireDelay (paclr_ipd(24), paclr(24), tipd_paclr(24));
VitalWireDelay (paclr_ipd(25), paclr(25), tipd_paclr(25));
VitalWireDelay (paclr_ipd(26), paclr(26), tipd_paclr(26));
VitalWireDelay (paclr_ipd(27), paclr(27), tipd_paclr(27));
VitalWireDelay (paclr_ipd(28), paclr(28), tipd_paclr(28));
VitalWireDelay (paclr_ipd(29), paclr(29), tipd_paclr(29));
VitalWireDelay (paclr_ipd(30), paclr(30), tipd_paclr(30));
VitalWireDelay (paclr_ipd(31), paclr(31), tipd_paclr(31));
VitalWireDelay (paclr_ipd(32), paclr(32), tipd_paclr(32));
VitalWireDelay (paclr_ipd(33), paclr(33), tipd_paclr(33));
VitalWireDelay (paclr_ipd(34), paclr(34), tipd_paclr(34));
VitalWireDelay (paclr_ipd(35), paclr(35), tipd_paclr(35));
VitalWireDelay (paclr_ipd(36), paclr(36), tipd_paclr(36));
VitalWireDelay (paclr_ipd(37), paclr(37), tipd_paclr(37));
VitalWireDelay (paclr_ipd(38), paclr(38), tipd_paclr(38));
VitalWireDelay (paclr_ipd(39), paclr(39), tipd_paclr(39));
VitalWireDelay (paclr_ipd(40), paclr(40), tipd_paclr(40));
VitalWireDelay (paclr_ipd(41), paclr(41), tipd_paclr(41));
VitalWireDelay (paclr_ipd(42), paclr(42), tipd_paclr(42));
VitalWireDelay (paclr_ipd(43), paclr(43), tipd_paclr(43));
VitalWireDelay (paclr_ipd(44), paclr(44), tipd_paclr(44));
VitalWireDelay (paclr_ipd(45), paclr(45), tipd_paclr(45));
VitalWireDelay (paclr_ipd(46), paclr(46), tipd_paclr(46));
VitalWireDelay (paclr_ipd(47), paclr(47), tipd_paclr(47));
VitalWireDelay (paclr_ipd(48), paclr(48), tipd_paclr(48));
VitalWireDelay (paclr_ipd(49), paclr(49), tipd_paclr(49));
VitalWireDelay (paclr_ipd(50), paclr(50), tipd_paclr(50));
VitalWireDelay (paclr_ipd(51), paclr(51), tipd_paclr(51));
VitalWireDelay (papre_ipd(0), papre(0), tipd_papre(0));
VitalWireDelay (papre_ipd(1), papre(1), tipd_papre(1));
VitalWireDelay (papre_ipd(2), papre(2), tipd_papre(2));
VitalWireDelay (papre_ipd(3), papre(3), tipd_papre(3));
VitalWireDelay (papre_ipd(4), papre(4), tipd_papre(4));
VitalWireDelay (papre_ipd(5), papre(5), tipd_papre(5));
VitalWireDelay (papre_ipd(6), papre(6), tipd_papre(6));
VitalWireDelay (papre_ipd(7), papre(7), tipd_papre(7));
VitalWireDelay (papre_ipd(8), papre(8), tipd_papre(8));
VitalWireDelay (papre_ipd(9), papre(9), tipd_papre(9));
VitalWireDelay (papre_ipd(10), papre(10), tipd_papre(10));
VitalWireDelay (papre_ipd(11), papre(11), tipd_papre(11));
VitalWireDelay (papre_ipd(12), papre(12), tipd_papre(12));
VitalWireDelay (papre_ipd(13), papre(13), tipd_papre(13));
VitalWireDelay (papre_ipd(14), papre(14), tipd_papre(14));
VitalWireDelay (papre_ipd(15), papre(15), tipd_papre(15));
VitalWireDelay (papre_ipd(16), papre(16), tipd_papre(16));
VitalWireDelay (papre_ipd(17), papre(17), tipd_papre(17));
VitalWireDelay (papre_ipd(18), papre(18), tipd_papre(18));
VitalWireDelay (papre_ipd(19), papre(19), tipd_papre(19));
VitalWireDelay (papre_ipd(20), papre(20), tipd_papre(20));
VitalWireDelay (papre_ipd(21), papre(21), tipd_papre(21));
VitalWireDelay (papre_ipd(22), papre(22), tipd_papre(22));
VitalWireDelay (papre_ipd(23), papre(23), tipd_papre(23));
VitalWireDelay (papre_ipd(24), papre(24), tipd_papre(24));
VitalWireDelay (papre_ipd(25), papre(25), tipd_papre(25));
VitalWireDelay (papre_ipd(26), papre(26), tipd_papre(26));
VitalWireDelay (papre_ipd(27), papre(27), tipd_papre(27));
VitalWireDelay (papre_ipd(28), papre(28), tipd_papre(28));
VitalWireDelay (papre_ipd(29), papre(29), tipd_papre(29));
VitalWireDelay (papre_ipd(30), papre(30), tipd_papre(30));
VitalWireDelay (papre_ipd(31), papre(31), tipd_papre(31));
VitalWireDelay (papre_ipd(32), papre(32), tipd_papre(32));
VitalWireDelay (papre_ipd(33), papre(33), tipd_papre(33));
VitalWireDelay (papre_ipd(34), papre(34), tipd_papre(34));
VitalWireDelay (papre_ipd(35), papre(35), tipd_papre(35));
VitalWireDelay (papre_ipd(36), papre(36), tipd_papre(36));
VitalWireDelay (papre_ipd(37), papre(37), tipd_papre(37));
VitalWireDelay (papre_ipd(38), papre(38), tipd_papre(38));
VitalWireDelay (papre_ipd(39), papre(39), tipd_papre(39));
VitalWireDelay (papre_ipd(40), papre(40), tipd_papre(40));
VitalWireDelay (papre_ipd(41), papre(41), tipd_papre(41));
VitalWireDelay (papre_ipd(42), papre(42), tipd_papre(42));
VitalWireDelay (papre_ipd(43), papre(43), tipd_papre(43));
VitalWireDelay (papre_ipd(44), papre(44), tipd_papre(44));
VitalWireDelay (papre_ipd(45), papre(45), tipd_papre(45));
VitalWireDelay (papre_ipd(46), papre(46), tipd_papre(46));
VitalWireDelay (papre_ipd(47), papre(47), tipd_papre(47));
VitalWireDelay (papre_ipd(48), papre(48), tipd_papre(48));
VitalWireDelay (papre_ipd(49), papre(49), tipd_papre(49));
VitalWireDelay (papre_ipd(50), papre(50), tipd_papre(50));
VitalWireDelay (papre_ipd(51), papre(51), tipd_papre(51));
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
end block;
VITALtiming : process(datain, ptermclk, pclk_ipd, pena_ipd, paclr_ipd,
papre_ipd, clk_ipd, aclr_ipd, ena_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_penable_clk : std_ulogic := '0';
variable Tviol_clk : std_ulogic := '0';
variable Tviol_datain_ptermclk : std_ulogic := '0';
variable Tviol_ptermclk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_pena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datain_pclk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable fbkout_VitalGlitchData : VitalGlitchDataType;
variable tmp_regout : std_logic;
variable oldclk : std_logic;
variable pterm_aclr : std_logic;
variable pterm_preset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
penable <= product(pena_ipd);
pterm_aclr := product(paclr_ipd);
pterm_preset := product(papre_ipd);
ptermclk <= product(pclk_ipd);
for N in 0 to 51 loop
if (papre_ipd(N) = 'U') then
pterm_preset := '0';
end if;
exit when pterm_preset = '0';
end loop;
for N in 0 to 51 loop
if (paclr_ipd(N) = 'U') then
pterm_aclr := '0';
end if;
exit when pterm_aclr = '0';
end loop;
for N in 0 to 51 loop
if (pclk_ipd(N) = 'U') then
ptermclk <= '0';
end if;
exit when ptermclk = '0';
end loop;
if (now <= 0 ns) then
if (power_up = "low") then
tmp_regout := '0';
elsif (power_up = "high") then
tmp_regout := '1';
end if;
ptermclk <= '0';
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR (NOT penable)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_penable_clk,
TimingData => TimingData_pena_clk,
TestSignal => pena_ipd,
TestSignalName => "PENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_pena_clk_noedge_posedge(0),
SetupLow => tsetup_pena_clk_noedge_posedge(0),
HoldHigh => thold_pena_clk_noedge_posedge(0),
HoldLow => thold_pena_clk_noedge_posedge(0),
CheckEnabled => TO_X01((aclr_ipd) OR (NOT penable)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_datain_ptermclk,
TimingData => TimingData_datain_pclk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => ptermclk,
RefSignalName => "PCLK",
SetupHigh => tsetup_datain_pclk_noedge_posedge(0),
SetupLow => tsetup_datain_pclk_noedge_posedge(0),
HoldHigh => thold_datain_pclk_noedge_posedge(0),
HoldLow => thold_datain_pclk_noedge_posedge(0),
CheckEnabled => TO_X01((aclr_ipd) OR (NOT penable)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := (Tviol_datain_clk or Tviol_datain_ptermclk or Tviol_penable_clk);
if ((aclr_ipd = '1') or (pterm_aclr = '1')) then
tmp_regout := '0';
elsif (pterm_preset = '1') then
tmp_regout := '1';
elsif (violation = 'X') then
tmp_regout := 'X';
elsif (penable = '1') then
if ((clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') or ((ptermclk'event) and (oldclk = '0') and (ptermclk = '1'))) then
tmp_regout := datain;
end if;
end if;
oldclk := ptermclk;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE),
2 => (pclk_ipd'last_event, tpd_pclk_regout_posedge(0), TRUE),
3 => (pena_ipd'last_event, tpd_pena_regout_posedge(0), TRUE),
4 => (paclr_ipd'last_event, tpd_paclr_regout_posedge(0), TRUE),
5 => (papre_ipd'last_event, tpd_papre_regout_posedge(0), TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => fbkout,
OutSignalName => "FBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE),
2 => (pclk_ipd'last_event, tpd_pclk_regout_posedge(0), TRUE),
3 => (pena_ipd'last_event, tpd_pena_regout_posedge(0), TRUE),
4 => (paclr_ipd'last_event, tpd_paclr_regout_posedge(0), TRUE),
5 => (papre_ipd'last_event, tpd_papre_regout_posedge(0), TRUE)),
GlitchData => fbkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_mcell_reg;
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
use work.max_asynch_mcell;
use work.max_mcell_register;
entity max_mcell is
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
output_mode : string := "comb";
register_mode : string := "false";
power_up : string := "low" );
port ( pterm0 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm1 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm2 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm3 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm4 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pterm5 : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pclk : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pena : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
paclr : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
papre : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pxor : in std_logic_vector(51 downto 0) := "0000000000000000000000000000000000000000000000000000";
pexpin : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
fpin : in std_logic := '1';
dataout : out std_logic;
pexpout : out std_logic );
attribute VITAL_LEVEL0 of max_mcell : entity is TRUE;
end max_mcell;
architecture vital_mcell_atom of max_mcell is
attribute VITAL_LEVEL0 of vital_mcell_atom : architecture is TRUE;
component max_asynch_mcell
generic ( operation_mode : string := "normal";
pexp_mode : string := "off";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pterm0_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pxor_combout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_combout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_pterm0_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm1_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm2_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm3_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm4_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pterm5_pexpout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pexpin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fbkin_pexpout : VitalDelayType01 := DefPropDelay01;
tpd_fpin_regin : VitalDelayType01 := DefPropDelay01;
tipd_pterm0 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm1 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm2 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm3 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm4 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pterm5 : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_fpin : VitalDelayType01 := DefPropDelay01;
tipd_pxor : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pexpin : VitalDelayType01 := DefPropDelay01);
port ( pterm0 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm1 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm2 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm3 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm4 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pterm5 : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
fpin : in std_logic := '1';
pxor : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pexpin : in std_logic := '0';
fbkin : in std_logic;
combout : out std_logic;
regin : out std_logic;
pexpout : out std_logic );
end component;
component max_mcell_register
generic ( operation_mode : string := "normal";
power_up : string := "low";
register_mode : string := "dff";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_pclk_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_regout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pclk_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_pena_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_paclr_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_papre_fbkout_posedge : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tpd_aclr_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_fbkout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pena_clk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_pclk_noedge_posedge : VitalDelayArrayType(51 downto 0) := (OTHERS => DefSetupHoldCnst);
tipd_pclk : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_pena : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_paclr : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_papre : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01);
port ( datain : in std_logic;
clk : in std_logic;
aclr : in std_logic;
pclk : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
pena : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
paclr : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
papre : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
regout : out std_logic;
fbkout : out std_logic);
end component;
signal fbk, dffin, combo, dffo :std_ulogic ;
begin
pcom: max_asynch_mcell
generic map ( operation_mode => operation_mode,
pexp_mode => pexp_mode, register_mode => register_mode)
port map ( pterm0 => pterm0,
pterm1 => pterm1,
pterm2 => pterm2,
pterm3 => pterm3,
pterm4 => pterm4,
pterm5 => pterm5,
fpin => fpin,
pxor => pxor,
pexpin => pexpin,
fbkin => fbk,
regin => dffin,
combout => combo,
pexpout => pexpout);
preg: max_mcell_register
generic map ( operation_mode => operation_mode,
power_up => power_up,
register_mode => register_mode)
port map ( datain => dffin,
clk => clk,
aclr => aclr,
pclk => pclk,
pena => pena,
paclr => paclr,
papre => papre,
regout => dffo,
fbkout => fbk);
dataout <= combo when output_mode = "comb" else dffo;
end vital_mcell_atom;
--
--
-- MAX7K_SEXP Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
entity max_asynch_sexp is
generic ( TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_datain_dataout : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01);
tipd_datain : VitalDelayArrayType01(51 downto 0) := (OTHERS => DefPropDelay01));
port ( datain : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
dataout : out STD_LOGIC);
attribute VITAL_LEVEL0 of max_asynch_sexp : entity is TRUE;
end max_asynch_sexp;
architecture behave of max_asynch_sexp is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic_vector(51 downto 0) := (OTHERS => 'U');
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd(0), datain(0), tipd_datain(0));
VitalWireDelay (datain_ipd(1), datain(1), tipd_datain(1));
VitalWireDelay (datain_ipd(2), datain(2), tipd_datain(2));
VitalWireDelay (datain_ipd(3), datain(3), tipd_datain(3));
VitalWireDelay (datain_ipd(4), datain(4), tipd_datain(4));
VitalWireDelay (datain_ipd(5), datain(5), tipd_datain(5));
VitalWireDelay (datain_ipd(6), datain(6), tipd_datain(6));
VitalWireDelay (datain_ipd(7), datain(7), tipd_datain(7));
VitalWireDelay (datain_ipd(8), datain(8), tipd_datain(8));
VitalWireDelay (datain_ipd(9), datain(9), tipd_datain(9));
VitalWireDelay (datain_ipd(10), datain(10), tipd_datain(10));
VitalWireDelay (datain_ipd(11), datain(11), tipd_datain(11));
VitalWireDelay (datain_ipd(12), datain(12), tipd_datain(12));
VitalWireDelay (datain_ipd(13), datain(13), tipd_datain(13));
VitalWireDelay (datain_ipd(14), datain(14), tipd_datain(14));
VitalWireDelay (datain_ipd(15), datain(15), tipd_datain(15));
VitalWireDelay (datain_ipd(16), datain(16), tipd_datain(16));
VitalWireDelay (datain_ipd(17), datain(17), tipd_datain(17));
VitalWireDelay (datain_ipd(18), datain(18), tipd_datain(18));
VitalWireDelay (datain_ipd(19), datain(19), tipd_datain(19));
VitalWireDelay (datain_ipd(20), datain(20), tipd_datain(20));
VitalWireDelay (datain_ipd(21), datain(21), tipd_datain(21));
VitalWireDelay (datain_ipd(22), datain(22), tipd_datain(22));
VitalWireDelay (datain_ipd(23), datain(23), tipd_datain(23));
VitalWireDelay (datain_ipd(24), datain(24), tipd_datain(24));
VitalWireDelay (datain_ipd(25), datain(25), tipd_datain(25));
VitalWireDelay (datain_ipd(26), datain(26), tipd_datain(26));
VitalWireDelay (datain_ipd(27), datain(27), tipd_datain(27));
VitalWireDelay (datain_ipd(28), datain(28), tipd_datain(28));
VitalWireDelay (datain_ipd(29), datain(29), tipd_datain(29));
VitalWireDelay (datain_ipd(30), datain(30), tipd_datain(30));
VitalWireDelay (datain_ipd(31), datain(31), tipd_datain(31));
VitalWireDelay (datain_ipd(32), datain(32), tipd_datain(32));
VitalWireDelay (datain_ipd(33), datain(33), tipd_datain(33));
VitalWireDelay (datain_ipd(34), datain(34), tipd_datain(34));
VitalWireDelay (datain_ipd(35), datain(35), tipd_datain(35));
VitalWireDelay (datain_ipd(36), datain(36), tipd_datain(36));
VitalWireDelay (datain_ipd(37), datain(37), tipd_datain(37));
VitalWireDelay (datain_ipd(38), datain(38), tipd_datain(38));
VitalWireDelay (datain_ipd(39), datain(39), tipd_datain(39));
VitalWireDelay (datain_ipd(40), datain(40), tipd_datain(40));
VitalWireDelay (datain_ipd(41), datain(41), tipd_datain(41));
VitalWireDelay (datain_ipd(42), datain(42), tipd_datain(42));
VitalWireDelay (datain_ipd(43), datain(43), tipd_datain(43));
VitalWireDelay (datain_ipd(44), datain(44), tipd_datain(44));
VitalWireDelay (datain_ipd(45), datain(45), tipd_datain(45));
VitalWireDelay (datain_ipd(46), datain(46), tipd_datain(46));
VitalWireDelay (datain_ipd(47), datain(47), tipd_datain(47));
VitalWireDelay (datain_ipd(48), datain(48), tipd_datain(48));
VitalWireDelay (datain_ipd(49), datain(49), tipd_datain(49));
VitalWireDelay (datain_ipd(50), datain(50), tipd_datain(50));
VitalWireDelay (datain_ipd(51), datain(51), tipd_datain(51));
end block;
VITAL: process(datain_ipd)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable tmp_dataout : std_logic;
begin
tmp_dataout := not (product(datain_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout(0), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- MAX_SEXP
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.max_atom_pack.all;
use work.max_asynch_sexp;
entity max_sexp is
port ( datain : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
dataout : out std_logic);
end max_sexp;
architecture structure of max_sexp is
signal data_out : std_logic;
component max_asynch_sexp
port ( datain : in std_logic_vector(51 downto 0) := "1111111111111111111111111111111111111111111111111111";
dataout: out STD_LOGIC);
end component;
begin
pcom: max_asynch_sexp
port map ( datain => datain,
dataout => data_out);
dataout <= data_out;
end structure;
| gpl-3.0 | 3864694c8a9ecec68192b68577428cb8 | 0.618347 | 3.267005 | false | false | false | false |
alvieboy/xtc-base | regbank_2p.vhd | 1 | 1,982 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity regbank_2p is
generic (
ADDRESS_BITS: integer := 4;
ZEROSIZE: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_wr: in std_logic_vector(31 downto 0);
rb2_we: in std_logic;
rb2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end entity regbank_2p;
architecture behave of regbank_2p is
constant NUMADDRESSES: integer := 2 ** ADDRESS_BITS;
signal rb1_we: std_logic;
signal ssra, ssrb: std_logic;
constant srval: std_logic_vector(31 downto 0) := (others => '0');
constant addrzero: std_logic_vector(ZEROSIZE-1 downto 0):= (others => '0');
begin
-- Register bank.
-- Note the hack for writing to 1st port when 2nd port is
-- being written to same address
process(rb1_addr,rb2_addr,rb2_we)
begin
rb1_we<='0';
if rb2_we='1' and rb1_addr=rb2_addr then
rb1_we<='1';
end if;
end process;
ssra<='1' when rb1_addr(ZEROSIZE-1 downto 0)=addrzero else '0';
ssrb<='1' when rb2_addr(ZEROSIZE-1 downto 0)=addrzero else '0';
rb: entity work.generic_dp_ram_r
generic map (
address_bits => ADDRESS_BITS,
srval_1 => srval,
srval_2 => srval
)
port map (
clka => clk,
ena => rb1_en,
wea => rb1_we,
ssra => ssra,
addra => rb1_addr,
dia => rb2_wr,
doa => rb1_rd,
clkb => clk,
enb => rb2_en,
ssrb => ssrb,
web => rb2_we,
addrb => rb2_addr,
dib => rb2_wr,
dob => open,
dbg_addr => dbg_addr,
dbg_do => dbg_do
);
end behave;
| bsd-3-clause | 8b45bae2b82812541f52d4348ace79ec | 0.587286 | 2.936296 | false | false | false | false |
shvorin/pcie-emu | hdllib/common/types.vhd | 1 | 1,562 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
library ieee;
use ieee.std_logic_1164.all;
package types is
-- measured in bytes
constant dword_logsize : natural := 2;
constant qword_logsize : natural := 3;
constant qqword_logsize : natural := 4;
constant data256_logsize : natural := 5;
constant cell_logsize : natural := 6;
---------------------------------------------------------------------------
subtype dword_range is integer range 2 ** (dword_logsize + 3) - 1 downto 0;
subtype dword is std_logic_vector(dword_range);
type dword_array is array (integer range <>) of dword;
subtype qword_range is integer range 2 ** (qword_logsize + 3) - 1 downto 0;
subtype qword is std_logic_vector(qword_range);
type qword_array is array (integer range <>) of qword;
subtype qqword_range is integer range 2 ** (qqword_logsize + 3) - 1 downto 0;
subtype qqword is std_logic_vector(qqword_range);
type qqword_array is array (integer range <>) of qqword;
subtype data256_range is integer range 2 ** (data256_logsize + 3) - 1 downto 0;
subtype data256_t is std_logic_vector(data256_range);
type data256_array is array (integer range <>) of data256_t;
---------------------------------------------------------------------------
type boolean_array is array (integer range <>) of boolean;
type integer_array is array (integer range <>) of integer;
end types;
| bsd-3-clause | 184c490f796a01e0e17771cdb20abc63 | 0.606274 | 3.984694 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaiigz_hssi_components.vhd | 1 | 127,621 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package ARRIAIIGZ_HSSI_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
function rx_top_basic_width (channel_width : integer) return integer;
function rx_top_num_of_basic (channel_width : integer) return integer;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function alpha_tolower (given_string : string) return string;
function arriaiigz_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string;
function arriaiigz_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer;
function arriaiigz_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer;
-- GENERIC utility functions END
TYPE CMU_MULT_STATE_TYPE IS (INITIAL,INACTIVE,ACTIVE);
--
-- arriaiigz_hssi_clock_divider
--
COMPONENT arriaiigz_hssi_clock_divider
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_refclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchdonein :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_clk0in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_vcobypassin : VitalDelayType01 := DefpropDelay01;
tipd_clk1in :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchbaseclkin :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdig : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(100 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaiigz_hssi_clock_divider";
channel_num : INTEGER := 0;
coreclk_out_gated_by_quad_reset : STRING := "false";
data_rate : INTEGER := 0;
divide_by : INTEGER := 4;
divider_type : STRING := "CHANNEL_REGULAR";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
enable_refclk_out : STRING := "false";
inclk_select : INTEGER := 0;
logical_channel_address : INTEGER := 0;
pre_divide_by : INTEGER := 1;
rate_switch_base_clk_in_select : INTEGER := 0;
rate_switch_done_in_select : INTEGER := 0;
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
refclkin_select : INTEGER := 0;
select_local_rate_switch_base_clock : STRING := "false";
select_local_rate_switch_done : STRING := "true"; -- shawn
select_local_refclk : STRING := "false";
select_refclk_dig : STRING := "false";
sim_analogfastrefclkout_phase_shift : INTEGER := 0;
sim_analogrefclkout_phase_shift : INTEGER := 0;
sim_coreclkout_phase_shift : INTEGER := 0;
sim_refclkout_phase_shift : INTEGER := 0;
use_coreclk_out_post_divider : STRING := "false";
use_refclk_post_divider : STRING := "false";
use_vco_bypass : STRING := "false"
);
PORT (
clk0in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
clk1in : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(100 - 1 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchbaseclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rateswitchdonein : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclkdig : IN STD_LOGIC := '0';
refclkin : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
vcobypassin : IN STD_LOGIC := '0';
analogfastrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogfastrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkoutshifted : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
analogrefclkpulse : OUT STD_LOGIC;
analogrefclkpulseshifted : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC_VECTOR(100 - 1 DOWNTO 0);
rateswitchbaseclock : OUT STD_LOGIC;
rateswitchdone : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
refclkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaiigz_hssi_pll
--
COMPONENT arriaiigz_hssi_pll
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_earlyeios : VitalDelayType01 := DefpropDelay01;
tipd_locktorefclk : VitalDelayType01 := DefpropDelay01;
tipd_pfdfbclk : VitalDelayType01 := DefpropDelay01;
tipd_powerdown : VitalDelayType01 := DefpropDelay01;
tipd_inclk :VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tpd_inclk_clk : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaiigz_hssi_pll";
auto_settings : STRING := "true";
bandwidth_type : STRING := "Auto";
base_data_rate : STRING := "unused";
channel_num : INTEGER := 0;
charge_pump_current_bits : INTEGER := 0;
charge_pump_mode_bits : INTEGER := 0;
charge_pump_test_enable : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
effective_data_rate : STRING := "unused";
enable_dynamic_divider : STRING := "false";
fast_lock_control : STRING := "false";
inclk0_input_period : INTEGER := 0;
inclk1_input_period : INTEGER := 0;
inclk2_input_period : INTEGER := 0;
inclk3_input_period : INTEGER := 0;
inclk4_input_period : INTEGER := 0;
inclk5_input_period : INTEGER := 0;
inclk6_input_period : INTEGER := 0;
inclk7_input_period : INTEGER := 0;
inclk8_input_period : INTEGER := 0;
inclk9_input_period : INTEGER := 0;
input_clock_frequency : STRING := "unused";
logical_channel_address : INTEGER := 0;
logical_tx_pll_number : INTEGER := 0;
loop_filter_c_bits : INTEGER := 0;
loop_filter_r_bits : INTEGER := 0;
m : INTEGER := 0;
n : INTEGER := 0;
pd_charge_pump_current_bits : INTEGER := 0;
pd_loop_filter_r_bits : INTEGER := 0;
pfd_clk_select : INTEGER := 0;
pfd_fb_select : STRING := "internal";
pll_type : STRING := "Auto";
protocol_hint : STRING := "basic";
refclk_divide_by : INTEGER := 0;
refclk_multiply_by : INTEGER := 0;
sim_is_negative_ppm_drift : STRING := "false";
sim_net_ppm_variation : INTEGER := 0;
test_charge_pump_current_down : STRING := "false";
test_charge_pump_current_up : STRING := "false";
use_refclk_pin : STRING := "false";
vco_data_rate : INTEGER := 0;
vco_divide_by : INTEGER := 0;
vco_range : STRING := "low";
vco_multiply_by : INTEGER := 0;
vco_post_scale : INTEGER := 0;
vco_tuning_bits : INTEGER := 0;
volt_reg_control_bits : INTEGER := 0;
volt_reg_output_bits : INTEGER := 0;
sim_clkout_phase_shift : INTEGER := 0;
sim_clkout_latency : INTEGER := 0;
PARAM_DELAY : INTEGER := 0
);
PORT (
areset : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
earlyeios : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 - 1 DOWNTO 0) := (others => '0');
inclk : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
locktorefclk : IN STD_LOGIC := '1';
pfdfbclk : IN STD_LOGIC := '0';
powerdown : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
clk : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
freqlocked : OUT STD_LOGIC;
locked : OUT STD_LOGIC;
pfdfbclkout : OUT STD_LOGIC;
pfdrefclkout : OUT STD_LOGIC;
vcobypassout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaiigz_hssi_tx_pma
--
COMPONENT arriaiigz_hssi_tx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_datain :VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(20 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0inpulse : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_pclk : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_fastrefclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_refclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk4inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk4in : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefpropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_rxdetecten : VitalDelayType01 := DefpropDelay01;
tipd_refclk1inpulse : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpmareset : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk0in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revserialfdbk : VitalDelayType01 := DefpropDelay01;
tipd_refclk3in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxpowerdown : VitalDelayType01 := DefpropDelay01;
tipd_refclk3inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2inpulse : VitalDelayType01 := DefpropDelay01;
tipd_refclk2in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdetectclk : VitalDelayType01 := DefpropDelay01;
tipd_fastrefclk1in :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "arriaiigz_hssi_tx_pma";
analog_power : STRING := "1.5V";
channel_number : INTEGER := 9999;
channel_type : STRING := "auto";
clkin_select : INTEGER := 0; -- 9999; out of bound in loading
clkmux_delay : STRING := "false";
common_mode : STRING := "0.6V";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_reverse_serial_loopback : STRING := "false";
logical_channel_address : INTEGER := 0;
logical_protocol_hint_0 : STRING := "basic";
logical_protocol_hint_1 : STRING := "basic";
logical_protocol_hint_2 : STRING := "basic";
logical_protocol_hint_3 : STRING := "basic";
low_speed_test_select : INTEGER := 9999;
physical_clkin0_mapping : STRING := "x1";
physical_clkin1_mapping : STRING := "x4";
physical_clkin2_mapping : STRING := "xn_top";
physical_clkin3_mapping : STRING := "xn_bottom";
physical_clkin4_mapping : STRING := "hypertransport";
preemp_pretap : INTEGER := 0;
preemp_pretap_inv : STRING := "false";
preemp_tap_1 : INTEGER := 0;
preemp_tap_1_a : INTEGER := 0;
preemp_tap_1_b : INTEGER := 0;
preemp_tap_1_c : INTEGER := 0;
preemp_tap_2 : INTEGER := 0;
preemp_tap_2_inv : STRING := "false";
protocol_hint : STRING := "basic";
rx_detect : INTEGER := 9999;
serialization_factor : INTEGER := 8;
slew_rate : STRING := "low";
termination : STRING := "OCT 100 Ohms";
use_external_termination : STRING := "false";
use_pclk : STRING := "false";
use_pma_direct : STRING := "false";
use_rx_detect : STRING := "false";
use_ser_double_data_mode : STRING := "false";
vod_selection : INTEGER := 0;
vod_selection_a : INTEGER := 0;
vod_selection_b : INTEGER := 0;
vod_selection_c : INTEGER := 0;
vod_selection_d : INTEGER := 0
);
PORT (
datain : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(20 - 1 DOWNTO 0) := (others => '0');
detectrxpowerdown : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(11 - 1 DOWNTO 0) := (others => '0');
fastrefclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
fastrefclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
forceelecidle : IN STD_LOGIC := '0';
pclk : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (OTHERS => '0');
powerdn : IN STD_LOGIC := '0';
refclk0in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk0inpulse : IN STD_LOGIC := '0';
refclk1in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk1inpulse : IN STD_LOGIC := '0';
refclk2in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk2inpulse : IN STD_LOGIC := '0';
refclk3in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
refclk3inpulse : IN STD_LOGIC := '0';
refclk4in : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (OTHERS => '0');
refclk4inpulse : IN STD_LOGIC := '0';
revserialfdbk : IN STD_LOGIC := '0';
rxdetectclk : IN STD_LOGIC := '0';
rxdetecten : IN STD_LOGIC := '0';
txpmareset : IN STD_LOGIC := '0';
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dftout : OUT STD_LOGIC_VECTOR(6 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
rxdetectvalidout : OUT STD_LOGIC;
rxfoundout : OUT STD_LOGIC;
seriallpbkout : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaiigz_hssi_rx_pma
--
COMPONENT arriaiigz_hssi_rx_pma
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_rxpmareset : VitalDelayType01 := DefpropDelay01;
tipd_plllocked : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_ignorephslck : VitalDelayType01 := DefpropDelay01;
tipd_locktoref : VitalDelayType01 := DefpropDelay01;
tipd_adcepowerdn : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_adcestandby : VitalDelayType01 := DefpropDelay01;
tipd_powerdn : VitalDelayType01 := DefpropDelay01;
tipd_seriallpbken : VitalDelayType01 := DefpropDelay01;
tipd_adcereset : VitalDelayType01 := DefpropDelay01;
tipd_deserclock :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_locktodata : VitalDelayType01 := DefpropDelay01;
tipd_freqlock : VitalDelayType01 := DefpropDelay01;
tipd_offsetcancellationen : VitalDelayType01 := DefpropDelay01;
tipd_testbussel :VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoverdatain :VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_seriallpbkin : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(300 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_adaptcapture : VitalDelayType01 := DefpropDelay01;
lpm_type : STRING := "arriaiigz_hssi_rx_pma";
adaptive_equalization_mode : STRING := "none";
allow_serial_loopback : STRING := "false";
allow_vco_bypass : INTEGER := 0;
analog_power : STRING := "1.4V";
channel_number : INTEGER := 0;
channel_type : STRING := "auto";
common_mode : STRING := "0.82V";
deserialization_factor : INTEGER := 8;
dfe_piclk_bandwidth : INTEGER := 0;
dfe_piclk_phase : INTEGER := 0;
dfe_piclk_sel : INTEGER := 0;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
enable_ltd : STRING := "false";
enable_ltr : STRING := "false";
eq_adapt_seq_control : INTEGER := 0;
eq_dc_gain : INTEGER := 0;
eq_max_gradient_control : INTEGER := 0;
eqa_ctrl : INTEGER := 0;
eqb_ctrl : INTEGER := 0;
eqc_ctrl : INTEGER := 0;
eqd_ctrl : INTEGER := 0;
eqv_ctrl : INTEGER := 0;
eyemon_bandwidth : INTEGER := 0;
force_signal_detect : STRING := "true";
ignore_lock_detect : STRING := "false";
logical_channel_address : INTEGER := 0;
low_speed_test_select : INTEGER := 0;
offset_cancellation : INTEGER := 0;
ppm_gen1_2_xcnt_en : INTEGER := 1;
ppm_post_eidle : INTEGER := 0;
ppmselect : INTEGER := 0;
protocol_hint : STRING := "basic";
send_direct_reverse_serial_loopback : STRING := "None";
signal_detect_hysteresis : INTEGER := 4;
signal_detect_hysteresis_valid_threshold : INTEGER := 2;
signal_detect_loss_threshold : INTEGER := 3;
termination : STRING := "OCT 100 Ohms";
use_deser_double_data_width : STRING := "false";
use_external_termination : STRING := "false";
use_pma_direct : STRING := "false";
PARAM_DELAY : INTEGER := 0
);
PORT (
adaptcapture : IN STD_LOGIC := '0';
adcepowerdn : IN STD_LOGIC := '0';
adcereset : IN STD_LOGIC := '0';
adcestandby : IN STD_LOGIC := '0';
datain : IN STD_LOGIC := '0';
deserclock : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(300 - 1 DOWNTO 0) := (others => '0');
extra10gin : IN STD_LOGIC_VECTOR(38 - 1 DOWNTO 0) := (others => '0');
freqlock : IN STD_LOGIC := '0';
ignorephslck : IN STD_LOGIC := '0';
locktodata : IN STD_LOGIC := '0';
locktoref : IN STD_LOGIC := '0';
offsetcancellationen : IN STD_LOGIC := '0';
plllocked : IN STD_LOGIC := '0';
powerdn : IN STD_LOGIC := '0';
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
recoverdatain : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
rxpmareset : IN STD_LOGIC := '0';
seriallpbken : IN STD_LOGIC := '0';
seriallpbkin : IN STD_LOGIC := '0';
testbussel : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
adaptdone : OUT STD_LOGIC;
analogtestbus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
clockout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dataoutfull : OUT STD_LOGIC_VECTOR(20 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(300 - 1 DOWNTO 0);
locktorefout : OUT STD_LOGIC;
ppmdetectclkrel : OUT STD_LOGIC;
recoverdataout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
reverselpbkout : OUT STD_LOGIC;
revserialfdbkout : OUT STD_LOGIC;
signaldetect : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaiigz_hssi_tx_pcs
--
COMPONENT arriaiigz_hssi_tx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bitslipboundaryselect :VitalDelayArrayType01(4 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_ctrlenable :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datain :VitalDelayArrayType01(39 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datainfull :VitalDelayArrayType01(43 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_detectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_dispval :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(149 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enrevparallellpbk : VitalDelayType01 := DefpropDelay01;
tipd_forcedisp :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_forcedispcompliance : VitalDelayType01 := DefpropDelay01;
tipd_forceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_freezptr : VitalDelayType01 := DefpropDelay01;
tipd_hipdatain :VitalDelayArrayType01(9 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipforceelecidle : VitalDelayType01 := DefpropDelay01;
tipd_hiptxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_hiptxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hippowerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hipdetectrxloop : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnrdclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifobyteserdisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnbottomwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopwrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoptrsreset : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntopbytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottombytesel : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxntoprdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnrdclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbottomrdclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipestatetransdone : VitalDelayType01 := DefpropDelay01;
tipd_pipetxswing : VitalDelayType01 := DefpropDelay01;
tipd_pipetxmargin :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pipetxdeemph : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_revparallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrl : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ctrlenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_detectrxloop_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dispval_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedisp_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forcedispcompliance_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_phfifowrenable_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_forceelecidle_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_powerdn_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxdeemph_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxswing_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pipetxmargin_coreclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_phfifooverflow_posedge : VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaiigz_hssi_tx_pcs";
allow_polarity_inversion : STRING := "false";
auto_spd_self_switch_enable : STRING := "false";
bitslip_enable : STRING := "false";
channel_bonding : STRING := "none"; -- none, x8, x4
channel_number : INTEGER := 0;
channel_width : INTEGER := 8;
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false"; --NEW_PARAM, RTL=
datapath_protocol : STRING := "basic"; --replaced by protocol_hint
disable_ph_low_latency_mode : STRING := "false";
disparity_mode : STRING := "none"; -- legacy, new, none
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_delay : INTEGER := 6; -- new in 6.0 <3-6>
enable_bit_reversal : STRING := "false";
enable_idle_selection : STRING := "false";
enable_phfifo_bypass : STRING := "false";
enable_reverse_parallel_loopback : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_symbol_swap : STRING := "false";
enc_8b_10b_compatibility_mode : STRING := "true";
enc_8b_10b_mode : STRING := "none"; -- cascade, normal, none
force_echar : STRING := "false";
force_kchar : STRING := "false";
hip_enable : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none";
ph_fifo_xn_mapping1 : STRING := "none";
ph_fifo_xn_mapping2 : STRING := "none";
ph_fifo_xn_select : INTEGER := 9999;
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_voltage_swing_control : STRING := "false"; --NEW_PARAM, RTL=
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
refclk_select : STRING := "local"; -- cmu_clk_divider
reset_clock_output_during_digital_reset : STRING := "false";
self_test_mode : STRING := "incremental";
use_double_data_mode : STRING := "false";
use_serializer_double_data_mode : STRING := "false";
wr_clk_mux_select : STRING := "core_clk"; -- INT_CLK // int_clk
use_top_quad_as_mater : STRING := "true"; -- NEW_PARAM todo: select top/bottom to provide phfifo pointers
dprio_width : INTEGER := 150
);
PORT (
bitslipboundaryselect : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (others => '0');
coreclk : IN STD_LOGIC := '0';
ctrlenable : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
datain : IN STD_LOGIC_VECTOR(39 DOWNTO 0) := (others => '0');
datainfull : IN STD_LOGIC_VECTOR(43 DOWNTO 0) := (others => '0'); -- WYS_TO_CHANGE
detectrxloop : IN STD_LOGIC := '0';
digitalreset : IN STD_LOGIC := '0';
dispval : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(149 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enrevparallellpbk : IN STD_LOGIC := '0';
forcedisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0'); --fix_width
forcedispcompliance : IN STD_LOGIC := '0';
forceelecidle : IN STD_LOGIC := '0';
freezptr : IN STD_LOGIC := '0';
hipdatain : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
hipdetectrxloop : IN STD_LOGIC := '0';
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hipforceelecidle : IN STD_LOGIC := '0';
hippowerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
hiptxdeemph : IN STD_LOGIC := '0';
hiptxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
invpol : IN STD_LOGIC := '0';
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
localrefclk : IN STD_LOGIC := '0';
phfifobyteserdisable : IN STD_LOGIC := '0';
phfifoptrsreset : IN STD_LOGIC := '0';
phfiforddisable : IN STD_LOGIC := '0';
phfiforeset : IN STD_LOGIC := '0';
phfifowrenable : IN STD_LOGIC := '1';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdclk : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifoxnbottombytesel : IN STD_LOGIC := '0';
phfifoxnbottomrdclk : IN STD_LOGIC := '0';
phfifoxnbottomrdenable : IN STD_LOGIC := '0';
phfifoxnbottomwrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
phfifoxntopbytesel : IN STD_LOGIC := '0';
phfifoxntoprdclk : IN STD_LOGIC := '0';
phfifoxntoprdenable : IN STD_LOGIC := '0';
phfifoxntopwrenable : IN STD_LOGIC := '0';
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
pipestatetransdone : IN STD_LOGIC := '0';
pipetxdeemph : IN STD_LOGIC := '0'; --NEW; RTL=txdeemph;
pipetxmargin : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); --NEW; RTL=txmargin[2:0]
pipetxswing : IN STD_LOGIC := '0'; --NEW; RTL=txswing
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
prbscidenable : IN STD_LOGIC := '0';
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0'; --NEW, RTL=rate
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revparallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
xgmctrl : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(149 DOWNTO 0);
forceelecidleout : OUT STD_LOGIC;
grayelecidleinferselout : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
hiptxclkout : OUT STD_LOGIC;
iqpphfifobyteselout : OUT STD_LOGIC;
iqpphfifordclkout : OUT STD_LOGIC;
iqpphfifordenableout : OUT STD_LOGIC;
iqpphfifowrenableout : OUT STD_LOGIC;
parallelfdbkout : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifooverflow : OUT STD_LOGIC;
phfifordclkout : OUT STD_LOGIC;
phfiforddisableout : OUT STD_LOGIC;
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC;
phfifounderflow : OUT STD_LOGIC;
phfifowrenableout : OUT STD_LOGIC;
pipeenrevparallellpbkout : OUT STD_LOGIC;
pipepowerdownout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pipepowerstateout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rateswitchout : OUT STD_LOGIC;
rdenablesync : OUT STD_LOGIC;
txdetectrx : OUT STD_LOGIC;
xgmctrlenable : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
--
-- arriaiigz_hssi_rx_pcs
--
COMPONENT arriaiigz_hssi_rx_pcs
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_phfifox8bytesel : VitalDelayType01 := DefpropDelay01;
tipd_xgmctrlin : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_parallelfdbk :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_masterclk : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnwrclk :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidlerateswitch : VitalDelayType01 := DefpropDelay01;
tipd_pipepowerstate :VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_alignstatussync : VitalDelayType01 := DefpropDelay01;
tipd_powerdn :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4bytesel : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_phfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_dprioin :VitalDelayArrayType01(399 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_disablefifowrin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectdividedclk : VitalDelayType01 := DefpropDelay01;
tipd_datain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_enabledeskew : VitalDelayType01 := DefpropDelay01;
tipd_hippowerdown :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_revbyteorderwa : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrenable : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrclk : VitalDelayType01 := DefpropDelay01;
tipd_enabyteord : VitalDelayType01 := DefpropDelay01;
tipd_invpol : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8rdenable : VitalDelayType01 := DefpropDelay01;
tipd_revbitorderwa : VitalDelayType01 := DefpropDelay01;
tipd_localrefclk : VitalDelayType01 := DefpropDelay01;
tipd_enapatternalign : VitalDelayType01 := DefpropDelay01;
tipd_iqpphfifoxnrdenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnptrsreset :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_signaldetected : VitalDelayType01 := DefpropDelay01;
tipd_alignstatus : VitalDelayType01 := DefpropDelay01;
tipd_rxdetectvalid : VitalDelayType01 := DefpropDelay01;
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_autospdxnconfigsel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recoveredclk : VitalDelayType01 := DefpropDelay01;
tipd_hiprateswitch : VitalDelayType01 := DefpropDelay01;
tipd_phfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifox4wrclk : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnbytesel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfifowrena : VitalDelayType01 := DefpropDelay01;
tipd_a1a2size : VitalDelayType01 := DefpropDelay01;
tipd_phfifox8wrenable : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnptrsreset :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnwrenable :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnrdenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rateswitchisdone : VitalDelayType01 := DefpropDelay01;
tipd_elecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_hip8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchxndone : VitalDelayType01 := DefpropDelay01;
tipd_iqpautospdxnspgchg :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rmfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_rmfifordena : VitalDelayType01 := DefpropDelay01;
tipd_disablefifordin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_hipelecidleinfersel :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifox4rdenable : VitalDelayType01 := DefpropDelay01;
tipd_pipe8b10binvpolarity : VitalDelayType01 := DefpropDelay01;
tipd_fifordin : VitalDelayType01 := DefpropDelay01;
tipd_ppmdetectrefclk : VitalDelayType01 := DefpropDelay01;
tipd_prbscidenable : VitalDelayType01 := DefpropDelay01;
tipd_digitalreset : VitalDelayType01 := DefpropDelay01;
tipd_rxfound :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cdrctrllocktorefcl : VitalDelayType01 := DefpropDelay01;
tipd_phfifoxnwrclk :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_iqpphfifoxnbytesel :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_autospdxnspdchg :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phfifoxnwrenable :VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fiforesetrd : VitalDelayType01 := DefpropDelay01;
tipd_xgmdatain :VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_phfifordenable_coreclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tpd_coreclk_a1a2sizeout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_ctrldetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_dataoutfull_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_disperr_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_errdetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_patterndetect_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatadeleted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_rmfifodatainserted_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_runningdisp_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_syncstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipebufferstat_posedge : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_coreclk_byteorderalignstatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifooverflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_phfifounderflow_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipephydonestatus_posedge: VitalDelayType01 := DefPropDelay01;
tpd_coreclk_pipedatavalid_posedge: VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaiigz_hssi_rx_pcs";
align_ordered_set_based : STRING := "false";
align_pattern : STRING := "0101111100"; -- word align: size of align_pattern_length;
align_pattern_length : INTEGER := 10; -- <7, 8, 10, 16, 20, 32, 40>;
align_to_deskew_pattern_pos_disp_only : STRING := "false"; -- <true/false>;
allow_align_polarity_inversion : STRING := "false";
allow_pipe_polarity_inversion : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
auto_spd_self_switch_enable : STRING := "false";
bit_slip_enable : STRING := "false";
byte_order_back_compat_enable : STRING := "false";
byte_order_double_data_mode_mask_enable : STRING := "false";
byte_order_invalid_code_or_run_disp_error : STRING := "false";
byte_order_mode : STRING := "none"; --NEW_PARAM_replace byte_ordering_mode
byte_order_pad_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pattern : STRING := "0101111100"; -- <10-bit binary string>;
byte_order_pld_ctrl_enable : STRING := "false"; --ww47_cram added in build 165
cdrctrl_bypass_ppm_detector_cycle : INTEGER := 0;
cdrctrl_cid_mode_enable : STRING := "false";
cdrctrl_enable : STRING := "false";
cdrctrl_mask_cycle : INTEGER := 0;
cdrctrl_min_lock_to_ref_cycle : INTEGER := 0;
cdrctrl_rxvalid_mask : STRING := "false";
channel_bonding : STRING := "none"; -- <none, x4, x8>;
channel_number : INTEGER := 0; -- <integer 0-3>;
channel_width : INTEGER := 10; -- <integer 8,10,16,20,32,40>;
clk1_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, MASTER_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
clk2_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK, CORE_CLK>;
clk_pd_enable : STRING := "false"; --ww47_cram_p1
core_clock_0ppm : STRING := "false";
datapath_low_latency_mode : STRING := "false";
datapath_protocol : STRING := "basic"; -- <basic/pipe/xaui> replaced by protocol_hint
dec_8b_10b_compatibility_mode : STRING := "true";
dec_8b_10b_mode : STRING := "none"; -- <normal/cascaded/none>;
dec_8b_10b_polarity_inv_enable : STRING := "false";
deskew_pattern : STRING := "1100111100"; -- K28.3
disable_auto_idle_insertion : STRING := "false";
disable_running_disp_in_word_align : STRING := "false";
disallow_kchar_after_pattern_ordered_set : STRING := "false";
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
elec_idle_eios_detect_priority_over_eidle_disable : STRING := "false";
elec_idle_gen1_sigdet_enable : STRING := "false";
elec_idle_infer_enable : STRING := "false";
elec_idle_k_detect : STRING := "false";
elec_idle_num_com_detect : INTEGER := 0;
enable_bit_reversal : STRING := "false";
enable_deep_align : STRING := "false";
enable_deep_align_byte_swap : STRING := "false";
enable_self_test_mode : STRING := "false";
enable_true_complement_match_in_word_align : STRING := "true";
error_from_wa_or_8b_10b_select : STRING := "false";
force_signal_detect_dig : STRING := "false";
hip_enable : STRING := "false";
infiniband_invalid_code : INTEGER := 0; -- <integer 0-3>;
insert_pad_on_underflow : STRING := "false";
iqp_bypass : STRING := "false";
iqp_ph_fifo_xn_select : INTEGER := 9999;
logical_channel_address : INTEGER := 0;
migrated_from_prev_family : STRING := "false"; -- b165
num_align_code_groups_in_ordered_set : INTEGER := 1; -- <integer 0-3>;
num_align_cons_good_data : INTEGER := 3; -- wordalign<Integer 1-256>;
num_align_cons_pat : INTEGER := 4; -- <Integer 1-256>;
num_align_loss_sync_error : INTEGER := 1; --NEW_PARAM_replace align_loss_sync_error_num
ph_fifo_disable : STRING := "false";
ph_fifo_low_latency_enable : STRING := "false";
ph_fifo_reg_mode : STRING := "false";
ph_fifo_reset_enable : STRING := "false";
ph_fifo_user_ctrl_enable : STRING := "false";
ph_fifo_xn_mapping0 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping1 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_mapping2 : STRING := "none"; --ww47_cram_p1
ph_fifo_xn_select : INTEGER := 9999;
phystatus_delay : INTEGER := 0;
phystatus_reset_toggle : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pipe_hip_enable : STRING := "false"; --NEW_PARAM todo: remove
pma_done_count : INTEGER := 53392; --ww47_cram_p1
prbs_all_one_detect : STRING := "false";
prbs_cid_pattern : STRING := "false";
prbs_cid_pattern_length : INTEGER := 0;
protocol_hint : STRING := "basic";
rate_match_almost_empty_threshold : INTEGER := 11; -- <integer 0-15>;
rate_match_almost_full_threshold : INTEGER := 13; -- <integer 0-15>;
rate_match_back_to_back : STRING := "false";
rate_match_delete_threshold : INTEGER := 13;
rate_match_empty_threshold : INTEGER := 5;
rate_match_fifo_mode : STRING := "false"; -- <normal/cascaded/generic/cascaded_generic/none> in s2gx, bool in s4gx;
rate_match_full_threshold : INTEGER := 20;
rate_match_insert_threshold : INTEGER := 11;
rate_match_ordered_set_based : STRING := "false"; -- <integer 10 or 20>;
rate_match_pattern1 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern2 : STRING := "00000000000010111100"; -- <20-bit binary string>;
rate_match_pattern_size : INTEGER := 10; -- <integer 10 or 20>;
rate_match_pipe_enable : STRING := "false";
rate_match_reset_enable : STRING := "true"; --NEW_PARAM - default diff from atom
rate_match_skip_set_based : STRING := "false";
rate_match_start_threshold : INTEGER := 7;
rd_clk_mux_select : STRING := "int_clk"; -- <INT_CLK, CORE_CLK>;
recovered_clk_mux_select : STRING := "recvd_clk"; -- <RECVD_CLK, LOCAL_REFCLK, DIGITAL_REFCLK>;
reset_clock_output_during_digital_reset : STRING := "false";
run_length : INTEGER := 200; -- <5-320 or 4-254 depending on the deserialization factor>;
run_length_enable : STRING := "false";
rx_detect_bypass : STRING := "false";
rx_phfifo_wait_cnt : INTEGER := 32;
rxstatus_error_report_mode : INTEGER := 0;
self_test_mode : STRING := "incremental"; -- <PRBS_7,PRBS_8,PRBS_10,PRBS_23,low_freq,mixed_freq,high_freq,incremental,cjpat,crpat>;
test_bus_sel : INTEGER := 0;
use_alignment_state_machine : STRING := "false";
use_deserializer_double_data_mode : STRING := "false";
use_deskew_fifo : STRING := "false";
use_double_data_mode : STRING := "false";
use_parallel_loopback : STRING := "false";
use_rising_edge_triggered_pattern_align : STRING := "false"; -- <true/false>; //83 para: new=23 rem=40
enable_phfifo_bypass : STRING := "false"
);
PORT (
a1a2size : IN STD_LOGIC := '0';
alignstatus : IN STD_LOGIC := '0';
alignstatussync : IN STD_LOGIC := '0';
autospdxnconfigsel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- config_sel_centrl, quad_up, quad_down
autospdxnspdchg : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- From CMU.spped-change_centrl, rx3(up), rx0(down)
bitslip : IN STD_LOGIC := '0';
cdrctrllocktorefcl : IN STD_LOGIC := '0'; -- pld_ltr
coreclk : IN STD_LOGIC := '0';
datain : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0'); --NEW: updated width
digitalreset : IN STD_LOGIC := '0';
disablefifordin : IN STD_LOGIC := '0';
disablefifowrin : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC_VECTOR(399 DOWNTO 0) := (others => '0');
elecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
enabledeskew : IN STD_LOGIC := '0';
enabyteord : IN STD_LOGIC := '0';
enapatternalign : IN STD_LOGIC := '0';
fifordin : IN STD_LOGIC := '0';
fiforesetrd : IN STD_LOGIC := '0';
grayelecidleinferselfromtx : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
hip8b10binvpolarity : IN STD_LOGIC := '0'; -- hip_rxpolarity
hipelecidleinfersel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- hip_eidleinfersel_ch
hippowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- hip_powerdown_ch
hiprateswitch : IN STD_LOGIC := '0'; -- hip_rate
invpol : IN STD_LOGIC := '0';
iqpautospdxnspgchg : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- speed_change_in_pipe_quad_up, down
iqpphfifoxnbytesel : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnptrsreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- reset_pc_ptrs_in_pipe_quad_up, down
iqpphfifoxnrdenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rd_enable_ptrs_in_pipe_quad_up, down
iqpphfifoxnwrclk : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- rx_div2_sync_in_pipe_quad_up, down
iqpphfifoxnwrenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0'); -- wr_enable_ptrs_in_pipe_quad_up, down
localrefclk : IN STD_LOGIC := '0';
masterclk : IN STD_LOGIC := '0';
parallelfdbk : IN STD_LOGIC_VECTOR(19 DOWNTO 0) := (others => '0');
phfifordenable : IN STD_LOGIC := '1';
phfiforeset : IN STD_LOGIC := '0';
phfifowrdisable : IN STD_LOGIC := '0';
phfifox4bytesel : IN STD_LOGIC := '0';
phfifox4rdenable : IN STD_LOGIC := '0';
phfifox4wrclk : IN STD_LOGIC := '0';
phfifox4wrenable : IN STD_LOGIC := '0';
phfifox8bytesel : IN STD_LOGIC := '0';
phfifox8rdenable : IN STD_LOGIC := '0';
phfifox8wrclk : IN STD_LOGIC := '0';
phfifox8wrenable : IN STD_LOGIC := '0';
phfifoxnbytesel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rx_we_in_centrl, quad_up, quad_down
phfifoxnptrsreset : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to both RX & TX.
phfifoxnrdenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- rd_enable_in_centrl, quad_up, quad_down
phfifoxnwrclk : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- ph fifo. From CMU to RX.
phfifoxnwrenable : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0'); -- wr_enable_in_centrl, quad_up, quad_down
pipe8b10binvpolarity : IN STD_LOGIC := '0';
pipeenrevparallellpbkfromtx : IN STD_LOGIC := '0';
pipepowerdown : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
pipepowerstate : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
pmatestbusin : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
powerdn : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
ppmdetectdividedclk : IN STD_LOGIC := '0';
ppmdetectrefclk : IN STD_LOGIC := '0';
prbscidenable : IN STD_LOGIC := '0'; -- prbs_cid_en
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchisdone : IN STD_LOGIC := '0';
rateswitchxndone : IN STD_LOGIC := '0';
recoveredclk : IN STD_LOGIC := '0';
refclk : IN STD_LOGIC := '0';
revbitorderwa : IN STD_LOGIC := '0';
revbyteorderwa : IN STD_LOGIC := '0';
rmfifordena : IN STD_LOGIC := '0';
rmfiforeset : IN STD_LOGIC := '0';
rmfifowrena : IN STD_LOGIC := '0';
rxdetectvalid : IN STD_LOGIC := '0';
rxelecidlerateswitch : IN STD_LOGIC := '0';
rxfound : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
signaldetected : IN STD_LOGIC := '0';
wareset : IN STD_LOGIC := '0'; -- new in 9.1
xauidelcondmet : IN STD_LOGIC := '0';
xauififoovr : IN STD_LOGIC := '0';
xauiinsertincomplete : IN STD_LOGIC := '0';
xauilatencycomp : IN STD_LOGIC := '0';
xgmctrlin : IN STD_LOGIC := '0';
xgmdatain : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0'); --54 ins ---
a1a2sizeout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
a1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
a2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
adetectdeskew : OUT STD_LOGIC;
alignstatussyncout : OUT STD_LOGIC;
autospdrateswitchout : OUT STD_LOGIC;
autospdspdchgout : OUT STD_LOGIC; --ww47_out speed_chang_out_pipe
bistdone : OUT STD_LOGIC;
bisterr : OUT STD_LOGIC;
bitslipboundaryselectout : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --ww47_out wa_boundary
byteorderalignstatus : OUT STD_LOGIC;
cdrctrlearlyeios : OUT STD_LOGIC; --ww47_out Asserted when K_I or K_X_I is detected on the incoming data. To PMA and/or PLD?
cdrctrllocktorefclkout : OUT STD_LOGIC; --ww47_out Force CDR(RX PLL) to LTR.
clkout : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
ctrldetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dataout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
dataoutfull : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); -- new in 6.1
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
disablefifordout : OUT STD_LOGIC;
disablefifowrout : OUT STD_LOGIC;
disperr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dprioout : OUT STD_LOGIC_VECTOR(399 DOWNTO 0);
errdetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
fifordout : OUT STD_LOGIC;
hipdataout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --ww47_out hip_rxd_ch(8:0)
hipdatavalid : OUT STD_LOGIC; --ww47_out hip_rxvalid
hipelecidle : OUT STD_LOGIC; --ww47_out hip_rxelecidle
hipphydonestatus : OUT STD_LOGIC; --ww47_out hip_phystatus
hipstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); --ww47_out hip_rxstatus_ch(2:0)
iqpphfifobyteselout : OUT STD_LOGIC; --ww47_out rx_we_out_pipe
iqpphfifoptrsresetout : OUT STD_LOGIC; --ww47_out reset_pc_pters_out_pipe
iqpphfifordenableout : OUT STD_LOGIC; --ww47_out rd_enable_pipe_out
iqpphfifowrclkout : OUT STD_LOGIC; --ww47_out rx_div2_sync_out_pipe
iqpphfifowrenableout : OUT STD_LOGIC; --ww47_out wr_enable_out_pipe
k1detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
k2detect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
patterndetect : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
phfifobyteselout : OUT STD_LOGIC;
phfifobyteserdisableout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifooverflow : OUT STD_LOGIC;
phfifoptrsresetout : OUT STD_LOGIC; --ww47_out From Auto Speed Neg to TX
phfifordenableout : OUT STD_LOGIC;
phfiforesetout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifounderflow : OUT STD_LOGIC;
phfifowrclkout : OUT STD_LOGIC;
phfifowrdisableout : OUT STD_LOGIC; --ww47_out Sim Only. From RX Ch0 to CMU
phfifowrenableout : OUT STD_LOGIC;
pipebufferstat : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pipedatavalid : OUT STD_LOGIC;
pipeelecidle : OUT STD_LOGIC;
pipephydonestatus : OUT STD_LOGIC;
pipestatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
pipestatetransdoneout : OUT STD_LOGIC;
rateswitchout : OUT STD_LOGIC;
rdalign : OUT STD_LOGIC;
revparallelfdbkdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
rlv : OUT STD_LOGIC;
rmfifoalmostempty : OUT STD_LOGIC;
rmfifoalmostfull : OUT STD_LOGIC;
rmfifodatadeleted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifodatainserted : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rmfifoempty : OUT STD_LOGIC;
rmfifofull : OUT STD_LOGIC;
runningdisp : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
signaldetect : OUT STD_LOGIC;
syncstatus : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
syncstatusdeskew : OUT STD_LOGIC;
xauidelcondmetout : OUT STD_LOGIC;
xauififoovrout : OUT STD_LOGIC;
xauiinsertincompleteout : OUT STD_LOGIC;
xauilatencycompout : OUT STD_LOGIC;
xgmctrldet : OUT STD_LOGIC;
xgmdataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
xgmdatavalid : OUT STD_LOGIC;
xgmrunningdisp : OUT STD_LOGIC
);
END COMPONENT;
--
-- arriaiigz_hssi_cmu
--
COMPONENT arriaiigz_hssi_cmu
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_txphfiforddisable : VitalDelayType01 := DefpropDelay01;
tipd_txctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txclk : VitalDelayType01 := DefpropDelay01;
tipd_syncstatus : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpcsdprioin : VitalDelayArrayType01(1599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatain : VitalDelayArrayType01(31 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanclk : VitalDelayType01 := DefpropDelay01;
tipd_rateswitchdonein : VitalDelayType01 := DefpropDelay01;
tipd_rdenablesync : VitalDelayType01 := DefpropDelay01;
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_rxphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_testin : VitalDelayArrayType01(9999 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpllreset : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxrunningdisp : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatavalid : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_refclkdividerdprioin : VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txpcsdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_rateswitch : VitalDelayType01 := DefpropDelay01;
tipd_rxctrl : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxanalogreset : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxclk : VitalDelayType01 := DefpropDelay01;
tipd_txphfifowrenable : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifowrdisable : VitalDelayType01 := DefpropDelay01;
tipd_rdalign : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_fixedclk : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_scanmode : VitalDelayType01 := DefpropDelay01;
tipd_rxphfifordenable : VitalDelayType01 := DefpropDelay01;
tipd_cmuplldprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txphfiforeset : VitalDelayType01 := DefpropDelay01;
tipd_txcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_adet : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdigitalreset : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cmudividerdprioin : VitalDelayArrayType01(599 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxcoreclk : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_scanin : VitalDelayArrayType01(22 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_quadreset : VitalDelayType01 := DefpropDelay01;
tipd_nonuserfromcal : VitalDelayType01 := DefpropDelay01;
tipd_scanshift : VitalDelayType01 := DefpropDelay01;
tipd_txpmadprioin : VitalDelayArrayType01(1799 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_recovclk : VitalDelayType01 := DefpropDelay01;
tipd_rxpowerdown : VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriooe_posedge : VitalDelayType01 := DefPropDelay01;
lpm_type : STRING := "arriaiigz_hssi_cmu";
analog_test_bus_enable : STRING := "false";
auto_spd_deassert_ph_fifo_rst_count : INTEGER := 0;
auto_spd_phystatus_notify_count : INTEGER := 0;
bonded_quad_mode : STRING := "none";
bypass_bandgap : STRING := "false";
central_test_bus_select : INTEGER := 0;
cmu_type : STRING := "regular";
devaddr : INTEGER := 1;
dprio_config_mode : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
in_xaui_mode : STRING := "false";
migrated_from_prev_family : STRING := "false";
num_con_align_chars_for_align : INTEGER := 4;
num_con_errors_for_align_loss : INTEGER := 2;
num_con_good_data_for_align_approach : INTEGER := 3;
offset_all_errors_align : STRING := "false";
pipe_auto_speed_nego_enable : STRING := "false";
pipe_freq_scale_mode : STRING := "Data width";
pma_done_count : INTEGER := 0;
portaddr : INTEGER := 1;
rx0_auto_spd_self_switch_enable : STRING := "false";
rx0_channel_bonding : STRING := "none";
rx0_clk1_mux_select : STRING := "recovered clock";
rx0_clk2_mux_select : STRING := "recovered clock";
rx0_clk_pd_enable : STRING := "false";
rx0_ph_fifo_reg_mode : STRING := "false";
rx0_ph_fifo_reset_enable : STRING := "false";
rx0_ph_fifo_user_ctrl_enable : STRING := "false";
rx0_phfifo_wait_cnt : INTEGER := 0;
rx0_rd_clk_mux_select : STRING := "int clock";
rx0_recovered_clk_mux_select : STRING := "recovered clock";
rx0_reset_clock_output_during_digital_reset : STRING := "false";
rx0_use_double_data_mode : STRING := "false";
rx_master_direction : STRING := "none";
rx_xaui_sm_backward_compatible_enable : STRING := "false";
test_mode : STRING := "false";
tx0_auto_spd_self_switch_enable : STRING := "false";
tx0_channel_bonding : STRING := "none";
tx0_clk_pd_enable : STRING := "false";
tx0_ph_fifo_reg_mode : STRING := "false";
tx0_ph_fifo_reset_enable : STRING := "false";
tx0_ph_fifo_user_ctrl_enable : STRING := "false";
tx0_rd_clk_mux_select : STRING := "int clock";
tx0_reset_clock_output_during_digital_reset : STRING := "false";
tx0_use_double_data_mode : STRING := "false";
tx0_wr_clk_mux_select : STRING := "int_clk";
tx_master_direction : STRING := "none";
tx_pll0_used_as_rx_cdr : STRING := "false";
tx_pll1_used_as_rx_cdr : STRING := "false";
tx_xaui_sm_backward_compatible_enable : STRING := "false";
use_deskew_fifo : STRING := "false";
vcceh_voltage : STRING := "3.0V";
vcceh_voltage_user_specified_auto : STRING := "true";
protocol_hint : STRING := "basic";
clkdiv0_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv0_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv1_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv1_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv2_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv2_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv3_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv3_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv4_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv4_inclk1_logical_to_physical_mapping : STRING := "pll1";
clkdiv5_inclk0_logical_to_physical_mapping : STRING := "pll0";
clkdiv5_inclk1_logical_to_physical_mapping : STRING := "pll1";
cmu_divider0_inclk0_physical_mapping : STRING := "pll0";
cmu_divider0_inclk1_physical_mapping : STRING := "pll1";
cmu_divider0_inclk2_physical_mapping : STRING := "x4";
cmu_divider0_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider0_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider1_inclk0_physical_mapping : STRING := "pll0";
cmu_divider1_inclk1_physical_mapping : STRING := "pll1";
cmu_divider1_inclk2_physical_mapping : STRING := "x4";
cmu_divider1_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider1_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider2_inclk0_physical_mapping : STRING := "pll0";
cmu_divider2_inclk1_physical_mapping : STRING := "pll1";
cmu_divider2_inclk2_physical_mapping : STRING := "x4";
cmu_divider2_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider2_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider3_inclk0_physical_mapping : STRING := "pll0";
cmu_divider3_inclk1_physical_mapping : STRING := "pll1";
cmu_divider3_inclk2_physical_mapping : STRING := "x4";
cmu_divider3_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider3_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider4_inclk0_physical_mapping : STRING := "pll0";
cmu_divider4_inclk1_physical_mapping : STRING := "pll1";
cmu_divider4_inclk2_physical_mapping : STRING := "x4";
cmu_divider4_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider4_inclk4_physical_mapping : STRING := "xn_b";
cmu_divider5_inclk0_physical_mapping : STRING := "pll0";
cmu_divider5_inclk1_physical_mapping : STRING := "pll1";
cmu_divider5_inclk2_physical_mapping : STRING := "x4";
cmu_divider5_inclk3_physical_mapping : STRING := "xn_t";
cmu_divider5_inclk4_physical_mapping : STRING := "xn_b";
pll0_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll0_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll0_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll0_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll0_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll0_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll0_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll0_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll0_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll0_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll1_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll1_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll1_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll1_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll1_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll1_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll1_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll1_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll1_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll1_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll2_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll2_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll2_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll2_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll2_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll2_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll2_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll2_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll2_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll2_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll3_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll3_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll3_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll3_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll3_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll3_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll3_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll3_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll3_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll3_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll4_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll4_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll4_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll4_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll4_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll4_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll4_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll4_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll4_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll4_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll5_inclk0_logical_to_physical_mapping : STRING := "clkrefclk0";
pll5_inclk1_logical_to_physical_mapping : STRING := "clkrefclk1";
pll5_inclk2_logical_to_physical_mapping : STRING := "iq2";
pll5_inclk3_logical_to_physical_mapping : STRING := "iq3";
pll5_inclk4_logical_to_physical_mapping : STRING := "iq4";
pll5_inclk5_logical_to_physical_mapping : STRING := "iq5";
pll5_inclk6_logical_to_physical_mapping : STRING := "iq6";
pll5_inclk7_logical_to_physical_mapping : STRING := "iq7";
pll5_inclk8_logical_to_physical_mapping : STRING := "pld_clk";
pll5_inclk9_logical_to_physical_mapping : STRING := "gpll_clk";
pll0_logical_to_physical_mapping : INTEGER := 0;
pll1_logical_to_physical_mapping : INTEGER := 1;
pll2_logical_to_physical_mapping : INTEGER := 2;
pll3_logical_to_physical_mapping : INTEGER := 3;
pll4_logical_to_physical_mapping : INTEGER := 4;
pll5_logical_to_physical_mapping : INTEGER := 5;
refclk_divider0_logical_to_physical_mapping : INTEGER := 0;
refclk_divider1_logical_to_physical_mapping : INTEGER := 1;
rx0_logical_to_physical_mapping : INTEGER := 0;
rx1_logical_to_physical_mapping : INTEGER := 1;
rx2_logical_to_physical_mapping : INTEGER := 2;
rx3_logical_to_physical_mapping : INTEGER := 3;
rx4_logical_to_physical_mapping : INTEGER := 4;
rx5_logical_to_physical_mapping : INTEGER := 5;
tx0_logical_to_physical_mapping : INTEGER := 0;
tx1_logical_to_physical_mapping : INTEGER := 1;
tx2_logical_to_physical_mapping : INTEGER := 2;
tx3_logical_to_physical_mapping : INTEGER := 3;
tx4_logical_to_physical_mapping : INTEGER := 4;
tx5_logical_to_physical_mapping : INTEGER := 5;
tx0_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx0_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx0_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx0_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx0_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx1_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx1_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx1_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx1_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx1_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx2_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx2_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx2_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx2_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx2_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx3_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx3_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx3_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx3_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx3_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx4_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx4_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx4_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx4_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx4_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
tx5_pma_inclk0_logical_to_physical_mapping : STRING := "x1";
tx5_pma_inclk1_logical_to_physical_mapping : STRING := "x4";
tx5_pma_inclk2_logical_to_physical_mapping : STRING := "xn_top";
tx5_pma_inclk3_logical_to_physical_mapping : STRING := "xn_bottom";
tx5_pma_inclk4_logical_to_physical_mapping : STRING := "hypertransport";
sim_dump_dprio_internal_reg_at_time : INTEGER := 0; -- in ps
sim_dump_filename : STRING := "sim_dprio_dump.txt" -- over-write when multiple CMUs
);
PORT (
adet : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
cmudividerdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
cmuplldprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extra10gin : IN STD_LOGIC_VECTOR(6 DOWNTO 0) := (others => '0');
fixedclk : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
lccmurtestbussel : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
nonuserfromcal : IN STD_LOGIC := '0';
pmacramtest : IN STD_LOGIC := '0'; -- new 9.0 ww47
quadreset : IN STD_LOGIC := '0';
rateswitch : IN STD_LOGIC := '0';
rateswitchdonein : IN STD_LOGIC := '0';
rdalign : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rdenablesync : IN STD_LOGIC := '0';
recovclk : IN STD_LOGIC := '0';
refclkdividerdprioin : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
rxanalogreset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxclk : IN STD_LOGIC := '0';
rxcoreclk : IN STD_LOGIC := '0';
rxctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
rxdatavalid : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
rxpcsdprioin : IN STD_LOGIC_VECTOR(1599 DOWNTO 0) := (others => '0');
rxphfifordenable : IN STD_LOGIC := '0';
rxphfiforeset : IN STD_LOGIC := '0';
rxphfifowrdisable : IN STD_LOGIC := '0';
rxpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
rxpowerdown : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (others => '0');
rxrunningdisp : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
scanclk : IN STD_LOGIC := '0';
scanin : IN STD_LOGIC_VECTOR(22 DOWNTO 0) := (others => '0');
scanmode : IN STD_LOGIC := '0';
scanshift : IN STD_LOGIC := '0';
syncstatus : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(9999 DOWNTO 0) := (others => '0');
txclk : IN STD_LOGIC := '0';
txcoreclk : IN STD_LOGIC := '0';
txctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txdatain : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
txdigitalreset : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
txpcsdprioin : IN STD_LOGIC_VECTOR(599 DOWNTO 0) := (others => '0');
txphfiforddisable : IN STD_LOGIC := '0';
txphfiforeset : IN STD_LOGIC := '0';
txphfifowrenable : IN STD_LOGIC := '0';
txpllreset : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => '0');
txpmadprioin : IN STD_LOGIC_VECTOR(1799 DOWNTO 0) := (others => '0');
alignstatus : OUT STD_LOGIC;
autospdx4configsel : OUT STD_LOGIC;
autospdx4rateswitchout : OUT STD_LOGIC;
autospdx4spdchg : OUT STD_LOGIC;
clkdivpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cmudividerdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
cmuplldprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
digitaltestout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
dpriodisableout : OUT STD_LOGIC;
dpriooe : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC;
enabledeskew : OUT STD_LOGIC;
extra10gout : OUT STD_LOGIC;
fiforesetrd : OUT STD_LOGIC;
lccmutestbus : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
phfifiox4ptrsreset : OUT STD_LOGIC;
pllpowerdn : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pllresetout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
quadresetout : OUT STD_LOGIC;
refclkdividerdprioout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxadcepowerdown : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxadceresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcrupowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxcruresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxibpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rxpcsdprioout : OUT STD_LOGIC_VECTOR(1599 DOWNTO 0);
rxphfifox4byteselout : OUT STD_LOGIC;
rxphfifox4wrclkout : OUT STD_LOGIC;
rxphfifox4rdenableout : OUT STD_LOGIC;
rxphfifox4wrenableout : OUT STD_LOGIC;
rxpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0);
scanout : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
testout : OUT STD_LOGIC_VECTOR(6999 DOWNTO 0);
txanalogresetout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txctrlout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdataout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
txdetectrxpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txdigitalresetout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txdividerpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txobpowerdown : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
txpcsdprioout : OUT STD_LOGIC_VECTOR(599 DOWNTO 0);
txphfifox4byteselout : OUT STD_LOGIC;
txphfifox4rdclkout : OUT STD_LOGIC;
txphfifox4rdenableout : OUT STD_LOGIC;
txphfifox4wrenableout : OUT STD_LOGIC;
txpmadprioout : OUT STD_LOGIC_VECTOR(1799 DOWNTO 0)
);
END COMPONENT;
--
-- arriaiigz_hssi_calibration_block
--
COMPONENT arriaiigz_hssi_calibration_block
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_clk : VitalDelayType01 := DefpropDelay01;
lpm_type : string := "arriaiigz_hssi_calibration_block";
cont_cal_mode : string := "false";
enable_rx_cal_tw : string := "false";
enable_tx_cal_tw : string := "false";
migrated_from_prev_family : string := "false";
rtest : string := "false";
rx_cal_wt_value : integer := 0;
send_rx_cal_status : string := "true";
tx_cal_wt_value : integer := 1);
PORT (
clk : IN std_logic := '0';
enabletestbus : IN std_logic := '0';
powerdn : IN std_logic := '0';
testctrl : IN std_logic := '0';
calibrationstatus : OUT std_logic_vector(4 DOWNTO 0);
nonusertocmu : OUT std_logic);
END COMPONENT;
--
-- arriaiigz_hssi_refclk_divider
--
COMPONENT arriaiigz_hssi_refclk_divider
GENERIC (
divider_number : INTEGER := 0; -- 0 or 1 for logical numbering
enable_divider : STRING := "false";
lpm_type : STRING := "arriaiigz_hssi_refclk_divider";
refclk_coupling_termination : STRING := "dc_coupling_external_termination";
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tipd_dpriodisable : VitalDelayType01 := DefPropDelay01;
tipd_dprioin : VitalDelayType01 := DefPropDelay01;
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tpd_inclk_clkout : VitalDelayType01 := DefPropDelay01
);
PORT (
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
inclk : IN STD_LOGIC:= '0';
clkout : OUT STD_LOGIC;
dprioout : OUT STD_LOGIC);
END COMPONENT;
end arriaiigz_hssi_components;
package body ARRIAIIGZ_HSSI_COMPONENTS is
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(39 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function rx_top_basic_width (channel_width : integer) return integer is
variable basic_width : integer;
begin
if (channel_width mod 10 = 0) then
basic_width := 10;
else
basic_width := 8;
end if;
return(basic_width);
end rx_top_basic_width;
function rx_top_num_of_basic (channel_width : integer) return integer is
variable num_of_basic : integer;
begin
if (channel_width mod 10 = 0) then
num_of_basic := channel_width/10;
else
num_of_basic := channel_width/8;
end if;
return(num_of_basic);
end rx_top_num_of_basic;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
function arriaiigz_tx_pcs_mph_fifo_xn_mapping (ph_fifo_xn_select : integer; ph_fifo_xn_mapping0 : string; ph_fifo_xn_mapping1 : string; ph_fifo_xn_mapping2 : string) return string is
begin
CASE ph_fifo_xn_select IS
WHEN 0 => RETURN ph_fifo_xn_mapping0;
WHEN 1 => RETURN ph_fifo_xn_mapping1;
WHEN 2 => RETURN ph_fifo_xn_mapping2;
WHEN OTHERS => RETURN "none";
END CASE;
end arriaiigz_tx_pcs_mph_fifo_xn_mapping;
function arriaiigz_tx_pcs_mphfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1) or (ph_fifo_xn_select = 2)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end arriaiigz_tx_pcs_mphfifo_index;
function arriaiigz_tx_pcs_miqp_phfifo_index ( ph_fifo_xn_select : integer) return integer is
variable fifo_index : integer;
begin
if ((ph_fifo_xn_select = 0) OR (ph_fifo_xn_select = 1)) then
fifo_index := ph_fifo_xn_select;
else
fifo_index := 0;
end if;
return(fifo_index);
end arriaiigz_tx_pcs_miqp_phfifo_index;
end ARRIAIIGZ_HSSI_COMPONENTS;
| gpl-3.0 | eec46d151de2d350454e9b65a4482481 | 0.499879 | 4.281147 | false | false | false | false |
alvieboy/xtc-base | xtccomppkg.old.vhd | 1 | 18,203 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
package xtccomppkg is
component generic_dp_ram is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component generic_dp_ram_r is
generic (
address_bits: integer := 8;
srval_1: std_logic_vector(31 downto 0);
srval_2: std_logic_vector(31 downto 0)
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
ssra: in std_logic;
dia: in std_logic_vector(31 downto 0);
doa: out std_logic_vector(31 downto 0);
clkb: in std_logic;
enb: in std_logic;
ssrb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(31 downto 0);
dob: out std_logic_vector(31 downto 0);
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0);
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component xtc is
port (
wb_syscon: in wb_syscon_type;
-- Master wishbone interface
wbo: out wb_mosi_type;
wbi: in wb_miso_type;
-- ROM wb interface
romwbo: out wb_mosi_type;
romwbi: in wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
break: out std_logic;
intack: out std_logic;
edbg: in memory_debug_type
);
end component;
component icache is
generic (
ADDRESS_HIGH: integer := 26
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
valid: out std_logic;
data: out std_logic_vector(31 downto 0);
address: in std_logic_vector(31 downto 0);
strobe: in std_logic;
enable: in std_logic;
stall: out std_logic;
flush: in std_logic;
abort: in std_logic;
tag: in std_logic_vector(31 downto 0);
tagen: in std_logic;
-- Master wishbone interface
m_wb_ack_i: in std_logic;
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_adr_o: out std_logic_vector(31 downto 0);
m_wb_cyc_o: out std_logic;
m_wb_stb_o: out std_logic;
m_wb_stall_i: in std_logic;
m_wb_we_o: out std_logic
);
end component;
component mux32_4 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
i2: in std_logic_vector(31 downto 0);
i3: in std_logic_vector(31 downto 0);
sel: in std_logic_vector(1 downto 0);
o: out std_logic_vector(31 downto 0)
);
end component;
component mux32_2 is
port (
i0: in std_logic_vector(31 downto 0);
i1: in std_logic_vector(31 downto 0);
sel: in std_logic;
o: out std_logic_vector(31 downto 0)
);
end component mux32_2;
component alu is
port (
clk: in std_logic;
rst: in std_logic;
a: in unsigned(31 downto 0);
b: in unsigned(31 downto 0);
o: out unsigned(31 downto 0);
y: out unsigned(31 downto 0);
op: in alu_op_type;
en: in std_logic;
ci: in std_logic;
cen:in std_logic;
busy: out std_logic;
valid: out std_logic;
co: out std_logic;
zero: out std_logic;
ovf: out std_logic;
sign: out std_logic
);
end component;
component fetch is port (
clk: in std_logic;
rst: in std_logic;
-- Connection to ROM
stall: in std_logic;
valid: in std_logic;
address: out std_logic_vector(31 downto 0);
read: in std_logic_vector(31 downto 0);
enable: out std_logic;
strobe: out std_logic;
abort: out std_logic;
nseq: out std_logic;
-- Control
freeze: in std_logic;
jump: in std_logic;
jumpaddr: in word_type;
dual: in std_logic;
-- Outputs for next stages
fuo: out fetch_output_type
);
end component;
component decode is
port (
clk: in std_logic;
rst: in std_logic;
-- Input for previous stages
fui: in fetch_output_type;
-- Output for next stages
duo: out decode_output_type;
busy: out std_logic;
freeze: in std_logic;
flush: in std_logic;
jump: in std_logic;
jumpmsb: in std_logic;
dual: out std_logic
);
end component;
component fetchdata is
port (
clk: in std_logic;
rst: in std_logic;
-- Register access
r1_en: out std_logic;
r1_addr: out regaddress_type;
r1_read: in word_type_std;
r2_en: out std_logic;
r2_addr: out regaddress_type;
r2_read: in word_type_std;
w_addr: out regaddress_type;
w_en: out std_logic;
-- Input for previous stages
dui: in decode_output_type;
freeze: in std_logic;
flush: in std_logic;
refetch: in std_logic;
executed: in boolean;
clrhold: in std_logic;
-- Output for next stages
fduo: out fetchdata_output_type
);
end component;
component execute is
port (
clk: in std_logic;
rst: in std_logic;
mem_busy: in std_logic;
busy: out std_logic;
refetch: in std_logic;
wb_busy: in std_logic;
int: in std_logic;
intline: in std_logic_vector(7 downto 0);
nmi: in std_logic;
nmiack: out std_logic;
-- Input for previous stages
fdui: in fetchdata_output_type;
-- Output for next stages
euo: out execute_output_type;
-- Input from memory unit, for SPR update
mui: in memory_output_type;
-- Coprocessor interface
co: out copifo;
ci: in copifi;
dbgo: out execute_debug_type
);
end component execute;
component memory is
port (
clk: in std_logic;
rst: in std_logic;
-- Memory interface
wb_ack_i: in std_logic;
wb_err_i: in std_logic;
wb_dat_i: in std_logic_vector(31 downto 0);
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_o: out std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_stall_i: in std_logic;
protw: in std_logic_vector(31 downto 0);
proten: in std_logic;
busy: out std_logic;
refetch: out std_logic;
dbgo: out memory_debug_type;
-- Input for previous stages
eui: in execute_output_type;
-- Output for next stages
muo: out memory_output_type
);
end component memory;
component writeback is
port (
clk: in std_logic;
rst: in std_logic;
busy: out std_logic;
-- Register 0 access writeback
r0_en: out std_logic;
r0_we: out std_logic;
r0_addr: out regaddress_type;
r0_write: out word_type_std;
-- Register 1 access writeback
r1_en: out std_logic;
r1_we: out std_logic;
r1_addr: out regaddress_type;
r1_write: out word_type_std;
-- Input for previous stages
mui: in memory_output_type;
eui: in execute_output_type
);
end component;
component regbank_2p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_wr: in std_logic_vector(31 downto 0);
rb2_we: in std_logic;
rb2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component regbank_3p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_wr: in std_logic_vector(31 downto 0);
rb3_we: in std_logic;
rb3_en: in std_logic
-- RTL Debug access
--dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
--dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component opdec is
port (
opcode_low: in std_logic_vector(15 downto 0);
opcode_high: in std_logic_vector(15 downto 0);
dec: out opdec_type
);
end component;
component taint is
generic (
COUNT: integer := 16
);
port (
clk: in std_logic;
rst: in std_logic;
req1_en: in std_logic;
req1_r: in regaddress_type;
req2_en: in std_logic;
req2_r: in regaddress_type;
ready: out std_logic;
set_en: in std_logic;
set_r: in regaddress_type;
clr_en: in std_logic;
clr_r: in regaddress_type;
taint: out std_logic_vector(COUNT-1 downto 0)
);
end component;
component wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end component;
component xtc_wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_syscon: in wb_syscon_type;
-- Master
m_wbi: in wb_mosi_type;
m_wbo: out wb_miso_type;
-- Slave signals
s0_wbo: out wb_mosi_type;
s0_wbi: in wb_miso_type;
s1_wbo: out wb_mosi_type;
s1_wbi: in wb_miso_type
);
end component;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_syscon: in wb_syscon_type;
-- Master 0 signals
m0_wbi: in wb_mosi_type;
m0_wbo: out wb_miso_type;
-- Master 1 signals
m1_wbi: in wb_mosi_type;
m1_wbo: out wb_miso_type;
-- Slave signals
s0_wbi: in wb_miso_type;
s0_wbo: out wb_mosi_type
);
end component;
component wb_master_p_to_slave_np is
port (
syscon: in wb_syscon_type;
-- Master signals
mwbi: in wb_mosi_type;
mwbo: out wb_miso_type;
-- Slave signals
swbi: in wb_miso_type;
swbo: out wb_mosi_type
);
end component;
component xtc_top_bram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type
);
end component;
component xtc_top_sdram is
port (
wb_syscon: in wb_syscon_type;
-- IO wishbone interface
iowbo: out wb_mosi_type;
iowbi: in wb_miso_type;
-- DMA
dmawbi: in wb_mosi_type;
dmawbo: out wb_miso_type;
nmi: in std_logic;
nmiack: out std_logic;
rstreq: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end component;
component regbank_5p is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw_wr: in std_logic_vector(31 downto 0);
rbw_we: in std_logic;
rbw_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component regbank_5p;
component regbank_4r_2w is
generic (
ADDRESS_BITS: integer := 4
);
port (
clk: in std_logic;
rb1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb1_en: in std_logic;
rb1_rd: out std_logic_vector(31 downto 0);
rb2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb2_en: in std_logic;
rb2_rd: out std_logic_vector(31 downto 0);
rb3_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb3_en: in std_logic;
rb3_rd: out std_logic_vector(31 downto 0);
rb4_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rb4_en: in std_logic;
rb4_rd: out std_logic_vector(31 downto 0);
rbw1_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw1_wr: in std_logic_vector(31 downto 0);
rbw1_we: in std_logic;
rbw1_en: in std_logic;
rbw2_addr: in std_logic_vector(ADDRESS_BITS-1 downto 0);
rbw2_wr: in std_logic_vector(31 downto 0);
rbw2_we: in std_logic;
rbw2_en: in std_logic;
-- RTL Debug access
dbg_addr: in std_logic_vector(address_bits-1 downto 0) := (others => '0');
dbg_do: out std_logic_vector(32-1 downto 0)
);
end component;
component insnqueue is
port (
rst: in std_logic;
clkw: in std_logic;
din: in std_logic_vector(15 downto 0);
en: in std_logic;
clr: in std_logic;
full: out std_logic;
clkr: in std_logic;
pop: in std_logic;
dualpop: in std_logic;
dout0: out std_logic_vector(15 downto 0);
dout1: out std_logic_vector(15 downto 0);
empty: out std_logic;
dvalid: out std_logic
);
end component;
component xtc_ioctrl is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
-- Slaves
swbi: in slot_wbi;
swbo: out slot_wbo;
sids: in slot_ids
);
end component xtc_ioctrl;
component mmu is
generic (
TLB_ENTRY_BITS: natural := 3;
CONTEXT_SIZE_BITS: natural := 6;
SIMPLIFIED: boolean := true
);
port (
clk: in std_logic;
rst: in std_logic;
addr: in std_logic_vector(31 downto 0);
ctx: in std_logic_vector(CONTEXT_SIZE_BITS-1 downto 0);
en: in std_logic;
tlbw: in std_logic;
tlba: in std_logic_vector(TLB_ENTRY_BITS-1 downto 0);
tlbv: in tlb_entry_type;
paddr: out std_logic_vector(31 downto 0);
valid: out std_logic;
pw: out std_logic; -- Write permission
pr: out std_logic; -- Read permission
px: out std_logic; -- eXecute permission
ps: out std_logic -- Supervisor/User
);
end component;
component dcache is
generic (
ADDRESS_HIGH: integer := 31;
CACHE_MAX_BITS: integer := 13; -- 8 Kb
CACHE_LINE_SIZE_BITS: integer := 6 -- 64 bytes
);
port (
syscon: in wb_syscon_type;
ci: in dcache_in_type;
co: out dcache_out_type;
mwbi: in wb_miso_type;
mwbo: out wb_mosi_type
);
end component;
component generic_dp_ram_rf is
generic (
address_bits: integer := 8;
data_bits: integer := 32
);
port (
clka: in std_logic;
ena: in std_logic;
wea: in std_logic;
addra: in std_logic_vector(address_bits-1 downto 0);
dia: in std_logic_vector(data_bits-1 downto 0);
doa: out std_logic_vector(data_bits-1 downto 0);
clkb: in std_logic;
enb: in std_logic;
web: in std_logic;
addrb: in std_logic_vector(address_bits-1 downto 0);
dib: in std_logic_vector(data_bits-1 downto 0);
dob: out std_logic_vector(data_bits-1 downto 0)
);
end component;
component nodev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end component;
component sinkdev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end component;
end package;
| bsd-3-clause | 9e4438c908b5c81f5a1db3732366bd80 | 0.567049 | 3.166841 | false | false | false | false |
asicguy/gplgpu | hdl/altera_ddr3_128_sim/ddr3_int_phy_alt_mem_phy_seq.vhd | 2 | 647,873 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr3_int_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr3_int_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr3_int_phy_alt_mem_phy_record_pkg;
--
package body ddr3_int_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 7;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr3_int_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr3_int_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr3_int_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr3_int_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr3_int_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
package ddr3_int_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
package body ddr3_int_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr3_int_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 8;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr3_int_phy_alt_mem_phy_iram_ram;
--
entity ddr3_int_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr3_int_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr3_int_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr3_int_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr3_int_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr3_int_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr3_int_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr3_int_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr3_int_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr3_int_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr3_int_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr3_int_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr3_int_phy_alt_mem_phy_admin;
--
use work.ddr3_int_phy_alt_mem_phy_mmi;
--
use work.ddr3_int_phy_alt_mem_phy_iram;
--
use work.ddr3_int_phy_alt_mem_phy_dgrb;
--
use work.ddr3_int_phy_alt_mem_phy_dgwb;
--
use work.ddr3_int_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr3_int_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr3_int_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr3_int_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr3_int_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr3_int_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr3_int_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr3_int_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr3_int_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| gpl-3.0 | d6e815bfcbff9cb6d54a2414ccdc7121 | 0.441648 | 4.425543 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/220model_87.vhd | 1 | 375,178 | ---------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--------------------------------------------------------------------------
--
-- Quartus II 11.0 Build 157 04/27/2011
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
-- These models are based on LPM version 220 (EIA-IS103 October 1998).
--------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
-------------------------------------------------------------------------------
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_COMMON_CONVERSION
--
-- Description : Common conversion functions
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
-- PACKAGE DECLARATION
package LPM_COMMON_CONVERSION is
-- FUNCTION DECLARATION
function STR_TO_INT (str : string) return integer;
function INT_TO_STR (value : in integer) return string;
function HEX_STR_TO_INT (str : in string) return integer;
function BIN_STR_TO_INT (str : in string) return integer;
function OCT_STR_TO_INT (str : in string) return integer;
function INT_STR_TO_INT (str : in string) return integer;
function ALPHA_TOLOWER (given_string : in string) return string;
procedure SHRINK_LINE (str_line : inout line; pos : in integer);
end LPM_COMMON_CONVERSION;
package body LPM_COMMON_CONVERSION is
function STR_TO_INT ( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in 1 to len loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "in string parameter! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 10 + digit;
end loop;
return ivalue;
end STR_TO_INT;
-- This function converts an integer to a string
function INT_TO_STR (value : in integer) return string is
variable ivalue : integer := 0;
variable index : integer := 0;
variable digit : integer := 0;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 => line_no(index) := '0';
when 1 => line_no(index) := '1';
when 2 => line_no(index) := '2';
when 3 => line_no(index) := '3';
when 4 => line_no(index) := '4';
when 5 => line_no(index) := '5';
when 6 => line_no(index) := '6';
when 7 => line_no(index) := '7';
when 8 => line_no(index) := '8';
when 9 => line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end INT_TO_STR;
-- This function converts a hexadecimal number to an integer
function HEX_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'A' => digit := 10;
when 'a' => digit := 10;
when 'B' => digit := 11;
when 'b' => digit := 11;
when 'C' => digit := 12;
when 'c' => digit := 12;
when 'D' => digit := 13;
when 'd' => digit := 13;
when 'E' => digit := 14;
when 'e' => digit := 14;
when 'F' => digit := 15;
when 'f' => digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal hex character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end HEX_STR_TO_INT;
-- This function converts a binary number to an integer
function BIN_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when others =>
ASSERT FALSE
REPORT "Illegal bin character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 2 + digit;
end loop;
return ivalue;
end BIN_STR_TO_INT;
-- This function converts a octadecimal number to an integer
function OCT_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when others =>
ASSERT FALSE
REPORT "Illegal octadecimal character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 8 + digit;
end loop;
return ivalue;
end OCT_STR_TO_INT;
-- This function converts a integer string to an integer
function INT_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case str(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
-- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto")
function ALPHA_TOLOWER (given_string : in string) return string is
-- VARIABLE DECLARATION
variable result_string : string(given_string'low to given_string'high);
begin
for i in given_string'low to given_string'high loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(given_string'low to given_string'high));
end;
-- This procedure "cuts" the str_line into desired length
procedure SHRINK_LINE (str_line : inout line; pos : in integer) is
subtype nstring is string(1 to pos);
variable str : nstring;
begin
if (pos >= 1) then
read(str_line, str);
end if;
end;
end LPM_COMMON_CONVERSION;
-- END OF PACKAGE
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_HINT_EVALUATION
--
-- Description : Common function to grep the value of altera specific parameters
-- within the lpm_hint parameter.
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_HINT_EVALUATION is
-- FUNCTION DECLARATION
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string;
end LPM_HINT_EVALUATION;
package body LPM_HINT_EVALUATION is
-- This function will search through the string (given string) to look for a match for the
-- a given parameter(compare_param_name). It will return the value for the given parameter.
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string is
variable param_name_left_index : integer := given_string'length;
variable param_name_right_index : integer := given_string'length;
variable param_value_left_index : integer := given_string'length;
variable param_value_right_index : integer := given_string'length;
variable set_right_index : boolean := true;
variable extract_param_value : boolean := true;
variable extract_param_name : boolean := false;
variable param_found : boolean := false;
variable given_string_tmp : string(1 to given_string'length) := given_string;
begin
-- checking every character of the given_string from right to left.
for i in given_string'length downto 1 loop
if (given_string(i) /= ' ') then
if (given_string(i) = '=') then
extract_param_value := false;
extract_param_name := true;
set_right_index := true;
elsif (given_string(i) = ',') then
extract_param_value := true;
extract_param_name := false;
set_right_index := true;
if (compare_param_name = given_string_tmp(param_name_left_index to param_name_right_index)) then
param_found := true; -- the compare_param_name have been found in the given_string
exit;
end if;
else
if (extract_param_value = true) then
if (set_right_index = true) then
param_value_right_index := i;
set_right_index := false;
end if;
param_value_left_index := i;
elsif (extract_param_name = true) then
if (set_right_index = true) then
param_name_right_index := i;
set_right_index := false;
end if;
param_name_left_index := i;
end if;
end if;
end if;
end loop;
-- for the case whether parameter's name is the left most part of the given_string
if (extract_param_name = true) then
if(compare_param_name = given_string_tmp(param_name_left_index to param_name_right_index)) then
param_found := true;
end if;
end if;
if(param_found = true) then
return given_string_tmp(param_value_left_index to param_value_right_index);
else
return ""; -- return empty string if parameter not found
end if;
end get_parameter_value;
end LPM_HINT_EVALUATION;
-- END OF PACKAGE
-- BEGINING OF PACKAGES
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_DEVICE_FAMILIES is
-- FUNCTION DECLARATION
function IS_FAMILY_MAX7000B (device : in string) return boolean;
function IS_FAMILY_MAX7000AE (device : in string) return boolean;
function IS_FAMILY_MAX3000A (device : in string) return boolean;
function IS_FAMILY_MAX7000S (device : in string) return boolean;
function IS_FAMILY_STRATIX (device : in string) return boolean;
function IS_FAMILY_STRATIXGX (device : in string) return boolean;
function IS_FAMILY_CYCLONE (device : in string) return boolean;
function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean;
function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean;
function FEATURE_FAMILY_MAX (device : in string) return boolean;
function IS_VALID_FAMILY (device: in string) return boolean;
end LPM_DEVICE_FAMILIES;
package body LPM_DEVICE_FAMILIES is
function IS_FAMILY_MAX7000B (device : in string) return boolean is
variable is_max7000b : boolean := false;
begin
if ((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b"))
then
is_max7000b := true;
end if;
return is_max7000b;
end IS_FAMILY_MAX7000B;
function IS_FAMILY_MAX7000AE (device : in string) return boolean is
variable is_max7000ae : boolean := false;
begin
if ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae"))
then
is_max7000ae := true;
end if;
return is_max7000ae;
end IS_FAMILY_MAX7000AE;
function IS_FAMILY_MAX3000A (device : in string) return boolean is
variable is_max3000a : boolean := false;
begin
if ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a"))
then
is_max3000a := true;
end if;
return is_max3000a;
end IS_FAMILY_MAX3000A;
function IS_FAMILY_MAX7000S (device : in string) return boolean is
variable is_max7000s : boolean := false;
begin
if ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s"))
then
is_max7000s := true;
end if;
return is_max7000s;
end IS_FAMILY_MAX7000S;
function IS_FAMILY_STRATIX (device : in string) return boolean is
variable is_stratix : boolean := false;
begin
if ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager"))
then
is_stratix := true;
end if;
return is_stratix;
end IS_FAMILY_STRATIX;
function IS_FAMILY_STRATIXGX (device : in string) return boolean is
variable is_stratixgx : boolean := false;
begin
if ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora"))
then
is_stratixgx := true;
end if;
return is_stratixgx;
end IS_FAMILY_STRATIXGX;
function IS_FAMILY_CYCLONE (device : in string) return boolean is
variable is_cyclone : boolean := false;
begin
if ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado"))
then
is_cyclone := true;
end if;
return is_cyclone;
end IS_FAMILY_CYCLONE;
function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean is
variable var_family_base_stratix : boolean := false;
begin
if (IS_FAMILY_STRATIX(device) or IS_FAMILY_STRATIXGX(device) )
then
var_family_base_stratix := true;
end if;
return var_family_base_stratix;
end FEATURE_FAMILY_BASE_STRATIX;
function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean is
variable var_family_base_cyclone : boolean := false;
begin
if (IS_FAMILY_CYCLONE(device) )
then
var_family_base_cyclone := true;
end if;
return var_family_base_cyclone;
end FEATURE_FAMILY_BASE_CYCLONE;
function FEATURE_FAMILY_MAX (device : in string) return boolean is
variable var_family_max : boolean := false;
begin
if ((device = "MAX5000") or IS_FAMILY_MAX3000A(device) or (device = "MAX7000") or (device = "MAX7000A") or IS_FAMILY_MAX7000AE(device) or (device = "MAX7000E") or IS_FAMILY_MAX7000S(device) or IS_FAMILY_MAX7000B(device) or (device = "MAX9000") )
then
var_family_max := true;
end if;
return var_family_max;
end FEATURE_FAMILY_MAX;
function IS_VALID_FAMILY (device : in string) return boolean is
variable is_valid : boolean := false;
begin
if (((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b"))
or ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae"))
or ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a"))
or ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s"))
or ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager"))
or ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora"))
or ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado"))
or ((device = "MAX II") or (device = "max ii") or (device = "MAXII") or (device = "maxii") or (device = "Tsunami") or (device = "TSUNAMI") or (device = "tsunami"))
or ((device = "Stratix II") or (device = "STRATIX II") or (device = "stratix ii") or (device = "StratixII") or (device = "STRATIXII") or (device = "stratixii") or (device = "Armstrong") or (device = "ARMSTRONG") or (device = "armstrong"))
or ((device = "Stratix II GX") or (device = "STRATIX II GX") or (device = "stratix ii gx") or (device = "StratixIIGX") or (device = "STRATIXIIGX") or (device = "stratixiigx"))
or ((device = "Arria GX") or (device = "ARRIA GX") or (device = "arria gx") or (device = "ArriaGX") or (device = "ARRIAGX") or (device = "arriagx") or (device = "Stratix II GX Lite") or (device = "STRATIX II GX LITE") or (device = "stratix ii gx lite") or (device = "StratixIIGXLite") or (device = "STRATIXIIGXLITE") or (device = "stratixiigxlite"))
or ((device = "Cyclone II") or (device = "CYCLONE II") or (device = "cyclone ii") or (device = "Cycloneii") or (device = "CYCLONEII") or (device = "cycloneii") or (device = "Magellan") or (device = "MAGELLAN") or (device = "magellan"))
or ((device = "HardCopy II") or (device = "HARDCOPY II") or (device = "hardcopy ii") or (device = "HardCopyII") or (device = "HARDCOPYII") or (device = "hardcopyii") or (device = "Fusion") or (device = "FUSION") or (device = "fusion"))
or ((device = "Stratix III") or (device = "STRATIX III") or (device = "stratix iii") or (device = "StratixIII") or (device = "STRATIXIII") or (device = "stratixiii") or (device = "Titan") or (device = "TITAN") or (device = "titan") or (device = "SIII") or (device = "siii"))
or ((device = "Cyclone III") or (device = "CYCLONE III") or (device = "cyclone iii") or (device = "CycloneIII") or (device = "CYCLONEIII") or (device = "cycloneiii") or (device = "Barracuda") or (device = "BARRACUDA") or (device = "barracuda") or (device = "Cuda") or (device = "CUDA") or (device = "cuda") or (device = "CIII") or (device = "ciii"))
or ((device = "BS") or (device = "bs"))
or ((device = "Stratix IV") or (device = "STRATIX IV") or (device = "stratix iv") or (device = "TGX") or (device = "tgx") or (device = "StratixIV") or (device = "STRATIXIV") or (device = "stratixiv") or (device = "Stratix IV (GT)") or (device = "STRATIX IV (GT)") or (device = "stratix iv (gt)") or (device = "Stratix IV (GX)") or (device = "STRATIX IV (GX)") or (device = "stratix iv (gx)") or (device = "Stratix IV (E)") or (device = "STRATIX IV (E)") or (device = "stratix iv (e)") or (device = "StratixIV(GT)") or (device = "STRATIXIV(GT)") or (device = "stratixiv(gt)") or (device = "StratixIV(GX)") or (device = "STRATIXIV(GX)") or (device = "stratixiv(gx)") or (device = "StratixIV(E)") or (device = "STRATIXIV(E)") or (device = "stratixiv(e)") or (device = "StratixIIIGX") or (device = "STRATIXIIIGX") or (device = "stratixiiigx") or (device = "Stratix IV (GT/GX/E)") or (device = "STRATIX IV (GT/GX/E)") or (device = "stratix iv (gt/gx/e)") or (device = "Stratix IV (GT/E/GX)") or (device = "STRATIX IV (GT/E/GX)") or (device = "stratix iv (gt/e/gx)") or (device = "Stratix IV (E/GT/GX)") or (device = "STRATIX IV (E/GT/GX)") or (device = "stratix iv (e/gt/gx)") or (device = "Stratix IV (E/GX/GT)") or (device = "STRATIX IV (E/GX/GT)") or (device = "stratix iv (e/gx/gt)") or (device = "StratixIV(GT/GX/E)") or (device = "STRATIXIV(GT/GX/E)") or (device = "stratixiv(gt/gx/e)") or (device = "StratixIV(GT/E/GX)") or (device = "STRATIXIV(GT/E/GX)") or (device = "stratixiv(gt/e/gx)") or (device = "StratixIV(E/GX/GT)") or (device = "STRATIXIV(E/GX/GT)") or (device = "stratixiv(e/gx/gt)") or (device = "StratixIV(E/GT/GX)") or (device = "STRATIXIV(E/GT/GX)") or (device = "stratixiv(e/gt/gx)") or (device = "Stratix IV (GX/E)") or (device = "STRATIX IV (GX/E)") or (device = "stratix iv (gx/e)") or (device = "StratixIV(GX/E)") or (device = "STRATIXIV(GX/E)") or (device = "stratixiv(gx/e)"))
or ((device = "tgx_commercial_v1_1") or (device = "TGX_COMMERCIAL_V1_1"))
or ((device = "Arria II GX") or (device = "ARRIA II GX") or (device = "arria ii gx") or (device = "ArriaIIGX") or (device = "ARRIAIIGX") or (device = "arriaiigx") or (device = "Arria IIGX") or (device = "ARRIA IIGX") or (device = "arria iigx") or (device = "ArriaII GX") or (device = "ARRIAII GX") or (device = "arriaii gx") or (device = "Arria II") or (device = "ARRIA II") or (device = "arria ii") or (device = "ArriaII") or (device = "ARRIAII") or (device = "arriaii") or (device = "Arria II (GX/E)") or (device = "ARRIA II (GX/E)") or (device = "arria ii (gx/e)") or (device = "ArriaII(GX/E)") or (device = "ARRIAII(GX/E)") or (device = "arriaii(gx/e)") or (device = "PIRANHA") or (device = "piranha"))
or ((device = "HardCopy III") or (device = "HARDCOPY III") or (device = "hardcopy iii") or (device = "HardCopyIII") or (device = "HARDCOPYIII") or (device = "hardcopyiii") or (device = "HCX") or (device = "hcx"))
or ((device = "HardCopy IV") or (device = "HARDCOPY IV") or (device = "hardcopy iv") or (device = "HardCopyIV") or (device = "HARDCOPYIV") or (device = "hardcopyiv") or (device = "HardCopy IV (GX)") or (device = "HARDCOPY IV (GX)") or (device = "hardcopy iv (gx)") or (device = "HardCopy IV (E)") or (device = "HARDCOPY IV (E)") or (device = "hardcopy iv (e)") or (device = "HardCopyIV(GX)") or (device = "HARDCOPYIV(GX)") or (device = "hardcopyiv(gx)") or (device = "HardCopyIV(E)") or (device = "HARDCOPYIV(E)") or (device = "hardcopyiv(e)") or (device = "HCXIV") or (device = "hcxiv") or (device = "HardCopy IV (GX/E)") or (device = "HARDCOPY IV (GX/E)") or (device = "hardcopy iv (gx/e)") or (device = "HardCopy IV (E/GX)") or (device = "HARDCOPY IV (E/GX)") or (device = "hardcopy iv (e/gx)") or (device = "HardCopyIV(GX/E)") or (device = "HARDCOPYIV(GX/E)") or (device = "hardcopyiv(gx/e)") or (device = "HardCopyIV(E/GX)") or (device = "HARDCOPYIV(E/GX)") or (device = "hardcopyiv(e/gx)"))
or ((device = "Cyclone III LS") or (device = "CYCLONE III LS") or (device = "cyclone iii ls") or (device = "CycloneIIILS") or (device = "CYCLONEIIILS") or (device = "cycloneiiils") or (device = "Cyclone III LPS") or (device = "CYCLONE III LPS") or (device = "cyclone iii lps") or (device = "Cyclone LPS") or (device = "CYCLONE LPS") or (device = "cyclone lps") or (device = "CycloneLPS") or (device = "CYCLONELPS") or (device = "cyclonelps") or (device = "Tarpon") or (device = "TARPON") or (device = "tarpon") or (device = "Cyclone IIIE") or (device = "CYCLONE IIIE") or (device = "cyclone iiie"))
or ((device = "Cyclone IV GX") or (device = "CYCLONE IV GX") or (device = "cyclone iv gx") or (device = "Cyclone IVGX") or (device = "CYCLONE IVGX") or (device = "cyclone ivgx") or (device = "CycloneIV GX") or (device = "CYCLONEIV GX") or (device = "cycloneiv gx") or (device = "CycloneIVGX") or (device = "CYCLONEIVGX") or (device = "cycloneivgx") or (device = "Cyclone IV") or (device = "CYCLONE IV") or (device = "cyclone iv") or (device = "CycloneIV") or (device = "CYCLONEIV") or (device = "cycloneiv") or (device = "Cyclone IV (GX)") or (device = "CYCLONE IV (GX)") or (device = "cyclone iv (gx)") or (device = "CycloneIV(GX)") or (device = "CYCLONEIV(GX)") or (device = "cycloneiv(gx)") or (device = "Cyclone III GX") or (device = "CYCLONE III GX") or (device = "cyclone iii gx") or (device = "CycloneIII GX") or (device = "CYCLONEIII GX") or (device = "cycloneiii gx") or (device = "Cyclone IIIGX") or (device = "CYCLONE IIIGX") or (device = "cyclone iiigx") or (device = "CycloneIIIGX") or (device = "CYCLONEIIIGX") or (device = "cycloneiiigx") or (device = "Cyclone III GL") or (device = "CYCLONE III GL") or (device = "cyclone iii gl") or (device = "CycloneIII GL") or (device = "CYCLONEIII GL") or (device = "cycloneiii gl") or (device = "Cyclone IIIGL") or (device = "CYCLONE IIIGL") or (device = "cyclone iiigl") or (device = "CycloneIIIGL") or (device = "CYCLONEIIIGL") or (device = "cycloneiiigl") or (device = "Stingray") or (device = "STINGRAY") or (device = "stingray"))
or ((device = "Cyclone IV E") or (device = "CYCLONE IV E") or (device = "cyclone iv e") or (device = "CycloneIV E") or (device = "CYCLONEIV E") or (device = "cycloneiv e") or (device = "Cyclone IVE") or (device = "CYCLONE IVE") or (device = "cyclone ive") or (device = "CycloneIVE") or (device = "CYCLONEIVE") or (device = "cycloneive"))
or ((device = "Stratix V") or (device = "STRATIX V") or (device = "stratix v") or (device = "StratixV") or (device = "STRATIXV") or (device = "stratixv") or (device = "Stratix V (GS)") or (device = "STRATIX V (GS)") or (device = "stratix v (gs)") or (device = "StratixV(GS)") or (device = "STRATIXV(GS)") or (device = "stratixv(gs)") or (device = "Stratix V (GT)") or (device = "STRATIX V (GT)") or (device = "stratix v (gt)") or (device = "StratixV(GT)") or (device = "STRATIXV(GT)") or (device = "stratixv(gt)") or (device = "Stratix V (GX)") or (device = "STRATIX V (GX)") or (device = "stratix v (gx)") or (device = "StratixV(GX)") or (device = "STRATIXV(GX)") or (device = "stratixv(gx)") or (device = "Stratix V (GS/GX)") or (device = "STRATIX V (GS/GX)") or (device = "stratix v (gs/gx)") or (device = "StratixV(GS/GX)") or (device = "STRATIXV(GS/GX)") or (device = "stratixv(gs/gx)") or (device = "Stratix V (GS/GT)") or (device = "STRATIX V (GS/GT)") or (device = "stratix v (gs/gt)") or (device = "StratixV(GS/GT)") or (device = "STRATIXV(GS/GT)") or (device = "stratixv(gs/gt)") or (device = "Stratix V (GT/GX)") or (device = "STRATIX V (GT/GX)") or (device = "stratix v (gt/gx)") or (device = "StratixV(GT/GX)") or (device = "STRATIXV(GT/GX)") or (device = "stratixv(gt/gx)") or (device = "Stratix V (GX/GS)") or (device = "STRATIX V (GX/GS)") or (device = "stratix v (gx/gs)") or (device = "StratixV(GX/GS)") or (device = "STRATIXV(GX/GS)") or (device = "stratixv(gx/gs)") or (device = "Stratix V (GT/GS)") or (device = "STRATIX V (GT/GS)") or (device = "stratix v (gt/gs)") or (device = "StratixV(GT/GS)") or (device = "STRATIXV(GT/GS)") or (device = "stratixv(gt/gs)") or (device = "Stratix V (GX/GT)") or (device = "STRATIX V (GX/GT)") or (device = "stratix v (gx/gt)") or (device = "StratixV(GX/GT)") or (device = "STRATIXV(GX/GT)") or (device = "stratixv(gx/gt)") or (device = "Stratix V (GS/GT/GX)") or (device = "STRATIX V (GS/GT/GX)") or (device = "stratix v (gs/gt/gx)") or (device = "Stratix V (GS/GX/GT)") or (device = "STRATIX V (GS/GX/GT)") or (device = "stratix v (gs/gx/gt)") or (device = "Stratix V (GT/GS/GX)") or (device = "STRATIX V (GT/GS/GX)") or (device = "stratix v (gt/gs/gx)") or (device = "Stratix V (GT/GX/GS)") or (device = "STRATIX V (GT/GX/GS)") or (device = "stratix v (gt/gx/gs)") or (device = "Stratix V (GX/GS/GT)") or (device = "STRATIX V (GX/GS/GT)") or (device = "stratix v (gx/gs/gt)") or (device = "Stratix V (GX/GT/GS)") or (device = "STRATIX V (GX/GT/GS)") or (device = "stratix v (gx/gt/gs)") or (device = "StratixV(GS/GT/GX)") or (device = "STRATIXV(GS/GT/GX)") or (device = "stratixv(gs/gt/gx)") or (device = "StratixV(GS/GX/GT)") or (device = "STRATIXV(GS/GX/GT)") or (device = "stratixv(gs/gx/gt)") or (device = "StratixV(GT/GS/GX)") or (device = "STRATIXV(GT/GS/GX)") or (device = "stratixv(gt/gs/gx)") or (device = "StratixV(GT/GX/GS)") or (device = "STRATIXV(GT/GX/GS)") or (device = "stratixv(gt/gx/gs)") or (device = "StratixV(GX/GS/GT)") or (device = "STRATIXV(GX/GS/GT)") or (device = "stratixv(gx/gs/gt)") or (device = "StratixV(GX/GT/GS)") or (device = "STRATIXV(GX/GT/GS)") or (device = "stratixv(gx/gt/gs)"))
or ((device = "Arria II GZ") or (device = "ARRIA II GZ") or (device = "arria ii gz") or (device = "ArriaII GZ") or (device = "ARRIAII GZ") or (device = "arriaii gz") or (device = "Arria IIGZ") or (device = "ARRIA IIGZ") or (device = "arria iigz") or (device = "ArriaIIGZ") or (device = "ARRIAIIGZ") or (device = "arriaiigz"))
or ((device = "arriaiigz_commercial_v1_1") or (device = "ARRIAIIGZ_COMMERCIAL_V1_1"))
or ((device = "MAX V") or (device = "max v") or (device = "MAXV") or (device = "maxv") or (device = "Jade") or (device = "JADE") or (device = "jade"))
or ((device = "Arria V") or (device = "ARRIA V") or (device = "arria v") or (device = "ArriaV") or (device = "ARRIAV") or (device = "arriav")))
then
is_valid := true;
end if;
return is_valid;
end IS_VALID_FAMILY;
end LPM_DEVICE_FAMILIES;
-- END OF PACKAGE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_constant
--
-- Description : Parameterized constant generator megafunction. lpm_constant
-- may be useful for convert a parameter into a constant.
--
-- Limitation : n/a
--
-- results Expected: Value specified by the argument to lpm_cvalue.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CONSTANT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the result[] port. (Required)
lpm_cvalue : natural; -- Constant value to be driven out on the
-- result[] port. (Required)
lpm_strength : string := "UNUSED";
lpm_type : string := "LPM_CONSTANT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- // Value specified by the argument to lpm_cvalue. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_CONSTANT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CONSTANT is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= conv_std_logic_vector(lpm_cvalue, lpm_width);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inv
--
-- Description : Parameterized inverter megafunction.
--
-- Limitation : n/a
--
-- results Expected: Inverted value of input data.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_INV is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INV";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INV;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INV is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= not data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_and
--
-- Description : Parameterized AND gate. This megafunction takes in data inputs
-- for a number of AND gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each AND gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_and is
generic (
-- Width of the data[][] and result[] ports. Number of AND gates. (Required)
lpm_width : natural;
-- Number of inputs to each AND gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_AND";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the AND gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of the AND operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end lpm_and;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_and is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process; -- MSG process
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) and data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_or
--
-- Description : Parameterized OR gate megafunction. This megafunction takes in
-- data inputs for a number of OR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each OR gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_OR is
generic (
-- Width of the data[] and result[] ports. Number of OR gates. (Required)
lpm_width : natural;
-- Number of inputs to each OR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_OR";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the OR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of OR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0));
end LPM_OR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) or data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_xor
--
-- Description : Parameterized XOR gate megafunction. This megafunction takes in
-- data inputs for a number of XOR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each XOR gates.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_XOR is
generic (
-- Width of the data[] and result[] ports. Number of XOR gates. (Required)
lpm_width : natural;
-- Number of inputs to each XOR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_XOR";
lpm_hint : string := "UNUSED");
port (
-- data input to the XOR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- result of XOR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_XOR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_XOR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) xor data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_bustri
--
-- Description : Parameterized tri-state buffer. lpm_bustri is useful for
-- controlling both unidirectional and bidirectional I/O bus
-- controllers.
--
-- Limitation : n/a
--
-- results Expected: Belows are the three configurations which are valid:
--
-- 1) Only the input ports data[lpm_width-1..0] and enabledt are
-- present, and only the output ports tridata[lpm_width-1..0]
-- are present.
--
-- ----------------------------------------------------
-- | Input | Output |
-- |====================================================|
-- | enabledt | tridata[lpm_width-1..0] |
-- |----------------------------------------------------|
-- | 0 | Z |
-- |----------------------------------------------------|
-- | 1 | data[lpm_width-1..0] |
-- ----------------------------------------------------
--
-- 2) Only the input ports tridata[lpm_width-1..0] and enabletr
-- are present, and only the output ports result[lpm_width-1..0]
-- are present.
--
-- ----------------------------------------------------
-- | Input | Output |
-- |====================================================|
-- | enabletr | result[lpm_width-1..0] |
-- |----------------------------------------------------|
-- | 0 | Z |
-- |----------------------------------------------------|
-- | 1 | tridata[lpm_width-1..0] |
-- ----------------------------------------------------
--
-- 3) All ports are present: input ports data[lpm_width-1..0],
-- enabledt, and enabletr; output ports result[lpm_width-1..0];
-- and bidirectional ports tridata[lpm_width-1..0].
--
-- ----------------------------------------------------------------------------
-- | Input | Bidirectional | Output |
-- |----------------------------------------------------------------------------|
-- | enabledt | enabletr | tridata[lpm_width-1..0] | result[lpm_width-1..0] |
-- |============================================================================|
-- | 0 | 0 | Z (input) | Z |
-- |----------------------------------------------------------------------------|
-- | 0 | 1 | Z (input) | tridata[lpm_width-1..0] |
-- |----------------------------------------------------------------------------|
-- | 1 | 0 | data[lpm_width-1..0] | Z |
-- |----------------------------------------------------------------------------|
-- | 1 | 1 | data[lpm_width-1..0] | data[lpm_width-1..0] |
-- ----------------------------------------------------------------------------
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_BUSTRI is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0 (Required)
lpm_type : string := "LPM_BUSTRI";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Bidirectional bus signal. (Required)
tridata : inout std_logic_vector(lpm_width-1 downto 0);
-- Data input to the tridata[] bus. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- If high, enables tridata[] onto the result bus.
enabletr : in std_logic := '1';
-- If high, enables data onto the tridata[] bus.
enabledt : in std_logic := '1';
-- Output from the tridata[] bus.
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_BUSTRI;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_BUSTRI is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- get the tri-state buffer output
BUSTRI: process(data, tridata, enabletr, enabledt)
begin
if enabledt = '0' and enabletr = '1' then
result <= tridata;
elsif enabledt = '1' and enabletr = '0' then
result <= (OTHERS => 'Z');
elsif enabledt = '1' and enabletr = '1' then
result <= data;
else
result <= (OTHERS => 'Z');
end if;
end process BUSTRI;
-- SIGNAL ASSIGNMENT
tridata <= data when (enabledt = '1')
else (OTHERS => 'Z');
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_mux
--
-- Description : Parameterized multiplexer megafunctions.
--
-- Limitation : n/a
--
-- results Expected: Selected input port.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_MUX is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[][] and result[] ports. (Required)
lpm_size : natural; -- Number of input buses to the multiplexer. (Required)
lpm_widths : natural; -- Width of the sel[] input port. (Required)
lpm_pipeline : natural := 0;-- Specifies the number of Clock cycles of latency
-- associated with the result[] output.
lpm_type : string := "LPM_MUX";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Data input. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Selects one of the input buses. (Required)
sel : in std_logic_vector(lpm_widths-1 downto 0);
-- Clock for pipelined usage
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Selected input port. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_MUX;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_MUX is
-- TYPE DECLARATION
type t_resulttmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 1) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 1!"
SEVERITY ERROR;
end if;
if (lpm_widths <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widths parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (aclr, clock, sel, data, clken)
variable resulttmp : t_resulttmp;
variable sel_int : integer;
begin
if (lpm_pipeline >= 0) then
sel_int := conv_integer(sel);
for i in 0 to lpm_width-1 loop
if (sel_int < lpm_size) then
resulttmp(lpm_pipeline)(i) := data(sel_int,i);
else
resulttmp(lpm_pipeline)(i) := 'X';
end if;
end loop;
if (lpm_pipeline > 0) then
if (aclr = '1') then
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif (rising_edge(clock) and clken = '1') then
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
result <= resulttmp(0);
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_decode
--
-- Description : Parameterized decoder megafunction.
--
-- Limitation : n/a
--
-- Results Expected: Decoded output.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_DECODE is
generic (
-- Width of the data[] port, or the input value to be decoded. (Required)
lpm_width : natural;
-- Number of explicit decoder outputs. (Required)
lpm_decodes : natural;
-- Number of Clock cycles of latency
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_DECODE";
lpm_hint : string := "UNUSED"
);
port (
-- Data input. Treated as an unsigned binary encoded number. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Enable. All outputs low when not active.
enable : in std_logic := '1';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Decoded output. (Required)
eq : out std_logic_vector(lpm_decodes-1 downto 0)
);
end LPM_DECODE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_DECODE is
-- TYPE DECLARATION
type t_eqtmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_decodes-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_decodes <= 0) then
ASSERT FALSE
REPORT "Value of lpm_decodes parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_decodes > (2**lpm_width)) then
ASSERT FALSE
REPORT "Value of lpm_decodes parameter must be less or equal to 2^lpm_width!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, data, enable)
variable eqtmp : t_eqtmp;
begin
for i in 0 to lpm_decodes-1 loop
if (conv_integer(data) = i) then
if (enable = '1') then
eqtmp(lpm_pipeline)(i) := '1';
else
eqtmp(lpm_pipeline)(i) := '0';
end if;
else
eqtmp(lpm_pipeline)(i) := '0';
end if;
end loop;
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
eqtmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
eqtmp(0 to lpm_pipeline - 1) := eqtmp(1 to lpm_pipeline);
end if;
end if;
eq <= eqtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_clshift
--
-- Description : Parameterized combinatorial logic shifter or barrel shifter
-- megafunction.
--
-- Limitation : n/a
--
-- results Expected: Return the shifted data and underflow/overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CLSHIFT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[] and result[] ports.
-- MUST be greater than 0 (Required)
lpm_widthdist : natural; -- Width of the distance[] input port.
-- MUST be greater than 0 (Required)
lpm_shifttype : string := "LOGICAL"; -- Type of shifting operation to be performed.
lpm_pipeline : natural := 0; -- Number of Clock cycles of latency.
lpm_type : string := "LPM_CLSHIFT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- data to be shifted. (Required)
data : in STD_LOGIC_VECTOR(lpm_width-1 downto 0);
-- Number of positions to shift data[] in the direction specified by the
-- direction port. (Required)
distance : in STD_LOGIC_VECTOR(lpm_widthdist-1 downto 0);
-- direction of shift. Low = left (toward the MSB), high = right (toward the LSB).
direction : in STD_LOGIC := '0';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Shifted data. (Required)
result : out STD_LOGIC_VECTOR(lpm_width-1 downto 0);
-- Logical or arithmetic underflow.
underflow : out STD_LOGIC;
-- Logical or arithmetic overflow.
overflow : out STD_LOGIC
);
end LPM_CLSHIFT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CLSHIFT is
-- TYPE DECLARATION
type t_resulttmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal i_result : std_logic_vector(lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthdist <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthdist parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- Get the shifted data
process(data, distance, direction)
variable tmpdata : std_logic_vector(lpm_width-1 downto 0);
variable tmpdist : integer;
begin
if ((lpm_shifttype = "ARITHMETIC") or (lpm_shifttype = "LOGICAL")) then
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(unsigned(distance));
for i in lpm_width-1 downto 0 loop
if (direction = '0') then
if (i >= tmpdist) then
i_result(i) <= tmpdata(i-tmpdist);
else
i_result(i) <= '0';
end if;
elsif (direction = '1') then
if ((i+tmpdist) < lpm_width) then
i_result(i) <= tmpdata(i+tmpdist);
elsif (lpm_shifttype = "ARITHMETIC") then
i_result(i) <= data(lpm_width-1);
else
i_result(i) <= '0';
end if;
end if;
end loop;
elsif (lpm_shifttype = "ROTATE") then
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(unsigned(distance)) mod lpm_width;
for i in lpm_width-1 downto 0 loop
if (direction = '0') then
if (i >= tmpdist) then
i_result(i) <= tmpdata(i-tmpdist);
else
i_result(i) <= tmpdata(i+lpm_width-tmpdist);
end if;
elsif (direction = '1') then
if (i+tmpdist < lpm_width) then
i_result(i) <= tmpdata(i+tmpdist);
else
i_result(i) <= tmpdata(i-lpm_width+tmpdist);
end if;
end if;
end loop;
else
ASSERT FALSE
REPORT "Illegal lpm_shifttype property value for LPM_CLSHIFT!"
SEVERITY ERROR;
end if;
end process;
-- Get the overflow/underflow status bit.
process(aclr, clock, data, distance, direction, i_result)
variable neg_one : signed(lpm_width-1 downto 0) := (OTHERS => '1');
variable tmpdata : std_logic_vector(lpm_width-1 downto 0);
variable tmpdist : integer;
variable msb_cnt : integer := 0;
variable lsb_cnt : integer := 0;
variable sgn_bit : std_logic;
variable result_pipe : t_resulttmp := (OTHERS => (OTHERS => '0'));
variable overflow_pipe : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable underflow_pipe : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
begin
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(distance);
result_pipe(lpm_pipeline) := i_result;
overflow_pipe(lpm_pipeline) := '0';
underflow_pipe(lpm_pipeline) := '0';
if ((tmpdist /= 0) and (tmpdata /= 0)) then
if (lpm_shifttype = "ROTATE") then
overflow_pipe(lpm_pipeline) := 'U';
underflow_pipe(lpm_pipeline) := 'U';
else
if (tmpdist < lpm_width) then
if (lpm_shifttype = "LOGICAL") then
msb_cnt := 0;
while ((msb_cnt < lpm_width) and
(tmpdata(lpm_width-msb_cnt-1) = '0')) loop
msb_cnt := msb_cnt + 1;
end loop;
if ((tmpdist > msb_cnt) and (direction = '0')) then
overflow_pipe(lpm_pipeline) := '1';
elsif ((tmpdist + msb_cnt >= lpm_width) and (direction = '1')) then
underflow_pipe(lpm_pipeline) := '1';
end if;
elsif (lpm_shifttype = "ARITHMETIC") then
sgn_bit := '0';
if (tmpdata(lpm_width-1) = '1') then
sgn_bit := '1';
end if;
msb_cnt := 0;
while ((msb_cnt < lpm_width) and
(tmpdata(lpm_width-msb_cnt-1) = sgn_bit)) loop
msb_cnt := msb_cnt + 1;
end loop;
lsb_cnt := 0;
while ((lsb_cnt < lpm_width) and (tmpdata(lsb_cnt) = '0')) loop
lsb_cnt := lsb_cnt + 1;
end loop;
if (direction = '1') then -- shift right
if (tmpdata(lpm_width-1) = '1') then -- negative
if ((msb_cnt + tmpdist >= lpm_width) and
(msb_cnt /= lpm_width)) then
underflow_pipe(lpm_pipeline) := '1';
end if;
else -- non-neg
if (((msb_cnt + tmpdist) >= lpm_width) and
(msb_cnt /= lpm_width)) then
underflow_pipe(lpm_pipeline) := '1';
end if;
end if;
elsif (direction = '0') then -- shift left
if (tmpdata(lpm_width-1) = '1') then -- negative
if (((signed(tmpdata) /= neg_one) and
(tmpdist >= lpm_width)) or (tmpdist >= msb_cnt)) then
overflow_pipe(lpm_pipeline) := '1';
end if;
else -- non-neg
if (((tmpdata /= 0) and (tmpdist >= lpm_width-1)) or
(tmpdist >= msb_cnt)) then
overflow_pipe(lpm_pipeline) := '1';
end if;
end if;
end if;
end if;
else
if (direction = '0') then
overflow_pipe(lpm_pipeline) := '1';
elsif (direction = '1') then
underflow_pipe(lpm_pipeline) := '1';
end if;
end if; -- tmpdist < lpm_width
end if; -- lpm_shifttype = "ROTATE"
end if; -- tmpdist /= 0 and tmpdata /= 0
if (aclr = '1') then
if (lpm_pipeline > 0) then
result_pipe := (OTHERS => (OTHERS => '0'));
overflow_pipe := (OTHERS => '0');
underflow_pipe := (OTHERS => '0');
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
result_pipe(0 to lpm_pipeline - 1) := result_pipe(1 to lpm_pipeline);
overflow_pipe(0 to lpm_pipeline - 1) := overflow_pipe(1 to lpm_pipeline);
underflow_pipe(0 to lpm_pipeline - 1) := underflow_pipe(1 to lpm_pipeline);
end if;
end if;
result <= result_pipe(0);
overflow <= overflow_pipe(0);
underflow <= underflow_pipe(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub_signed
--
-- Description : This entity is instiatiated by lpm_add_sub megafunction to perform
-- adder/subtrator function for signed number.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_ADD_SUB_SIGNED is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width downto 1);
datab : in std_logic_vector(lpm_width downto 1);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB_SIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB_SIGNED is
-- SIGNAL DECLARATION
signal i_dataa, i_datab : std_logic_vector(lpm_width downto 0);
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width downto 0);
begin
i_dataa <= (dataa(lpm_width) & dataa);
i_datab <= (datab(lpm_width) & datab);
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, i_dataa, i_datab, cin, add_sub)
variable resulttmp : T_RESULTTMP := (OTHERS => (OTHERS => '0'));
variable couttmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable overflowtmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable i_cin : std_logic;
begin
if ((lpm_direction = "ADD") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT"))and (add_sub = '1'))) then
if (cin = 'Z') then
i_cin := '0';
else
i_cin := cin;
end if;
-- Perform as adder
resulttmp(lpm_pipeline) := i_dataa + i_datab + i_cin;
couttmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width) xor
i_dataa(lpm_width) xor
i_datab(lpm_width);
if ((i_dataa(lpm_width) = '0') and (i_datab(lpm_width) = '0') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '1')) or
((i_dataa(lpm_width) = '1') and (i_datab(lpm_width) = '1') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '0')) then
overflowtmp(lpm_pipeline) := '1';
else
overflowtmp(lpm_pipeline) := '0';
end if;
elsif ((lpm_direction = "SUB") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '0'))) then
if (cin = 'Z') then
i_cin := '1';
else
i_cin := cin;
end if;
-- Perform as subtrator
resulttmp(lpm_pipeline) := i_dataa - i_datab + i_cin - 1;
couttmp(lpm_pipeline) := (not resulttmp(lpm_pipeline)(lpm_width)) xor
i_dataa(lpm_width) xor
i_datab(lpm_width);
if ((i_dataa(lpm_width) = '0') and (i_datab(lpm_width) = '1') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '1')) or
((i_dataa(lpm_width) = '1') and (i_datab(lpm_width) = '0') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '0')) then
overflowtmp(lpm_pipeline) := '1';
else
overflowtmp(lpm_pipeline) := '0';
end if;
elsif ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_ADD_SUB!"
SEVERITY ERROR;
end if;
-- Pipeline the result
if (aclr = '1') then
if (lpm_pipeline > 0) then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
overflowtmp(0 to lpm_pipeline - 1) := overflowtmp(1 to lpm_pipeline);
couttmp(0 to lpm_pipeline - 1) := couttmp(1 to lpm_pipeline);
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
-- send the pipeline result to output ports
cout <= couttmp(0);
overflow <= overflowtmp(0);
result <= resulttmp(0)(lpm_width-1 downto 0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub_unsigned
--
-- Description : This entity is instiatiated by lpm_add_sub megafunction to perform
-- adder/subtrator function for unsigned number.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_ADD_SUB_UNSIGNED is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB_UNSIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB_UNSIGNED is
-- SIGNAL DECLARATION
signal i_dataa, i_datab : std_logic_vector(lpm_width downto 0);
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width downto 0);
begin
i_dataa <= ('0' & dataa);
i_datab <= ('0' & datab);
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, i_dataa, i_datab, cin, add_sub)
variable resulttmp : T_RESULTTMP := (OTHERS => (OTHERS => '0'));
variable couttmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable overflowtmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable i_cin : std_logic;
begin
if ((lpm_direction = "ADD") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '1'))) then
if (cin = 'Z') then
i_cin := '0';
else
i_cin := cin;
end if;
-- Perform as adder
resulttmp(lpm_pipeline) := i_dataa + i_datab + i_cin;
couttmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width);
elsif ((lpm_direction = "SUB") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '0'))) then
if (cin = 'Z') then
i_cin := '1';
else
i_cin := cin;
end if;
-- Perform as subtractor
resulttmp(lpm_pipeline) := i_dataa - i_datab + i_cin - 1;
couttmp(lpm_pipeline) := not resulttmp(lpm_pipeline)(lpm_width);
elsif ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_ADD_SUB!"
SEVERITY ERROR;
end if;
overflowtmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width);
-- Pipeline the result
if (aclr = '1') then
if (lpm_pipeline > 0) then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1') ) then
if ((clken = '1') and (lpm_pipeline > 0)) then
overflowtmp(0 to lpm_pipeline - 1) := overflowtmp(1 to lpm_pipeline);
couttmp(0 to lpm_pipeline - 1) := couttmp(1 to lpm_pipeline);
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
-- Send the pipelined result to output ports
cout <= couttmp(0);
overflow <= overflowtmp(0);
result <= resulttmp(0)(lpm_width-1 downto 0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub
--
-- Description : Parameterized adder/subtractor megafunction.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
use work.LPM_ADD_SUB_SIGNED;
use work.LPM_ADD_SUB_UNSIGNED;
-- ENTITY DECLARATION
entity LPM_ADD_SUB is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_representation : string := "SIGNED";
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB is
-- COMPONENT DECLARATION
component LPM_ADD_SUB_SIGNED
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width downto 1);
datab : in std_logic_vector(lpm_width downto 1);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end component;
component LPM_ADD_SUB_UNSIGNED
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end component;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if ((lpm_representation /= "SIGNED") and
(lpm_representation /= "UNSIGNED")) then
ASSERT FALSE
REPORT "Value of lpm_representation parameter must be SIGNED or UNSIGNED!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: if (lpm_representation = "UNSIGNED") generate
U: LPM_ADD_SUB_UNSIGNED
generic map (
lpm_width => lpm_width,
lpm_direction => lpm_direction,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
cin => cin,
add_sub => add_sub,
clock => clock,
aclr => aclr,
clken => clken,
result => result,
cout => cout,
overflow => overflow
);
end generate;
L2: if (lpm_representation = "SIGNED") generate
V: LPM_ADD_SUB_SIGNED
generic map (
lpm_width => lpm_width,
lpm_direction => lpm_direction,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
cin => cin,
add_sub => add_sub,
clock => clock,
aclr => aclr,
clken => clken,
result => result,
cout => cout,
overflow => overflow
);
end generate;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare_signed
--
-- Description : This module is used in lpm_compare megafunction when
-- type of comparison is "SIGNED".
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_COMPARE_SIGNED is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE_SIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE_SIGNED is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must NOT less than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- perform the data comparison
process(aclr, clock, dataa, datab)
variable agbtmp : std_logic_vector (0 to lpm_pipeline);
variable agebtmp : std_logic_vector (0 to lpm_pipeline);
variable aebtmp : std_logic_vector (0 to lpm_pipeline);
variable anebtmp : std_logic_vector (0 to lpm_pipeline);
variable albtmp : std_logic_vector (0 to lpm_pipeline);
variable alebtmp : std_logic_vector (0 to lpm_pipeline);
begin
-- get the status of comparation
if (signed(dataa) > signed(datab)) then
agbtmp(lpm_pipeline) := '1';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '0';
elsif (signed(dataa) = signed(datab)) then
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '0';
aebtmp(lpm_pipeline) := '1';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '1';
else
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '0';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '1';
alebtmp(lpm_pipeline) := '1';
end if;
-- if lpm_pipine > 0, then create latency on the output result
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
agbtmp(0 to lpm_pipeline-1) := agbtmp(1 to lpm_pipeline);
agebtmp(0 to lpm_pipeline-1) := agebtmp(1 to lpm_pipeline) ;
anebtmp(0 to lpm_pipeline-1) := anebtmp(1 to lpm_pipeline);
aebtmp(0 to lpm_pipeline-1) := aebtmp(1 to lpm_pipeline);
albtmp(0 to lpm_pipeline-1) := albtmp(1 to lpm_pipeline);
alebtmp(0 to lpm_pipeline-1) := alebtmp(1 to lpm_pipeline);
end if;
end if;
agb <= agbtmp(0);
ageb <= agebtmp(0);
aneb <= anebtmp(0);
aeb <= aebtmp(0);
alb <= albtmp(0);
aleb <= alebtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare_unsigned
--
-- Description : This module is used in lpm_compare megafunction when
-- type of comparison is "UNSIGNED".
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_COMPARE_UNSIGNED is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE_UNSIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE_UNSIGNED is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must NOT less than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- perform the data comparison
process(aclr, clock, dataa, datab)
variable agbtmp : std_logic_vector (0 to lpm_pipeline);
variable agebtmp : std_logic_vector (0 to lpm_pipeline);
variable aebtmp : std_logic_vector (0 to lpm_pipeline);
variable anebtmp : std_logic_vector (0 to lpm_pipeline);
variable albtmp : std_logic_vector (0 to lpm_pipeline);
variable alebtmp : std_logic_vector (0 to lpm_pipeline);
begin
-- get the status of comparation
if (unsigned(dataa) > unsigned(datab)) then
agbtmp(lpm_pipeline) := '1';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '0';
elsif (unsigned(dataa) = unsigned(datab)) then
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '0';
aebtmp(lpm_pipeline) := '1';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '1';
else
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '0';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '1';
alebtmp(lpm_pipeline) := '1';
end if;
-- if lpm_pipine > 0, then create latency on the output result
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
agbtmp(0 to lpm_pipeline-1) := agbtmp(1 to lpm_pipeline);
agebtmp(0 to lpm_pipeline-1) := agebtmp(1 to lpm_pipeline) ;
anebtmp(0 to lpm_pipeline-1) := anebtmp(1 to lpm_pipeline);
aebtmp(0 to lpm_pipeline-1) := aebtmp(1 to lpm_pipeline);
albtmp(0 to lpm_pipeline-1) := albtmp(1 to lpm_pipeline);
alebtmp(0 to lpm_pipeline-1) := alebtmp(1 to lpm_pipeline);
end if;
end if;
agb <= agbtmp(0);
ageb <= agebtmp(0);
aneb <= anebtmp(0);
aeb <= aebtmp(0);
alb <= albtmp(0);
aleb <= alebtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare
--
-- Description : Parameterized comparator megafunction. The comparator will
-- compare between data[] and datab[] and return the status of
-- comparation for the following operation.
-- 1) dataa[] < datab[].
-- 2) dataa[] == datab[].
-- 3) dataa[] > datab[].
-- 4) dataa[] >= datab[].
-- 5) dataa[] != datab[].
-- 6) dataa[] <= datab[].
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMPARE_SIGNED;
use work.LPM_COMPARE_UNSIGNED;
-- ENTITY DECLARATION
entity LPM_COMPARE is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Type of comparison performed: "SIGNED", "UNSIGNED"
lpm_representation : string := "UNSIGNED";
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type: string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE is
-- COMPONENT DECLARATION
component LPM_COMPARE_SIGNED
generic (
lpm_width : natural;
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
alb : out std_logic;
aeb : out std_logic;
agb : out std_logic;
aleb : out std_logic;
aneb : out std_logic;
ageb : out std_logic
);
end component;
component LPM_COMPARE_UNSIGNED
generic (
lpm_width : natural;
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
alb : out std_logic;
aeb : out std_logic;
agb : out std_logic;
aleb : out std_logic;
aneb : out std_logic;
ageb : out std_logic
);
end component;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if ((lpm_representation /= "UNSIGNED") and (lpm_representation /= "SIGNED")) then
ASSERT FALSE
REPORT "Value of lpm_representation parameter must be SIGNED or UNSIGNED!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- instantiate LPM_COMPARE_UNSIGNED to perform "UNSIGNED" data comparison
L1: if lpm_representation = "UNSIGNED" generate
U1: LPM_COMPARE_UNSIGNED
generic map (
lpm_width => lpm_width,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
clock => clock,
aclr => aclr,
clken => clken,
alb => alb,
aeb => aeb,
agb => agb,
aleb => aleb,
aneb => aneb,
ageb => ageb
);
end generate;
-- instantiate LPM_COMPARE_SIGNED to perform "SIGNED" data comparison
L2: if lpm_representation = "SIGNED" generate
U2: LPM_COMPARE_SIGNED
generic map (
lpm_width => lpm_width,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
clock => clock,
aclr => aclr,
clken => clken,
alb => alb,
aeb => aeb,
agb => agb,
aleb => aleb,
aneb => aneb,
ageb => ageb
);
end generate;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_mult
--
-- Description : Parameterized multiplier megafunction.
--
-- Limitation : n/a
--
-- results Expected: dataa[] * datab[] + sum[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_MULT is
-- GENERIC DECLARATION
generic (
lpm_widtha : natural; -- Width of the dataa[] port. (Required)
lpm_widthb : natural; -- Width of the datab[] port. (Required)
lpm_widthp : natural; -- Width of the result[] port. (Required)
lpm_widths : natural := 1; -- Width of the sum[] port. (Required)
lpm_representation : string := "UNSIGNED"; -- Type of multiplication performed
lpm_pipeline : natural := 0; -- Number of clock cycles of latency
lpm_type : string := "LPM_MULT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Multiplicand. (Required)
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
-- Multiplier. (Required)
datab : in std_logic_vector(lpm_widthb-1 downto 0);
-- Partial sum.
sum : in std_logic_vector(lpm_widths-1 downto 0) := (OTHERS => '0');
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
result : out std_logic_vector(lpm_widthp-1 downto 0)
);
end LPM_MULT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_MULT is
-- FUNCTION DECLARATION
function str2bin (constant i_str : in string;
constant i_width_str : in natural) return std_logic_vector is
variable binary_bits : std_logic_vector (255 downto 0) := (others => '0');
begin
if(i_str'length > 0) then
for i in 0 to (i_str'right - i_str'left) loop
if (i_str'left >= i) then
case i_str(i_str'right - i) is
when '0' => binary_bits(i) := '0';
when '1' => binary_bits(i) := '1';
when others => binary_bits(i) := 'X';
end case;
end if;
end loop;
end if;
return binary_bits(i_width_str -1 downto 0);
end str2bin;
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_widthp-1 downto 0);
-- CONSTANT DECLARATION
constant INPUT_A_IS_CONSTANT : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT");
constant INPUT_B_IS_CONSTANT : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT");
constant INPUT_A_FIXED_VALUE : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE");
constant INPUT_B_FIXED_VALUE : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE");
constant DATAA_FIXED : std_logic_vector(lpm_widtha-1 downto 0) := str2bin(INPUT_A_FIXED_VALUE, lpm_widtha);
constant DATAB_FIXED : std_logic_vector(lpm_widthb-1 downto 0) := str2bin(INPUT_B_FIXED_VALUE, lpm_widthb);
-- SIGNAL DECLARATION
signal i_dataa : std_logic_vector(lpm_widtha-1 downto 0);
signal i_datab : std_logic_vector(lpm_widthb-1 downto 0);
begin
i_dataa <= dataa when (INPUT_A_IS_CONSTANT /= "FIXED")
else DATAA_FIXED;
i_datab <= datab when (INPUT_B_IS_CONSTANT /= "FIXED")
else DATAB_FIXED;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_widtha <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widtha parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthb <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthb parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthp <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthp parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widths <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widths parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (clock, aclr, i_dataa, i_datab, sum)
variable resulttmp : T_RESULTTMP;
variable tmp_prod_ab : std_logic_vector(lpm_widtha+lpm_widthb downto 0);
variable tmp_prod_s : std_logic_vector(lpm_widths downto 0);
variable tmp_prod_p : std_logic_vector(lpm_widthp-1 downto 0);
variable tmp_use : integer;
begin
if (lpm_representation = "SIGNED") then
tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto 0) := signed(i_dataa) * signed(i_datab);
tmp_prod_ab(lpm_widtha+lpm_widthb) := tmp_prod_ab(lpm_widtha+lpm_widthb-1);
elsif (lpm_representation = "UNSIGNED") then
tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto 0) := unsigned(i_dataa) * unsigned(i_datab);
tmp_prod_ab(lpm_widtha+lpm_widthb) := '0';
else
ASSERT FALSE
REPORT "Illegal lpm_representation property value for LPM_MULT!"
SEVERITY ERROR;
end if;
tmp_use := 1; --AB
if (lpm_widths > (lpm_widtha+lpm_widthb)) then
if (lpm_representation = "SIGNED") then
tmp_prod_s := (OTHERS => tmp_prod_ab(lpm_widtha+lpm_widthb));
tmp_prod_s(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab;
tmp_prod_s := signed(tmp_prod_s) + signed(sum);
tmp_prod_p := (OTHERS => tmp_prod_s(lpm_widths));
else
tmp_prod_s := (OTHERS => '0');
tmp_prod_s(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab;
tmp_prod_s := unsigned(tmp_prod_s) + unsigned(sum);
tmp_prod_p := (OTHERS => '0');
end if;
tmp_use := 2; --S
elsif (lpm_widths > 0) then
if (lpm_representation = "SIGNED") then
tmp_prod_ab := signed(tmp_prod_ab) + signed(sum);
tmp_prod_p := (OTHERS => tmp_prod_ab(lpm_widtha+lpm_widthb));
else
tmp_prod_ab := unsigned(tmp_prod_ab) + unsigned(sum);
tmp_prod_p := (OTHERS => '0');
end if;
end if;
if (tmp_use = 2) then --S
if (lpm_widthp > lpm_widths) then
tmp_prod_p(lpm_widths downto 0) := tmp_prod_s;
elsif (lpm_widthp = lpm_widths) then
tmp_prod_p := tmp_prod_s(lpm_widthp-1 downto 0);
else
tmp_prod_p := tmp_prod_s(lpm_widths-1 downto lpm_widths-lpm_widthp);
end if;
else --AB
if (lpm_widthp > (lpm_widtha+lpm_widthb)) then
tmp_prod_p(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab(lpm_widtha+lpm_widthb downto 0);
elsif (lpm_widthp = lpm_widtha+lpm_widthb) then
tmp_prod_p := tmp_prod_ab(lpm_widthp-1 downto 0);
else
tmp_prod_p := tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto lpm_widtha+lpm_widthb-lpm_widthp);
end if;
end if;
resulttmp(lpm_pipeline) := tmp_prod_p;
-- Pipelining the result of multiplication
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if((clken = '1') and (lpm_pipeline > 0) and (now > 0 ns)) then
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
result <= resulttmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_divide
--
-- Description : Parameterized divider megafunction. This function performs a
-- divide operation such that denom * quotient + remain = numer
-- The function allows for all combinations of signed(two's
-- complement) and unsigned inputs. If any of the inputs is
-- signed, the output is signed. Otherwise the output is unsigned.
-- The function also allows the remainder to be specified as
-- always positive (in which case remain >= 0); otherwise remain
-- is zero or the same sign as the numerator
-- (this parameter is ignored in the case of purely unsigned
-- division). Finally the function is also pipelinable.
--
-- Limitation : n/a
--
-- Results Expected: Return quotient and remainder.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_DIVIDE is
generic (
lpm_widthn : natural; -- Width of the numer[] and quotient[] port. (Required)
lpm_widthd : natural; -- Width of the denom[] and remain[] port. (Required)
lpm_nrepresentation : string := "UNSIGNED"; -- The representation of numer
lpm_drepresentation : string := "UNSIGNED"; -- The representation of denom
lpm_pipeline : natural := 0; -- Number of Clock cycles of latency
lpm_type : string := "LPM_DIVIDE";
lpm_hint : string := "LPM_REMAINDERPOSITIVE=TRUE"
);
port (
numer : in std_logic_vector(lpm_widthn-1 downto 0); -- The numerator (Required)
denom : in std_logic_vector(lpm_widthd-1 downto 0); -- The denominator (Required)
clock : in std_logic := '0'; -- Clock input for pipelined usage
aclr : in std_logic := '0'; -- Asynchronous clear signal
clken : in std_logic := '1'; -- Clock enable for pipelined usage
quotient : out std_logic_vector(lpm_widthn-1 downto 0); -- Quotient (Required)
remain : out std_logic_vector(lpm_widthd-1 downto 0) -- Remainder (Required)
);
end LPM_DIVIDE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture behave of lpm_divide is
-- CONSTANT DECLARATION
constant MAX_WIDTH : integer := 256;
constant LPM_REMAINDERPOSITIVE : string := GET_PARAMETER_VALUE(LPM_HINT, "LPM_REMAINDERPOSITIVE");
-- TYPE DECLARATION
type QPIPELINE is array (0 to lpm_pipeline) of std_logic_vector(lpm_widthn-1 downto 0);
type RPIPELINE is array (0 to lpm_pipeline) of std_logic_vector(lpm_widthd-1 downto 0);
-- SIGNAL DECLARATION
signal quotient_pipe : std_logic_vector (lpm_widthn - 1 downto 0)
:= (others => '0');
signal quotient_value : std_logic_vector (lpm_widthn - 1 downto 0)
:= (others => '0');
signal remainder_pipe : std_logic_vector (lpm_widthd - 1 downto 0)
:= (others => '0');
signal remainder_value : std_logic_vector (lpm_widthd - 1 downto 0)
:= (others => '0');
-- FUNCTION DECLARATION
-- Bitwise left shift
procedure shift_left ( val : inout std_logic_vector; num : in integer) is
variable temp : std_logic_vector((val'length - 1) downto 0);
begin
if num /= 0 then
temp := val;
if (val'length > 1) then
for i in temp'high downto num loop
temp(i) := temp(i- num);
end loop;
for i in num-1 downto 0 loop
temp(i) := '0';
end loop;
end if;
temp(0) :='0';
val := temp;
end if;
end shift_left;
-- Bitwise right shift
procedure shift_right ( val : inout std_logic_vector ) is
variable temp : std_logic_vector(val'length-1 downto 0);
begin
temp := val;
if (val'length > 1) then
for i in 0 to temp'high - 1 loop
temp(i) := temp(i+1);
end loop;
end if;
temp(temp'high) := '0';
val := temp;
end shift_right;
begin
-- SIGNAL ASSIGNMENTS
quotient <= quotient_pipe when (lpm_pipeline > 0) else quotient_value;
remain <= remainder_pipe when (lpm_pipeline > 0) else remainder_value;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_widthn <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthn parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthd <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthd parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((LPM_REMAINDERPOSITIVE /= "TRUE") and
(LPM_REMAINDERPOSITIVE /= "FALSE")) then
ASSERT FALSE
REPORT " LPM_REMAINDERPOSITIVE value must be TRUE or FALSE!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (numer, denom)
variable i_denom : std_logic_vector(MAX_WIDTH-1 downto 0) := (OTHERS => '0');
variable i_quotient : std_logic_vector(lpm_widthn-1 downto 0) := (OTHERS => '0');
variable i_remain : std_logic_vector(MAX_WIDTH-1 downto 0) := (OTHERS => '0');
variable sign_numer : std_logic;
variable sign_denom : std_logic;
variable trailing_zero_count : integer;
variable int_numer, int_denom, int_quotient, int_remain : integer := 0;
variable signed_quotient : signed(lpm_widthn-1 downto 0);
variable unsigned_quotient : unsigned(lpm_widthn-1 downto 0);
begin
if ((lpm_widthn < 32) and (lpm_widthd < 32)) then
-- perform division using integer division.
if (lpm_nrepresentation = "UNSIGNED") then
int_numer := conv_integer(unsigned(numer));
elsif (lpm_nrepresentation = "SIGNED") then
int_numer := conv_integer(signed(numer));
else
ASSERT FALSE
REPORT "Illegal lpm_nrepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
int_denom := conv_integer(unsigned(denom));
elsif (lpm_drepresentation = "SIGNED") then
int_denom := conv_integer(signed(denom));
else
ASSERT FALSE
REPORT "Illegal lpm_drepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (int_denom = 0) then
remainder_value <= (OTHERS => 'X');
quotient_value <= (OTHERS => 'X');
else
int_quotient := int_numer / int_denom;
int_remain := int_numer rem int_denom;
-- LPM 220 standard
if ((LPM_REMAINDERPOSITIVE="TRUE") and (int_remain < 0)) then
if (int_denom < 0) then
int_quotient := int_quotient + 1;
else
int_quotient := int_quotient - 1;
end if;
int_remain := int_numer - (int_quotient*int_denom);
end if;
signed_quotient := conv_signed(int_quotient, lpm_widthn);
unsigned_quotient := conv_unsigned(int_quotient, lpm_widthn);
remainder_value <= conv_std_logic_vector(int_remain, lpm_widthd);
if ((lpm_nrepresentation = "UNSIGNED") and (lpm_drepresentation = "UNSIGNED")) then
quotient_value <= conv_std_logic_vector(unsigned_quotient, lpm_widthn);
else
quotient_value <= conv_std_logic_vector(signed_quotient, lpm_widthn);
end if;
end if;
else
-- perform division using long division algorithm
sign_numer := '0';
sign_denom := '0';
trailing_zero_count := 0;
i_quotient := (OTHERS => '0');
i_denom := (OTHERS => '0');
i_remain := (OTHERS => '0');
if (lpm_nrepresentation = "UNSIGNED") then
i_remain(lpm_widthn -1 downto 0) := numer;
elsif (lpm_nrepresentation = "SIGNED") then
if (numer(lpm_widthn-1) = '1') then
i_remain(lpm_widthn -1 downto 0) := not numer + 1;
sign_numer := '1';
else
i_remain(lpm_widthn -1 downto 0) := numer;
end if;
else
ASSERT FALSE
REPORT "Illegal lpm_nrepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := denom;
elsif (lpm_drepresentation = "SIGNED") then
if (denom(lpm_widthd-1) = '1') then
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := not denom + 1;
sign_denom := '1';
else
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := denom;
end if;
else
ASSERT FALSE
REPORT "Illegal lpm_drepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
-- if divide with zero, set quotient to all 'X'
if (i_denom = 0) then
i_quotient := (OTHERS => 'X');
i_remain := (OTHERS => 'X');
elsif (numer = 0) then
i_quotient := (OTHERS => '0');
else
-- get number of zero bits in the denom
for i in 0 to lpm_widthd-1 loop
if (i_denom(MAX_WIDTH-lpm_widthd + i) /= '0') then
trailing_zero_count := i;
exit;
end if;
end loop;
-- shift the i_denom until the first non-zero bit become leftmost bit.
for i in 0 to lpm_widthd-1 loop
if (i_denom(MAX_WIDTH-1-i) /= '0') then
shift_left(i_denom, i);
exit;
end if;
end loop;
-- perform division
if (unsigned(i_remain) >= unsigned(i_denom)) then
i_remain := i_remain - i_denom;
i_quotient(0) := '1';
else
i_quotient(0) := '0';
end if;
while (i_denom(trailing_zero_count) = '0') loop
shift_right(i_denom);
shift_left(i_quotient, 1);
if (unsigned(i_remain) >= unsigned(i_denom)) then
i_remain := i_remain - i_denom;
i_quotient(0) := '1';
else
i_quotient(0) := '0';
end if;
end loop;
-- quotient is negative number if either numer or denom (but not both)
-- is negative number
if ((sign_numer xor sign_denom) = '1') then
i_quotient := not i_quotient + 1;
end if;
-- LPM 220 standard
if ((sign_numer = '1') and (i_remain /= 0)) then
if (LPM_REMAINDERPOSITIVE = "TRUE") then
if (sign_denom = '1') then
i_quotient := i_quotient + 1;
else
i_quotient := i_quotient - 1;
end if;
i_remain := i_denom - i_remain;
else
i_remain := not i_remain + 1;
end if;
end if;
end if;
remainder_value <= i_remain(lpm_widthd -1 downto 0);
quotient_value <= i_quotient;
end if;
end process;
process (aclr, clock)
variable tmp_quotient : QPIPELINE := (OTHERS => (OTHERS => '0'));
variable tmp_remain : RPIPELINE := (OTHERS => (OTHERS => '0'));
begin
if (aclr = '1') then
if (lpm_pipeline > 0) then
-- clear the pipeline
for i in 0 to lpm_pipeline loop
tmp_quotient(i) := (OTHERS => '0');
tmp_remain(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if (lpm_pipeline > 0) then
if (clken = '1') then
-- pipeline the result
tmp_remain(lpm_pipeline) := remainder_value;
tmp_quotient(lpm_pipeline) := quotient_value;
tmp_quotient(0 to lpm_pipeline-1) := tmp_quotient(1 to lpm_pipeline);
tmp_remain(0 to lpm_pipeline-1) := tmp_remain(1 to lpm_pipeline);
end if;
end if;
end if;
quotient_pipe <= tmp_quotient(0);
remainder_pipe <= tmp_remain(0);
end process;
end behave;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_abs
--
-- Description : Parameterized absolute value megafunction. This megafunction
-- requires the input data to be signed number.
--
-- Limitation :
--
-- results Expected: Return absolute value of data and the overflow status
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_abs is
generic (
lpm_width : natural; -- Width of the data[] and result[] ports.
-- MUST be greater than 0 (Required)
lpm_type : string := "LPM_ABS";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0); -- (Required)
result : out std_logic_vector(lpm_width-1 downto 0); -- (Required)
overflow : out std_logic
);
end LPM_ABS;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ABS is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
GENERATE_ABS : process(data)
begin
if (data(lpm_width-1) = '1') then
if (lpm_width = 1) then
overflow <= '1';
result <= data;
elsif ((lpm_width > 1) and (data(lpm_width -2 downto 0) = 0)) then
overflow <= '1';
result <= data;
else
result <= 0 - data;
overflow <= '0';
end if;
else
result <= data;
overflow <= '0';
end if;
end process GENERATE_ABS;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_counter
--
-- Description : Parameterized counter megafunction. The lpm_counter
-- megafunction is a binary counter that features an up,
-- down, or up/down counter with optional synchronous or
-- asynchronous clear, set, and load ports.
--
-- Limitation : n/a
--
-- Results Expected: data output from the counter and carry-out of the MSB.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_COUNTER is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_modulus : natural := 0;
lpm_avalue : string := "UNUSED";
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
lpm_port_updown : string := "PORT_CONNECTIVITY";
lpm_type : string := "LPM_COUNTER";
lpm_hint : string := "UNUSED"
);
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
aset : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sset : in std_logic := '0';
sload : in std_logic := '0';
data : in std_logic_vector(lpm_width-1 downto 0):= (OTHERS => '0');
cin : in std_logic := '1';
q : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic := '0';
eq : out std_logic_vector(15 downto 0) := (OTHERS => '0')
);
end LPM_COUNTER;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COUNTER is
-- CONSTANT DECLARATION
constant ONES : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '1');
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+5 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+4 downto 0) := unsigned(ivalue(lpm_width downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal count : std_logic_vector(lpm_width downto 0);
signal dir : std_logic_vector(1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_modulus < 0) then
ASSERT FALSE
REPORT "Value of lpm_modulus parameter must be greater or equal to 0!"
SEVERITY ERROR;
end if;
if(lpm_width < 31) then
if (lpm_modulus > 2**lpm_width) then
ASSERT FALSE
REPORT "LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input."
SEVERITY WARNING;
end if;
end if;
wait;
end process MSG;
DIRECTION: process (updown)
begin
if (lpm_port_updown = "PORT_USED") then
dir(0) <= updown;
if ((updown = '0') or (updown = '1')) then
dir(1) <= '0'; -- increment or decrement
else
dir(1) <= '1'; -- unknown
end if;
elsif (lpm_port_updown = "PORT_UNUSED") then
if (lpm_direction = "DOWN") then
dir <= "00"; -- decrement
else
dir <= "01"; -- increment
end if;
else
if (lpm_direction = "UP") then
dir <= "01"; -- increment
elsif (lpm_direction = "DOWN") then
dir <= "00"; -- decrement
else
dir(0) <= updown;
if ((updown = '0') or (updown = '1')) then
dir(1) <= '0'; -- increment or decrement
else
if ((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) then
dir <= "01"; -- default to increment
else
dir(1) <= '1'; -- unknown
end if;
end if;
end if;
end if;
end process DIRECTION;
COUNTER: process (clock, aclr, aset, aload, data)
variable imodulus : integer := lpm_modulus;
variable init : boolean := false;
variable avalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
if (init = false) then
-- Initialize to pvalue and setup variables
if (lpm_pvalue /= "UNUSED") then
count <= pvalue;
else
count <= (OTHERS => '0');
end if;
if (lpm_width < 31) then -- 32 bit integer limit
if (lpm_modulus > (2 ** lpm_width)) then
imodulus := 2 ** lpm_width ;
else
imodulus := lpm_modulus;
end if;
else
imodulus := lpm_modulus;
end if;
-- Check parameters validity
if ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT") and
(lpm_direction /= "UP") and (lpm_direction /= "DOWN")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for lpm_counter!"
SEVERITY ERROR;
end if;
init := true;
end if;
if (aclr = '1') then
count <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
count <= (OTHERS => '1');
else
count <= avalue;
end if;
elsif (aload = '1') then
count(lpm_width-1 downto 0) <= data;
elsif (clock'event and (clock = '1')) then
if (clk_en = '1') then
if (sclr = '1') then
count <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
count <= (OTHERS => '1');
else
count <= svalue;
end if;
elsif (sload = '1') then
count(lpm_width-1 downto 0) <= data;
elsif (cnt_en = '1') then
if (imodulus = 1) then
count <= (OTHERS => '0');
elsif (cin = '1') then
if ((dir(0) = '1') and (dir(1) = '0')) then
-- Increase the count
if (((lpm_modulus = 0) and (unsigned(count(lpm_width-1 downto 0)) = unsigned(ONES))) or
((lpm_modulus /= 0) and ((count + 1) = imodulus))) then
count <= conv_std_logic_vector(0, lpm_width+1);
else
count <= count + 1;
end if;
elsif ((dir(0) = '0') and (dir(1) = '0')) then
-- Decrease the count
if (count = 0) then
if (lpm_modulus /= 0) then
count <= conv_std_logic_vector(imodulus-1, lpm_width+1);
else
count <= (OTHERS => '1');
end if;
else
count <= count - 1;
end if;
end if;
end if;
end if;
end if;
end if;
count(lpm_width) <= '0';
end process COUNTER;
CARRYOUT: process (count, cin, dir)
variable imodulus : integer := lpm_modulus;
variable init : boolean := false;
begin
if (init = false) then
if (lpm_width < 31) then -- 32 bit integer limit
if (lpm_modulus > (2 ** lpm_width)) then
imodulus := 2 ** lpm_width ;
else
imodulus := lpm_modulus;
end if;
else
imodulus := lpm_modulus;
end if;
init := true;
end if;
if (dir(1) = '0') then
cout <= '0';
if (imodulus = 1) then
cout <= '1';
elsif (cin = '1') then
if (((dir(0) = '0') and (count = 0)) or
((dir(0) = '1') and (((count = imodulus - 1) and (lpm_modulus /= 0)) or
((lpm_modulus = 0) and
(unsigned(count(lpm_width-1 downto 0)) = unsigned(ONES)))) )) then
cout <= '1';
end if;
end if;
end if;
end process CARRYOUT;
q <= count(lpm_width-1 downto 0);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_latch
--
-- Description : Parameterized latch megafunction.
--
-- Limitation : n/a
--
-- Results Expected: data output from the latch.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_LATCH is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[] and q[] ports. (Required)
lpm_avalue : string := "UNUSED"; -- Constant value that is loaded when aset is high.
lpm_pvalue : string := "UNUSED";
lpm_type : string := "LPM_LATCH";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
gate : in std_logic;
aclr : in std_logic := '0';
aset : in std_logic := '0';
aconst : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_LATCH;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_LATCH is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal init : std_logic := '0';
signal tmp_init: std_logic := '0';
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (tmp_init)
begin
if (tmp_init = '1') then
init <= '1';
end if;
end process;
process (data, gate, aclr, aset, init)
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
if (init = '0') then
if (lpm_pvalue /= "UNUSED") then
-- initialize to pvalue
q <= pvalue;
end if;
tmp_init <= '1';
else
if (aclr = '1') then
q <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
q <= (OTHERS => '1');
else
q <= avalue;
end if;
elsif (gate = '1') then
q <= data;
end if;
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ff
--
-- Description : Parameterized flipflop megafunction. The lpm_ff function
-- contains features that are not available in the DFF, DFFE,
-- DFFEA, TFF, and TFFE primitives, such as synchronous or
-- asynchronous set, clear, and load inputs.
--
-- Limitation : n/a
--
-- Results Expected: Data output from D or T flipflops.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_FF is
generic (
-- Width of the data[] and q[] ports. (Required)
lpm_width : natural;
-- Constant value that is loaded when aset is high.
lpm_avalue : string := "UNUSED";
-- Constant value that is loaded on the rising edge of clock when sset is high.
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
-- Type of flipflop.
lpm_fftype : string := "DFF";
lpm_type : string := "LPM_FF";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '1');
clock : in std_logic;
enable : in std_logic := '1';
aclr : in std_logic := '0';
aset : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sset : in std_logic := '0';
sload : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_FF;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_FF is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal iq : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
begin
-- PROCESS DECLARATION
process (data, clock, aclr, aset, aload)
variable init : std_logic := '0';
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
-- INITIALIZE TO PVALUE --
if (init = '0') then
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of LPM_WIDTH parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((lpm_fftype /= "DFF") and (lpm_fftype /= "TFF")) then
ASSERT FALSE
REPORT "Illegal LPM_FFTYPE property value for LPM_FF!"
SEVERITY ERROR;
end if;
if (lpm_pvalue /= "UNUSED") then
iq <= pvalue;
end if;
init := '1';
end if;
if (aclr = '1') then
iq <= (OTHERS => '0');
elsif (aclr = 'X') then
iq <= (OTHERS => 'X');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
iq <= (OTHERS => '1');
else
iq <= avalue;
end if;
elsif (aload = '1') then
if (lpm_fftype = "TFF") then
iq <= data;
end if;
elsif ((aclr = '0') and (now = 0 ps)) then
if (lpm_pvalue = "UNUSED") then
iq <= (OTHERS => '0');
else
iq <= pvalue;
end if;
elsif (clock'event and (clock = '1') and (NOW > 0 ns)) then
if (enable = '1') then
if (sclr = '1') then
iq <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
iq <= (OTHERS => '1');
else
iq <= svalue;
end if;
elsif (sload = '1') then
if (lpm_fftype = "TFF") then
iq <= data;
end if;
else
if (lpm_fftype = "TFF") then
for i in 0 to lpm_width-1 loop
if (data(i) = '1') then
iq(i) <= not iq(i);
end if;
end loop;
else
iq <= data;
end if;
end if;
end if;
end if;
end process;
q <= iq;
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_shiftreg
--
-- Description : Parameterized shift register megafunction.
--
-- Limitation : n/a
--
-- Results Expected: data output from the shift register and the Serial shift data output.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_SHIFTREG is
generic (
-- Width of the data[] and q ports. (Required)
lpm_width : natural;
lpm_direction : string := "LEFT";
-- Constant value that is loaded when aset is high.
lpm_avalue : string := "UNUSED";
-- Constant value that is loaded on the rising edge of clock when sset is high.
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
lpm_type : string := "L_SHIFTREG";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the shift register.
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
-- Positive-edge-triggered clock. (Required)
clock : in std_logic;
-- Clock enable input
enable : in std_logic := '1';
-- Serial shift data input.
shiftin : in std_logic := '1';
-- Synchronous parallel load. High (1): load operation; low (0): shift operation.
load : in std_logic := '0';
-- Asynchronous clear input.
aclr : in std_logic := '0';
-- Asynchronous set input.
aset : in std_logic := '0';
-- Synchronous clear input.
sclr : in std_logic := '0';
-- Synchronous set input.
sset : in std_logic := '0';
-- Data output from the shift register.
q : out std_logic_vector(lpm_width-1 downto 0);
-- Serial shift data output.
shiftout : out std_logic
);
end LPM_SHIFTREG;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_SHIFTREG is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal i_q : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal init : std_logic := '0';
signal tmp_init : std_logic := '0';
signal i_shiftout_pos : natural := lpm_width-1;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (tmp_init)
begin
if (tmp_init = '1') then
init <= '1';
end if;
end process;
process (clock, aclr, aset, init)
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
-- initIALIZE TO PVALUE --
if (init = '0') then
if (lpm_pvalue /= "UNUSED") then
i_q <= pvalue;
end if;
if ((lpm_direction = "LEFT") or (lpm_direction = "UNUSED")) then
i_shiftout_pos <= lpm_width-1;
elsif (lpm_direction = "RIGHT") then
i_shiftout_pos <= 0;
else
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_SHIFTREG!"
SEVERITY ERROR;
end if;
tmp_init <= '1';
elsif (aclr = '1') then
i_q <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
i_q <= (OTHERS => '1');
else
i_q <= avalue;
end if;
elsif (rising_edge(clock)) then
if (enable = '1') then
if (sclr = '1') then
i_q <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
i_q <= (OTHERS => '1');
else
i_q <= svalue;
end if;
elsif (load = '1') then
i_q <= data;
else
if (lpm_width < 2) then
i_q(0) <= shiftin;
elsif (lpm_direction = "LEFT") then
i_q <= (i_q(lpm_width-2 downto 0) & shiftin);
else
i_q <= (shiftin & i_q(lpm_width-1 downto 1));
end if;
end if;
end if;
end if;
end process;
q <= i_q;
shiftout <= i_q(i_shiftout_pos);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_dq
--
-- Description : Parameterized RAM with separate input and output ports megafunction.
-- lpm_ram_dp implement asynchronous memory or memory with synchronous
-- inputs and/or outputs.
--
-- Limitation : n/a
--
-- Results Expected: data output from the memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use work.LPM_DEVICE_FAMILIES.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_RAM_DQ is
generic (
-- Width of data[] and q[] ports. (Required)
lpm_width : natural;
-- Width of the address port. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Controls whether the data port is registered.
lpm_indata : string := "REGISTERED";
-- Controls whether the address and we ports are registered.
lpm_address_control: string := "REGISTERED";
-- Controls whether the q ports are registered.
lpm_outdata : string := "REGISTERED";
-- Name of the file containing RAM initialization data.
lpm_file : string := "UNUSED";
-- Specified whether to use the EAB or not.
use_eab : string := "ON";
intended_device_family : string := "UNUSED";
lpm_type : string := L_RAM_DQ;
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the memory. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Address input to the memory. (Required)
address : in std_logic_vector(lpm_widthad-1 downto 0);
-- Synchronizes memory loading.
inclock : in std_logic := '0';
-- Synchronizes q outputs from memory.
outclock : in std_logic := '0';
-- Write enable input. Enables write operations to the memory when high. (Required)
we : in std_logic;
-- Data output from the memory. (Required)
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_RAM_DQ;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_ram_dq is
-- TYPE DECLARATION
type LPM_MEMORY is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal address_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal we_tmp : std_logic;
signal we_reg : std_logic := '0';
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown intended_device_family " & intended_device_family
SEVERITY ERROR;
end if;
wait;
end process MSG;
SYNC: process( data, data_reg, address, address_reg,
we, we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
we_tmp <= we;
else
ASSERT FALSE
REPORT "Illegal lpm_address_control property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
elsif (lpm_indata = "UNREGISTERED") then
data_tmp <= data;
else
ASSERT FALSE
REPORT "Illegal lpm_indata property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal lpm_outdata property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
end process SYNC;
INPUT_REG: process (inclock)
begin
if (inclock'event and (inclock = '1')) then
data_reg <= data;
address_reg <= address;
we_reg <= we;
end if;
end process INPUT_REG;
OUTPUT_REG: process (outclock)
begin
if (outclock'event and (outclock = '1')) then
q_reg <= q_tmp;
end if;
end process OUTPUT_REG;
MEMORY: process(data_tmp, we_tmp, address_tmp, inclock)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if not (mem_init) then
-- Initialize to 0
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (lpm_file /= "UNUSED") then
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
while not ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'low) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- data record
i := 0;
k := lpm_width / 8;
if ((lpm_width mod 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (we_tmp = '1') then
if (((use_eab = "ON") or
(lpm_hint = "use_eab=ON")) and (lpm_address_control = "REGISTERED")) then
if (inclock = '0') then
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
else
mem_data (conv_integer(address_tmp)) := data_tmp;
end if;
end if;
q_tmp <= mem_data(conv_integer(address_tmp));
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_dp
--
-- Description : Parameterized dual-port RAM megafunction.
--
-- Limitation : n/a
--
-- Results Expected: Data output from the memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_COMMON_CONVERSION.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_RAM_DP is
generic (
-- Width of the data[] and q[] ports. (Required)
lpm_width : natural;
-- Width of the rdaddress[] and wraddress[] ports. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Determines the clock used by the data port.
lpm_indata : string := "REGISTERED";
-- Determines the clock used by the rdaddress and rden ports.
lpm_rdaddress_control : string := "REGISTERED";
-- Determines the clock used by the wraddress and wren ports.
lpm_wraddress_control : string := "REGISTERED";
-- Determines the clock used by the q[] port.
lpm_outdata : string := "REGISTERED";
-- Name of the file containing RAM initialization data.
lpm_file : string := "UNUSED";
-- Specified whether to use the EAB or not.
use_eab : string := "ON";
-- Specified whether to use the rden port or not.
rden_used : string := "TRUE";
intended_device_family : string := "UNUSED";
lpm_type : string := "LPM_RAM_DP";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the memory. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Read address input to the memory. (Required)
rdaddress : in std_logic_vector(lpm_widthad-1 downto 0);
-- Write address input to the memory. (Required)
wraddress : in std_logic_vector(lpm_widthad-1 downto 0);
-- Positive-edge-triggered clock for read operation.
rdclock : in std_logic := '0';
-- Clock enable for rdclock.
rdclken : in std_logic := '1';
-- Positive-edge-triggered clock for write operation.
wrclock : in std_logic := '0';
-- Clock enable for wrclock.
wrclken : in std_logic := '1';
-- Read enable input. Disables reading when low (0).
rden : in std_logic := '1';
-- Write enable input. (Required)
wren : in std_logic;
-- Data output from the memory. (Required)
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_RAM_DP;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_RAM_DP is
-- TYPE DECLARATION
type LPM_MEMORY is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal rdaddress_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal rdaddress_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal wraddress_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal wraddress_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal wren_tmp : std_logic;
signal wren_reg : std_logic := '0';
signal rden_tmp : std_logic;
signal rden_reg : std_logic := '0';
begin
-- SIGNAL ASSIGNMENTS
rden_tmp <= '1' when (rden_used = "FALSE")
else rden when (lpm_rdaddress_control = "UNREGISTERED")
else rden_reg;
rdaddress_tmp <= rdaddress when (lpm_rdaddress_control = "UNREGISTERED")
else rdaddress_reg;
wren_tmp <= wren when (lpm_wraddress_control = "UNREGISTERED")
else wren_reg;
wraddress_tmp <= wraddress when (lpm_wraddress_control = "UNREGISTERED")
else wraddress_reg;
data_tmp <= data when (lpm_indata = "UNREGISTERED")
else data_reg;
q <= q_tmp when (lpm_outdata = "UNREGISTERED")
else q_reg;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((lpm_indata /= "REGISTERED") and (lpm_indata /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value lpm_indata must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_outdata /= "REGISTERED") and (lpm_outdata /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_outdata parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_wraddress_control /= "REGISTERED") and
(lpm_wraddress_control /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_wraddress_control parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_rdaddress_control /= "REGISTERED") and
(lpm_rdaddress_control /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_rdaddress_control parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown INTENDED_DEVICE_FAMILY " & intended_device_family
SEVERITY ERROR;
end if;
wait;
end process MSG;
INPUT_REG: process (wrclock)
begin
if (wrclock'event and (wrclock = '1')) then
if (wrclken = '1') then
data_reg <= data;
wraddress_reg <= wraddress;
wren_reg <= wren;
end if;
end if;
end process INPUT_REG;
OUTPUT_REG: process (rdclock)
begin
if (rdclock'event and (rdclock = '1')) then
if (rdclken = '1') then
rdaddress_reg <= rdaddress;
rden_reg <= rden;
q_reg <= q_tmp;
end if;
end if;
end process OUTPUT_REG;
MEMORY: process(data_tmp, wren_tmp, rdaddress_tmp, wraddress_tmp, rden_tmp, wrclock)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum : string(2 downto 1) := " ";
variable startadd : string(4 downto 1) := " ";
variable ibase : integer := 0;
variable ibyte : integer := 0;
variable istartadd : integer := 0;
variable check_sum_vec, check_sum_vec_tmp : std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if NOT(mem_init) then
-- Initialize to 0
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if ((use_eab = "ON") or (lpm_hint = "use_eab=ON")) then
q_tmp <= (others => '1');
end if;
if (lpm_file /= "UNUSED") then
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
while not ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00" => -- data record
i := 0;
k := lpm_width / 8;
if ((lpm_width mod 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
-- read in data a byte (2 hex chars) at a time.
READ(L=>buf, VALUE=>datain,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (wren_tmp = '1') then
if (((use_eab = "ON") or (lpm_hint = "use_eab=ON")) and
(lpm_wraddress_control = "REGISTERED")) then
if (wrclock = '0') then
mem_data (conv_integer(wraddress_tmp)) := data_tmp;
end if;
else
mem_data (conv_integer(wraddress_tmp)) := data_tmp ;
end if;
end if;
if ((rden_tmp = '1') or (rden_used = "FALSE")) then
q_tmp <= mem_data(conv_integer(rdaddress_tmp));
end if;
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_io
--
-- Description :
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use std.textio.all;
entity LPM_RAM_IO is
generic ( LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_IO";
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port ( ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
OUTENAB : in STD_LOGIC := 'Z';
WE : in STD_LOGIC := 'Z';
DIO : inout STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end LPM_RAM_IO;
architecture LPM_SYN of lpm_ram_io is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal data_tmp, di, do : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp, q : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal address_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal we_tmp : std_logic;
signal we_reg : std_logic := '0';
signal memenab_tmp : std_logic;
signal memenab_reg : std_logic := '0';
signal outenab_used : std_logic;
-- provided for MP2 compliance
signal we_used : std_logic;
begin
sync: process( di, data_reg, address, address_reg, memenab, memenab_reg,
we,we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
memenab_tmp <= memenab_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
we_tmp <= we;
memenab_tmp <= memenab;
else
ASSERT FALSE
REPORT "Illegal LPM_ADDRESS_CONTROL property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
elsif (lpm_indata = "UNREGISTERED") then
data_tmp <= di;
else
ASSERT FALSE
REPORT "Illegal LPM_INDATA property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal LPM_OUTDATA property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
data_reg <= di;
address_reg <= address;
we_reg <= we;
memenab_reg <= memenab;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
INITIALIZE : process(we, outenab)
variable init : boolean := FALSE;
begin
if NOT (init) then
if (outenab = 'Z' and we = 'Z') then
ASSERT FALSE
REPORT "One of OutEnab or WE must be used!"
SEVERITY ERROR;
end if;
-- In reality, both are needed in current TDF implementation
if (outenab /= 'Z' and we /= 'Z') then
ASSERT FALSE
REPORT "Only one of OutEnab or WE should be used!"
-- Change severity to ERROR for full LPM 220 compliance
SEVERITY WARNING;
end if;
-- Comment out the following 5 lines for full LPM 220 compliance
if (we = 'Z') then
ASSERT FALSE
REPORT "WE is required!"
SEVERITY WARNING;
end if;
if (outenab = 'Z') then
outenab_used <= '0';
we_used <= '1';
else
outenab_used <= '1';
we_used <= '0';
end if;
-- Comment out the following 5 lines for full LPM 220 compliance
if (we = 'Z') then
we_used <= '0';
else
we_used <= '1';
end if;
init := TRUE;
end if;
end process;
memory: process(data_tmp, we_tmp, memenab_tmp, outenab, address_tmp, inclock, we_used, outenab_used)
variable mem_data : lpm_memory;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i,j,k,n,m,lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE /= "UNUSED") then
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (((we_used = '1' and we_tmp = '1')
or (outenab_used = '1' and we_used = '0' and outenab = '0'))
and memenab_tmp = '1') then
if (((use_eab = "ON") or (lpm_hint = "USE_EAB=ON")) and (lpm_address_control = "REGISTERED")) then
if inclock = '0' then
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
else
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
q_tmp <= data_tmp ;
else
q_tmp <= mem_data(conv_integer(address_tmp)) ;
end if;
end process;
di <= dio when ((outenab_used = '0' and we = '1')
or (outenab_used = '1' and outenab = '0'))
else (OTHERS => 'Z');
do <= q when memenab_tmp = '1' else (OTHERS => 'Z') ;
dio <= do when ((outenab_used = '0' and we = '0')
or (outenab_used = '1' and outenab = '1'))
else (OTHERS => 'Z');
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_rom
--
-- Description : Parameterized ROM megafunction. This megafunction is provided
-- only for backward compatibility in Cyclone, Stratix, and
-- Stratix GX designs; instead, Altera recommends using the
-- altsyncram megafunction.
--
-- Limitation : This option is available for all Altera devices supported by
-- the Quartus II software except MAX 3000 and MAX 7000 devices.
--
-- Results Expected: Output of memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use work.LPM_DEVICE_FAMILIES.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_ROM is
generic (
-- Width of the q[] port. (Required)
lpm_width : natural;
-- Width of the address[] port. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Indicates whether the address port is registered.
lpm_address_control : string := "REGISTERED";
-- Indicates whether the q and eq ports are registered.
lpm_outdata : string := "REGISTERED";
-- Name of the memory file containing ROM initialization data
lpm_file : string;
intended_device_family : string := "UNUSED";
lpm_type : string := "LPM_ROM";
lpm_hint : string := "UNUSED"
);
port (
-- Address input to the memory. (Required)
address : in STD_LOGIC_VECTOR(lpm_widthad-1 downto 0);
-- Clock for input registers.
inclock : in STD_LOGIC := '0';
-- Clock for output registers.
outclock : in STD_LOGIC := '0';
-- Memory enable input.
memenab : in STD_LOGIC := '1';
-- Output of memory. (Required)
q : out STD_LOGIC_VECTOR(lpm_width-1 downto 0)
);
end LPM_ROM;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_rom is
-- FUNCTION DECLARATION
--- Get the number of word stored in memory ---
function get_num_words (constant i_lpm_numwords,
i_lpm_widthad : in natural) return natural is
variable i_num_words : natural;
begin
if (i_lpm_numwords = 0) then
i_num_words := (2**lpm_widthad);
elsif (i_lpm_numwords > 0) then
i_num_words := i_lpm_numwords;
else
ASSERT FALSE
REPORT "Value of lpm_numwords parameter must be greater than 0!"
SEVERITY ERROR;
end if;
return i_num_words;
end get_num_words;
-- CONSTANT DECLARATION
constant NUM_WORDS : natural := get_num_words(lpm_numwords, lpm_widthad);
-- TYPE DECLARATION
type LPM_MEMORY is array(NUM_WORDS-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown INTENDED_DEVICE_FAMILY " & intended_device_family
SEVERITY ERROR;
end if;
if (FEATURE_FAMILY_MAX(intended_device_family) = true) then
ASSERT FALSE
REPORT "LPM_ROM megafunction does not support " & intended_device_family & " devices"
SEVERITY ERROR;
end if;
wait;
end process MSG;
ENABLE_MEM: process(memenab, q2)
begin
if (memenab = '1') then
q <= q2;
else
q <= (OTHERS => 'Z');
end if;
end process ENABLE_MEM;
SYNC: process(address, address_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
else
ASSERT FALSE
REPORT "Illegal lpm_address_control property value for LPM_RAM_ROM!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q2 <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q2 <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal lpm_outdata property value for LPM_RAM_ROM!"
SEVERITY ERROR;
end if;
end process SYNC;
INPUT_REG: process (inclock)
begin
if (inclock'event and (inclock = '1')) then
address_reg <= address;
end if;
end process INPUT_REG;
OUTPUT_REG: process (outclock)
begin
if (outclock'event and (outclock = '1')) then
q_reg <= q_tmp;
end if;
end process OUTPUT_REG;
MEMORY: process(memenab, address_tmp)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if NOT(mem_init) then
-- check for number of words out of bound
if ((NUM_WORDS > (2**lpm_widthad)) or
(NUM_WORDS <= (2**(lpm_widthad-1)))) then
ASSERT FALSE
REPORT "The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD!"
SEVERITY ERROR;
end if;
-- Initialize to zero
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if ((lpm_file = "UNUSED") or (lpm_file = "")) then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY ERROR;
else
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
-- read in data a byte (2 hex chars) at a time.
READ(L=>buf, VALUE=>datain,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
q_tmp <= mem_data(conv_integer(address_tmp));
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo
--
-- Description :
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_FIFO is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_type : string := "LPM_FIFO";
lpm_hint : string := "");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0);
full : out std_logic;
empty : out std_logic);
end LPM_FIFO;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO is
-- TYPE DECLARATION
type lpm_memory is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- FUNCTION DECLARATION
function get_underflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "UNDERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_underflow_checking;
function get_overflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "OVERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_overflow_checking;
function get_allow_rwcycle_when_full return string is
constant param_value : string := get_parameter_value(LPM_HINT, "ALLOW_RWCYCLE_WHEN_FULL");
begin
if ( param_value /= "") then
return param_value;
else
return "OFF";
end if;
end get_allow_rwcycle_when_full;
function get_intended_device_family return string is
constant param_value : string := get_parameter_value(LPM_HINT, "INTENDED_DEVICE_FAMILY");
begin
if ( param_value /= "") then
return param_value;
else
return "Stratix II";
end if;
end get_intended_device_family;
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant UNKNOWNS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X');
constant underflow_checking : string := get_underflow_checking;
constant overflow_checking : string := get_overflow_checking;
constant allow_rwcycle_when_full : string := get_allow_rwcycle_when_full;
constant intended_device_family : string := get_intended_device_family;
-- SIGNAL DECLARATION
signal i_count_id : integer := 0;
signal i_read_id : integer := 0;
signal i_write_id : integer := 0;
signal i_full_flag : std_logic := '0';
signal i_empty_flag : std_logic := '1';
signal i_tmp_q : std_logic_vector(lpm_width-1 downto 0) := ZEROS;
begin
-- PROCESS DECLARATION
process (clock, aclr)
-- VARIABLE DECLARATION
variable mem_data : lpm_memory := (OTHERS => ZEROS);
variable tmp_data : std_logic_vector(lpm_width-1 downto 0) := ZEROS;
variable write_id : integer := 0;
variable write_flag : boolean := false;
variable full_flag : boolean := false;
variable valid_rreq : boolean := false;
variable valid_wreq : boolean := false;
variable max_widthu : integer := 0;
variable numwords_minus_one : integer := 0;
variable need_init : boolean := true;
begin
if (need_init) then
if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) then
ASSERT FALSE
REPORT "Illegal LPM_SHOWAHEAD property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) then
ASSERT FALSE
REPORT "Illegal UNDERFLOW_CHECKING property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) then
ASSERT FALSE
REPORT "Illegal OVERFLOW_CHECKING property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((allow_rwcycle_when_full /= "ON") and (allow_rwcycle_when_full /= "OFF")) then
ASSERT FALSE
REPORT "Illegal ALLOW_RWCYCLE_WHEN_FULL property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Illegal INTENDED_DEVICE_FAMILY for LPM_FIFO!"
SEVERITY ERROR;
end if;
for i in 0 to (lpm_widthu - 1) loop
if (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) then
mem_data(i) := UNKNOWNS;
else
mem_data(i) := ZEROS;
end if;
end loop;
if (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) then
i_tmp_q <= UNKNOWNS;
else
i_tmp_q <= ZEROS;
end if;
max_widthu := (2 ** lpm_widthu) - 1;
numwords_minus_one := lpm_numwords - 1;
need_init := false;
end if; -- need_init
if (aclr = '1') then
full_flag := false;
if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) then
i_tmp_q <= ZEROS;
end if;
write_id := 0;
if (lpm_showahead = "ON") then
i_tmp_q <= mem_data(0);
end if;
end if; -- aclr event
if (clock'event and (clock = '1') and
((aclr = '0') or (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))))
then
valid_rreq := rdreq = '1' and ((i_empty_flag = '0') or
(underflow_checking = "OFF"));
valid_wreq := wrreq = '1' and ((i_full_flag = '0') or
(overflow_checking = "OFF") or ((rdreq = '1') and
(allow_rwcycle_when_full = "ON")));
if (sclr = '1')
then
i_tmp_q <= mem_data(i_read_id);
i_read_id <= 0;
i_count_id <= 0;
i_write_id <= 0;
i_full_flag <= '0';
i_empty_flag <= '1';
write_id := 0;
full_flag := false;
if (valid_wreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
end if;
if ((lpm_showahead = "ON") or (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
then
i_tmp_q <= mem_data(0);
end if;
else
-- Both WRITE and READ operations
if (valid_wreq and valid_rreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
i_empty_flag <= '0';
if (allow_rwcycle_when_full = "OFF")
then
i_full_flag <= '0';
full_flag := false;
end if;
if (i_write_id >= max_widthu)
then
i_write_id <= 0;
else
i_write_id <= i_write_id + 1;
end if;
i_tmp_q <= mem_data(i_read_id);
if (i_read_id >= max_widthu)
then
i_read_id <= 0;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(0);
end if;
else
i_read_id <= i_read_id + 1;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id + 1);
end if;
end if;
-- WRITE operation only
elsif (valid_wreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id);
end if;
i_count_id <= i_count_id + 1;
i_empty_flag <= '0';
if (i_count_id >= max_widthu)
then
i_count_id <= 0;
end if;
if ((i_count_id = numwords_minus_one) and (i_empty_flag = '0'))
then
i_full_flag <= '1';
full_flag := true;
end if;
if (i_write_id >= max_widthu)
then
i_write_id <= 0;
else
i_write_id <= i_write_id + 1;
end if;
-- READ operation only
elsif (valid_rreq)
then
i_tmp_q <= mem_data(i_read_id);
i_count_id <= i_count_id - 1;
i_full_flag <= '0';
full_flag := false;
if (i_count_id <= 0)
then
i_count_id <= max_widthu;
end if;
if (i_count_id = 1 and i_full_flag = '0')
then
i_empty_flag <= '1';
end if;
if (i_read_id >= max_widthu)
then
i_read_id <= 0;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(0);
end if;
else
i_read_id <= i_read_id + 1;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id + 1);
end if;
end if;
end if; -- if Both WRITE and READ operations
end if; -- if sclr = '1'
elsif (clock'event and (clock = '0'))
then
if (write_flag)
then
write_flag := false;
mem_data(write_id) := tmp_data;
end if;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id);
end if;
end if; -- clock event
if (aclr = '1')
then
i_full_flag <= '0';
i_empty_flag <= '1';
i_read_id <= 0;
i_write_id <= 0;
i_count_id <= 0;
write_id := 0;
end if;
end process; -- clock, aclr events
q <= i_tmp_q;
full <= i_full_flag;
empty <= i_empty_flag;
usedw <= conv_std_logic_vector(i_count_id, lpm_widthu);
end behavior; -- LPM_FIFO
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc_dffpipe
--
-- Description : Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_DFFPIPE is
-- GENERIC DECLARATION
generic (
lpm_delay : natural;
lpm_width : natural
);
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
d : in std_logic_vector (lpm_width-1 downto 0);
clock : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
q : out std_logic_vector (lpm_width-1 downto 0)
);
end LPM_FIFO_DC_DFFPIPE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_DFFPIPE is
-- TYPE DECLARATION
type DELAYPIPE is array (lpm_delay downto 0) of std_logic_vector (lpm_width-1 downto 0);
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
begin
-- PROCESS DECLARATION
process (clock, aclr, d)
------ VARIABLE DECLARATION
variable intpipe : DELAYPIPE := (OTHERS => ZEROS);
variable delay : integer := lpm_delay - 1;
variable need_init : boolean := true;
begin
if (lpm_delay = 0)
then
if ((aclr = '1') or need_init)
then
q <= ZEROS;
need_init := false;
else
q <= d;
end if;
else
if ((aclr = '1') or need_init)
then
for i in lpm_delay downto 0 loop
intpipe(i) := ZEROS;
end loop;
need_init := false;
q <= ZEROS;
end if;
if (rising_edge(clock) and (NOW > 0 ns))
then
if (delay > 0) then
for i in delay downto 1 loop
intpipe(i) := intpipe(i-1);
end loop;
end if;
intpipe(0) := d;
q <= intpipe(delay);
end if;
end if; -- (lpm_delay = 0)
end process; -- clock, aclr, d events
end behavior; -- lpm_fifo_dc_dffpipe
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc_fefifo
--
-- Description : Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_FEFIFO is
-- GENERIC DECLARATION
generic (
lpm_widthad : natural;
lpm_numwords : natural;
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_mode : string);
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
usedw_in : in std_logic_vector(lpm_widthad-1 downto 0);
wreq : in std_logic := 'Z';
rreq : in std_logic := 'Z';
clock : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
empty : out std_logic;
full : out std_logic);
end LPM_FIFO_DC_FEFIFO;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_FEFIFO is
-- SIGNAL DECLARATION
signal i_empty : std_logic := '1';
signal i_full : std_logic := '0';
begin
-- PROCESS DECLARATION
process (clock, aclr)
------ VARIABLE DECLARATION
variable sm_empty : std_logic_vector(1 downto 0) := "00";
variable lrreq : std_logic := '0';
variable almost_full : integer := 0;
variable usedw_is_1 : boolean := false;
variable need_init : boolean := true;
begin
if (need_init)
then
if ((lpm_mode /= "READ") and (lpm_mode /= "WRITE"))
then
ASSERT FALSE
REPORT "Error! LPM_MODE must be READ or WRITE."
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! OVERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if (lpm_numwords >= 3)
then
almost_full := lpm_numwords - 3;
else
almost_full := 0;
end if;
need_init := false;
end if; -- need_init
if (aclr'event and (aclr = '1'))
then
sm_empty := "00";
lrreq := '0';
i_empty <= '1';
i_full <= '0';
end if; -- aclr event
if (rising_edge(clock) and (aclr = '0') and (NOW > 0 ns))
then
if (lpm_mode = "READ")
then
case sm_empty is
-- state_empty
when "00" =>
if (usedw_in /= 0)
then
sm_empty := "01";
end if;
-- state_non_empty
when "01" =>
if (lpm_widthad > 1)
then
usedw_is_1 := ((usedw_in = 1) and (lrreq = '0')) or ((usedw_in = 2) and (lrreq = '1'));
else
usedw_is_1 := (usedw_in = 1) and (lrreq = '0');
end if;
if ((rreq = '1') and usedw_is_1)
then
sm_empty := "10";
end if;
-- state_emptywait
when "10" =>
if (usedw_in > 1)
then
sm_empty := "01";
else
sm_empty := "00";
end if;
when others =>
ASSERT FALSE
REPORT "Error! Invalid sm_empty state in read mode."
SEVERITY ERROR;
end case;
elsif (lpm_mode = "WRITE")
then
case sm_empty is
-- state_empty
when "00" =>
if (wreq = '1')
then
sm_empty := "01";
end if;
-- state_one
when "01" =>
if (wreq = '0')
then
sm_empty := "11";
end if;
-- state_non_empty
when "11" =>
if (wreq = '1')
then
sm_empty := "01";
elsif (usedw_in = 0)
then
sm_empty := "00";
end if;
when others =>
ASSERT FALSE
REPORT "Error! Invalid sm_empty state in write mode."
SEVERITY ERROR;
end case;
end if;
i_empty <= not sm_empty(0);
if ((aclr = '0') and (usedw_in >= almost_full) and (NOW > 0 ns))
then
i_full <= '1';
else
i_full <= '0';
end if;
if (underflow_checking = "OFF")
then
lrreq := rreq;
else
lrreq := rreq and not i_empty;
end if;
end if; -- clock event
end process; -- clock, aclr events
empty <= i_empty;
full <= i_full;
end behavior; -- lpm_fifo_dc_fefifo
-- END OF ARCHITECTURE
--
-- Entity Name : lpm_fifo_dc_async
--
-- Description : Asynchoronous Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_FIFO_DC_FEFIFO;
use work.LPM_FIFO_DC_DFFPIPE;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_ASYNC is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
use_eab : string := "ON";
intended_device_family : string := "Stratix");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
rdreq : in std_logic;
wrreq : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
rdempty : out std_logic;
wrempty : out std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end LPM_FIFO_DC_ASYNC;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_ASYNC is
-- TYPE DECLARATION
type LPM_MEMORY is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant ZEROU : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
constant GRAY_DELAYPIPE : integer := 1;
constant WRUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full
constant RDUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full
-- SIGNAL DECLARATION
signal i_data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal i_rdptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrptr_tmp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rdptrrg : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrdelaycycle : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rden : std_logic := '0';
signal i_wren : std_logic := '0';
signal i_rdenclock : std_logic := '0';
signal i_wren_tmp : std_logic := '0';
signal i_rdempty : std_logic := '1';
signal i_wrempty : std_logic := '1';
signal i_rdfull : std_logic := '0';
signal i_wrfull : std_logic := '0';
signal i_rdusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_ws_nbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rs_nbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_ws_dbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rs_dbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wr_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rd_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wr_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rd_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_q_tmp : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_zero : std_logic := '0';
-- COMPONENT DECLARATION
component LPM_FIFO_DC_FEFIFO
generic (
lpm_widthad : natural;
lpm_numwords : natural;
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_mode : string);
port (
usedw_in : in std_logic_vector(lpm_widthad-1 downto 0);
wreq : in std_logic := 'Z';
rreq : in std_logic := 'Z';
clock : in std_logic;
aclr : in std_logic := '0';
empty : out std_logic;
full : out std_logic);
end component;
component LPM_FIFO_DC_DFFPIPE
generic (
lpm_delay : natural;
lpm_width : natural);
port (
d : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
aclr : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0));
end component;
begin
-- COMPONENT ASSIGNMENTS
-- Delays & DFF Pipes
DP_RDPTR_D: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => 0,
lpm_width => lpm_widthu)
port map (
d => i_rdptr,
clock => i_rdenclock,
aclr => aclr,
q => i_rdptrrg);
DP_WRPTR_D: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => 1,
lpm_width => lpm_widthu)
port map (
d => i_wrptr,
clock => wrclk,
aclr => aclr,
q => i_wrdelaycycle);
DP_WS_NBRP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => WRSYNC_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rdptrrg,
clock => wrclk,
aclr => aclr,
q => i_ws_nbrp);
DP_RS_NBWP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => RDSYNC_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_wrdelaycycle,
clock => rdclk,
aclr => aclr,
q => i_rs_nbwp);
DP_WS_DBRP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => GRAY_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_ws_nbrp,
clock => wrclk,
aclr => aclr,
q => i_ws_dbrp);
DP_RS_DBWP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => GRAY_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rs_nbwp,
clock => rdclk,
aclr => aclr,
q => i_rs_dbwp);
DP_WR_USEDW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => DELAY_WRUSEDW,
lpm_width => lpm_widthu)
port map (
d => i_wr_udwn,
clock => wrclk,
aclr => aclr,
q => i_wrusedw);
DP_RD_USEDW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => DELAY_RDUSEDW,
lpm_width => lpm_widthu)
port map (
d => i_rd_udwn,
clock => rdclk,
aclr => aclr,
q => i_rdusedw);
DP_WR_DBUW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => WRUSEDW_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_wr_udwn,
clock => wrclk,
aclr => aclr,
q => i_wr_dbuw);
DP_RD_DBUW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => RDUSEDW_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rd_udwn,
clock => rdclk,
aclr => aclr,
q => i_rd_dbuw);
-- Empty/Full
WR_FE: LPM_FIFO_DC_FEFIFO
generic map (
lpm_widthad => lpm_widthu,
lpm_numwords => lpm_numwords,
underflow_checking => underflow_checking,
overflow_checking => overflow_checking,
lpm_mode => "WRITE")
port map (
usedw_in => i_wr_dbuw,
wreq => wrreq,
rreq => i_zero,
clock => wrclk,
aclr => aclr,
empty => i_wrempty,
full => i_wrfull);
RD_FE: LPM_FIFO_DC_FEFIFO
generic map (
lpm_widthad => lpm_widthu,
lpm_numwords => lpm_numwords,
underflow_checking => underflow_checking,
overflow_checking => overflow_checking,
lpm_mode => "READ")
port map (
usedw_in => i_rd_dbuw,
wreq => i_zero,
rreq => rdreq,
clock => rdclk,
aclr => aclr,
empty => i_rdempty,
full => i_rdfull);
-- PROCESS DECLARATION
-- FIFOram
process (wrclk, rdclk, aclr)
------ VARIABLE DECLARATION
variable max_widthu : integer := 0;
variable max_widthu_minus_one : integer := 0;
variable mem_data : LPM_MEMORY := (OTHERS => ZEROS);
variable need_init : boolean := true;
begin
if (need_init) then
if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF"))
then
ASSERT FALSE
REPORT "Error! LPM_SHOWAHEAD must be ON or OFF."
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! OVERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((use_eab /= "ON") and (use_eab /= "OFF"))
then
ASSERT FALSE
REPORT "Error! USE_EAB must be ON or OFF."
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Error! Illegal INTENDED_DEVICE_FAMILY."
SEVERITY ERROR;
end if;
max_widthu := 2 ** lpm_widthu;
max_widthu_minus_one := (2 ** lpm_widthu) - 1;
for i in lpm_numwords - 1 downto 0 loop
mem_data(i) := ZEROS;
end loop;
need_init := false;
end if; -- need_init
if (aclr'event and (aclr = '1'))
then
i_rdptr <= ZEROU;
i_wrptr <= ZEROU;
if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF"))
then
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(0);
else
i_q_tmp <= ZEROS;
end if;
end if;
end if; -- aclr event
if (rising_edge(wrclk))
then
if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF")))
then
i_data_tmp <= ZEROS;
i_wrptr_tmp <= ZEROU;
i_wren_tmp <= '0';
elsif (NOW > 0 ns)
then
i_data_tmp <= data;
i_wrptr_tmp <= i_wrptr;
i_wren_tmp <= i_wren;
if (i_wren = '1')
then
if ((aclr = '0') and (i_wrptr < max_widthu_minus_one))
then
i_wrptr <= i_wrptr + 1;
else
i_wrptr <= ZEROU;
end if;
if (use_eab = "OFF")
then
mem_data(CONV_INTEGER(i_wrptr) mod max_widthu) := data;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if;
end if;
end if;
end if; -- wrclk = '1' and wrclk'event
if ((falling_edge(wrclk) and (use_eab = "ON")) and (NOW > 0 ns))
then
if (i_wren_tmp = '1')
then
mem_data(CONV_INTEGER(i_wrptr_tmp) mod max_widthu) := i_data_tmp;
end if;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if; -- wrclk = '0' and wrclk event and (use_eab = "ON")) and (NOW > 0 ns)
if (rising_edge(rdclk))
then
if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF")))
then
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(0);
else
i_q_tmp <= ZEROS;
end if;
elsif ((i_rden = '1') and (NOW > 0 ns))
then
if ((aclr = '0') and (i_rdptr < max_widthu_minus_one))
then
i_rdptr <= i_rdptr + 1;
else
i_rdptr <= ZEROU;
end if;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr + 1) mod max_widthu);
else
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if;
end if; -- rdclk = '1' and rdclk event
end process; -- aclr, wrclk, rdclk events
i_rden <= rdreq when underflow_checking = "OFF" else
rdreq and not i_rdempty;
i_wren <= wrreq when overflow_checking = "OFF" else
wrreq and not i_wrfull;
-- Delays & DFF Pipes
process (rdclk)
begin
if (falling_edge(rdclk))
then
i_rdenclock <= '0';
elsif (rising_edge(rdclk))
then
if (i_rden = '1')
then
i_rdenclock <= '1';
end if;
end if;
end process; -- rdclk event
process (i_wrptr, i_ws_dbrp)
begin
if (NOW > 0 ns)
then
i_wr_udwn <= i_wrptr - i_ws_dbrp;
end if;
end process; -- i_wrptr, i_ws_dbrp events
process (i_rdptr, i_rs_dbwp)
begin
if (NOW > 0 ns)
then
i_rd_udwn <= i_rs_dbwp - i_rdptr;
end if;
end process; -- i_rdptr, i_rs_dbwp events
-- Outputs
rdempty <= i_rdempty;
rdfull <= i_rdfull;
wrempty <= i_wrempty;
wrfull <= i_wrfull;
rdusedw <= i_rdusedw;
wrusedw <= i_wrusedw;
q <= i_q_tmp;
end behavior; -- lpm_fifo_dc_async
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc
--
-- Description : Dual clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
use work.LPM_FIFO_DC_ASYNC;
-- ENTITY DECLARATION
entity LPM_FIFO_DC is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_hint : string := "";
lpm_type : string := "LPM_FIFO_DC");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
rdclock : in std_logic;
wrclock : in std_logic;
aclr : in std_logic := '0';
rdreq : in std_logic;
wrreq : in std_logic;
-- OUTPUT PORT DECLARATION
rdfull : out std_logic;
wrfull : out std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end LPM_FIFO_DC;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC is
-- FUNCTION DECLARATION
function get_underflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "UNDERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return underflow_checking;
end if;
end get_underflow_checking;
function get_overflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "OVERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return overflow_checking;
end if;
end get_overflow_checking;
function get_use_eab return string is
constant param_value : string := get_parameter_value(LPM_HINT, "USE_EAB");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_use_eab;
function get_intended_device_family return string is
constant param_value : string := get_parameter_value(LPM_HINT, "INTENDED_DEVICE_FAMILY");
begin
if ( param_value /= "") then
return param_value;
else
return "Stratix II";
end if;
end get_intended_device_family;
-- CONSTANT DECLARATION
constant C_UNDERFLOW_CHECKING : string := get_underflow_checking;
constant C_OVERFLOW_CHECKING : string := get_overflow_checking;
constant C_USE_EAB : string := get_use_eab;
constant C_INTENDED_DEVICE_FAMILY : string := get_intended_device_family;
-- SIGNAL DECLARATION
signal i_rdfull_a : std_logic := '0';
signal i_wrfull_a : std_logic := '0';
signal i_rdempty_a : std_logic := '1';
signal i_wrempty_a : std_logic := '1';
signal i_rdfull_s : std_logic := '0';
signal i_wrfull_s : std_logic := '0';
signal i_rdempty_s : std_logic := '1';
signal i_wrempty_s : std_logic := '1';
signal i_rdusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rdusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_q_a : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_q_s : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
-- COMPONENT DECLARATION
component LPM_FIFO_DC_ASYNC
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
use_eab : string := "ON";
intended_device_family : string := "Stratix");
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
aclr : in std_logic := '0';
rdreq : in std_logic;
wrreq : in std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end component;
begin
-- COMPONENT ASSIGNMENTS
ASYNC: LPM_FIFO_DC_ASYNC
generic map (
lpm_width => lpm_width,
lpm_widthu => lpm_widthu,
lpm_numwords => lpm_numwords,
lpm_showahead => lpm_showahead,
underflow_checking => C_UNDERFLOW_CHECKING,
overflow_checking => C_OVERFLOW_CHECKING,
use_eab => C_USE_EAB,
intended_device_family => C_INTENDED_DEVICE_FAMILY)
port map (
data => data,
rdclk => rdclock,
wrclk => wrclock,
aclr => aclr,
rdreq => rdreq,
wrreq => wrreq,
rdfull => i_rdfull_a,
wrfull => i_wrfull_a,
rdempty => i_rdempty_a,
wrempty => i_wrempty_a,
rdusedw => i_rdusedw_a,
wrusedw => i_wrusedw_a,
q => i_q_a);
rdfull <= i_rdfull_a;
wrfull <= i_wrfull_a;
rdempty <= i_rdempty_a;
wrempty <= i_wrempty_a;
rdusedw <= i_rdusedw_a;
wrusedw <= i_wrusedw_a;
q <= i_q_a;
end behavior; -- lpm_fifo_dc
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inpad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_INpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INpad";
lpm_hint : string := "UNUSED"
);
port (
pad : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INpad is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= pad;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_outpad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_OUTpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "L_OUTpad";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
pad : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_OUTpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OUTpad is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
pad <= data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_bipad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_BIpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_BIpad";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
enable : in std_logic;
result : out std_logic_vector(lpm_width-1 downto 0);
pad : inout std_logic_vector(lpm_width-1 downto 0)
);
end LPM_BIpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_BIpad is
signal tmp_pad : std_logic_vector(lpm_width-1 downto 0);
begin
tmp_pad <= pad;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(data, tmp_pad, enable)
begin
if enable = '1' then
pad <= data;
result <= (OTHERS => 'Z');
else
result <= tmp_pad;
pad <= (OTHERS => 'Z');
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
| gpl-3.0 | 7589ac40c0631acb9da0a29c54a67c47 | 0.415075 | 4.555121 | false | false | false | false |
keith-epidev/md2x | build/code/alu.vhdl | 1 | 2,462 | library ieee;
use ieee.std_logic_1164.all;
entity alu is
port (
A,B : in std_logic_vector(7 downto 0);
S : in std_logic_vector(3 downto 0);
Cin : in std_logic;
F : out std_logic_vector(7 downto 0);
Cout : out std_logic
);
end alu;
architecture arch of alu is
component N_add_sub is
generic(
size:integer := 8
);
port (
A,B : in std_logic_vector(size-1 downto 0);
Cin : in std_logic;
mode : in std_logic;
sum : out std_logic_vector(size-1 downto 0);
Cout : out std_logic
);
end component;
component logic_unit is
port (
A,B : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0)
);
end component;
component sr_unit is
port (
A : in std_logic_vector(7 downto 0);
Cin : in std_logic;
mode : in std_logic_vector(1 downto 0);
F : out std_logic_vector(7 downto 0);
Cout : out std_logic
);
end component;
signal A_val, B_val: std_logic_vector (7 downto 0);
signal U1_F :std_logic_vector(7 downto 0);
signal U1_cout : std_logic;
signal U1_mode : std_logic;
signal U2_F :std_logic_vector(7 downto 0);
signal U3_F :std_logic_vector(7 downto 0);
signal U3_mode : std_logic_vector(1 downto 0);
signal U3_cout : std_logic;
begin
U1 : N_add_sub port map(A_val,B_val,Cin,U1_mode,U1_F,U1_cout);
U2 : logic_unit port map(A_val,B_val,Cin,S(1 downto 0),U2_F);
U3 : sr_unit port map(A_val,Cin,U3_mode,U3_F,U3_cout);
U3_mode <= S(1 downto 0);
with S(3 downto 2) select
F <= U3_F when "10",
U2_F when "11",
U1_F when others;
with S(3 downto 2) select
Cout <= '0' when "10",
U3_Cout when "11",
U1_Cout when others;
mode: process(A,B,S,Cin) begin
-- swizzle inputs
if(S(3) = '0')then
case S(2 downto 0) is
when "000" =>
A_val <= (others=>'0');
B_val <= (others=>'0');
U1_mode <= '0';
when "001" =>
A_val <= (others=>'0');
B_val <= (others=>'0');
U1_mode <= '1';
when "010" =>
A_val <= A;
B_val <= (others=>'0');
U1_mode <= '0';
when "011" =>
A_val <= A;
B_val <= (others=>'0');
U1_mode <= '1';
when "100" =>
A_val <= A;
B_val <= B;
U1_mode <= '0';
when "101" =>
A_val <= A;
B_val <= A;
U1_mode <= '0';
when "110" =>
A_val <= A;
B_val <= B;
U1_mode <= '1';
when others =>
A_val <= B;
B_val <= A;
U1_mode <= '1';
end case;
else
A_val <= A;
B_val <= B;
end if;
end process mode;
end arch;
| gpl-2.0 | 401862a15833de54bdbccf77db0d4e4e | 0.575548 | 2.358238 | false | false | false | false |
alvieboy/xtc-base | sdram_wrap.vhd | 1 | 4,941 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity sdram_ctrl is
generic (
HIGH_BIT: integer := 24
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
dbg: out memory_debug_type;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24;
MHZ: integer := 96;
REFRESH_CYCLES: integer := 4096;
ADDRESS_BITS: integer := 13
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (ADDRESS_BITS-1 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0);
tag_in : in std_logic_vector(31 downto 0);
tag_out : out std_logic_vector(31 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (HIGH_BIT downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_tag : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => HIGH_BIT,
ADDRESS_BITS => 12
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask,
tag_in => wb_tag_i,
tag_out => sdr_tag
);
sdr_address(HIGH_BIT downto 2) <= wb_adr_i(HIGH_BIT downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
resync: if true generate
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
wb_ack_o <= '0';
else
wb_ack_o <= sdr_data_out_valid;
end if;
wb_dat_o <= sdr_data_out;
wb_tag_o <= sdr_tag;
end if;
end process;
end generate;
noresync: if false generate
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
wb_tag_o <= sdr_tag;
end generate;
dbg.strobe <= ( not pending ) and wb_stb_i and wb_cyc_i;
dbg.write <= wb_we_i;
dbg.address <= unsigned(wb_adr_i);
dbg.data <= unsigned(wb_dat_i);
dbg.pc <= x"deadbeef";
end behave;
| bsd-3-clause | 15199f6a37d7e41820ff796c42e7a206 | 0.579235 | 2.877694 | false | false | false | false |
EPiCS/reconos | pcores/reconos_osif_fifo_v1_00_a/hdl/vhdl/reconos_osif_fifo.vhd | 2 | 10,575 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - OSIF FIFO - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple bidirectional FIFO accessible from the AXI-Bus
-- and from other hardware via the known FIFO interface.
-- This FIFO is used to connect the hwts to the AXI-Bus
-- and therefore to the processing system.
-- Register Definition (as seen from Bus):
-- Reg0: Read data
-- Reg1: Write data
-- Reg2: Fill - number of elements in receive-FIFO
-- Reg3: Rem - free space in send-FIFO
--
-- REMARK: Different clocks for AXI, FIFO-Rd and FIFO-Wr
-- are not supported yet. S_AXI_ACKL is used and
-- FIFO_**_Clk are just added for the future.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library reconos_osif_fifo_v1_00_a;
use reconos_osif_fifo_v1_00_a.user_logic;
entity reconos_osif_fifo is
generic (
C_FIFO_DEPTH : integer := 32;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
-- FIFO ports
OSIF_FIFO_Sw2Hw_Clk : in std_logic;
OSIF_FIFO_Sw2Hw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : out std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : out std_logic;
OSIF_FIFO_Sw2Hw_RE : in std_logic;
OSIF_FIFO_Hw2Sw_Clk : in std_logic;
OSIF_FIFO_Hw2Sw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : out std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : out std_logic;
OSIF_FIFO_Hw2Sw_WE : in std_logic;
OSIF_FIFO_Rst : in std_logic;
-- Bus protocol ports
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
-- Interrupt for Bus (only hw2bus)
OSIF_FIFO_Has_Data : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
attribute SIGIS of OSIF_FIFO_Rst : signal is "Rst";
attribute SIGIS of OSIF_FIFO_Sw2Hw_Clk : signal is "Clk";
attribute SIGIS of OSIF_FIFO_Hw2Sw_Clk : signal is "Clk";
attribute SIGIS of OSIF_FIFO_Has_Data : signal is "Intr_Level_High";
end entity reconos_osif_fifo;
architecture implementation of reconos_osif_fifo is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 4;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- Index for CS/CE
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity reconos_osif_fifo_v1_00_a.user_logic
generic map (
-- FIFO parameters
C_FIFO_DEPTH => C_FIFO_DEPTH,
-- Bus protocol parameters
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- FIFO ports
OSIF_FIFO_Sw2Hw_Clk => OSIF_FIFO_Sw2Hw_Clk,
OSIF_FIFO_Sw2Hw_Data => OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill => OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty => OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Sw2Hw_RE => OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Clk => OSIF_FIFO_Hw2Sw_Clk,
OSIF_FIFO_Hw2Sw_Data => OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_Rem => OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full => OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Hw2Sw_WE => OSIF_FIFO_Hw2Sw_WE,
OSIF_FIFO_Rst => OSIF_FIFO_Rst,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
OSIF_FIFO_Has_Data => OSIF_FIFO_Has_Data
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end implementation;
| gpl-2.0 | 4b3f344cb9e7dc21311f7b0988925353 | 0.584547 | 2.825762 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiiils_atoms.vhd | 1 | 362,407 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiiils_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiiils_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiiils_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiiils_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiiils_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiiils_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiiils_pllpack;
package body cycloneiiils_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiiils_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiiils_dffe : entity is TRUE;
end cycloneiiils_dffe;
-- architecture body --
architecture behave of cycloneiiils_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiiils_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiiils_mux21 : entity is TRUE;
end cycloneiiils_mux21;
architecture AltVITAL of cycloneiiils_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiiils_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_mux41 : entity is TRUE;
end cycloneiiils_mux41;
architecture AltVITAL of cycloneiiils_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiiils_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiiils_atom_pack.all;
-- entity declaration --
entity cycloneiiils_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiiils_and1 : entity is TRUE;
end cycloneiiils_and1;
-- architecture body --
architecture AltVITAL of cycloneiiils_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_lcell_comb
--
-- Description : Cyclone III LS LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiiils_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_lcell_comb : entity is TRUE;
end cycloneiiils_lcell_comb;
architecture vital_lcell_comb of cycloneiiils_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_routing_wire
--
-- Description : Cyclone III LS Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_routing_wire : entity is TRUE;
end cycloneiiils_routing_wire;
ARCHITECTURE behave of cycloneiiils_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III LS PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiiils_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiiils_mn_cntr;
ARCHITECTURE behave of cycloneiiils_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III LS PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiiils_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiiils_scale_cntr;
ARCHITECTURE behave of cycloneiiils_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiiils_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiiils_pll_reg;
ARCHITECTURE behave of cycloneiiils_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_pll
--
-- Description : Timing simulation model for the Cyclone III LS PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiiils_atom_pack.all;
USE work.cycloneiiils_pllpack.all;
USE work.cycloneiiils_mn_cntr;
USE work.cycloneiiils_scale_cntr;
USE work.cycloneiiils_dffe;
USE work.cycloneiiils_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIIILS:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiiils_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiiils_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III LS";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiiils_pll;
ARCHITECTURE vital_pll of cycloneiiils_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiiils_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiiils_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiiils_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiiils_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiiils_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiiils_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiiils_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiiils_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiiils_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiiils_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiiils_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiiils_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiiils_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_ff
--
-- Description : Cyclone III LS FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
use work.cycloneiiils_and1;
entity cycloneiiils_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_ff : entity is TRUE;
end cycloneiiils_ff;
architecture vital_lcell_ff of cycloneiiils_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiiils_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiiils_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiiils_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiiils_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiiils_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiiils_ram_register;
ARCHITECTURE reg_arch OF cycloneiiils_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiiils_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiiils_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiiils_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiiils_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiiils_atom_pack.all;
USE work.cycloneiiils_ram_register;
USE work.cycloneiiils_ram_pulse_generator;
ENTITY cycloneiiils_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiiils_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiiils_ram_block;
ARCHITECTURE block_arch OF cycloneiiils_ram_block IS
COMPONENT cycloneiiils_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiiils_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiiils_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiiils_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiiils_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiiils_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiiils_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiiils_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiiils_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone III LS MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiiils_mac_data_reg;
ARCHITECTURE vital_cycloneiiils_mac_data_reg OF cycloneiiils_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cycloneiiils_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone III LS MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiiils_mac_sign_reg;
ARCHITECTURE cycloneiiils_mac_sign_reg OF cycloneiiils_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiiils_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_mult_internal
--
-- Description : Cyclone III LS MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiiils_mac_mult_internal;
ARCHITECTURE vital_cycloneiiils_mac_mult_internal OF cycloneiiils_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cycloneiiils_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_mult
--
-- Description : Cyclone III LS MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiiils_atom_pack.all;
USE work.cycloneiiils_mac_data_reg;
USE work.cycloneiiils_mac_sign_reg;
USE work.cycloneiiils_mac_mult_internal;
ENTITY cycloneiiils_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiiils_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_mac_mult;
ARCHITECTURE vital_cycloneiiils_mac_mult OF cycloneiiils_mac_mult IS
COMPONENT cycloneiiils_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiiils_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiiils_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiiils_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiiils_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiiils_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiiils_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiiils_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cycloneiiils_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_mac_out
--
-- Description : Cyclone III LS MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_mac_out IS
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiiils_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_mac_out;
ARCHITECTURE vital_cycloneiiils_mac_out OF cycloneiiils_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cycloneiiils_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_io_ibuf
--
-- Description : Cyclone III LS IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiiils_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiiils_io_ibuf;
ARCHITECTURE arch OF cycloneiiils_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_io_obuf
--
-- Description : Cyclone III LS IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiiils_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiiils_io_obuf;
ARCHITECTURE arch OF cycloneiiils_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(15 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_ddio_oe
--
-- Description : Cyclone III LS DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiiils_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_ddio_oe;
ARCHITECTURE arch OF cycloneiiils_ddio_oe IS
component cycloneiiils_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiiils_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_latch
--
-- Description : Cyclone III LS latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_latch : entity is TRUE;
end cycloneiiils_latch;
architecture vital_latch of cycloneiiils_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_negedge,
SetupLow => tsetup_d_ena_noedge_negedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiiils_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_negedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_ddio_out
--
-- Description : Cyclone III LS DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiiils_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiiils_ddio_out;
ARCHITECTURE arch OF cycloneiiils_ddio_out IS
component cycloneiiils_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiiils_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiiils_latch";
tsetup_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiiils_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiiils_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiiils_pseudo_diff_out --
--Description: Simulation model for Cyclone III LS Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiiils_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiiils_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiiils_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiiils_io_pad
-- Description : Simulation model for cycloneiiils IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiiils_io_pad IS
GENERIC (
lpm_type : string := "cycloneiiils_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiiils_io_pad;
ARCHITECTURE arch OF cycloneiiils_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiiils_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
ENTITY cycloneiiils_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_ena_reg : entity is TRUE;
end cycloneiiils_ena_reg;
ARCHITECTURE behave of cycloneiiils_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiiils_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III LS CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEIIILS_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
use work.cycloneiiils_ena_reg;
entity cycloneiiils_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiiils_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiiils_clkctrl : entity is TRUE;
end cycloneiiils_clkctrl;
architecture vital_clkctrl of cycloneiiils_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiiils_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal outclk_tmp : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiiils_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiiils_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_tmp <= ena_out AND clkmux_out;
-- output path
process (inclk_ipd,outclk_tmp)
variable outclk_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLK",
OutTemp => outclk_tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkctrl;
--
--
-- CYCLONEIIILS_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiiils_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiiils_rublock;
architecture architecture_rublock of cycloneiiils_rublock is
begin
end architecture_rublock;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_controller
--
-- Description : cycloneiiils CONTROLLER VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_controller is
generic (
lpm_type : string := "cycloneiiils_controller"
);
port (
nceout : out std_logic
);
end cycloneiiils_controller;
architecture architecture_controller of cycloneiiils_controller is
begin
end architecture_controller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiiils_termination
--
-- Description : Cyclone III LS Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiiils_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiiils_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiiils_termination;
ARCHITECTURE cycloneiiils_termination_arch OF cycloneiiils_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiiils_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_jtag
--
-- Description : cycloneiiils JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_jtag is
generic (
lpm_type : string := "cycloneiiils_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiiils_jtag;
architecture architecture_jtag of cycloneiiils_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiiils_crcblock
--
-- Description : Cyclone III LS CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiiils_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
cyclecomplete : out std_logic;
regout : out std_logic
);
end cycloneiiils_crcblock;
architecture architecture_crcblock of cycloneiiils_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--
--
-- CYCLONEIIILS_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiiils_atom_pack.all;
entity cycloneiiils_oscillator is
generic
(
lpm_type: string := "cycloneiiils_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout1: out std_logic;
observableoutputport: out std_logic;
clkout : out std_logic
);
end cycloneiiils_oscillator;
architecture architecture_oscillator of cycloneiiils_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
| gpl-3.0 | 8f43632315936bef41adcf976d4a9251 | 0.4653 | 4.157474 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixv_pcie_hip_atoms.vhd | 1 | 227,512 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_gen3_pcie_hip is
generic (
func_mode : string := "disable";
in_cvp_mode : string := "not_cvp_mode";
bonding_mode : string := "bond_disable";
prot_mode : string := "disabled_prot_mode";
pcie_spec_1p0_compliance : string := "spec_1p1";
vc_enable : string := "single_vc";
enable_slot_register : string := "false";
pcie_mode : string := "shared_mode";
bypass_cdc : string := "false";
enable_rx_reordering : string := "true";
enable_rx_buffer_checking : string := "false";
single_rx_detect_data : bit_vector := B"0000";
single_rx_detect : string := "single_rx_detect";
use_crc_forwarding : string := "false";
bypass_tl : string := "false";
gen123_lane_rate_mode : string := "gen1";
lane_mask : string := "x4";
disable_link_x2_support : string := "false";
national_inst_thru_enhance : string := "true";
hip_hard_reset : string := "enable";
dis_paritychk : string := "enable";
wrong_device_id : string := "disable";
data_pack_rx : string := "disable";
ast_width : string := "rx_tx_64";
rx_sop_ctrl : string := "boundary_64";
rx_ast_parity : string := "disable";
tx_ast_parity : string := "disable";
ltssm_1ms_timeout : string := "disable";
ltssm_freqlocked_check : string := "disable";
deskew_comma : string := "skp_eieos_deskw";
dl_tx_check_parity_edb : string := "disable";
tl_tx_check_parity_msg : string := "disable";
port_link_number_data : bit_vector := B"00000001";
port_link_number : string := "port_link_number";
device_number_data : bit_vector := B"00000";
device_number : string := "device_number";
bypass_clk_switch : string := "false";
core_clk_out_sel : string := "div_1";
core_clk_divider : string := "div_1";
core_clk_source : string := "pll_fixed_clk";
core_clk_sel : string := "pld_clk";
enable_ch0_pclk_out : string := "true";
enable_ch01_pclk_out : string := "pclk_ch0";
pipex1_debug_sel : string := "disable";
pclk_out_sel : string := "pclk";
vendor_id_data : bit_vector := B"1000101110010";
vendor_id : string := "vendor_id";
device_id_data : bit_vector := B"0000000000000001";
device_id : string := "device_id";
revision_id_data : bit_vector := B"00000001";
revision_id : string := "revision_id";
class_code_data : bit_vector := B"111111110000000000000000";
class_code : string := "class_code";
subsystem_vendor_id_data : bit_vector := B"0001000101110010";
subsystem_vendor_id : string := "subsystem_vendor_id";
subsystem_device_id_data : bit_vector := B"0000000000000001";
subsystem_device_id : string := "subsystem_device_id";
no_soft_reset : string := "false";
maximum_current_data : bit_vector := B"000";
maximum_current : string := "maximum_current";
d1_support : string := "false";
d2_support : string := "false";
d0_pme : string := "false";
d1_pme : string := "false";
d2_pme : string := "false";
d3_hot_pme : string := "false";
d3_cold_pme : string := "false";
use_aer : string := "false";
low_priority_vc : string := "single_vc";
vc_arbitration : string := "single_vc";
disable_snoop_packet : string := "false";
max_payload_size : string := "payload_512";
surprise_down_error_support : string := "false";
dll_active_report_support : string := "false";
extend_tag_field : string := "false";
endpoint_l0_latency_data : bit_vector := B"000";
endpoint_l0_latency : string := "endpoint_l0_latency";
endpoint_l1_latency_data : bit_vector := B"000";
endpoint_l1_latency : string := "endpoint_l1_latency";
indicator_data : bit_vector := B"111";
indicator : string := "indicator";
role_based_error_reporting : string := "false";
slot_power_scale_data : bit_vector := B"00";
slot_power_scale : string := "slot_power_scale";
max_link_width : string := "x4";
enable_l1_aspm : string := "false";
enable_l0s_aspm : string := "false";
l1_exit_latency_sameclock_data : bit_vector := B"000";
l1_exit_latency_sameclock : string := "l1_exit_latency_sameclock";
l1_exit_latency_diffclock_data : bit_vector := B"000";
l1_exit_latency_diffclock : string := "l1_exit_latency_diffclock";
hot_plug_support_data : bit_vector := B"0000000";
hot_plug_support : string := "hot_plug_support";
slot_power_limit_data : bit_vector := B"00000000";
slot_power_limit : string := "slot_power_limit";
slot_number_data : bit_vector := B"0000000000000";
slot_number : string := "slot_number";
diffclock_nfts_count_data : bit_vector := B"00000000";
diffclock_nfts_count : string := "diffclock_nfts_count";
sameclock_nfts_count_data : bit_vector := B"00000000";
sameclock_nfts_count : string := "sameclock_nfts_count";
completion_timeout : string := "abcd";
enable_completion_timeout_disable : string := "true";
extended_tag_reset : string := "false";
ecrc_check_capable : string := "true";
ecrc_gen_capable : string := "true";
no_command_completed : string := "true";
msi_multi_message_capable : string := "count_4";
msi_64bit_addressing_capable : string := "true";
msi_masking_capable : string := "false";
msi_support : string := "true";
interrupt_pin : string := "inta";
ena_ido_req : string := "false";
ena_ido_cpl : string := "false";
enable_function_msix_support : string := "true";
msix_table_size_data : bit_vector := B"00000000000";
msix_table_size : string := "msix_table_size";
msix_table_bir_data : bit_vector := B"000";
msix_table_bir : string := "msix_table_bir";
msix_table_offset_data : bit_vector := B"00000000000000000000000000000";
msix_table_offset : string := "msix_table_offset";
msix_pba_bir_data : bit_vector := B"000";
msix_pba_bir : string := "msix_pba_bir";
msix_pba_offset_data : bit_vector := B"00000000000000000000000000000";
msix_pba_offset : string := "msix_pba_offset";
bridge_port_vga_enable : string := "false";
bridge_port_ssid_support : string := "false";
ssvid_data : bit_vector := B"0000000000000000";
ssvid : string := "ssvid";
ssid_data : bit_vector := B"0000000000000000";
ssid : string := "ssid";
eie_before_nfts_count_data : bit_vector := B"0100";
eie_before_nfts_count : string := "eie_before_nfts_count";
gen2_diffclock_nfts_count_data : bit_vector := B"11111111";
gen2_diffclock_nfts_count : string := "gen2_diffclock_nfts_count";
gen2_sameclock_nfts_count_data : bit_vector := B"11111111";
gen2_sameclock_nfts_count : string := "gen2_sameclock_nfts_count";
deemphasis_enable : string := "false";
pcie_spec_version : string := "v2";
l0_exit_latency_sameclock_data : bit_vector := B"110";
l0_exit_latency_sameclock : string := "l0_exit_latency_sameclock";
l0_exit_latency_diffclock_data : bit_vector := B"110";
l0_exit_latency_diffclock : string := "l0_exit_latency_diffclock";
rx_ei_l0s : string := "disable";
l2_async_logic : string := "enable";
aspm_config_management : string := "true";
atomic_op_routing : string := "false";
atomic_op_completer_32bit : string := "false";
atomic_op_completer_64bit : string := "false";
cas_completer_128bit : string := "false";
ltr_mechanism : string := "false";
tph_completer : string := "false";
extended_format_field : string := "true";
atomic_malformed : string := "false";
flr_capability : string := "true";
enable_adapter_half_rate_mode : string := "false";
vc0_clk_enable : string := "true";
vc1_clk_enable : string := "false";
register_pipe_signals : string := "false";
bar0_io_space : string := "false";
bar0_64bit_mem_space : string := "true";
bar0_prefetchable : string := "true";
bar0_size_mask_data : bit_vector := B"1111111111111111111111111111";
bar0_size_mask : string := "bar0_size_mask";
bar1_io_space : string := "false";
bar1_64bit_mem_space : string := "false";
bar1_prefetchable : string := "false";
bar1_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar1_size_mask : string := "bar1_size_mask";
bar2_io_space : string := "false";
bar2_64bit_mem_space : string := "false";
bar2_prefetchable : string := "false";
bar2_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar2_size_mask : string := "bar2_size_mask";
bar3_io_space : string := "false";
bar3_64bit_mem_space : string := "false";
bar3_prefetchable : string := "false";
bar3_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar3_size_mask : string := "bar3_size_mask";
bar4_io_space : string := "false";
bar4_64bit_mem_space : string := "false";
bar4_prefetchable : string := "false";
bar4_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar4_size_mask : string := "bar4_size_mask";
bar5_io_space : string := "false";
bar5_64bit_mem_space : string := "false";
bar5_prefetchable : string := "false";
bar5_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar5_size_mask : string := "bar5_size_mask";
expansion_base_address_register_data : bit_vector := B"00000000000000000000000000000000";
expansion_base_address_register : string := "expansion_base_address_register";
io_window_addr_width : string := "window_32_bit";
prefetchable_mem_window_addr_width : string := "prefetch_32";
skp_os_gen3_count_data : bit_vector := B"00000000000";
skp_os_gen3_count : string := "skp_os_gen3_count";
rx_cdc_almost_empty_data : bit_vector := B"0000";
rx_cdc_almost_empty : string := "rx_cdc_almost_empty";
tx_cdc_almost_empty_data : bit_vector := B"0000";
tx_cdc_almost_empty : string := "tx_cdc_almost_empty";
rx_cdc_almost_full_data : bit_vector := B"0000";
rx_cdc_almost_full : string := "rx_cdc_almost_full";
tx_cdc_almost_full_data : bit_vector := B"0000";
tx_cdc_almost_full : string := "tx_cdc_almost_full";
rx_l0s_count_idl_data : bit_vector := B"00000000";
rx_l0s_count_idl : string := "rx_l0s_count_idl";
cdc_dummy_insert_limit_data : bit_vector := B"0000";
cdc_dummy_insert_limit : string := "cdc_dummy_insert_limit";
ei_delay_powerdown_count_data : bit_vector := B"00001010";
ei_delay_powerdown_count : string := "ei_delay_powerdown_count";
millisecond_cycle_count_data : bit_vector := B"00000000000000000000";
millisecond_cycle_count : string := "millisecond_cycle_count";
skp_os_schedule_count_data : bit_vector := B"00000000000";
skp_os_schedule_count : string := "skp_os_schedule_count";
fc_init_timer_data : bit_vector := B"10000000000";
fc_init_timer : string := "fc_init_timer";
l01_entry_latency_data : bit_vector := B"11111";
l01_entry_latency : string := "l01_entry_latency";
flow_control_update_count_data : bit_vector := B"11110";
flow_control_update_count : string := "flow_control_update_count";
flow_control_timeout_count_data : bit_vector := B"11001000";
flow_control_timeout_count : string := "flow_control_timeout_count";
vc0_rx_flow_ctrl_posted_header_data : bit_vector := B"00110010";
vc0_rx_flow_ctrl_posted_header : string := "vc0_rx_flow_ctrl_posted_header";
vc0_rx_flow_ctrl_posted_data_data : bit_vector := B"000101101000";
vc0_rx_flow_ctrl_posted_data : string := "vc0_rx_flow_ctrl_posted_data";
vc0_rx_flow_ctrl_nonposted_header_data : bit_vector := B"00110110";
vc0_rx_flow_ctrl_nonposted_header : string := "vc0_rx_flow_ctrl_nonposted_header";
vc0_rx_flow_ctrl_nonposted_data_data : bit_vector := B"00000000";
vc0_rx_flow_ctrl_nonposted_data : string := "vc0_rx_flow_ctrl_nonposted_data";
vc0_rx_flow_ctrl_compl_header_data : bit_vector := B"01110000";
vc0_rx_flow_ctrl_compl_header : string := "vc0_rx_flow_ctrl_compl_header";
vc0_rx_flow_ctrl_compl_data_data : bit_vector := B"000111000000";
vc0_rx_flow_ctrl_compl_data : string := "vc0_rx_flow_ctrl_compl_data";
rx_ptr0_posted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_min : string := "rx_ptr0_posted_dpram_min";
rx_ptr0_posted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_max : string := "rx_ptr0_posted_dpram_max";
rx_ptr0_nonposted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_min : string := "rx_ptr0_nonposted_dpram_min";
rx_ptr0_nonposted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_max : string := "rx_ptr0_nonposted_dpram_max";
retry_buffer_last_active_address_data : bit_vector := B"1111111111";
retry_buffer_last_active_address : string := "retry_buffer_last_active_address";
retry_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
retry_buffer_memory_settings : string := "retry_buffer_memory_settings";
vc0_rx_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
vc0_rx_buffer_memory_settings : string := "vc0_rx_buffer_memory_settings";
bist_memory_settings_data : bit_vector := B"000000000000000000000000000000000000000000000000000000000000000000000000000";
bist_memory_settings : string := "bist_memory_settings";
credit_buffer_allocation_aux : string := "balanced";
iei_enable_settings : string := "gen2_infei_infsd_gen1_infei_sd";
vsec_id_data : bit_vector := B"0001000101110010";
vsec_id : string := "vsec_id";
cvp_rate_sel : string := "full_rate";
hard_reset_bypass : string := "false";
cvp_data_compressed : string := "false";
cvp_data_encrypted : string := "false";
cvp_mode_reset : string := "false";
cvp_clk_reset : string := "false";
vsec_cap_data : bit_vector := B"0000";
vsec_cap : string := "vsec_cap";
jtag_id_data : bit_vector := B"00000000000000000000000000000000";
jtag_id : string := "jtag_id";
user_id_data : bit_vector := B"0000000000000000";
user_id : string := "user_id";
cseb_extend_pci : string := "false";
cseb_extend_pcie : string := "false";
cseb_cpl_status_during_cvp : string := "config_retry_status";
cseb_route_to_avl_rx_st : string := "cseb";
cseb_config_bypass : string := "disable";
cseb_cpl_tag_checking : string := "enable";
cseb_bar_match_checking : string := "enable";
cseb_min_error_checking : string := "false";
cseb_temp_busy_crs : string := "completer_abort";
cseb_disable_auto_crs : string := "false";
gen3_diffclock_nfts_count_data : bit_vector := B"10000000";
gen3_diffclock_nfts_count : string := "g3_diffclock_nfts_count";
gen3_sameclock_nfts_count_data : bit_vector := B"10000000";
gen3_sameclock_nfts_count : string := "g3_sameclock_nfts_count";
gen3_coeff_errchk : string := "enable";
gen3_paritychk : string := "enable";
gen3_coeff_delay_count_data : bit_vector := B"1111101";
gen3_coeff_delay_count : string := "g3_coeff_dly_count";
gen3_coeff_1_data : bit_vector := B"000000000000000000";
gen3_coeff_1 : string := "g3_coeff_1";
gen3_coeff_1_sel : string := "coeff_1";
gen3_coeff_1_preset_hint_data : bit_vector := B"000";
gen3_coeff_1_preset_hint : string := "g3_coeff_1_prst_hint";
gen3_coeff_1_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_more : string := "g3_coeff_1_nxtber_more";
gen3_coeff_1_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_less : string := "g3_coeff_1_nxtber_less";
gen3_coeff_1_reqber_data : bit_vector := B"00000";
gen3_coeff_1_reqber : string := "g3_coeff_1_reqber";
gen3_coeff_1_ber_meas_data : bit_vector := B"000000";
gen3_coeff_1_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_2_data : bit_vector := B"000000000000000000";
gen3_coeff_2 : string := "g3_coeff_2";
gen3_coeff_2_sel : string := "coeff_2";
gen3_coeff_2_preset_hint_data : bit_vector := B"000";
gen3_coeff_2_preset_hint : string := "g3_coeff_2_prst_hint";
gen3_coeff_2_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_more : string := "g3_coeff_2_nxtber_more";
gen3_coeff_2_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_less : string := "g3_coeff_2_nxtber_less";
gen3_coeff_2_reqber_data : bit_vector := B"00000";
gen3_coeff_2_reqber : string := "g3_coeff_2_reqber";
gen3_coeff_2_ber_meas_data : bit_vector := B"000000";
gen3_coeff_2_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_3_data : bit_vector := B"000000000000000000";
gen3_coeff_3 : string := "g3_coeff_3";
gen3_coeff_3_sel : string := "coeff_3";
gen3_coeff_3_preset_hint_data : bit_vector := B"000";
gen3_coeff_3_preset_hint : string := "g3_coeff_3_prst_hint";
gen3_coeff_3_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_more : string := "g3_coeff_3_nxtber_more";
gen3_coeff_3_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_less : string := "g3_coeff_3_nxtber_less";
gen3_coeff_3_reqber_data : bit_vector := B"00000";
gen3_coeff_3_reqber : string := "g3_coeff_3_reqber";
gen3_coeff_3_ber_meas_data : bit_vector := B"000000";
gen3_coeff_3_ber_meas : string := "g3_coeff_3_ber_meas";
gen3_coeff_4_data : bit_vector := B"000000000000000000";
gen3_coeff_4 : string := "g3_coeff_4";
gen3_coeff_4_sel : string := "coeff_4";
gen3_coeff_4_preset_hint_data : bit_vector := B"000";
gen3_coeff_4_preset_hint : string := "g3_coeff_4_prst_hint";
gen3_coeff_4_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_more : string := "g3_coeff_4_nxtber_more";
gen3_coeff_4_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_less : string := "g3_coeff_4_nxtber_less";
gen3_coeff_4_reqber_data : bit_vector := B"00000";
gen3_coeff_4_reqber : string := "g3_coeff_4_reqber";
gen3_coeff_4_ber_meas_data : bit_vector := B"000000";
gen3_coeff_4_ber_meas : string := "g3_coeff_4_ber_meas";
gen3_coeff_5_data : bit_vector := B"000000000000000000";
gen3_coeff_5 : string := "g3_coeff_5";
gen3_coeff_5_sel : string := "coeff_5";
gen3_coeff_5_preset_hint_data : bit_vector := B"000";
gen3_coeff_5_preset_hint : string := "g3_coeff_5_prst_hint";
gen3_coeff_5_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_more : string := "g3_coeff_5_nxtber_more";
gen3_coeff_5_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_less : string := "g3_coeff_5_nxtber_less";
gen3_coeff_5_reqber_data : bit_vector := B"00000";
gen3_coeff_5_reqber : string := "g3_coeff_5_reqber";
gen3_coeff_5_ber_meas_data : bit_vector := B"000000";
gen3_coeff_5_ber_meas : string := "g3_coeff_5_ber_meas";
gen3_coeff_6_data : bit_vector := B"000000000000000000";
gen3_coeff_6 : string := "g3_coeff_6";
gen3_coeff_6_sel : string := "coeff_6";
gen3_coeff_6_preset_hint_data : bit_vector := B"000";
gen3_coeff_6_preset_hint : string := "g3_coeff_6_prst_hint";
gen3_coeff_6_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_more : string := "g3_coeff_6_nxtber_more";
gen3_coeff_6_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_less : string := "g3_coeff_6_nxtber_less";
gen3_coeff_6_reqber_data : bit_vector := B"00000";
gen3_coeff_6_reqber : string := "g3_coeff_6_reqber";
gen3_coeff_6_ber_meas_data : bit_vector := B"000000";
gen3_coeff_6_ber_meas : string := "g3_coeff_6_ber_meas";
gen3_coeff_7_data : bit_vector := B"000000000000000000";
gen3_coeff_7 : string := "g3_coeff_7";
gen3_coeff_7_sel : string := "coeff_7";
gen3_coeff_7_preset_hint_data : bit_vector := B"000";
gen3_coeff_7_preset_hint : string := "g3_coeff_7_prst_hint";
gen3_coeff_7_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_more : string := "g3_coeff_7_nxtber_more";
gen3_coeff_7_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_less : string := "g3_coeff_7_nxtber_less";
gen3_coeff_7_reqber_data : bit_vector := B"00000";
gen3_coeff_7_reqber : string := "g3_coeff_7_reqber";
gen3_coeff_7_ber_meas_data : bit_vector := B"000000";
gen3_coeff_7_ber_meas : string := "g3_coeff_7_ber_meas";
gen3_coeff_8_data : bit_vector := B"000000000000000000";
gen3_coeff_8 : string := "g3_coeff_8";
gen3_coeff_8_sel : string := "coeff_8";
gen3_coeff_8_preset_hint_data : bit_vector := B"000";
gen3_coeff_8_preset_hint : string := "g3_coeff_8_prst_hint";
gen3_coeff_8_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_more : string := "g3_coeff_8_nxtber_more";
gen3_coeff_8_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_less : string := "g3_coeff_8_nxtber_less";
gen3_coeff_8_reqber_data : bit_vector := B"00000";
gen3_coeff_8_reqber : string := "g3_coeff_8_reqber";
gen3_coeff_8_ber_meas_data : bit_vector := B"000000";
gen3_coeff_8_ber_meas : string := "g3_coeff_8_ber_meas";
gen3_coeff_9_data : bit_vector := B"000000000000000000";
gen3_coeff_9 : string := "g3_coeff_9";
gen3_coeff_9_sel : string := "coeff_9";
gen3_coeff_9_preset_hint_data : bit_vector := B"000";
gen3_coeff_9_preset_hint : string := "g3_coeff_9_prst_hint";
gen3_coeff_9_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_more : string := "g3_coeff_9_nxtber_more";
gen3_coeff_9_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_less : string := "g3_coeff_9_nxtber_less";
gen3_coeff_9_reqber_data : bit_vector := B"00000";
gen3_coeff_9_reqber : string := "g3_coeff_9_reqber";
gen3_coeff_9_ber_meas_data : bit_vector := B"000000";
gen3_coeff_9_ber_meas : string := "g3_coeff_9_ber_meas";
gen3_coeff_10_data : bit_vector := B"000000000000000000";
gen3_coeff_10 : string := "g3_coeff_10";
gen3_coeff_10_sel : string := "coeff_10";
gen3_coeff_10_preset_hint_data : bit_vector := B"000";
gen3_coeff_10_preset_hint : string := "g3_coeff_10_prst_hint";
gen3_coeff_10_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_more : string := "g3_coeff_10_nxtber_more";
gen3_coeff_10_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_less : string := "g3_coeff_10_nxtber_less";
gen3_coeff_10_reqber_data : bit_vector := B"00000";
gen3_coeff_10_reqber : string := "g3_coeff_10_reqber";
gen3_coeff_10_ber_meas_data : bit_vector := B"000000";
gen3_coeff_10_ber_meas : string := "g3_coeff_10_ber_meas";
gen3_coeff_11_data : bit_vector := B"000000000000000000";
gen3_coeff_11 : string := "g3_coeff_11";
gen3_coeff_11_sel : string := "coeff_11";
gen3_coeff_11_preset_hint_data : bit_vector := B"000";
gen3_coeff_11_preset_hint : string := "g3_coeff_11_prst_hint";
gen3_coeff_11_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_more : string := "g3_coeff_11_nxtber_more";
gen3_coeff_11_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_less : string := "g3_coeff_11_nxtber_less";
gen3_coeff_11_reqber_data : bit_vector := B"00000";
gen3_coeff_11_reqber : string := "g3_coeff_11_reqber";
gen3_coeff_11_ber_meas_data : bit_vector := B"000000";
gen3_coeff_11_ber_meas : string := "g3_coeff_11_ber_meas";
gen3_coeff_12_data : bit_vector := B"000000000000000000";
gen3_coeff_12 : string := "g3_coeff_12";
gen3_coeff_12_sel : string := "coeff_12";
gen3_coeff_12_preset_hint_data : bit_vector := B"000";
gen3_coeff_12_preset_hint : string := "g3_coeff_12_prst_hint";
gen3_coeff_12_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_more : string := "g3_coeff_12_nxtber_more";
gen3_coeff_12_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_less : string := "g3_coeff_12_nxtber_less";
gen3_coeff_12_reqber_data : bit_vector := B"00000";
gen3_coeff_12_reqber : string := "g3_coeff_12_reqber";
gen3_coeff_12_ber_meas_data : bit_vector := B"000000";
gen3_coeff_12_ber_meas : string := "g3_coeff_12_ber_meas";
gen3_coeff_13_data : bit_vector := B"000000000000000000";
gen3_coeff_13 : string := "g3_coeff_13";
gen3_coeff_13_sel : string := "coeff_13";
gen3_coeff_13_preset_hint_data : bit_vector := B"000";
gen3_coeff_13_preset_hint : string := "g3_coeff_13_prst_hint";
gen3_coeff_13_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_more : string := "g3_coeff_13_nxtber_more";
gen3_coeff_13_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_less : string := "g3_coeff_13_nxtber_less";
gen3_coeff_13_reqber_data : bit_vector := B"00000";
gen3_coeff_13_reqber : string := "g3_coeff_13_reqber";
gen3_coeff_13_ber_meas_data : bit_vector := B"000000";
gen3_coeff_13_ber_meas : string := "g3_coeff_13_ber_meas";
gen3_coeff_14_data : bit_vector := B"000000000000000000";
gen3_coeff_14 : string := "g3_coeff_14";
gen3_coeff_14_sel : string := "coeff_14";
gen3_coeff_14_preset_hint_data : bit_vector := B"000";
gen3_coeff_14_preset_hint : string := "g3_coeff_14_prst_hint";
gen3_coeff_14_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_more : string := "g3_coeff_14_nxtber_more";
gen3_coeff_14_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_less : string := "g3_coeff_14_nxtber_less";
gen3_coeff_14_reqber_data : bit_vector := B"00000";
gen3_coeff_14_reqber : string := "g3_coeff_14_reqber";
gen3_coeff_14_ber_meas_data : bit_vector := B"000000";
gen3_coeff_14_ber_meas : string := "g3_coeff_14_ber_meas";
gen3_coeff_15_data : bit_vector := B"000000000000000000";
gen3_coeff_15 : string := "g3_coeff_15";
gen3_coeff_15_sel : string := "coeff_15";
gen3_coeff_15_preset_hint_data : bit_vector := B"000";
gen3_coeff_15_preset_hint : string := "g3_coeff_15_prst_hint";
gen3_coeff_15_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_more : string := "g3_coeff_15_nxtber_more";
gen3_coeff_15_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_less : string := "g3_coeff_15_nxtber_less";
gen3_coeff_15_reqber_data : bit_vector := B"00000";
gen3_coeff_15_reqber : string := "g3_coeff_15_reqber";
gen3_coeff_15_ber_meas_data : bit_vector := B"000000";
gen3_coeff_15_ber_meas : string := "g3_coeff_15_ber_meas";
gen3_coeff_16_data : bit_vector := B"000000000000000000";
gen3_coeff_16 : string := "g3_coeff_16";
gen3_coeff_16_sel : string := "coeff_16";
gen3_coeff_16_preset_hint_data : bit_vector := B"000";
gen3_coeff_16_preset_hint : string := "g3_coeff_16_prst_hint";
gen3_coeff_16_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_more : string := "g3_coeff_16_nxtber_more";
gen3_coeff_16_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_less : string := "g3_coeff_16_nxtber_less";
gen3_coeff_16_reqber_data : bit_vector := B"00000";
gen3_coeff_16_reqber : string := "g3_coeff_16_reqber";
gen3_coeff_16_ber_meas_data : bit_vector := B"000000";
gen3_coeff_16_ber_meas : string := "g3_coeff_16_ber_meas";
gen3_preset_coeff_1_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_1 : string := "g3_prst_coeff_1";
gen3_preset_coeff_2_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_2 : string := "g3_prst_coeff_2";
gen3_preset_coeff_3_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_3 : string := "g3_prst_coeff_3";
gen3_preset_coeff_4_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_4 : string := "g3_prst_coeff_4";
gen3_preset_coeff_5_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_5 : string := "g3_prst_coeff_5";
gen3_preset_coeff_6_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_6 : string := "g3_prst_coeff_6";
gen3_preset_coeff_7_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_7 : string := "g3_prst_coeff_7";
gen3_preset_coeff_8_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_8 : string := "g3_prst_coeff_8";
gen3_preset_coeff_9_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_9 : string := "g3_prst_coeff_9";
gen3_preset_coeff_10_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_10 : string := "g3_prst_coeff_10";
gen3_rxfreqlock_counter_data : bit_vector := "00000000000000000000";
gen3_rxfreqlock_counter : string := "g3_rxfreqlock_count";
rstctrl_pld_clr : string := "false";-- "false", "true".
rstctrl_debug_en : string := "false";-- "false", "true".
rstctrl_force_inactive_rst : string := "false";-- "false", "true".
rstctrl_perst_enable : string := "level";-- "level", "neg_edge", "not_used".
hrdrstctrl_en : string := "hrdrstctrl_dis";--"hrdrstctrl_dis", "hrdrstctrl_en".
rstctrl_hip_ep : string := "hip_ep"; --"hip_ep", "hip_not_ep".
rstctrl_hard_block_enable : string := "hard_rst_ctl";--"hard_rst_ctl", "pld_rst_ctl".
rstctrl_rx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_tx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_rx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_crst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_srst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pma_syncp_inv : string := "false";--"false", "true".
rstctrl_1us_count_fref_clk : string := "rstctrl_1us_cnt";--
rstctrl_1us_count_fref_clk_value : bit_vector := B"00000000000000111111";--
rstctrl_1ms_count_fref_clk : string := "rstctrl_1ms_cnt";--
rstctrl_1ms_count_fref_clk_value : bit_vector := B"00001111010000100100";--
rstctrl_off_cal_done_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_rx_pma_rstb_cmu_select : string := "not_active";-- "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
rstctrl_rx_pll_freq_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
rstctrl_mask_tx_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_rx_pll_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_perstn_select : string := "perstn_pin";-- "perstn_pin", "perstn_pld".
rstctrl_tx_lc_pll_rstb_select : string := "not_active";-- "ch1_out", "ch7_out", "not_active".
rstctrl_fref_clk_select : string := "ch0_sel";-- "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
rstctrl_off_cal_en_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
rstctrl_tx_pma_syncp_select : string := "not_active";-- "ch1_out", "ch4_out", "ch4_10_out", "not_active".
rstctrl_rx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_cmu_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_tx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_lc_pll_lock_select : string := "not_active";-- "ch1_sel", "ch7_sel", "not_active".
rstctrl_timer_a : string := "rstctrl_timer_a";
rstctrl_timer_a_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_a_value : bit_vector := B"00000001" ;
rstctrl_timer_b : string := "rstctrl_timer_b";
rstctrl_timer_b_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_b_value : bit_vector := B"00000001";
rstctrl_timer_c : string := "rstctrl_timer_c";
rstctrl_timer_c_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_c_value : bit_vector := B"00000001";
rstctrl_timer_d : string := "rstctrl_timer_d";
rstctrl_timer_d_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_d_value : bit_vector := B"00000001";
rstctrl_timer_e : string := "rstctrl_timer_e";
rstctrl_timer_e_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_e_value : bit_vector := B"00000001";
rstctrl_timer_f : string := "rstctrl_timer_f";
rstctrl_timer_f_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_f_value : bit_vector := B"00000001";
rstctrl_timer_g : string := "rstctrl_timer_g";
rstctrl_timer_g_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_g_value : bit_vector := B"00000001";
rstctrl_timer_h : string := "rstctrl_timer_h";
rstctrl_timer_h_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_h_value : bit_vector := B"00000001";
rstctrl_timer_i : string := "rstctrl_timer_i";
rstctrl_timer_i_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_i_value : bit_vector := B"00000001";
rstctrl_timer_j : string := "rstctrl_timer_j";
rstctrl_timer_j_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_j_value : bit_vector := B"00000001"
);
port (
dpriostatus : out std_logic_vector(15 downto 0);
lmidout : out std_logic_vector(31 downto 0);
lmiack : out std_logic_vector(0 downto 0);
lmirden : in std_logic_vector(0 downto 0);
lmiwren : in std_logic_vector(0 downto 0);
lmiaddr : in std_logic_vector(11 downto 0);
lmidin : in std_logic_vector(31 downto 0);
flrreset : in std_logic_vector(0 downto 0);
flrsts : out std_logic_vector(0 downto 0);
resetstatus : out std_logic_vector(0 downto 0);
l2exit : out std_logic_vector(0 downto 0);
hotrstexit : out std_logic_vector(0 downto 0);
hiphardreset : in std_logic_vector(0 downto 0);
dlupexit : out std_logic_vector(0 downto 0);
coreclkout : out std_logic_vector(0 downto 0);
pldclk : in std_logic_vector(0 downto 0);
pldsrst : in std_logic_vector(0 downto 0);
pldrst : in std_logic_vector(0 downto 0);
pclkch0 : in std_logic_vector(0 downto 0);
pclkch1 : in std_logic_vector(0 downto 0);
pclkcentral : in std_logic_vector(0 downto 0);
pllfixedclkch0 : in std_logic_vector(0 downto 0);
pllfixedclkch1 : in std_logic_vector(0 downto 0);
pllfixedclkcentral : in std_logic_vector(0 downto 0);
phyrst : in std_logic_vector(0 downto 0);
physrst : in std_logic_vector(0 downto 0);
coreclkin : in std_logic_vector(0 downto 0);
corerst : in std_logic_vector(0 downto 0);
corepor : in std_logic_vector(0 downto 0);
corecrst : in std_logic_vector(0 downto 0);
coresrst : in std_logic_vector(0 downto 0);
swdnout : out std_logic_vector(6 downto 0);
swupout : out std_logic_vector(2 downto 0);
swdnin : in std_logic_vector(2 downto 0);
swupin : in std_logic_vector(6 downto 0);
swctmod : in std_logic_vector(1 downto 0);
rxstdata : out std_logic_vector(255 downto 0);
rxstparity : out std_logic_vector(31 downto 0);
rxstbe : out std_logic_vector(31 downto 0);
rxsterr : out std_logic_vector(3 downto 0);
rxstsop : out std_logic_vector(3 downto 0);
rxsteop : out std_logic_vector(3 downto 0);
rxstempty : out std_logic_vector(1 downto 0);
rxstvalid : out std_logic_vector(3 downto 0);
rxstbardec1 : out std_logic_vector(7 downto 0);
rxstbardec2 : out std_logic_vector(7 downto 0);
rxstmask : in std_logic_vector(0 downto 0);
rxstready : in std_logic_vector(0 downto 0);
txstready : out std_logic_vector(0 downto 0);
txcredfchipcons : out std_logic_vector(5 downto 0);
txcredfcinfinite : out std_logic_vector(5 downto 0);
txcredhdrfcp : out std_logic_vector(7 downto 0);
txcreddatafcp : out std_logic_vector(11 downto 0);
txcredhdrfcnp : out std_logic_vector(7 downto 0);
txcreddatafcnp : out std_logic_vector(11 downto 0);
txcredhdrfccp : out std_logic_vector(7 downto 0);
txcreddatafccp : out std_logic_vector(11 downto 0);
txstdata : in std_logic_vector(255 downto 0);
txstparity : in std_logic_vector(31 downto 0);
txsterr : in std_logic_vector(3 downto 0);
txstsop : in std_logic_vector(3 downto 0);
txsteop : in std_logic_vector(3 downto 0);
txstempty : in std_logic_vector(1 downto 0);
txstvalid : in std_logic_vector(0 downto 0);
r2cuncecc : out std_logic_vector(0 downto 0);
rxcorrecc : out std_logic_vector(0 downto 0);
retryuncecc : out std_logic_vector(0 downto 0);
retrycorrecc : out std_logic_vector(0 downto 0);
rxparerr : out std_logic_vector(0 downto 0);
txparerr : out std_logic_vector(1 downto 0);
r2cparerr : out std_logic_vector(0 downto 0);
pmetosr : out std_logic_vector(0 downto 0);
pmetocr : in std_logic_vector(0 downto 0);
pmevent : in std_logic_vector(0 downto 0);
pmdata : in std_logic_vector(9 downto 0);
pmauxpwr : in std_logic_vector(0 downto 0);
tlcfgsts : out std_logic_vector(52 downto 0);
tlcfgctl : out std_logic_vector(31 downto 0);
tlcfgadd : out std_logic_vector(3 downto 0);
appintaack : out std_logic_vector(0 downto 0);
appintasts : in std_logic_vector(0 downto 0);
intstatus : out std_logic_vector(3 downto 0);
appmsiack : out std_logic_vector(0 downto 0);
appmsireq : in std_logic_vector(0 downto 0);
appmsitc : in std_logic_vector(2 downto 0);
appmsinum : in std_logic_vector(4 downto 0);
aermsinum : in std_logic_vector(4 downto 0);
pexmsinum : in std_logic_vector(4 downto 0);
hpgctrler : in std_logic_vector(4 downto 0);
cfglink2csrpld : in std_logic_vector(12 downto 0);
cfgprmbuspld : in std_logic_vector(7 downto 0);
csebisshadow : out std_logic_vector(0 downto 0);
csebwrdata : out std_logic_vector(31 downto 0);
csebwrdataparity : out std_logic_vector(3 downto 0);
csebbe : out std_logic_vector(3 downto 0);
csebaddr : out std_logic_vector(32 downto 0);
csebaddrparity : out std_logic_vector(4 downto 0);
csebwren : out std_logic_vector(0 downto 0);
csebrden : out std_logic_vector(0 downto 0);
csebwrrespreq : out std_logic_vector(0 downto 0);
csebrddata : in std_logic_vector(31 downto 0);
csebrddataparity : in std_logic_vector(3 downto 0);
csebwaitrequest : in std_logic_vector(0 downto 0);
csebwrrespvalid : in std_logic_vector(0 downto 0);
csebwrresponse : in std_logic_vector(4 downto 0);
csebrdresponse : in std_logic_vector(4 downto 0);
dlup : out std_logic_vector(0 downto 0);
testouthip : out std_logic_vector(255 downto 0);
testout1hip : out std_logic_vector(63 downto 0);
ev1us : out std_logic_vector(0 downto 0);
ev128ns : out std_logic_vector(0 downto 0);
wakeoen : out std_logic_vector(0 downto 0);
serrout : out std_logic_vector(0 downto 0);
ltssmstate : out std_logic_vector(4 downto 0);
laneact : out std_logic_vector(3 downto 0);
currentspeed : out std_logic_vector(1 downto 0);
slotclkcfg : in std_logic_vector(0 downto 0);
mode : in std_logic_vector(1 downto 0);
testinhip : in std_logic_vector(31 downto 0);
testin1hip : in std_logic_vector(31 downto 0);
cplpending : in std_logic_vector(0 downto 0);
cplerr : in std_logic_vector(6 downto 0);
appinterr : in std_logic_vector(1 downto 0);
egressblkerr : in std_logic_vector(0 downto 0);
pmexitd0ack : in std_logic_vector(0 downto 0);
pmexitd0req : out std_logic_vector(0 downto 0);
currentcoeff0 : out std_logic_vector(17 downto 0);
currentcoeff1 : out std_logic_vector(17 downto 0);
currentcoeff2 : out std_logic_vector(17 downto 0);
currentcoeff3 : out std_logic_vector(17 downto 0);
currentcoeff4 : out std_logic_vector(17 downto 0);
currentcoeff5 : out std_logic_vector(17 downto 0);
currentcoeff6 : out std_logic_vector(17 downto 0);
currentcoeff7 : out std_logic_vector(17 downto 0);
currentrxpreset0 : out std_logic_vector(2 downto 0);
currentrxpreset1 : out std_logic_vector(2 downto 0);
currentrxpreset2 : out std_logic_vector(2 downto 0);
currentrxpreset3 : out std_logic_vector(2 downto 0);
currentrxpreset4 : out std_logic_vector(2 downto 0);
currentrxpreset5 : out std_logic_vector(2 downto 0);
currentrxpreset6 : out std_logic_vector(2 downto 0);
currentrxpreset7 : out std_logic_vector(2 downto 0);
rate0 : out std_logic_vector(1 downto 0);
rate1 : out std_logic_vector(1 downto 0);
rate2 : out std_logic_vector(1 downto 0);
rate3 : out std_logic_vector(1 downto 0);
rate4 : out std_logic_vector(1 downto 0);
rate5 : out std_logic_vector(1 downto 0);
rate6 : out std_logic_vector(1 downto 0);
rate7 : out std_logic_vector(1 downto 0);
ratectrl : out std_logic_vector(1 downto 0);
ratetiedtognd : out std_logic_vector(0 downto 0);
eidleinfersel0 : out std_logic_vector(2 downto 0);
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
eidleinfersel4 : out std_logic_vector(2 downto 0);
eidleinfersel5 : out std_logic_vector(2 downto 0);
eidleinfersel6 : out std_logic_vector(2 downto 0);
eidleinfersel7 : out std_logic_vector(2 downto 0);
txdata0 : out std_logic_vector(31 downto 0);
txdatak0 : out std_logic_vector(3 downto 0);
txdetectrx0 : out std_logic_vector(0 downto 0);
txelecidle0 : out std_logic_vector(0 downto 0);
txcompl0 : out std_logic_vector(0 downto 0);
rxpolarity0 : out std_logic_vector(0 downto 0);
powerdown0 : out std_logic_vector(1 downto 0);
txdataskip0 : out std_logic_vector(0 downto 0);
txblkst0 : out std_logic_vector(0 downto 0);
txsynchd0 : out std_logic_vector(1 downto 0);
txdeemph0 : out std_logic_vector(0 downto 0);
txmargin0 : out std_logic_vector(2 downto 0);
rxdata0 : in std_logic_vector(31 downto 0);
rxdatak0 : in std_logic_vector(3 downto 0);
rxvalid0 : in std_logic_vector(0 downto 0);
phystatus0 : in std_logic_vector(0 downto 0);
rxelecidle0 : in std_logic_vector(0 downto 0);
rxstatus0 : in std_logic_vector(2 downto 0);
rxdataskip0 : in std_logic_vector(0 downto 0);
rxblkst0 : in std_logic_vector(0 downto 0);
rxsynchd0 : in std_logic_vector(1 downto 0);
rxfreqlocked0 : in std_logic_vector(0 downto 0);
txdata1 : out std_logic_vector(31 downto 0);
txdatak1 : out std_logic_vector(3 downto 0);
txdetectrx1 : out std_logic_vector(0 downto 0);
txelecidle1 : out std_logic_vector(0 downto 0);
txcompl1 : out std_logic_vector(0 downto 0);
rxpolarity1 : out std_logic_vector(0 downto 0);
powerdown1 : out std_logic_vector(1 downto 0);
txdataskip1 : out std_logic_vector(0 downto 0);
txblkst1 : out std_logic_vector(0 downto 0);
txsynchd1 : out std_logic_vector(1 downto 0);
txdeemph1 : out std_logic_vector(0 downto 0);
txmargin1 : out std_logic_vector(2 downto 0);
rxdata1 : in std_logic_vector(31 downto 0);
rxdatak1 : in std_logic_vector(3 downto 0);
rxvalid1 : in std_logic_vector(0 downto 0);
phystatus1 : in std_logic_vector(0 downto 0);
rxelecidle1 : in std_logic_vector(0 downto 0);
rxstatus1 : in std_logic_vector(2 downto 0);
rxdataskip1 : in std_logic_vector(0 downto 0);
rxblkst1 : in std_logic_vector(0 downto 0);
rxsynchd1 : in std_logic_vector(1 downto 0);
rxfreqlocked1 : in std_logic_vector(0 downto 0);
txdata2 : out std_logic_vector(31 downto 0);
txdatak2 : out std_logic_vector(3 downto 0);
txdetectrx2 : out std_logic_vector(0 downto 0);
txelecidle2 : out std_logic_vector(0 downto 0);
txcompl2 : out std_logic_vector(0 downto 0);
rxpolarity2 : out std_logic_vector(0 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
txdataskip2 : out std_logic_vector(0 downto 0);
txblkst2 : out std_logic_vector(0 downto 0);
txsynchd2 : out std_logic_vector(1 downto 0);
txdeemph2 : out std_logic_vector(0 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
rxdata2 : in std_logic_vector(31 downto 0);
rxdatak2 : in std_logic_vector(3 downto 0);
rxvalid2 : in std_logic_vector(0 downto 0);
phystatus2 : in std_logic_vector(0 downto 0);
rxelecidle2 : in std_logic_vector(0 downto 0);
rxstatus2 : in std_logic_vector(2 downto 0);
rxdataskip2 : in std_logic_vector(0 downto 0);
rxblkst2 : in std_logic_vector(0 downto 0);
rxsynchd2 : in std_logic_vector(1 downto 0);
rxfreqlocked2 : in std_logic_vector(0 downto 0);
txdata3 : out std_logic_vector(31 downto 0);
txdatak3 : out std_logic_vector(3 downto 0);
txdetectrx3 : out std_logic_vector(0 downto 0);
txelecidle3 : out std_logic_vector(0 downto 0);
txcompl3 : out std_logic_vector(0 downto 0);
rxpolarity3 : out std_logic_vector(0 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
txdataskip3 : out std_logic_vector(0 downto 0);
txblkst3 : out std_logic_vector(0 downto 0);
txsynchd3 : out std_logic_vector(1 downto 0);
txdeemph3 : out std_logic_vector(0 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
rxdata3 : in std_logic_vector(31 downto 0);
rxdatak3 : in std_logic_vector(3 downto 0);
rxvalid3 : in std_logic_vector(0 downto 0);
phystatus3 : in std_logic_vector(0 downto 0);
rxelecidle3 : in std_logic_vector(0 downto 0);
rxstatus3 : in std_logic_vector(2 downto 0);
rxdataskip3 : in std_logic_vector(0 downto 0);
rxblkst3 : in std_logic_vector(0 downto 0);
rxsynchd3 : in std_logic_vector(1 downto 0);
rxfreqlocked3 : in std_logic_vector(0 downto 0);
txdata4 : out std_logic_vector(31 downto 0);
txdatak4 : out std_logic_vector(3 downto 0);
txdetectrx4 : out std_logic_vector(0 downto 0);
txelecidle4 : out std_logic_vector(0 downto 0);
txcompl4 : out std_logic_vector(0 downto 0);
rxpolarity4 : out std_logic_vector(0 downto 0);
powerdown4 : out std_logic_vector(1 downto 0);
txdataskip4 : out std_logic_vector(0 downto 0);
txblkst4 : out std_logic_vector(0 downto 0);
txsynchd4 : out std_logic_vector(1 downto 0);
txdeemph4 : out std_logic_vector(0 downto 0);
txmargin4 : out std_logic_vector(2 downto 0);
rxdata4 : in std_logic_vector(31 downto 0);
rxdatak4 : in std_logic_vector(3 downto 0);
rxvalid4 : in std_logic_vector(0 downto 0);
phystatus4 : in std_logic_vector(0 downto 0);
rxelecidle4 : in std_logic_vector(0 downto 0);
rxstatus4 : in std_logic_vector(2 downto 0);
rxdataskip4 : in std_logic_vector(0 downto 0);
rxblkst4 : in std_logic_vector(0 downto 0);
rxsynchd4 : in std_logic_vector(1 downto 0);
rxfreqlocked4 : in std_logic_vector(0 downto 0);
txdata5 : out std_logic_vector(31 downto 0);
txdatak5 : out std_logic_vector(3 downto 0);
txdetectrx5 : out std_logic_vector(0 downto 0);
txelecidle5 : out std_logic_vector(0 downto 0);
txcompl5 : out std_logic_vector(0 downto 0);
rxpolarity5 : out std_logic_vector(0 downto 0);
powerdown5 : out std_logic_vector(1 downto 0);
txdataskip5 : out std_logic_vector(0 downto 0);
txblkst5 : out std_logic_vector(0 downto 0);
txsynchd5 : out std_logic_vector(1 downto 0);
txdeemph5 : out std_logic_vector(0 downto 0);
txmargin5 : out std_logic_vector(2 downto 0);
rxdata5 : in std_logic_vector(31 downto 0);
rxdatak5 : in std_logic_vector(3 downto 0);
rxvalid5 : in std_logic_vector(0 downto 0);
phystatus5 : in std_logic_vector(0 downto 0);
rxelecidle5 : in std_logic_vector(0 downto 0);
rxstatus5 : in std_logic_vector(2 downto 0);
rxdataskip5 : in std_logic_vector(0 downto 0);
rxblkst5 : in std_logic_vector(0 downto 0);
rxsynchd5 : in std_logic_vector(1 downto 0);
rxfreqlocked5 : in std_logic_vector(0 downto 0);
txdata6 : out std_logic_vector(31 downto 0);
txdatak6 : out std_logic_vector(3 downto 0);
txdetectrx6 : out std_logic_vector(0 downto 0);
txelecidle6 : out std_logic_vector(0 downto 0);
txcompl6 : out std_logic_vector(0 downto 0);
rxpolarity6 : out std_logic_vector(0 downto 0);
powerdown6 : out std_logic_vector(1 downto 0);
txdataskip6 : out std_logic_vector(0 downto 0);
txblkst6 : out std_logic_vector(0 downto 0);
txsynchd6 : out std_logic_vector(1 downto 0);
txdeemph6 : out std_logic_vector(0 downto 0);
txmargin6 : out std_logic_vector(2 downto 0);
rxdata6 : in std_logic_vector(31 downto 0);
rxdatak6 : in std_logic_vector(3 downto 0);
rxvalid6 : in std_logic_vector(0 downto 0);
phystatus6 : in std_logic_vector(0 downto 0);
rxelecidle6 : in std_logic_vector(0 downto 0);
rxstatus6 : in std_logic_vector(2 downto 0);
rxdataskip6 : in std_logic_vector(0 downto 0);
rxblkst6 : in std_logic_vector(0 downto 0);
rxsynchd6 : in std_logic_vector(1 downto 0);
rxfreqlocked6 : in std_logic_vector(0 downto 0);
txdata7 : out std_logic_vector(31 downto 0);
txdatak7 : out std_logic_vector(3 downto 0);
txdetectrx7 : out std_logic_vector(0 downto 0);
txelecidle7 : out std_logic_vector(0 downto 0);
txcompl7 : out std_logic_vector(0 downto 0);
rxpolarity7 : out std_logic_vector(0 downto 0);
powerdown7 : out std_logic_vector(1 downto 0);
txdataskip7 : out std_logic_vector(0 downto 0);
txblkst7 : out std_logic_vector(0 downto 0);
txsynchd7 : out std_logic_vector(1 downto 0);
txdeemph7 : out std_logic_vector(0 downto 0);
txmargin7 : out std_logic_vector(2 downto 0);
rxdata7 : in std_logic_vector(31 downto 0);
rxdatak7 : in std_logic_vector(3 downto 0);
rxvalid7 : in std_logic_vector(0 downto 0);
phystatus7 : in std_logic_vector(0 downto 0);
rxelecidle7 : in std_logic_vector(0 downto 0);
rxstatus7 : in std_logic_vector(2 downto 0);
rxdataskip7 : in std_logic_vector(0 downto 0);
rxblkst7 : in std_logic_vector(0 downto 0);
rxsynchd7 : in std_logic_vector(1 downto 0);
rxfreqlocked7 : in std_logic_vector(0 downto 0);
dbgpipex1rx : in std_logic_vector(43 downto 0);
memredsclk : in std_logic_vector(0 downto 0);
memredenscan : in std_logic_vector(0 downto 0);
memredscen : in std_logic_vector(0 downto 0);
memredscin : in std_logic_vector(0 downto 0);
memredscsel : in std_logic_vector(0 downto 0);
memredscrst : in std_logic_vector(0 downto 0);
memredscout : out std_logic_vector(0 downto 0);
memregscanen : in std_logic_vector(0 downto 0);
memregscanin : in std_logic_vector(0 downto 0);
memhiptestenable : in std_logic_vector(0 downto 0);
memregscanout : out std_logic_vector(0 downto 0);
bisttesten : in std_logic_vector(0 downto 0);
bistenrpl : in std_logic_vector(0 downto 0);
bistscanin : in std_logic_vector(0 downto 0);
bistscanen : in std_logic_vector(0 downto 0);
bistenrcv : in std_logic_vector(0 downto 0);
bistscanoutrpl : out std_logic_vector(0 downto 0);
bistdonearpl : out std_logic_vector(0 downto 0);
bistdonebrpl : out std_logic_vector(0 downto 0);
bistpassrpl : out std_logic_vector(0 downto 0);
derrrpl : out std_logic_vector(0 downto 0);
derrcorextrpl : out std_logic_vector(0 downto 0);
bistscanoutrcv : out std_logic_vector(0 downto 0);
bistdonearcv : out std_logic_vector(0 downto 0);
bistdonebrcv : out std_logic_vector(0 downto 0);
bistpassrcv : out std_logic_vector(0 downto 0);
derrcorextrcv : out std_logic_vector(0 downto 0);
bistscanoutrcv1 : out std_logic_vector(0 downto 0);
bistdonearcv1 : out std_logic_vector(0 downto 0);
bistdonebrcv1 : out std_logic_vector(0 downto 0);
bistpassrcv1 : out std_logic_vector(0 downto 0);
derrcorextrcv1 : out std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
nfrzdrv : in std_logic_vector(0 downto 0);
frzreg : in std_logic_vector(0 downto 0);
frzlogic : in std_logic_vector(0 downto 0);
idrpl : in std_logic_vector(7 downto 0);
idrcv : in std_logic_vector(7 downto 0);
plniotri : in std_logic_vector(0 downto 0);
entest : in std_logic_vector(0 downto 0);
npor : in std_logic_vector(0 downto 0);
usermode : in std_logic_vector(0 downto 0);
cvpclk : out std_logic_vector(0 downto 0);
cvpdata : out std_logic_vector(31 downto 0);
cvpstartxfer : out std_logic_vector(0 downto 0);
cvpconfig : out std_logic_vector(0 downto 0);
cvpfullconfig : out std_logic_vector(0 downto 0);
cvpconfigready : in std_logic_vector(0 downto 0);
cvpen : in std_logic_vector(0 downto 0);
cvpconfigerror : in std_logic_vector(0 downto 0);
cvpconfigdone : in std_logic_vector(0 downto 0);
pinperstn : in std_logic_vector(0 downto 0);
pldperstn : in std_logic_vector(0 downto 0);
iocsrrdydly : in std_logic_vector(0 downto 0);
softaltpe3rstn : in std_logic_vector(0 downto 0);
softaltpe3srstn : in std_logic_vector(0 downto 0);
softaltpe3crstn : in std_logic_vector(0 downto 0);
pldclrpmapcshipn : in std_logic_vector(0 downto 0);
pldclrpcshipn : in std_logic_vector(0 downto 0);
pldclrhipn : in std_logic_vector(0 downto 0);
s0ch0emsiptieoff : out std_logic_vector(100 downto 0);
s0ch1emsiptieoff : out std_logic_vector(100 downto 0);
s0ch2emsiptieoff : out std_logic_vector(100 downto 0);
s1ch0emsiptieoff : out std_logic_vector(100 downto 0);
s1ch1emsiptieoff : out std_logic_vector(188 downto 0);
s1ch2emsiptieoff : out std_logic_vector(100 downto 0);
s2ch0emsiptieoff : out std_logic_vector(100 downto 0);
s2ch1emsiptieoff : out std_logic_vector(100 downto 0);
s2ch2emsiptieoff : out std_logic_vector(100 downto 0);
s3ch0emsiptieoff : out std_logic_vector(188 downto 0);
s3ch1emsiptieoff : out std_logic_vector(188 downto 0);
s3ch2emsiptieoff : out std_logic_vector(188 downto 0);
emsiptieofftop : out std_logic_vector(299 downto 0);
emsiptieoffbot : out std_logic_vector(299 downto 0);
txpcsrstn0 : out std_logic_vector(0 downto 0);
rxpcsrstn0 : out std_logic_vector(0 downto 0);
g3txpcsrstn0 : out std_logic_vector(0 downto 0);
g3rxpcsrstn0 : out std_logic_vector(0 downto 0);
txpmasyncp0 : out std_logic_vector(0 downto 0);
rxpmarstb0 : out std_logic_vector(0 downto 0);
txlcpllrstb0 : out std_logic_vector(0 downto 0);
offcalen0 : out std_logic_vector(0 downto 0);
frefclk0 : in std_logic_vector(0 downto 0);
offcaldone0 : in std_logic_vector(0 downto 0);
txlcplllock0 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock0 : in std_logic_vector(0 downto 0);
rxpllphaselock0 : in std_logic_vector(0 downto 0);
masktxplllock0 : in std_logic_vector(0 downto 0);
txpcsrstn1 : out std_logic_vector(0 downto 0);
rxpcsrstn1 : out std_logic_vector(0 downto 0);
g3txpcsrstn1 : out std_logic_vector(0 downto 0);
g3rxpcsrstn1 : out std_logic_vector(0 downto 0);
txpmasyncp1 : out std_logic_vector(0 downto 0);
rxpmarstb1 : out std_logic_vector(0 downto 0);
txlcpllrstb1 : out std_logic_vector(0 downto 0);
offcalen1 : out std_logic_vector(0 downto 0);
frefclk1 : in std_logic_vector(0 downto 0);
offcaldone1 : in std_logic_vector(0 downto 0);
txlcplllock1 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock1 : in std_logic_vector(0 downto 0);
rxpllphaselock1 : in std_logic_vector(0 downto 0);
masktxplllock1 : in std_logic_vector(0 downto 0);
txpcsrstn2 : out std_logic_vector(0 downto 0);
rxpcsrstn2 : out std_logic_vector(0 downto 0);
g3txpcsrstn2 : out std_logic_vector(0 downto 0);
g3rxpcsrstn2 : out std_logic_vector(0 downto 0);
txpmasyncp2 : out std_logic_vector(0 downto 0);
rxpmarstb2 : out std_logic_vector(0 downto 0);
txlcpllrstb2 : out std_logic_vector(0 downto 0);
offcalen2 : out std_logic_vector(0 downto 0);
frefclk2 : in std_logic_vector(0 downto 0);
offcaldone2 : in std_logic_vector(0 downto 0);
txlcplllock2 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock2 : in std_logic_vector(0 downto 0);
rxpllphaselock2 : in std_logic_vector(0 downto 0);
masktxplllock2 : in std_logic_vector(0 downto 0);
txpcsrstn3 : out std_logic_vector(0 downto 0);
rxpcsrstn3 : out std_logic_vector(0 downto 0);
g3txpcsrstn3 : out std_logic_vector(0 downto 0);
g3rxpcsrstn3 : out std_logic_vector(0 downto 0);
txpmasyncp3 : out std_logic_vector(0 downto 0);
rxpmarstb3 : out std_logic_vector(0 downto 0);
txlcpllrstb3 : out std_logic_vector(0 downto 0);
offcalen3 : out std_logic_vector(0 downto 0);
frefclk3 : in std_logic_vector(0 downto 0);
offcaldone3 : in std_logic_vector(0 downto 0);
txlcplllock3 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock3 : in std_logic_vector(0 downto 0);
rxpllphaselock3 : in std_logic_vector(0 downto 0);
masktxplllock3 : in std_logic_vector(0 downto 0);
txpcsrstn4 : out std_logic_vector(0 downto 0);
rxpcsrstn4 : out std_logic_vector(0 downto 0);
g3txpcsrstn4 : out std_logic_vector(0 downto 0);
g3rxpcsrstn4 : out std_logic_vector(0 downto 0);
txpmasyncp4 : out std_logic_vector(0 downto 0);
rxpmarstb4 : out std_logic_vector(0 downto 0);
txlcpllrstb4 : out std_logic_vector(0 downto 0);
offcalen4 : out std_logic_vector(0 downto 0);
frefclk4 : in std_logic_vector(0 downto 0);
offcaldone4 : in std_logic_vector(0 downto 0);
txlcplllock4 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock4 : in std_logic_vector(0 downto 0);
rxpllphaselock4 : in std_logic_vector(0 downto 0);
masktxplllock4 : in std_logic_vector(0 downto 0);
txpcsrstn5 : out std_logic_vector(0 downto 0);
rxpcsrstn5 : out std_logic_vector(0 downto 0);
g3txpcsrstn5 : out std_logic_vector(0 downto 0);
g3rxpcsrstn5 : out std_logic_vector(0 downto 0);
txpmasyncp5 : out std_logic_vector(0 downto 0);
rxpmarstb5 : out std_logic_vector(0 downto 0);
txlcpllrstb5 : out std_logic_vector(0 downto 0);
offcalen5 : out std_logic_vector(0 downto 0);
frefclk5 : in std_logic_vector(0 downto 0);
offcaldone5 : in std_logic_vector(0 downto 0);
txlcplllock5 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock5 : in std_logic_vector(0 downto 0);
rxpllphaselock5 : in std_logic_vector(0 downto 0);
masktxplllock5 : in std_logic_vector(0 downto 0);
txpcsrstn6 : out std_logic_vector(0 downto 0);
rxpcsrstn6 : out std_logic_vector(0 downto 0);
g3txpcsrstn6 : out std_logic_vector(0 downto 0);
g3rxpcsrstn6 : out std_logic_vector(0 downto 0);
txpmasyncp6 : out std_logic_vector(0 downto 0);
rxpmarstb6 : out std_logic_vector(0 downto 0);
txlcpllrstb6 : out std_logic_vector(0 downto 0);
offcalen6 : out std_logic_vector(0 downto 0);
frefclk6 : in std_logic_vector(0 downto 0);
offcaldone6 : in std_logic_vector(0 downto 0);
txlcplllock6 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock6 : in std_logic_vector(0 downto 0);
rxpllphaselock6 : in std_logic_vector(0 downto 0);
masktxplllock6 : in std_logic_vector(0 downto 0);
txpcsrstn7 : out std_logic_vector(0 downto 0);
rxpcsrstn7 : out std_logic_vector(0 downto 0);
g3txpcsrstn7 : out std_logic_vector(0 downto 0);
g3rxpcsrstn7 : out std_logic_vector(0 downto 0);
txpmasyncp7 : out std_logic_vector(0 downto 0);
rxpmarstb7 : out std_logic_vector(0 downto 0);
txlcpllrstb7 : out std_logic_vector(0 downto 0);
offcalen7 : out std_logic_vector(0 downto 0);
frefclk7 : in std_logic_vector(0 downto 0);
offcaldone7 : in std_logic_vector(0 downto 0);
txlcplllock7 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock7 : in std_logic_vector(0 downto 0);
rxpllphaselock7 : in std_logic_vector(0 downto 0);
masktxplllock7 : in std_logic_vector(0 downto 0);
txpcsrstn8 : out std_logic_vector(0 downto 0);
rxpcsrstn8 : out std_logic_vector(0 downto 0);
g3txpcsrstn8 : out std_logic_vector(0 downto 0);
g3rxpcsrstn8 : out std_logic_vector(0 downto 0);
txpmasyncp8 : out std_logic_vector(0 downto 0);
rxpmarstb8 : out std_logic_vector(0 downto 0);
txlcpllrstb8 : out std_logic_vector(0 downto 0);
offcalen8 : out std_logic_vector(0 downto 0);
frefclk8 : in std_logic_vector(0 downto 0);
offcaldone8 : in std_logic_vector(0 downto 0);
txlcplllock8 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock8 : in std_logic_vector(0 downto 0);
rxpllphaselock8 : in std_logic_vector(0 downto 0);
masktxplllock8 : in std_logic_vector(0 downto 0);
txpcsrstn9 : out std_logic_vector(0 downto 0);
rxpcsrstn9 : out std_logic_vector(0 downto 0);
g3txpcsrstn9 : out std_logic_vector(0 downto 0);
g3rxpcsrstn9 : out std_logic_vector(0 downto 0);
txpmasyncp9 : out std_logic_vector(0 downto 0);
rxpmarstb9 : out std_logic_vector(0 downto 0);
txlcpllrstb9 : out std_logic_vector(0 downto 0);
offcalen9 : out std_logic_vector(0 downto 0);
frefclk9 : in std_logic_vector(0 downto 0);
offcaldone9 : in std_logic_vector(0 downto 0);
txlcplllock9 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock9 : in std_logic_vector(0 downto 0);
rxpllphaselock9 : in std_logic_vector(0 downto 0);
masktxplllock9 : in std_logic_vector(0 downto 0);
txpcsrstn10 : out std_logic_vector(0 downto 0);
rxpcsrstn10 : out std_logic_vector(0 downto 0);
g3txpcsrstn10 : out std_logic_vector(0 downto 0);
g3rxpcsrstn10 : out std_logic_vector(0 downto 0);
txpmasyncp10 : out std_logic_vector(0 downto 0);
rxpmarstb10 : out std_logic_vector(0 downto 0);
txlcpllrstb10 : out std_logic_vector(0 downto 0);
offcalen10 : out std_logic_vector(0 downto 0);
frefclk10 : in std_logic_vector(0 downto 0);
offcaldone10 : in std_logic_vector(0 downto 0);
txlcplllock10 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock10 : in std_logic_vector(0 downto 0);
rxpllphaselock10 : in std_logic_vector(0 downto 0);
masktxplllock10 : in std_logic_vector(0 downto 0);
txpcsrstn11 : out std_logic_vector(0 downto 0);
rxpcsrstn11 : out std_logic_vector(0 downto 0);
g3txpcsrstn11 : out std_logic_vector(0 downto 0);
g3rxpcsrstn11 : out std_logic_vector(0 downto 0);
txpmasyncp11 : out std_logic_vector(0 downto 0);
rxpmarstb11 : out std_logic_vector(0 downto 0);
txlcpllrstb11 : out std_logic_vector(0 downto 0);
offcalen11 : out std_logic_vector(0 downto 0);
frefclk11 : in std_logic_vector(0 downto 0);
offcaldone11 : in std_logic_vector(0 downto 0);
txlcplllock11 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock11 : in std_logic_vector(0 downto 0);
rxpllphaselock11 : in std_logic_vector(0 downto 0);
masktxplllock11 : in std_logic_vector(0 downto 0);
reservedin : in std_logic_vector(31 downto 0);
reservedclkin : in std_logic_vector(0 downto 0);
reservedout : out std_logic_vector(31 downto 0);
reservedclkout : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_gen3_pcie_hip;
architecture behavior of stratixv_hssi_gen3_pcie_hip is
component stratixv_hssi_gen3_pcie_hip_encrypted
generic (
func_mode : string := "disable";
in_cvp_mode : string := "not_cvp_mode";
bonding_mode : string := "bond_disable";
prot_mode : string := "disabled_prot_mode";
pcie_spec_1p0_compliance : string := "spec_1p1";
vc_enable : string := "single_vc";
enable_slot_register : string := "false";
pcie_mode : string := "shared_mode";
bypass_cdc : string := "false";
enable_rx_reordering : string := "true";
enable_rx_buffer_checking : string := "false";
single_rx_detect_data : bit_vector := B"0000";
single_rx_detect : string := "single_rx_detect";
use_crc_forwarding : string := "false";
bypass_tl : string := "false";
gen123_lane_rate_mode : string := "gen1";
lane_mask : string := "x4";
disable_link_x2_support : string := "false";
national_inst_thru_enhance : string := "true";
hip_hard_reset : string := "enable";
dis_paritychk : string := "enable";
wrong_device_id : string := "disable";
data_pack_rx : string := "disable";
ast_width : string := "rx_tx_64";
rx_sop_ctrl : string := "boundary_64";
rx_ast_parity : string := "disable";
tx_ast_parity : string := "disable";
ltssm_1ms_timeout : string := "disable";
ltssm_freqlocked_check : string := "disable";
deskew_comma : string := "skp_eieos_deskw";
dl_tx_check_parity_edb : string := "disable";
tl_tx_check_parity_msg : string := "disable";
port_link_number_data : bit_vector := B"00000001";
port_link_number : string := "port_link_number";
device_number_data : bit_vector := B"00000";
device_number : string := "device_number";
bypass_clk_switch : string := "false";
core_clk_out_sel : string := "div_1";
core_clk_divider : string := "div_1";
core_clk_source : string := "pll_fixed_clk";
core_clk_sel : string := "pld_clk";
enable_ch0_pclk_out : string := "true";
enable_ch01_pclk_out : string := "pclk_ch0";
pipex1_debug_sel : string := "disable";
pclk_out_sel : string := "pclk";
vendor_id_data : bit_vector := B"1000101110010";
vendor_id : string := "vendor_id";
device_id_data : bit_vector := B"0000000000000001";
device_id : string := "device_id";
revision_id_data : bit_vector := B"00000001";
revision_id : string := "revision_id";
class_code_data : bit_vector := B"111111110000000000000000";
class_code : string := "class_code";
subsystem_vendor_id_data : bit_vector := B"0001000101110010";
subsystem_vendor_id : string := "subsystem_vendor_id";
subsystem_device_id_data : bit_vector := B"0000000000000001";
subsystem_device_id : string := "subsystem_device_id";
no_soft_reset : string := "false";
maximum_current_data : bit_vector := B"000";
maximum_current : string := "maximum_current";
d1_support : string := "false";
d2_support : string := "false";
d0_pme : string := "false";
d1_pme : string := "false";
d2_pme : string := "false";
d3_hot_pme : string := "false";
d3_cold_pme : string := "false";
use_aer : string := "false";
low_priority_vc : string := "single_vc";
vc_arbitration : string := "single_vc";
disable_snoop_packet : string := "false";
max_payload_size : string := "payload_512";
surprise_down_error_support : string := "false";
dll_active_report_support : string := "false";
extend_tag_field : string := "false";
endpoint_l0_latency_data : bit_vector := B"000";
endpoint_l0_latency : string := "endpoint_l0_latency";
endpoint_l1_latency_data : bit_vector := B"000";
endpoint_l1_latency : string := "endpoint_l1_latency";
indicator_data : bit_vector := B"111";
indicator : string := "indicator";
role_based_error_reporting : string := "false";
slot_power_scale_data : bit_vector := B"00";
slot_power_scale : string := "slot_power_scale";
max_link_width : string := "x4";
enable_l1_aspm : string := "false";
enable_l0s_aspm : string := "false";
l1_exit_latency_sameclock_data : bit_vector := B"000";
l1_exit_latency_sameclock : string := "l1_exit_latency_sameclock";
l1_exit_latency_diffclock_data : bit_vector := B"000";
l1_exit_latency_diffclock : string := "l1_exit_latency_diffclock";
hot_plug_support_data : bit_vector := B"0000000";
hot_plug_support : string := "hot_plug_support";
slot_power_limit_data : bit_vector := B"00000000";
slot_power_limit : string := "slot_power_limit";
slot_number_data : bit_vector := B"0000000000000";
slot_number : string := "slot_number";
diffclock_nfts_count_data : bit_vector := B"00000000";
diffclock_nfts_count : string := "diffclock_nfts_count";
sameclock_nfts_count_data : bit_vector := B"00000000";
sameclock_nfts_count : string := "sameclock_nfts_count";
completion_timeout : string := "abcd";
enable_completion_timeout_disable : string := "true";
extended_tag_reset : string := "false";
ecrc_check_capable : string := "true";
ecrc_gen_capable : string := "true";
no_command_completed : string := "true";
msi_multi_message_capable : string := "count_4";
msi_64bit_addressing_capable : string := "true";
msi_masking_capable : string := "false";
msi_support : string := "true";
interrupt_pin : string := "inta";
ena_ido_req : string := "false";
ena_ido_cpl : string := "false";
enable_function_msix_support : string := "true";
msix_table_size_data : bit_vector := B"00000000000";
msix_table_size : string := "msix_table_size";
msix_table_bir_data : bit_vector := B"000";
msix_table_bir : string := "msix_table_bir";
msix_table_offset_data : bit_vector := B"00000000000000000000000000000";
msix_table_offset : string := "msix_table_offset";
msix_pba_bir_data : bit_vector := B"000";
msix_pba_bir : string := "msix_pba_bir";
msix_pba_offset_data : bit_vector := B"00000000000000000000000000000";
msix_pba_offset : string := "msix_pba_offset";
bridge_port_vga_enable : string := "false";
bridge_port_ssid_support : string := "false";
ssvid_data : bit_vector := B"0000000000000000";
ssvid : string := "ssvid";
ssid_data : bit_vector := B"0000000000000000";
ssid : string := "ssid";
eie_before_nfts_count_data : bit_vector := B"0100";
eie_before_nfts_count : string := "eie_before_nfts_count";
gen2_diffclock_nfts_count_data : bit_vector := B"11111111";
gen2_diffclock_nfts_count : string := "gen2_diffclock_nfts_count";
gen2_sameclock_nfts_count_data : bit_vector := B"11111111";
gen2_sameclock_nfts_count : string := "gen2_sameclock_nfts_count";
deemphasis_enable : string := "false";
pcie_spec_version : string := "v2";
l0_exit_latency_sameclock_data : bit_vector := B"110";
l0_exit_latency_sameclock : string := "l0_exit_latency_sameclock";
l0_exit_latency_diffclock_data : bit_vector := B"110";
l0_exit_latency_diffclock : string := "l0_exit_latency_diffclock";
rx_ei_l0s : string := "disable";
l2_async_logic : string := "enable";
aspm_config_management : string := "true";
atomic_op_routing : string := "false";
atomic_op_completer_32bit : string := "false";
atomic_op_completer_64bit : string := "false";
cas_completer_128bit : string := "false";
ltr_mechanism : string := "false";
tph_completer : string := "false";
extended_format_field : string := "true";
atomic_malformed : string := "false";
flr_capability : string := "true";
enable_adapter_half_rate_mode : string := "false";
vc0_clk_enable : string := "true";
vc1_clk_enable : string := "false";
register_pipe_signals : string := "false";
bar0_io_space : string := "false";
bar0_64bit_mem_space : string := "true";
bar0_prefetchable : string := "true";
bar0_size_mask_data : bit_vector := B"1111111111111111111111111111";
bar0_size_mask : string := "bar0_size_mask";
bar1_io_space : string := "false";
bar1_64bit_mem_space : string := "false";
bar1_prefetchable : string := "false";
bar1_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar1_size_mask : string := "bar1_size_mask";
bar2_io_space : string := "false";
bar2_64bit_mem_space : string := "false";
bar2_prefetchable : string := "false";
bar2_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar2_size_mask : string := "bar2_size_mask";
bar3_io_space : string := "false";
bar3_64bit_mem_space : string := "false";
bar3_prefetchable : string := "false";
bar3_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar3_size_mask : string := "bar3_size_mask";
bar4_io_space : string := "false";
bar4_64bit_mem_space : string := "false";
bar4_prefetchable : string := "false";
bar4_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar4_size_mask : string := "bar4_size_mask";
bar5_io_space : string := "false";
bar5_64bit_mem_space : string := "false";
bar5_prefetchable : string := "false";
bar5_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar5_size_mask : string := "bar5_size_mask";
expansion_base_address_register_data : bit_vector := B"00000000000000000000000000000000";
expansion_base_address_register : string := "expansion_base_address_register";
io_window_addr_width : string := "window_32_bit";
prefetchable_mem_window_addr_width : string := "prefetch_32";
skp_os_gen3_count_data : bit_vector := B"00000000000";
skp_os_gen3_count : string := "skp_os_gen3_count";
rx_cdc_almost_empty_data : bit_vector := B"0000";
rx_cdc_almost_empty : string := "rx_cdc_almost_empty";
tx_cdc_almost_empty_data : bit_vector := B"0000";
tx_cdc_almost_empty : string := "tx_cdc_almost_empty";
rx_cdc_almost_full_data : bit_vector := B"0000";
rx_cdc_almost_full : string := "rx_cdc_almost_full";
tx_cdc_almost_full_data : bit_vector := B"0000";
tx_cdc_almost_full : string := "tx_cdc_almost_full";
rx_l0s_count_idl_data : bit_vector := B"00000000";
rx_l0s_count_idl : string := "rx_l0s_count_idl";
cdc_dummy_insert_limit_data : bit_vector := B"0000";
cdc_dummy_insert_limit : string := "cdc_dummy_insert_limit";
ei_delay_powerdown_count_data : bit_vector := B"00001010";
ei_delay_powerdown_count : string := "ei_delay_powerdown_count";
millisecond_cycle_count_data : bit_vector := B"00000000000000000000";
millisecond_cycle_count : string := "millisecond_cycle_count";
skp_os_schedule_count_data : bit_vector := B"00000000000";
skp_os_schedule_count : string := "skp_os_schedule_count";
fc_init_timer_data : bit_vector := B"10000000000";
fc_init_timer : string := "fc_init_timer";
l01_entry_latency_data : bit_vector := B"11111";
l01_entry_latency : string := "l01_entry_latency";
flow_control_update_count_data : bit_vector := B"11110";
flow_control_update_count : string := "flow_control_update_count";
flow_control_timeout_count_data : bit_vector := B"11001000";
flow_control_timeout_count : string := "flow_control_timeout_count";
vc0_rx_flow_ctrl_posted_header_data : bit_vector := B"00110010";
vc0_rx_flow_ctrl_posted_header : string := "vc0_rx_flow_ctrl_posted_header";
vc0_rx_flow_ctrl_posted_data_data : bit_vector := B"000101101000";
vc0_rx_flow_ctrl_posted_data : string := "vc0_rx_flow_ctrl_posted_data";
vc0_rx_flow_ctrl_nonposted_header_data : bit_vector := B"00110110";
vc0_rx_flow_ctrl_nonposted_header : string := "vc0_rx_flow_ctrl_nonposted_header";
vc0_rx_flow_ctrl_nonposted_data_data : bit_vector := B"00000000";
vc0_rx_flow_ctrl_nonposted_data : string := "vc0_rx_flow_ctrl_nonposted_data";
vc0_rx_flow_ctrl_compl_header_data : bit_vector := B"01110000";
vc0_rx_flow_ctrl_compl_header : string := "vc0_rx_flow_ctrl_compl_header";
vc0_rx_flow_ctrl_compl_data_data : bit_vector := B"000111000000";
vc0_rx_flow_ctrl_compl_data : string := "vc0_rx_flow_ctrl_compl_data";
rx_ptr0_posted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_min : string := "rx_ptr0_posted_dpram_min";
rx_ptr0_posted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_max : string := "rx_ptr0_posted_dpram_max";
rx_ptr0_nonposted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_min : string := "rx_ptr0_nonposted_dpram_min";
rx_ptr0_nonposted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_max : string := "rx_ptr0_nonposted_dpram_max";
retry_buffer_last_active_address_data : bit_vector := B"1111111111";
retry_buffer_last_active_address : string := "retry_buffer_last_active_address";
retry_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
retry_buffer_memory_settings : string := "retry_buffer_memory_settings";
vc0_rx_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
vc0_rx_buffer_memory_settings : string := "vc0_rx_buffer_memory_settings";
bist_memory_settings_data : bit_vector := B"000000000000000000000000000000000000000000000000000000000000000000000000000";
bist_memory_settings : string := "bist_memory_settings";
credit_buffer_allocation_aux : string := "balanced";
iei_enable_settings : string := "gen2_infei_infsd_gen1_infei_sd";
vsec_id_data : bit_vector := B"0001000101110010";
vsec_id : string := "vsec_id";
cvp_rate_sel : string := "full_rate";
hard_reset_bypass : string := "false";
cvp_data_compressed : string := "false";
cvp_data_encrypted : string := "false";
cvp_mode_reset : string := "false";
cvp_clk_reset : string := "false";
vsec_cap_data : bit_vector := B"0000";
vsec_cap : string := "vsec_cap";
jtag_id_data : bit_vector := B"00000000000000000000000000000000";
jtag_id : string := "jtag_id";
user_id_data : bit_vector := B"0000000000000000";
user_id : string := "user_id";
cseb_extend_pci : string := "false";
cseb_extend_pcie : string := "false";
cseb_cpl_status_during_cvp : string := "config_retry_status";
cseb_route_to_avl_rx_st : string := "cseb";
cseb_config_bypass : string := "disable";
cseb_cpl_tag_checking : string := "enable";
cseb_bar_match_checking : string := "enable";
cseb_min_error_checking : string := "false";
cseb_temp_busy_crs : string := "completer_abort";
cseb_disable_auto_crs : string := "false";
gen3_diffclock_nfts_count_data : bit_vector := B"10000000";
gen3_diffclock_nfts_count : string := "g3_diffclock_nfts_count";
gen3_sameclock_nfts_count_data : bit_vector := B"10000000";
gen3_sameclock_nfts_count : string := "g3_sameclock_nfts_count";
gen3_coeff_errchk : string := "enable";
gen3_paritychk : string := "enable";
gen3_coeff_delay_count_data : bit_vector := B"1111101";
gen3_coeff_delay_count : string := "g3_coeff_dly_count";
gen3_coeff_1_data : bit_vector := B"000000000000000000";
gen3_coeff_1 : string := "g3_coeff_1";
gen3_coeff_1_sel : string := "coeff_1";
gen3_coeff_1_preset_hint_data : bit_vector := B"000";
gen3_coeff_1_preset_hint : string := "g3_coeff_1_prst_hint";
gen3_coeff_1_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_more : string := "g3_coeff_1_nxtber_more";
gen3_coeff_1_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_less : string := "g3_coeff_1_nxtber_less";
gen3_coeff_1_reqber_data : bit_vector := B"00000";
gen3_coeff_1_reqber : string := "g3_coeff_1_reqber";
gen3_coeff_1_ber_meas_data : bit_vector := B"000000";
gen3_coeff_1_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_2_data : bit_vector := B"000000000000000000";
gen3_coeff_2 : string := "g3_coeff_2";
gen3_coeff_2_sel : string := "coeff_2";
gen3_coeff_2_preset_hint_data : bit_vector := B"000";
gen3_coeff_2_preset_hint : string := "g3_coeff_2_prst_hint";
gen3_coeff_2_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_more : string := "g3_coeff_2_nxtber_more";
gen3_coeff_2_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_less : string := "g3_coeff_2_nxtber_less";
gen3_coeff_2_reqber_data : bit_vector := B"00000";
gen3_coeff_2_reqber : string := "g3_coeff_2_reqber";
gen3_coeff_2_ber_meas_data : bit_vector := B"000000";
gen3_coeff_2_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_3_data : bit_vector := B"000000000000000000";
gen3_coeff_3 : string := "g3_coeff_3";
gen3_coeff_3_sel : string := "coeff_3";
gen3_coeff_3_preset_hint_data : bit_vector := B"000";
gen3_coeff_3_preset_hint : string := "g3_coeff_3_prst_hint";
gen3_coeff_3_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_more : string := "g3_coeff_3_nxtber_more";
gen3_coeff_3_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_less : string := "g3_coeff_3_nxtber_less";
gen3_coeff_3_reqber_data : bit_vector := B"00000";
gen3_coeff_3_reqber : string := "g3_coeff_3_reqber";
gen3_coeff_3_ber_meas_data : bit_vector := B"000000";
gen3_coeff_3_ber_meas : string := "g3_coeff_3_ber_meas";
gen3_coeff_4_data : bit_vector := B"000000000000000000";
gen3_coeff_4 : string := "g3_coeff_4";
gen3_coeff_4_sel : string := "coeff_4";
gen3_coeff_4_preset_hint_data : bit_vector := B"000";
gen3_coeff_4_preset_hint : string := "g3_coeff_4_prst_hint";
gen3_coeff_4_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_more : string := "g3_coeff_4_nxtber_more";
gen3_coeff_4_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_less : string := "g3_coeff_4_nxtber_less";
gen3_coeff_4_reqber_data : bit_vector := B"00000";
gen3_coeff_4_reqber : string := "g3_coeff_4_reqber";
gen3_coeff_4_ber_meas_data : bit_vector := B"000000";
gen3_coeff_4_ber_meas : string := "g3_coeff_4_ber_meas";
gen3_coeff_5_data : bit_vector := B"000000000000000000";
gen3_coeff_5 : string := "g3_coeff_5";
gen3_coeff_5_sel : string := "coeff_5";
gen3_coeff_5_preset_hint_data : bit_vector := B"000";
gen3_coeff_5_preset_hint : string := "g3_coeff_5_prst_hint";
gen3_coeff_5_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_more : string := "g3_coeff_5_nxtber_more";
gen3_coeff_5_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_less : string := "g3_coeff_5_nxtber_less";
gen3_coeff_5_reqber_data : bit_vector := B"00000";
gen3_coeff_5_reqber : string := "g3_coeff_5_reqber";
gen3_coeff_5_ber_meas_data : bit_vector := B"000000";
gen3_coeff_5_ber_meas : string := "g3_coeff_5_ber_meas";
gen3_coeff_6_data : bit_vector := B"000000000000000000";
gen3_coeff_6 : string := "g3_coeff_6";
gen3_coeff_6_sel : string := "coeff_6";
gen3_coeff_6_preset_hint_data : bit_vector := B"000";
gen3_coeff_6_preset_hint : string := "g3_coeff_6_prst_hint";
gen3_coeff_6_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_more : string := "g3_coeff_6_nxtber_more";
gen3_coeff_6_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_less : string := "g3_coeff_6_nxtber_less";
gen3_coeff_6_reqber_data : bit_vector := B"00000";
gen3_coeff_6_reqber : string := "g3_coeff_6_reqber";
gen3_coeff_6_ber_meas_data : bit_vector := B"000000";
gen3_coeff_6_ber_meas : string := "g3_coeff_6_ber_meas";
gen3_coeff_7_data : bit_vector := B"000000000000000000";
gen3_coeff_7 : string := "g3_coeff_7";
gen3_coeff_7_sel : string := "coeff_7";
gen3_coeff_7_preset_hint_data : bit_vector := B"000";
gen3_coeff_7_preset_hint : string := "g3_coeff_7_prst_hint";
gen3_coeff_7_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_more : string := "g3_coeff_7_nxtber_more";
gen3_coeff_7_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_less : string := "g3_coeff_7_nxtber_less";
gen3_coeff_7_reqber_data : bit_vector := B"00000";
gen3_coeff_7_reqber : string := "g3_coeff_7_reqber";
gen3_coeff_7_ber_meas_data : bit_vector := B"000000";
gen3_coeff_7_ber_meas : string := "g3_coeff_7_ber_meas";
gen3_coeff_8_data : bit_vector := B"000000000000000000";
gen3_coeff_8 : string := "g3_coeff_8";
gen3_coeff_8_sel : string := "coeff_8";
gen3_coeff_8_preset_hint_data : bit_vector := B"000";
gen3_coeff_8_preset_hint : string := "g3_coeff_8_prst_hint";
gen3_coeff_8_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_more : string := "g3_coeff_8_nxtber_more";
gen3_coeff_8_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_less : string := "g3_coeff_8_nxtber_less";
gen3_coeff_8_reqber_data : bit_vector := B"00000";
gen3_coeff_8_reqber : string := "g3_coeff_8_reqber";
gen3_coeff_8_ber_meas_data : bit_vector := B"000000";
gen3_coeff_8_ber_meas : string := "g3_coeff_8_ber_meas";
gen3_coeff_9_data : bit_vector := B"000000000000000000";
gen3_coeff_9 : string := "g3_coeff_9";
gen3_coeff_9_sel : string := "coeff_9";
gen3_coeff_9_preset_hint_data : bit_vector := B"000";
gen3_coeff_9_preset_hint : string := "g3_coeff_9_prst_hint";
gen3_coeff_9_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_more : string := "g3_coeff_9_nxtber_more";
gen3_coeff_9_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_less : string := "g3_coeff_9_nxtber_less";
gen3_coeff_9_reqber_data : bit_vector := B"00000";
gen3_coeff_9_reqber : string := "g3_coeff_9_reqber";
gen3_coeff_9_ber_meas_data : bit_vector := B"000000";
gen3_coeff_9_ber_meas : string := "g3_coeff_9_ber_meas";
gen3_coeff_10_data : bit_vector := B"000000000000000000";
gen3_coeff_10 : string := "g3_coeff_10";
gen3_coeff_10_sel : string := "coeff_10";
gen3_coeff_10_preset_hint_data : bit_vector := B"000";
gen3_coeff_10_preset_hint : string := "g3_coeff_10_prst_hint";
gen3_coeff_10_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_more : string := "g3_coeff_10_nxtber_more";
gen3_coeff_10_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_less : string := "g3_coeff_10_nxtber_less";
gen3_coeff_10_reqber_data : bit_vector := B"00000";
gen3_coeff_10_reqber : string := "g3_coeff_10_reqber";
gen3_coeff_10_ber_meas_data : bit_vector := B"000000";
gen3_coeff_10_ber_meas : string := "g3_coeff_10_ber_meas";
gen3_coeff_11_data : bit_vector := B"000000000000000000";
gen3_coeff_11 : string := "g3_coeff_11";
gen3_coeff_11_sel : string := "coeff_11";
gen3_coeff_11_preset_hint_data : bit_vector := B"000";
gen3_coeff_11_preset_hint : string := "g3_coeff_11_prst_hint";
gen3_coeff_11_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_more : string := "g3_coeff_11_nxtber_more";
gen3_coeff_11_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_less : string := "g3_coeff_11_nxtber_less";
gen3_coeff_11_reqber_data : bit_vector := B"00000";
gen3_coeff_11_reqber : string := "g3_coeff_11_reqber";
gen3_coeff_11_ber_meas_data : bit_vector := B"000000";
gen3_coeff_11_ber_meas : string := "g3_coeff_11_ber_meas";
gen3_coeff_12_data : bit_vector := B"000000000000000000";
gen3_coeff_12 : string := "g3_coeff_12";
gen3_coeff_12_sel : string := "coeff_12";
gen3_coeff_12_preset_hint_data : bit_vector := B"000";
gen3_coeff_12_preset_hint : string := "g3_coeff_12_prst_hint";
gen3_coeff_12_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_more : string := "g3_coeff_12_nxtber_more";
gen3_coeff_12_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_less : string := "g3_coeff_12_nxtber_less";
gen3_coeff_12_reqber_data : bit_vector := B"00000";
gen3_coeff_12_reqber : string := "g3_coeff_12_reqber";
gen3_coeff_12_ber_meas_data : bit_vector := B"000000";
gen3_coeff_12_ber_meas : string := "g3_coeff_12_ber_meas";
gen3_coeff_13_data : bit_vector := B"000000000000000000";
gen3_coeff_13 : string := "g3_coeff_13";
gen3_coeff_13_sel : string := "coeff_13";
gen3_coeff_13_preset_hint_data : bit_vector := B"000";
gen3_coeff_13_preset_hint : string := "g3_coeff_13_prst_hint";
gen3_coeff_13_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_more : string := "g3_coeff_13_nxtber_more";
gen3_coeff_13_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_less : string := "g3_coeff_13_nxtber_less";
gen3_coeff_13_reqber_data : bit_vector := B"00000";
gen3_coeff_13_reqber : string := "g3_coeff_13_reqber";
gen3_coeff_13_ber_meas_data : bit_vector := B"000000";
gen3_coeff_13_ber_meas : string := "g3_coeff_13_ber_meas";
gen3_coeff_14_data : bit_vector := B"000000000000000000";
gen3_coeff_14 : string := "g3_coeff_14";
gen3_coeff_14_sel : string := "coeff_14";
gen3_coeff_14_preset_hint_data : bit_vector := B"000";
gen3_coeff_14_preset_hint : string := "g3_coeff_14_prst_hint";
gen3_coeff_14_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_more : string := "g3_coeff_14_nxtber_more";
gen3_coeff_14_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_less : string := "g3_coeff_14_nxtber_less";
gen3_coeff_14_reqber_data : bit_vector := B"00000";
gen3_coeff_14_reqber : string := "g3_coeff_14_reqber";
gen3_coeff_14_ber_meas_data : bit_vector := B"000000";
gen3_coeff_14_ber_meas : string := "g3_coeff_14_ber_meas";
gen3_coeff_15_data : bit_vector := B"000000000000000000";
gen3_coeff_15 : string := "g3_coeff_15";
gen3_coeff_15_sel : string := "coeff_15";
gen3_coeff_15_preset_hint_data : bit_vector := B"000";
gen3_coeff_15_preset_hint : string := "g3_coeff_15_prst_hint";
gen3_coeff_15_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_more : string := "g3_coeff_15_nxtber_more";
gen3_coeff_15_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_less : string := "g3_coeff_15_nxtber_less";
gen3_coeff_15_reqber_data : bit_vector := B"00000";
gen3_coeff_15_reqber : string := "g3_coeff_15_reqber";
gen3_coeff_15_ber_meas_data : bit_vector := B"000000";
gen3_coeff_15_ber_meas : string := "g3_coeff_15_ber_meas";
gen3_coeff_16_data : bit_vector := B"000000000000000000";
gen3_coeff_16 : string := "g3_coeff_16";
gen3_coeff_16_sel : string := "coeff_16";
gen3_coeff_16_preset_hint_data : bit_vector := B"000";
gen3_coeff_16_preset_hint : string := "g3_coeff_16_prst_hint";
gen3_coeff_16_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_more : string := "g3_coeff_16_nxtber_more";
gen3_coeff_16_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_less : string := "g3_coeff_16_nxtber_less";
gen3_coeff_16_reqber_data : bit_vector := B"00000";
gen3_coeff_16_reqber : string := "g3_coeff_16_reqber";
gen3_coeff_16_ber_meas_data : bit_vector := B"000000";
gen3_coeff_16_ber_meas : string := "g3_coeff_16_ber_meas";
gen3_preset_coeff_1_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_1 : string := "g3_prst_coeff_1";
gen3_preset_coeff_2_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_2 : string := "g3_prst_coeff_2";
gen3_preset_coeff_3_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_3 : string := "g3_prst_coeff_3";
gen3_preset_coeff_4_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_4 : string := "g3_prst_coeff_4";
gen3_preset_coeff_5_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_5 : string := "g3_prst_coeff_5";
gen3_preset_coeff_6_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_6 : string := "g3_prst_coeff_6";
gen3_preset_coeff_7_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_7 : string := "g3_prst_coeff_7";
gen3_preset_coeff_8_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_8 : string := "g3_prst_coeff_8";
gen3_preset_coeff_9_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_9 : string := "g3_prst_coeff_9";
gen3_preset_coeff_10_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_10 : string := "g3_prst_coeff_10";
gen3_rxfreqlock_counter_data : bit_vector := "00000000000000000000";
gen3_rxfreqlock_counter : string := "g3_rxfreqlock_count";
rstctrl_pld_clr : string := "false";-- "false", "true".
rstctrl_debug_en : string := "false";-- "false", "true".
rstctrl_force_inactive_rst : string := "false";-- "false", "true".
rstctrl_perst_enable : string := "level";-- "level", "neg_edge", "not_used".
hrdrstctrl_en : string := "hrdrstctrl_dis";--"hrdrstctrl_dis", "hrdrstctrl_en".
rstctrl_hip_ep : string := "hip_ep"; --"hip_ep", "hip_not_ep".
rstctrl_hard_block_enable : string := "hard_rst_ctl";--"hard_rst_ctl", "pld_rst_ctl".
rstctrl_rx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_tx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_rx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_crst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_srst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pma_syncp_inv : string := "false";--"false", "true".
rstctrl_1us_count_fref_clk : string := "rstctrl_1us_cnt";--
rstctrl_1us_count_fref_clk_value : bit_vector := B"00000000000000111111";--
rstctrl_1ms_count_fref_clk : string := "rstctrl_1ms_cnt";--
rstctrl_1ms_count_fref_clk_value : bit_vector := B"00001111010000100100";--
rstctrl_off_cal_done_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_rx_pma_rstb_cmu_select : string := "not_active";-- "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
rstctrl_rx_pll_freq_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
rstctrl_mask_tx_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_rx_pll_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_perstn_select : string := "perstn_pin";-- "perstn_pin", "perstn_pld".
rstctrl_tx_lc_pll_rstb_select : string := "not_active";-- "ch1_out", "ch7_out", "not_active".
rstctrl_fref_clk_select : string := "not_active";-- "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
rstctrl_off_cal_en_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
rstctrl_tx_pma_syncp_select : string := "not_active";-- "ch1_out", "ch4_out", "ch4_10_out", "not_active".
rstctrl_rx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_cmu_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_tx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_lc_pll_lock_select : string := "not_active";-- "ch1_sel", "ch7_sel", "not_active".
rstctrl_timer_a : string := "rstctrl_timer_a";
rstctrl_timer_a_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_a_value : bit_vector := B"00000001" ;
rstctrl_timer_b : string := "rstctrl_timer_b";
rstctrl_timer_b_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_b_value : bit_vector := B"00000001";
rstctrl_timer_c : string := "rstctrl_timer_c";
rstctrl_timer_c_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_c_value : bit_vector := B"00000001";
rstctrl_timer_d : string := "rstctrl_timer_d";
rstctrl_timer_d_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_d_value : bit_vector := B"00000001";
rstctrl_timer_e : string := "rstctrl_timer_e";
rstctrl_timer_e_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_e_value : bit_vector := B"00000001";
rstctrl_timer_f : string := "rstctrl_timer_f";
rstctrl_timer_f_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_f_value : bit_vector := B"00000001";
rstctrl_timer_g : string := "rstctrl_timer_g";
rstctrl_timer_g_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_g_value : bit_vector := B"00000001";
rstctrl_timer_h : string := "rstctrl_timer_h";
rstctrl_timer_h_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_h_value : bit_vector := B"00000001";
rstctrl_timer_i : string := "rstctrl_timer_i";
rstctrl_timer_i_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_i_value : bit_vector := B"00000001";
rstctrl_timer_j : string := "rstctrl_timer_j";
rstctrl_timer_j_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_j_value : bit_vector := B"00000001"
);
port (
dpriostatus : out std_logic_vector(15 downto 0);
lmidout : out std_logic_vector(31 downto 0);
lmiack : out std_logic_vector(0 downto 0);
lmirden : in std_logic_vector(0 downto 0);
lmiwren : in std_logic_vector(0 downto 0);
lmiaddr : in std_logic_vector(11 downto 0);
lmidin : in std_logic_vector(31 downto 0);
flrreset : in std_logic_vector(0 downto 0);
flrsts : out std_logic_vector(0 downto 0);
resetstatus : out std_logic_vector(0 downto 0);
l2exit : out std_logic_vector(0 downto 0);
hotrstexit : out std_logic_vector(0 downto 0);
hiphardreset : in std_logic_vector(0 downto 0);
dlupexit : out std_logic_vector(0 downto 0);
coreclkout : out std_logic_vector(0 downto 0);
pldclk : in std_logic_vector(0 downto 0);
pldsrst : in std_logic_vector(0 downto 0);
pldrst : in std_logic_vector(0 downto 0);
pclkch0 : in std_logic_vector(0 downto 0);
pclkch1 : in std_logic_vector(0 downto 0);
pclkcentral : in std_logic_vector(0 downto 0);
pllfixedclkch0 : in std_logic_vector(0 downto 0);
pllfixedclkch1 : in std_logic_vector(0 downto 0);
pllfixedclkcentral : in std_logic_vector(0 downto 0);
phyrst : in std_logic_vector(0 downto 0);
physrst : in std_logic_vector(0 downto 0);
coreclkin : in std_logic_vector(0 downto 0);
corerst : in std_logic_vector(0 downto 0);
corepor : in std_logic_vector(0 downto 0);
corecrst : in std_logic_vector(0 downto 0);
coresrst : in std_logic_vector(0 downto 0);
swdnout : out std_logic_vector(6 downto 0);
swupout : out std_logic_vector(2 downto 0);
swdnin : in std_logic_vector(2 downto 0);
swupin : in std_logic_vector(6 downto 0);
swctmod : in std_logic_vector(1 downto 0);
rxstdata : out std_logic_vector(255 downto 0);
rxstparity : out std_logic_vector(31 downto 0);
rxstbe : out std_logic_vector(31 downto 0);
rxsterr : out std_logic_vector(3 downto 0);
rxstsop : out std_logic_vector(3 downto 0);
rxsteop : out std_logic_vector(3 downto 0);
rxstempty : out std_logic_vector(1 downto 0);
rxstvalid : out std_logic_vector(3 downto 0);
rxstbardec1 : out std_logic_vector(7 downto 0);
rxstbardec2 : out std_logic_vector(7 downto 0);
rxstmask : in std_logic_vector(0 downto 0);
rxstready : in std_logic_vector(0 downto 0);
txstready : out std_logic_vector(0 downto 0);
txcredfchipcons : out std_logic_vector(5 downto 0);
txcredfcinfinite : out std_logic_vector(5 downto 0);
txcredhdrfcp : out std_logic_vector(7 downto 0);
txcreddatafcp : out std_logic_vector(11 downto 0);
txcredhdrfcnp : out std_logic_vector(7 downto 0);
txcreddatafcnp : out std_logic_vector(11 downto 0);
txcredhdrfccp : out std_logic_vector(7 downto 0);
txcreddatafccp : out std_logic_vector(11 downto 0);
txstdata : in std_logic_vector(255 downto 0);
txstparity : in std_logic_vector(31 downto 0);
txsterr : in std_logic_vector(3 downto 0);
txstsop : in std_logic_vector(3 downto 0);
txsteop : in std_logic_vector(3 downto 0);
txstempty : in std_logic_vector(1 downto 0);
txstvalid : in std_logic_vector(0 downto 0);
r2cuncecc : out std_logic_vector(0 downto 0);
rxcorrecc : out std_logic_vector(0 downto 0);
retryuncecc : out std_logic_vector(0 downto 0);
retrycorrecc : out std_logic_vector(0 downto 0);
rxparerr : out std_logic_vector(0 downto 0);
txparerr : out std_logic_vector(1 downto 0);
r2cparerr : out std_logic_vector(0 downto 0);
pmetosr : out std_logic_vector(0 downto 0);
pmetocr : in std_logic_vector(0 downto 0);
pmevent : in std_logic_vector(0 downto 0);
pmdata : in std_logic_vector(9 downto 0);
pmauxpwr : in std_logic_vector(0 downto 0);
tlcfgsts : out std_logic_vector(52 downto 0);
tlcfgctl : out std_logic_vector(31 downto 0);
tlcfgadd : out std_logic_vector(3 downto 0);
appintaack : out std_logic_vector(0 downto 0);
appintasts : in std_logic_vector(0 downto 0);
intstatus : out std_logic_vector(3 downto 0);
appmsiack : out std_logic_vector(0 downto 0);
appmsireq : in std_logic_vector(0 downto 0);
appmsitc : in std_logic_vector(2 downto 0);
appmsinum : in std_logic_vector(4 downto 0);
aermsinum : in std_logic_vector(4 downto 0);
pexmsinum : in std_logic_vector(4 downto 0);
hpgctrler : in std_logic_vector(4 downto 0);
cfglink2csrpld : in std_logic_vector(12 downto 0);
cfgprmbuspld : in std_logic_vector(7 downto 0);
csebisshadow : out std_logic_vector(0 downto 0);
csebwrdata : out std_logic_vector(31 downto 0);
csebwrdataparity : out std_logic_vector(3 downto 0);
csebbe : out std_logic_vector(3 downto 0);
csebaddr : out std_logic_vector(32 downto 0);
csebaddrparity : out std_logic_vector(4 downto 0);
csebwren : out std_logic_vector(0 downto 0);
csebrden : out std_logic_vector(0 downto 0);
csebwrrespreq : out std_logic_vector(0 downto 0);
csebrddata : in std_logic_vector(31 downto 0);
csebrddataparity : in std_logic_vector(3 downto 0);
csebwaitrequest : in std_logic_vector(0 downto 0);
csebwrrespvalid : in std_logic_vector(0 downto 0);
csebwrresponse : in std_logic_vector(4 downto 0);
csebrdresponse : in std_logic_vector(4 downto 0);
dlup : out std_logic_vector(0 downto 0);
testouthip : out std_logic_vector(255 downto 0);
testout1hip : out std_logic_vector(63 downto 0);
ev1us : out std_logic_vector(0 downto 0);
ev128ns : out std_logic_vector(0 downto 0);
wakeoen : out std_logic_vector(0 downto 0);
serrout : out std_logic_vector(0 downto 0);
ltssmstate : out std_logic_vector(4 downto 0);
laneact : out std_logic_vector(3 downto 0);
currentspeed : out std_logic_vector(1 downto 0);
slotclkcfg : in std_logic_vector(0 downto 0);
mode : in std_logic_vector(1 downto 0);
testinhip : in std_logic_vector(31 downto 0);
testin1hip : in std_logic_vector(31 downto 0);
cplpending : in std_logic_vector(0 downto 0);
cplerr : in std_logic_vector(6 downto 0);
appinterr : in std_logic_vector(1 downto 0);
egressblkerr : in std_logic_vector(0 downto 0);
pmexitd0ack : in std_logic_vector(0 downto 0);
pmexitd0req : out std_logic_vector(0 downto 0);
currentcoeff0 : out std_logic_vector(17 downto 0);
currentcoeff1 : out std_logic_vector(17 downto 0);
currentcoeff2 : out std_logic_vector(17 downto 0);
currentcoeff3 : out std_logic_vector(17 downto 0);
currentcoeff4 : out std_logic_vector(17 downto 0);
currentcoeff5 : out std_logic_vector(17 downto 0);
currentcoeff6 : out std_logic_vector(17 downto 0);
currentcoeff7 : out std_logic_vector(17 downto 0);
currentrxpreset0 : out std_logic_vector(2 downto 0);
currentrxpreset1 : out std_logic_vector(2 downto 0);
currentrxpreset2 : out std_logic_vector(2 downto 0);
currentrxpreset3 : out std_logic_vector(2 downto 0);
currentrxpreset4 : out std_logic_vector(2 downto 0);
currentrxpreset5 : out std_logic_vector(2 downto 0);
currentrxpreset6 : out std_logic_vector(2 downto 0);
currentrxpreset7 : out std_logic_vector(2 downto 0);
rate0 : out std_logic_vector(1 downto 0);
rate1 : out std_logic_vector(1 downto 0);
rate2 : out std_logic_vector(1 downto 0);
rate3 : out std_logic_vector(1 downto 0);
rate4 : out std_logic_vector(1 downto 0);
rate5 : out std_logic_vector(1 downto 0);
rate6 : out std_logic_vector(1 downto 0);
rate7 : out std_logic_vector(1 downto 0);
ratectrl : out std_logic_vector(1 downto 0);
ratetiedtognd : out std_logic_vector(0 downto 0);
eidleinfersel0 : out std_logic_vector(2 downto 0);
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
eidleinfersel4 : out std_logic_vector(2 downto 0);
eidleinfersel5 : out std_logic_vector(2 downto 0);
eidleinfersel6 : out std_logic_vector(2 downto 0);
eidleinfersel7 : out std_logic_vector(2 downto 0);
txdata0 : out std_logic_vector(31 downto 0);
txdatak0 : out std_logic_vector(3 downto 0);
txdetectrx0 : out std_logic_vector(0 downto 0);
txelecidle0 : out std_logic_vector(0 downto 0);
txcompl0 : out std_logic_vector(0 downto 0);
rxpolarity0 : out std_logic_vector(0 downto 0);
powerdown0 : out std_logic_vector(1 downto 0);
txdataskip0 : out std_logic_vector(0 downto 0);
txblkst0 : out std_logic_vector(0 downto 0);
txsynchd0 : out std_logic_vector(1 downto 0);
txdeemph0 : out std_logic_vector(0 downto 0);
txmargin0 : out std_logic_vector(2 downto 0);
rxdata0 : in std_logic_vector(31 downto 0);
rxdatak0 : in std_logic_vector(3 downto 0);
rxvalid0 : in std_logic_vector(0 downto 0);
phystatus0 : in std_logic_vector(0 downto 0);
rxelecidle0 : in std_logic_vector(0 downto 0);
rxstatus0 : in std_logic_vector(2 downto 0);
rxdataskip0 : in std_logic_vector(0 downto 0);
rxblkst0 : in std_logic_vector(0 downto 0);
rxsynchd0 : in std_logic_vector(1 downto 0);
rxfreqlocked0 : in std_logic_vector(0 downto 0);
txdata1 : out std_logic_vector(31 downto 0);
txdatak1 : out std_logic_vector(3 downto 0);
txdetectrx1 : out std_logic_vector(0 downto 0);
txelecidle1 : out std_logic_vector(0 downto 0);
txcompl1 : out std_logic_vector(0 downto 0);
rxpolarity1 : out std_logic_vector(0 downto 0);
powerdown1 : out std_logic_vector(1 downto 0);
txdataskip1 : out std_logic_vector(0 downto 0);
txblkst1 : out std_logic_vector(0 downto 0);
txsynchd1 : out std_logic_vector(1 downto 0);
txdeemph1 : out std_logic_vector(0 downto 0);
txmargin1 : out std_logic_vector(2 downto 0);
rxdata1 : in std_logic_vector(31 downto 0);
rxdatak1 : in std_logic_vector(3 downto 0);
rxvalid1 : in std_logic_vector(0 downto 0);
phystatus1 : in std_logic_vector(0 downto 0);
rxelecidle1 : in std_logic_vector(0 downto 0);
rxstatus1 : in std_logic_vector(2 downto 0);
rxdataskip1 : in std_logic_vector(0 downto 0);
rxblkst1 : in std_logic_vector(0 downto 0);
rxsynchd1 : in std_logic_vector(1 downto 0);
rxfreqlocked1 : in std_logic_vector(0 downto 0);
txdata2 : out std_logic_vector(31 downto 0);
txdatak2 : out std_logic_vector(3 downto 0);
txdetectrx2 : out std_logic_vector(0 downto 0);
txelecidle2 : out std_logic_vector(0 downto 0);
txcompl2 : out std_logic_vector(0 downto 0);
rxpolarity2 : out std_logic_vector(0 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
txdataskip2 : out std_logic_vector(0 downto 0);
txblkst2 : out std_logic_vector(0 downto 0);
txsynchd2 : out std_logic_vector(1 downto 0);
txdeemph2 : out std_logic_vector(0 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
rxdata2 : in std_logic_vector(31 downto 0);
rxdatak2 : in std_logic_vector(3 downto 0);
rxvalid2 : in std_logic_vector(0 downto 0);
phystatus2 : in std_logic_vector(0 downto 0);
rxelecidle2 : in std_logic_vector(0 downto 0);
rxstatus2 : in std_logic_vector(2 downto 0);
rxdataskip2 : in std_logic_vector(0 downto 0);
rxblkst2 : in std_logic_vector(0 downto 0);
rxsynchd2 : in std_logic_vector(1 downto 0);
rxfreqlocked2 : in std_logic_vector(0 downto 0);
txdata3 : out std_logic_vector(31 downto 0);
txdatak3 : out std_logic_vector(3 downto 0);
txdetectrx3 : out std_logic_vector(0 downto 0);
txelecidle3 : out std_logic_vector(0 downto 0);
txcompl3 : out std_logic_vector(0 downto 0);
rxpolarity3 : out std_logic_vector(0 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
txdataskip3 : out std_logic_vector(0 downto 0);
txblkst3 : out std_logic_vector(0 downto 0);
txsynchd3 : out std_logic_vector(1 downto 0);
txdeemph3 : out std_logic_vector(0 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
rxdata3 : in std_logic_vector(31 downto 0);
rxdatak3 : in std_logic_vector(3 downto 0);
rxvalid3 : in std_logic_vector(0 downto 0);
phystatus3 : in std_logic_vector(0 downto 0);
rxelecidle3 : in std_logic_vector(0 downto 0);
rxstatus3 : in std_logic_vector(2 downto 0);
rxdataskip3 : in std_logic_vector(0 downto 0);
rxblkst3 : in std_logic_vector(0 downto 0);
rxsynchd3 : in std_logic_vector(1 downto 0);
rxfreqlocked3 : in std_logic_vector(0 downto 0);
txdata4 : out std_logic_vector(31 downto 0);
txdatak4 : out std_logic_vector(3 downto 0);
txdetectrx4 : out std_logic_vector(0 downto 0);
txelecidle4 : out std_logic_vector(0 downto 0);
txcompl4 : out std_logic_vector(0 downto 0);
rxpolarity4 : out std_logic_vector(0 downto 0);
powerdown4 : out std_logic_vector(1 downto 0);
txdataskip4 : out std_logic_vector(0 downto 0);
txblkst4 : out std_logic_vector(0 downto 0);
txsynchd4 : out std_logic_vector(1 downto 0);
txdeemph4 : out std_logic_vector(0 downto 0);
txmargin4 : out std_logic_vector(2 downto 0);
rxdata4 : in std_logic_vector(31 downto 0);
rxdatak4 : in std_logic_vector(3 downto 0);
rxvalid4 : in std_logic_vector(0 downto 0);
phystatus4 : in std_logic_vector(0 downto 0);
rxelecidle4 : in std_logic_vector(0 downto 0);
rxstatus4 : in std_logic_vector(2 downto 0);
rxdataskip4 : in std_logic_vector(0 downto 0);
rxblkst4 : in std_logic_vector(0 downto 0);
rxsynchd4 : in std_logic_vector(1 downto 0);
rxfreqlocked4 : in std_logic_vector(0 downto 0);
txdata5 : out std_logic_vector(31 downto 0);
txdatak5 : out std_logic_vector(3 downto 0);
txdetectrx5 : out std_logic_vector(0 downto 0);
txelecidle5 : out std_logic_vector(0 downto 0);
txcompl5 : out std_logic_vector(0 downto 0);
rxpolarity5 : out std_logic_vector(0 downto 0);
powerdown5 : out std_logic_vector(1 downto 0);
txdataskip5 : out std_logic_vector(0 downto 0);
txblkst5 : out std_logic_vector(0 downto 0);
txsynchd5 : out std_logic_vector(1 downto 0);
txdeemph5 : out std_logic_vector(0 downto 0);
txmargin5 : out std_logic_vector(2 downto 0);
rxdata5 : in std_logic_vector(31 downto 0);
rxdatak5 : in std_logic_vector(3 downto 0);
rxvalid5 : in std_logic_vector(0 downto 0);
phystatus5 : in std_logic_vector(0 downto 0);
rxelecidle5 : in std_logic_vector(0 downto 0);
rxstatus5 : in std_logic_vector(2 downto 0);
rxdataskip5 : in std_logic_vector(0 downto 0);
rxblkst5 : in std_logic_vector(0 downto 0);
rxsynchd5 : in std_logic_vector(1 downto 0);
rxfreqlocked5 : in std_logic_vector(0 downto 0);
txdata6 : out std_logic_vector(31 downto 0);
txdatak6 : out std_logic_vector(3 downto 0);
txdetectrx6 : out std_logic_vector(0 downto 0);
txelecidle6 : out std_logic_vector(0 downto 0);
txcompl6 : out std_logic_vector(0 downto 0);
rxpolarity6 : out std_logic_vector(0 downto 0);
powerdown6 : out std_logic_vector(1 downto 0);
txdataskip6 : out std_logic_vector(0 downto 0);
txblkst6 : out std_logic_vector(0 downto 0);
txsynchd6 : out std_logic_vector(1 downto 0);
txdeemph6 : out std_logic_vector(0 downto 0);
txmargin6 : out std_logic_vector(2 downto 0);
rxdata6 : in std_logic_vector(31 downto 0);
rxdatak6 : in std_logic_vector(3 downto 0);
rxvalid6 : in std_logic_vector(0 downto 0);
phystatus6 : in std_logic_vector(0 downto 0);
rxelecidle6 : in std_logic_vector(0 downto 0);
rxstatus6 : in std_logic_vector(2 downto 0);
rxdataskip6 : in std_logic_vector(0 downto 0);
rxblkst6 : in std_logic_vector(0 downto 0);
rxsynchd6 : in std_logic_vector(1 downto 0);
rxfreqlocked6 : in std_logic_vector(0 downto 0);
txdata7 : out std_logic_vector(31 downto 0);
txdatak7 : out std_logic_vector(3 downto 0);
txdetectrx7 : out std_logic_vector(0 downto 0);
txelecidle7 : out std_logic_vector(0 downto 0);
txcompl7 : out std_logic_vector(0 downto 0);
rxpolarity7 : out std_logic_vector(0 downto 0);
powerdown7 : out std_logic_vector(1 downto 0);
txdataskip7 : out std_logic_vector(0 downto 0);
txblkst7 : out std_logic_vector(0 downto 0);
txsynchd7 : out std_logic_vector(1 downto 0);
txdeemph7 : out std_logic_vector(0 downto 0);
txmargin7 : out std_logic_vector(2 downto 0);
rxdata7 : in std_logic_vector(31 downto 0);
rxdatak7 : in std_logic_vector(3 downto 0);
rxvalid7 : in std_logic_vector(0 downto 0);
phystatus7 : in std_logic_vector(0 downto 0);
rxelecidle7 : in std_logic_vector(0 downto 0);
rxstatus7 : in std_logic_vector(2 downto 0);
rxdataskip7 : in std_logic_vector(0 downto 0);
rxblkst7 : in std_logic_vector(0 downto 0);
rxsynchd7 : in std_logic_vector(1 downto 0);
rxfreqlocked7 : in std_logic_vector(0 downto 0);
dbgpipex1rx : in std_logic_vector(43 downto 0);
memredsclk : in std_logic_vector(0 downto 0);
memredenscan : in std_logic_vector(0 downto 0);
memredscen : in std_logic_vector(0 downto 0);
memredscin : in std_logic_vector(0 downto 0);
memredscsel : in std_logic_vector(0 downto 0);
memredscrst : in std_logic_vector(0 downto 0);
memredscout : out std_logic_vector(0 downto 0);
memregscanen : in std_logic_vector(0 downto 0);
memregscanin : in std_logic_vector(0 downto 0);
memhiptestenable : in std_logic_vector(0 downto 0);
memregscanout : out std_logic_vector(0 downto 0);
bisttesten : in std_logic_vector(0 downto 0);
bistenrpl : in std_logic_vector(0 downto 0);
bistscanin : in std_logic_vector(0 downto 0);
bistscanen : in std_logic_vector(0 downto 0);
bistenrcv : in std_logic_vector(0 downto 0);
bistscanoutrpl : out std_logic_vector(0 downto 0);
bistdonearpl : out std_logic_vector(0 downto 0);
bistdonebrpl : out std_logic_vector(0 downto 0);
bistpassrpl : out std_logic_vector(0 downto 0);
derrrpl : out std_logic_vector(0 downto 0);
derrcorextrpl : out std_logic_vector(0 downto 0);
bistscanoutrcv : out std_logic_vector(0 downto 0);
bistdonearcv : out std_logic_vector(0 downto 0);
bistdonebrcv : out std_logic_vector(0 downto 0);
bistpassrcv : out std_logic_vector(0 downto 0);
derrcorextrcv : out std_logic_vector(0 downto 0);
bistscanoutrcv1 : out std_logic_vector(0 downto 0);
bistdonearcv1 : out std_logic_vector(0 downto 0);
bistdonebrcv1 : out std_logic_vector(0 downto 0);
bistpassrcv1 : out std_logic_vector(0 downto 0);
derrcorextrcv1 : out std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
nfrzdrv : in std_logic_vector(0 downto 0);
frzreg : in std_logic_vector(0 downto 0);
frzlogic : in std_logic_vector(0 downto 0);
idrpl : in std_logic_vector(7 downto 0);
idrcv : in std_logic_vector(7 downto 0);
plniotri : in std_logic_vector(0 downto 0);
entest : in std_logic_vector(0 downto 0);
npor : in std_logic_vector(0 downto 0);
usermode : in std_logic_vector(0 downto 0);
cvpclk : out std_logic_vector(0 downto 0);
cvpdata : out std_logic_vector(31 downto 0);
cvpstartxfer : out std_logic_vector(0 downto 0);
cvpconfig : out std_logic_vector(0 downto 0);
cvpfullconfig : out std_logic_vector(0 downto 0);
cvpconfigready : in std_logic_vector(0 downto 0);
cvpen : in std_logic_vector(0 downto 0);
cvpconfigerror : in std_logic_vector(0 downto 0);
cvpconfigdone : in std_logic_vector(0 downto 0);
pinperstn : in std_logic_vector(0 downto 0);
pldperstn : in std_logic_vector(0 downto 0);
iocsrrdydly : in std_logic_vector(0 downto 0);
softaltpe3rstn : in std_logic_vector(0 downto 0);
softaltpe3srstn : in std_logic_vector(0 downto 0);
softaltpe3crstn : in std_logic_vector(0 downto 0);
pldclrpmapcshipn : in std_logic_vector(0 downto 0);
pldclrpcshipn : in std_logic_vector(0 downto 0);
pldclrhipn : in std_logic_vector(0 downto 0);
s0ch0emsiptieoff : out std_logic_vector(100 downto 0);
s0ch1emsiptieoff : out std_logic_vector(100 downto 0);
s0ch2emsiptieoff : out std_logic_vector(100 downto 0);
s1ch0emsiptieoff : out std_logic_vector(100 downto 0);
s1ch1emsiptieoff : out std_logic_vector(188 downto 0);
s1ch2emsiptieoff : out std_logic_vector(100 downto 0);
s2ch0emsiptieoff : out std_logic_vector(100 downto 0);
s2ch1emsiptieoff : out std_logic_vector(100 downto 0);
s2ch2emsiptieoff : out std_logic_vector(100 downto 0);
s3ch0emsiptieoff : out std_logic_vector(188 downto 0);
s3ch1emsiptieoff : out std_logic_vector(188 downto 0);
s3ch2emsiptieoff : out std_logic_vector(188 downto 0);
emsiptieofftop : out std_logic_vector(299 downto 0);
emsiptieoffbot : out std_logic_vector(299 downto 0);
txpcsrstn0 : out std_logic_vector(0 downto 0);
rxpcsrstn0 : out std_logic_vector(0 downto 0);
g3txpcsrstn0 : out std_logic_vector(0 downto 0);
g3rxpcsrstn0 : out std_logic_vector(0 downto 0);
txpmasyncp0 : out std_logic_vector(0 downto 0);
rxpmarstb0 : out std_logic_vector(0 downto 0);
txlcpllrstb0 : out std_logic_vector(0 downto 0);
offcalen0 : out std_logic_vector(0 downto 0);
frefclk0 : in std_logic_vector(0 downto 0);
offcaldone0 : in std_logic_vector(0 downto 0);
txlcplllock0 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock0 : in std_logic_vector(0 downto 0);
rxpllphaselock0 : in std_logic_vector(0 downto 0);
masktxplllock0 : in std_logic_vector(0 downto 0);
txpcsrstn1 : out std_logic_vector(0 downto 0);
rxpcsrstn1 : out std_logic_vector(0 downto 0);
g3txpcsrstn1 : out std_logic_vector(0 downto 0);
g3rxpcsrstn1 : out std_logic_vector(0 downto 0);
txpmasyncp1 : out std_logic_vector(0 downto 0);
rxpmarstb1 : out std_logic_vector(0 downto 0);
txlcpllrstb1 : out std_logic_vector(0 downto 0);
offcalen1 : out std_logic_vector(0 downto 0);
frefclk1 : in std_logic_vector(0 downto 0);
offcaldone1 : in std_logic_vector(0 downto 0);
txlcplllock1 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock1 : in std_logic_vector(0 downto 0);
rxpllphaselock1 : in std_logic_vector(0 downto 0);
masktxplllock1 : in std_logic_vector(0 downto 0);
txpcsrstn2 : out std_logic_vector(0 downto 0);
rxpcsrstn2 : out std_logic_vector(0 downto 0);
g3txpcsrstn2 : out std_logic_vector(0 downto 0);
g3rxpcsrstn2 : out std_logic_vector(0 downto 0);
txpmasyncp2 : out std_logic_vector(0 downto 0);
rxpmarstb2 : out std_logic_vector(0 downto 0);
txlcpllrstb2 : out std_logic_vector(0 downto 0);
offcalen2 : out std_logic_vector(0 downto 0);
frefclk2 : in std_logic_vector(0 downto 0);
offcaldone2 : in std_logic_vector(0 downto 0);
txlcplllock2 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock2 : in std_logic_vector(0 downto 0);
rxpllphaselock2 : in std_logic_vector(0 downto 0);
masktxplllock2 : in std_logic_vector(0 downto 0);
txpcsrstn3 : out std_logic_vector(0 downto 0);
rxpcsrstn3 : out std_logic_vector(0 downto 0);
g3txpcsrstn3 : out std_logic_vector(0 downto 0);
g3rxpcsrstn3 : out std_logic_vector(0 downto 0);
txpmasyncp3 : out std_logic_vector(0 downto 0);
rxpmarstb3 : out std_logic_vector(0 downto 0);
txlcpllrstb3 : out std_logic_vector(0 downto 0);
offcalen3 : out std_logic_vector(0 downto 0);
frefclk3 : in std_logic_vector(0 downto 0);
offcaldone3 : in std_logic_vector(0 downto 0);
txlcplllock3 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock3 : in std_logic_vector(0 downto 0);
rxpllphaselock3 : in std_logic_vector(0 downto 0);
masktxplllock3 : in std_logic_vector(0 downto 0);
txpcsrstn4 : out std_logic_vector(0 downto 0);
rxpcsrstn4 : out std_logic_vector(0 downto 0);
g3txpcsrstn4 : out std_logic_vector(0 downto 0);
g3rxpcsrstn4 : out std_logic_vector(0 downto 0);
txpmasyncp4 : out std_logic_vector(0 downto 0);
rxpmarstb4 : out std_logic_vector(0 downto 0);
txlcpllrstb4 : out std_logic_vector(0 downto 0);
offcalen4 : out std_logic_vector(0 downto 0);
frefclk4 : in std_logic_vector(0 downto 0);
offcaldone4 : in std_logic_vector(0 downto 0);
txlcplllock4 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock4 : in std_logic_vector(0 downto 0);
rxpllphaselock4 : in std_logic_vector(0 downto 0);
masktxplllock4 : in std_logic_vector(0 downto 0);
txpcsrstn5 : out std_logic_vector(0 downto 0);
rxpcsrstn5 : out std_logic_vector(0 downto 0);
g3txpcsrstn5 : out std_logic_vector(0 downto 0);
g3rxpcsrstn5 : out std_logic_vector(0 downto 0);
txpmasyncp5 : out std_logic_vector(0 downto 0);
rxpmarstb5 : out std_logic_vector(0 downto 0);
txlcpllrstb5 : out std_logic_vector(0 downto 0);
offcalen5 : out std_logic_vector(0 downto 0);
frefclk5 : in std_logic_vector(0 downto 0);
offcaldone5 : in std_logic_vector(0 downto 0);
txlcplllock5 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock5 : in std_logic_vector(0 downto 0);
rxpllphaselock5 : in std_logic_vector(0 downto 0);
masktxplllock5 : in std_logic_vector(0 downto 0);
txpcsrstn6 : out std_logic_vector(0 downto 0);
rxpcsrstn6 : out std_logic_vector(0 downto 0);
g3txpcsrstn6 : out std_logic_vector(0 downto 0);
g3rxpcsrstn6 : out std_logic_vector(0 downto 0);
txpmasyncp6 : out std_logic_vector(0 downto 0);
rxpmarstb6 : out std_logic_vector(0 downto 0);
txlcpllrstb6 : out std_logic_vector(0 downto 0);
offcalen6 : out std_logic_vector(0 downto 0);
frefclk6 : in std_logic_vector(0 downto 0);
offcaldone6 : in std_logic_vector(0 downto 0);
txlcplllock6 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock6 : in std_logic_vector(0 downto 0);
rxpllphaselock6 : in std_logic_vector(0 downto 0);
masktxplllock6 : in std_logic_vector(0 downto 0);
txpcsrstn7 : out std_logic_vector(0 downto 0);
rxpcsrstn7 : out std_logic_vector(0 downto 0);
g3txpcsrstn7 : out std_logic_vector(0 downto 0);
g3rxpcsrstn7 : out std_logic_vector(0 downto 0);
txpmasyncp7 : out std_logic_vector(0 downto 0);
rxpmarstb7 : out std_logic_vector(0 downto 0);
txlcpllrstb7 : out std_logic_vector(0 downto 0);
offcalen7 : out std_logic_vector(0 downto 0);
frefclk7 : in std_logic_vector(0 downto 0);
offcaldone7 : in std_logic_vector(0 downto 0);
txlcplllock7 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock7 : in std_logic_vector(0 downto 0);
rxpllphaselock7 : in std_logic_vector(0 downto 0);
masktxplllock7 : in std_logic_vector(0 downto 0);
txpcsrstn8 : out std_logic_vector(0 downto 0);
rxpcsrstn8 : out std_logic_vector(0 downto 0);
g3txpcsrstn8 : out std_logic_vector(0 downto 0);
g3rxpcsrstn8 : out std_logic_vector(0 downto 0);
txpmasyncp8 : out std_logic_vector(0 downto 0);
rxpmarstb8 : out std_logic_vector(0 downto 0);
txlcpllrstb8 : out std_logic_vector(0 downto 0);
offcalen8 : out std_logic_vector(0 downto 0);
frefclk8 : in std_logic_vector(0 downto 0);
offcaldone8 : in std_logic_vector(0 downto 0);
txlcplllock8 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock8 : in std_logic_vector(0 downto 0);
rxpllphaselock8 : in std_logic_vector(0 downto 0);
masktxplllock8 : in std_logic_vector(0 downto 0);
txpcsrstn9 : out std_logic_vector(0 downto 0);
rxpcsrstn9 : out std_logic_vector(0 downto 0);
g3txpcsrstn9 : out std_logic_vector(0 downto 0);
g3rxpcsrstn9 : out std_logic_vector(0 downto 0);
txpmasyncp9 : out std_logic_vector(0 downto 0);
rxpmarstb9 : out std_logic_vector(0 downto 0);
txlcpllrstb9 : out std_logic_vector(0 downto 0);
offcalen9 : out std_logic_vector(0 downto 0);
frefclk9 : in std_logic_vector(0 downto 0);
offcaldone9 : in std_logic_vector(0 downto 0);
txlcplllock9 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock9 : in std_logic_vector(0 downto 0);
rxpllphaselock9 : in std_logic_vector(0 downto 0);
masktxplllock9 : in std_logic_vector(0 downto 0);
txpcsrstn10 : out std_logic_vector(0 downto 0);
rxpcsrstn10 : out std_logic_vector(0 downto 0);
g3txpcsrstn10 : out std_logic_vector(0 downto 0);
g3rxpcsrstn10 : out std_logic_vector(0 downto 0);
txpmasyncp10 : out std_logic_vector(0 downto 0);
rxpmarstb10 : out std_logic_vector(0 downto 0);
txlcpllrstb10 : out std_logic_vector(0 downto 0);
offcalen10 : out std_logic_vector(0 downto 0);
frefclk10 : in std_logic_vector(0 downto 0);
offcaldone10 : in std_logic_vector(0 downto 0);
txlcplllock10 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock10 : in std_logic_vector(0 downto 0);
rxpllphaselock10 : in std_logic_vector(0 downto 0);
masktxplllock10 : in std_logic_vector(0 downto 0);
txpcsrstn11 : out std_logic_vector(0 downto 0);
rxpcsrstn11 : out std_logic_vector(0 downto 0);
g3txpcsrstn11 : out std_logic_vector(0 downto 0);
g3rxpcsrstn11 : out std_logic_vector(0 downto 0);
txpmasyncp11 : out std_logic_vector(0 downto 0);
rxpmarstb11 : out std_logic_vector(0 downto 0);
txlcpllrstb11 : out std_logic_vector(0 downto 0);
offcalen11 : out std_logic_vector(0 downto 0);
frefclk11 : in std_logic_vector(0 downto 0);
offcaldone11 : in std_logic_vector(0 downto 0);
txlcplllock11 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock11 : in std_logic_vector(0 downto 0);
rxpllphaselock11 : in std_logic_vector(0 downto 0);
masktxplllock11 : in std_logic_vector(0 downto 0);
reservedin : in std_logic_vector(31 downto 0);
reservedclkin : in std_logic_vector(0 downto 0);
reservedout : out std_logic_vector(31 downto 0);
reservedclkout : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_gen3_pcie_hip_encrypted
generic map (
func_mode => func_mode,
in_cvp_mode => in_cvp_mode,
bonding_mode => bonding_mode,
prot_mode => prot_mode,
pcie_spec_1p0_compliance => pcie_spec_1p0_compliance,
vc_enable => vc_enable,
enable_slot_register => enable_slot_register,
pcie_mode => pcie_mode,
bypass_cdc => bypass_cdc,
enable_rx_reordering => enable_rx_reordering,
enable_rx_buffer_checking => enable_rx_buffer_checking,
single_rx_detect_data => single_rx_detect_data,
single_rx_detect => single_rx_detect,
use_crc_forwarding => use_crc_forwarding,
bypass_tl => bypass_tl,
gen123_lane_rate_mode => gen123_lane_rate_mode,
lane_mask => lane_mask,
disable_link_x2_support => disable_link_x2_support,
national_inst_thru_enhance => national_inst_thru_enhance,
hip_hard_reset => hip_hard_reset,
dis_paritychk => dis_paritychk,
wrong_device_id => wrong_device_id,
data_pack_rx => data_pack_rx,
ast_width => ast_width,
rx_sop_ctrl => rx_sop_ctrl,
rx_ast_parity => rx_ast_parity,
tx_ast_parity => tx_ast_parity,
ltssm_1ms_timeout => ltssm_1ms_timeout,
ltssm_freqlocked_check => ltssm_freqlocked_check,
deskew_comma => deskew_comma,
dl_tx_check_parity_edb => dl_tx_check_parity_edb,
tl_tx_check_parity_msg => tl_tx_check_parity_msg,
port_link_number_data => port_link_number_data,
port_link_number => port_link_number,
device_number_data => device_number_data,
device_number => device_number,
bypass_clk_switch => bypass_clk_switch,
core_clk_out_sel => core_clk_out_sel,
core_clk_divider => core_clk_divider,
core_clk_source => core_clk_source,
core_clk_sel => core_clk_sel,
enable_ch0_pclk_out => enable_ch0_pclk_out,
enable_ch01_pclk_out => enable_ch01_pclk_out,
pipex1_debug_sel => pipex1_debug_sel,
pclk_out_sel => pclk_out_sel,
vendor_id_data => vendor_id_data,
vendor_id => vendor_id,
device_id_data => device_id_data,
device_id => device_id,
revision_id_data => revision_id_data,
revision_id => revision_id,
class_code_data => class_code_data,
class_code => class_code,
subsystem_vendor_id_data => subsystem_vendor_id_data,
subsystem_vendor_id => subsystem_vendor_id,
subsystem_device_id_data => subsystem_device_id_data,
subsystem_device_id => subsystem_device_id,
no_soft_reset => no_soft_reset,
maximum_current_data => maximum_current_data,
maximum_current => maximum_current,
d1_support => d1_support,
d2_support => d2_support,
d0_pme => d0_pme,
d1_pme => d1_pme,
d2_pme => d2_pme,
d3_hot_pme => d3_hot_pme,
d3_cold_pme => d3_cold_pme,
use_aer => use_aer,
low_priority_vc => low_priority_vc,
vc_arbitration => vc_arbitration,
disable_snoop_packet => disable_snoop_packet,
max_payload_size => max_payload_size,
surprise_down_error_support => surprise_down_error_support,
dll_active_report_support => dll_active_report_support,
extend_tag_field => extend_tag_field,
endpoint_l0_latency_data => endpoint_l0_latency_data,
endpoint_l0_latency => endpoint_l0_latency,
endpoint_l1_latency_data => endpoint_l1_latency_data,
endpoint_l1_latency => endpoint_l1_latency,
indicator_data => indicator_data,
indicator => indicator,
role_based_error_reporting => role_based_error_reporting,
slot_power_scale_data => slot_power_scale_data,
slot_power_scale => slot_power_scale,
max_link_width => max_link_width,
enable_l1_aspm => enable_l1_aspm,
enable_l0s_aspm => enable_l0s_aspm,
l1_exit_latency_sameclock_data => l1_exit_latency_sameclock_data,
l1_exit_latency_sameclock => l1_exit_latency_sameclock,
l1_exit_latency_diffclock_data => l1_exit_latency_diffclock_data,
l1_exit_latency_diffclock => l1_exit_latency_diffclock,
hot_plug_support_data => hot_plug_support_data,
hot_plug_support => hot_plug_support,
slot_power_limit_data => slot_power_limit_data,
slot_power_limit => slot_power_limit,
slot_number_data => slot_number_data,
slot_number => slot_number,
diffclock_nfts_count_data => diffclock_nfts_count_data,
diffclock_nfts_count => diffclock_nfts_count,
sameclock_nfts_count_data => sameclock_nfts_count_data,
sameclock_nfts_count => sameclock_nfts_count,
completion_timeout => completion_timeout,
enable_completion_timeout_disable => enable_completion_timeout_disable,
extended_tag_reset => extended_tag_reset,
ecrc_check_capable => ecrc_check_capable,
ecrc_gen_capable => ecrc_gen_capable,
no_command_completed => no_command_completed,
msi_multi_message_capable => msi_multi_message_capable,
msi_64bit_addressing_capable => msi_64bit_addressing_capable,
msi_masking_capable => msi_masking_capable,
msi_support => msi_support,
interrupt_pin => interrupt_pin,
ena_ido_req => ena_ido_req,
ena_ido_cpl => ena_ido_cpl,
enable_function_msix_support => enable_function_msix_support,
msix_table_size_data => msix_table_size_data,
msix_table_size => msix_table_size,
msix_table_bir_data => msix_table_bir_data,
msix_table_bir => msix_table_bir,
msix_table_offset_data => msix_table_offset_data,
msix_table_offset => msix_table_offset,
msix_pba_bir_data => msix_pba_bir_data,
msix_pba_bir => msix_pba_bir,
msix_pba_offset_data => msix_pba_offset_data,
msix_pba_offset => msix_pba_offset,
bridge_port_vga_enable => bridge_port_vga_enable,
bridge_port_ssid_support => bridge_port_ssid_support,
ssvid_data => ssvid_data,
ssvid => ssvid,
ssid_data => ssid_data,
ssid => ssid,
eie_before_nfts_count_data => eie_before_nfts_count_data,
eie_before_nfts_count => eie_before_nfts_count,
gen2_diffclock_nfts_count_data => gen2_diffclock_nfts_count_data,
gen2_diffclock_nfts_count => gen2_diffclock_nfts_count,
gen2_sameclock_nfts_count_data => gen2_sameclock_nfts_count_data,
gen2_sameclock_nfts_count => gen2_sameclock_nfts_count,
deemphasis_enable => deemphasis_enable,
pcie_spec_version => pcie_spec_version,
l0_exit_latency_sameclock_data => l0_exit_latency_sameclock_data,
l0_exit_latency_sameclock => l0_exit_latency_sameclock,
l0_exit_latency_diffclock_data => l0_exit_latency_diffclock_data,
l0_exit_latency_diffclock => l0_exit_latency_diffclock,
rx_ei_l0s => rx_ei_l0s,
l2_async_logic => l2_async_logic,
aspm_config_management => aspm_config_management,
atomic_op_routing => atomic_op_routing,
atomic_op_completer_32bit => atomic_op_completer_32bit,
atomic_op_completer_64bit => atomic_op_completer_64bit,
cas_completer_128bit => cas_completer_128bit,
ltr_mechanism => ltr_mechanism,
tph_completer => tph_completer,
extended_format_field => extended_format_field,
atomic_malformed => atomic_malformed,
flr_capability => flr_capability,
enable_adapter_half_rate_mode => enable_adapter_half_rate_mode,
vc0_clk_enable => vc0_clk_enable,
vc1_clk_enable => vc1_clk_enable,
register_pipe_signals => register_pipe_signals,
bar0_io_space => bar0_io_space,
bar0_64bit_mem_space => bar0_64bit_mem_space,
bar0_prefetchable => bar0_prefetchable,
bar0_size_mask_data => bar0_size_mask_data,
bar0_size_mask => bar0_size_mask,
bar1_io_space => bar1_io_space,
bar1_64bit_mem_space => bar1_64bit_mem_space,
bar1_prefetchable => bar1_prefetchable,
bar1_size_mask_data => bar1_size_mask_data,
bar1_size_mask => bar1_size_mask,
bar2_io_space => bar2_io_space,
bar2_64bit_mem_space => bar2_64bit_mem_space,
bar2_prefetchable => bar2_prefetchable,
bar2_size_mask_data => bar2_size_mask_data,
bar2_size_mask => bar2_size_mask,
bar3_io_space => bar3_io_space,
bar3_64bit_mem_space => bar3_64bit_mem_space,
bar3_prefetchable => bar3_prefetchable,
bar3_size_mask_data => bar3_size_mask_data,
bar3_size_mask => bar3_size_mask,
bar4_io_space => bar4_io_space,
bar4_64bit_mem_space => bar4_64bit_mem_space,
bar4_prefetchable => bar4_prefetchable,
bar4_size_mask_data => bar4_size_mask_data,
bar4_size_mask => bar4_size_mask,
bar5_io_space => bar5_io_space,
bar5_64bit_mem_space => bar5_64bit_mem_space,
bar5_prefetchable => bar5_prefetchable,
bar5_size_mask_data => bar5_size_mask_data,
bar5_size_mask => bar5_size_mask,
expansion_base_address_register_data => expansion_base_address_register_data,
expansion_base_address_register => expansion_base_address_register,
io_window_addr_width => io_window_addr_width,
prefetchable_mem_window_addr_width => prefetchable_mem_window_addr_width,
skp_os_gen3_count_data => skp_os_gen3_count_data,
skp_os_gen3_count => skp_os_gen3_count,
rx_cdc_almost_empty_data => rx_cdc_almost_empty_data,
rx_cdc_almost_empty => rx_cdc_almost_empty,
tx_cdc_almost_empty_data => tx_cdc_almost_empty_data,
tx_cdc_almost_empty => tx_cdc_almost_empty,
rx_cdc_almost_full_data => rx_cdc_almost_full_data,
rx_cdc_almost_full => rx_cdc_almost_full,
tx_cdc_almost_full_data => tx_cdc_almost_full_data,
tx_cdc_almost_full => tx_cdc_almost_full,
rx_l0s_count_idl_data => rx_l0s_count_idl_data,
rx_l0s_count_idl => rx_l0s_count_idl,
cdc_dummy_insert_limit_data => cdc_dummy_insert_limit_data,
cdc_dummy_insert_limit => cdc_dummy_insert_limit,
ei_delay_powerdown_count_data => ei_delay_powerdown_count_data,
ei_delay_powerdown_count => ei_delay_powerdown_count,
millisecond_cycle_count_data => millisecond_cycle_count_data,
millisecond_cycle_count => millisecond_cycle_count,
skp_os_schedule_count_data => skp_os_schedule_count_data,
skp_os_schedule_count => skp_os_schedule_count,
fc_init_timer_data => fc_init_timer_data,
fc_init_timer => fc_init_timer,
l01_entry_latency_data => l01_entry_latency_data,
l01_entry_latency => l01_entry_latency,
flow_control_update_count_data => flow_control_update_count_data,
flow_control_update_count => flow_control_update_count,
flow_control_timeout_count_data => flow_control_timeout_count_data,
flow_control_timeout_count => flow_control_timeout_count,
vc0_rx_flow_ctrl_posted_header_data => vc0_rx_flow_ctrl_posted_header_data,
vc0_rx_flow_ctrl_posted_header => vc0_rx_flow_ctrl_posted_header,
vc0_rx_flow_ctrl_posted_data_data => vc0_rx_flow_ctrl_posted_data_data,
vc0_rx_flow_ctrl_posted_data => vc0_rx_flow_ctrl_posted_data,
vc0_rx_flow_ctrl_nonposted_header_data => vc0_rx_flow_ctrl_nonposted_header_data,
vc0_rx_flow_ctrl_nonposted_header => vc0_rx_flow_ctrl_nonposted_header,
vc0_rx_flow_ctrl_nonposted_data_data => vc0_rx_flow_ctrl_nonposted_data_data,
vc0_rx_flow_ctrl_nonposted_data => vc0_rx_flow_ctrl_nonposted_data,
vc0_rx_flow_ctrl_compl_header_data => vc0_rx_flow_ctrl_compl_header_data,
vc0_rx_flow_ctrl_compl_header => vc0_rx_flow_ctrl_compl_header,
vc0_rx_flow_ctrl_compl_data_data => vc0_rx_flow_ctrl_compl_data_data,
vc0_rx_flow_ctrl_compl_data => vc0_rx_flow_ctrl_compl_data,
rx_ptr0_posted_dpram_min_data => rx_ptr0_posted_dpram_min_data,
rx_ptr0_posted_dpram_min => rx_ptr0_posted_dpram_min,
rx_ptr0_posted_dpram_max_data => rx_ptr0_posted_dpram_max_data,
rx_ptr0_posted_dpram_max => rx_ptr0_posted_dpram_max,
rx_ptr0_nonposted_dpram_min_data => rx_ptr0_nonposted_dpram_min_data,
rx_ptr0_nonposted_dpram_min => rx_ptr0_nonposted_dpram_min,
rx_ptr0_nonposted_dpram_max_data => rx_ptr0_nonposted_dpram_max_data,
rx_ptr0_nonposted_dpram_max => rx_ptr0_nonposted_dpram_max,
retry_buffer_last_active_address_data => retry_buffer_last_active_address_data,
retry_buffer_last_active_address => retry_buffer_last_active_address,
retry_buffer_memory_settings_data => retry_buffer_memory_settings_data,
retry_buffer_memory_settings => retry_buffer_memory_settings,
vc0_rx_buffer_memory_settings_data => vc0_rx_buffer_memory_settings_data,
vc0_rx_buffer_memory_settings => vc0_rx_buffer_memory_settings,
bist_memory_settings_data => bist_memory_settings_data,
bist_memory_settings => bist_memory_settings,
credit_buffer_allocation_aux => credit_buffer_allocation_aux,
iei_enable_settings => iei_enable_settings,
vsec_id_data => vsec_id_data,
vsec_id => vsec_id,
cvp_rate_sel => cvp_rate_sel,
hard_reset_bypass => hard_reset_bypass,
cvp_data_compressed => cvp_data_compressed,
cvp_data_encrypted => cvp_data_encrypted,
cvp_mode_reset => cvp_mode_reset,
cvp_clk_reset => cvp_clk_reset,
vsec_cap_data => vsec_cap_data,
vsec_cap => vsec_cap,
jtag_id_data => jtag_id_data,
jtag_id => jtag_id,
user_id_data => user_id_data,
user_id => user_id,
cseb_extend_pci => cseb_extend_pci,
cseb_extend_pcie => cseb_extend_pcie,
cseb_cpl_status_during_cvp => cseb_cpl_status_during_cvp,
cseb_route_to_avl_rx_st => cseb_route_to_avl_rx_st,
cseb_config_bypass => cseb_config_bypass,
cseb_cpl_tag_checking => cseb_cpl_tag_checking,
cseb_bar_match_checking => cseb_bar_match_checking,
cseb_min_error_checking => cseb_min_error_checking,
cseb_temp_busy_crs => cseb_temp_busy_crs,
cseb_disable_auto_crs => cseb_disable_auto_crs,
gen3_diffclock_nfts_count_data => gen3_diffclock_nfts_count_data,
gen3_diffclock_nfts_count => gen3_diffclock_nfts_count,
gen3_sameclock_nfts_count_data => gen3_sameclock_nfts_count_data,
gen3_sameclock_nfts_count => gen3_sameclock_nfts_count,
gen3_coeff_errchk => gen3_coeff_errchk,
gen3_paritychk => gen3_paritychk,
gen3_coeff_delay_count_data => gen3_coeff_delay_count_data,
gen3_coeff_delay_count => gen3_coeff_delay_count,
gen3_coeff_1_data => gen3_coeff_1_data,
gen3_coeff_1 => gen3_coeff_1,
gen3_coeff_1_sel => gen3_coeff_1_sel,
gen3_coeff_1_preset_hint_data => gen3_coeff_1_preset_hint_data,
gen3_coeff_1_preset_hint => gen3_coeff_1_preset_hint,
gen3_coeff_1_nxtber_more_ptr => gen3_coeff_1_nxtber_more_ptr,
gen3_coeff_1_nxtber_more => gen3_coeff_1_nxtber_more,
gen3_coeff_1_nxtber_less_ptr => gen3_coeff_1_nxtber_less_ptr,
gen3_coeff_1_nxtber_less => gen3_coeff_1_nxtber_less,
gen3_coeff_1_reqber_data => gen3_coeff_1_reqber_data,
gen3_coeff_1_reqber => gen3_coeff_1_reqber,
gen3_coeff_1_ber_meas_data => gen3_coeff_1_ber_meas_data,
gen3_coeff_1_ber_meas => gen3_coeff_1_ber_meas,
gen3_coeff_2_data => gen3_coeff_2_data,
gen3_coeff_2 => gen3_coeff_2,
gen3_coeff_2_sel => gen3_coeff_2_sel,
gen3_coeff_2_preset_hint_data => gen3_coeff_2_preset_hint_data,
gen3_coeff_2_preset_hint => gen3_coeff_2_preset_hint,
gen3_coeff_2_nxtber_more_ptr => gen3_coeff_2_nxtber_more_ptr,
gen3_coeff_2_nxtber_more => gen3_coeff_2_nxtber_more,
gen3_coeff_2_nxtber_less_ptr => gen3_coeff_2_nxtber_less_ptr,
gen3_coeff_2_nxtber_less => gen3_coeff_2_nxtber_less,
gen3_coeff_2_reqber_data => gen3_coeff_2_reqber_data,
gen3_coeff_2_reqber => gen3_coeff_2_reqber,
gen3_coeff_2_ber_meas_data => gen3_coeff_2_ber_meas_data,
gen3_coeff_2_ber_meas => gen3_coeff_2_ber_meas,
gen3_coeff_3_data => gen3_coeff_3_data,
gen3_coeff_3 => gen3_coeff_3,
gen3_coeff_3_sel => gen3_coeff_3_sel,
gen3_coeff_3_preset_hint_data => gen3_coeff_3_preset_hint_data,
gen3_coeff_3_preset_hint => gen3_coeff_3_preset_hint,
gen3_coeff_3_nxtber_more_ptr => gen3_coeff_3_nxtber_more_ptr,
gen3_coeff_3_nxtber_more => gen3_coeff_3_nxtber_more,
gen3_coeff_3_nxtber_less_ptr => gen3_coeff_3_nxtber_less_ptr,
gen3_coeff_3_nxtber_less => gen3_coeff_3_nxtber_less,
gen3_coeff_3_reqber_data => gen3_coeff_3_reqber_data,
gen3_coeff_3_reqber => gen3_coeff_3_reqber,
gen3_coeff_3_ber_meas_data => gen3_coeff_3_ber_meas_data,
gen3_coeff_3_ber_meas => gen3_coeff_3_ber_meas,
gen3_coeff_4_data => gen3_coeff_4_data,
gen3_coeff_4 => gen3_coeff_4,
gen3_coeff_4_sel => gen3_coeff_4_sel,
gen3_coeff_4_preset_hint_data => gen3_coeff_4_preset_hint_data,
gen3_coeff_4_preset_hint => gen3_coeff_4_preset_hint,
gen3_coeff_4_nxtber_more_ptr => gen3_coeff_4_nxtber_more_ptr,
gen3_coeff_4_nxtber_more => gen3_coeff_4_nxtber_more,
gen3_coeff_4_nxtber_less_ptr => gen3_coeff_4_nxtber_less_ptr,
gen3_coeff_4_nxtber_less => gen3_coeff_4_nxtber_less,
gen3_coeff_4_reqber_data => gen3_coeff_4_reqber_data,
gen3_coeff_4_reqber => gen3_coeff_4_reqber,
gen3_coeff_4_ber_meas_data => gen3_coeff_4_ber_meas_data,
gen3_coeff_4_ber_meas => gen3_coeff_4_ber_meas,
gen3_coeff_5_data => gen3_coeff_5_data,
gen3_coeff_5 => gen3_coeff_5,
gen3_coeff_5_sel => gen3_coeff_5_sel,
gen3_coeff_5_preset_hint_data => gen3_coeff_5_preset_hint_data,
gen3_coeff_5_preset_hint => gen3_coeff_5_preset_hint,
gen3_coeff_5_nxtber_more_ptr => gen3_coeff_5_nxtber_more_ptr,
gen3_coeff_5_nxtber_more => gen3_coeff_5_nxtber_more,
gen3_coeff_5_nxtber_less_ptr => gen3_coeff_5_nxtber_less_ptr,
gen3_coeff_5_nxtber_less => gen3_coeff_5_nxtber_less,
gen3_coeff_5_reqber_data => gen3_coeff_5_reqber_data,
gen3_coeff_5_reqber => gen3_coeff_5_reqber,
gen3_coeff_5_ber_meas_data => gen3_coeff_5_ber_meas_data,
gen3_coeff_5_ber_meas => gen3_coeff_5_ber_meas,
gen3_coeff_6_data => gen3_coeff_6_data,
gen3_coeff_6 => gen3_coeff_6,
gen3_coeff_6_sel => gen3_coeff_6_sel,
gen3_coeff_6_preset_hint_data => gen3_coeff_6_preset_hint_data,
gen3_coeff_6_preset_hint => gen3_coeff_6_preset_hint,
gen3_coeff_6_nxtber_more_ptr => gen3_coeff_6_nxtber_more_ptr,
gen3_coeff_6_nxtber_more => gen3_coeff_6_nxtber_more,
gen3_coeff_6_nxtber_less_ptr => gen3_coeff_6_nxtber_less_ptr,
gen3_coeff_6_nxtber_less => gen3_coeff_6_nxtber_less,
gen3_coeff_6_reqber_data => gen3_coeff_6_reqber_data,
gen3_coeff_6_reqber => gen3_coeff_6_reqber,
gen3_coeff_6_ber_meas_data => gen3_coeff_6_ber_meas_data,
gen3_coeff_6_ber_meas => gen3_coeff_6_ber_meas,
gen3_coeff_7_data => gen3_coeff_7_data,
gen3_coeff_7 => gen3_coeff_7,
gen3_coeff_7_sel => gen3_coeff_7_sel,
gen3_coeff_7_preset_hint_data => gen3_coeff_7_preset_hint_data,
gen3_coeff_7_preset_hint => gen3_coeff_7_preset_hint,
gen3_coeff_7_nxtber_more_ptr => gen3_coeff_7_nxtber_more_ptr,
gen3_coeff_7_nxtber_more => gen3_coeff_7_nxtber_more,
gen3_coeff_7_nxtber_less_ptr => gen3_coeff_7_nxtber_less_ptr,
gen3_coeff_7_nxtber_less => gen3_coeff_7_nxtber_less,
gen3_coeff_7_reqber_data => gen3_coeff_7_reqber_data,
gen3_coeff_7_reqber => gen3_coeff_7_reqber,
gen3_coeff_7_ber_meas_data => gen3_coeff_7_ber_meas_data,
gen3_coeff_7_ber_meas => gen3_coeff_7_ber_meas,
gen3_coeff_8_data => gen3_coeff_8_data,
gen3_coeff_8 => gen3_coeff_8,
gen3_coeff_8_sel => gen3_coeff_8_sel,
gen3_coeff_8_preset_hint_data => gen3_coeff_8_preset_hint_data,
gen3_coeff_8_preset_hint => gen3_coeff_8_preset_hint,
gen3_coeff_8_nxtber_more_ptr => gen3_coeff_8_nxtber_more_ptr,
gen3_coeff_8_nxtber_more => gen3_coeff_8_nxtber_more,
gen3_coeff_8_nxtber_less_ptr => gen3_coeff_8_nxtber_less_ptr,
gen3_coeff_8_nxtber_less => gen3_coeff_8_nxtber_less,
gen3_coeff_8_reqber_data => gen3_coeff_8_reqber_data,
gen3_coeff_8_reqber => gen3_coeff_8_reqber,
gen3_coeff_8_ber_meas_data => gen3_coeff_8_ber_meas_data,
gen3_coeff_8_ber_meas => gen3_coeff_8_ber_meas,
gen3_coeff_9_data => gen3_coeff_9_data,
gen3_coeff_9 => gen3_coeff_9,
gen3_coeff_9_sel => gen3_coeff_9_sel,
gen3_coeff_9_preset_hint_data => gen3_coeff_9_preset_hint_data,
gen3_coeff_9_preset_hint => gen3_coeff_9_preset_hint,
gen3_coeff_9_nxtber_more_ptr => gen3_coeff_9_nxtber_more_ptr,
gen3_coeff_9_nxtber_more => gen3_coeff_9_nxtber_more,
gen3_coeff_9_nxtber_less_ptr => gen3_coeff_9_nxtber_less_ptr,
gen3_coeff_9_nxtber_less => gen3_coeff_9_nxtber_less,
gen3_coeff_9_reqber_data => gen3_coeff_9_reqber_data,
gen3_coeff_9_reqber => gen3_coeff_9_reqber,
gen3_coeff_9_ber_meas_data => gen3_coeff_9_ber_meas_data,
gen3_coeff_9_ber_meas => gen3_coeff_9_ber_meas,
gen3_coeff_10_data => gen3_coeff_10_data,
gen3_coeff_10 => gen3_coeff_10,
gen3_coeff_10_sel => gen3_coeff_10_sel,
gen3_coeff_10_preset_hint_data => gen3_coeff_10_preset_hint_data,
gen3_coeff_10_preset_hint => gen3_coeff_10_preset_hint,
gen3_coeff_10_nxtber_more_ptr => gen3_coeff_10_nxtber_more_ptr,
gen3_coeff_10_nxtber_more => gen3_coeff_10_nxtber_more,
gen3_coeff_10_nxtber_less_ptr => gen3_coeff_10_nxtber_less_ptr,
gen3_coeff_10_nxtber_less => gen3_coeff_10_nxtber_less,
gen3_coeff_10_reqber_data => gen3_coeff_10_reqber_data,
gen3_coeff_10_reqber => gen3_coeff_10_reqber,
gen3_coeff_10_ber_meas_data => gen3_coeff_10_ber_meas_data,
gen3_coeff_10_ber_meas => gen3_coeff_10_ber_meas,
gen3_coeff_11_data => gen3_coeff_11_data,
gen3_coeff_11 => gen3_coeff_11,
gen3_coeff_11_sel => gen3_coeff_11_sel,
gen3_coeff_11_preset_hint_data => gen3_coeff_11_preset_hint_data,
gen3_coeff_11_preset_hint => gen3_coeff_11_preset_hint,
gen3_coeff_11_nxtber_more_ptr => gen3_coeff_11_nxtber_more_ptr,
gen3_coeff_11_nxtber_more => gen3_coeff_11_nxtber_more,
gen3_coeff_11_nxtber_less_ptr => gen3_coeff_11_nxtber_less_ptr,
gen3_coeff_11_nxtber_less => gen3_coeff_11_nxtber_less,
gen3_coeff_11_reqber_data => gen3_coeff_11_reqber_data,
gen3_coeff_11_reqber => gen3_coeff_11_reqber,
gen3_coeff_11_ber_meas_data => gen3_coeff_11_ber_meas_data,
gen3_coeff_11_ber_meas => gen3_coeff_11_ber_meas,
gen3_coeff_12_data => gen3_coeff_12_data,
gen3_coeff_12 => gen3_coeff_12,
gen3_coeff_12_sel => gen3_coeff_12_sel,
gen3_coeff_12_preset_hint_data => gen3_coeff_12_preset_hint_data,
gen3_coeff_12_preset_hint => gen3_coeff_12_preset_hint,
gen3_coeff_12_nxtber_more_ptr => gen3_coeff_12_nxtber_more_ptr,
gen3_coeff_12_nxtber_more => gen3_coeff_12_nxtber_more,
gen3_coeff_12_nxtber_less_ptr => gen3_coeff_12_nxtber_less_ptr,
gen3_coeff_12_nxtber_less => gen3_coeff_12_nxtber_less,
gen3_coeff_12_reqber_data => gen3_coeff_12_reqber_data,
gen3_coeff_12_reqber => gen3_coeff_12_reqber,
gen3_coeff_12_ber_meas_data => gen3_coeff_12_ber_meas_data,
gen3_coeff_12_ber_meas => gen3_coeff_12_ber_meas,
gen3_coeff_13_data => gen3_coeff_13_data,
gen3_coeff_13 => gen3_coeff_13,
gen3_coeff_13_sel => gen3_coeff_13_sel,
gen3_coeff_13_preset_hint_data => gen3_coeff_13_preset_hint_data,
gen3_coeff_13_preset_hint => gen3_coeff_13_preset_hint,
gen3_coeff_13_nxtber_more_ptr => gen3_coeff_13_nxtber_more_ptr,
gen3_coeff_13_nxtber_more => gen3_coeff_13_nxtber_more,
gen3_coeff_13_nxtber_less_ptr => gen3_coeff_13_nxtber_less_ptr,
gen3_coeff_13_nxtber_less => gen3_coeff_13_nxtber_less,
gen3_coeff_13_reqber_data => gen3_coeff_13_reqber_data,
gen3_coeff_13_reqber => gen3_coeff_13_reqber,
gen3_coeff_13_ber_meas_data => gen3_coeff_13_ber_meas_data,
gen3_coeff_13_ber_meas => gen3_coeff_13_ber_meas,
gen3_coeff_14_data => gen3_coeff_14_data,
gen3_coeff_14 => gen3_coeff_14,
gen3_coeff_14_sel => gen3_coeff_14_sel,
gen3_coeff_14_preset_hint_data => gen3_coeff_14_preset_hint_data,
gen3_coeff_14_preset_hint => gen3_coeff_14_preset_hint,
gen3_coeff_14_nxtber_more_ptr => gen3_coeff_14_nxtber_more_ptr,
gen3_coeff_14_nxtber_more => gen3_coeff_14_nxtber_more,
gen3_coeff_14_nxtber_less_ptr => gen3_coeff_14_nxtber_less_ptr,
gen3_coeff_14_nxtber_less => gen3_coeff_14_nxtber_less,
gen3_coeff_14_reqber_data => gen3_coeff_14_reqber_data,
gen3_coeff_14_reqber => gen3_coeff_14_reqber,
gen3_coeff_14_ber_meas_data => gen3_coeff_14_ber_meas_data,
gen3_coeff_14_ber_meas => gen3_coeff_14_ber_meas,
gen3_coeff_15_data => gen3_coeff_15_data,
gen3_coeff_15 => gen3_coeff_15,
gen3_coeff_15_sel => gen3_coeff_15_sel,
gen3_coeff_15_preset_hint_data => gen3_coeff_15_preset_hint_data,
gen3_coeff_15_preset_hint => gen3_coeff_15_preset_hint,
gen3_coeff_15_nxtber_more_ptr => gen3_coeff_15_nxtber_more_ptr,
gen3_coeff_15_nxtber_more => gen3_coeff_15_nxtber_more,
gen3_coeff_15_nxtber_less_ptr => gen3_coeff_15_nxtber_less_ptr,
gen3_coeff_15_nxtber_less => gen3_coeff_15_nxtber_less,
gen3_coeff_15_reqber_data => gen3_coeff_15_reqber_data,
gen3_coeff_15_reqber => gen3_coeff_15_reqber,
gen3_coeff_15_ber_meas_data => gen3_coeff_15_ber_meas_data,
gen3_coeff_15_ber_meas => gen3_coeff_15_ber_meas,
gen3_coeff_16_data => gen3_coeff_16_data,
gen3_coeff_16 => gen3_coeff_16,
gen3_coeff_16_sel => gen3_coeff_16_sel,
gen3_coeff_16_preset_hint_data => gen3_coeff_16_preset_hint_data,
gen3_coeff_16_preset_hint => gen3_coeff_16_preset_hint,
gen3_coeff_16_nxtber_more_ptr => gen3_coeff_16_nxtber_more_ptr,
gen3_coeff_16_nxtber_more => gen3_coeff_16_nxtber_more,
gen3_coeff_16_nxtber_less_ptr => gen3_coeff_16_nxtber_less_ptr,
gen3_coeff_16_nxtber_less => gen3_coeff_16_nxtber_less,
gen3_coeff_16_reqber_data => gen3_coeff_16_reqber_data,
gen3_coeff_16_reqber => gen3_coeff_16_reqber,
gen3_coeff_16_ber_meas_data => gen3_coeff_16_ber_meas_data,
gen3_coeff_16_ber_meas => gen3_coeff_16_ber_meas,
gen3_preset_coeff_1_data => gen3_preset_coeff_1_data,
gen3_preset_coeff_1 => gen3_preset_coeff_1,
gen3_preset_coeff_2_data => gen3_preset_coeff_2_data,
gen3_preset_coeff_2 => gen3_preset_coeff_2,
gen3_preset_coeff_3_data => gen3_preset_coeff_3_data,
gen3_preset_coeff_3 => gen3_preset_coeff_3,
gen3_preset_coeff_4_data => gen3_preset_coeff_4_data,
gen3_preset_coeff_4 => gen3_preset_coeff_4,
gen3_preset_coeff_5_data => gen3_preset_coeff_5_data,
gen3_preset_coeff_5 => gen3_preset_coeff_5,
gen3_preset_coeff_6_data => gen3_preset_coeff_6_data,
gen3_preset_coeff_6 => gen3_preset_coeff_6,
gen3_preset_coeff_7_data => gen3_preset_coeff_7_data,
gen3_preset_coeff_7 => gen3_preset_coeff_7,
gen3_preset_coeff_8_data => gen3_preset_coeff_8_data,
gen3_preset_coeff_8 => gen3_preset_coeff_8,
gen3_preset_coeff_9_data => gen3_preset_coeff_9_data,
gen3_preset_coeff_9 => gen3_preset_coeff_9,
gen3_preset_coeff_10_data => gen3_preset_coeff_10_data,
gen3_preset_coeff_10 => gen3_preset_coeff_10,
gen3_rxfreqlock_counter_data => gen3_rxfreqlock_counter_data,
gen3_rxfreqlock_counter => gen3_rxfreqlock_counter,
rstctrl_pld_clr => rstctrl_pld_clr ,
rstctrl_debug_en => rstctrl_debug_en ,
rstctrl_force_inactive_rst => rstctrl_force_inactive_rst ,
rstctrl_perst_enable => rstctrl_perst_enable ,
hrdrstctrl_en => hrdrstctrl_en ,
rstctrl_hip_ep => rstctrl_hip_ep ,
rstctrl_hard_block_enable => rstctrl_hard_block_enable ,
rstctrl_rx_pma_rstb_inv => rstctrl_rx_pma_rstb_inv ,
rstctrl_tx_pma_rstb_inv => rstctrl_tx_pma_rstb_inv ,
rstctrl_rx_pcs_rst_n_inv => rstctrl_rx_pcs_rst_n_inv ,
rstctrl_tx_pcs_rst_n_inv => rstctrl_tx_pcs_rst_n_inv ,
rstctrl_altpe3_crst_n_inv => rstctrl_altpe3_crst_n_inv ,
rstctrl_altpe3_srst_n_inv => rstctrl_altpe3_srst_n_inv ,
rstctrl_altpe3_rst_n_inv => rstctrl_altpe3_rst_n_inv ,
rstctrl_tx_pma_syncp_inv => rstctrl_tx_pma_syncp_inv ,
rstctrl_1us_count_fref_clk => rstctrl_1us_count_fref_clk ,
rstctrl_1us_count_fref_clk_value => rstctrl_1us_count_fref_clk_value ,
rstctrl_1ms_count_fref_clk => rstctrl_1ms_count_fref_clk ,
rstctrl_1ms_count_fref_clk_value => rstctrl_1ms_count_fref_clk_value ,
rstctrl_off_cal_done_select => rstctrl_off_cal_done_select ,
rstctrl_rx_pma_rstb_cmu_select => rstctrl_rx_pma_rstb_cmu_select ,
rstctrl_rx_pll_freq_lock_select => rstctrl_rx_pll_freq_lock_select ,
rstctrl_mask_tx_pll_lock_select => rstctrl_mask_tx_pll_lock_select ,
rstctrl_rx_pll_lock_select => rstctrl_rx_pll_lock_select ,
rstctrl_perstn_select => rstctrl_perstn_select ,
rstctrl_tx_lc_pll_rstb_select => rstctrl_tx_lc_pll_rstb_select ,
rstctrl_fref_clk_select => rstctrl_fref_clk_select ,
rstctrl_off_cal_en_select => rstctrl_off_cal_en_select ,
rstctrl_tx_pma_syncp_select => rstctrl_tx_pma_syncp_select ,
rstctrl_rx_pcs_rst_n_select => rstctrl_rx_pcs_rst_n_select ,
rstctrl_tx_cmu_pll_lock_select => rstctrl_tx_cmu_pll_lock_select ,
rstctrl_tx_pcs_rst_n_select => rstctrl_tx_pcs_rst_n_select ,
rstctrl_tx_lc_pll_lock_select => rstctrl_tx_lc_pll_lock_select ,
rstctrl_timer_a => rstctrl_timer_a ,
rstctrl_timer_a_type => rstctrl_timer_a_type ,
rstctrl_timer_a_value => rstctrl_timer_a_value ,
rstctrl_timer_b => rstctrl_timer_b ,
rstctrl_timer_b_type => rstctrl_timer_b_type ,
rstctrl_timer_b_value => rstctrl_timer_b_value ,
rstctrl_timer_c => rstctrl_timer_c ,
rstctrl_timer_c_type => rstctrl_timer_c_type ,
rstctrl_timer_c_value => rstctrl_timer_c_value ,
rstctrl_timer_d => rstctrl_timer_d ,
rstctrl_timer_d_type => rstctrl_timer_d_type ,
rstctrl_timer_d_value => rstctrl_timer_d_value ,
rstctrl_timer_e => rstctrl_timer_e ,
rstctrl_timer_e_type => rstctrl_timer_e_type ,
rstctrl_timer_e_value => rstctrl_timer_e_value ,
rstctrl_timer_f => rstctrl_timer_f ,
rstctrl_timer_f_type => rstctrl_timer_f_type ,
rstctrl_timer_f_value => rstctrl_timer_f_value ,
rstctrl_timer_g => rstctrl_timer_g ,
rstctrl_timer_g_type => rstctrl_timer_g_type ,
rstctrl_timer_g_value => rstctrl_timer_g_value ,
rstctrl_timer_h => rstctrl_timer_h ,
rstctrl_timer_h_type => rstctrl_timer_h_type ,
rstctrl_timer_h_value => rstctrl_timer_h_value ,
rstctrl_timer_i => rstctrl_timer_i ,
rstctrl_timer_i_type => rstctrl_timer_i_type ,
rstctrl_timer_i_value => rstctrl_timer_i_value ,
rstctrl_timer_j => rstctrl_timer_j ,
rstctrl_timer_j_type => rstctrl_timer_j_type ,
rstctrl_timer_j_value => rstctrl_timer_j_value
)
port map (
dpriostatus => dpriostatus,
lmidout => lmidout,
lmiack => lmiack,
lmirden => lmirden,
lmiwren => lmiwren,
lmiaddr => lmiaddr,
lmidin => lmidin,
flrreset => flrreset,
flrsts => flrsts,
resetstatus => resetstatus,
l2exit => l2exit,
hotrstexit => hotrstexit,
hiphardreset => hiphardreset,
dlupexit => dlupexit,
coreclkout => coreclkout,
pldclk => pldclk,
pldsrst => pldsrst,
pldrst => pldrst,
pclkch0 => pclkch0,
pclkch1 => pclkch1,
pclkcentral => pclkcentral,
pllfixedclkch0 => pllfixedclkch0,
pllfixedclkch1 => pllfixedclkch1,
pllfixedclkcentral => pllfixedclkcentral,
phyrst => phyrst,
physrst => physrst,
coreclkin => coreclkin,
corerst => corerst,
corepor => corepor,
corecrst => corecrst,
coresrst => coresrst,
swdnout => swdnout,
swupout => swupout,
swdnin => swdnin,
swupin => swupin,
swctmod => swctmod,
rxstdata => rxstdata,
rxstparity => rxstparity,
rxstbe => rxstbe,
rxsterr => rxsterr,
rxstsop => rxstsop,
rxsteop => rxsteop,
rxstempty => rxstempty,
rxstvalid => rxstvalid,
rxstbardec1 => rxstbardec1,
rxstbardec2 => rxstbardec2,
rxstmask => rxstmask,
rxstready => rxstready,
txstready => txstready,
txcredfchipcons => txcredfchipcons,
txcredfcinfinite => txcredfcinfinite,
txcredhdrfcp => txcredhdrfcp,
txcreddatafcp => txcreddatafcp,
txcredhdrfcnp => txcredhdrfcnp,
txcreddatafcnp => txcreddatafcnp,
txcredhdrfccp => txcredhdrfccp,
txcreddatafccp => txcreddatafccp,
txstdata => txstdata,
txstparity => txstparity,
txsterr => txsterr,
txstsop => txstsop,
txsteop => txsteop,
txstempty => txstempty,
txstvalid => txstvalid,
r2cuncecc => r2cuncecc,
rxcorrecc => rxcorrecc,
retryuncecc => retryuncecc,
retrycorrecc => retrycorrecc,
rxparerr => rxparerr,
txparerr => txparerr,
r2cparerr => r2cparerr,
pmetosr => pmetosr,
pmetocr => pmetocr,
pmevent => pmevent,
pmdata => pmdata,
pmauxpwr => pmauxpwr,
tlcfgsts => tlcfgsts,
tlcfgctl => tlcfgctl,
tlcfgadd => tlcfgadd,
appintaack => appintaack,
appintasts => appintasts,
intstatus => intstatus,
appmsiack => appmsiack,
appmsireq => appmsireq,
appmsitc => appmsitc,
appmsinum => appmsinum,
aermsinum => aermsinum,
pexmsinum => pexmsinum,
hpgctrler => hpgctrler,
cfglink2csrpld => cfglink2csrpld,
cfgprmbuspld => cfgprmbuspld,
csebisshadow => csebisshadow,
csebwrdata => csebwrdata,
csebwrdataparity => csebwrdataparity,
csebbe => csebbe,
csebaddr => csebaddr,
csebaddrparity => csebaddrparity,
csebwren => csebwren,
csebrden => csebrden,
csebwrrespreq => csebwrrespreq,
csebrddata => csebrddata,
csebrddataparity => csebrddataparity,
csebwaitrequest => csebwaitrequest,
csebwrrespvalid => csebwrrespvalid,
csebwrresponse => csebwrresponse,
csebrdresponse => csebrdresponse,
dlup => dlup,
testouthip => testouthip,
testout1hip => testout1hip,
ev1us => ev1us,
ev128ns => ev128ns,
wakeoen => wakeoen,
serrout => serrout,
ltssmstate => ltssmstate,
laneact => laneact,
currentspeed => currentspeed,
slotclkcfg => slotclkcfg,
mode => mode,
testinhip => testinhip,
testin1hip => testin1hip,
cplpending => cplpending,
cplerr => cplerr,
appinterr => appinterr,
egressblkerr => egressblkerr,
pmexitd0ack => pmexitd0ack,
pmexitd0req => pmexitd0req,
currentcoeff0 => currentcoeff0,
currentcoeff1 => currentcoeff1,
currentcoeff2 => currentcoeff2,
currentcoeff3 => currentcoeff3,
currentcoeff4 => currentcoeff4,
currentcoeff5 => currentcoeff5,
currentcoeff6 => currentcoeff6,
currentcoeff7 => currentcoeff7,
currentrxpreset0 => currentrxpreset0,
currentrxpreset1 => currentrxpreset1,
currentrxpreset2 => currentrxpreset2,
currentrxpreset3 => currentrxpreset3,
currentrxpreset4 => currentrxpreset4,
currentrxpreset5 => currentrxpreset5,
currentrxpreset6 => currentrxpreset6,
currentrxpreset7 => currentrxpreset7,
rate0 => rate0,
rate1 => rate1,
rate2 => rate2,
rate3 => rate3,
rate4 => rate4,
rate5 => rate5,
rate6 => rate6,
rate7 => rate7,
ratectrl => ratectrl,
ratetiedtognd => ratetiedtognd,
eidleinfersel0 => eidleinfersel0,
eidleinfersel1 => eidleinfersel1,
eidleinfersel2 => eidleinfersel2,
eidleinfersel3 => eidleinfersel3,
eidleinfersel4 => eidleinfersel4,
eidleinfersel5 => eidleinfersel5,
eidleinfersel6 => eidleinfersel6,
eidleinfersel7 => eidleinfersel7,
txdata0 => txdata0,
txdatak0 => txdatak0,
txdetectrx0 => txdetectrx0,
txelecidle0 => txelecidle0,
txcompl0 => txcompl0,
rxpolarity0 => rxpolarity0,
powerdown0 => powerdown0,
txdataskip0 => txdataskip0,
txblkst0 => txblkst0,
txsynchd0 => txsynchd0,
txdeemph0 => txdeemph0,
txmargin0 => txmargin0,
rxdata0 => rxdata0,
rxdatak0 => rxdatak0,
rxvalid0 => rxvalid0,
phystatus0 => phystatus0,
rxelecidle0 => rxelecidle0,
rxstatus0 => rxstatus0,
rxdataskip0 => rxdataskip0,
rxblkst0 => rxblkst0,
rxsynchd0 => rxsynchd0,
rxfreqlocked0 => rxfreqlocked0,
txdata1 => txdata1,
txdatak1 => txdatak1,
txdetectrx1 => txdetectrx1,
txelecidle1 => txelecidle1,
txcompl1 => txcompl1,
rxpolarity1 => rxpolarity1,
powerdown1 => powerdown1,
txdataskip1 => txdataskip1,
txblkst1 => txblkst1,
txsynchd1 => txsynchd1,
txdeemph1 => txdeemph1,
txmargin1 => txmargin1,
rxdata1 => rxdata1,
rxdatak1 => rxdatak1,
rxvalid1 => rxvalid1,
phystatus1 => phystatus1,
rxelecidle1 => rxelecidle1,
rxstatus1 => rxstatus1,
rxdataskip1 => rxdataskip1,
rxblkst1 => rxblkst1,
rxsynchd1 => rxsynchd1,
rxfreqlocked1 => rxfreqlocked1,
txdata2 => txdata2,
txdatak2 => txdatak2,
txdetectrx2 => txdetectrx2,
txelecidle2 => txelecidle2,
txcompl2 => txcompl2,
rxpolarity2 => rxpolarity2,
powerdown2 => powerdown2,
txdataskip2 => txdataskip2,
txblkst2 => txblkst2,
txsynchd2 => txsynchd2,
txdeemph2 => txdeemph2,
txmargin2 => txmargin2,
rxdata2 => rxdata2,
rxdatak2 => rxdatak2,
rxvalid2 => rxvalid2,
phystatus2 => phystatus2,
rxelecidle2 => rxelecidle2,
rxstatus2 => rxstatus2,
rxdataskip2 => rxdataskip2,
rxblkst2 => rxblkst2,
rxsynchd2 => rxsynchd2,
rxfreqlocked2 => rxfreqlocked2,
txdata3 => txdata3,
txdatak3 => txdatak3,
txdetectrx3 => txdetectrx3,
txelecidle3 => txelecidle3,
txcompl3 => txcompl3,
rxpolarity3 => rxpolarity3,
powerdown3 => powerdown3,
txdataskip3 => txdataskip3,
txblkst3 => txblkst3,
txsynchd3 => txsynchd3,
txdeemph3 => txdeemph3,
txmargin3 => txmargin3,
rxdata3 => rxdata3,
rxdatak3 => rxdatak3,
rxvalid3 => rxvalid3,
phystatus3 => phystatus3,
rxelecidle3 => rxelecidle3,
rxstatus3 => rxstatus3,
rxdataskip3 => rxdataskip3,
rxblkst3 => rxblkst3,
rxsynchd3 => rxsynchd3,
rxfreqlocked3 => rxfreqlocked3,
txdata4 => txdata4,
txdatak4 => txdatak4,
txdetectrx4 => txdetectrx4,
txelecidle4 => txelecidle4,
txcompl4 => txcompl4,
rxpolarity4 => rxpolarity4,
powerdown4 => powerdown4,
txdataskip4 => txdataskip4,
txblkst4 => txblkst4,
txsynchd4 => txsynchd4,
txdeemph4 => txdeemph4,
txmargin4 => txmargin4,
rxdata4 => rxdata4,
rxdatak4 => rxdatak4,
rxvalid4 => rxvalid4,
phystatus4 => phystatus4,
rxelecidle4 => rxelecidle4,
rxstatus4 => rxstatus4,
rxdataskip4 => rxdataskip4,
rxblkst4 => rxblkst4,
rxsynchd4 => rxsynchd4,
rxfreqlocked4 => rxfreqlocked4,
txdata5 => txdata5,
txdatak5 => txdatak5,
txdetectrx5 => txdetectrx5,
txelecidle5 => txelecidle5,
txcompl5 => txcompl5,
rxpolarity5 => rxpolarity5,
powerdown5 => powerdown5,
txdataskip5 => txdataskip5,
txblkst5 => txblkst5,
txsynchd5 => txsynchd5,
txdeemph5 => txdeemph5,
txmargin5 => txmargin5,
rxdata5 => rxdata5,
rxdatak5 => rxdatak5,
rxvalid5 => rxvalid5,
phystatus5 => phystatus5,
rxelecidle5 => rxelecidle5,
rxstatus5 => rxstatus5,
rxdataskip5 => rxdataskip5,
rxblkst5 => rxblkst5,
rxsynchd5 => rxsynchd5,
rxfreqlocked5 => rxfreqlocked5,
txdata6 => txdata6,
txdatak6 => txdatak6,
txdetectrx6 => txdetectrx6,
txelecidle6 => txelecidle6,
txcompl6 => txcompl6,
rxpolarity6 => rxpolarity6,
powerdown6 => powerdown6,
txdataskip6 => txdataskip6,
txblkst6 => txblkst6,
txsynchd6 => txsynchd6,
txdeemph6 => txdeemph6,
txmargin6 => txmargin6,
rxdata6 => rxdata6,
rxdatak6 => rxdatak6,
rxvalid6 => rxvalid6,
phystatus6 => phystatus6,
rxelecidle6 => rxelecidle6,
rxstatus6 => rxstatus6,
rxdataskip6 => rxdataskip6,
rxblkst6 => rxblkst6,
rxsynchd6 => rxsynchd6,
rxfreqlocked6 => rxfreqlocked6,
txdata7 => txdata7,
txdatak7 => txdatak7,
txdetectrx7 => txdetectrx7,
txelecidle7 => txelecidle7,
txcompl7 => txcompl7,
rxpolarity7 => rxpolarity7,
powerdown7 => powerdown7,
txdataskip7 => txdataskip7,
txblkst7 => txblkst7,
txsynchd7 => txsynchd7,
txdeemph7 => txdeemph7,
txmargin7 => txmargin7,
rxdata7 => rxdata7,
rxdatak7 => rxdatak7,
rxvalid7 => rxvalid7,
phystatus7 => phystatus7,
rxelecidle7 => rxelecidle7,
rxstatus7 => rxstatus7,
rxdataskip7 => rxdataskip7,
rxblkst7 => rxblkst7,
rxsynchd7 => rxsynchd7,
rxfreqlocked7 => rxfreqlocked7,
dbgpipex1rx => dbgpipex1rx,
memredsclk => memredsclk,
memredenscan => memredenscan,
memredscen => memredscen,
memredscin => memredscin,
memredscsel => memredscsel,
memredscrst => memredscrst,
memredscout => memredscout,
memregscanen => memregscanen,
memregscanin => memregscanin,
memhiptestenable => memhiptestenable,
memregscanout => memregscanout,
bisttesten => bisttesten,
bistenrpl => bistenrpl,
bistscanin => bistscanin,
bistscanen => bistscanen,
bistenrcv => bistenrcv,
bistscanoutrpl => bistscanoutrpl,
bistdonearpl => bistdonearpl,
bistdonebrpl => bistdonebrpl,
bistpassrpl => bistpassrpl,
derrrpl => derrrpl,
derrcorextrpl => derrcorextrpl,
bistscanoutrcv => bistscanoutrcv,
bistdonearcv => bistdonearcv,
bistdonebrcv => bistdonebrcv,
bistpassrcv => bistpassrcv,
derrcorextrcv => derrcorextrcv,
bistscanoutrcv1 => bistscanoutrcv1,
bistdonearcv1 => bistdonearcv1,
bistdonebrcv1 => bistdonebrcv1,
bistpassrcv1 => bistpassrcv1,
derrcorextrcv1 => derrcorextrcv1,
scanmoden => scanmoden,
scanshiftn => scanshiftn,
nfrzdrv => nfrzdrv,
frzreg => frzreg,
frzlogic => frzlogic,
idrpl => idrpl,
idrcv => idrcv,
plniotri => plniotri,
entest => entest,
npor => npor,
usermode => usermode,
cvpclk => cvpclk,
cvpdata => cvpdata,
cvpstartxfer => cvpstartxfer,
cvpconfig => cvpconfig,
cvpfullconfig => cvpfullconfig,
cvpconfigready => cvpconfigready,
cvpen => cvpen,
cvpconfigerror => cvpconfigerror,
cvpconfigdone => cvpconfigdone,
pinperstn => pinperstn,
pldperstn => pldperstn,
iocsrrdydly => iocsrrdydly,
softaltpe3rstn => softaltpe3rstn,
softaltpe3srstn => softaltpe3srstn,
softaltpe3crstn => softaltpe3crstn,
pldclrpmapcshipn => pldclrpmapcshipn,
pldclrpcshipn => pldclrpcshipn,
pldclrhipn => pldclrhipn,
s0ch0emsiptieoff => s0ch0emsiptieoff,
s0ch1emsiptieoff => s0ch1emsiptieoff,
s0ch2emsiptieoff => s0ch2emsiptieoff,
s1ch0emsiptieoff => s1ch0emsiptieoff,
s1ch1emsiptieoff => s1ch1emsiptieoff,
s1ch2emsiptieoff => s1ch2emsiptieoff,
s2ch0emsiptieoff => s2ch0emsiptieoff,
s2ch1emsiptieoff => s2ch1emsiptieoff,
s2ch2emsiptieoff => s2ch2emsiptieoff,
s3ch0emsiptieoff => s3ch0emsiptieoff,
s3ch1emsiptieoff => s3ch1emsiptieoff,
s3ch2emsiptieoff => s3ch2emsiptieoff,
emsiptieofftop => emsiptieofftop,
emsiptieoffbot => emsiptieoffbot,
txpcsrstn0 => txpcsrstn0 ,
rxpcsrstn0 => rxpcsrstn0 ,
g3txpcsrstn0 => g3txpcsrstn0 ,
g3rxpcsrstn0 => g3rxpcsrstn0 ,
txpmasyncp0 => txpmasyncp0 ,
rxpmarstb0 => rxpmarstb0 ,
txlcpllrstb0 => txlcpllrstb0 ,
offcalen0 => offcalen0 ,
frefclk0 => frefclk0 ,
offcaldone0 => offcaldone0 ,
txlcplllock0 => txlcplllock0 ,
rxfreqtxcmuplllock0 => rxfreqtxcmuplllock0 ,
rxpllphaselock0 => rxpllphaselock0 ,
masktxplllock0 => masktxplllock0 ,
txpcsrstn1 => txpcsrstn1 ,
rxpcsrstn1 => rxpcsrstn1 ,
g3txpcsrstn1 => g3txpcsrstn1 ,
g3rxpcsrstn1 => g3rxpcsrstn1 ,
txpmasyncp1 => txpmasyncp1 ,
rxpmarstb1 => rxpmarstb1 ,
txlcpllrstb1 => txlcpllrstb1 ,
offcalen1 => offcalen1 ,
frefclk1 => frefclk1 ,
offcaldone1 => offcaldone1 ,
txlcplllock1 => txlcplllock1 ,
rxfreqtxcmuplllock1 => rxfreqtxcmuplllock1 ,
rxpllphaselock1 => rxpllphaselock1 ,
masktxplllock1 => masktxplllock1 ,
txpcsrstn2 => txpcsrstn2 ,
rxpcsrstn2 => rxpcsrstn2 ,
g3txpcsrstn2 => g3txpcsrstn2 ,
g3rxpcsrstn2 => g3rxpcsrstn2 ,
txpmasyncp2 => txpmasyncp2 ,
rxpmarstb2 => rxpmarstb2 ,
txlcpllrstb2 => txlcpllrstb2 ,
offcalen2 => offcalen2 ,
frefclk2 => frefclk2 ,
offcaldone2 => offcaldone2 ,
txlcplllock2 => txlcplllock2 ,
rxfreqtxcmuplllock2 => rxfreqtxcmuplllock2 ,
rxpllphaselock2 => rxpllphaselock2 ,
masktxplllock2 => masktxplllock2 ,
txpcsrstn3 => txpcsrstn3 ,
rxpcsrstn3 => rxpcsrstn3 ,
g3txpcsrstn3 => g3txpcsrstn3 ,
g3rxpcsrstn3 => g3rxpcsrstn3 ,
txpmasyncp3 => txpmasyncp3 ,
rxpmarstb3 => rxpmarstb3 ,
txlcpllrstb3 => txlcpllrstb3 ,
offcalen3 => offcalen3 ,
frefclk3 => frefclk3 ,
offcaldone3 => offcaldone3 ,
txlcplllock3 => txlcplllock3 ,
rxfreqtxcmuplllock3 => rxfreqtxcmuplllock3 ,
rxpllphaselock3 => rxpllphaselock3 ,
masktxplllock3 => masktxplllock3 ,
txpcsrstn4 => txpcsrstn4 ,
rxpcsrstn4 => rxpcsrstn4 ,
g3txpcsrstn4 => g3txpcsrstn4 ,
g3rxpcsrstn4 => g3rxpcsrstn4 ,
txpmasyncp4 => txpmasyncp4 ,
rxpmarstb4 => rxpmarstb4 ,
txlcpllrstb4 => txlcpllrstb4 ,
offcalen4 => offcalen4 ,
frefclk4 => frefclk4 ,
offcaldone4 => offcaldone4 ,
txlcplllock4 => txlcplllock4 ,
rxfreqtxcmuplllock4 => rxfreqtxcmuplllock4 ,
rxpllphaselock4 => rxpllphaselock4 ,
masktxplllock4 => masktxplllock4 ,
txpcsrstn5 => txpcsrstn5 ,
rxpcsrstn5 => rxpcsrstn5 ,
g3txpcsrstn5 => g3txpcsrstn5 ,
g3rxpcsrstn5 => g3rxpcsrstn5 ,
txpmasyncp5 => txpmasyncp5 ,
rxpmarstb5 => rxpmarstb5 ,
txlcpllrstb5 => txlcpllrstb5 ,
offcalen5 => offcalen5 ,
frefclk5 => frefclk5 ,
offcaldone5 => offcaldone5 ,
txlcplllock5 => txlcplllock5 ,
rxfreqtxcmuplllock5 => rxfreqtxcmuplllock5 ,
rxpllphaselock5 => rxpllphaselock5 ,
masktxplllock5 => masktxplllock5 ,
txpcsrstn6 => txpcsrstn6 ,
rxpcsrstn6 => rxpcsrstn6 ,
g3txpcsrstn6 => g3txpcsrstn6 ,
g3rxpcsrstn6 => g3rxpcsrstn6 ,
txpmasyncp6 => txpmasyncp6 ,
rxpmarstb6 => rxpmarstb6 ,
txlcpllrstb6 => txlcpllrstb6 ,
offcalen6 => offcalen6 ,
frefclk6 => frefclk6 ,
offcaldone6 => offcaldone6 ,
txlcplllock6 => txlcplllock6 ,
rxfreqtxcmuplllock6 => rxfreqtxcmuplllock6 ,
rxpllphaselock6 => rxpllphaselock6 ,
masktxplllock6 => masktxplllock6 ,
txpcsrstn7 => txpcsrstn7 ,
rxpcsrstn7 => rxpcsrstn7 ,
g3txpcsrstn7 => g3txpcsrstn7 ,
g3rxpcsrstn7 => g3rxpcsrstn7 ,
txpmasyncp7 => txpmasyncp7 ,
rxpmarstb7 => rxpmarstb7 ,
txlcpllrstb7 => txlcpllrstb7 ,
offcalen7 => offcalen7 ,
frefclk7 => frefclk7 ,
offcaldone7 => offcaldone7 ,
txlcplllock7 => txlcplllock7 ,
rxfreqtxcmuplllock7 => rxfreqtxcmuplllock7 ,
rxpllphaselock7 => rxpllphaselock7 ,
masktxplllock7 => masktxplllock7 ,
txpcsrstn8 => txpcsrstn8 ,
rxpcsrstn8 => rxpcsrstn8 ,
g3txpcsrstn8 => g3txpcsrstn8 ,
g3rxpcsrstn8 => g3rxpcsrstn8 ,
txpmasyncp8 => txpmasyncp8 ,
rxpmarstb8 => rxpmarstb8 ,
txlcpllrstb8 => txlcpllrstb8 ,
offcalen8 => offcalen8 ,
frefclk8 => frefclk8 ,
offcaldone8 => offcaldone8 ,
txlcplllock8 => txlcplllock8 ,
rxfreqtxcmuplllock8 => rxfreqtxcmuplllock8 ,
rxpllphaselock8 => rxpllphaselock8 ,
masktxplllock8 => masktxplllock8 ,
txpcsrstn9 => txpcsrstn9 ,
rxpcsrstn9 => rxpcsrstn9 ,
g3txpcsrstn9 => g3txpcsrstn9 ,
g3rxpcsrstn9 => g3rxpcsrstn9 ,
txpmasyncp9 => txpmasyncp9 ,
rxpmarstb9 => rxpmarstb9 ,
txlcpllrstb9 => txlcpllrstb9 ,
offcalen9 => offcalen9 ,
frefclk9 => frefclk9 ,
offcaldone9 => offcaldone9 ,
txlcplllock9 => txlcplllock9 ,
rxfreqtxcmuplllock9 => rxfreqtxcmuplllock9 ,
rxpllphaselock9 => rxpllphaselock9 ,
masktxplllock9 => masktxplllock9 ,
txpcsrstn10 => txpcsrstn10 ,
rxpcsrstn10 => rxpcsrstn10 ,
g3txpcsrstn10 => g3txpcsrstn10 ,
g3rxpcsrstn10 => g3rxpcsrstn10 ,
txpmasyncp10 => txpmasyncp10 ,
rxpmarstb10 => rxpmarstb10 ,
txlcpllrstb10 => txlcpllrstb10 ,
offcalen10 => offcalen10 ,
frefclk10 => frefclk10 ,
offcaldone10 => offcaldone10 ,
txlcplllock10 => txlcplllock10 ,
rxfreqtxcmuplllock10 => rxfreqtxcmuplllock10 ,
rxpllphaselock10 => rxpllphaselock10 ,
masktxplllock10 => masktxplllock10 ,
txpcsrstn11 => txpcsrstn11 ,
rxpcsrstn11 => rxpcsrstn11 ,
g3txpcsrstn11 => g3txpcsrstn11 ,
g3rxpcsrstn11 => g3rxpcsrstn11 ,
txpmasyncp11 => txpmasyncp11 ,
rxpmarstb11 => rxpmarstb11 ,
txlcpllrstb11 => txlcpllrstb11 ,
offcalen11 => offcalen11 ,
frefclk11 => frefclk11 ,
offcaldone11 => offcaldone11 ,
txlcplllock11 => txlcplllock11 ,
rxfreqtxcmuplllock11 => rxfreqtxcmuplllock11 ,
rxpllphaselock11 => rxpllphaselock11 ,
masktxplllock11 => masktxplllock11 ,
reservedin => reservedin,
reservedclkin => reservedclkin,
reservedout => reservedout,
reservedclkout => reservedclkout
);
end behavior;
| gpl-3.0 | b72909d2bad78d054cdea015844b40ea | 0.524131 | 3.244147 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_io_g.vhd | 1 | 5,902 | -------------------------------------------------------------------------------
--
-- The G port controller.
--
-- $Id: t400_io_g.vhd,v 1.3 2006-06-05 20:32:34 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_io_g is
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in io_g_op_t;
m_i : in dw_t;
dec_data_i : in dec_data_t;
cs_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port G Interface -------------------------------------------------------
io_g_o : out dw_t;
io_g_en_o : out dw_t
);
end t400_io_g;
use work.t400_io_pack.all;
architecture rtl of t400_io_g is
signal g_q : dw_t;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Process g_reg
--
-- Purpose:
-- Implements the G output register.
--
g_reg: process (ck_i, por_i)
begin
if por_i then
g_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
g_q <= (others => '0');
elsif ck_en_i then
case op_i is
when IOG_LOAD_M =>
g_q <= m_i;
when IOG_LOAD_DEC =>
g_q <= dec_data_i(dw_range_t);
when others =>
null;
end case;
end if;
-- reset G(0) in MICROBUS operation upon write
if opt_microbus_g = t400_opt_microbus_c and
cs_n_i = '0' and wr_n_i = '0' then
g_q(0) <= '0';
end if;
end if;
end process g_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process out_driver
--
-- Purpose:
-- Implements the output driver data and enable.
--
out_driver: process (g_q,
vdd_s)
begin
-- bit 3
io_g_o(3) <= io_out_f(dat => g_q(3),
opt => opt_out_type_3_g);
io_g_en_o(3) <= io_en_f (en => vdd_s, dat => g_q(3),
opt => opt_out_type_3_g);
-- bit 2
io_g_o(2) <= io_out_f(dat => g_q(2),
opt => opt_out_type_2_g);
io_g_en_o(2) <= io_en_f (en => vdd_s, dat => g_q(2),
opt => opt_out_type_2_g);
-- bit 1
io_g_o(1) <= io_out_f(dat => g_q(1),
opt => opt_out_type_1_g);
io_g_en_o(1) <= io_en_f (en => vdd_s, dat => g_q(1),
opt => opt_out_type_1_g);
-- bit 0
io_g_o(0) <= io_out_f(dat => g_q(0),
opt => opt_out_type_0_g);
io_g_en_o(0) <= io_en_f (en => vdd_s, dat => g_q(0),
opt => opt_out_type_0_g);
end process out_driver;
--
-----------------------------------------------------------------------------
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/07 02:24:16 arniml
-- fix sensitivity list
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 0a31f5a6504defe880ad23855f0543cb | 0.504914 | 3.638718 | false | false | false | false |
keith-epidev/md2x | build/code/lcd.vhdl | 1 | 2,056 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.my_lib.all;
entity lcd is
port(
clk: in std_logic;
reset: in std_logic;
rs: out std_logic;
rw: out std_logic;
e: out std_logic;
data: out std_logic_vector(7 downto 0);
disp: in disp_chars
);
end lcd;
architecture Behavioral of lcd is
component pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end component;
signal lcd_clk : std_logic;
signal state : std_logic_vector(f_log2(8)-1 downto 0);
--signal index : std_logic_vector(f_log2(16*2)-1 downto 0) := (others=>'0');
type cmd_list is array(0 to 7) of std_logic_vector(7 downto 0);
signal init_data :cmd_list := ( X"30", X"30", X"30", X"38", X"0C", X"01", X"06",X"01");
signal e_state: std_logic := '0';
signal align: std_logic := '0';
begin
p1: pulser generic map(delay=>50000) port map(clk, '1', lcd_clk);
e <= e_state;
process(lcd_clk,reset)
variable index : integer := 0;
begin
if(reset = '1')then
index:= 0;
state <= (others=>'0');
elsif(lcd_clk'event and lcd_clk = '1')then
if(e_state = '1')then
e_state <= '0';
if(state < 8) then
data <= init_data(conv_integer(state));
rs <= '0';
rw <= '0';
state <= state+1;
else
if( align = '0' and (index = 0 or index = 16 ) )then
rs <= '0';
rw <= '0';
align <= '1';
if(index = 0)then
data <=X"80";
else
data <= X"C0";
end if;
else
if( disp(index) = "00000000" )then
data <= X"20";
else
data <= disp(index);
end if;
index := index+1;
align <= '0';
rs <= '1';
rw <= '0';
if(index = 16*2)then
index := 0;
end if;
end if;
end if;
else
e_state <= not e_state;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | f628d9f4646a52d6c7e8edfbfc70df49 | 0.537451 | 2.659767 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/altera_primitives.vhd | 1 | 51,896 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
Library ieee;
use ieee.std_logic_1164.all;
entity GLOBAL is
port(
a_in : in std_logic;
a_out : out std_logic);
end GLOBAL;
architecture BEHAVIOR of GLOBAL is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity CARRY is
port(
a_in : in std_logic;
a_out : out std_logic);
end CARRY;
architecture BEHAVIOR of CARRY is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity CASCADE is
port(
a_in : in std_logic;
a_out : out std_logic);
end CASCADE;
architecture BEHAVIOR of CASCADE is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity CARRY_SUM is
port(
sin : in std_logic;
cin : in std_logic;
sout : out std_logic;
cout : out std_logic);
end CARRY_SUM;
architecture BEHAVIOR of CARRY_SUM is
begin
sout <= sin;
cout <= cin;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity EXP is
port(
a_in : in std_logic;
a_out : out std_logic);
end EXP;
architecture BEHAVIOR of EXP is
begin
a_out <= not a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity SOFT is
port(
a_in : in std_logic;
a_out : out std_logic);
end SOFT;
architecture BEHAVIOR of SOFT is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity OPNDRN is
port(
a_in : in std_logic;
a_out : out std_logic);
end OPNDRN;
architecture BEHAVIOR of OPNDRN is
begin
process (a_in)
begin
if (a_in = '0') then
a_out <= '0';
elsif (a_in = '1') then
a_out <= 'Z';
else
a_out <= 'X';
end if;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity ROW_GLOBAL is
port(
a_in : in std_logic;
a_out : out std_logic);
end ROW_GLOBAL;
architecture BEHAVIOR of ROW_GLOBAL is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity TRI is
port(
a_in : in std_logic;
oe : in std_logic;
a_out : out std_logic);
end TRI;
architecture BEHAVIOR of TRI is
begin
a_out <= a_in when oe = '1'
else 'Z';
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity LUT_INPUT is
port(
a_in : in std_logic;
a_out : out std_logic);
end LUT_INPUT;
architecture BEHAVIOR of LUT_INPUT is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity LUT_OUTPUT is
port(
a_in : in std_logic;
a_out : out std_logic);
end LUT_OUTPUT;
architecture BEHAVIOR of LUT_OUTPUT is
begin
a_out <= a_in;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity latch is
port(
d : in std_logic;
ena : in std_logic;
q : out std_logic);
end latch;
architecture BEHAVIOR of latch is
signal iq : std_logic := '0';
begin
process (d, ena)
begin
if (ena = '1') then
iq <= d;
end if;
end process;
q <= iq;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port(
d : in std_logic;
ena : in std_logic;
clrn : in std_logic;
prn : in std_logic;
q : out std_logic);
end dlatch;
architecture BEHAVIOR of dlatch is
signal iq : std_logic := '0';
begin
process (d, ena, clrn, prn)
begin
if (clrn = '0') then
iq <= '0';
elsif (prn = '0') then
iq <= '1';
elsif (ena = '1') then
iq <= d;
end if;
end process;
q <= iq;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GDFF is
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end PRIM_GDFF;
architecture BEHAVIOR of PRIM_GDFF is
signal iq : std_logic := '0';
signal init : std_logic := '0';
signal stalled_adata : std_logic := '0';
begin
process (clk, clr, pre, ald, stalled_adata)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (ald = '1') then
iq <= stalled_adata;
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if (sclr = '1') then
iq <= '0';
elsif (sload = '1') then
iq <= stalled_adata;
else
iq <= d;
end if;
end if;
end if;
end process;
process (adt, init)
begin
if (init = '0') then
stalled_adata <= adt;
init <= '1';
else
stalled_adata <= adt after 1 ps;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GDFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GDFF;
entity DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end DFF;
architecture BEHAVIOR of DFF is
component PRIM_GDFF
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal zero_bit : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GDFF_INST : PRIM_GDFF
port map (
d => d,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
ald => zero_bit,
adt => zero_bit,
sclr => zero_bit,
sload => zero_bit,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- DFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GDFF;
entity DFFE is
port(
d, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end DFFE;
architecture BEHAVIOR of DFFE is
component PRIM_GDFF
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal zero_bit : std_logic := '0';
begin
PRIM_GDFF_INST : PRIM_GDFF
port map (
d => d,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
ald => zero_bit,
adt => zero_bit,
sclr => zero_bit,
sload => zero_bit,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- DFFE
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GDFF;
entity DFFEA is
port(
d, clk, ena, clrn, prn, aload, adata : in std_logic;
q : out std_logic);
end DFFEA;
architecture BEHAVIOR of DFFEA is
component PRIM_GDFF
port(
d, clk, ena, clr, pre, ald, adt, sclr, sload : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal zero_bit : std_logic := '0';
begin
PRIM_GDFF_INST : PRIM_GDFF
port map (
d => d,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
ald => aload,
adt => adata,
sclr => zero_bit,
sload => zero_bit,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- DFFEA
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.dffeas_pack.all;
entity DFFEAS is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of dffeas : entity is TRUE;
end DFFEAS;
architecture vital_dffeas of dffeas is
attribute VITAL_LEVEL0 of vital_dffeas : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFEAS",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_dffeas;
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GTFF is
port(
t, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end PRIM_GTFF;
architecture BEHAVIOR of PRIM_GTFF is
signal iq : std_logic := '0';
signal init : std_logic := '0';
begin
process (clk, clr, pre)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if (t = '1') then
iq <= not iq;
end if;
end if;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GTFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GTFF;
entity TFF is
port(
t, clk, clrn, prn : in std_logic;
q : out std_logic);
end TFF;
architecture BEHAVIOR of TFF is
component PRIM_GTFF
port(
t, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GTFF_INST : PRIM_GTFF
port map (
t => t,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- TFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GTFF;
entity TFFE is
port(
t, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end TFFE;
architecture BEHAVIOR of TFFE is
component PRIM_GTFF
port(
t, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
begin
PRIM_GTFF_INST : PRIM_GTFF
port map (
t => t,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- TFFE
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GJKFF is
port(
j, k, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end PRIM_GJKFF;
architecture BEHAVIOR of PRIM_GJKFF is
signal iq : std_logic := '0';
begin
process (clk, clr, pre)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if ((j = '1') and (k = '0')) then
iq <= '1';
elsif ((j = '0') and (k = '1')) then
iq <= '0';
elsif ((j = '1') and (k = '1')) then
iq <= not iq;
end if;
end if;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GJKFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GJKFF;
entity JKFF is
port(
j, k, clk, clrn, prn : in std_logic;
q : out std_logic);
end JKFF;
architecture BEHAVIOR of JKFF is
component PRIM_GJKFF
port(
j, k, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GJKFF_INST : PRIM_GJKFF
port map (
j => j,
k => k,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- JKFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GJKFF;
entity JKFFE is
port(
j, k, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end JKFFE;
architecture BEHAVIOR of JKFFE is
component PRIM_GJKFF
port(
j, k, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
begin
PRIM_GJKFF_INST : PRIM_GJKFF
port map (
j => j,
k => k,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- JKFFE
Library ieee;
use ieee.std_logic_1164.all;
entity PRIM_GSRFF is
port(
s, r, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end PRIM_GSRFF;
architecture BEHAVIOR of PRIM_GSRFF is
signal iq : std_logic := '0';
begin
process (clk, clr, pre)
begin
if (clr = '1') then
iq <= '0';
elsif (pre = '1') then
iq <= '1';
elsif (clk'event and (clk = '1') and (clk'last_value = '0')) then
if (ena = '1') then
if ((s = '1') and (r = '0')) then
iq <= '1';
elsif ((s = '0') and (r = '1')) then
iq <= '0';
elsif ((s = '1') and (r = '1')) then
iq <= not iq;
end if;
end if;
end if;
end process;
q <= iq;
end BEHAVIOR; -- PRIM_GSRFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GSRFF;
entity SRFF is
port(
s, r, clk, clrn, prn : in std_logic;
q : out std_logic);
end SRFF;
architecture BEHAVIOR of SRFF is
component PRIM_GSRFF
port(
s, r, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
signal one_bit : std_logic := '1';
begin
PRIM_GSRFF_INST : PRIM_GSRFF
port map (
s => s,
r => r,
clk => clk,
ena => one_bit,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- SRFF
Library ieee;
use ieee.std_logic_1164.all;
use work.PRIM_GSRFF;
entity SRFFE is
port(
s, r, clk, ena, clrn, prn : in std_logic;
q : out std_logic);
end SRFFE;
architecture BEHAVIOR of SRFFE is
component PRIM_GSRFF
port(
s, r, clk, ena, clr, pre : in std_logic;
q : out std_logic);
end component;
signal clear : std_logic := '0';
signal preset : std_logic := '0';
begin
PRIM_GSRFF_INST : PRIM_GSRFF
port map (
s => s,
r => r,
clk => clk,
ena => ena,
clr => clear,
pre => preset,
q => q );
clear <= not clrn;
preset <= not prn;
end BEHAVIOR; -- SRFFE
library ieee;
use ieee.std_logic_1164.all;
-- ENTITY DECLARATION
entity clklock is
generic(
input_frequency : natural := 10000; -- units in ps
clockboost : natural := 1
);
port(
inclk : in std_logic; -- required port, input reference clock
outclk : out std_logic -- outclk output
);
end clklock;
-- END ENTITY DECLARATION
-- BEGINNING OF ARCHITECTURE BEHAVIOR
architecture behavior of clklock is
-- CONSTANT DECLARATION
constant valid_lock_cycles : natural := 1;
constant invalid_lock_cycles : natural := 2;
-- SIGNAL DECLARATION
SIGNAL pll_lock : std_logic := '0';
SIGNAL check_lock : std_logic := '0';
SIGNAL outclk_tmp : std_logic := 'X';
begin
-- checking for invalid parameters
MSG: process
begin
if (input_frequency <= 0) then
ASSERT FALSE
REPORT "The period of the input clock (input_frequency) must be greater than 0!"
SEVERITY ERROR;
end if;
if ((clockboost /= 1) and (clockboost /= 2)) then
ASSERT FALSE
REPORT "The clock multiplication factor (clockboost) must be a value of 1 or 2!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
LOCK: process(inclk, pll_lock, check_lock)
-- VARIABLE DECLARATION
variable inclk_ps : time := 0 ps;
variable violation : boolean := false;
variable pll_lock_tmp : std_logic := '0';
variable start_lock_count, stop_lock_count : integer := 0;
variable pll_last_rising_edge, pll_last_falling_edge : time := 0 ps;
variable pll_rising_edge_count : integer := 0;
variable pll_cycle, pll_duty_cycle : time := 0 ps;
variable expected_next_clk_edge : time := 0 ps;
variable clk_per_tolerance : time := 0 ps;
variable last_synchronizing_rising_edge_for_outclk : time := 0 ps;
variable input_cycles_per_outclk : integer := 1;
variable input_cycle_count_to_sync0 : integer := 0;
variable init : boolean := true;
variable output_value : std_logic := '0';
variable vco_per : time := 0 ps;
variable high_time : time := 0 ps;
variable low_time : time := 0 ps;
variable sched_time : time := 0 ps;
variable tmp_per : integer := 0;
variable temp, tmp_rem, my_rem : integer := 0;
variable inc : integer := 1;
variable cycle_to_adjust : integer := 0;
variable outclk_synchronizing_period : time;
variable outclk_cycles_per_sync_period : integer := clockboost;
variable schedule_outclk : boolean := false;
begin
if (init) then
outclk_cycles_per_sync_period := clockboost;
input_cycles_per_outclk := 1;
clk_per_tolerance := (0.1 * real(input_frequency)) * 1 ps;
init := false;
end if;
if (inclk'event and inclk = '1') then
if (pll_lock_tmp = '1') then
check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0;
end if;
if pll_rising_edge_count = 0 then -- at 1st rising edge
inclk_ps := (input_frequency / 1) * 1 ps;
pll_duty_cycle := inclk_ps/2;
elsif pll_rising_edge_count = 1 then -- at 2nd rising edge
pll_cycle := now - pll_last_rising_edge; -- calculate period
if ((NOW - pll_last_rising_edge) < (inclk_ps - clk_per_tolerance) or
(NOW - pll_last_rising_edge) > (inclk_ps + clk_per_tolerance)) then
ASSERT FALSE
REPORT "Inclock_Period Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
end if;
else
start_lock_count := 1;
end if;
else
violation := false;
end if;
if ((now - pll_last_falling_edge) < (pll_duty_cycle - clk_per_tolerance/2) or
(now - pll_last_falling_edge) > (pll_duty_cycle + clk_per_tolerance/2)) then
ASSERT FALSE
REPORT "Duty Cycle Violation"
SEVERITY WARNING;
violation := true;
else
violation := false;
end if;
else
pll_cycle := now - pll_last_rising_edge; -- calculate period
if ((now - pll_last_rising_edge) < (inclk_ps - clk_per_tolerance) or
(now - pll_last_rising_edge) > (inclk_ps + clk_per_tolerance)) then
ASSERT FALSE
REPORT "Cycle Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
end if;
else
start_lock_count := 1;
end if;
else
violation := false;
end if;
end if;
pll_last_rising_edge := now;
pll_rising_edge_count := pll_rising_edge_count +1;
if (not violation) then
if (pll_lock_tmp = '1') then
input_cycle_count_to_sync0 := input_cycle_count_to_sync0 + 1;
if (input_cycle_count_to_sync0 = input_cycles_per_outclk) then
outclk_synchronizing_period := now - last_synchronizing_rising_edge_for_outclk;
last_synchronizing_rising_edge_for_outclk := now;
schedule_outclk := true;
input_cycle_count_to_sync0 := 0;
end if;
else
start_lock_count := start_lock_count + 1;
if (start_lock_count >= valid_lock_cycles) then
pll_lock_tmp := '1';
input_cycle_count_to_sync0 := 0;
outclk_synchronizing_period := ((pll_cycle/1 ps) * input_cycles_per_outclk) * 1 ps;
last_synchronizing_rising_edge_for_outclk := now;
schedule_outclk := true;
end if;
end if;
else
start_lock_count := 1;
end if;
elsif (inclk'event and inclk= '0') then
if (pll_lock_tmp = '1') then
check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0;
if (now > 0 ns and ((now - pll_last_rising_edge) < (pll_duty_cycle - clk_per_tolerance/2) or
(now - pll_last_rising_edge) > (pll_duty_cycle + clk_per_tolerance/2))) then
ASSERT FALSE
REPORT "Duty Cycle Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
end if;
end if;
else
violation := false;
end if;
else
start_lock_count := start_lock_count + 1;
end if;
pll_last_falling_edge := now;
else
if pll_lock_tmp = '1' then
if (inclk = '1') then
expected_next_clk_edge := pll_last_rising_edge + (inclk_ps+clk_per_tolerance)/2.0;
else
expected_next_clk_edge := pll_last_falling_edge + (inclk_ps+clk_per_tolerance)/2.0;
end if;
violation := false;
if (now < expected_next_clk_edge) then
check_lock <= not check_lock after (expected_next_clk_edge - now);
elsif (now = expected_next_clk_edge) then
check_lock <= not check_lock after (inclk_ps+clk_per_tolerance)/2.0;
else
ASSERT FALSE
REPORT "Inclock_Period Violation"
SEVERITY WARNING;
violation := true;
if (pll_lock = '1') then
stop_lock_count := stop_lock_count + 1;
if (stop_lock_count = invalid_lock_cycles) then
pll_lock_tmp := '0';
ASSERT FALSE
REPORT "clklock out of lock."
SEVERITY WARNING;
else
check_lock <= not check_lock after (inclk_ps/2.0);
end if;
end if;
end if;
end if;
end if;
pll_lock <= pll_lock_tmp;
if (pll_lock'event and pll_lock = '0') then
start_lock_count := 1;
stop_lock_count := 0;
outclk_tmp <= 'X';
end if;
-- outclk output
if (schedule_outclk = true) then
-- initialize variables
sched_time := 0 ps;
cycle_to_adjust := 0;
inc := 1;
output_value := '1';
temp := outclk_synchronizing_period / 1 ps;
my_rem := temp rem outclk_cycles_per_sync_period;
-- schedule <outclk_cycles_per_sync_period> number of output clock
-- cycles in this loop in order to synchronize the output clock to the
-- input clock - to get rid of drifting for cases where the input clock
-- period is not always divisible
for i in 1 to outclk_cycles_per_sync_period loop
tmp_per := temp/outclk_cycles_per_sync_period;
if ((my_rem /= 0) and (inc <= my_rem)) then
tmp_rem := (outclk_cycles_per_sync_period * inc) rem my_rem;
cycle_to_adjust := (outclk_cycles_per_sync_period * inc) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
-- if this cycle is the one to adjust the output period in, then
-- increment the period by 1 unit
if (cycle_to_adjust = i) then
tmp_per := tmp_per + 1;
inc := inc + 1;
end if;
-- adjust the high and low cycle period
vco_per := tmp_per * 1 ps;
high_time := (tmp_per / 2) * 1 ps;
if ((tmp_per rem 2) /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the high and low cycle of 1 output clock period
for j in 1 to 2 loop
outclk_tmp <= transport output_value after sched_time;
output_value := not output_value;
if (output_value = '0') then
sched_time := sched_time + high_time;
elsif (output_value = '1') then
sched_time := sched_time + low_time;
end if;
end loop;
end loop;
-- reset schedule_outclk
schedule_outclk := false;
end if; -- schedule_outclk
end process LOCK;
outclk <= outclk_tmp;
end behavior;
-- END ARCHITECTURE BEHAVIOR
Library ieee;
use ieee.std_logic_1164.all;
entity alt_inbuf is
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf" );
port(
i : in std_logic;
o : out std_logic);
end alt_inbuf;
architecture BEHAVIOR of alt_inbuf is
begin
o <= i;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf" );
port(
i : in std_logic;
o : out std_logic);
end alt_outbuf;
architecture BEHAVIOR of alt_outbuf is
begin
o <= i;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf_tri is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic);
end alt_outbuf_tri;
architecture BEHAVIOR of alt_outbuf_tri is
begin
o <= i when oe = '1'
else 'Z';
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_iobuf is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
slow_slew_rate : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
o : out std_logic);
end alt_iobuf;
architecture BEHAVIOR of alt_iobuf is
begin
process(i, io, oe)
begin
if oe = '1' then
io <= i;
else
io <= 'Z';
end if;
o <= io;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_inbuf_diff is
generic(
io_standard : string := "NONE";
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_inbuf_diff" );
port(
i : in std_logic;
ibar : in std_logic;
o : out std_logic);
end alt_inbuf_diff;
architecture BEHAVIOR of alt_inbuf_diff is
begin
process(i, ibar)
variable out_tmp : std_logic;
variable in_tmp : std_logic_vector(1 downto 0);
begin
in_tmp(0) := ibar;
in_tmp(1) := i;
case in_tmp is
when "00" => out_tmp := 'X';
when "01" => out_tmp := '0';
when "10" => out_tmp := '1';
when "11" => out_tmp := 'X';
when others => out_tmp := 'X';
end case;
o <= out_tmp;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_diff" );
port(
i : in std_logic;
o : out std_logic;
obar : out std_logic);
end alt_outbuf_diff;
architecture BEHAVIOR of alt_outbuf_diff is
begin
o <= i;
obar <= not i;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_outbuf_tri_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
lpm_type : string := "alt_outbuf_tri_diff" );
port(
i : in std_logic;
oe : in std_logic;
o : out std_logic;
obar : out std_logic);
end alt_outbuf_tri_diff;
architecture BEHAVIOR of alt_outbuf_tri_diff is
begin
o <= i when oe = '1'
else 'Z' when oe = '0'
else 'X';
obar <= (not i) when oe = '1'
else 'Z' when oe = '0'
else 'X';
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_iobuf_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_iobuf_diff" );
port(
i : in std_logic;
oe : in std_logic;
io : inout std_logic;
iobar : inout std_logic;
o : out std_logic);
end alt_iobuf_diff;
architecture BEHAVIOR of alt_iobuf_diff is
begin
process(i, io, iobar, oe)
variable in_tmp : std_logic_vector(1 downto 0);
variable out_tmp : std_logic;
begin
in_tmp(0) := iobar;
in_tmp(1) := io;
case in_tmp is
when "00" => out_tmp := 'X';
when "01" => out_tmp := '0';
when "10" => out_tmp := '1';
when "11" => out_tmp := 'X';
when others => out_tmp := 'X';
end case;
if oe = '1' then
io <= i;
iobar <= not i;
elsif oe = '0' then
io <= 'Z';
iobar <= 'Z';
else
io <= 'X';
iobar <= 'X';
end if;
o <= out_tmp;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_bidir_diff is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_diff" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic;
iobar : inout std_logic);
end alt_bidir_diff;
architecture BEHAVIOR of alt_bidir_diff is
begin
process(bidirin, io, iobar, oe)
variable in_tmp : std_logic_vector(1 downto 0);
variable out_tmp : std_logic;
begin
in_tmp(0) := iobar;
in_tmp(1) := io;
case in_tmp is
when "00" => out_tmp := 'X';
when "01" => out_tmp := '0';
when "10" => out_tmp := '1';
when "11" => out_tmp := 'X';
when others => out_tmp := 'X';
end case;
if oe = '1' then
io <= bidirin;
iobar <= not bidirin;
bidirin <= 'Z';
elsif oe = '0' then
io <= 'Z';
iobar <= 'Z';
bidirin <= out_tmp;
else
io <= 'X';
iobar <= 'X';
bidirin <= 'X';
end if;
end process;
end BEHAVIOR;
Library ieee;
use ieee.std_logic_1164.all;
entity alt_bidir_buf is
generic(
io_standard : string := "NONE";
current_strength : string := "NONE";
current_strength_new : string := "NONE";
slew_rate : integer := -1;
location : string := "NONE";
enable_bus_hold : string := "NONE";
weak_pull_up_resistor : string := "NONE";
termination : string := "NONE";
input_termination : string := "NONE";
output_termination : string := "NONE";
lpm_type : string := "alt_bidir_buf" );
port(
oe : in std_logic;
bidirin : inout std_logic;
io : inout std_logic);
end alt_bidir_buf;
architecture BEHAVIOR of alt_bidir_buf is
begin
process(bidirin, io, oe)
variable in_tmp : std_logic;
variable out_tmp : std_logic;
begin
in_tmp := io;
case in_tmp is
when '0' => out_tmp := '0';
when '1' => out_tmp := '1';
when others => out_tmp := 'X';
end case;
if oe = '1' then
io <= bidirin;
bidirin <= 'Z';
elsif oe = '0' then
io <= 'Z';
bidirin <= out_tmp;
else
io <= 'X';
bidirin <= 'X';
end if;
end process;
end BEHAVIOR;
| gpl-3.0 | 91f9ac61fc139b8eb5751eb9e4ad9f73 | 0.477455 | 3.947665 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/max_components.vhd | 1 | 2,787 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.max_atom_pack.all;
package MAX_COMPONENTS is
component max_mcell
generic ( operation_mode : string := "normal";
output_mode : string := "comb";
register_mode : string := "dff";
pexp_mode : string := "off";
power_up : string := "low");
port ( pterm0 : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pterm1 : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pterm2 : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pterm3 : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pterm4 : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pterm5 : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pclk : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pena : in std_logic_vector(51 downto 0) := (OTHERS => '1');
paclr : in std_logic_vector(51 downto 0) := (OTHERS => '1');
papre : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pxor : in std_logic_vector(51 downto 0) := (OTHERS => '1');
pexpin : in std_logic := '0';
clk : in std_logic := '0';
fpin : in std_logic := '1';
aclr : in std_logic := '0';
dataout : out std_logic;
pexpout : out std_logic );
end component;
component max_io
generic ( operation_mode : string := "input";
open_drain_output :string := "false";
bus_hold : string := "false";
weak_pull_up : string := "false");
port ( datain : in std_logic := '0';
oe : in std_logic := '1';
devoe : in std_logic := '0';
dataout : out std_logic;
padio : inout std_logic);
end component;
component max_sexp
port ( datain : in std_logic_vector(51 downto 0) := (OTHERS => '1');
dataout : out std_logic);
end component;
end max_components;
| gpl-3.0 | 39f854c0dbaf138ad2bb8a7ab8c71bb1 | 0.610693 | 3.432266 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_alu.vhd | 1 | 8,091 | -------------------------------------------------------------------------------
--
-- The Arithmetic Logic Unit (ALU).
-- It contains the accumulator and the C flag.
--
-- $Id: t400_alu.vhd,v 1.3 2006-05-22 00:01:56 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
use work.t400_opt_pack.all;
entity t400_alu is
generic (
opt_cko_g : integer := t400_opt_cko_crystal_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
cko_i : in std_logic;
-- Control Interface ------------------------------------------------------
op_i : in alu_op_t;
-- Data Interface ---------------------------------------------------------
m_i : in dw_t;
dec_data_i : in dec_data_t;
q_low_i : in dw_t;
b_i : in b_t;
g_i : in dw_t;
in_i : in dw_t;
sio_i : in dw_t;
a_o : out dw_t;
carry_o : out std_logic;
c_o : out std_logic
);
end t400_alu;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_alu is
subtype alu_dw_t is unsigned(dw_t'high+1 downto 0);
signal alu_result_s : alu_dw_t;
signal a_q : dw_t;
signal c_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process regs
--
-- Purpose:
-- Implements the sequential registers of the ALU:
-- * A - accumulator
-- * C - carry flag
--
regs: process (ck_i, por_i)
begin
if por_i then
a_q <= (others => '0');
c_q <= '0';
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
a_q <= (others => '0');
c_q <= '0';
elsif ck_en_i then
-- update accumulator
case op_i is
when ALU_CLRA |
ALU_ADD |
ALU_ADD_10 |
ALU_ADD_C |
ALU_ADD_DEC |
ALU_COMP |
ALU_XOR =>
a_q <= std_logic_vector(alu_result_s(dw_t'range));
when ALU_LOAD_M =>
a_q <= m_i;
when ALU_LOAD_Q =>
a_q <= q_low_i;
when ALU_LOAD_G =>
a_q <= g_i;
when ALU_LOAD_IN =>
a_q <= in_i;
when ALU_LOAD_IL =>
a_q(3) <= in_i(3);
if opt_cko_g = t400_opt_cko_gpi_c then
a_q(2) <= cko_i;
else
a_q(2) <= '1';
end if;
a_q(1) <= '0';
a_q(0) <= in_i(0);
when ALU_LOAD_BR =>
a_q(3 downto 2) <= (others => '0');
a_q(1 downto 0) <= b_i(br_range_t);
when ALU_LOAD_BD =>
a_q <= b_i(bd_range_t);
when ALU_LOAD_SIO =>
a_q <= sio_i;
when others =>
null;
end case;
-- update C flag upon the following instructions
case op_i is
-- carry result of addition -----------------------------------------
when ALU_ADD_C =>
c_q <= alu_result_s(alu_dw_t'high);
-- reset C flag -----------------------------------------------------
when ALU_RC =>
c_q <= '0';
-- set C flag -------------------------------------------------------
when ALU_SC =>
c_q <= '1';
when others =>
null;
end case;
end if;
end if;
end process regs;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process dp
--
-- Purpose:
-- Implements the ALU's data path.
--
dp: process (op_i,
a_q,
m_i,
dec_data_i,
c_q)
variable in1_v,
in2_v,
in3_v,
add_v, xor_v : alu_dw_t;
begin
-- prepare adder
in1_v := '0' & unsigned(a_q);
if op_i = ALU_ADD_10 then
in2_v := to_unsigned(10, alu_dw_t'length);
elsif op_i = ALU_ADD_DEC then
in2_v := '0' & unsigned(dec_data_i(dw_t'range));
else
in2_v := '0' & unsigned(m_i);
end if;
if op_i = ALU_ADD_C then
in3_v := (others => '0');
in3_v(0) := c_q;
else
in3_v := (others => '0');
end if;
add_v := in1_v + in2_v + in3_v;
-- prepare exclusive or
xor_v := in1_v xor in2_v;
case op_i is
-- ALU operation: Clear accumulator -------------------------------------
when ALU_CLRA =>
alu_result_s <= (others => '0');
-- ALU operation: Add to accumulator ------------------------------------
when ALU_ADD |
ALU_ADD_10 |
ALU_ADD_C |
ALU_ADD_DEC =>
alu_result_s <= add_v;
-- ALU operation: Complement accumulator --------------------------------
when ALU_COMP =>
alu_result_s <= '0' & not unsigned(a_q);
-- ALU operation: XOR to accumulator ------------------------------------
when ALU_XOR =>
alu_result_s <= xor_v;
when others =>
alu_result_s <= (others => '-');
end case;
end process dp;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
a_o <= a_q;
carry_o <= alu_result_s(alu_dw_t'high);
c_o <= c_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/21 21:47:40 arniml
-- route cko to ALU for INIL instruction
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | a1d4e08e5abf1eb6323a82705636236a | 0.457051 | 3.929577 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_int.vhd | 1 | 6,596 | -------------------------------------------------------------------------------
--
-- Testbench for interrupt evaluation.
--
-- $Id: tb_int.vhd,v 1.5 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_int is
end tb_int;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.t400_system_comp_pack.t420;
use work.tb_pack.all;
use work.t400_opt_pack.all;
architecture behav of tb_int is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_8_s : std_logic_vector(7 downto 0);
begin
vdd_8_s <= (others => '1');
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c,
opt_l_out_type_3_g => t400_opt_out_type_od_c,
opt_l_out_type_2_g => t400_opt_out_type_od_c,
opt_l_out_type_1_g => t400_opt_out_type_od_c,
opt_l_out_type_0_g => t400_opt_out_type_od_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_8_s(0),
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
io_in_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => vdd_8_s,
io_d_i => io_d_s,
io_g_i => vdd_8_s(3 downto 0),
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
-----------------------------------------------------------------------------
-- Process int
--
-- Purpose:
-- Generates interrupts based on current PC.
--
int: process
variable int_v : std_logic;
begin
loop
wait until tb_pc_s'event;
-- see if we need to generate an interrupt
case to_integer(tb_pc_s) is
when 16#030# =>
int_v := '0';
when 16#0b0# =>
int_v := '0';
when 16#1b0# =>
int_v := '0';
when 16#230# =>
int_v := '0';
when 16#2b0# =>
int_v := '0';
when 16#330# =>
int_v := '0';
when 16#3b0# =>
int_v := '0';
when others =>
int_v := 'H';
end case;
io_in_s(1) <= int_v;
if int_v = '0' then
-- wait for appropriate interrupt active time
wait for period_c * 4 * 3; -- three instruction cycles
io_in_s(1) <= 'H';
end if;
end loop;
end process int;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- MUX the nibbles of SA to L
-----------------------------------------------------------------------------
io_l_s(3 downto 0) <= std_logic_vector(tb_sa_s(3 downto 0))
when io_g_s(1 downto 0) = "00" else
std_logic_vector(tb_sa_s(7 downto 4))
when io_g_s(1 downto 0) = "01" else
'0' & '0' & std_logic_vector(tb_sa_s(9 downto 8))
when io_g_s(1 downto 0) = "10" else
(others => 'H');
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/05/28 23:09:20 arniml
-- lower nibble is OD to prevent contention with testbench
--
-- Revision 1.3 2006/05/28 15:36:59 arniml
-- don't generate interrupt when in interrupt routine around 0x100
--
-- Revision 1.2 2006/05/28 02:53:47 arniml
-- provide SA at L port
--
-- Revision 1.1 2006/05/27 19:08:21 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | cb0d7848b8b3575d1b199172d257250e | 0.497878 | 3.668521 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_t411.vhd | 1 | 4,542 | -------------------------------------------------------------------------------
--
-- Testbench for the T411 system toplevel.
--
-- $Id: tb_t411.vhd,v 1.6 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t411 is
end tb_t411;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t411;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t411 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(1 downto 0);
signal io_g_s : std_logic_vector(2 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t411_b : t411
generic map (
opt_ck_div_g => t400_opt_ck_div_8_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 2,
g_width_g => 3
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2006/05/27 19:10:12 arniml
-- explicitly select clock divider 8
--
-- Revision 1.4 2006/05/23 01:18:26 arniml
-- consider IN port
--
-- Revision 1.3 2006/05/15 21:56:02 arniml
-- moved elements to separate design unit tb_elems
--
-- Revision 1.2 2006/05/06 13:34:25 arniml
-- remove delta cycle filter on sk_s
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 5545b5d5ba9240486af8e0db87e3ca5b | 0.551299 | 3.726005 | false | false | false | false |
keith-epidev/md2x | build/code/pulser.vhdl | 1 | 829 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.my_lib.all;
entity pulser is
generic(
delay:integer := 500000
);
port(
clk: in std_logic;
enable: in std_logic;
output: out std_logic
);
end pulser;
architecture Behavioral of pulser is
signal timer: std_logic_vector(f_log2(delay)-1 downto 0);
signal pulse: std_logic;
begin
output <= pulse;
pulser_signal:process(clk)
begin
if(clk'event and clk = '1')then
if(pulse = '1')then
pulse <= '0';
end if;
if(enable = '1') then
if(timer < delay -1)then
timer <= timer + 1;
else
pulse <= '1';
timer <= (others=>'0');
end if;
else
timer <= (others=>'0');
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 6054adef0712bcf27bca792269432224 | 0.594692 | 2.868512 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiigx_atoms.vhd | 1 | 673,860 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixiigx_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixiigx_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixiigx_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiigx_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixiigx_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixiigx_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixiigx_pllpack;
package body stratixiigx_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixiigx_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiigx_dffe : entity is TRUE;
end stratixiigx_dffe;
-- architecture body --
architecture behave of stratixiigx_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixiigx_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixiigx_mux21 : entity is TRUE;
end stratixiigx_mux21;
architecture AltVITAL of stratixiigx_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiigx_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_mux41 : entity is TRUE;
end stratixiigx_mux41;
architecture AltVITAL of stratixiigx_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiigx_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiigx_atom_pack.all;
-- entity declaration --
entity stratixiigx_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiigx_and1 : entity is TRUE;
end stratixiigx_and1;
-- architecture body --
architecture AltVITAL of stratixiigx_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
----------------------------------------------------------------------------
-- Module Name : stratixiigx_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixiigx_ram_register;
ARCHITECTURE reg_arch OF stratixiigx_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixiigx_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiigx_ram_pulse_generator:ENTITY IS TRUE;
END stratixiigx_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiigx_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE work.stratixiigx_ram_register;
USE work.stratixiigx_ram_pulse_generator;
ENTITY stratixiigx_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiigx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixiigx_ram_block;
ARCHITECTURE block_arch OF stratixiigx_ram_block IS
COMPONENT stratixiigx_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiigx_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= '1' WHEN (port_a_disable_ce_on_input_registers = "on") ELSE ena0;
active_b_in <= '1' WHEN (port_b_disable_ce_on_input_registers = "on") ELSE
ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : stratixiigx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : stratixiigx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
stall => wire_gnd,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixiigx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : stratixiigx_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixiigx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixiigx_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : stratixiigx_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : stratixiigx_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixiigx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixiigx_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixiigx_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : stratixiigx_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixiigx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : stratixiigx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : stratixiigx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : stratixiigx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= '1' WHEN (port_a_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= '1' WHEN (port_b_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixiigx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixiigx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-------------------------------------------------------------------
--
-- Entity Name : stratixiigx_jtag
--
-- Description : StratixIIGX JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_jtag is
generic (
lpm_type : string := "stratixiigx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixiigx_jtag;
architecture architecture_jtag of stratixiigx_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixiigx_crcblock
--
-- Description : StratixIIGX CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixiigx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixiigx_crcblock;
architecture architecture_crcblock of stratixiigx_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
-------------------------------------------------------------------
--
-- Entity Name : stratixiigx_asmiblock
--
-- Description : StratixIIGXIIGX ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_asmiblock is
generic (
lpm_type : string := "stratixiigx_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
end stratixiigx_asmiblock;
architecture architecture_asmiblock of stratixiigx_asmiblock is
begin
process(dclkin, scein, sdoin, oe)
begin
end process;
end architecture_asmiblock; -- end of stratixiigx_asmiblock
---------------------------------------------------------------------
--
-- Entity Name : stratixiigx_lcell_ff
--
-- Description : StratixIIGX LCELL_FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
use work.stratixiigx_and1;
entity stratixiigx_lcell_ff is
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixiigx_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_lcell_ff : entity is TRUE;
end stratixiigx_lcell_ff;
architecture vital_lcell_ff of stratixiigx_lcell_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal datain_dly : std_logic;
signal adatasdata_ipd : std_logic;
signal adatasdata_dly : std_logic;
signal adatasdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal aclr_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixiigx_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
dataindelaybuffer: stratixiigx_and1
port map(IN1 => datain_ipd,
Y => datain_dly);
adatasdatadelaybuffer: stratixiigx_and1
port map(IN1 => adatasdata_ipd,
Y => adatasdata_dly);
adatasdatadelaybuffer1: stratixiigx_and1
port map(IN1 => adatasdata_dly,
Y => adatasdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (adatasdata_ipd, adatasdata, tipd_adatasdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, datain_dly, adatasdata_dly1,
sclr_ipd, sload_ipd, aclr_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_adatasdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_adatasdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(aload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_adatasdata_clk,
TimingData => TimingData_adatasdata_clk,
TestSignal => adatasdata_ipd,
TestSignalName => "ADATASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_adatasdata_clk_noedge_posedge,
SetupLow => tsetup_adatasdata_clk_noedge_posedge,
HoldHigh => thold_adatasdata_clk_noedge_posedge,
HoldLow => thold_adatasdata_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_adatasdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (aclr_ipd = '1')) then
iregout := '0';
elsif (aload_ipd = '1') then
iregout := adatasdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := adatasdata_dly1;
else
iregout := datain_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => iregout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (adatasdata_ipd'last_event, tpd_adatasdata_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
---------------------------------------------------------------------
--
-- Entity Name : stratixiigx_lcell_comb
--
-- Description : StratixIIGX LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixiigx_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_lcell_comb : entity is TRUE;
end stratixiigx_lcell_comb;
architecture vital_lcell_comb of stratixiigx_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_ena_reg : entity is TRUE;
end stratixiigx_ena_reg;
ARCHITECTURE behave of stratixiigx_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/ENA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for StratixIIGX CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIIGX_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
use work.stratixiigx_ena_reg;
entity stratixiigx_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiigx_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_clkctrl : entity is TRUE;
end stratixiigx_clkctrl;
architecture vital_clkctrl of stratixiigx_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component stratixiigx_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : stratixiigx_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg_out
);
outclk <= cereg_out AND clkmux_out;
end vital_clkctrl;
--
--
-- STRATIXIIGX_ASYNCH_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_asynch_io is
generic(
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
dqs_input_frequency : STRING := "10000 ps";
dqs_out_mode : STRING := "none";
dqs_delay_buffer_mode : STRING := "low";
dqs_phase_shift : INTEGER := 0;
dqs_offsetctrl_enable : STRING := "false";
dqs_ctrl_latches_enable : STRING := "false";
dqs_edge_detect_enable : STRING := "false";
gated_dqs : STRING := "false";
sim_dqs_intrinsic_delay : INTEGER := 0;
sim_dqs_delay_increment : INTEGER := 0;
sim_dqs_offset_increment : INTEGER := 0;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_regin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_dqsupdateen : VitalDelayType01 := DefPropDelay01;
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01));
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of stratixiigx_asynch_io : entity is TRUE;
end stratixiigx_asynch_io;
architecture behave of stratixiigx_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_in : std_logic_vector(5 downto 0);
signal offsetctrlin_in : std_logic_vector(5 downto 0);
signal dqsupdateen_in : std_logic;
signal dqs_delay_int : integer := 0;
signal tmp_dqsbusout : std_logic;
signal dqs_ctrl_latches_ena : std_logic := '1';
signal combout_tmp_sig : std_logic := '0';
signal dqsbusout_tmp_sig : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_in(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (delayctrlin_in(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_in(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_in(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_in(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_in(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
VitalWireDelay (offsetctrlin_in(5), offsetctrlin(5), tipd_offsetctrlin(5));
VitalWireDelay (offsetctrlin_in(4), offsetctrlin(4), tipd_offsetctrlin(4));
VitalWireDelay (offsetctrlin_in(3), offsetctrlin(3), tipd_offsetctrlin(3));
VitalWireDelay (offsetctrlin_in(2), offsetctrlin(2), tipd_offsetctrlin(2));
VitalWireDelay (offsetctrlin_in(1), offsetctrlin(1), tipd_offsetctrlin(1));
VitalWireDelay (offsetctrlin_in(0), offsetctrlin(0), tipd_offsetctrlin(0));
end block;
dqs_ctrl_latches_ena <= '1' when dqs_ctrl_latches_enable = "false" ELSE
dqsupdateen_in when dqs_edge_detect_enable = "false" ELSE
(not (combout_tmp_sig xor tmp_dqsbusout) and dqsupdateen_in);
process(delayctrlin_in, offsetctrlin_in, dqs_ctrl_latches_ena)
variable tmp_delayctrl : integer := 0;
variable tmp_offsetctrl : integer := 0;
begin
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
tmp_delayctrl := 31;
else
tmp_delayctrl := alt_conv_integer(delayctrlin_in);
end if;
if (dqs_offsetctrl_enable = "true") then
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
tmp_offsetctrl := 31;
else
tmp_offsetctrl := alt_conv_integer(offsetctrlin_in);
end if;
else
tmp_offsetctrl := 0;
end if;
if (dqs_ctrl_latches_ena = '1') THEN
dqs_delay_int <= sim_dqs_intrinsic_delay + sim_dqs_delay_increment*tmp_delayctrl + sim_dqs_offset_increment*tmp_offsetctrl;
end if;
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
assert false report "OFFSETCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
end process;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, tmp_dqsbusout)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable dqsbusout_tmp : std_logic;
variable combout_delay : VitalDelayType01 := (0 ps, 0 ps);
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
tmp_dqsbusout <= transport tmp_combout after (dqs_delay_int * 1 ps);
if (gated_dqs = "true") then
dqsbusout_tmp := tmp_dqsbusout AND regin;
else
dqsbusout_tmp := tmp_dqsbusout;
end if;
-- for dqs delay ctrl latches enable
dqsbusout_tmp_sig <= dqsbusout_tmp;
combout_tmp_sig <= tmp_combout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => dqsbusout_tmp,
Paths => (1 => (tmp_dqsbusout'last_event, tpd_padio_dqsbusout, TRUE),
2 => (regin'last_event, tpd_regin_dqsbusout, gated_dqs = "true")),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- STRATIXIIGX_IO_REGISTER
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_io_register is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_io_register : entity is TRUE;
end stratixiigx_io_register;
architecture vital_io_reg of stratixiigx_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--
-- STRATIXIIGX_IO_LATCH
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_io_latch is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_io_latch : entity is TRUE;
end stratixiigx_io_latch;
architecture vital_io_latch of stratixiigx_io_latch is
attribute VITAL_LEVEL0 of vital_io_latch : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd = '1') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_latch;
--
-- STRATIXIIGX_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
use work.stratixiigx_asynch_io;
use work.stratixiigx_io_register;
use work.stratixiigx_io_latch;
use work.stratixiigx_mux21;
use work.stratixiigx_and1;
entity stratixiigx_io is
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixiigx_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end stratixiigx_io;
architecture structure of stratixiigx_io is
component stratixiigx_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout: out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
end component;
component stratixiigx_io_register
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component stratixiigx_io_latch
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component stratixiigx_mux21
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component stratixiigx_and1
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
begin
not_inclk <= (ddioinclk) WHEN (ddioinclk_input = "dqsb_bus") ELSE (not inclk);
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : stratixiigx_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map ( regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio0_reg
in_ddio0_reg : stratixiigx_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map (regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio1_latch
in_ddio1_reg : stratixiigx_io_latch
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => "none", -- this register does not have sync_reset
POWER_UP => input_power_up)
port map (regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn);
-- out_reg
out_reg : stratixiigx_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- out ddio reg
out_ddio_reg : stratixiigx_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe reg
oe_reg : stratixiigx_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe_pulse reg
oe_pulse_reg : stratixiigx_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : stratixiigx_and1
port map (Y => outclk_delayed,
IN1 => outclk);
ddio_data_mux : stratixiigx_mux21
port map (MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : stratixiigx_asynch_io
generic map ( OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
dqs_input_frequency => dqs_input_frequency,
dqs_out_mode => dqs_out_mode,
dqs_delay_buffer_mode => dqs_delay_buffer_mode,
dqs_phase_shift => dqs_phase_shift,
dqs_offsetctrl_enable => dqs_offsetctrl_enable,
dqs_ctrl_latches_enable => dqs_ctrl_latches_enable,
dqs_edge_detect_enable => dqs_edge_detect_enable,
gated_dqs => gated_dqs,
sim_dqs_intrinsic_delay => sim_dqs_intrinsic_delay,
sim_dqs_delay_increment => sim_dqs_delay_increment,
sim_dqs_offset_increment => sim_dqs_offset_increment)
port map( datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
padio => padio,
delayctrlin => delayctrlin,
offsetctrlin => offsetctrlin,
dqsupdateen => dqsupdateen,
dqsbusout => dqsbusout,
combout => combout,
regout => regout,
ddioregout => ddioregout);
end structure;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiigx_m_cntr
--
-- Description : Timing simulation model for the M counter. M is the loop
-- feedback counter of the StratixIIGX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiigx_m_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiigx_m_cntr;
ARCHITECTURE behave of stratixiigx_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiigx_n_cntr
--
-- Description : Timing simulation model for the N counter. N is the
-- input counter of the StratixIIGX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiigx_n_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiigx_n_cntr;
ARCHITECTURE behave of stratixiigx_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on PLL input clk. This edge will be ignored." severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiigx_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixIIGX PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiigx_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixiigx_scale_cntr;
ARCHITECTURE behave of stratixiigx_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiigx_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixiigx_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixiigx_pll_reg;
ARCHITECTURE behave of stratixiigx_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiigx_pll
--
-- Description : Timing simulation model for the StratixIIGX PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 6 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixiigx_atom_pack.all;
USE work.stratixiigx_pllpack.all;
USE work.stratixiigx_m_cntr;
USE work.stratixiigx_n_cntr;
USE work.stratixiigx_scale_cntr;
USE work.stratixiigx_dffe;
USE work.stratixiigx_pll_reg;
ENTITY stratixiigx_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
-- LVDS mode parameters
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiigx_pll";
-- Simulation only generics
family_name : string := "StratixIIGX";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
-- lvds specific ports
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END stratixiigx_pll;
ARCHITECTURE vital_pll of stratixiigx_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 5) := (OTHERS => 0);
signal c_high_val : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val : int_array(0 to 5) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 5) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 5);
-- old values
signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 5);
-- hold registers
signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 5);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal sig_c_hi_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0);
--signal i_clk5_counter : string(1 to 2) := "c5";
--signal i_clk4_counter : string(1 to 2) := "c4";
--signal i_clk3_counter : string(1 to 2) := "c3";
--signal i_clk2_counter : string(1 to 2) := "c2";
--signal i_clk1_counter : string(1 to 2) := "c1";
--signal i_clk0_counter : string(1 to 2) := "c0";
signal i_clk5_counter : integer := 5;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT GPP_SCAN_CHAIN : integer := 174;
CONSTANT FAST_SCAN_CHAIN : integer := 75;
CONSTANT GATE_LOCK_CYCLES : integer := 7;
CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148);
CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000");
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal c_clk : std_logic_array(0 to 5);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_tap : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_out_last_value : std_logic_vector(7 downto 0);
signal vco_tap_last_value : std_logic_vector(7 downto 0);
-- signals to assign values to counter params
signal m_val : int_array(0 to 1) := (OTHERS => 1);
signal n_val : int_array(0 to 1) := (OTHERS => 1);
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 9) := " ";
-- old values
signal m_val_old : int_array(0 to 1) := (OTHERS => 1);
signal n_val_old : int_array(0 to 1) := (OTHERS => 1);
signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 9) := " ";
signal num_output_cntrs : integer := 6;
signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal sclkout0_tmp : std_logic;
signal sclkout1_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanread_ipd : std_logic;
signal scanwrite_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
-- registered signals
signal scanread_reg : std_logic := '0';
signal scanwrite_reg : std_logic := '0';
signal scanwrite_enabled : std_logic := '0';
signal gated_scanclk : std_logic := '1';
signal inclk_c0_dly1 : std_logic := '0';
signal inclk_c0_dly2 : std_logic := '0';
signal inclk_c0_dly3 : std_logic := '0';
signal inclk_c0_dly4 : std_logic := '0';
signal inclk_c0_dly5 : std_logic := '0';
signal inclk_c0_dly6 : std_logic := '0';
signal inclk_c1_dly1 : std_logic := '0';
signal inclk_c1_dly2 : std_logic := '0';
signal inclk_c1_dly3 : std_logic := '0';
signal inclk_c1_dly4 : std_logic := '0';
signal inclk_c1_dly5 : std_logic := '0';
signal inclk_c1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "c0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal ext_fbk_cntr_index : integer := 0;
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandone_tmp : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 5);
signal inclk_m_from_vco : std_logic;
signal inclk_sclkout0_from_vco : std_logic;
signal inclk_sclkout1_from_vco : std_logic;
--signal tap0_is_active : boolean := true;
signal sig_quiet_time : time := 0 ps;
signal sig_slowest_clk_old : time := 0 ps;
signal sig_slowest_clk_new : time := 0 ps;
signal sig_m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
COMPONENT stratixiigx_m_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiigx_n_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiigx_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiigx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixiigx_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanread_ipd, scanread, tipd_scanread);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (scanwrite_ipd, scanwrite, tipd_scanwrite);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
inclk_m <= clkin when m_test_source = 0 else
clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else
clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else
clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else
clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else
clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else
clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else
inclk_m_from_vco;
ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index);
ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index);
ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index);
ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index);
ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index);
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
pll_in_test_mode <= true when m_test_source /= 5 or c0_test_source /= 5 or
c1_test_source /= 5 or c2_test_source /= 5 or
c3_test_source /= 5 or c4_test_source /= 5 or
c5_test_source /= 5 else
false;
m1 : stratixiigx_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val(0),
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
end process;
process (inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end process;
process (inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end process;
n1 : stratixiigx_n_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val(0),
modulus => n_val(0));
inclk_c0 <= clkin when c0_test_source = 0 else
refclk when c0_test_source = 1 else
inclk_c_from_vco(0);
c0 : stratixiigx_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= clkin when c1_test_source = 0 else
fbclk when c1_test_source = 2 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixiigx_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= clkin when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixiigx_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= clkin when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixiigx_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= '0' when (pll_type = "fast") else
clkin when (c4_test_source = 0) else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixiigx_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= '0' when (pll_type = "fast") else
clkin when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixiigx_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c0_dly2 <= inclk_c0_dly1;
inclk_c0_dly3 <= inclk_c0_dly2;
inclk_c0_dly4 <= inclk_c0_dly3;
inclk_c0_dly5 <= inclk_c0_dly4;
inclk_c0_dly6 <= inclk_c0_dly5;
inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c1_dly2 <= inclk_c1_dly1;
inclk_c1_dly3 <= inclk_c1_dly2;
inclk_c1_dly4 <= inclk_c1_dly3;
inclk_c1_dly5 <= inclk_c1_dly4;
inclk_c1_dly6 <= inclk_c1_dly5;
process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0_dly6'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1_dly6'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "c0") then
enable0_tmp <= c0_tmp;
elsif (enable0_counter = "c1") then
enable0_tmp <= c1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "c0") then
enable1_tmp <= c0_tmp;
elsif (enable1_counter = "c1") then
enable1_tmp <= c1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (sim_gate_lock_device_behavior = "on") then
if (count = gate_lock_counter) then
output := '1';
end if;
elsif (count = GATE_LOCK_CYCLES) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT family_name & " PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val(0));
write (buf, string'(" ( "));
write (buf, n_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val(0));
write (buf, string'(" ( "));
write (buf, m_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
if (ss > 0) then
write (buf, string'(" M2 modulus = "));
write (buf, m_val(1));
write (buf, string'(" ( "));
write (buf, m_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" N2 modulus = "));
write (buf, n_val(1));
write (buf, string'(" ( "));
write (buf, n_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
end if;
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, sig_c_low_val_tmp(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_tap, fbclk, scanclk_ipd, gated_scanclk)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable n_fast : std_logic_vector(1 downto 0);
variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
variable c_mode_val_tmp : str_array(0 to 5);
variable m_ph_val_tmp : integer := 0;
variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_m2 : integer;
variable i_n2 : integer;
variable i_ss : integer;
variable i_c_high : int_array(0 to 5);
variable i_c_low : int_array(0 to 5);
variable i_c_initial : int_array(0 to 5);
variable i_c_ph : int_array(0 to 5);
variable i_c_mode : str_array(0 to 5);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 2) := "c0";
variable clk1_cntr : string(1 to 2) := "c1";
variable clk2_cntr : string(1 to 2) := "c2";
variable clk3_cntr : string(1 to 2) := "c3";
variable clk4_cntr : string(1 to 2) := "c4";
variable clk5_cntr : string(1 to 2) := "c5";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable m_lo, m_hi : std_logic_vector(4 downto 0);
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable got_first_gated_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable scanclk_period : time := 0 ps;
variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable Tviol_scanread_scanclk : std_ulogic := '0';
variable Tviol_scanwrite_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanread_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanwrite_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
if (refclk_int > (refclk_int * max_modulus / m_mod)) then
q_period := refclk_int * 1 ps;
else
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(2) = '0') then
index := 0;
elsif (arg(2) = '1') then
index := 1;
elsif (arg(2) = '2') then
index := 2;
elsif (arg(2) = '3') then
index := 3;
elsif (arg(2) = '4') then
index := 4;
else index := 5;
end if;
return index;
end extract_cntr_index;
begin
if (init) then
if (m = 0) then
clk5_cntr := "c5";
clk4_cntr := "c4";
clk3_cntr := "c3";
clk2_cntr := "c2";
clk1_cntr := "c1";
clk0_cntr := "c0";
else
clk5_cntr := clk5_counter;
clk4_cntr := clk4_counter;
clk3_cntr := clk3_counter;
clk2_cntr := clk2_counter;
clk1_cntr := clk1_counter;
clk0_cntr := clk0_counter;
end if;
if (operation_mode = "external_feedback") then
if (feedback_source = "clk0") then
fbk_cntr := clk0_cntr;
elsif (feedback_source = "clk1") then
fbk_cntr := clk1_cntr;
elsif (feedback_source = "clk2") then
fbk_cntr := clk2_cntr;
elsif (feedback_source = "clk3") then
fbk_cntr := clk3_cntr;
elsif (feedback_source = "clk4") then
fbk_cntr := clk4_cntr;
elsif (feedback_source = "clk5") then
fbk_cntr := clk5_cntr;
else
fbk_cntr := "c0";
end if;
if (fbk_cntr = "c0") then
fbk_cntr_index := 0;
elsif (fbk_cntr = "c1") then
fbk_cntr_index := 1;
elsif (fbk_cntr = "c2") then
fbk_cntr_index := 2;
elsif (fbk_cntr = "c3") then
fbk_cntr_index := 3;
elsif (fbk_cntr = "c4") then
fbk_cntr_index := 4;
elsif (fbk_cntr = "c5") then
fbk_cntr_index := 5;
end if;
ext_fbk_cntr <= fbk_cntr;
ext_fbk_cntr_index <= fbk_cntr_index;
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (i_c_mode(fbk_cntr_index) = "bypass") then
output_count := 1;
else
output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index);
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val(0) <= i_n;
m_val(0) <= i_m;
m_val(1) <= m2;
n_val(1) <= n2;
if (i_m = 1) then
m_mode_val(0) <= "bypass";
else
m_mode_val(0) <= " ";
end if;
if (m2 = 1) then
m_mode_val(1) <= "bypass";
end if;
if (i_n = 1) then
n_mode_val(0) <= "bypass";
end if;
if (n2 = 1) then
n_mode_val(1) <= "bypass";
end if;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
m_val_tmp := m_val;
for i in 0 to 5 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds") then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_tmp(i) := i_c_ph(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
lfc_val <= loop_filter_c;
lfr_val <= loop_filter_r;
cp_curr_val <= charge_pump_current;
if (pll_type = "fast") then
scan_chain_length := FAST_SCAN_CHAIN;
end if;
-- initialize the scan_chain contents
-- CP/LF bits
scan_data(11 downto 0) <= "000000000000";
for i in 0 to 3 loop
if (pll_type = "fast" or pll_type = "lvds") then
if (fpll_loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
else
if (loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
end if;
end loop;
for i in 0 to 15 loop
if (charge_pump_curr_arr(i) = charge_pump_current) then
scan_data(3 downto 0) <= int2bin(i, 4);
end if;
end loop;
for i in 0 to 39 loop
if (loop_filter_r_arr(i) = loop_filter_r) then
if (i >= 16 and i <= 23) then
scan_data(9 downto 4) <= int2bin((i+8), 6);
elsif (i >= 24 and i <= 31) then
scan_data(9 downto 4) <= int2bin((i+16), 6);
elsif (i >= 32) then
scan_data(9 downto 4) <= int2bin((i+24), 6);
else
scan_data(9 downto 4) <= int2bin(i, 6);
end if;
end if;
end loop;
if (pll_type = "fast" or pll_type = "lvds") then
scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph
-- C0-C3 high
scan_data(25 downto 22) <= int2bin(i_c_high(0), 4);
scan_data(35 downto 32) <= int2bin(i_c_high(1), 4);
scan_data(45 downto 42) <= int2bin(i_c_high(2), 4);
scan_data(55 downto 52) <= int2bin(i_c_high(3), 4);
-- C0-C3 low
scan_data(30 downto 27) <= int2bin(i_c_low(0), 4);
scan_data(40 downto 37) <= int2bin(i_c_low(1), 4);
scan_data(50 downto 47) <= int2bin(i_c_low(2), 4);
scan_data(60 downto 57) <= int2bin(i_c_low(3), 4);
-- C0-C3 mode
for i in 0 to 3 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(26 + (10*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
else
scan_data(26 + (10*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
end if;
end loop;
-- M
if (i_m = 1) then
scan_data(66) <= '1';
scan_data(71) <= '0';
scan_data(65 downto 62) <= "0000";
scan_data(70 downto 67) <= "0000";
else
scan_data(66) <= '0'; -- set BYPASS bit to 0
scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low
if (i_m rem 2 = 0) then
-- M is an even no. : set M high = low,
-- set odd/even bit to 0
scan_data(65 downto 62) <= int2bin(i_m/2, 4);
scan_data(71) <= '0';
else -- M is odd : M high = low + 1
scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4);
scan_data(71) <= '1';
end if;
end if;
-- N
scan_data(73 downto 72) <= int2bin(i_n, 2);
if (i_n = 1) then
scan_data(74) <= '1';
scan_data(73 downto 72) <= "00";
end if;
else -- PLL type is auto or enhanced
scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph
-- C0-C5 high
scan_data(123 downto 116) <= int2bin(i_c_high(0), 8);
scan_data(105 downto 98) <= int2bin(i_c_high(1), 8);
scan_data(87 downto 80) <= int2bin(i_c_high(2), 8);
scan_data(69 downto 62) <= int2bin(i_c_high(3), 8);
scan_data(51 downto 44) <= int2bin(i_c_high(4), 8);
scan_data(33 downto 26) <= int2bin(i_c_high(5), 8);
-- C0-C5 low
scan_data(132 downto 125) <= int2bin(i_c_low(0), 8);
scan_data(114 downto 107) <= int2bin(i_c_low(1), 8);
scan_data(96 downto 89) <= int2bin(i_c_low(2), 8);
scan_data(78 downto 71) <= int2bin(i_c_low(3), 8);
scan_data(60 downto 53) <= int2bin(i_c_low(4), 8);
scan_data(42 downto 35) <= int2bin(i_c_low(5), 8);
-- C0-C5 mode
for i in 0 to 5 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(124 - (18*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
else
scan_data(124 - (18*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
end if;
end loop;
-- M/M2
scan_data(142 downto 134) <= int2bin(i_m, 9);
scan_data(143) <= '0';
scan_data(152 downto 144) <= int2bin(m2, 9);
scan_data(153) <= '0';
if (i_m = 1) then
scan_data(143) <= '1';
scan_data(142 downto 134) <= "000000000";
end if;
if (m2 = 1) then
scan_data(153) <= '1';
scan_data(152 downto 144) <= "000000000";
end if;
-- N/N2
scan_data(162 downto 154) <= int2bin(i_n, 9);
scan_data(172 downto 164) <= int2bin(n2, 9);
if (i_n = 1) then
scan_data(163) <= '1';
scan_data(162 downto 154) <= "000000000";
end if;
if (n2 = 1) then
scan_data(173) <= '1';
scan_data(172 downto 164) <= "000000000";
end if;
end if;
if (pll_type = "fast" or pll_type = "lvds") then
num_output_cntrs <= 4;
else
num_output_cntrs <= 6;
end if;
init := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then
-- falling edge : deassert scandone
scandone_tmp <= transport '0' after (1.5 * scanclk_period);
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
reconfig_err <= false;
-- make temporary copy of scan_data for processing
tmp_scan_data := scan_data;
-- save old values
lfc_old <= lfc_val;
lfr_old <= lfr_val;
cp_curr_old <= cp_curr_val;
-- CP
-- Bits 0-3 : all values are legal
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0)));
-- LF Resistance : bits 4-9
-- values from 010000 - 010111, 100000 - 100111,
-- 110000 - 110111 are illegal
lfr_tmp := tmp_scan_data(9 downto 4);
lfr_int := alt_conv_integer(lfr_tmp);
if (((lfr_int >= 16) and (lfr_int <= 23)) or
((lfr_int >= 32) and (lfr_int <= 39)) or
((lfr_int >= 48) and (lfr_int <= 55))) then
reconfig_err <= true;
ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning;
else
if (lfr_int >= 56) then
lfr_int := lfr_int - 24;
elsif ((lfr_int >= 40) and (lfr_int <= 47)) then
lfr_int := lfr_int - 16;
elsif ((lfr_int >= 24) and (lfr_int <= 31)) then
lfr_int := lfr_int - 8;
end if;
lfr_val <= loop_filter_r_arr(lfr_int);
end if;
-- LF Capacitance : bits 10,11 : all values are legal
lfc_tmp := scan_data(11 downto 10);
if (pll_type = "fast" or pll_type = "lvds") then
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp));
else
lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp));
end if;
-- cntrs c0-c5
-- save old values for display info.
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
m_ph_val_old <= m_ph_val;
c_high_val_old <= c_high_val;
c_low_val_old <= c_low_val;
c_ph_val_old <= c_ph_val;
c_mode_val_old <= c_mode_val;
-- first the M counter phase : bit order same for fast and GPP
if (scan_data(12) = '0') then
-- do nothing
elsif (scan_data(12) = '1' and scan_data(13) = '1') then
m_ph_val_tmp := m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7) then
m_ph_val_tmp := 0;
end if;
elsif (scan_data(12) = '1' and scan_data(13) = '0') then
m_ph_val_tmp := m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0) then
m_ph_val_tmp := 7;
end if;
else
reconfig_err <= true;
ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning;
end if;
-- read the fast PLL bits
if (pll_type = "fast" or pll_type = "lvds") then
-- C3-C0 phase bits
for i in 3 downto 0 loop
start_bit := 14 + ((3-i)*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
-- C0-C3 counter moduli
for i in 0 to 3 loop
start_bit := 22 + (i*10);
if (tmp_scan_data(start_bit + 4) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high_fast := tmp_scan_data(start_bit+3 downto start_bit);
low_fast := tmp_scan_data(start_bit+8 downto start_bit+5);
if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then
c_high_val_tmp(i) := 16;
else
c_high_val_tmp(i) := alt_conv_integer(high_fast);
end if;
if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then
c_low_val_tmp(i) := 16;
else
c_low_val_tmp(i) := alt_conv_integer(low_fast);
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- M
-- some temporary storage
if (tmp_scan_data(65 downto 62) = "0000") then
m_hi := "10000";
else
m_hi := "0" & tmp_scan_data(65 downto 62);
end if;
if (tmp_scan_data(70 downto 67) = "0000") then
m_lo := "10000";
else
m_lo := "0" & tmp_scan_data(70 downto 67);
end if;
m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
if (tmp_scan_data(66) = '1') then
if (tmp_scan_data(71) = '1') then
-- this will turn off the M counter : error
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning;
else -- M counter is being bypassed
if (m_mode_val(0) /= "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(0) := 1;
m_mode_val(0) <= "bypass";
end if;
else
if (m_mode_val(0) = "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning;
end if;
m_mode_val(0) <= " ";
if (tmp_scan_data(71) = '1') then
-- odd : check for duty cycle, if not 50% -- error
if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
else -- even
if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
-- N
is_error := false;
n_fast := tmp_scan_data(73 downto 72);
n_val(0) <= alt_conv_integer(n_fast);
if (tmp_scan_data(74) /= '1') then
if (alt_conv_integer(n_fast) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_fast) = 0) then
n_val(0) <= 4;
ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note;
end if;
if (not is_error) then
if (n_mode_val(0) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning;
else
ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note;
end if;
n_mode_val(0) <= " ";
end if;
elsif (tmp_scan_data(74) = '1') then
if (tmp_scan_data(72) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(0) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(0) <= 1;
n_mode_val(0) <= "bypass";
end if;
end if;
else -- GENERAL PURPOSE PLL
for i in 0 to 5 loop
start_bit := 116 - (i*18);
if (tmp_scan_data(start_bit + 8) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high := tmp_scan_data(start_bit + 7 downto start_bit);
low := tmp_scan_data(start_bit+16 downto start_bit+9);
if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then
c_high_val_tmp(i) := 256;
else
c_high_val_tmp(i) := alt_conv_integer(high);
end if;
if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then
c_low_val_tmp(i) := 256;
else
c_low_val_tmp(i) := alt_conv_integer(low);
end if;
end loop;
-- the phase taps
for i in 0 to 5 loop
start_bit := 14 + (i*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- cntrs M/M2
for i in 0 to 1 loop
start_bit := 134 + (i*10);
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
m_tmp := tmp_scan_data(start_bit+8 downto start_bit);
m_val_tmp(i) := alt_conv_integer(m_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(m_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then
m_val_tmp(i) := 512;
end if;
if (not is_error) then
if (m_mode_val(i) = "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning;
else
end if;
m_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val(i) /= "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(i) := 1;
m_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (m_mode_val(0) /= m_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
sig_m_val_tmp <= m_val_tmp;
-- cntrs N/N2
for i in 0 to 1 loop
start_bit := 154 + i*10;
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
n_tmp := tmp_scan_data(start_bit+8 downto start_bit);
n_val(i) <= alt_conv_integer(n_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(n_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_tmp) = 0) then
n_val(i) <= 512;
end if;
if (not is_error) then
if (n_mode_val(i) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning;
else
end if;
n_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(i) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(i) <= 1;
n_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (n_mode_val(0) /= n_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val(1)+c_low_val(1), c_mode_val(1),
c_high_val(2)+c_low_val(2), c_mode_val(2),
c_high_val(3)+c_low_val(3), c_mode_val(3),
c_high_val(4)+c_low_val(4), c_mode_val(4),
c_high_val(5)+c_low_val(5), c_mode_val(5),
sig_refclk_period, m_val(0));
slowest_clk_new := slowest_clk(c_high_val_tmp(0)+c_low_val_tmp(0), c_mode_val_tmp(0),
c_high_val_tmp(1)+c_low_val_tmp(1), c_mode_val_tmp(1),
c_high_val_tmp(2)+c_low_val_tmp(2), c_mode_val_tmp(2),
c_high_val_tmp(3)+c_low_val_tmp(3), c_mode_val_tmp(3),
c_high_val_tmp(4)+c_low_val_tmp(4), c_mode_val_tmp(4),
c_high_val_tmp(5)+c_low_val_tmp(5), c_mode_val_tmp(5),
sig_refclk_period, m_val_tmp(0));
if (slowest_clk_new > slowest_clk_old) then
quiet_time := slowest_clk_new;
else
quiet_time := slowest_clk_old;
end if;
sig_quiet_time <= quiet_time;
sig_slowest_clk_old <= slowest_clk_old;
sig_slowest_clk_new <= slowest_clk_new;
tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps);
scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps);
if (tmp_rem /= 0) then
scanclk_cycles := scanclk_cycles + 1;
end if;
scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2));
end if;
if (scanwrite_enabled = '1') then
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (c_clk(0)'event and c_clk(0) = '1') then
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
c0_rising_edge_transfer_done := true;
end if;
if (c_clk(1)'event and c_clk(1) = '1') then
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
c1_rising_edge_transfer_done := true;
end if;
if (c_clk(2)'event and c_clk(2) = '1') then
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
c2_rising_edge_transfer_done := true;
end if;
if (c_clk(3)'event and c_clk(3) = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (c_clk(4)'event and c_clk(4) = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (c_clk(5)'event and c_clk(5) = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
end if;
if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanwrite_enabled = '1') then
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x) and vco_tap(x) = '0') then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = x) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end loop;
end if;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
if (areset_ipd = '1') then
c_ph_val <= i_c_ph;
c_ph_val_tmp := i_c_ph;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
end if;
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x)) then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
inclk_c_from_vco(i) <= vco_tap(x);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
end if;
end loop;
if (m_ph_val = x) then
inclk_m_from_vco <= vco_tap(x);
end if;
vco_tap_last_value(x) <= vco_tap(x);
end if;
end loop;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_posedge,
SetupLow => tsetup_scandata_scanclk_noedge_posedge,
HoldHigh => thold_scandata_scanclk_noedge_posedge,
HoldLow => thold_scandata_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiigx_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanread_scanclk,
TimingData => TimingData_scanread_scanclk,
TestSignal => scanread_ipd,
TestSignalName => "scanread",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanread_scanclk_noedge_posedge,
SetupLow => tsetup_scanread_scanclk_noedge_posedge,
HoldHigh => thold_scanread_scanclk_noedge_posedge,
HoldLow => thold_scanread_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiigx_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanwrite_scanclk,
TimingData => TimingData_scanwrite_scanclk,
TestSignal => scanwrite_ipd,
TestSignalName => "scanwrite",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanwrite_scanclk_noedge_posedge,
SetupLow => tsetup_scanwrite_scanclk_noedge_posedge,
HoldHigh => thold_scanwrite_scanclk_noedge_posedge,
HoldLow => thold_scanwrite_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiigx_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event and scanclk_ipd = '0') then
-- enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end if;
if (scanread_reg = '1') then
gated_scanclk <= transport scanclk_ipd and scanread_reg;
else
gated_scanclk <= transport '1';
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
-- register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk) then
scanclk_period := now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
-- reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd = '0' and scanread_reg = '1') then
got_first_scanclk := false;
got_first_gated_scanclk := false;
end if;
scanclk_last_rising_edge := now;
end if;
if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then
if (not got_first_gated_scanclk) then
got_first_gated_scanclk := true;
end if;
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
end process;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1);
SCHEDULE : process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, vco_out)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable pll_is_disabled : boolean := false;
variable next_vco_sched_time : time := 0 ps;
variable tap0_is_active : boolean := true;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val(0) * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
pll_is_in_reset := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
if (ena_ipd = '1' and not stop_vco and next_vco_sched_time <= now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
pll_is_disabled := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
if (ena_ipd'event and ena_ipd = '1') then
assert false report family_name & " PLL is enabled" severity note;
pll_is_disabled := false;
if (areset_ipd /= '1' and not stop_vco and next_vco_sched_time < now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- illegal value on areset_ipd
if (areset_ipd'event and areset_ipd = 'X') then
assert false report "Illegal value 'X' detected on ARESET input" severity warning;
end if;
if (areset_ipd = '1' or ena_ipd = '0' or stop_vco) then
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
-- first_schedule := true;
-- vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
-- reset all counter phase taps to POF programmed values
end if;
if (schedule_vco'event and areset_ipd /= '1' and ena_ipd /= '0' and (not stop_vco) and now > 0 ps) then
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val(0);
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val(0) * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus);
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_M := initial_delay/1 ps + fbk_phase;
end if;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap0
vco_out(0) <= transport vco_val after sched_time;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap 0
vco_out(0) <= transport vco_val after sched_time;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
next_vco_sched_time := now + sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- now schedule the other taps with the appropriate phase-shift
if (vco_out(0)'event) then
for k in 1 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_out(0) after phase_shift(k);
end loop;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped : do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
-- check which vco_tap has event
for x in 0 to 7 loop
if (vco_out(x) /= vco_out_last_value(x)) then
-- TAP X has event
if (x = 0 and areset_ipd = '0' and ena_ipd = '1' and sig_stop_vco = '0') then
if (vco_out(0) = '1') then
tap0_is_active := true;
end if;
if (tap0_is_active) then
vco_tap(0) <= vco_out(0);
end if;
elsif (tap0_is_active) then
vco_tap(x) <= vco_out(x);
end if;
if (sig_stop_vco = '1') then
vco_tap(x) <= '0';
end if;
vco_out_last_value(x) <= vco_out(x);
end if;
end loop;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
end process SCHEDULE;
clk0_tmp <= c_clk(i_clk0_counter);
clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk(3) <= clk3_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk(4) <= clk4_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk(5) <= clk5_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(0) <= sclkout0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(1) <= sclkout1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
scandataout <= scandataout_tmp;
scandone <= scandone_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiigx_mac_bit_register
--
-- Description : a single bit register. This is used for registering all
-- single bit input ports.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_bit_register IS
GENERIC (
power_up : std_logic := '0';
tipd_data : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0'
);
END stratixiigx_mac_bit_register;
ARCHITECTURE arch OF stratixiigx_mac_bit_register IS
SIGNAL data_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic := '0';
SIGNAL viol_notifier : std_logic := '0';
SIGNAL data_dly : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
clk_delay: process (data_ipd)
begin
data_dly <= data_ipd;
end process;
PROCESS (data_dly, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_reg : STD_LOGIC := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg := data_dly;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg := '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
end if;
end if;
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_REGISTER
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_register IS
GENERIC (
data_width : integer := 18;
power_up : std_logic := '0';
tipd_data : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END stratixiigx_mac_register;
ARCHITECTURE arch OF stratixiigx_mac_register IS
SIGNAL data_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL viol_notifier : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
PROCESS (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg <= data_ipd;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg <= (others => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
end if;
end if;
END PROCESS;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_reg(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_reg(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_RS_BLOCK
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_rs_block IS
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END stratixiigx_mac_rs_block;
ARCHITECTURE arch OF stratixiigx_mac_rs_block IS
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tbuf : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_mult : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dly : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturated : std_logic := '0';
SIGNAL min : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL max : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL msb : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
round_ipd <= round ;
saturate_ipd <= saturate ;
addnsub_ipd <= addnsub ;
signa_ipd <= signa ;
signb_ipd <= signb ;
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
datain_ipd(71 downto 0) <= datain(71 downto 0) ;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
addnsub_ipd,
round_ipd)
VARIABLE dataout_round_tmp2 : std_logic_vector(71 DOWNTO 0);
BEGIN
IF (round_ipd = '1') THEN
dataout_round_tmp2 := datain_ipd + (2 **(conv_integer(dataoutsize - signsize - roundsize - "00000001")));
ELSE
dataout_round_tmp2 := datain_ipd;
END IF;
dataout_round <= dataout_round_tmp2;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
addnsub_ipd,
dataout_round)
VARIABLE dataout_saturate_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE saturated_tmp4 : std_logic := '0';
VARIABLE gnd : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE min_tmp5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE max_tmp6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE msb_tmp7 : std_logic := '0';
VARIABLE i : integer;
BEGIN
IF (saturate_ipd = '1') THEN
IF (block_type = "mac_mult") THEN
IF (dataout_round(dataa_width + datab_width - 1) = '0' AND dataout_round(dataa_width + datab_width - 2) = '1') THEN
dataout_saturate_tmp3 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN dataa_width + datab_width - 2 TO (72 - 1) LOOP
dataout_saturate_tmp3(i) := '0';
END LOOP;
saturated_tmp4 := '1';
ELSE
dataout_saturate_tmp3 := dataout_round;
saturated_tmp4 := '0';
END IF;
min_tmp5 := dataout_saturate_tmp3;
max_tmp6 := dataout_saturate_tmp3;
ELSE
IF ((operation(2) = '1') AND ((block_type = "ab") OR (block_type = "cd"))) THEN
saturated_tmp4 := '0';
i := datab_width - 2;
WHILE (i < (datab_width + signsize - 2)) LOOP
IF (dataout_round(datab_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
IF (saturated_tmp4 = '1') THEN
min_tmp5 := "111111111111111111111111111111111111111111111111111111111111111111111111";
max_tmp6 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN 0 TO ((datab_width - 2) - 1) LOOP
max_tmp6(i) := '0';
END LOOP;
FOR i IN datab_width - 2 TO (72 - 1) LOOP
min_tmp5(i) := '0';
END LOOP;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
msb_tmp7 := dataout_round(datab_width + 15);
ELSE
IF ((signa_ipd OR signb_ipd OR NOT addnsub_ipd) = '1') THEN
min_tmp5 := gnd + (2 **(conv_integer(dataa_width)));
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width))) - 1);
ELSE
min_tmp5 := "000000000000000000000000000000000000000000000000000000000000000000000000";
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width + 1))) - 1);
END IF;
saturated_tmp4 := '0';
i := dataa_width - 2;
WHILE (i < (dataa_width + signsize - 1)) LOOP
IF (dataout_round(dataa_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
msb_tmp7 := dataout_round(i);
END IF;
IF (saturated_tmp4 = '1') THEN
IF (msb_tmp7 = '1') THEN
dataout_saturate_tmp3 := max_tmp6;
ELSE
dataout_saturate_tmp3 := min_tmp5;
END IF;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
END IF;
ELSE
saturated_tmp4 := '0';
dataout_saturate_tmp3 := dataout_round;
END IF;
dataout_saturate <= dataout_saturate_tmp3;
saturated <= saturated_tmp4;
min <= min_tmp5;
max <= max_tmp6;
msb <= msb_tmp7;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
dataout_round,
dataout_saturate)
VARIABLE dataout_dly_tmp8 : std_logic_vector(71 DOWNTO 0);
VARIABLE i : integer;
VARIABLE width_tmp : integer;
BEGIN
IF (round_ipd = '1') THEN
dataout_dly_tmp8 := dataout_saturate;
width_tmp := conv_integer(dataoutsize) - conv_integer(signsize) - conv_integer(roundsize);
i := 0;
WHILE (i < width_tmp) LOOP
dataout_dly_tmp8(i) := '0';
i := i + 1;
END LOOP;
ELSE
dataout_dly_tmp8 := dataout_saturate;
END IF;
dataout_dly <= dataout_dly_tmp8;
END PROCESS;
dataout_tbuf <= datain WHEN (operation = 0) OR (operation = 7) ELSE rs_saturate ;
rs_saturate <= rs_mac_mult WHEN (saturate_ipd = '1') ELSE rs_mac_out ;
rs_mac_mult <= (dataout_dly(71 DOWNTO 3) & "00" & saturated)
WHEN ((saturate_ipd = '1') AND (saturated = '1') AND (block_type = "mac_mult")) ELSE rs_mac_out ;
rs_mac_out <= (dataout_dly(71 DOWNTO 3) & saturated & datain_ipd(1 DOWNTO 0))
WHEN ((saturate_ipd = '1') AND (block_type /= "mac_mult")) ELSE dataout_dly ;
pathDelay : BLOCK
BEGIN
g1 : for i in dataout'range generate
PROCESS (dataout_tbuf)
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(i),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END GENERATE;
END BLOCK;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_MULT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_mult_internal IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width : integer := 36;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0) := (others => '0')
);
END stratixiigx_mac_mult_internal;
ARCHITECTURE arch OF stratixiigx_mac_mult_internal IS
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL neg : std_logic := '0';
SIGNAL dataout_pre_bypass : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_output : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
BEGIN
neg <= (dataa_ipd(dataa_width - 1) AND signa) XOR (datab_ipd(datab_width - 1) AND signb) ;
abs_a <= (NOT dataa_ipd(dataa_width - 1 DOWNTO 0) + 1) WHEN (signa AND dataa_ipd(dataa_width - 1)) = '1' ELSE dataa_ipd(dataa_width - 1 DOWNTO 0) ;
abs_b <= (NOT datab_ipd(datab_width - 1 DOWNTO 0) + 1) WHEN (signb AND datab_ipd(datab_width - 1)) = '1' ELSE datab_ipd(datab_width - 1 DOWNTO 0) ;
abs_output((dataa_width + datab_width) - 1 DOWNTO 0) <= abs_a(dataa_width-1 downto 0) * abs_b(datab_width-1 downto 0) ;
dataout_pre_bypass((dataa_width + datab_width) - 1 DOWNTO 0) <= (NOT abs_output + 1) WHEN neg = '1' ELSE abs_output ;
dataout_tmp((dataa_width + datab_width) - 1 DOWNTO 0) <= datab(datab_width-1 downto 0) & dataa(dataa_width-1 downto 0) when ((dynamic_mode = "yes") and (bypass = '1')) else dataa(dataa_width-1 downto 0) & datab(datab_width-1 downto 0) WHEN (bypass = '1') ELSE dataout_pre_bypass ;
PathDelay : block
begin
do:for i in dataout_tmp'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
sa: for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
PROCESS(dataa_ipd)
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sa;
sb: for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
PROCESS(datab_ipd)
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sb;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_MULT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
use work.stratixiigx_mac_mult_internal;
use work.stratixiigx_mac_bit_register;
use work.stratixiigx_mac_register;
use work.stratixiigx_mac_rs_block;
ENTITY stratixiigx_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixiigx_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiigx_mac_mult;
ARCHITECTURE arch OF stratixiigx_mac_mult IS
COMPONENT stratixiigx_mac_mult_internal
GENERIC (
dataout_width : integer := 36;
dataa_width : integer := 18;
datab_width : integer := 18;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0));
END COMPONENT;
COMPONENT stratixiigx_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixiigx_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT stratixiigx_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL mult_output : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL round_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL mode_out : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_rs : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_src : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_dataa : std_logic := '0';
SIGNAL clear_dataa : std_logic := '0';
SIGNAL aclr_dataa : std_logic := '0';
SIGNAL ena_dataa : std_logic := '0';
SIGNAL async_dataa : std_logic := '0';
SIGNAL clk_datab : std_logic := '0';
SIGNAL clear_datab : std_logic := '0';
SIGNAL aclr_datab : std_logic := '0';
SIGNAL ena_datab : std_logic := '0';
SIGNAL async_datab : std_logic := '0';
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_round : std_logic := '0';
SIGNAL clear_round : std_logic := '0';
SIGNAL aclr_round : std_logic := '0';
SIGNAL ena_round : std_logic := '0';
SIGNAL async_round : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode : std_logic := '0';
SIGNAL clear_mode : std_logic := '0';
SIGNAL aclr_mode : std_logic := '0';
SIGNAL ena_mode : std_logic := '0';
SIGNAL async_mode : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL signa_internal : std_logic := '0';
SIGNAL signb_internal : std_logic := '0';
SIGNAL bypass : std_logic := '0';
SIGNAL mac_mult_dataoutsize : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_60 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp62 : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL port_tmp63 : std_logic := '0';
SIGNAL port_tmp64 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp65 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp2 : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp3 : std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
BEGIN
dataout <= dataout_tmp1(dataout'range);
scanouta <= scanouta_tmp2;
scanoutb <= scanoutb_tmp3;
dataout_tmp1 <= dataout_tmp(35 DOWNTO 0) ;
dataa_src <= scanina WHEN (sourcea = '1') ELSE dataa ;
datab_src <= scaninb WHEN (sourceb = '1') ELSE datab ;
dataa_mac_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => dataa_width,
power_up => '0')
PORT MAP (
data => dataa_src,
clk => clk_dataa,
aclr => aclr_dataa,
if_aclr => clear_dataa,
ena => ena_dataa,
dataout => scanouta_tmp,
async => async_dataa);
async_dataa <= '1' WHEN (dataa_clock = "none") ELSE '0' ;
clear_dataa <= '1' WHEN (dataa_clear /= "none") ELSE '0' ;
clk_dataa <= '1' WHEN clk(conv_integer(dataa_clk)) = '1' ELSE '0' ;
aclr_dataa <= '1' WHEN (aclr(conv_integer(dataa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_dataa <= '1' WHEN ena(conv_integer(dataa_clk)) = '1' ELSE '0' ;
dataa_clk <= "0000" WHEN ((dataa_clock = "0") OR (dataa_clock = "none")) ELSE "0001" WHEN (dataa_clock = "1") ELSE "0010" WHEN (dataa_clock = "2") ELSE "0011" WHEN (dataa_clock = "3") ELSE "0000" ;
dataa_aclr <= "0000" WHEN ((dataa_clear = "0") OR (dataa_clear = "none")) ELSE "0001" WHEN (dataa_clear = "1") ELSE "0010" WHEN (dataa_clear = "2") ELSE "0011" WHEN (dataa_clear = "3") ELSE "0000" ;
datab_mac_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => datab_width,
power_up => '0')
PORT MAP (
data => datab_src,
clk => clk_datab,
aclr => aclr_datab,
if_aclr => clear_datab,
ena => ena_datab,
dataout => scanoutb_tmp,
async => async_datab);
async_datab <= '1' WHEN (datab_clock = "none") ELSE '0' ;
clear_datab <= '1' WHEN (datab_clear /= "none") ELSE '0' ;
clk_datab <= '1' WHEN clk(conv_integer(datab_clk)) = '1' ELSE '0' ;
aclr_datab <= '1' WHEN (aclr(conv_integer(datab_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_datab <= '1' WHEN ena(conv_integer(datab_clk)) = '1' ELSE '0' ;
datab_clk <= "0000" WHEN ((datab_clock = "0") OR (datab_clock = "none")) ELSE "0001" WHEN (datab_clock = "1") ELSE "0010" WHEN (datab_clock = "2") ELSE "0011" WHEN (datab_clock = "3") ELSE "0000" ;
datab_aclr <= "0000" WHEN ((datab_clear = "0") OR (datab_clear = "none")) ELSE "0001" WHEN (datab_clear = "1") ELSE "0010" WHEN (datab_clear = "2") ELSE "0011" WHEN (datab_clear = "3") ELSE "0000" ;
signa_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_out,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_out,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
round_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round,
clk => clk_round,
aclr => aclr_round,
if_aclr => clear_round,
ena => ena_round,
dataout => round_out,
async => async_round);
async_round <= '1' WHEN (round_clock = "none") ELSE '0' ;
clear_round <= '1' WHEN (round_clear /= "none") ELSE '0' ;
clk_round <= '1' WHEN clk(conv_integer(round_clk)) = '1' ELSE '0' ;
aclr_round <= '1' WHEN (aclr(conv_integer(round_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round <= '1' WHEN ena(conv_integer(round_clk)) = '1' ELSE '0' ;
round_clk <= "0000" WHEN ((round_clock = "0") OR (round_clock = "none")) ELSE "0001" WHEN (round_clock = "1") ELSE "0010" WHEN (round_clock = "2") ELSE "0011" WHEN (round_clock = "3") ELSE "0000" ;
round_aclr <= "0000" WHEN ((round_clear = "0") OR (round_clear = "none")) ELSE "0001" WHEN (round_clear = "1") ELSE "0010" WHEN (round_clear = "2") ELSE "0011" WHEN (round_clear = "3") ELSE "0000" ;
saturate_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_out,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode,
clk => clk_mode,
aclr => aclr_mode,
if_aclr => clear_mode,
ena => ena_mode,
dataout => mode_out,
async => async_mode);
async_mode <= '1' WHEN (mode_clock = "none") ELSE '0' ;
clear_mode <= '1' WHEN (mode_clear /= "none") ELSE '0' ;
clk_mode <= '1' WHEN clk(conv_integer(mode_clk)) = '1' ELSE '0' ;
aclr_mode <= '1' WHEN (aclr(conv_integer(mode_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode <= '1' WHEN ena(conv_integer(mode_clk)) = '1' ELSE '0' ;
mode_clk <= "0000" WHEN ((mode_clock = "0") OR (mode_clock = "none")) ELSE "0001" WHEN (mode_clock = "1") ELSE "0010" WHEN (mode_clock = "2") ELSE "0011" WHEN (mode_clock = "3") ELSE "0000" ;
mode_aclr <= "0000" WHEN ((mode_clear = "0") OR (mode_clear = "none")) ELSE "0001" WHEN (mode_clear = "1") ELSE "0010" WHEN (mode_clear = "2") ELSE "0011" WHEN (mode_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_out,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
mac_multiply : stratixiigx_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
dataout_width => dataa_width + datab_width,
dynamic_mode => dynamic_mode)
PORT MAP (
dataa => scanouta_tmp,
datab => scanoutb_tmp,
signa => signa_internal,
signb => signb_internal,
bypass => bypass,
scanouta => scanouta_tmp2,
scanoutb => scanoutb_tmp3,
dataout => mult_output);
signa_internal <= '0' WHEN ((signa_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signa_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signa_out ;
signb_internal <= '0' WHEN ((signb_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signb_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signb_out ;
bypass <= '1' WHEN ((bypass_multiplier = "yes") AND (dynamic_mode = "no")) OR (((bypass_multiplier = "yes") AND (mode_out = '1')) AND (dynamic_mode = "yes")) ELSE '0' ;
tmp_60 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & mult_output(35 DOWNTO 0);
port_tmp62 <= "1111";
port_tmp63 <= '0';
port_tmp64 <= "00000010";
port_tmp65 <= "00001111";
mac_rs_block : stratixiigx_mac_rs_block
GENERIC MAP (
block_type => "mac_mult",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => port_tmp62,
round => round_out,
saturate => saturate_out,
addnsub => port_tmp63,
signa => signa_out,
signb => signb_out,
signsize => port_tmp64,
roundsize => port_tmp65,
dataoutsize => mac_mult_dataoutsize,
dataa => scanouta_tmp,
datab => scanoutb_tmp,
datain => tmp_60,
dataout => dataout_rs);
mac_mult_dataoutsize <= CONV_STD_LOGIC_VECTOR(dataa_width + datab_width, 8) ;
dataout_reg <= tmp_60 when bypass = '1' else dataout_rs;
dataout_mac_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => dataa_width + datab_width,
power_up => '0')
PORT MAP (
data => dataout_reg((dataa_width + datab_width) -1 downto 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_tmp((dataa_width + datab_width) -1 downto 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
END arch;
--////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_ADDNSUB
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_addnsub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
block_type : string := "ab");
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END stratixiigx_mac_addnsub;
ARCHITECTURE arch OF stratixiigx_mac_addnsub IS
-- REGULAR ADD/SUB
SIGNAL sa : std_logic := '0';
SIGNAL sb : std_logic := '0';
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
-- 36 BIT MULT
SIGNAL dataa_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
--SIGNAL z36 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--SIGNAL z18 : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
overflow <= overflow_tmp2;
PROCESS (dataa, datab, datac, datad, signa, signb, operation, addnsub)
--VARIABLE z36_tmp3 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--VARIABLE z18_tmp4 : std_logic_vector(17 DOWNTO 0) := (others => '0');
VARIABLE dataout_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE overflow_tmp_tmp13 : std_logic;
VARIABLE sa_tmp14 : std_logic;
VARIABLE sb_tmp15 : std_logic;
VARIABLE abs_a_tmp16 : std_logic_vector(71 DOWNTO 0);
VARIABLE abs_b_tmp17 : std_logic_vector(71 DOWNTO 0);
VARIABLE dataout_t : std_logic_vector(72 downto 0) := (others => '0');
VARIABLE dataa_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_s : std_logic_vector(71 downto 0) := (others => '0');
BEGIN
IF ((unsigned(operation) = 7) AND (block_type /= "sum")) THEN
dataa_u := (others => '0');
datab_u := (others => '0');
datac_u := (others => '0');
datad_u := (others => '0');
datab_s := (others => '0');
datac_s := (others => '0');
dataa_u(35 downto 0) := dataa(35 downto 0);
datab_u(71 downto 36) := datab(35 downto 0);
datab_s(71 downto 36) := datab(35 downto 0);
datac_u(53 downto 18) := datac(35 downto 0);
datac_s(71 downto 18) := sxt(datac(datac_width-1 downto 0), 54);
datad_u(53 downto 18) := datad(35 downto 0);
datad_s(71 downto 18) := sxt(datad(datad_width-1 downto 0), 54);
if((signa = '0') and (signb = '0')) then
dataout_tmp_tmp12 := unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signa = '0') and (signb = '1')) then
dataout_t := signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '0')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '1')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF ((operation(2) = '1') AND (block_type = "ab")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16) XOR dataout_tmp_tmp12(datab_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16);
END IF;
ELSE
IF ((operation(2) = '1') AND (block_type = "cd")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16) XOR dataout_tmp_tmp12(datad_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16);
END IF;
ELSE
IF (block_type = "sum") THEN
if ((signa = '1') and (signb = '0')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(ext(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '0') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(ext(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '1') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
else
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
unsigned(ext(dataa(dataa_width downto 0), dataa_width+2)) +
unsigned(ext(datab(datab_width downto 0), dataa_width+2));
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF (block_type = "cd") THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1) XOR dataout_tmp_tmp12(datac_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1);
END IF;
ELSE
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1) XOR dataout_tmp_tmp12(dataa_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1);
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
--z36 <= z36_tmp3;
--z18 <= z18_tmp4;
dataout_tmp <= dataout_tmp_tmp12;
overflow_tmp <= overflow_tmp_tmp13;
sa <= sa_tmp14;
sb <= sb_tmp15;
abs_a <= abs_a_tmp16;
abs_b <= abs_b_tmp17;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
overflow_tmp2 <= overflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_DYNAMIC_SRC
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_dynamic_src IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0'
);
END stratixiigx_mac_dynamic_src;
ARCHITECTURE arch OF stratixiigx_mac_dynamic_src IS
SIGNAL outa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp : std_logic := '0';
SIGNAL satb_tmp : std_logic := '0';
SIGNAL satc_tmp : std_logic := '0';
SIGNAL satd_tmp : std_logic := '0';
SIGNAL satab_tmp : std_logic := '0';
SIGNAL satcd_tmp : std_logic := '0';
SIGNAL i : integer;
SIGNAL j : integer;
SIGNAL outa_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp5 : std_logic := '0';
SIGNAL satb_tmp6 : std_logic := '0';
SIGNAL satc_tmp7 : std_logic := '0';
SIGNAL satd_tmp8 : std_logic := '0';
SIGNAL satab_tmp9 : std_logic := '0';
SIGNAL satcd_tmp10 : std_logic := '0';
SIGNAL dynamic_dataa_width : integer := 36;
SIGNAL dynamic_datab_width : integer := 36;
SIGNAL dynamic_datac_width : integer := 36;
SIGNAL dynamic_datad_width : integer := 36;
BEGIN
outa <= outa_tmp1;
outb <= outb_tmp2;
outc <= outc_tmp3;
outd <= outd_tmp4;
sata <= sata_tmp5;
satb <= satb_tmp6;
satc <= satc_tmp7;
satd <= satd_tmp8;
satab <= satab_tmp9;
satcd <= satcd_tmp10;
dynamic_dataa_width <= dataa_width WHEN (dataa_width > 0) ELSE 36;
dynamic_datab_width <= datab_width WHEN (datab_width > 0) ELSE 36;
dynamic_datac_width <= datac_width WHEN (datac_width > 0) ELSE 36;
dynamic_datad_width <= datad_width WHEN (datad_width > 0) ELSE 36;
PROCESS (accuma, accumc, dataa, datab, datac, datad, multabsaturate, multcdsaturate, signa, signb, zeroacc, zeroacc1, operation)
VARIABLE outa_tmp_tmp11 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outb_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outc_tmp_tmp13 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outd_tmp_tmp14 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE j_tmp15 : integer;
VARIABLE temp_tmp16 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE sata_tmp_tmp17 : std_logic := '0';
VARIABLE satb_tmp_tmp18 : std_logic := '0';
VARIABLE satc_tmp_tmp19 : std_logic := '0';
VARIABLE satd_tmp_tmp20 : std_logic := '0';
VARIABLE satab_tmp_tmp21 : std_logic := '0';
VARIABLE satcd_tmp_tmp22 : std_logic := '0';
BEGIN
CASE operation IS
WHEN "0000" =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') then
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "0100" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11:= sxt(dataa(datab_width+15 downto 0), 72);
ELSE
outa_tmp_tmp11:= ext(dataa(datab_width+15 downto 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
j_tmp15 := dataa_width - 1;
FOR i IN (datab_width + 15) DOWNTO 0 LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 - 1;
END LOOP;
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1100" =>
temp_tmp16 := zeroacc1 & zeroacc;
CASE temp_tmp16 IS
WHEN "00" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "01" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "10" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "11" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN OTHERS =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
WHEN "1101" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1110" =>
IF (zeroacc1 = '1') THEN
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN OTHERS =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signa = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signa = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
IF (multabsaturate = '1') THEN
IF ((outa_tmp_tmp11(0) AND ((zeroacc AND operation(2)) OR NOT operation(2))) = '1') THEN
sata_tmp_tmp17 := '1';
outa_tmp_tmp11(0) := '0';
ELSE
sata_tmp_tmp17 := '0';
END IF;
IF (outb_tmp_tmp12(0) = '1') THEN
satb_tmp_tmp18 := '1';
outb_tmp_tmp12(0) := '0';
ELSE
satb_tmp_tmp18 := '0';
END IF;
ELSE
sata_tmp_tmp17 := '0';
satb_tmp_tmp18 := '0';
END IF;
IF (multcdsaturate = '1') THEN
IF ((outc_tmp_tmp13(0) AND ((zeroacc1 AND operation(2)) OR NOT operation(2))) = '1') THEN
satc_tmp_tmp19 := '1';
outc_tmp_tmp13(0) := '0';
ELSE
satc_tmp_tmp19 := '0';
END IF;
IF (outd_tmp_tmp14(0) = '1') THEN
satd_tmp_tmp20 := '1';
outd_tmp_tmp14(0) := '0';
ELSE
satd_tmp_tmp20 := '0';
END IF;
ELSE
satc_tmp_tmp19 := '0';
satd_tmp_tmp20 := '0';
END IF;
IF ((sata_tmp_tmp17 OR satb_tmp_tmp18) = '1') THEN
satab_tmp_tmp21 := '1';
ELSE
satab_tmp_tmp21 := '0';
END IF;
IF ((satc_tmp_tmp19 OR satd_tmp_tmp20) = '1') THEN
satcd_tmp_tmp22 := '1';
ELSE
satcd_tmp_tmp22 := '0';
END IF;
outa_tmp <= outa_tmp_tmp11;
outb_tmp <= outb_tmp_tmp12;
outc_tmp <= outc_tmp_tmp13;
outd_tmp <= outd_tmp_tmp14;
j <= j_tmp15;
sata_tmp <= sata_tmp_tmp17;
satb_tmp <= satb_tmp_tmp18;
satc_tmp <= satc_tmp_tmp19;
satd_tmp <= satd_tmp_tmp20;
satab_tmp <= satab_tmp_tmp21;
satcd_tmp <= satcd_tmp_tmp22;
END PROCESS;
outa_tmp1 <= outa_tmp ;
outb_tmp2 <= outb_tmp ;
outc_tmp3 <= outc_tmp ;
outd_tmp4 <= outd_tmp ;
sata_tmp5 <= sata_tmp ;
satb_tmp6 <= satb_tmp ;
satc_tmp7 <= satc_tmp ;
satd_tmp8 <= satd_tmp ;
satab_tmp9 <= satab_tmp ;
satcd_tmp10 <= satcd_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_DYNAMIC_MUX
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_dynamic_mux IS
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END stratixiigx_mac_dynamic_mux;
ARCHITECTURE arch OF stratixiigx_mac_dynamic_mux IS
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
accoverflow <= accoverflow_tmp2;
PROCESS (ab, cd, sata, satb, satc, satd, multsatab, multsatcd, outsatab, outsatcd, multabsaturate, multcdsaturate, saturateab, saturatecd, overab, overcd, sum, m36, bypass, operation)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
VARIABLE accoverflow_tmp_tmp4 : std_logic := '0';
VARIABLE temp_tmp5 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp6 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp7 : std_logic_vector(3 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp8 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp9 : std_logic_vector(1 DOWNTO 0) := (others => '0');
BEGIN
CASE operation IS
WHEN "0000" =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
WHEN "0100" =>
temp_tmp5 := saturateab & multabsaturate;
CASE temp_tmp5 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "0001" =>
IF (multabsaturate = '1') THEN
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 2) & satb & sata;
ELSE
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 0);
END IF;
accoverflow_tmp_tmp4 := '0';
WHEN "0010" =>
temp_tmp6 := multsatcd & multsatab;
CASE temp_tmp6 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 2) & satb & sata;
accoverflow_tmp_tmp4 := '0';
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & sum(1 DOWNTO 0);
accoverflow_tmp_tmp4 := satd;
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & satb & sata;
accoverflow_tmp_tmp4 := satd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
END CASE;
WHEN "0111" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & m36;
accoverflow_tmp_tmp4 := '0';
WHEN "1100" =>
temp_tmp7 := saturatecd & saturateab & multsatcd & multsatab;
CASE temp_tmp7 IS
WHEN "0000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "0110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1101" =>
temp_tmp8 := saturateab & multabsaturate;
CASE temp_tmp8 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1110" =>
temp_tmp9 := saturatecd & multcdsaturate;
CASE temp_tmp9 IS
WHEN "00" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN "10" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overcd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
END CASE;
dataout_tmp <= dataout_tmp_tmp3;
accoverflow_tmp <= accoverflow_tmp_tmp4;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
accoverflow_tmp2 <= accoverflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_OUT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
use work.stratixiigx_mac_addnsub;
use work.stratixiigx_mac_dynamic_mux;
use work.stratixiigx_mac_dynamic_src;
use work.stratixiigx_mac_rs_block;
ENTITY stratixiigx_mac_out_internal IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width -1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0'
);
END stratixiigx_mac_out_internal;
ARCHITECTURE arch OF stratixiigx_mac_out_internal IS
COMPONENT stratixiigx_mac_addnsub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
block_type : string := "ab";
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixiigx_mac_dynamic_mux
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixiigx_mac_dynamic_src
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixiigx_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataa_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata : std_logic := '0';
SIGNAL satb : std_logic := '0';
SIGNAL satc : std_logic := '0';
SIGNAL satd : std_logic := '0';
SIGNAL satab : std_logic := '0';
SIGNAL satcd : std_logic := '0';
SIGNAL addnsub_ab_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_cd_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_sum : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_ab : std_logic := '0';
SIGNAL overflow_cd : std_logic := '0';
SIGNAL overflow_sum : std_logic := '0';
SIGNAL rs_block_ab_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_ab_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL feedback_ipd : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL saturateab_ipd : std_logic := '0';
SIGNAL saturatecd_ipd : std_logic := '0';
SIGNAL multabsaturate_ipd : std_logic := '0';
SIGNAL multcdsaturate_ipd : std_logic := '0';
SIGNAL dataout_tbuf : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tbuf : std_logic;
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signx_or_y : std_logic;
SIGNAL addnsub_signa_input : std_logic;
SIGNAL addnsub_signb_input : std_logic;
SIGNAL feedback_accuma : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL feedback_accumc : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL xory_addnsub0 : std_logic := '0';
SIGNAL xory_addnsub1 : std_logic := '0';
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_8 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_10 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp38 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp43 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp50 : std_logic := '0';
SIGNAL tmp_59 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataa_ipd(dataa_width -1 downto 0) <= dataa;
datab_ipd(datab_width -1 downto 0) <= datab;
datac_ipd(datac_width -1 downto 0) <= datac;
datad_ipd(datad_width -1 downto 0) <= datad;
WireDelay : block
begin
loopbits : FOR i in feedback'RANGE GENERATE
VitalWireDelay (feedback_ipd(i), feedback(i), tipd_feedback(i));
END GENERATE;
end block;
multabsaturate_ipd <= multabsaturate ;
multcdsaturate_ipd <= multcdsaturate ;
saturateab_ipd <= saturateab ;
saturatecd_ipd <= saturatecd ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '0')) AND (zeroacc1 = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE "0000" ;
addnsub_signa_input <= signx WHEN (operation_mode = "36_bit_multiply") ELSE signx WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
addnsub_signb_input <= signy WHEN (operation_mode = "36_bit_multiply") ELSE signy WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
tmp_4(dataa_ipd'range) <= dataa_ipd;
tmp_6(datab_ipd'range) <= datab_ipd;
tmp_8(datac_ipd'range) <= datac_ipd;
tmp_10(datad_ipd'range) <= datad_ipd;
dynamic_src : stratixiigx_mac_dynamic_src
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
accuma => feedback_accuma,
accumc => feedback_accumc,
dataa => tmp_4,
datab => tmp_6,
datac => tmp_8,
datad => tmp_10,
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
zeroacc => zeroacc,
zeroacc1 => zeroacc1,
signa => signx,
signb => signy,
operation => operation,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
satab => satab,
satcd => satcd,
outa => dataa_src,
outb => datab_src,
outc => datac_src,
outd => datad_src);
signx_or_y <= signx OR signy ;
feedback_accuma <= feedback(52 DOWNTO 37) & feedback(35 DOWNTO 0) WHEN (operation_mode = "dynamic") ELSE feedback(51 DOWNTO 0) ;
feedback_accumc <= feedback(124 DOWNTO 109) & feedback(107 DOWNTO 72) WHEN (operation_mode = "dynamic") ELSE feedback(123 DOWNTO 72) ;
addnsub_ab : stratixiigx_mac_addnsub
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => addnsub_signa_input,
signb => addnsub_signb_input,
operation => operation,
addnsub => addnsub0,
dataout => addnsub_ab_out,
overflow => overflow_ab);
addnsub_cd : stratixiigx_mac_addnsub
GENERIC MAP (
block_type => "cd",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => signx_or_y,
signb => signx_or_y,
operation => operation,
addnsub => addnsub1,
dataout => addnsub_cd_out,
overflow => overflow_cd);
port_tmp38 <= "00001111";
mac_rs_block_low : stratixiigx_mac_rs_block
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => operation,
round => roundab,
saturate => saturateab_ipd,
addnsub => addnsub0,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_ab_sign_size,
roundsize => port_tmp38,
dataoutsize => rs_block_ab_size,
dataa => dataa_src(dataa_width-1 downto 0),
datab => datab_src(datab_width-1 downto 0),
datain => addnsub_ab_out,
dataout => dataout_low);
rs_block_ab_size <= CONV_STD_LOGIC_VECTOR((datab_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_ab_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp43 <= "00001111";
mac_rs_block_high : stratixiigx_mac_rs_block
GENERIC MAP (
block_type => "cd",
dataa_width => datac_width,
datab_width => datad_width)
PORT MAP (
operation => operation,
round => roundcd,
saturate => saturatecd_ipd,
addnsub => addnsub1,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_cd_sign_size,
roundsize => port_tmp43,
dataoutsize => rs_block_cd_size,
dataa => datac_src(datac_width -1 downto 0),
datab => datad_src(datad_width -1 downto 0),
datain => addnsub_cd_out,
dataout => dataout_high);
rs_block_cd_size <= CONV_STD_LOGIC_VECTOR((datad_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_cd_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp50 <= '1';
addnsub_sum_abcd : stratixiigx_mac_addnsub
GENERIC MAP (
block_type => "sum",
dataa_width => dataa_width,
datab_width => dataa_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataout_low,
datab => dataout_high,
datac => datac_src,
datad => datad_src,
signa => xory_addnsub0,
signb => xory_addnsub1,
operation => operation,
addnsub => port_tmp50,
dataout => addnsub_sum,
overflow => overflow_sum);
xory_addnsub0 <= signx_or_y OR NOT addnsub0 ;
xory_addnsub1 <= signx_or_y OR NOT addnsub1 ;
tmp_59 <= datad_ipd & datac_ipd & datab_ipd & dataa_ipd;
dynamic_mux : stratixiigx_mac_dynamic_mux
PORT MAP (
ab => dataout_low,
cd => dataout_high,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
multsatab => satab,
multsatcd => satcd,
outsatab => dataout_low(2),
outsatcd => dataout_high(2),
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
saturateab => saturateab_ipd,
saturatecd => saturatecd_ipd,
overab => overflow_ab,
overcd => overflow_cd,
sum => addnsub_sum,
m36 => addnsub_ab_out,
bypass => tmp_59,
operation => operation,
dataout => dataout_tmp,
accoverflow => accoverflow_tmp);
PathDelay: for i in dataout'range generate
PROCESS(dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc'last_event, tpd_zeroacc_dataout(i), TRUE),
10 => (zeroacc1'last_event, tpd_zeroacc1_dataout(i), TRUE),
11 => (mode0'last_event, tpd_mode0_dataout(i), TRUE),
12 => (mode1'last_event, tpd_mode1_dataout(i), TRUE),
13 => (multabsaturate'last_event, tpd_multabsaturate_dataout(i), TRUE),
14 => (multcdsaturate'last_event, tpd_multcdsaturate_dataout(i), TRUE),
15 => (feedback'last_event, tpd_feedback_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate PathDelay;
acc: for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc'last_event, tpd_zeroacc_accoverflow, TRUE),
7 => (zeroacc1'last_event, tpd_zeroacc1_accoverflow, TRUE),
8 => (mode0'last_event, tpd_mode0_accoverflow, TRUE),
9 => (mode1'last_event, tpd_mode1_accoverflow, TRUE),
10 => (feedback'last_event, tpd_feedback_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
END GENERATE acc;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_PIN_MAP
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_mac_pin_map IS
GENERIC (
tipd_addnsub : VitalDelayType01 := DefPropDelay01;
data_width : integer := 144;
tipd_datain : VitalDelayArrayType01(143 downto 0) := (OTHERS => (20 ps,20 ps));
operation_mode : string := "output_only";
pinmap : string := "map");
PORT (
datain : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END stratixiigx_mac_pin_map;
ARCHITECTURE arch OF stratixiigx_mac_pin_map IS
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL datain_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp2 : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (addnsub_ipd, addnsub, tipd_addnsub);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
dataout <= dataout_tmp2(dataout'range);
PROCESS (datain_ipd, addnsub_ipd)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
BEGIN
IF (operation_mode = "dynamic") THEN
IF (pinmap = "map") THEN
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) &
'X' & datain_ipd(107 DOWNTO 72) &
"XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) &
'X' & datain_ipd(35 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := datain_ipd(143 DOWNTO 72)& "XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) & 'X' & datain_ipd(35 DOWNTO 0);
WHEN "1110" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) & 'X' & datain_ipd(107 DOWNTO 0);
WHEN "0111" =>
IF (addnsub_ipd = '1') THEN
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
ELSE
dataout_tmp_tmp3(17 DOWNTO 0) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(35 DOWNTO 18) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(53 DOWNTO 36) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(71 DOWNTO 54) := "XXXXXXXXXXXXXXXXXX";
END IF;
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
ELSE
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "1101" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(143 DOWNTO 72) := datain_ipd(143 DOWNTO 72);
WHEN "1110" =>
dataout_tmp_tmp3(107 DOWNTO 0) := datain_ipd(107 DOWNTO 0);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "0111" =>
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
END IF;
ELSE
dataout_tmp_tmp3 := datain_ipd;
END IF;
dataout_tmp <= dataout_tmp_tmp3;
END PROCESS;
dataout_tmp2 <= dataout_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXIIGX_MAC_OUT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
use work.stratixiigx_mac_out_internal;
use work.stratixiigx_mac_pin_map;
use work.stratixiigx_mac_bit_register;
use work.stratixiigx_mac_register;
ENTITY stratixiigx_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "stratixiigx_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiigx_mac_out;
ARCHITECTURE arch OF stratixiigx_mac_out IS
COMPONENT stratixiigx_mac_out_internal
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width-1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic);
END COMPONENT;
COMPONENT stratixiigx_mac_pin_map
GENERIC (
pinmap : string := "map";
data_width : integer := 144;
operation_mode : string := "output_only");
PORT (
datain : IN std_logic_vector(data_width-1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width-1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT stratixiigx_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixiigx_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataa_f : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL datac_f : std_logic_vector(datac_width-1 DOWNTO 0) := (others => '0');
SIGNAL signa_pipe : std_logic := '0';
SIGNAL signb_pipe : std_logic := '0';
SIGNAL multabsaturate_pipe : std_logic := '0';
SIGNAL multcdsaturate_pipe : std_logic := '0';
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL multabsaturate_out : std_logic := '0';
SIGNAL multcdsaturate_out : std_logic := '0';
SIGNAL addnsub0_pipe : std_logic := '0';
SIGNAL addnsub1_pipe : std_logic := '0';
SIGNAL addnsub0_out : std_logic := '0';
SIGNAL addnsub1_out : std_logic := '0';
SIGNAL zeroacc_pipe : std_logic := '0';
SIGNAL zeroacc1_pipe : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL zeroacc1_out : std_logic := '0';
SIGNAL dataout_feedback : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_map : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_mapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_unmapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_non_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic7 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_to_reg : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_reg : std_logic := '0';
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipe : std_logic := '0';
SIGNAL round1_pipe : std_logic := '0';
SIGNAL saturate_pipe : std_logic := '0';
SIGNAL saturate1_pipe : std_logic := '0';
SIGNAL mode0_pipe : std_logic := '0';
SIGNAL mode1_pipe : std_logic := '0';
SIGNAL round0_out : std_logic := '0';
SIGNAL round1_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL saturate1_out : std_logic := '0';
SIGNAL mode0_out : std_logic := '0';
SIGNAL mode1_out : std_logic := '0';
SIGNAL addnsub0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_zeroacc1 : std_logic := '0';
SIGNAL clear_zeroacc1 : std_logic := '0';
SIGNAL aclr_zeroacc1 : std_logic := '0';
SIGNAL ena_zeroacc1 : std_logic := '0';
SIGNAL async_zeroacc1 : std_logic := '0';
SIGNAL clk_addnsub0 : std_logic := '0';
SIGNAL clear_addnsub0 : std_logic := '0';
SIGNAL aclr_addnsub0 : std_logic := '0';
SIGNAL ena_addnsub0 : std_logic := '0';
SIGNAL async_addnsub0 : std_logic := '0';
SIGNAL clk_addnsub1 : std_logic := '0';
SIGNAL clear_addnsub1 : std_logic := '0';
SIGNAL aclr_addnsub1 : std_logic := '0';
SIGNAL ena_addnsub1 : std_logic := '0';
SIGNAL async_addnsub1 : std_logic := '0';
SIGNAL clk_round0 : std_logic := '0';
SIGNAL clear_round0 : std_logic := '0';
SIGNAL aclr_round0 : std_logic := '0';
SIGNAL ena_round0 : std_logic := '0';
SIGNAL async_round0 : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode0 : std_logic := '0';
SIGNAL clear_mode0 : std_logic := '0';
SIGNAL aclr_mode0 : std_logic := '0';
SIGNAL ena_mode0 : std_logic := '0';
SIGNAL async_mode0 : std_logic := '0';
SIGNAL clk_round1 : std_logic := '0';
SIGNAL clear_round1 : std_logic := '0';
SIGNAL aclr_round1 : std_logic := '0';
SIGNAL ena_round1 : std_logic := '0';
SIGNAL async_round1 : std_logic := '0';
SIGNAL clk_saturate1 : std_logic := '0';
SIGNAL clear_saturate1 : std_logic := '0';
SIGNAL aclr_saturate1 : std_logic := '0';
SIGNAL ena_saturate1 : std_logic := '0';
SIGNAL async_saturate1 : std_logic := '0';
SIGNAL clk_mode1 : std_logic := '0';
SIGNAL clear_mode1 : std_logic := '0';
SIGNAL aclr_mode1 : std_logic := '0';
SIGNAL ena_mode1 : std_logic := '0';
SIGNAL async_mode1 : std_logic := '0';
SIGNAL clk_multabsaturate : std_logic := '0';
SIGNAL clear_multabsaturate : std_logic := '0';
SIGNAL aclr_multabsaturate : std_logic := '0';
SIGNAL ena_multabsaturate : std_logic := '0';
SIGNAL async_multabsaturate : std_logic := '0';
SIGNAL clk_multcdsaturate : std_logic := '0';
SIGNAL clear_multcdsaturate : std_logic := '0';
SIGNAL aclr_multcdsaturate : std_logic := '0';
SIGNAL ena_multcdsaturate : std_logic := '0';
SIGNAL async_multcdsaturate : std_logic := '0';
SIGNAL clk_signa_pipeline : std_logic := '0';
SIGNAL clear_signa_pipeline : std_logic := '0';
SIGNAL aclr_signa_pipeline : std_logic := '0';
SIGNAL ena_signa_pipeline : std_logic := '0';
SIGNAL async_signa_pipeline : std_logic := '0';
SIGNAL clk_signb_pipeline : std_logic := '0';
SIGNAL clear_signb_pipeline : std_logic := '0';
SIGNAL aclr_signb_pipeline : std_logic := '0';
SIGNAL ena_signb_pipeline : std_logic := '0';
SIGNAL async_signb_pipeline : std_logic := '0';
SIGNAL clk_zeroacc_pipeline : std_logic := '0';
SIGNAL clear_zeroacc_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc_pipeline : std_logic := '0';
SIGNAL ena_zeroacc_pipeline : std_logic := '0';
SIGNAL async_zeroacc_pipeline : std_logic := '0';
SIGNAL clk_zeroacc1_pipeline : std_logic := '0';
SIGNAL clear_zeroacc1_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc1_pipeline : std_logic := '0';
SIGNAL ena_zeroacc1_pipeline : std_logic := '0';
SIGNAL async_zeroacc1_pipeline : std_logic := '0';
SIGNAL clk_addnsub0_pipeline : std_logic := '0';
SIGNAL clear_addnsub0_pipeline : std_logic := '0';
SIGNAL aclr_addnsub0_pipeline : std_logic := '0';
SIGNAL ena_addnsub0_pipeline : std_logic := '0';
SIGNAL async_addnsub0_pipeline : std_logic := '0';
SIGNAL clk_addnsub1_pipeline : std_logic := '0';
SIGNAL clear_addnsub1_pipeline : std_logic := '0';
SIGNAL aclr_addnsub1_pipeline : std_logic := '0';
SIGNAL ena_addnsub1_pipeline : std_logic := '0';
SIGNAL async_addnsub1_pipeline : std_logic := '0';
SIGNAL clk_round0_pipeline : std_logic := '0';
SIGNAL clear_round0_pipeline : std_logic := '0';
SIGNAL aclr_round0_pipeline : std_logic := '0';
SIGNAL ena_round0_pipeline : std_logic := '0';
SIGNAL async_round0_pipeline : std_logic := '0';
SIGNAL clk_saturate_pipeline : std_logic := '0';
SIGNAL clear_saturate_pipeline : std_logic := '0';
SIGNAL aclr_saturate_pipeline : std_logic := '0';
SIGNAL ena_saturate_pipeline : std_logic := '0';
SIGNAL async_saturate_pipeline : std_logic := '0';
SIGNAL clk_mode0_pipeline : std_logic := '0';
SIGNAL clear_mode0_pipeline : std_logic := '0';
SIGNAL aclr_mode0_pipeline : std_logic := '0';
SIGNAL ena_mode0_pipeline : std_logic := '0';
SIGNAL async_mode0_pipeline : std_logic := '0';
SIGNAL clk_round1_pipeline : std_logic := '0';
SIGNAL clear_round1_pipeline : std_logic := '0';
SIGNAL aclr_round1_pipeline : std_logic := '0';
SIGNAL ena_round1_pipeline : std_logic := '0';
SIGNAL async_round1_pipeline : std_logic := '0';
SIGNAL clk_saturate1_pipeline : std_logic := '0';
SIGNAL clear_saturate1_pipeline : std_logic := '0';
SIGNAL aclr_saturate1_pipeline : std_logic := '0';
SIGNAL ena_saturate1_pipeline : std_logic := '0';
SIGNAL async_saturate1_pipeline : std_logic := '0';
SIGNAL clk_mode1_pipeline : std_logic := '0';
SIGNAL clear_mode1_pipeline : std_logic := '0';
SIGNAL aclr_mode1_pipeline : std_logic := '0';
SIGNAL ena_mode1_pipeline : std_logic := '0';
SIGNAL async_mode1_pipeline : std_logic := '0';
SIGNAL clk_multabsaturate_pipeline : std_logic := '0';
SIGNAL clear_multabsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multabsaturate_pipeline : std_logic := '0';
SIGNAL ena_multabsaturate_pipeline : std_logic := '0';
SIGNAL async_multabsaturate_pipeline : std_logic := '0';
SIGNAL clk_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clear_multcdsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multcdsaturate_pipeline : std_logic := '0';
SIGNAL ena_multcdsaturate_pipeline : std_logic := '0';
SIGNAL async_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL clk_output1 : std_logic := '0';
SIGNAL clear_output1 : std_logic := '0';
SIGNAL aclr_output1 : std_logic := '0';
SIGNAL ena_output1 : std_logic := '0';
SIGNAL async_output1 : std_logic := '0';
SIGNAL clk_output2 : std_logic := '0';
SIGNAL clear_output2 : std_logic := '0';
SIGNAL aclr_output2 : std_logic := '0';
SIGNAL ena_output2 : std_logic := '0';
SIGNAL async_output2 : std_logic := '0';
SIGNAL clk_output3 : std_logic := '0';
SIGNAL clear_output3 : std_logic := '0';
SIGNAL aclr_output3 : std_logic := '0';
SIGNAL ena_output3 : std_logic := '0';
SIGNAL async_output3 : std_logic := '0';
SIGNAL clk_output4 : std_logic := '0';
SIGNAL clear_output4 : std_logic := '0';
SIGNAL aclr_output4 : std_logic := '0';
SIGNAL ena_output4 : std_logic := '0';
SIGNAL async_output4 : std_logic := '0';
SIGNAL clk_output5 : std_logic := '0';
SIGNAL clear_output5 : std_logic := '0';
SIGNAL aclr_output5 : std_logic := '0';
SIGNAL ena_output5 : std_logic := '0';
SIGNAL async_output5 : std_logic := '0';
SIGNAL clk_output6 : std_logic := '0';
SIGNAL clear_output6 : std_logic := '0';
SIGNAL aclr_output6 : std_logic := '0';
SIGNAL ena_output6 : std_logic := '0';
SIGNAL async_output6 : std_logic := '0';
SIGNAL clk_output7 : std_logic := '0';
SIGNAL clear_output7 : std_logic := '0';
SIGNAL aclr_output7 : std_logic := '0';
SIGNAL ena_output7 : std_logic := '0';
SIGNAL async_output7 : std_logic := '0';
SIGNAL tmp_186 : std_logic := '0';
SIGNAL tmp_189 : std_logic := '0';
SIGNAL accoverflow_tmp2 : std_logic := '0';
SIGNAL pin_map_addnsub : std_logic := '0';
BEGIN
dataout <= dataout_tmp(dataout'range);
accoverflow <= accoverflow_tmp2;
signa_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_pipe,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_pipe,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_pipe,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
zeroacc1_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1,
clk => clk_zeroacc1,
aclr => aclr_zeroacc1,
if_aclr => clear_zeroacc1,
ena => ena_zeroacc1,
dataout => zeroacc1_pipe,
async => async_zeroacc1);
async_zeroacc1 <= '1' WHEN (zeroacc1_clock = "none") ELSE '0' ;
clear_zeroacc1 <= '1' WHEN (zeroacc1_clear /= "none") ELSE '0' ;
clk_zeroacc1 <= '1' WHEN clk(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
aclr_zeroacc1 <= '1' WHEN (aclr(conv_integer(zeroacc1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1 <= '1' WHEN ena(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
zeroacc1_clk <= "0000" WHEN ((zeroacc1_clock = "0") OR (zeroacc1_clock = "none")) ELSE "0001" WHEN (zeroacc1_clock = "1") ELSE "0010" WHEN (zeroacc1_clock = "2") ELSE "0011" WHEN (zeroacc1_clock = "3") ELSE "0000" ;
zeroacc1_aclr <= "0000" WHEN ((zeroacc1_clear = "0") OR (zeroacc1_clear = "none")) ELSE "0001" WHEN (zeroacc1_clear = "1") ELSE "0010" WHEN (zeroacc1_clear = "2") ELSE "0011" WHEN (zeroacc1_clear = "3") ELSE "0000" ;
addnsub0_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
if_aclr => clear_addnsub0,
ena => ena_addnsub0,
dataout => addnsub0_pipe,
async => async_addnsub0);
async_addnsub0 <= '1' WHEN (addnsub0_clock = "none") ELSE '0' ;
clear_addnsub0 <= '1' WHEN (addnsub0_clear /= "none") ELSE '0' ;
clk_addnsub0 <= '1' WHEN clk(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
aclr_addnsub0 <= '1' WHEN (aclr(conv_integer(addnsub0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0 <= '1' WHEN ena(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
addnsub0_clk <= "0000" WHEN ((addnsub0_clock = "0") OR (addnsub0_clock = "none")) ELSE "0001" WHEN (addnsub0_clock = "1") ELSE "0010" WHEN (addnsub0_clock = "2") ELSE "0011" WHEN (addnsub0_clock = "3") ELSE "0000" ;
addnsub0_aclr <= "0000" WHEN ((addnsub0_clear = "0") OR (addnsub0_clear = "none")) ELSE "0001" WHEN (addnsub0_clear = "1") ELSE "0010" WHEN (addnsub0_clear = "2") ELSE "0011" WHEN (addnsub0_clear = "3") ELSE "0000" ;
addnsub1_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
if_aclr => clear_addnsub1,
ena => ena_addnsub1,
dataout => addnsub1_pipe,
async => async_addnsub1);
async_addnsub1 <= '1' WHEN (addnsub1_clock = "none") ELSE '0' ;
clear_addnsub1 <= '1' WHEN (addnsub1_clear /= "none") ELSE '0' ;
clk_addnsub1 <= '1' WHEN clk(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
aclr_addnsub1 <= '1' WHEN (aclr(conv_integer(addnsub1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1 <= '1' WHEN ena(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
addnsub1_clk <= "0000" WHEN ((addnsub1_clock = "0") OR (addnsub1_clock = "none")) ELSE "0001" WHEN (addnsub1_clock = "1") ELSE "0010" WHEN (addnsub1_clock = "2") ELSE "0011" WHEN (addnsub1_clock = "3") ELSE "0000" ;
addnsub1_aclr <= "0000" WHEN ((addnsub1_clear = "0") OR (addnsub1_clear = "none")) ELSE "0001" WHEN (addnsub1_clear = "1") ELSE "0010" WHEN (addnsub1_clear = "2") ELSE "0011" WHEN (addnsub1_clear = "3") ELSE "0000" ;
round0_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0,
clk => clk_round0,
aclr => aclr_round0,
if_aclr => clear_round0,
ena => ena_round0,
dataout => round0_pipe,
async => async_round0);
async_round0 <= '1' WHEN (round0_clock = "none") ELSE '0' ;
clear_round0 <= '1' WHEN (round0_clear /= "none") ELSE '0' ;
clk_round0 <= '1' WHEN clk(conv_integer(round0_clk)) = '1' ELSE '0' ;
aclr_round0 <= '1' WHEN (aclr(conv_integer(round0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0 <= '1' WHEN ena(conv_integer(round0_clk)) = '1' ELSE '0' ;
round0_clk <= "0000" WHEN ((round0_clock = "0") OR (round0_clock = "none")) ELSE "0001" WHEN (round0_clock = "1") ELSE "0010" WHEN (round0_clock = "2") ELSE "0011" WHEN (round0_clock = "3") ELSE "0000" ;
round0_aclr <= "0000" WHEN ((round0_clear = "0") OR (round0_clear = "none")) ELSE "0001" WHEN (round0_clear = "1") ELSE "0010" WHEN (round0_clear = "2") ELSE "0011" WHEN (round0_clear = "3") ELSE "0000" ;
saturate_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_pipe,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode0_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0,
clk => clk_mode0,
aclr => aclr_mode0,
if_aclr => clear_mode0,
ena => ena_mode0,
dataout => mode0_pipe,
async => async_mode0);
async_mode0 <= '1' WHEN (mode0_clock = "none") ELSE '0' ;
clear_mode0 <= '1' WHEN (mode0_clear /= "none") ELSE '0' ;
clk_mode0 <= '1' WHEN clk(conv_integer(mode0_clk)) = '1' ELSE '0' ;
aclr_mode0 <= '1' WHEN (aclr(conv_integer(mode0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0 <= '1' WHEN ena(conv_integer(mode0_clk)) = '1' ELSE '0' ;
mode0_clk <= "0000" WHEN ((mode0_clock = "0") OR (mode0_clock = "none")) ELSE "0001" WHEN (mode0_clock = "1") ELSE "0010" WHEN (mode0_clock = "2") ELSE "0011" WHEN (mode0_clock = "3") ELSE "0000" ;
mode0_aclr <= "0000" WHEN ((mode0_clear = "0") OR (mode0_clear = "none")) ELSE "0001" WHEN (mode0_clear = "1") ELSE "0010" WHEN (mode0_clear = "2") ELSE "0011" WHEN (mode0_clear = "3") ELSE "0000" ;
round1_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1,
clk => clk_round1,
aclr => aclr_round1,
if_aclr => clear_round1,
ena => ena_round1,
dataout => round1_pipe,
async => async_round1);
async_round1 <= '1' WHEN (round1_clock = "none") ELSE '0' ;
clear_round1 <= '1' WHEN (round1_clear /= "none") ELSE '0' ;
clk_round1 <= '1' WHEN clk(conv_integer(round1_clk)) = '1' ELSE '0' ;
aclr_round1 <= '1' WHEN (aclr(conv_integer(round1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1 <= '1' WHEN ena(conv_integer(round1_clk)) = '1' ELSE '0' ;
round1_clk <= "0000" WHEN ((round1_clock = "0") OR (round1_clock = "none")) ELSE "0001" WHEN (round1_clock = "1") ELSE "0010" WHEN (round1_clock = "2") ELSE "0011" WHEN (round1_clock = "3") ELSE "0000" ;
round1_aclr <= "0000" WHEN ((round1_clear = "0") OR (round1_clear = "none")) ELSE "0001" WHEN (round1_clear = "1") ELSE "0010" WHEN (round1_clear = "2") ELSE "0011" WHEN (round1_clear = "3") ELSE "0000" ;
saturate1_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1,
clk => clk_saturate1,
aclr => aclr_saturate1,
if_aclr => clear_saturate1,
ena => ena_saturate1,
dataout => saturate1_pipe,
async => async_saturate1);
async_saturate1 <= '1' WHEN (saturate1_clock = "none") ELSE '0' ;
clear_saturate1 <= '1' WHEN (saturate1_clear /= "none") ELSE '0' ;
clk_saturate1 <= '1' WHEN clk(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
aclr_saturate1 <= '1' WHEN (aclr(conv_integer(saturate1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1 <= '1' WHEN ena(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
saturate1_clk <= "0000" WHEN ((saturate1_clock = "0") OR (saturate1_clock = "none")) ELSE "0001" WHEN (saturate1_clock = "1") ELSE "0010" WHEN (saturate1_clock = "2") ELSE "0011" WHEN (saturate1_clock = "3") ELSE "0000" ;
saturate1_aclr <= "0000" WHEN ((saturate1_clear = "0") OR (saturate1_clear = "none")) ELSE "0001" WHEN (saturate1_clear = "1") ELSE "0010" WHEN (saturate1_clear = "2") ELSE "0011" WHEN (saturate1_clear = "3") ELSE "0000" ;
mode1_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1,
clk => clk_mode1,
aclr => aclr_mode1,
if_aclr => clear_mode1,
ena => ena_mode1,
dataout => mode1_pipe,
async => async_mode1);
async_mode1 <= '1' WHEN (mode1_clock = "none") ELSE '0' ;
clear_mode1 <= '1' WHEN (mode1_clear /= "none") ELSE '0' ;
clk_mode1 <= '1' WHEN clk(conv_integer(mode1_clk)) = '1' ELSE '0' ;
aclr_mode1 <= '1' WHEN (aclr(conv_integer(mode1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1 <= '1' WHEN ena(conv_integer(mode1_clk)) = '1' ELSE '0' ;
mode1_clk <= "0000" WHEN ((mode1_clock = "0") OR (mode1_clock = "none")) ELSE "0001" WHEN (mode1_clock = "1") ELSE "0010" WHEN (mode1_clock = "2") ELSE "0011" WHEN (mode1_clock = "3") ELSE "0000" ;
mode1_aclr <= "0000" WHEN ((mode1_clear = "0") OR (mode1_clear = "none")) ELSE "0001" WHEN (mode1_clear = "1") ELSE "0010" WHEN (mode1_clear = "2") ELSE "0011" WHEN (mode1_clear = "3") ELSE "0000" ;
multabsaturate_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate,
clk => clk_multabsaturate,
aclr => aclr_multabsaturate,
if_aclr => clear_multabsaturate,
ena => ena_multabsaturate,
dataout => multabsaturate_pipe,
async => async_multabsaturate);
async_multabsaturate <= '1' WHEN (multabsaturate_clock = "none") ELSE '0' ;
clear_multabsaturate <= '1' WHEN (multabsaturate_clear /= "none") ELSE '0' ;
clk_multabsaturate <= '1' WHEN clk(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
aclr_multabsaturate <= '1' WHEN (aclr(conv_integer(multabsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate <= '1' WHEN ena(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
multabsaturate_clk <= "0000" WHEN ((multabsaturate_clock = "0") OR (multabsaturate_clock = "none")) ELSE "0001" WHEN (multabsaturate_clock = "1") ELSE "0010" WHEN (multabsaturate_clock = "2") ELSE "0011" WHEN (multabsaturate_clock = "3") ELSE "0000" ;
multabsaturate_aclr <= "0000" WHEN ((multabsaturate_clear = "0") OR (multabsaturate_clear = "none")) ELSE "0001" WHEN (multabsaturate_clear = "1") ELSE "0010" WHEN (multabsaturate_clear = "2") ELSE "0011" WHEN (multabsaturate_clear = "3") ELSE "0000" ;
multcdsaturate_mac_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate,
clk => clk_multcdsaturate,
aclr => aclr_multcdsaturate,
if_aclr => clear_multcdsaturate,
ena => ena_multcdsaturate,
dataout => multcdsaturate_pipe,
async => async_multcdsaturate);
async_multcdsaturate <= '1' WHEN (multcdsaturate_clock = "none") ELSE '0' ;
clear_multcdsaturate <= '1' WHEN (multcdsaturate_clear /= "none") ELSE '0' ;
clk_multcdsaturate <= '1' WHEN clk(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate <= '1' WHEN (aclr(conv_integer(multcdsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate <= '1' WHEN ena(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
multcdsaturate_clk <= "0000" WHEN ((multcdsaturate_clock = "0") OR (multcdsaturate_clock = "none")) ELSE "0001" WHEN (multcdsaturate_clock = "1") ELSE "0010" WHEN (multcdsaturate_clock = "2") ELSE "0011" WHEN (multcdsaturate_clock = "3") ELSE "0000" ;
multcdsaturate_aclr <= "0000" WHEN ((multcdsaturate_clear = "0") OR (multcdsaturate_clear = "none")) ELSE "0001" WHEN (multcdsaturate_clear = "1") ELSE "0010" WHEN (multcdsaturate_clear = "2") ELSE "0011" WHEN (multcdsaturate_clear = "3") ELSE "0000" ;
signa_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
if_aclr => clear_signa_pipeline,
ena => ena_signa_pipeline,
dataout => signa_out,
async => async_signa_pipeline);
async_signa_pipeline <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0' ;
clear_signa_pipeline <= '1' WHEN (signa_pipeline_clear /= "none") ELSE '0' ;
clk_signa_pipeline <= '1' WHEN clk(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
aclr_signa_pipeline <= '1' WHEN (aclr(conv_integer(signa_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa_pipeline <= '1' WHEN ena(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
signa_pipeline_clk <= "0000" WHEN ((signa_pipeline_clock = "0") OR (signa_pipeline_clock = "none")) ELSE "0001" WHEN (signa_pipeline_clock = "1") ELSE "0010" WHEN (signa_pipeline_clock = "2") ELSE "0011" WHEN (signa_pipeline_clock = "3") ELSE "0000" ;
signa_pipeline_aclr <= "0000" WHEN ((signa_pipeline_clear = "0") OR (signa_pipeline_clear = "none")) ELSE "0001" WHEN (signa_pipeline_clear = "1") ELSE "0010" WHEN (signa_pipeline_clear = "2") ELSE "0011" WHEN (signa_pipeline_clear = "3") ELSE "0000" ;
signb_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
if_aclr => clear_signb_pipeline,
ena => ena_signb_pipeline,
dataout => signb_out,
async => async_signb_pipeline);
async_signb_pipeline <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0' ;
clear_signb_pipeline <= '1' WHEN (signb_pipeline_clear /= "none") ELSE '0' ;
clk_signb_pipeline <= '1' WHEN clk(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
aclr_signb_pipeline <= '1' WHEN (aclr(conv_integer(signb_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb_pipeline <= '1' WHEN ena(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
signb_pipeline_clk <= "0000" WHEN ((signb_pipeline_clock = "0") OR (signb_pipeline_clock = "none")) ELSE "0001" WHEN (signb_pipeline_clock = "1") ELSE "0010" WHEN (signb_pipeline_clock = "2") ELSE "0011" WHEN (signb_pipeline_clock = "3") ELSE "0000" ;
signb_pipeline_aclr <= "0000" WHEN ((signb_pipeline_clear = "0") OR (signb_pipeline_clear = "none")) ELSE "0001" WHEN (signb_pipeline_clear = "1") ELSE "0010" WHEN (signb_pipeline_clear = "2") ELSE "0011" WHEN (signb_pipeline_clear = "3") ELSE "0000" ;
zeroacc_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
if_aclr => clear_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
dataout => zeroacc_out,
async => async_zeroacc_pipeline);
async_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc_pipeline <= '1' WHEN clk(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc_pipeline <= '1' WHEN ena(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
zeroacc_pipeline_clk <= "0000" WHEN ((zeroacc_pipeline_clock = "0") OR (zeroacc_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc_pipeline_clock = "3") ELSE "0000" ;
zeroacc_pipeline_aclr <= "0000" WHEN ((zeroacc_pipeline_clear = "0") OR (zeroacc_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc_pipeline_clear = "3") ELSE "0000" ;
zeroacc1_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1_pipe,
clk => clk_zeroacc1_pipeline,
aclr => aclr_zeroacc1_pipeline,
if_aclr => clear_zeroacc1_pipeline,
ena => ena_zeroacc1_pipeline,
dataout => zeroacc1_out,
async => async_zeroacc1_pipeline);
async_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc1_pipeline <= '1' WHEN clk(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc1_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1_pipeline <= '1' WHEN ena(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
zeroacc1_pipeline_clk <= "0000" WHEN ((zeroacc1_pipeline_clock = "0") OR (zeroacc1_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clock = "3") ELSE "0000" ;
zeroacc1_pipeline_aclr <= "0000" WHEN ((zeroacc1_pipeline_clear = "0") OR (zeroacc1_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clear = "3") ELSE "0000" ;
addnsub0_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
if_aclr => clear_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
dataout => addnsub0_out,
async => async_addnsub0_pipeline);
async_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clock = "none") ELSE '0' ;
clear_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub0_pipeline <= '1' WHEN clk(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub0_pipeline <= '1' WHEN (aclr(conv_integer(addnsub0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0_pipeline <= '1' WHEN ena(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
addnsub0_pipeline_clk <= "0000" WHEN ((addnsub0_pipeline_clock = "0") OR (addnsub0_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clock = "1") ELSE "0010" WHEN (addnsub0_pipeline_clock = "2") ELSE "0011" WHEN (addnsub0_pipeline_clock = "3") ELSE "0000" ;
addnsub0_pipeline_aclr <= "0000" WHEN ((addnsub0_pipeline_clear = "0") OR (addnsub0_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clear = "1") ELSE "0010" WHEN (addnsub0_pipeline_clear = "2") ELSE "0011" WHEN (addnsub0_pipeline_clear = "3") ELSE "0000" ;
addnsub1_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
if_aclr => clear_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
dataout => addnsub1_out,
async => async_addnsub1_pipeline);
async_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clock = "none") ELSE '0' ;
clear_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub1_pipeline <= '1' WHEN clk(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub1_pipeline <= '1' WHEN (aclr(conv_integer(addnsub1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1_pipeline <= '1' WHEN ena(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
addnsub1_pipeline_clk <= "0000" WHEN ((addnsub1_pipeline_clock = "0") OR (addnsub1_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clock = "1") ELSE "0010" WHEN (addnsub1_pipeline_clock = "2") ELSE "0011" WHEN (addnsub1_pipeline_clock = "3") ELSE "0000" ;
addnsub1_pipeline_aclr <= "0000" WHEN ((addnsub1_pipeline_clear = "0") OR (addnsub1_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clear = "1") ELSE "0010" WHEN (addnsub1_pipeline_clear = "2") ELSE "0011" WHEN (addnsub1_pipeline_clear = "3") ELSE "0000" ;
round0_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0_pipe,
clk => clk_round0_pipeline,
aclr => aclr_round0_pipeline,
if_aclr => clear_round0_pipeline,
ena => ena_round0_pipeline,
dataout => round0_out,
async => async_round0_pipeline);
async_round0_pipeline <= '1' WHEN (round0_pipeline_clock = "none") ELSE '0' ;
clear_round0_pipeline <= '1' WHEN (round0_pipeline_clear /= "none") ELSE '0' ;
clk_round0_pipeline <= '1' WHEN clk(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
aclr_round0_pipeline <= '1' WHEN (aclr(conv_integer(round0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0_pipeline <= '1' WHEN ena(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
round0_pipeline_clk <= "0000" WHEN ((round0_pipeline_clock = "0") OR (round0_pipeline_clock = "none")) ELSE "0001" WHEN (round0_pipeline_clock = "1") ELSE "0010" WHEN (round0_pipeline_clock = "2") ELSE "0011" WHEN (round0_pipeline_clock = "3") ELSE "0000" ;
round0_pipeline_aclr <= "0000" WHEN ((round0_pipeline_clear = "0") OR (round0_pipeline_clear = "none")) ELSE "0001" WHEN (round0_pipeline_clear = "1") ELSE "0010" WHEN (round0_pipeline_clear = "2") ELSE "0011" WHEN (round0_pipeline_clear = "3") ELSE "0000" ;
saturate_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate_pipe,
clk => clk_saturate_pipeline,
aclr => aclr_saturate_pipeline,
if_aclr => clear_saturate_pipeline,
ena => ena_saturate_pipeline,
dataout => saturate_out,
async => async_saturate_pipeline);
async_saturate_pipeline <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0' ;
clear_saturate_pipeline <= '1' WHEN (saturate_pipeline_clear /= "none") ELSE '0' ;
clk_saturate_pipeline <= '1' WHEN clk(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate_pipeline <= '1' WHEN (aclr(conv_integer(saturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate_pipeline <= '1' WHEN ena(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
saturate_pipeline_clk <= "0000" WHEN ((saturate_pipeline_clock = "0") OR (saturate_pipeline_clock = "none")) ELSE "0001" WHEN (saturate_pipeline_clock = "1") ELSE "0010" WHEN (saturate_pipeline_clock = "2") ELSE "0011" WHEN (saturate_pipeline_clock = "3") ELSE "0000" ;
saturate_pipeline_aclr <= "0000" WHEN ((saturate_pipeline_clear = "0") OR (saturate_pipeline_clear = "none")) ELSE "0001" WHEN (saturate_pipeline_clear = "1") ELSE "0010" WHEN (saturate_pipeline_clear = "2") ELSE "0011" WHEN (saturate_pipeline_clear = "3") ELSE "0000" ;
mode0_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0_pipe,
clk => clk_mode0_pipeline,
aclr => aclr_mode0_pipeline,
if_aclr => clear_mode0_pipeline,
ena => ena_mode0_pipeline,
dataout => mode0_out,
async => async_mode0_pipeline);
async_mode0_pipeline <= '1' WHEN (mode0_pipeline_clock = "none") ELSE '0' ;
clear_mode0_pipeline <= '1' WHEN (mode0_pipeline_clear /= "none") ELSE '0' ;
clk_mode0_pipeline <= '1' WHEN clk(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode0_pipeline <= '1' WHEN (aclr(conv_integer(mode0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0_pipeline <= '1' WHEN ena(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
mode0_pipeline_clk <= "0000" WHEN ((mode0_pipeline_clock = "0") OR (mode0_pipeline_clock = "none")) ELSE "0001" WHEN (mode0_pipeline_clock = "1") ELSE "0010" WHEN (mode0_pipeline_clock = "2") ELSE "0011" WHEN (mode0_pipeline_clock = "3") ELSE "0000" ;
mode0_pipeline_aclr <= "0000" WHEN ((mode0_pipeline_clear = "0") OR (mode0_pipeline_clear = "none")) ELSE "0001" WHEN (mode0_pipeline_clear = "1") ELSE "0010" WHEN (mode0_pipeline_clear = "2") ELSE "0011" WHEN (mode0_pipeline_clear = "3") ELSE "0000" ;
round1_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1_pipe,
clk => clk_round1_pipeline,
aclr => aclr_round1_pipeline,
if_aclr => clear_round1_pipeline,
ena => ena_round1_pipeline,
dataout => round1_out,
async => async_round1_pipeline);
async_round1_pipeline <= '1' WHEN (round1_pipeline_clock = "none") ELSE '0' ;
clear_round1_pipeline <= '1' WHEN (round1_pipeline_clear /= "none") ELSE '0' ;
clk_round1_pipeline <= '1' WHEN clk(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
aclr_round1_pipeline <= '1' WHEN (aclr(conv_integer(round1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1_pipeline <= '1' WHEN ena(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
round1_pipeline_clk <= "0000" WHEN ((round1_pipeline_clock = "0") OR (round1_pipeline_clock = "none")) ELSE "0001" WHEN (round1_pipeline_clock = "1") ELSE "0010" WHEN (round1_pipeline_clock = "2") ELSE "0011" WHEN (round1_pipeline_clock = "3") ELSE "0000" ;
round1_pipeline_aclr <= "0000" WHEN ((round1_pipeline_clear = "0") OR (round1_pipeline_clear = "none")) ELSE "0001" WHEN (round1_pipeline_clear = "1") ELSE "0010" WHEN (round1_pipeline_clear = "2") ELSE "0011" WHEN (round1_pipeline_clear = "3") ELSE "0000" ;
saturate1_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1_pipe,
clk => clk_saturate1_pipeline,
aclr => aclr_saturate1_pipeline,
if_aclr => clear_saturate1_pipeline,
ena => ena_saturate1_pipeline,
dataout => saturate1_out,
async => async_saturate1_pipeline);
async_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clock = "none") ELSE '0' ;
clear_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clear /= "none") ELSE '0' ;
clk_saturate1_pipeline <= '1' WHEN clk(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate1_pipeline <= '1' WHEN (aclr(conv_integer(saturate1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1_pipeline <= '1' WHEN ena(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
saturate1_pipeline_clk <= "0000" WHEN ((saturate1_pipeline_clock = "0") OR (saturate1_pipeline_clock = "none")) ELSE "0001" WHEN (saturate1_pipeline_clock = "1") ELSE "0010" WHEN (saturate1_pipeline_clock = "2") ELSE "0011" WHEN (saturate1_pipeline_clock = "3") ELSE "0000" ;
saturate1_pipeline_aclr <= "0000" WHEN ((saturate1_pipeline_clear = "0") OR (saturate1_pipeline_clear = "none")) ELSE "0001" WHEN (saturate1_pipeline_clear = "1") ELSE "0010" WHEN (saturate1_pipeline_clear = "2") ELSE "0011" WHEN (saturate1_pipeline_clear = "3") ELSE "0000" ;
mode1_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1_pipe,
clk => clk_mode1_pipeline,
aclr => aclr_mode1_pipeline,
if_aclr => clear_mode1_pipeline,
ena => ena_mode1_pipeline,
dataout => mode1_out,
async => async_mode1_pipeline);
async_mode1_pipeline <= '1' WHEN (mode1_pipeline_clock = "none") ELSE '0' ;
clear_mode1_pipeline <= '1' WHEN (mode1_pipeline_clear /= "none") ELSE '0' ;
clk_mode1_pipeline <= '1' WHEN clk(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode1_pipeline <= '1' WHEN (aclr(conv_integer(mode1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1_pipeline <= '1' WHEN ena(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
mode1_pipeline_clk <= "0000" WHEN ((mode1_pipeline_clock = "0") OR (mode1_pipeline_clock = "none")) ELSE "0001" WHEN (mode1_pipeline_clock = "1") ELSE "0010" WHEN (mode1_pipeline_clock = "2") ELSE "0011" WHEN (mode1_pipeline_clock = "3") ELSE "0000" ;
mode1_pipeline_aclr <= "0000" WHEN ((mode1_pipeline_clear = "0") OR (mode1_pipeline_clear = "none")) ELSE "0001" WHEN (mode1_pipeline_clear = "1") ELSE "0010" WHEN (mode1_pipeline_clear = "2") ELSE "0011" WHEN (mode1_pipeline_clear = "3") ELSE "0000" ;
multabsaturate_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate_pipe,
clk => clk_multabsaturate_pipeline,
aclr => aclr_multabsaturate_pipeline,
if_aclr => clear_multabsaturate_pipeline,
ena => ena_multabsaturate_pipeline,
dataout => multabsaturate_out,
async => async_multabsaturate_pipeline);
async_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multabsaturate_pipeline <= '1' WHEN clk(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multabsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multabsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate_pipeline <= '1' WHEN ena(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
multabsaturate_pipeline_clk <= "0000" WHEN ((multabsaturate_pipeline_clock = "0") OR (multabsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clock = "3") ELSE "0000" ;
multabsaturate_pipeline_aclr <= "0000" WHEN ((multabsaturate_pipeline_clear = "0") OR (multabsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clear = "3") ELSE "0000" ;
multcdsaturate_mac_pipeline_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate_pipe,
clk => clk_multcdsaturate_pipeline,
aclr => aclr_multcdsaturate_pipeline,
if_aclr => clear_multcdsaturate_pipeline,
ena => ena_multcdsaturate_pipeline,
dataout => multcdsaturate_out,
async => async_multcdsaturate_pipeline);
async_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multcdsaturate_pipeline <= '1' WHEN clk(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multcdsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate_pipeline <= '1' WHEN ena(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
multcdsaturate_pipeline_clk <= "0000" WHEN ((multcdsaturate_pipeline_clock = "0") OR (multcdsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clock = "3") ELSE "0000" ;
multcdsaturate_pipeline_aclr <= "0000" WHEN ((multcdsaturate_pipeline_clear = "0") OR (multcdsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clear = "3") ELSE "0000" ;
dataa_f <= (others => '0') WHEN (dataa_forced_to_zero = "yes") ELSE dataa ;
datac_f <= (others => '0') WHEN (datac_forced_to_zero = "yes") ELSE datac ;
mac_adder : stratixiigx_mac_out_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
operation_mode => operation_mode)
PORT MAP (
dataa => dataa_f,
datab => datab,
datac => datac_f,
datad => datad,
mode0 => mode0_out,
mode1 => mode1_out,
zeroacc => zeroacc_out,
zeroacc1 => zeroacc1_out,
roundab => round0_out,
roundcd => round1_out,
saturateab => saturate_out,
saturatecd => saturate1_out,
multabsaturate => multabsaturate_out,
multcdsaturate => multcdsaturate_out,
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
feedback => dataout_feedback,
dataout => dataout_map(dataout_width -1 downto 0),
accoverflow => accoverflow_reg);
pin_map_addnsub <= addnsub0_out AND addnsub1_out;
mac_pin_map : stratixiigx_mac_pin_map
GENERIC MAP (
operation_mode => operation_mode,
data_width => tmp_width,
pinmap => "map")
PORT MAP (
datain => dataout_map,
operation => operation,
addnsub => pin_map_addnsub,
dataout => dataout_to_reg);
output0_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => dataout_width,
power_up => '0')
PORT MAP (
data => dataout_to_reg(dataout_width -1 DOWNTO 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_non_dynamic(dataout_width -1 DOWNTO 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
output1_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(35 DOWNTO 18),
clk => clk_output1,
aclr => aclr_output1,
if_aclr => clear_output1,
ena => ena_output1,
dataout => dataout_dynamic1(17 downto 0),
async => async_output1);
async_output1 <= '1' WHEN (output1_clock = "none") ELSE '0' ;
clear_output1 <= '1' WHEN (output1_clear /= "none") ELSE '0' ;
clk_output1 <= '1' WHEN clk(conv_integer(output1_clk)) = '1' ELSE '0' ;
aclr_output1 <= '1' WHEN (aclr(conv_integer(output1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output1 <= '1' WHEN ena(conv_integer(output1_clk)) = '1' ELSE '0' ;
output1_clk <= "0000" WHEN ((output1_clock = "0") OR (output1_clock = "none")) ELSE "0001" WHEN (output1_clock = "1") ELSE "0010" WHEN (output1_clock = "2") ELSE "0011" WHEN (output1_clock = "3") ELSE "0000" ;
output1_aclr <= "0000" WHEN ((output1_clear = "0") OR (output1_clear = "none")) ELSE "0001" WHEN (output1_clear = "1") ELSE "0010" WHEN (output1_clear = "2") ELSE "0011" WHEN (output1_clear = "3") ELSE "0000" ;
output2_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(53 DOWNTO 36),
clk => clk_output2,
aclr => aclr_output2,
if_aclr => clear_output2,
ena => ena_output2,
dataout => dataout_dynamic2(17 downto 0),
async => async_output2);
async_output2 <= '1' WHEN (output2_clock = "none") ELSE '0' ;
clear_output2 <= '1' WHEN (output2_clear /= "none") ELSE '0' ;
clk_output2 <= '1' WHEN clk(conv_integer(output2_clk)) = '1' ELSE '0' ;
aclr_output2 <= '1' WHEN (aclr(conv_integer(output2_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output2 <= '1' WHEN ena(conv_integer(output2_clk)) = '1' ELSE '0' ;
output2_clk <= "0000" WHEN ((output2_clock = "0") OR (output2_clock = "none")) ELSE "0001" WHEN (output2_clock = "1") ELSE "0010" WHEN (output2_clock = "2") ELSE "0011" WHEN (output2_clock = "3") ELSE "0000" ;
output2_aclr <= "0000" WHEN ((output2_clear = "0") OR (output2_clear = "none")) ELSE "0001" WHEN (output2_clear = "1") ELSE "0010" WHEN (output2_clear = "2") ELSE "0011" WHEN (output2_clear = "3") ELSE "0000" ;
output3_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(71 DOWNTO 54),
clk => clk_output3,
aclr => aclr_output3,
if_aclr => clear_output3,
ena => ena_output3,
dataout => dataout_dynamic3(17 downto 0),
async => async_output3);
async_output3 <= '1' WHEN (output3_clock = "none") ELSE '0' ;
clear_output3 <= '1' WHEN (output3_clear /= "none") ELSE '0' ;
clk_output3 <= '1' WHEN clk(conv_integer(output3_clk)) = '1' ELSE '0' ;
aclr_output3 <= '1' WHEN (aclr(conv_integer(output3_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output3 <= '1' WHEN ena(conv_integer(output3_clk)) = '1' ELSE '0' ;
output3_clk <= "0000" WHEN ((output3_clock = "0") OR (output3_clock = "none")) ELSE "0001" WHEN (output3_clock = "1") ELSE "0010" WHEN (output3_clock = "2") ELSE "0011" WHEN (output3_clock = "3") ELSE "0000" ;
output3_aclr <= "0000" WHEN ((output3_clear = "0") OR (output3_clear = "none")) ELSE "0001" WHEN (output3_clear = "1") ELSE "0010" WHEN (output3_clear = "2") ELSE "0011" WHEN (output3_clear = "3") ELSE "0000" ;
output4_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(89 DOWNTO 72),
clk => clk_output4,
aclr => aclr_output4,
if_aclr => clear_output4,
ena => ena_output4,
dataout => dataout_dynamic4(17 downto 0),
async => async_output4);
async_output4 <= '1' WHEN (output4_clock = "none") ELSE '0' ;
clear_output4 <= '1' WHEN (output4_clear /= "none") ELSE '0' ;
clk_output4 <= '1' WHEN clk(conv_integer(output4_clk)) = '1' ELSE '0' ;
aclr_output4 <= '1' WHEN (aclr(conv_integer(output4_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output4 <= '1' WHEN ena(conv_integer(output4_clk)) = '1' ELSE '0' ;
output4_clk <= "0000" WHEN ((output4_clock = "0") OR (output4_clock = "none")) ELSE "0001" WHEN (output4_clock = "1") ELSE "0010" WHEN (output4_clock = "2") ELSE "0011" WHEN (output4_clock = "3") ELSE "0000" ;
output4_aclr <= "0000" WHEN ((output4_clear = "0") OR (output4_clear = "none")) ELSE "0001" WHEN (output4_clear = "1") ELSE "0010" WHEN (output4_clear = "2") ELSE "0011" WHEN (output4_clear = "3") ELSE "0000" ;
output5_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(107 DOWNTO 90),
clk => clk_output5,
aclr => aclr_output5,
if_aclr => clear_output5,
ena => ena_output5,
dataout => dataout_dynamic5(17 downto 0),
async => async_output5);
async_output5 <= '1' WHEN (output5_clock = "none") ELSE '0' ;
clear_output5 <= '1' WHEN (output5_clear /= "none") ELSE '0' ;
clk_output5 <= '1' WHEN clk(conv_integer(output5_clk)) = '1' ELSE '0' ;
aclr_output5 <= '1' WHEN (aclr(conv_integer(output5_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output5 <= '1' WHEN ena(conv_integer(output5_clk)) = '1' ELSE '0' ;
output5_clk <= "0000" WHEN ((output5_clock = "0") OR (output5_clock = "none")) ELSE "0001" WHEN (output5_clock = "1") ELSE "0010" WHEN (output5_clock = "2") ELSE "0011" WHEN (output5_clock = "3") ELSE "0000" ;
output5_aclr <= "0000" WHEN ((output5_clear = "0") OR (output5_clear = "none")) ELSE "0001" WHEN (output5_clear = "1") ELSE "0010" WHEN (output5_clear = "2") ELSE "0011" WHEN (output5_clear = "3") ELSE "0000" ;
output6_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(125 DOWNTO 108),
clk => clk_output6,
aclr => aclr_output6,
if_aclr => clear_output6,
ena => ena_output6,
dataout => dataout_dynamic6(17 downto 0),
async => async_output6);
async_output6 <= '1' WHEN (output6_clock = "none") ELSE '0' ;
clear_output6 <= '1' WHEN (output6_clear /= "none") ELSE '0' ;
clk_output6 <= '1' WHEN clk(conv_integer(output6_clk)) = '1' ELSE '0' ;
aclr_output6 <= '1' WHEN (aclr(conv_integer(output6_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output6 <= '1' WHEN ena(conv_integer(output6_clk)) = '1' ELSE '0' ;
output6_clk <= "0000" WHEN ((output6_clock = "0") OR (output6_clock = "none")) ELSE "0001" WHEN (output6_clock = "1") ELSE "0010" WHEN (output6_clock = "2") ELSE "0011" WHEN (output6_clock = "3") ELSE "0000" ;
output6_aclr <= "0000" WHEN ((output6_clear = "0") OR (output6_clear = "none")) ELSE "0001" WHEN (output6_clear = "1") ELSE "0010" WHEN (output6_clear = "2") ELSE "0011" WHEN (output6_clear = "3") ELSE "0000" ;
output7_reg : stratixiigx_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(tmp_width-1 DOWNTO 126),
clk => clk_output7,
aclr => aclr_output7,
if_aclr => clear_output7,
ena => ena_output7,
dataout => dataout_dynamic7(17 downto 0),
async => async_output7);
async_output7 <= '1' WHEN (output7_clock = "none") ELSE '0' ;
clear_output7 <= '1' WHEN (output7_clear /= "none") ELSE '0' ;
clk_output7 <= '1' WHEN clk(conv_integer(output7_clk)) = '1' ELSE '0' ;
aclr_output7 <= '1' WHEN (aclr(conv_integer(output7_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output7 <= '1' WHEN ena(conv_integer(output7_clk)) = '1' ELSE '0' ;
output7_clk <= "0000" WHEN ((output7_clock = "0") OR (output7_clock = "none")) ELSE "0001" WHEN (output7_clock = "1") ELSE "0010" WHEN (output7_clock = "2") ELSE "0011" WHEN (output7_clock = "3") ELSE "0000" ;
output7_aclr <= "0000" WHEN ((output7_clear = "0") OR (output7_clear = "none")) ELSE "0001" WHEN (output7_clear = "1") ELSE "0010" WHEN (output7_clear = "2") ELSE "0011" WHEN (output7_clear = "3") ELSE "0000" ;
tmp_186 <= '1' when (output_clear /= "none") else '0';
tmp_189 <= '1' when (output_clock = "none") else '0';
accoverflow_out_reg : stratixiigx_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => accoverflow_reg,
clk => clk_output,
aclr => aclr_output,
if_aclr => tmp_186,
ena => ena_output,
dataout => accoverflow_tmp,
async => tmp_189);
dataout_dynamic(tmp_width-1 DOWNTO 0) <= dataout_dynamic7(17 DOWNTO 0) & dataout_dynamic6(17 DOWNTO 0) & dataout_dynamic5(17 DOWNTO 0) & dataout_dynamic4(17 DOWNTO 0) & dataout_dynamic3(17 DOWNTO 0) & dataout_dynamic2(17 DOWNTO 0) & dataout_dynamic1(17 DOWNTO 0) & dataout_non_dynamic(17 DOWNTO 0) ;
dataout_tmp <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '0')) AND (zeroacc1_out = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '1')) AND (zeroacc1_out = '1')) ELSE "0000" ;
dataout_feedback <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
accoverflow_tmp2 <= accoverflow_tmp;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_lvds_tx_reg : ENTITY is TRUE;
END stratixiigx_lvds_tx_reg;
ARCHITECTURE vital_stratixiigx_lvds_tx_reg of stratixiigx_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_stratixiigx_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiigx_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiigx_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiigx_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the StratixIIGX
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE std.textio.all;
ENTITY stratixiigx_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixiigx_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixiigx_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiigx_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiigx_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE std.textio.all;
ENTITY stratixiigx_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixiigx_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixiigx_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiigx_lvds_transmitter
--
-- Description : Timing simulation model for the StratixIIGX LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) StratixIIGX_lvds_tx_parallel_register and
-- 3) StratixIIGX_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE std.textio.all;
USE work.stratixiigx_lvds_tx_parallel_register;
USE work.stratixiigx_lvds_tx_out_block;
USE work.stratixiigx_lvds_tx_reg;
ENTITY stratixiigx_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiigx_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixiigx_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixiigx_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixiigx_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixiigx_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixiigx_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixiigx_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixiigx_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixiigx_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixiigx_lvds_reg;
ARCHITECTURE vital_stratixiigx_lvds_reg of stratixiigx_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiigx_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiigx_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiigx_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE work.stratixiigx_lvds_rx_fifo_sync_ram;
ENTITY stratixiigx_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiigx_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiigx_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixiigx_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixiigx_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE work.stratixiigx_lvds_reg;
ENTITY stratixiigx_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixiigx_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiigx_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixiigx_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixiigx_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Bit Slip shift register
-- process (clk0_in, bsliprst_in)
-- begin
-- if (bsliprst_in = '1') then
-- elsif (clk0_in'event and clk0_in = '1' and clk0'last_value = '0') then
-- bitslip_arr(0) <= datain_in;
-- for i in 0 to (bitslip_rollover - 1) loop
-- bitslip_arr(i + 1) <= bitslip_arr(i);
-- end loop;
--
-- if (start_corrupt_bits = '1') then
-- num_corrupt_bits <= num_corrupt_bits + 1;
-- end if;
-- if (num_corrupt_bits+1 = 3) then
-- start_corrupt_bits <= '0';
-- end if;
-- end if;
-- end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixiigx_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_rx_deser
--
-- Description : Timing simulation model for the STRATIXIIGX LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiigx_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiigx_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiigx_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the STRATIXIIGX LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiigx_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiigx_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : STRATIXIIGX_LVDS_RECEIVER
--
-- Description : Timing simulation model for the STRATIXIIGX LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixiigx_lvds_rx_fifo
-- 2) stratixiigx_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixiigx_lvds_rx_parallel_reg
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiigx_atom_pack.all;
USE work.stratixiigx_lvds_rx_bitslip;
USE work.stratixiigx_lvds_rx_fifo;
USE work.stratixiigx_lvds_rx_deser;
USE work.stratixiigx_lvds_rx_parallel_reg;
USE work.stratixiigx_lvds_reg;
ENTITY stratixiigx_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixiigx_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiigx_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixiigx_lvds_receiver IS
COMPONENT stratixiigx_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiigx_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiigx_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiigx_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiigx_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal first_dpa_lock : std_logic;
signal loadreg_datain : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_int : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal clk0_dly : std_logic;
signal datain_tmp : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
-- INTERNAL PARAMETERS
CONSTANT DPA_CYCLES_TO_LOCK : integer := 2;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpareg1_out WHEN (enable_dpa = "on") ELSE gnd ;
reset_int <= (NOT devpor) OR (NOT devclrn) ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpareset_ipd OR reset_fifo ;
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_dly <= clk0_ipd;
xhdl_12 <= devclrn OR devpor;
-- SUB-MODULE INSTANTIATION
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixiigx_lvds_reg
PORT MAP ( d => in_reg_data,
clk => clk0_dly,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
datain_reg_tmp <= datain_reg;
dpa_clk <= clk0_ipd when (enable_dpa = "on") else '0' ;
dpa_rst <= dpareset_ipd when (enable_dpa = "on") else '0' ;
process (dpa_clk, dpa_rst)
variable dpa_lock_count : integer := 0;
variable dparst_msg : boolean := false;
variable dpa_is_locked : std_logic := '0';
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
if (enable_dpa = "on") then
ASSERT false report "DPA Phase tracking is not modeled, and once locked, DPA will continue to lock until the next reset is asserted. Please refer to the StratixIIGX device handbook for further details." severity warning;
end if;
initial := false;
end if;
if (dpa_rst = '1') then
dpa_is_locked := '0';
dpa_lock_count := 0;
if (not dparst_msg) then
ASSERT false report "DPA was reset" severity note;
dparst_msg := true;
end if;
elsif (dpa_clk'event and dpa_clk = '1') then
dparst_msg := false;
if (dpa_is_locked = '0') then
dpa_lock_count := dpa_lock_count + 1;
if (dpa_lock_count > DPA_CYCLES_TO_LOCK) then
dpa_is_locked := '1';
ASSERT false report "DPA locked" severity note;
reset_fifo <= '0';
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- ?????????? insert delay to mimic DPLL dataout ?????????
-- DPA registers
dpareg0 : stratixiigx_lvds_reg
PORT MAP ( d => in_reg_data,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixiigx_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
s_fifo : stratixiigx_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => fifo_wclk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= slip_datain_tmp;
s_bitslip_clk <= clk0_dly;
s_bslip : stratixiigx_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
--********* DESERIALISER *********//
loaden <= enable0_ipd;
-- only 1 enable signal used for StratixIIGX
rxload_reg : stratixiigx_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
s_deser : stratixiigx_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixiigx_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
postdpaserialdataout <= dpareg1_out ;
serialdataout <= datain_ipd;
END vital_arm_lvds_receiver;
-------------------------------------------------------------------------------
--
-- Entity Name : StratixIIGX_dll
--
-- Outputs : delayctrlout - current delay chain settings for DQS pin
-- offsetctrlout - current delay offset setting
-- dqsupdate - update enable signal for delay setting latces
-- upndnout - raw output of the phase comparator
--
-- Inputs : clk - reference clock matching in frequency to DQS clock
-- aload - asychronous load signal for delay setting counter
-- when asserted, counter is loaded with initial value
-- offset - offset added/subtracted from delayctrlout
-- upndnin - up/down input port for delay setting counter in
-- use_updndnin mode (user control mode)
-- upndninclkena - clock enable for the delaying setting counter
-- addnsub - dynamically control +/- on offsetctrlout
--
-- Formulae : delay (input_period) = sim_loop_intrinsic_delay +
-- sim_loop_delay_increment * dllcounter;
--
-- Latency : 3 (clk8 cycles) = pc + dc + dr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
USE work.stratixiigx_pllpack.all;
ENTITY stratixiigx_dll is
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixiigx_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiigx_dll;
ARCHITECTURE vital_armdll of stratixiigx_dll is
-- tuncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal addnsub_in : std_logic := '0';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal dqsupdate_out : std_logic := '1';
signal upndn_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_offsetctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_offset : integer := 0;
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : integer := 0;
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_int : integer := 0;
signal dr_offset_in : integer := 0;
signal dr_dllcount_in : integer := 0;
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_offset : integer := 0;
signal dr_reg_dllcount : integer := 0;
signal dr_delayctrl_out_tmp : integer := 0;
-- delay chain setting counter
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_offset <= dqs_str2int(static_offset);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "offset_only" ELSE "10" WHEN delayctrlout_mode="normal_offset" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
para_offsetctrlout_mode <= "11" WHEN offsetctrlout_mode = "dynamic_addnsub" ELSE "10" WHEN offsetctrlout_mode = "dynamic_sub" ELSE "01" WHEN offsetctrlout_mode = "dynamic_add" ELSE "00";
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetctrl_out <= dr_offsetctrl_out;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_offset_in <= (64 - alt_conv_integer(offset_in)) WHEN ((offset_in /= "000000") AND ((offsetctrlout_mode = "dynamic_addnsub" AND addnsub_in = '0') or (offsetctrlout_mode = "dynamic_sub"))) ELSE
alt_conv_integer(offset_in);
dr_dllcount_in <= dc_dllcount_out;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in;
-- outputs
dr_delayctrl_out <= dll_unsigned2bin(dr_delayctrl_out_tmp);
dr_offsetctrl_out <= dll_unsigned2bin(dr_reg_offset);
dr_delayctrl_out_tmp <= dr_offset_in WHEN (delayctrlout_mode = "offset_only") ELSE
dr_reg_offset WHEN (delayctrlout_mode = "normal_offset") ELSE
dr_reg_dllcount;
dr_delayctrl_int <= para_static_delay_ctrl WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
dr_offsetctrl_int <= para_static_offset WHEN (offsetctrlout_mode = "static") ELSE
dr_offset_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= 0;
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= 0;
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (offsetctrlout_mode = "dynamic_addnsub") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
end if;
elsif (offsetctrlout_mode = "dynamic_sub") then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
elsif (offsetctrlout_mode = "dynamic_add") then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (offsetctrlout_mode = "static") then
if (para_static_offset >= 0) then
if ((para_static_offset < 64) AND (para_static_offset < 64 - dr_delayctrl_int)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 64;
end if;
else
if ((para_static_offset > -63) AND (dr_delayctrl_int > (-1)*para_static_offset)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 0;
end if;
end if;
else
dr_reg_offset <= 14; -- error
end if; -- modes
end if; -- rising clock
end process ; -- generating dr_reg_offset
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount;
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := sim_loop_intrinsic_delay + sim_loop_delay_increment * pc_dllcount_in;
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
pc_delay <= pc_var_delay;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, upndn_in, upndninclkena_in, addnsub_in,
delayctrl_out, offsetctrl_out, dqsupdate_out, upndn_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/SRRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIIGX_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIIGX_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIIGX_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetctrlout <= offsetctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_armdll;
--
--
-- STRATIXIIGX_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixiigx_atom_pack.all;
entity stratixiigx_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiigx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end stratixiigx_rublock;
architecture architecture_rublock of stratixiigx_rublock is
signal update_reg : std_logic_vector(20 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(25 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is output of shift-reg bit 0
-- note that in Stratix, there is an inverter to regout.
-- but in Stratix II, there is no inverter.
regout <= shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(20 downto 9) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(8) <= '1';
else
update_reg(8) <= '0';
end if;
-- PGM[] field
update_reg(7 downto 1) <= conv_std_logic_vector(sim_init_page_select, 7);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1]);
--report " -> Field User Watchdog is set to %s", update_reg[8] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 24 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(25) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and
(operation_mode = "remote" or operation_mode = "active_serial_remote")) then
-- every bit in Update Reg gets updated
update_reg(20 downto 0) <= shift_reg(25 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[12:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[13] == 1) ? "Enableds" : (shift_reg[13] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[25:14];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
elsif (operation_mode = "remote") then
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
else
pgmout_update <= (others => 'X');
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1];
--report " -> Field User Watchdog is set to %s", (update_reg[8] == 1) ? "Enabled" : (update_reg[8] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiigx_termination
--
-- Outputs : incrup and incrdn - output of voltage comparator
-- terminationcontrol - to I/O, cannot wired to PLD
-- terminationcontrolprobe - internal testing outputs only
--
-- Descriptions : the Atom represent On Chip Termination calibration block.
-- The block has no digital outputs that can be observed in PLD.
-- Therefore we do not have simulation model other than entity
-- declaration.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_termination is
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixiigx_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END stratixiigx_termination;
ARCHITECTURE vital_armtermination of stratixiigx_termination is
begin
--------------------
-- INPUT PATH DELAYS
--------------------
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
end vital_armtermination;
---------------------------------------------------------------------
--
-- Entity Name : stratixiigx_routing_wire
--
-- Description : StratixIIGX Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiigx_atom_pack.all;
ENTITY stratixiigx_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiigx_routing_wire : entity is TRUE;
end stratixiigx_routing_wire;
ARCHITECTURE behave of stratixiigx_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| gpl-3.0 | 83465ad4dfab847f41284b2f4f3b00af | 0.496318 | 3.869267 | false | false | false | false |
thoralt/KCVGA | FPGA/VGA_OUTPUT.vhd | 1 | 5,151 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED."+";
USE IEEE.STD_LOGIC_UNSIGNED."-";
USE IEEE.STD_LOGIC_UNSIGNED."=";
ENTITY VGA_OUTPUT IS GENERIC
(
-- 1280, 1328, 1440, 1688
H_PIXELS, H_SYNC_START, H_SYNC_END, H_TOTAL,
V_PIXELS, V_SYNC_START, V_SYNC_END, V_TOTAL
-- H_PIXELS, H_FRONT_PORCH, H_SYNC_PULSE, H_BACK_PORCH,
-- V_PIXELS, V_FRONT_PORCH, V_SYNC_PULSE, V_BACK_PORCH
: NATURAL;
H_SYNC_POLARITY, V_SYNC_POLARITY : STD_LOGIC
);
PORT
(
CLK : IN STD_LOGIC;
HSYNC : OUT STD_LOGIC;
VSYNC : OUT STD_LOGIC;
R, G, B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
nRESET : IN STD_LOGIC;
SCANLINES : IN STD_LOGIC;
FRAMESYNC : OUT STD_LOGIC;
FIFO_RD : OUT STD_LOGIC;
VGA_ADDR_WR : OUT STD_LOGIC;
VGA_FIFO_EMPTY : IN STD_LOGIC;
VGA_ADDR : OUT STD_LOGIC_VECTOR(16 DOWNTO 0);
DATA_IN : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END VGA_OUTPUT;
ARCHITECTURE Behavioral OF VGA_OUTPUT IS
-- video timing constants, do not change
CONSTANT H_ACTIVE_BEGIN : INTEGER := H_TOTAL - H_SYNC_START;
CONSTANT H_ACTIVE_END : INTEGER := H_ACTIVE_BEGIN + H_PIXELS;
CONSTANT V_ACTIVE_BEGIN : INTEGER := V_TOTAL - V_SYNC_START;
CONSTANT V_ACTIVE_END : INTEGER := V_ACTIVE_BEGIN + V_PIXELS;
-- horizontal and vertical position counters
SIGNAL HPOS : INTEGER RANGE 0 TO H_TOTAL - 1 := 0;
SIGNAL VPOS : INTEGER RANGE 0 TO V_TOTAL - 1 := 0;
SIGNAL PIXEL_MULTIPLIER : INTEGER RANGE 0 TO 3 := 0;
SIGNAL LINE_MULTIPLIER : INTEGER RANGE 0 TO 3 := 0;
SIGNAL ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0); -- current VRAM address
SIGNAL PIXEL : STD_LOGIC_VECTOR(4 DOWNTO 0); -- latest pixel data from VRAM
BEGIN
-- the ColorGenerator combinatorial network connects the 5 bit color
-- vector from SRAM to the R, G, and B outputs (4 bits each)
i_ColorGenerator : ENTITY work.ColorGenerator PORT MAP
(PIXEL, R, G, B);
i_SyncGenerator : ENTITY work.SyncGenerator GENERIC
MAP(
H_TOTAL, V_TOTAL, V_ACTIVE_END, H_SYNC_END - H_SYNC_START,
V_SYNC_END - V_SYNC_START, H_SYNC_POLARITY, V_SYNC_POLARITY
) PORT
MAP(HPOS, VPOS, HSYNC, VSYNC, FRAMESYNC);
PROCESS (CLK, nRESET)
BEGIN
IF nRESET = '0' THEN
VPOS <= 0;
HPOS <= 0;
VGA_ADDR_WR <= '0';
FIFO_RD <= '0';
ELSIF rising_edge(clk) THEN
VGA_ADDR_WR <= '0';
FIFO_RD <= '0';
-- If at beginning of line: Set new address -> starts filling FIFO
IF HPOS = 0 THEN
PIXEL_MULTIPLIER <= 0;
VGA_ADDR <= ADDR;
VGA_ADDR_WR <= '1';
END IF;
-- request first data word
IF HPOS = H_ACTIVE_BEGIN - 3 THEN
FIFO_RD <= '1';
END IF;
-- read first data word
IF HPOS = H_ACTIVE_BEGIN - 1 THEN
PIXEL <= DATA_IN;
END IF;
-- are we inside the active video region?
IF HPOS >= H_ACTIVE_BEGIN AND HPOS < H_ACTIVE_END
AND VPOS >= V_ACTIVE_BEGIN AND VPOS < V_ACTIVE_END THEN
IF PIXEL_MULTIPLIER = 0 THEN
PIXEL_MULTIPLIER <= 1;
ELSIF PIXEL_MULTIPLIER = 1 THEN
FIFO_RD <= '1';
PIXEL_MULTIPLIER <= 2;
ELSIF PIXEL_MULTIPLIER = 2 THEN
PIXEL_MULTIPLIER <= 3;
ELSIF PIXEL_MULTIPLIER = 3 THEN
PIXEL <= DATA_IN;
PIXEL_MULTIPLIER <= 0;
END IF;
ELSE
-- blanking during front porch, sync pulse and back porch
PIXEL <= (OTHERS => '0');
END IF;
IF HPOS = H_ACTIVE_END THEN
IF LINE_MULTIPLIER = 0 THEN
LINE_MULTIPLIER <= 1;
ELSIF LINE_MULTIPLIER = 1 THEN
LINE_MULTIPLIER <= 2;
ELSIF LINE_MULTIPLIER = 2 THEN
LINE_MULTIPLIER <= 3;
ELSIF LINE_MULTIPLIER = 3 THEN
ADDR <= ADDR + 107;
LINE_MULTIPLIER <= 0;
END IF;
END IF;
-- update horizontal and vertical position counters
IF HPOS < H_TOTAL - 1 THEN
HPOS <= HPOS + 1;
ELSE
-- end of line
HPOS <= 0;
-- increment line counter
IF VPOS < V_TOTAL - 1 THEN
VPOS <= VPOS + 1;
ELSE
-- end of frame
VPOS <= 0;
LINE_MULTIPLIER <= 0;
ADDR <= (OTHERS => '0');
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;
| mit | 57a49e0615c60ff0ce43adc687d230cf | 0.491749 | 4.160743 | false | false | false | false |
keith-epidev/md2x | build/code/keyboard2.vhdl | 1 | 2,163 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY keyboard2 IS
PORT( keyboard_clk, keyboard_data, clock_25Mhz ,reset, reads : IN STD_LOGIC;
scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
scan_ready : OUT STD_LOGIC
);
END keyboard2;
ARCHITECTURE a OF keyboard2 IS
SIGNAL INCNT: STD_LOGIC_VECTOR( 3 DOWNTO 0 );
SIGNAL SHIFTIN: STD_LOGIC_VECTOR( 8 DOWNTO 0 );
SIGNAL READ_CHAR : STD_LOGIC;
SIGNAL INFLAG, ready_set : STD_LOGIC;
SIGNAL keyboard_clk_filtered : STD_LOGIC;
SIGNAL filter: STD_LOGIC_VECTOR( 7 DOWNTO 0 );
signal scanready: std_logic;
BEGIN
--PROCESS ( reads, ready_set )
-- BEGIN
-- IF (reads = '1' ) THEN
-- scanready <= '0';
-- ELSIF (ready_set'EVENT AND ready_set = '1') THEN
-- scanready <= '1';
-- END IF;
--END PROCESS;
scan_ready <= scanready;
Clock_filter: PROCESS ( clock_25Mhz) BEGIN
IF( clock_25Mhz'EVENT AND clock_25Mhz = '1')then
filter ( 6 DOWNTO 0 ) <= filter( 7 DOWNTO 1 ) ;
filter( 7 ) <= keyboard_clk;
IF filter = "11111111" THEN
keyboard_clk_filtered <= '1';
ELSIF filter = "00000000" THEN
keyboard_clk_filtered <= '0';
END IF;
END IF;
END PROCESS Clock_filter;
keys : PROCESS (KEYBOARD_CLK_filtered) BEGIN
IF(KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered = '1')then
IF RESET = '1' THEN
INCNT <= "0000";
READ_CHAR <= '0';
else
IF KEYBOARD_DATA = '0' AND READ_CHAR = '0' THEN
READ_CHAR <= '1';
ready_set <= '0';
ELSE
-- Shift in next 8 data bits to assemble a scan code
IF READ_CHAR = '1' THEN
IF INCNT < "1001" THEN
INCNT <= INCNT + 1 ;
SHIFTIN( 7 DOWNTO 0 ) <= SHIFTIN( 8 DOWNTO 1 );
SHIFTIN( 8 ) <= KEYBOARD_DATA;
ready_set <= '0';
-- End of scan code character, so set flags and exit loop
ELSE
scan_code <= SHIFTIN( 7 DOWNTO 0 );
READ_CHAR <='0';
ready_set <= '1';
scanready <= '1';
INCNT <= "0000";
END IF;
END IF;
END IF;
END IF;
if(scanready = '1')then
scanready <= '0';
end if;
END IF;
END PROCESS keys;
END a;
| gpl-2.0 | 2385a1828973d6eb45cd34577bfe780d | 0.604253 | 2.934871 | false | false | false | false |
thoralt/KCVGA | FPGA/KCVGA.vhd | 1 | 10,612 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY KCVGA IS PORT
(
pin_nRESET : IN STD_LOGIC;
pin_CLK : IN STD_LOGIC;
pin_PIC32_DATA : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
pin_PIC32_ADDRESS : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
pin_PIC32_nWR : IN STD_LOGIC;
pin_PIC32_nRD : IN STD_LOGIC;
-- pin_KC_CLK : IN STD_LOGIC; -- external video clock 7.09 MHz
-- pin_KC_R, pin_KC_G, pin_KC_B : IN STD_LOGIC; -- pixel colors
-- pin_KC_EZ : IN STD_LOGIC; -- foreground/background bit
-- pin_KC_EX : IN STD_LOGIC; -- intensity bit
-- pin_KC_HSYNC : IN STD_LOGIC; -- horizontal sync input
-- pin_KC_VSYNC : IN STD_LOGIC; -- vertical sync input
-- pin_VGA_R, pin_VGA_G, pin_VGA_B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-- pin_VGA_VSYNC, pin_VGA_HSYNC : OUT STD_LOGIC;
-- pin_JUMPER0 : IN STD_LOGIC -- SCANLINES
-- pin_JUMPER1: in STD_LOGIC;
-- pin_JUMPER2: in STD_LOGIC;
-- pin_JUMPER3: in STD_LOGIC;
-- pin_JUMPER4: in STD_LOGIC;
-- pin_JUMPER5: in STD_LOGIC
pin_SRAM_A : OUT STD_LOGIC_VECTOR (16 DOWNTO 0); -- SRAM address output
pin_SRAM_D : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- SRAM data output
pin_SRAM_nCE : OUT STD_LOGIC; -- SRAM chip enable
pin_SRAM_nOE : OUT STD_LOGIC; -- SRAM output enable
pin_SRAM_nWE : OUT STD_LOGIC; -- SRAM write enable
pin_SRAM_nBHE : OUT STD_LOGIC; -- SRAM H byte enable
pin_SRAM_nBLE : OUT STD_LOGIC -- SRAM L byte enable
);
END KCVGA;
ARCHITECTURE Behavioral OF KCVGA IS
SIGNAL sig_CLK_108MHZ, sig_RESET : STD_LOGIC;
-- SIGNAL sig_FRAMESYNC : STD_LOGIC; -- start of frame from VGA module for screensaver
-- SIGNAL sig_PIC32_WR_FIFO_OUT : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- SIGNAL sig_PIC32_WR_FIFO_IN : STD_LOGIC_VECTOR (31 DOWNTO 0);
-- SIGNAL sig_PIC32_WR_FIFO_WR : STD_LOGIC;
-- SIGNAL sig_PIC32_WR_FIFO_FULL : STD_LOGIC;
-- SIGNAL sig_PIC32_WR_FIFO_RD : STD_LOGIC;
-- SIGNAL sig_PIC32_WR_FIFO_EMPTY : STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_OUT: STD_LOGIC_VECTOR (31 downto 0);
-- signal sig_PIC32_RD_FIFO_IN: STD_LOGIC_VECTOR (31 downto 0);
-- signal sig_PIC32_RD_FIFO_WR: STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_FULL: STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_RD: STD_LOGIC;
-- signal sig_PIC32_RD_FIFO_EMPTY: STD_LOGIC;
-- SIGNAL sig_KC_FIFO_WR : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_FULL : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_RD : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_EMPTY : STD_LOGIC;
-- SIGNAL sig_KC_FIFO_OUT : STD_LOGIC_VECTOR (4 DOWNTO 0);
-- SIGNAL sig_KC_FIFO_IN : STD_LOGIC_VECTOR (4 DOWNTO 0);
-- SIGNAL sig_KC_ADDR_WR : STD_LOGIC;
-- SIGNAL sig_KC_ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0);
-- SIGNAL sig_VGA_ADDR_WR : STD_LOGIC;
-- SIGNAL sig_VGA_ADDR : STD_LOGIC_VECTOR(16 DOWNTO 0);
-- SIGNAL sig_VGA_FIFO_RST : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_RST_COMBINED : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_RD : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_WR : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_IN : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- SIGNAL sig_VGA_FIFO_OUT : STD_LOGIC_VECTOR(4 DOWNTO 0);
-- SIGNAL sig_VGA_FIFO_EMPTY : STD_LOGIC;
-- SIGNAL sig_VGA_FIFO_FULL : STD_LOGIC;
-- SIGNAL sig_FLAG_REGISTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
-- -- SIGNAL sig_DEBUG_REGISTER : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- SIGNAL suppress_no_load_pins_warning : STD_LOGIC;
BEGIN
--
-- +-------------------+
-- | KCVIDEO_INTERFACE |
-- | |
-- ====>| R,G,B,EX,EZ |
-- | |
-- ---->| KC_CLK |
-- ---->| HSYNC |
-- ---->| VSYNC |
-- +-------------------+
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-- suppress_no_load_pins_warning <=
-- pin_KC_EX
-- OR pin_KC_EZ
-- OR pin_KC_HSYNC
-- OR pin_KC_VSYNC
-- OR pin_KC_R
-- OR pin_KC_G
-- OR pin_KC_B
-- OR pin_JUMPER0
-- OR pin_KC_CLK;
i_CLK : ENTITY work.CLK PORT MAP
(
reset => sig_RESET,
clk_input => pin_CLK,
clk_output => sig_CLK_108MHZ
);
sig_RESET <= NOT pin_nRESET;
-- sig_FLAG_REGISTER <= '1' & '1'
-- & sig_PIC32_WR_FIFO_FULL & sig_PIC32_WR_FIFO_EMPTY
-- & sig_KC_FIFO_FULL & sig_KC_FIFO_EMPTY
-- & sig_VGA_FIFO_FULL & sig_VGA_FIFO_EMPTY;
-- always drive SRAM chip enable, high byte enable and low byte enable with
-- active signals
-- pin_SRAM_nCE <= '0';
-- pin_SRAM_nBHE <= '0';
-- pin_SRAM_nBLE <= '0';
i_PIC32_INTERFACE : ENTITY work.PIC32_INTERFACE PORT
MAP
(
CLK => sig_CLK_108MHZ,
RESET => sig_RESET,
A => pin_PIC32_ADDRESS,
D => pin_PIC32_DATA,
-- SRAM => sig_PIC32_WR_FIFO_IN,
-- OUT_FIFO_WR => sig_PIC32_WR_FIFO_WR,
-- OUT_FIFO_FULL => sig_PIC32_WR_FIFO_FULL,
nWR => pin_PIC32_nWR,
nRD => pin_PIC32_nRD,
-- FLAGS => sig_FLAG_REGISTER,
-- DEBUG => sig_DEBUG_REGISTER,
SRAM_A => pin_SRAM_A,
SRAM_D => pin_SRAM_D,
SRAM_nOE => pin_SRAM_nOE,
SRAM_nWE => pin_SRAM_nWE,
SRAM_nCE => pin_SRAM_nCE,
SRAM_nBLE => pin_SRAM_nBLE,
SRAM_nBHE => pin_SRAM_nBHE
-- suppress_no_load_pins_warning => suppress_no_load_pins_warning
);
-- i_PIC32_WR_FIFO : ENTITY work.FIFO GENERIC
-- MAP(
-- RAM_WIDTH => 32,
-- RAM_DEPTH => 128
-- ) PORT
-- MAP(
-- clk => sig_CLK_108MHZ,
-- rst => sig_RESET,
-- wr_en => sig_PIC32_WR_FIFO_WR,
-- wr_data => sig_PIC32_WR_FIFO_IN,
-- rd_en => sig_PIC32_WR_FIFO_RD,
-- rd_data => sig_PIC32_WR_FIFO_OUT,
-- empty => sig_PIC32_WR_FIFO_EMPTY,
-- full => sig_PIC32_WR_FIFO_FULL
-- );
-- i_KCVIDEO_INTERFACE : ENTITY work.KCVIDEO_INTERFACE PORT
-- MAP(
-- CLK => sig_CLK_108MHZ,
-- KC_CLK => pin_KC_CLK,
-- R => pin_KC_R,
-- G => pin_KC_G,
-- B => pin_KC_B,
-- EZ => pin_KC_EZ,
-- EX => pin_KC_EX,
-- HSYNC => pin_KC_HSYNC,
-- VSYNC => pin_KC_VSYNC,
-- nRESET => pin_nRESET,
-- FIFO_WR => sig_KC_FIFO_WR,
-- FIFO_FULL => sig_KC_FIFO_FULL,
-- FRAMESYNC => sig_FRAMESYNC,
-- DATA_OUT => sig_KC_FIFO_IN,
-- SRAM_ADDR => sig_KC_ADDR,
-- SRAM_ADDR_WR => sig_KC_ADDR_WR
-- );
-- i_KC_FIFO : ENTITY work.FIFO GENERIC
-- MAP(
-- RAM_WIDTH => 5,
-- RAM_DEPTH => 512
-- ) PORT
-- MAP(
-- clk => sig_CLK_108MHZ,
-- rst => sig_RESET,
-- wr_en => sig_KC_FIFO_WR,
-- wr_data => sig_KC_FIFO_IN,
-- rd_en => sig_KC_FIFO_RD,
-- rd_data => sig_KC_FIFO_OUT,
-- empty => sig_KC_FIFO_EMPTY,
-- full => sig_KC_FIFO_FULL
-- );
-- -- video mode definition
-- -- 1280x1024 @ 60 Hz, 108 MHz pixel clock, positive sync
-- i_VGA_OUTPUT : ENTITY work.VGA_OUTPUT GENERIC
-- MAP(
-- -- see https://www.mythtv.org/wiki/Modeline_Database
-- 1280, 1328, 1440, 1688, 1024, 1025, 1028, 1066, '1', '1'
-- ) PORT
-- MAP(
-- CLK => sig_CLK_108MHZ,
-- HSYNC => pin_VGA_HSYNC,
-- VSYNC => pin_VGA_VSYNC,
-- R => pin_VGA_R, G => pin_VGA_G, B => pin_VGA_B,
-- nRESET => pin_nRESET,
-- SCANLINES => pin_JUMPER0,
-- FRAMESYNC => sig_FRAMESYNC,
-- FIFO_RD => sig_VGA_FIFO_RD,
-- VGA_ADDR_WR => sig_VGA_ADDR_WR,
-- VGA_ADDR => sig_VGA_ADDR,
-- DATA_IN => sig_VGA_FIFO_OUT,
-- VGA_FIFO_EMPTY => sig_VGA_FIFO_EMPTY
-- );
-- sig_VGA_FIFO_RST_COMBINED <= sig_VGA_FIFO_RST OR sig_RESET;
-- i_VGA_FIFO : ENTITY work.FIFO GENERIC
-- MAP(
-- RAM_WIDTH => 5,
-- RAM_DEPTH => 512
-- ) PORT
-- MAP(
-- clk => sig_CLK_108MHZ,
-- rst => sig_VGA_FIFO_RST_COMBINED,
-- wr_en => sig_VGA_FIFO_WR,
-- wr_data => sig_VGA_FIFO_IN,
-- rd_en => sig_VGA_FIFO_RD,
-- rd_data => sig_VGA_FIFO_OUT,
-- empty => sig_VGA_FIFO_EMPTY,
-- full => sig_VGA_FIFO_FULL
-- );
-- i_SRAM_INTERFACE : ENTITY work.SRAM_INTERFACE PORT
-- MAP(
-- VGA_ADDR => sig_VGA_ADDR, -- address requested from VGA module
-- VGA_DATA => sig_VGA_FIFO_IN, -- data out to VGA module
-- VGA_ADDR_WR => sig_VGA_ADDR_WR, -- VGA address write input
-- VGA_FIFO_WR => sig_VGA_FIFO_WR, -- VGA FIFO write output
-- VGA_FIFO_RST => sig_VGA_FIFO_RST,
-- VGA_FIFO_FULL => sig_VGA_FIFO_FULL,
-- KCVIDEO_DATA => sig_KC_FIFO_OUT,
-- KCVIDEO_FIFO_RD => sig_KC_FIFO_RD,
-- KCVIDEO_FIFO_EMPTY => sig_KC_FIFO_EMPTY,
-- PIC32_DATA => sig_PIC32_WR_FIFO_OUT,
-- PIC32_FIFO_RD => sig_PIC32_WR_FIFO_RD,
-- PIC32_FIFO_EMPTY => sig_PIC32_WR_FIFO_EMPTY,
-- A => pin_SRAM_A,
-- D => pin_SRAM_D,
-- nOE => pin_SRAM_nOE,
-- nWE => pin_SRAM_nWE,
-- nCE => pin_SRAM_nCE,
-- nBLE => pin_SRAM_nBLE,
-- nBHE => pin_SRAM_nBHE,
-- reset => sig_RESET,
-- CLK => sig_CLK_108MHZ,
-- KCVIDEO_ADDR => sig_KC_ADDR,
-- KCVIDEO_ADDR_WR => sig_KC_ADDR_WR,
-- DEBUG => sig_DEBUG_REGISTER
-- );
END Behavioral;
| mit | b0569c0de57685d16e0d3bb9503e1c6c | 0.471919 | 3.161156 | false | false | false | false |
alvieboy/xtc-base | dcache2.vhd | 1 | 23,045 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
-- synopsys translate_off
use work.txt_util.all;
-- synopsys translate_on
entity dcache is
generic (
ADDRESS_HIGH: integer := 31;
CACHE_MAX_BITS: integer := 11; -- 8 Kb
CACHE_LINE_SIZE_BITS: integer := 6 -- 64 bytes
);
port (
syscon: in wb_syscon_type;
ci: in dcache_in_type;
co: out dcache_out_type;
mwbi: in wb_miso_type;
mwbo: out wb_mosi_type
);
end dcache;
architecture behave of dcache is
constant CACHE_LINE_ID_BITS: integer := CACHE_MAX_BITS-CACHE_LINE_SIZE_BITS;
subtype address_type is std_logic_vector(ADDRESS_HIGH downto 2);
-- A line descriptor
subtype line_number_type is std_logic_vector(CACHE_LINE_ID_BITS-1 downto 0);
-- Offset within a line
subtype line_offset_type is std_logic_vector(CACHE_LINE_SIZE_BITS-1-2 downto 0);
-- A tag descriptor
subtype tag_type is std_logic_vector((ADDRESS_HIGH-CACHE_MAX_BITS) downto 0);
-- A full tag memory descriptor. Includes valid bit and dirty bit
subtype full_tag_type is std_logic_vector(ADDRESS_HIGH-CACHE_MAX_BITS+2 downto 0);
constant VALIDBIT: integer := ADDRESS_HIGH-CACHE_MAX_BITS+1;
constant DIRTYBIT: integer := ADDRESS_HIGH-CACHE_MAX_BITS+2;
------------------------------------------------------------------------------
type state_type is (
idle,
readline,
preparewb,
writeback,
recover,
write_after_fill,
settle,
flush,
directmemory
);
constant BURSTWORDS: integer := (2**(CACHE_LINE_SIZE_BITS-2))-1;
type regs_type is record
req: std_logic;
req_addr: address_type;
req_we: std_logic;
req_wmask: std_logic_vector(3 downto 0);
req_data: std_logic_vector(31 downto 0);
req_tag: std_logic_vector(31 downto 0);
req_accesstype: std_logic_vector(1 downto 0);
fill_offset_r: line_offset_type;
req_offset: line_offset_type;
fill_offset_w: line_offset_type;
finished_w: line_offset_type;
fill_tag: tag_type;
fill_line_number: line_number_type;
flush_line_number: line_number_type;
fill_r_done: std_logic;
ack_write: std_logic;
writeback_tag: tag_type;
state: state_type;
misses: integer;
rvalid: std_logic;
wr_conflict: std_logic;
ack_q: std_logic;
ack_q_q: std_logic;
flush_req: std_logic;
in_flush: std_logic;
count: integer range 0 to BURSTWORDS;
end record;
function address_to_tag(a: in address_type) return tag_type is
variable t: tag_type;
begin
t:= a(ADDRESS_HIGH downto CACHE_MAX_BITS);
return t;
end address_to_tag;
function address_to_line_number(a: in address_type) return line_number_type is
variable r: line_number_type;
begin
r:=a(CACHE_MAX_BITS-1 downto CACHE_LINE_SIZE_BITS);
return r;
end address_to_line_number;
function address_to_line_offset(a: in address_type) return line_offset_type is
variable r: line_offset_type;
begin
r:=a(CACHE_LINE_SIZE_BITS-1 downto 2);
return r;
end address_to_line_offset;
------------------------------------------------------------------------------
-- extracted values from port A
signal line_number: line_number_type;
-- Some helpers
signal hit: std_logic;
--signal miss: std_logic;
--attribute keep : string;
-- attribute keep of a_miss : signal is "true";
--attribute keep of b_miss : signal is "true";
--signal a_b_conflict: std_logic;
-- Connection to tag memory
signal tmem_ena: std_logic;
signal tmem_wea: std_logic;
signal tmem_addra: line_number_type;
signal tmem_dia: full_tag_type;
signal tmem_doa: full_tag_type;
signal tmem_enb: std_logic;
signal tmem_web: std_logic;
signal tmem_addrb: line_number_type;
signal tmem_dib: full_tag_type;
signal tmem_dob: full_tag_type;
signal cmem_ena: std_logic;
signal cmem_wea: std_logic_vector(3 downto 0);
signal cmem_dia: std_logic_vector(31 downto 0);
signal cmem_doa: std_logic_vector(31 downto 0);
signal cmem_addra: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal cmem_enb: std_logic;
signal cmem_web: std_logic_vector(3 downto 0);
signal cmem_dib: std_logic_vector(31 downto 0);
signal cmem_dob: std_logic_vector(31 downto 0);
signal cmem_addrb: std_logic_vector(CACHE_MAX_BITS-1 downto 2);
signal r: regs_type;
signal same_address: std_logic;
constant offset_all_ones: line_offset_type := (others => '1');
constant offset_all_zeroes: line_offset_type := (others => '0');
constant line_number_all_ones: line_number_type := (others => '1');
signal dbg_valid: std_logic;
signal dbg_dirty: std_logic;
signal dbg_miss: std_logic;
signal dbg_tag_address: tag_type;
signal dbg_tag_stored: tag_type;
signal req_in_progess: std_logic;
signal req_last: std_logic;
signal wb_stb, wb_cyc: std_logic;
begin
-- These are alias, but written as signals so we can inspect them
line_number <= address_to_line_number(ci.address(address_type'RANGE));
-- TAG memory
tagmem: entity work.generic_dp_ram_rf
generic map (
address_bits => CACHE_LINE_ID_BITS,
data_bits => ADDRESS_HIGH-CACHE_MAX_BITS+3
)
port map (
clka => syscon.clk,
ena => tmem_ena,
wea => tmem_wea,
addra => tmem_addra,
dia => tmem_dia,
doa => tmem_doa,
clkb => syscon.clk,
enb => tmem_enb,
web => tmem_web,
addrb => tmem_addrb,
dib => tmem_dib,
dob => tmem_dob
);
-- Cache memory
memgen: for i in 0 to 3 generate
cachemem: entity work.generic_dp_ram_rf
generic map (
address_bits => cmem_addra'LENGTH,
data_bits => 8
)
port map (
clka => syscon.clk,
ena => cmem_ena,
wea => cmem_wea(i),
addra => cmem_addra,
dia => cmem_dia(((i+1)*8)-1 downto i*8),
doa => cmem_doa(((i+1)*8)-1 downto i*8),
clkb => syscon.clk,
enb => cmem_enb,
web => cmem_web(i),
addrb => cmem_addrb,
dib => cmem_dib(((i+1)*8)-1 downto i*8),
dob => cmem_dob(((i+1)*8)-1 downto i*8)
);
end generate;
co.in_flush <= r.in_flush;
reqcnt_inst: entity work.reqcnt
port map (
clk => syscon.clk,
rst => syscon.rst,
stb => wb_stb,
cyc => wb_cyc,
stall => mwbi.stall,
ack => mwbi.ack,
req => req_in_progess,
lastreq => req_last,
count => open
);
mwbo.cyc<=wb_cyc;
mwbo.stb<=wb_stb;
process(r,syscon.clk,syscon.rst, ci, mwbi, tmem_doa,
tmem_doa, tmem_dob, line_number, cmem_doa, cmem_dob,req_last)
variable w: regs_type;
variable have_request: std_logic;
variable will_busy: std_logic;
variable valid: std_logic;
--variable stall: std_logic;
variable miss: std_logic;
begin
w := r;
valid :='0';
--stall:='0';
miss := DontCareValue;
will_busy := '0';
co.valid<='0';
co.stall<='0';
wb_cyc <= '0';
wb_stb <= DontCareValue;
mwbo.adr <= (others => DontCareValue);
mwbo.dat <= (others => DontCareValue);
mwbo.tag <= (others => DontCareValue);
mwbo.we <= DontCareValue;
mwbo.sel<=(others => '1');
tmem_addra <= line_number;
tmem_addrb <= address_to_line_number( r.req_addr );--(others => DontCareValue);
tmem_ena <= '1';
tmem_wea <= '0';
tmem_enb <= '0';
--tmem_web <= '0';
--tmem_dib(tag_type'RANGE) <= address_to_tag(ci.address(r.req_addr'RANGE));--(others => DontCareValue);
tmem_dib(tag_type'RANGE) <= address_to_tag(r.req_addr);--(others => DontCareValue);
tmem_dib(DIRTYBIT)<=DontCareValue;
tmem_dib(VALIDBIT)<=DontCareValue;
tmem_dia <= (others => DontCareValue);
-- content memory is accessed at same time as tag memory
cmem_addra <= ci.address(CACHE_MAX_BITS-1 downto 2);
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);
cmem_ena <= ci.enable and ci.strobe;
if ci.we='0' then
cmem_wea <= "0000";
else
if ci.accesstype/=ACCESS_NOCACHE then
cmem_wea <= ci.wmask;
else
cmem_wea <= "0000";
end if;
end if;
cmem_web <= "0000";
cmem_dia <= ci.data;
cmem_enb <= r.req;-- and not miss; --ci.b_enable;
--cmem_dia <= (others => DontCareValue); -- No writes on port A
cmem_dib <= r.req_data;--ci.b_data_in;--(others => DontCareValue);
co.data <= cmem_doa;
--co.b_data_out <= cmem_dob;
--w.ack_b_write := '0';
w.rvalid := 'X';
-- synopsys translate_off
dbg_valid <= tmem_doa(VALIDBIT);
dbg_dirty <= tmem_doa(DIRTYBIT);
-- synopsys translate_on
tmem_web <= '0';
co.tag <= r.req_tag;
w.ack_q_q := '0';
w.ack_q := '0';
-- synopsys translate_off
dbg_tag_address<=address_to_tag(r.req_addr);
dbg_tag_stored<=tmem_doa(tag_type'RANGE);
-- synopsys translate_on
case r.state is
when idle =>
co.stall<='0';
-- Now, after reading from tag memory....
if (r.req='1') then
-- We had a request, check
miss:='1';
if tmem_doa(VALIDBIT)='1' then
if tmem_doa(tag_type'RANGE) = address_to_tag(r.req_addr) then
miss:='0';
end if;
end if;
-- For noncache access, we mark it as
-- miss.
if r.req_accesstype=ACCESS_NOCACHE then
miss := '1';
end if;
co.valid<=not miss;
else
co.valid<='0';
miss:='0';
end if;
-- Miss handling
if miss='1' then
-- Invalidate any potential write in cachemem from
-- a netx request.
--cmem_wea<="0000";
cmem_ena<='0';
if r.req_accesstype/=ACCESS_NOCACHE then
co.stall <= '1';
valid := '0';
w.misses := r.misses+1;
w.fill_tag := address_to_tag(r.req_addr);
w.fill_line_number := address_to_line_number(r.req_addr);
w.count := BURSTWORDS;
w.fill_r_done := '0';
w.fill_offset_r := r.req_offset;
w.fill_offset_w := r.req_offset;
if tmem_doa(VALIDBIT)='1' then
if tmem_doa(DIRTYBIT)='1' then
-- Read/Write miss to a dirty line for a different
-- tag.
w.writeback_tag := tmem_doa(tag_type'RANGE);
-- TODO: if this is a direct access, no need to writeback.
w.rvalid := '0';
--w.fill_r_done := '0';
w.fill_offset_r := (others => '0');
w.fill_offset_w := (others => '0');
if r.req_we='1' then
--- Oops, we wrote to the wrong line.
w.state := recover; -- was writeback
else
w.state := preparewb;
end if;
will_busy :='1';
else
-- Read/Write to a non-dirty line for a different
-- tag.
w.state := readline;
will_busy :='1';
end if;
else
-- Read/Write to a non-present line for a different
-- tag.
if r.req_we='1' then
-- It's a write.
case r.req_accesstype is
when ACCESS_WB_WA =>
w.state := readline;
when ACCESS_WB_NA | ACCESS_WT =>
-- Non-cacheable access, no allocate or writethrough.
-- Need to perform write directly to memory
w.state := directmemory;
w.fill_r_done := '0';
when others =>
--
end case;
else
-- It's a read.
w.state := readline;
end if;
will_busy :='1';
end if;
else
-- Non-cacheable address.
w.state := directmemory;
w.fill_r_done := '0';
will_busy := '1';
co.stall<='1';
end if;
else
-- This is a hit. Make sure we write the dirty bit (for writes).
tmem_web<=r.req_we;
tmem_enb<=r.req;
tmem_dib(DIRTYBIT)<='1';
tmem_dib(VALIDBIT)<='1';
valid := '1';
end if;
if r.flush_req='1' then
will_busy :='1';
co.stall <= '1';
cmem_enb <= '0';
cmem_dib <= (others => DontCareValue);
cmem_addrb <= (others => DontCareValue);
w.state := flush;
w.fill_line_number := (others => '0');
w.flush_line_number := (others => '0');
end if;
have_request := '0';
-- Queue requests
if will_busy='0' then
w.req := ci.strobe and ci.enable;
w.req_we := ci.we;
w.req_wmask := ci.wmask;
w.req_data := ci.data;
w.req_tag := ci.tag;
w.req_accesstype := ci.accesstype;
co.stall<='0';
if ci.strobe='1' and ci.enable='1' then
have_request := '1';
w.req_addr(address_type'RANGE) := ci.address(address_type'RANGE);
w.req_offset := address_to_line_offset(ci.address(address_type'RANGE));
end if;
end if;
when directmemory =>
co.stall <= '1';
tmem_web <= '0';
mwbo.adr <=(others => '0');
mwbo.adr (ADDRESS_HIGH downto 2) <= r.req_addr;
wb_cyc <='1';
wb_stb <=not r.fill_r_done;
mwbo.we <= r.req_we;
mwbo.sel <= r.req_wmask;
mwbo.dat <= r.req_data;
mwbo.tag <= r.req_tag;
co.data <= mwbi.dat;
co.tag <= mwbi.tag;
if mwbi.stall='0' then
w.fill_r_done:='1';
end if;
if mwbi.ack='1' then
co.valid<='1';
co.stall<='0';
w.req := ci.strobe and ci.enable;
w.req_we := ci.we;
w.req_wmask := ci.wmask;
w.req_data := ci.data;
w.req_tag := ci.tag;
w.req_accesstype := ci.accesstype;
co.stall<='0';
if ci.strobe='1' and ci.enable='1' then
have_request := '1';
w.req_addr(address_type'RANGE) := ci.address(address_type'RANGE);
w.req_offset := address_to_line_offset(ci.address(address_type'RANGE));
end if;
w.state:=idle;
end if;
when readline =>
co.stall <= '1';
tmem_web <= '0';
w.ack_q := mwbi.ack;
w.ack_q_q := r.ack_q;
mwbo.adr<=(others => '0');
mwbo.adr(ADDRESS_HIGH downto 2) <= r.fill_tag & r.fill_line_number & r.fill_offset_r;
mwbo.tag(cmem_addrb'LENGTH-1 downto 0) <= r.fill_line_number & r.fill_offset_r;
mwbo.tag(cmem_addrb'LENGTH) <= '1';
wb_cyc<='1';
wb_stb<=not r.fill_r_done;
mwbo.we<='0';
cmem_addrb <= mwbi.tag(cmem_addrb'LENGTH-1 downto 0);--r.fill_line_number & r.fill_offset_w;
cmem_addra <= r.req_addr(CACHE_MAX_BITS-1 downto 2);--r.req_offset;--(others => DontCareValue);
--cmem_enb <= '1';
cmem_enb <= mwbi.tag(cmem_addrb'LENGTH);-- <= '1';
cmem_ena <= '1';
cmem_wea <= (others => '0');
cmem_dia <= (others => 'X');
cmem_web <= (others => mwbi.ack);
cmem_dib <= mwbi.dat;
if mwbi.stall='0' and r.fill_r_done='0' then
if w.count=0 then--r.fill_offset_r = offset_all_ones then
w.fill_r_done := '1';
else
w.fill_offset_r := std_logic_vector(unsigned(r.fill_offset_r) + 1);
w.count := w.count - 1;
end if;
end if;
--if r.ack_q='1' then
--end if;
if mwbi.ack='1' then
w.fill_offset_w := std_logic_vector(unsigned(r.fill_offset_w) + 1);
w.finished_w := r.fill_offset_w;
--if r.fill_offset_w=offset_all_ones then
if r.fill_r_done='1' and req_last='1' then
w.state := settle;
tmem_addrb <= r.fill_line_number;
tmem_dib(tag_type'RANGE) <= r.fill_tag;
tmem_dib(VALIDBIT)<='1';
tmem_dib(DIRTYBIT)<=r.req_we;
tmem_web<='1';
tmem_enb<='1';
tmem_ena<='0';
if r.req_we='1' then
-- Perform write
w.state := write_after_fill;
end if;
end if;
else
cmem_dia <= (others => DontCareValue);
cmem_dib <= (others => DontCareValue);
end if;
-- Validate read for IWF
if true then
if r.ack_q_q='1' then
if r.finished_w=r.req_offset then
co.valid<='1';
co.tag<=r.req_tag;
w.req :='0';
end if;
end if;
end if;
when recover =>
-- Recover lost data on the content memory
co.stall <= '1';
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);
cmem_enb <= '1';
cmem_web <= "1111";
cmem_dib <= cmem_doa;
cmem_wea<="0000"; -- Don't allow writes.
-- synthesis translate_off
--report "Recover write";
-- synthesis translate_on
w.rvalid := '0';
w.fill_r_done := '0';
w.state := preparewb;
when writeback =>
co.stall <= '1';
w.rvalid := '1';
mwbo.adr <=(others => '0');
mwbo.adr(ADDRESS_HIGH downto 2) <= r.writeback_tag & r.fill_line_number & r.fill_offset_w;
wb_cyc <= '1';--r.rvalid ; --'1';
wb_stb <= not r.fill_r_done;
mwbo.we <= '1';--r.rvalid; --1';
mwbo.sel <= (others => '1');
mwbo.tag(cmem_addrb'LENGTH) <= '0';
if mwbi.stall='0' and r.fill_r_done='0' then
if w.count=0 then
w.fill_r_done := '1';
else
w.fill_offset_r := std_logic_vector(unsigned(r.fill_offset_r) + 1);
w.fill_offset_w := r.fill_offset_r;
w.count := w.count - 1;
end if;
end if;
if req_last='1' and r.count=0 then
if r.in_flush='1' then
w.state := flush;
w.in_flush:='0';
else
w.fill_offset_r := r.req_offset;--(others => '0');
w.fill_offset_w := r.req_offset;--(others => '0');
w.fill_r_done := '0';
w.count := BURSTWORDS;
w.state := readline;
end if;
end if;
mwbo.dat <= cmem_dob;
cmem_addrb <= (r.fill_line_number & r.fill_offset_r) ;
cmem_enb <= not mwbi.stall;-- or not r.rvalid;
cmem_addra <= (others => DontCareValue);
cmem_web <= (others=>'0');
--cmem_wea<="0000"; -- Don't allow writes.
cmem_ena <= '0';
when preparewb =>
co.stall <= '1';
mwbo.dat <= cmem_dob;
cmem_addrb <= (r.fill_line_number & r.fill_offset_r) ;
cmem_enb <= '1';
cmem_addra <= (others => DontCareValue);
cmem_web <= (others=>'0');
cmem_ena <= '0';
w.fill_offset_r := std_logic_vector(unsigned(r.fill_offset_r) + 1);
w.count := BURSTWORDS;
w.state := writeback;
--cmem_wea<="0000"; -- Don't allow writes.
when write_after_fill =>
cmem_addra <= (others => DontCareValue);
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);
cmem_dib <= r.req_data;
cmem_web <= r.req_wmask;
cmem_enb <= '1';
cmem_ena <= '0';
cmem_dia <= (others => 'X');
cmem_wea <= (others => 'X');
co.stall <= '1';
--b_stall := '1';
valid := '0'; -- ERROR
--b_valid := '0'; -- ERROR
--w.ack_b_write := '1';
w.state := settle;
when settle =>
cmem_addra <= r.req_addr(CACHE_MAX_BITS-1 downto 2);--r.fill_tag & r.fill_line_number & r.fill_offset_w;
cmem_addrb <= r.req_addr(CACHE_MAX_BITS-1 downto 2);--r.fill_tag & r.fill_line_number & r.fill_offset_w;
cmem_web <= (others => '0');
cmem_wea <= (others => '0');
tmem_ena <= '1';
cmem_ena <= '1';
tmem_addra <= address_to_line_number(r.req_addr);
tmem_addrb <= address_to_line_number(r.req_addr);
co.stall <= '1';
--b_stall := '1';
tmem_web <= '0';
valid := '0'; -- ERROR
--b_valid := '0';--r.ack_b_write; -- ERROR -- note: don't ack writes
w.state := idle;
when flush =>
co.stall<='1';
valid:='0';
tmem_addrb <= r.flush_line_number;
tmem_addra <= (others => DontCareValue);
tmem_ena <='0';
tmem_wea <='0';
tmem_dib(VALIDBIT)<='0';
tmem_dib(DIRTYBIT)<='0';
tmem_web<='1';
tmem_enb<='1';
cmem_enb <= '0';
cmem_addra <= (others => DontCareValue);
cmem_addrb <= (others => DontCareValue);
cmem_dia <= (others => DontCareValue);
cmem_dib <= (others => DontCareValue);
cmem_ena <= '0';
w.flush_line_number := r.flush_line_number+1;
w.fill_offset_r := (others => '0');
w.in_flush := '1';
w.flush_req := '0';
-- w.fill_offset_r := (others => '0');
w.fill_offset_w := (others => '0');
-- only valid in next cycle
if r.in_flush='1' and tmem_dob(VALIDBIT)='1' and tmem_dob(DIRTYBIT)='1' then
-- report "Need to wb" severity note;
w.writeback_tag := tmem_dob(tag_type'RANGE); -- NOTE: can we use tmem_doa ?
--w.fill_is_b := '1';
tmem_web<='0';
w.fill_offset_r := (others => '0');
w.flush_line_number := r.flush_line_number;
w.fill_r_done := '0';
w.rvalid := '1';
w.state := preparewb;
else
w.fill_line_number := r.flush_line_number;
if r.fill_line_number = line_number_all_ones then --r.in_flush='1' and r.fill_line_number=line_number_all_zeroes then
w.state := idle;
w.in_flush :='0';
end if;
end if;
end case;
if ci.flush='1' then
w.flush_req :='1';
end if;
if syscon.rst='1' then
w.req := '0';
w.misses :=0;
w.flush_req :='1';
w.in_flush :='0';
w.req:='0';
w.req_we:='0';
--r.fill_line_number := (others => '0');
-- r.flush_line_number := (others => '0');
--r.state <= flush;
w.state := idle;
--co.valid <= '0';
end if;
if rising_edge(syscon.clk) then
--co.valid <= valid;
--co.b_valid <= b_valid;
--co.a_stall <= a_stall;
--co.b_stall <= b_stall;
r <= w;
end if;
dbg_miss<=miss;
end process;
co.err <= '0';
end behave;
| bsd-3-clause | 9bfd49e32ededf4eb2ee1867a173fe16 | 0.514125 | 3.280894 | false | false | false | false |
alvieboy/xtc-base | txt_util.vhd | 1 | 16,790 | -- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library work;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
--67
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
| bsd-3-clause | a2823b1ca9d6d24e6a3f5fd042ca12e6 | 0.483204 | 3.973024 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixgx_components.vhd | 1 | 33,564 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
package stratixgx_components is
--
-- stratixgx_lcell
--
COMPONENT stratixgx_lcell
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "stratixgx_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
--
-- stratixgx_io
--
COMPONENT stratixgx_io
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratixgx_io"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
END COMPONENT;
--
-- stratixgx_mac_mult
--
COMPONENT stratixgx_mac_mult
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_mult"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector((dataa_width+datab_width)-1 downto 0);
scanouta : out std_logic_vector(dataa_width-1 downto 0);
scanoutb : out std_logic_vector(datab_width-1 downto 0)
);
END COMPONENT;
--
-- stratixgx_mac_out
--
COMPONENT stratixgx_mac_out
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 36;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0) := (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_out"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (dataout_width-1 downto 0);
accoverflow : out std_logic
);
END COMPONENT;
--
-- stratixgx_ram_block
--
COMPONENT stratixgx_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "stratixgx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixgx_pll
--
COMPONENT stratixgx_pll
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "stratixgx_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
scan_chain_mif_file : string := "";
family_name : string := "STRATIXGX";
skip_vco : string := "off";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END COMPONENT;
--
-- stratixgx_dll
--
COMPONENT stratixgx_dll
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "stratixgx_dll";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END COMPONENT;
--
-- stratixgx_lvds_transmitter
--
COMPONENT stratixgx_lvds_transmitter
GENERIC (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratixgx_lvds_transmitter";
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
--
-- stratixgx_jtag
--
COMPONENT stratixgx_jtag
generic (
lpm_type : string := "stratixgx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixgx_crcblock
--
COMPONENT stratixgx_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixgx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixgx_rublock
--
COMPONENT stratixgx_rublock
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixgx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
END COMPONENT;
--
-- stratixgx_routing_wire
--
COMPONENT stratixgx_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- stratixgx_lvds_receiver
--
COMPONENT stratixgx_lvds_receiver
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
END COMPONENT;
end stratixgx_components;
| gpl-3.0 | 498c5250c3394a178056631a7878a341 | 0.431653 | 4.20918 | false | false | false | false |
alvieboy/xtc-base | tb_standalone.vhd | 1 | 6,683 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.xtccomppkg.all;
use work.wishbonepkg.all;
entity tbs is
end entity tbs;
architecture sim of tbs is
constant period: time := 10 ns;
signal w_clk: std_logic := '0';
signal w_rst: std_logic := '0';
signal wb_read: std_logic_vector(31 downto 0);
signal wb_write: std_logic_vector(31 downto 0);
signal wb_address: std_logic_vector(31 downto 0);
signal wb_stb: std_logic;
signal wb_cyc: std_logic;
signal wb_sel: std_logic_vector(3 downto 0);
signal wb_we: std_logic;
signal wb_ack: std_logic;
signal wb_stall: std_logic;
signal rom_wb_ack: std_logic;
signal rom_wb_read: std_logic_vector(31 downto 0);
signal rom_wb_adr: std_logic_vector(31 downto 0);
signal rom_wb_cyc: std_logic;
signal rom_wb_stb: std_logic;
signal rom_wb_cti: std_logic_vector(2 downto 0);
signal rom_wb_stall: std_logic;
component wbarb2_1 is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master 0 signals
m0_wb_dat_o: out std_logic_vector(31 downto 0);
m0_wb_dat_i: in std_logic_vector(31 downto 0);
m0_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m0_wb_sel_i: in std_logic_vector(3 downto 0);
m0_wb_cti_i: in std_logic_vector(2 downto 0);
m0_wb_we_i: in std_logic;
m0_wb_cyc_i: in std_logic;
m0_wb_stb_i: in std_logic;
m0_wb_stall_o: out std_logic;
m0_wb_ack_o: out std_logic;
-- Master 1 signals
m1_wb_dat_o: out std_logic_vector(31 downto 0);
m1_wb_dat_i: in std_logic_vector(31 downto 0);
m1_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m1_wb_sel_i: in std_logic_vector(3 downto 0);
m1_wb_cti_i: in std_logic_vector(2 downto 0);
m1_wb_we_i: in std_logic;
m1_wb_cyc_i: in std_logic;
m1_wb_stb_i: in std_logic;
m1_wb_ack_o: out std_logic;
m1_wb_stall_o: out std_logic;
-- Slave signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
s0_wb_stall_i: in std_logic
);
end component;
component wb_singleport_ram is
generic (
bits: natural := 8
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(31 downto 0);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic
);
end component;
component wb_master_np_to_slave_p is
generic (
ADDRESS_HIGH: integer := 31;
ADDRESS_LOW: integer := 0
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master signals
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave signals
s_wb_dat_i: in std_logic_vector(31 downto 0);
s_wb_dat_o: out std_logic_vector(31 downto 0);
s_wb_adr_o: out std_logic_vector(ADDRESS_HIGH downto ADDRESS_LOW);
s_wb_sel_o: out std_logic_vector(3 downto 0);
s_wb_cti_o: out std_logic_vector(2 downto 0);
s_wb_we_o: out std_logic;
s_wb_cyc_o: out std_logic;
s_wb_stb_o: out std_logic;
s_wb_ack_i: in std_logic;
s_wb_stall_i: in std_logic
);
end component;
component romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_sel_i: in std_logic_vector(3 downto 0);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end component;
begin
w_clk <= not w_clk after period/2;
cpu: xtc
port map (
wb_clk_i => w_clk,
wb_rst_i => w_rst,
-- Master wishbone interface
wb_ack_i => wb_ack,
wb_dat_i => wb_read,
wb_dat_o => wb_write,
wb_adr_o => wb_address,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_stall_i => wb_stall,
-- ROM wb interface
rom_wb_ack_i => rom_wb_ack,
rom_wb_dat_i => rom_wb_read,
rom_wb_adr_o => rom_wb_adr,
rom_wb_cyc_o => rom_wb_cyc,
rom_wb_stb_o => rom_wb_stb,
rom_wb_stall_i => rom_wb_stall,
wb_inta_i => '0',
isnmi => '0'
);
myram: romram
generic map (
BITS => 15
)
port map (
ram_wb_clk_i => w_clk,
ram_wb_rst_i => w_rst,
ram_wb_ack_o => wb_ack,
ram_wb_dat_i => wb_write,
ram_wb_dat_o => wb_read,
ram_wb_adr_i => wb_address(14 downto 2),
ram_wb_cyc_i => wb_cyc,
ram_wb_stb_i => wb_stb,
ram_wb_sel_i => wb_sel,
ram_wb_we_i => wb_we,
ram_wb_stall_o => wb_stall,
rom_wb_clk_i => w_clk,
rom_wb_rst_i => w_rst,
rom_wb_ack_o => rom_wb_ack,
rom_wb_dat_o => rom_wb_read,
rom_wb_adr_i => rom_wb_adr(14 downto 2),
rom_wb_cyc_i => rom_wb_cyc,
rom_wb_stb_i => rom_wb_stb,
rom_wb_stall_o => rom_wb_stall
);
-- Reset procedure
process
begin
w_rst<='0';
wait for period;
w_rst<='1';
wait for period;
w_rst<='0';
wait;
end process;
end sim;
| bsd-3-clause | e085df06c3b1421fe167c3cf14019db3 | 0.576537 | 2.619757 | false | false | false | false |
alvieboy/xtc-base | uart_rx.vhd | 1 | 4,822 | --
-- UART for ZPUINO - Receiver unit
--
-- Copyright 2011 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end entity uart_rx;
architecture behave of uart_rx is
component uart_mv_filter is
generic (
bits: natural;
threshold: natural
);
port (
clk: in std_logic;
rst: in std_logic;
sin: in std_logic;
sout: out std_logic;
clear: in std_logic;
enable: in std_logic
);
end component uart_mv_filter;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
signal rxf: std_logic;
signal baudtick: std_logic;
signal rxd: std_logic_vector(7 downto 0);
signal datacount: unsigned(2 downto 0);
signal baudreset: std_logic;
signal filterreset: std_logic;
signal datao: std_logic_vector(7 downto 0);
signal dataready: std_logic;
signal start: std_logic;
signal debug_synctick_q: std_logic;
signal debug_baudreset_q: std_logic;
-- State
type uartrxstate is (
rx_idle,
rx_start,
rx_data,
rx_end
);
signal state: uartrxstate;
begin
data <= datao;
data_av <= dataready;
rxmvfilter: uart_mv_filter
generic map (
bits => 4,
threshold => 10
)
port map (
clk => clk,
rst => rst,
sin => rx,
sout => rxf,
clear => filterreset,
enable => rxclk
);
filterreset <= baudreset or baudtick;
--istart <= start;
baudgen: uart_brgen
port map (
clk => clk,
rst => baudreset,
en => rxclk,
count => x"000f",
clkout => baudtick
);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
state <= rx_idle;
dataready <= '0';
baudreset <= '0';
start<='0';
datao <= rxd;
else
datao <= rxd;
baudreset <= '0';
start<='0';
if read='1' then
dataready <= '0';
end if;
case state is
when rx_idle =>
if rx='0' then -- Start bit
state <= rx_start;
baudreset <= '1';
start <='1';
end if;
when rx_start =>
if baudtick='1' then
-- Check filtered output.
if rxf='0' then
datacount <= b"111";
state <= rx_data; -- Valid start bit.
else
state <= rx_idle;
end if;
end if;
when rx_data =>
if baudtick='1' then
rxd(7) <= rxf;
rxd(6 downto 0) <= rxd(7 downto 1);
datacount <= datacount - 1;
if datacount=0 then
state <= rx_end;
end if;
end if;
when rx_end =>
-- Check for framing errors ?
-- Do fast recovery here.
if rxf='1' then
dataready<='1';
state <= rx_idle;
end if;
if baudtick='1' then
-- Framing error.
state <= rx_idle;
end if;
when others =>
end case;
end if;
end if;
end process;
end behave;
| bsd-3-clause | aaf2e8d2f89704344279c07adb9dd649 | 0.582746 | 3.723552 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_comp_pack-p.vhd | 1 | 12,697 | -------------------------------------------------------------------------------
--
-- $Id: t400_comp_pack-p.vhd,v 1.8 2008-05-01 19:49:55 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
package t400_comp_pack is
component t400_clkgen
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Clock Interface ------------------------------------------------------
phi1_o : out std_logic;
out_en_o : out boolean;
in_en_o : out boolean;
icyc_en_o : out boolean
);
end component;
component t400_reset
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
icyc_en_i : in boolean;
-- Reset Interface ------------------------------------------------------
por_i : in boolean;
reset_n_i : in std_logic;
res_o : out boolean
);
end component;
component t400_stack
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Stack Control Interface ----------------------------------------------
op_i : in stack_op_t;
-- Program Counter Interface --------------------------------------------
pc_i : in pc_t;
pc_o : out pc_t
);
end component;
component t400_pmem_ctrl
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
a_i : in dw_t;
m_i : in dw_t;
-- Control Interface ----------------------------------------------------
op_i : in pc_op_t;
dec_data_i : in dec_data_t;
-- Stack Interface ------------------------------------------------------
pc_o : out pc_t;
pc_i : in pc_t;
-- Program Memory Interface ---------------------------------------------
pm_addr_o : out pc_t
);
end component;
component t400_alu
generic (
opt_cko_g : integer := t400_opt_cko_crystal_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
cko_i : in std_logic;
-- Control Interface ----------------------------------------------------
op_i : in alu_op_t;
-- Data Interface -------------------------------------------------------
m_i : in dw_t;
dec_data_i : in dec_data_t;
q_low_i : in dw_t;
b_i : in b_t;
g_i : in dw_t;
in_i : in dw_t;
sio_i : in dw_t;
a_o : out dw_t;
carry_o : out std_logic;
c_o : out std_logic
);
end component;
component t400_dmem_ctrl
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ----------------------------------------------------
dmem_op_i : in dmem_op_t;
b_op_i : in b_op_t;
dec_data_i : in dec_data_t;
a_i : in dw_t;
q_high_i : in dw_t;
b_o : out b_t;
-- Data Memory Interface ------------------------------------------------
dm_addr_o : out dm_addr_t;
dm_data_i : in dw_t;
dm_data_o : out dw_t;
dm_we_o : out std_logic
);
end component;
component t400_decoder
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
out_en_i : in boolean;
in_en_i : in boolean;
icyc_en_i : in boolean;
-- Module Control Interface ---------------------------------------------
pc_op_o : out pc_op_t;
stack_op_o : out stack_op_t;
dmem_op_o : out dmem_op_t;
b_op_o : out b_op_t;
skip_op_o : out skip_op_t;
alu_op_o : out alu_op_t;
io_l_op_o : out io_l_op_t;
io_d_op_o : out io_d_op_t;
io_g_op_o : out io_g_op_t;
io_in_op_o : out io_in_op_t;
sio_op_o : out sio_op_t;
dec_data_o : out dec_data_t;
en_o : out dw_t;
-- Skip Interface -------------------------------------------------------
skip_i : in boolean;
skip_lbi_i : in boolean;
is_lbi_o : out boolean;
int_i : in boolean;
-- Program Memory Interface ---------------------------------------------
pm_addr_i : in pc_t;
pm_data_i : in byte_t
);
end component;
component t400_skip
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in skip_op_t;
dec_data_i : in dec_data_t;
carry_i : in std_logic;
c_i : in std_logic;
bd_i : in dw_t;
is_lbi_i : in boolean;
skip_o : out boolean;
skip_lbi_o : out boolean;
-- Data Interface -------------------------------------------------------
a_i : in dw_t;
m_i : in dw_t;
g_i : in dw_t;
tim_c_i : in boolean
);
end component;
component t400_io_l
generic (
opt_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
in_en_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in io_l_op_t;
en2_i : in std_logic;
m_i : in dw_t;
a_i : in dw_t;
pm_data_i : in byte_t;
q_o : out byte_t;
-- Microbus Interface ---------------------------------------------------
cs_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
-- Port L Interface -----------------------------------------------------
io_l_i : in byte_t;
io_l_o : out byte_t;
io_l_en_o : out byte_t
);
end component;
component t400_io_d
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in io_d_op_t;
bd_i : in bd_t;
-- Port D Interface -----------------------------------------------------
io_d_o : out dw_t;
io_d_en_o : out dw_t
);
end component;
component t400_io_g
generic (
opt_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_microbus_g : integer := t400_opt_no_microbus_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
cs_n_i : in std_logic;
wr_n_i : in std_logic;
-- Control Interface ----------------------------------------------------
op_i : in io_g_op_t;
m_i : in dw_t;
dec_data_i : in dec_data_t;
-- Port G Interface -----------------------------------------------------
io_g_o : out dw_t;
io_g_en_o : out dw_t
);
end component;
component t400_io_in
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in io_in_op_t;
en1_i : in std_logic;
-- Port Interface -------------------------------------------------------
io_in_i : in dw_t;
in_o : out dw_t;
int_o : out boolean
);
end component;
component t400_sio
generic (
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
phi1_i : in std_logic;
out_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ----------------------------------------------------
op_i : in sio_op_t;
en0_i : in std_logic;
en3_i : in std_logic;
-- SIO Interface --------------------------------------------------------
a_i : in dw_t;
c_i : in std_logic;
sio_o : out dw_t;
-- Pad Interface --------------------------------------------------------
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end component;
component t400_timer
port (
-- System Interface -----------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
-- Skip Interface -------------------------------------------------------
op_i : in skip_op_t;
c_o : out boolean
);
end component;
end t400_comp_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.7 2006/06/05 20:31:56 arniml
-- microbus support for IO G added
--
-- Revision 1.6 2006/06/05 14:20:34 arniml
-- interface comments added
--
-- Revision 1.5 2006/05/27 19:11:33 arniml
-- updates for interrupt support
--
-- Revision 1.4 2006/05/22 00:03:08 arniml
-- io_in added
--
-- Revision 1.3 2006/05/21 21:47:40 arniml
-- route cko to ALU for INIL instruction
--
-- Revision 1.2 2006/05/20 02:48:17 arniml
-- timer module included
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 33ca84d25c32e690c5af3354c0761fd3 | 0.394188 | 3.5201 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneii_components.vhd | 1 | 31,761 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneii_atom_pack.all;
package cycloneii_components is
--
-- cycloneii_ram_block
--
COMPONENT cycloneii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneii_jtag
--
COMPONENT cycloneii_jtag
generic (
lpm_type : string := "cycloneii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneii_crcblock
--
COMPONENT cycloneii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneii_asmiblock
--
COMPONENT cycloneii_asmiblock
generic (
lpm_type : string := "cycloneii_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
END COMPONENT;
--
-- cycloneii_pll
--
COMPONENT cycloneii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "manual";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneii_pll";
family_name : string := "CycloneII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
testclearlock : in std_logic := '0';
sbdin : in std_logic := '0';
clk : out std_logic_vector(2 downto 0);
locked : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
sbdout : out std_logic
);
END COMPONENT;
--
-- cycloneii_routing_wire
--
COMPONENT cycloneii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneii_lcell_ff
--
COMPONENT cycloneii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "cycloneii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_sdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
sdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- cycloneii_lcell_comb
--
COMPONENT cycloneii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
lpm_type : string := "cycloneii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneii_io
--
COMPONENT cycloneii_io
generic (
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
use_differential_input : string := "false";
lpm_type : string := "cycloneii_io";
input_power_up : string := "low");
port (
datain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '1';
linkin : in std_logic := '0';
differentialin : in std_logic := '0';
differentialout : out std_logic;
linkout : out std_logic;
combout : out std_logic;
regout : out std_logic;
padio : inout std_logic
);
END COMPONENT;
--
-- cycloneii_clk_delay_ctrl
--
COMPONENT cycloneii_clk_delay_ctrl
generic (
behavioral_sim_delay : integer := 0;
delay_chain : STRING := "54";
delay_chain_mode : STRING := "static";
uses_calibration : STRING := "false";
use_new_style_dq_detection : STRING := "false";
tan_delay_under_delay_ctrl_signal : STRING := "unused";
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
lpm_type : STRING := "cycloneii_clk_delay_ctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_clkout : VitalDelayType01 := DefPropDelay01;
tpd_pllcalibrateclkdelayedin_clkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01;
tipd_pllcalibrateclkdelayedin : VitalDelayType01 := DefPropDelay01
);
port (
clk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
disablecalibration : in std_logic := '1';
pllcalibrateclkdelayedin: in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
clkout : out std_logic
);
END COMPONENT;
--
-- cycloneii_clk_delay_cal_ctrl
--
COMPONENT cycloneii_clk_delay_cal_ctrl
generic (
delay_ctrl_sim_delay_15_0 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_31_16 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_47_32 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
delay_ctrl_sim_delay_63_48 : STD_LOGIC_VECTOR(511 downto 0) := (OTHERS => '0');
lpm_type : STRING := "cycloneii_clk_delay_cal_ctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_plldataclk_calibratedata : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_calibratedata : VitalDelayType01 := DefPropDelay01;
tpd_pllcalibrateclk_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
tpd_disablecalibration_pllcalibrateclkdelayedout : VitalDelayType01 := DefPropDelay01;
tipd_plldataclk : VitalDelayType01 := DefPropDelay01;
tipd_pllcalibrateclk : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_disablecalibration : VitalDelayType01 := DefPropDelay01
);
port (
plldataclk : in std_logic := '0';
pllcalibrateclk : in std_logic := '0';
disablecalibration : in std_logic := '1';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
calibratedata : out std_logic;
pllcalibrateclkdelayedout : out std_logic
);
END COMPONENT;
--
-- cycloneii_mac_mult
--
COMPONENT cycloneii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneii_mac_out
--
COMPONENT cycloneii_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneii_clkctrl
--
COMPONENT cycloneii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
end cycloneii_components;
| gpl-3.0 | 3be280403aa80bc6fe9424a700955a27 | 0.498693 | 4.080293 | false | false | false | false |
EPiCS/reconos | demos/sort_demo/hw/hwt_sort_demo_v1_00_c/hdl/vhdl/bubble_sorter.vhd | 4 | 6,023 | --
-- bubble_sorter.vhd
-- Bubble sort module. Sequentially sorts the contents of an attached
-- single-port block RAM.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end bubble_sorter;
architecture Behavioral of bubble_sorter is
type state_t is (STATE_IDLE, STATE_LOAD_A, STATE_LOAD_B, STATE_LOAD_WAIT_A, STATE_LOAD_WAIT_B, STATE_COMPARE, STATE_WRITE, STATE_LOAD_NEXT, STATE_START_OVER);
signal state : state_t := STATE_IDLE;
signal ptr : natural range 0 to G_LEN-1; --std_logic_vector(0 to C_AWIDTH-1);
signal ptr_max : natural range 0 to G_LEN-1;
signal a : std_logic_vector(0 to G_DWIDTH-1);
signal b : std_logic_vector(0 to G_DWIDTH-1);
signal low : std_logic_vector(0 to G_DWIDTH-1);
signal high : std_logic_vector(0 to G_DWIDTH-1);
signal swap : boolean;
signal swapped : boolean;
begin
-- set RAM address
o_RAMAddr <= std_logic_vector(TO_UNSIGNED(ptr, G_AWIDTH));
-- concurrent signal assignments
swap <= true when a > b else false; -- should a and b be swapped?
low <= b when swap else a; -- lower value of a and b
high <= a when swap else b; -- higher value of a and b
-- sorting state machine
sort_proc : process(clk, reset)
variable ptr_max_new : natural range 0 to G_LEN-1; -- number of items left to sort
begin
if reset = '1' then
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
done <= '0';
swapped <= false;
a <= (others => '0');
b <= (others => '0');
elsif rising_edge(clk) then
o_RAMWE <= '0';
o_RAMData <= (others => '0');
case state is
when STATE_IDLE =>
done <= '0';
ptr <= 0;
ptr_max <= G_LEN-1;
ptr_max_new := G_LEN-1;
o_RAMData <= (others => '0');
o_RAMWE <= '0';
swapped <= false;
-- start sorting on 'start' signal
if start = '1' then
state <= STATE_LOAD_WAIT_A;
end if;
-- increase address (for B), wait for A to appear on RAM outputs
when STATE_LOAD_WAIT_A =>
ptr <= ptr + 1;
state <= STATE_LOAD_A;
-- wait for B to appear on RAM outputs
when STATE_LOAD_WAIT_B =>
state <= STATE_LOAD_B;
-- read A value from RAM
when STATE_LOAD_A =>
a <= i_RAMData;
state <= STATE_LOAD_B;
-- read B value from RAM
when STATE_LOAD_B =>
b <= i_RAMData;
state <= STATE_COMPARE;
-- compare A and B and act accordingly
when STATE_COMPARE =>
-- if A is higher than B
if swap then
-- write swapped values back
ptr <= ptr - 1; -- back to writing
o_RAMData <= low; -- write low value
o_RAMWE <= '1';
swapped <= true;
state <= STATE_WRITE;
else
if ptr < ptr_max then
-- generate addres for next value for b
a <= b;
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
else
-- if we swapped something then
if swapped then
-- start over
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
end if;
-- write high value
when STATE_WRITE =>
ptr_max_new := ptr; -- save location of last swapped value
ptr <= ptr + 1;
o_RAMData <= high;
o_RAMWE <= '1';
if ptr < ptr_max-1 then
state <= STATE_LOAD_NEXT;
else
-- if we swapped something then
if swapped then
-- start over
state <= STATE_START_OVER;
else
-- else we're done
done <= '1';
state <= STATE_IDLE;
end if;
end if;
-- load next B value
when STATE_LOAD_NEXT =>
ptr <= ptr + 1;
state <= STATE_LOAD_WAIT_B;
-- start from beginning
when STATE_START_OVER =>
ptr <= 0;
ptr_max <= ptr_max_new; -- sort up to last swapped value
swapped <= false;
state <= STATE_LOAD_WAIT_A;
when others =>
state <= STATE_IDLE;
end case;
end if;
end process;
end Behavioral;
| gpl-2.0 | deb417e25b4f9556317de0acbaed9826 | 0.497759 | 3.890827 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_rst_processing_system7_0_100M_0/sim/base_zynq_design_rst_processing_system7_0_100M_0.vhd | 1 | 5,983 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY base_zynq_design_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END base_zynq_design_rst_processing_system7_0_100M_0;
ARCHITECTURE base_zynq_design_rst_processing_system7_0_100M_0_arch OF base_zynq_design_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END base_zynq_design_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | 517de62e34f4ac50876525df174a2c08 | 0.710346 | 3.578349 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixv_hssi_components.vhd | 1 | 129,790 | -- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
package STRATIXV_HSSI_COMPONENTS is
component stratixv_channel_pll
generic
(
avmm_group_channel_index : integer := 0;
output_clock_frequency : string := "0 ps";
reference_clock_frequency : string := "0 ps";
sim_use_fast_model : string := "true";
use_default_base_address : string := "true";
user_base_address : integer := 0;
bbpd_salatch_offset_ctrl_clk0 : string := "clk0_offset_0mv";
bbpd_salatch_offset_ctrl_clk180 : string := "clk180_offset_0mv";
bbpd_salatch_offset_ctrl_clk270 : string := "clk270_offset_0mv";
bbpd_salatch_offset_ctrl_clk90 : string := "clk90_offset_0mv";
bbpd_salatch_sel : string := "normal";
bypass_cp_rgla : string := "false";
cdr_atb_select : string := "atb_disable";
cgb_clk_enable : string := "false";
charge_pump_current_test : string := "enable_ch_pump_normal";
clklow_fref_to_ppm_div_sel : integer := 1;
clock_monitor : string := "lpbk_data";
diag_rev_lpbk : string := "false";
eye_monitor_bbpd_data_ctrl : string := "cdr_data";
fast_lock_mode : string := "false";
fb_sel : string := "vcoclk";
gpon_lock2ref_ctrl : string := "lck2ref";
hs_levshift_power_supply_setting : integer := 1;
ignore_phslock : string := "false";
l_counter_pd_clock_disable : string := "false";
m_counter : integer := 25;
pcie_freq_control : string := "pcie_100mhz";
pd_charge_pump_current_ctrl : integer := 5;
pd_l_counter : integer := 1;
pfd_charge_pump_current_ctrl : integer := 20;
pfd_l_counter : integer := 1;
powerdown : string := "false";
ref_clk_div : integer := 1;
regulator_volt_inc : string := "volt_inc_0pct";
replica_bias_ctrl : string := "true";
reverse_serial_lpbk : string := "false";
ripple_cap_ctrl : string := "none";
rxpll_pd_bw_ctrl : integer := 300;
rxpll_pfd_bw_ctrl : integer := 3200;
txpll_hclk_driver_enable : string := "false";
vco_overange_ref : string := "off";
vco_range_ctrl_en : string := "false"
);
port
(
avmmaddress : in std_logic_vector(10 downto 0);
avmmbyteen : in std_logic;
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector(15 downto 0);
clk270eye : in std_logic;
clk270beyerm : in std_logic;
clk90eye : in std_logic;
clk90beyerm : in std_logic;
clkindeser : in std_logic;
crurstb : in std_logic;
deeye : in std_logic;
deeyerm : in std_logic;
doeye : in std_logic;
doeyerm : in std_logic;
earlyeios : in std_logic;
extclk : in std_logic;
extfbctrla : in std_logic;
extfbctrlb : in std_logic;
gpblck2refb : in std_logic;
lpbkpreen : in std_logic;
ltd : in std_logic;
ltr : in std_logic;
occalen : in std_logic;
pciel : in std_logic;
pciem : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
ppmlock : in std_logic;
refclk : in std_logic;
rstn : in std_logic;
rxp : in std_logic;
sd : in std_logic;
avmmreaddata : out std_logic_vector(15 downto 0);
blockselect : out std_logic;
ck0pd : out std_logic;
ck180pd : out std_logic;
ck270pd : out std_logic;
ck90pd : out std_logic;
clk270bcdr : out std_logic;
clk270bdes : out std_logic;
clk90bcdr : out std_logic;
clk90bdes : out std_logic;
clkcdr : out std_logic;
clklow : out std_logic;
decdr : out std_logic;
deven : out std_logic;
docdr : out std_logic;
dodd : out std_logic;
fref : out std_logic;
pdof : out std_logic_vector(3 downto 0);
pfdmodelock : out std_logic;
rxlpbdp : out std_logic;
rxlpbp : out std_logic;
rxplllock : out std_logic;
txpllhclk : out std_logic;
txrlpbk : out std_logic;
vctrloverrange : out std_logic
);
end component;
component stratixv_atx_pll
generic
(
avmm_group_channel_index : integer := 0 ;
output_clock_frequency : string := "" ;
reference_clock_frequency : string := "" ;
use_default_base_address : string := "true" ;
user_base_address0 : integer := 0 ;
user_base_address1 : integer := 0 ;
user_base_address2 : integer := 0 ;
cp_current_ctrl : integer := 300 ;
cp_current_test : string := "enable_ch_pump_normal" ;
cp_hs_levshift_power_supply_setting : integer := 1 ;
cp_replica_bias_ctrl : string := "disable_replica_bias_ctrl" ;
cp_rgla_bypass : string := "false" ;
cp_rgla_volt_inc : string := "boost_30pct" ;
l_counter : integer := 1 ;
lcpll_atb_select : string := "atb_disable" ;
lcpll_d2a_sel : string := "volt_1p02v" ;
lcpll_hclk_driver_enable : string := "driver_off" ;
lcvco_gear_sel : string := "high_gear" ;
lcvco_sel : string := "high_freq_14g" ;
lpf_ripple_cap_ctrl : string := "none" ;
lpf_rxpll_pfd_bw_ctrl : integer := 2400 ;
m_counter : integer := 4 ;
ref_clk_div : integer := 1 ;
refclk_sel : string := "refclk" ;
vreg1_lcvco_volt_inc : string := "volt_1p1v" ;
vreg1_vccehlow : string := "normal_operation" ;
vreg2_lcpll_volt_sel : string := "vreg2_volt_1p0v" ;
vreg3_lcpll_volt_sel : string := "vreg3_volt_1p0v"
);
port
(
avmmaddress : in std_logic_vector( 10 downto 0 );
avmmbyteen : in std_logic_vector( 1 downto 0 );
avmmclk : in std_logic;
avmmread : in std_logic;
avmmrstn : in std_logic;
avmmwrite : in std_logic;
avmmwritedata : in std_logic_vector( 15 downto 0 );
avmmreaddata : out std_logic_vector( 15 downto 0 );
blockselect : out std_logic;
ch0rcsrlc : in std_logic_vector( 31 downto 0 );
ch1rcsrlc : in std_logic_vector( 31 downto 0 );
ch2rcsrlc : in std_logic_vector( 31 downto 0 );
cmurstn : in std_logic;
cmurstnlpf : in std_logic;
extfbclk : in std_logic;
iqclklc : in std_logic;
pldclklc : in std_logic;
pllfbswblc : in std_logic;
pllfbswtlc : in std_logic;
refclklc : in std_logic;
clk010g : out std_logic;
clk025g : out std_logic;
clk18010g : out std_logic;
clk18025g : out std_logic;
clk33cmu : out std_logic;
clklowcmu : out std_logic;
frefcmu : out std_logic;
iqclkatt : out std_logic;
pfdmodelockcmu : out std_logic;
pldclkatt : out std_logic;
refclkatt : out std_logic;
txpllhclk : out std_logic
);
end component;
component stratixv_hssi_10g_rx_pcs
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
dis_signal_ok : string := "dis_signal_ok_dis";
gb_rx_idwidth : string := "idwidth_32";
gb_rx_odwidth : string := "odwidth_66";
bit_reverse : string := "bit_reverse_dis";
gb_sel_mode : string := "internal";
lpbk_mode : string := "lpbk_dis";
test_mode : string := "test_off";
blksync_bypass : string := "blksync_bypass_dis";
blksync_pipeln : string := "blksync_pipeln_dis";
blksync_knum_sh_cnt_prelock : string := "int";
blksync_knum_sh_cnt_postlock : string := "int";
blksync_enum_invalid_sh_cnt : string := "int";
blksync_bitslip_wait_cnt : string := "int";
bitslip_wait_cnt_user : string := "int";
blksync_bitslip_type : string := "bitslip_comb";
blksync_bitslip_wait_type : string := "bitslip_match";
dispchk_bypass : string := "dispchk_bypass_dis";
dispchk_rd_level : string := "dispchk_rd_level_min";
dispchk_rd_level_user : string := "int";
dispchk_pipeln : string := "dispchk_pipeln_dis";
descrm_bypass : string := "descrm_bypass_en";
descrm_mode : string := "async";
frmsync_bypass : string := "frmsync_bypass_dis";
frmsync_pipeln : string := "frmsync_pipeln_dis";
frmsync_mfrm_length : string := "int";
frmsync_mfrm_length_user : string := "int";
frmsync_knum_sync : string := "int";
frmsync_enum_sync : string := "int";
frmsync_enum_scrm : string := "int";
frmsync_flag_type : string := "all_framing_words";
dec_64b66b_10g_mode : string := "dec_64b66b_10g_mode_en";
dec_64b66b_rxsm_bypass : string := "dec_64b66b_rxsm_bypass_dis";
rx_sm_bypass : string := "rx_sm_bypass_dis";
rx_sm_pipeln : string := "rx_sm_pipeln_dis";
rx_sm_hiber : string := "rx_sm_hiber_en";
ber_xus_timer_window : string := "int";
ber_bit_err_total_cnt : string := "int";
crcchk_bypass : string := "crcchk_bypass_dis";
crcchk_pipeln : string := "crcchk_pipeln_dis";
crcflag_pipeln : string := "crcflag_pipeln_dis";
crcchk_init : string := "crcchk_init_user_setting";
crcchk_init_user : bit_vector := B"11111111111111111111111111111111";
crcchk_inv : string := "crcchk_inv_dis";
force_align : string := "force_align_dis";
align_del : string := "align_del_en";
control_del : bit_vector := B"11110000";
rxfifo_mode : string := "phase_comp";
master_clk_sel : string := "master_rx_pma_clk";
rd_clk_sel : string := "rd_rx_pma_clk";
gbexp_clken : string := "gbexp_clk_dis";
prbs_clken : string := "prbs_clk_dis";
blksync_clken : string := "blksync_clk_dis";
dispchk_clken : string := "dispchk_clk_dis";
descrm_clken : string := "descrm_clk_dis";
frmsync_clken : string := "frmsync_clk_dis";
dec64b66b_clken : string := "dec64b66b_clk_dis";
ber_clken : string := "ber_clk_dis";
rand_clken : string := "rand_clk_dis";
crcchk_clken : string := "crcchk_clk_dis";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
rxfifo_pempty : string := "pempty_default";
rxfifo_pfull : string := "pfull_default";
rxfifo_full : string := "full_default";
rxfifo_empty : string := "pempty_default";
bitslip_mode : string := "bitslip_dis";
fast_path : string := "fast_path_dis";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_rx_clk_out";
channel_number : integer := 0;
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
test_bus_mode : string := "tx"
);
port (
bercount : out std_logic_vector(5 downto 0);
errorblockcount : out std_logic_vector(7 downto 0);
pcsstatus : out std_logic_vector(0 downto 0);
randomerrorcount : out std_logic_vector(15 downto 0);
prbserrorlatch : out std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rxpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33txorrx : in std_logic_vector(0 downto 0);
rxpmadatavalid : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
rxpldclk : in std_logic_vector(0 downto 0);
rxpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
rxalignen : in std_logic_vector(0 downto 0);
rxalignclr : in std_logic_vector(0 downto 0);
rxrden : in std_logic_vector(0 downto 0);
rxdisparityclr : in std_logic_vector(0 downto 0);
rxclrerrorblockcount : in std_logic_vector(0 downto 0);
rxclrbercount : in std_logic_vector(0 downto 0);
rxbitslip : in std_logic_vector(0 downto 0);
rxprbserrorclr : in std_logic_vector(0 downto 0);
rxclkout : out std_logic_vector(0 downto 0);
rxclkiqout : out std_logic_vector(0 downto 0);
rxdatavalid : out std_logic_vector(0 downto 0);
rxfifoempty : out std_logic_vector(0 downto 0);
rxfifopartialempty : out std_logic_vector(0 downto 0);
rxfifopartialfull : out std_logic_vector(0 downto 0);
rxfifofull : out std_logic_vector(0 downto 0);
rxalignval : out std_logic_vector(0 downto 0);
rxblocklock : out std_logic_vector(0 downto 0);
rxsyncheadererror : out std_logic_vector(0 downto 0);
rxhighber : out std_logic_vector(0 downto 0);
rxframelock : out std_logic_vector(0 downto 0);
rxrdpossts : out std_logic_vector(0 downto 0);
rxrdnegsts : out std_logic_vector(0 downto 0);
rxskipinserted : out std_logic_vector(0 downto 0);
rxrxframe : out std_logic_vector(0 downto 0);
rxpayloadinserted : out std_logic_vector(0 downto 0);
rxsyncworderror : out std_logic_vector(0 downto 0);
rxscramblererror : out std_logic_vector(0 downto 0);
rxskipworderror : out std_logic_vector(0 downto 0);
rxdiagnosticerror : out std_logic_vector(0 downto 0);
rxmetaframeerror : out std_logic_vector(0 downto 0);
rxcrc32error : out std_logic_vector(0 downto 0);
rxdiagnosticstatus : out std_logic_vector(1 downto 0);
rxdata : out std_logic_vector(63 downto 0);
rxcontrol : out std_logic_vector(9 downto 0);
accumdisparity : out std_logic_vector(8 downto 0);
loopbackdatain : in std_logic_vector(39 downto 0);
rxpmadata : in std_logic_vector(39 downto 0);
rxtestdata : out std_logic_vector(19 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_10g_rx_pcs
component stratixv_hssi_10g_tx_pcs
generic (
prot_mode : string := "disable_mode";
sup_mode : string := "full_mode";
ctrl_plane_bonding : string := "individual";
master_clk_sel : string := "master_tx_pma_clk";
wr_clk_sel : string := "wr_tx_pma_clk";
wrfifo_clken : string := "wrfifo_clk_dis";
rdfifo_clken : string := "rdfifo_clk_dis";
frmgen_clken : string := "frmgen_clk_dis";
crcgen_clken : string := "crcgen_clk_dis";
enc64b66b_txsm_clken : string := "enc64b66b_txsm_clk_dis";
scrm_clken : string := "scrm_clk_dis";
dispgen_clken : string := "dispgen_clk_dis";
prbs_clken : string := "prbs_clk_dis";
sqwgen_clken : string := "sqwgen_clk_dis";
gbred_clken : string := "gbred_clk_dis";
gb_tx_idwidth : string := "idwidth_50";
gb_tx_odwidth : string := "odwidth_32";
txfifo_mode : string := "phase_comp";
txfifo_pempty : string := "pempty_default";
txfifo_pfull : string := "pfull_default";
txfifo_empty : string := "empty_default";
txfifo_full : string := "full_default";
frmgen_bypass : string := "frmgen_bypass_dis";
frmgen_pipeln : string := "frmgen_pipeln_dis";
frmgen_mfrm_length : string := "frmgen_mfrm_length_min";
frmgen_mfrm_length_user : string := "int";
frmgen_pyld_ins : string := "frmgen_pyld_ins_dis";
sh_err : string := "sh_err_dis";
frmgen_burst : string := "frmgen_burst_dis";
frmgen_wordslip : string := "frmgen_wordslip_dis";
crcgen_bypass : string := "crcgen_bypass_dis";
crcgen_init : string := "crcgen_init_user_setting";
crcgen_init_user : bit_vector := B"11111111111111111111111111111111";
crcgen_inv : string := "crcgen_inv_dis";
crcgen_err : string := "crcgen_err_dis";
enc_64b66b_10g_mode : string := "enc_64b66b_10g_mode_en";
enc_64b66b_txsm_bypass : string := "enc_64b66b_txsm_bypass_dis";
tx_sm_bypass : string := "tx_sm_bypass_dis";
tx_sm_pipeln : string := "tx_sm_pipeln_dis";
scrm_bypass : string := "scrm_bypass_dis";
test_mode : string := "test_off";
pseudo_random : string := "all_0";
pseudo_seed_a : string := "pseudo_seed_a_user_setting";
pseudo_seed_a_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
pseudo_seed_b : string := "pseudo_seed_b_user_setting";
pseudo_seed_b_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
bit_reverse : string := "bit_reverse_dis";
scrm_seed : string := "scram_seed_user_setting";
scrm_seed_user : bit_vector := B"1111111111111111111111111111111111111111111111111111111111";
scrm_mode : string := "async";
dispgen_bypass : string := "dispgen_bypass_dis";
dispgen_err : string := "dispgen_err_dis";
dispgen_pipeln : string := "dispgen_pipeln_dis";
gb_sel_mode : string := "internal";
sq_wave : string := "sq_wave_4";
bitslip_en : string := "bitslip_dis";
fastpath : string := "fastpath_dis";
distup_bypass_pipeln : string := "distup_bypass_pipeln_dis";
distup_master : string := "distup_master_en";
distdwn_bypass_pipeln : string := "distdwn_bypass_pipeln_dis";
distdwn_master : string := "distdwn_master_en";
compin_sel : string := "compin_master";
comp_cnt : string := "comp_cnt_00";
indv : string := "indv_en";
stretch_num_stages : string := "zero_stage";
stretch_en : string := "stretch_en";
iqtxrx_clkout_sel : string := "iq_tx_pma_clk";
channel_number : integer := 0;
frmgen_sync_word : bit_vector := B"0000000000000000011110001111011001111000111101100111100011110110";
frmgen_scrm_word : bit_vector := B"0000000000000000001010000000000000000000000000000000000000000000";
frmgen_skip_word : bit_vector := B"0000000000000000000111100001111000011110000111100001111000011110";
frmgen_diag_word : bit_vector := B"0000000000000000011001000000000000000000000000000000000000000000";
test_bus_mode : string := "tx";
lpm_type : string := "stratixv_hssi_10g_tx_pcs"
);
port (
txpmaclk : in std_logic_vector(0 downto 0);
pmaclkdiv33lc : in std_logic_vector(0 downto 0);
hardresetn : in std_logic_vector(0 downto 0);
txpldclk : in std_logic_vector(0 downto 0);
txpldrstn : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txdatavalid : in std_logic_vector(0 downto 0);
txbitslip : in std_logic_vector(6 downto 0);
txdiagnosticstatus : in std_logic_vector(1 downto 0);
txwordslip : in std_logic_vector(0 downto 0);
txbursten : in std_logic_vector(0 downto 0);
txdisparityclr : in std_logic_vector(0 downto 0);
txclkout : out std_logic_vector(0 downto 0);
txclkiqout : out std_logic_vector(0 downto 0);
txfifoempty : out std_logic_vector(0 downto 0);
txfifopartialempty : out std_logic_vector(0 downto 0);
txfifopartialfull : out std_logic_vector(0 downto 0);
txfifofull : out std_logic_vector(0 downto 0);
txframe : out std_logic_vector(0 downto 0);
txburstenexe : out std_logic_vector(0 downto 0);
txwordslipexe : out std_logic_vector(0 downto 0);
distupindv : in std_logic_vector(0 downto 0);
distdwnindv : in std_logic_vector(0 downto 0);
distupinwren : in std_logic_vector(0 downto 0);
distdwninwren : in std_logic_vector(0 downto 0);
distupinrden : in std_logic_vector(0 downto 0);
distdwninrden : in std_logic_vector(0 downto 0);
distupoutdv : out std_logic_vector(0 downto 0);
distdwnoutdv : out std_logic_vector(0 downto 0);
distupoutwren : out std_logic_vector(0 downto 0);
distdwnoutwren : out std_logic_vector(0 downto 0);
distupoutrden : out std_logic_vector(0 downto 0);
distdwnoutrden : out std_logic_vector(0 downto 0);
txtestdata : out std_logic_vector(19 downto 0);
txdata : in std_logic_vector(63 downto 0);
txcontrol : in std_logic_vector(8 downto 0);
loopbackdataout : out std_logic_vector(39 downto 0);
txpmadata : out std_logic_vector(39 downto 0);
syncdatain : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_10g_tx_pcs
component stratixv_hssi_8g_pcs_aggregate
generic (
xaui_sm_operation : string := "en_xaui_sm";
dskw_sm_operation : string := "dskw_xaui_sm";
data_agg_bonding : string := "agg_disable";
prot_mode_tx : string := "pipe_g1_tx";
pcs_dw_datapath : string := "sw_data_path";
dskw_control : string := "dskw_write_control";
refclkdig_sel : string := "dis_refclk_dig_sel"
);
port (
refclkdig : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
rcvdclkch0 : in std_logic_vector(0 downto 0);
rcvdclkch1 : in std_logic_vector(0 downto 0);
hardrst : in std_logic_vector(0 downto 0);
txpcsrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
dprioagg : in std_logic_vector(63 downto 0);
rcvdclkout : out std_logic_vector(0 downto 0);
rcvdclkouttop : out std_logic_vector(0 downto 0);
rcvdclkoutbot : out std_logic_vector(0 downto 0);
rdenablesynctopch1 : in std_logic_vector(0 downto 0);
txdatatctopch1 : in std_logic_vector(7 downto 0);
txctltctopch1 : in std_logic_vector(0 downto 0);
syncstatustopch1 : in std_logic_vector(0 downto 0);
rdaligntopch1 : in std_logic_vector(1 downto 0);
aligndetsynctopch1 : in std_logic_vector(1 downto 0);
fifordintopch1 : in std_logic_vector(0 downto 0);
alignstatussynctopch1 : in std_logic_vector(0 downto 0);
cgcomprddintopch1 : in std_logic_vector(1 downto 0);
cgcompwrintopch1 : in std_logic_vector(1 downto 0);
delcondmetintopch1 : in std_logic_vector(0 downto 0);
fifoovrintopch1 : in std_logic_vector(0 downto 0);
latencycompintopch1 : in std_logic_vector(0 downto 0);
insertincompleteintopch1 : in std_logic_vector(0 downto 0);
decdatatopch1 : in std_logic_vector(7 downto 0);
decctltopch1 : in std_logic_vector(0 downto 0);
decdatavalidtopch1 : in std_logic_vector(0 downto 0);
runningdisptopch1 : in std_logic_vector(1 downto 0);
txdatatstopch1 : out std_logic_vector(7 downto 0);
txctltstopch1 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch1 : out std_logic_vector(0 downto 0);
endskwqdtopch1 : out std_logic_vector(0 downto 0);
endskwrdptrstopch1 : out std_logic_vector(0 downto 0);
alignstatustopch1 : out std_logic_vector(0 downto 0);
alignstatussync0topch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch1 : out std_logic_vector(0 downto 0);
cgcomprddalltopch1 : out std_logic_vector(0 downto 0);
cgcompwralltopch1 : out std_logic_vector(0 downto 0);
delcondmet0topch1 : out std_logic_vector(0 downto 0);
insertincomplete0topch1 : out std_logic_vector(0 downto 0);
fifoovr0topch1 : out std_logic_vector(0 downto 0);
latencycomp0topch1 : out std_logic_vector(0 downto 0);
rxdatarstopch1 : out std_logic_vector(7 downto 0);
rxctlrstopch1 : out std_logic_vector(0 downto 0);
rdenablesynctopch0 : in std_logic_vector(0 downto 0);
txdatatctopch0 : in std_logic_vector(7 downto 0);
txctltctopch0 : in std_logic_vector(0 downto 0);
syncstatustopch0 : in std_logic_vector(0 downto 0);
rdaligntopch0 : in std_logic_vector(1 downto 0);
aligndetsynctopch0 : in std_logic_vector(1 downto 0);
fifordintopch0 : in std_logic_vector(0 downto 0);
alignstatussynctopch0 : in std_logic_vector(0 downto 0);
cgcomprddintopch0 : in std_logic_vector(1 downto 0);
cgcompwrintopch0 : in std_logic_vector(1 downto 0);
delcondmetintopch0 : in std_logic_vector(0 downto 0);
fifoovrintopch0 : in std_logic_vector(0 downto 0);
latencycompintopch0 : in std_logic_vector(0 downto 0);
insertincompleteintopch0 : in std_logic_vector(0 downto 0);
decdatatopch0 : in std_logic_vector(7 downto 0);
decctltopch0 : in std_logic_vector(0 downto 0);
decdatavalidtopch0 : in std_logic_vector(0 downto 0);
runningdisptopch0 : in std_logic_vector(1 downto 0);
txdatatstopch0 : out std_logic_vector(7 downto 0);
txctltstopch0 : out std_logic_vector(0 downto 0);
fiforstrdqdtopch0 : out std_logic_vector(0 downto 0);
endskwqdtopch0 : out std_logic_vector(0 downto 0);
endskwrdptrstopch0 : out std_logic_vector(0 downto 0);
alignstatustopch0 : out std_logic_vector(0 downto 0);
alignstatussync0topch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0topch0 : out std_logic_vector(0 downto 0);
cgcomprddalltopch0 : out std_logic_vector(0 downto 0);
cgcompwralltopch0 : out std_logic_vector(0 downto 0);
delcondmet0topch0 : out std_logic_vector(0 downto 0);
insertincomplete0topch0 : out std_logic_vector(0 downto 0);
fifoovr0topch0 : out std_logic_vector(0 downto 0);
latencycomp0topch0 : out std_logic_vector(0 downto 0);
rxdatarstopch0 : out std_logic_vector(7 downto 0);
rxctlrstopch0 : out std_logic_vector(0 downto 0);
rdenablesyncch2 : in std_logic_vector(0 downto 0);
txdatatcch2 : in std_logic_vector(7 downto 0);
txctltcch2 : in std_logic_vector(0 downto 0);
syncstatusch2 : in std_logic_vector(0 downto 0);
rdalignch2 : in std_logic_vector(1 downto 0);
aligndetsyncch2 : in std_logic_vector(1 downto 0);
fifordinch2 : in std_logic_vector(0 downto 0);
alignstatussyncch2 : in std_logic_vector(0 downto 0);
cgcomprddinch2 : in std_logic_vector(1 downto 0);
cgcompwrinch2 : in std_logic_vector(1 downto 0);
delcondmetinch2 : in std_logic_vector(0 downto 0);
fifoovrinch2 : in std_logic_vector(0 downto 0);
latencycompinch2 : in std_logic_vector(0 downto 0);
insertincompleteinch2 : in std_logic_vector(0 downto 0);
decdatach2 : in std_logic_vector(7 downto 0);
decctlch2 : in std_logic_vector(0 downto 0);
decdatavalidch2 : in std_logic_vector(0 downto 0);
runningdispch2 : in std_logic_vector(1 downto 0);
txdatatsch2 : out std_logic_vector(7 downto 0);
txctltsch2 : out std_logic_vector(0 downto 0);
fiforstrdqdch2 : out std_logic_vector(0 downto 0);
endskwqdch2 : out std_logic_vector(0 downto 0);
endskwrdptrsch2 : out std_logic_vector(0 downto 0);
alignstatusch2 : out std_logic_vector(0 downto 0);
alignstatussync0ch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch2 : out std_logic_vector(0 downto 0);
cgcomprddallch2 : out std_logic_vector(0 downto 0);
cgcompwrallch2 : out std_logic_vector(0 downto 0);
delcondmet0ch2 : out std_logic_vector(0 downto 0);
insertincomplete0ch2 : out std_logic_vector(0 downto 0);
fifoovr0ch2 : out std_logic_vector(0 downto 0);
latencycomp0ch2 : out std_logic_vector(0 downto 0);
rxdatarsch2 : out std_logic_vector(7 downto 0);
rxctlrsch2 : out std_logic_vector(0 downto 0);
rdenablesyncch1 : in std_logic_vector(0 downto 0);
txdatatcch1 : in std_logic_vector(7 downto 0);
txctltcch1 : in std_logic_vector(0 downto 0);
syncstatusch1 : in std_logic_vector(0 downto 0);
rdalignch1 : in std_logic_vector(1 downto 0);
aligndetsyncch1 : in std_logic_vector(1 downto 0);
fifordinch1 : in std_logic_vector(0 downto 0);
alignstatussyncch1 : in std_logic_vector(0 downto 0);
cgcomprddinch1 : in std_logic_vector(1 downto 0);
cgcompwrinch1 : in std_logic_vector(1 downto 0);
delcondmetinch1 : in std_logic_vector(0 downto 0);
fifoovrinch1 : in std_logic_vector(0 downto 0);
latencycompinch1 : in std_logic_vector(0 downto 0);
insertincompleteinch1 : in std_logic_vector(0 downto 0);
decdatach1 : in std_logic_vector(7 downto 0);
decctlch1 : in std_logic_vector(0 downto 0);
decdatavalidch1 : in std_logic_vector(0 downto 0);
runningdispch1 : in std_logic_vector(1 downto 0);
txdatatsch1 : out std_logic_vector(7 downto 0);
txctltsch1 : out std_logic_vector(0 downto 0);
fiforstrdqdch1 : out std_logic_vector(0 downto 0);
endskwqdch1 : out std_logic_vector(0 downto 0);
endskwrdptrsch1 : out std_logic_vector(0 downto 0);
alignstatusch1 : out std_logic_vector(0 downto 0);
alignstatussync0ch1 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch1 : out std_logic_vector(0 downto 0);
cgcomprddallch1 : out std_logic_vector(0 downto 0);
cgcompwrallch1 : out std_logic_vector(0 downto 0);
delcondmet0ch1 : out std_logic_vector(0 downto 0);
insertincomplete0ch1 : out std_logic_vector(0 downto 0);
fifoovr0ch1 : out std_logic_vector(0 downto 0);
latencycomp0ch1 : out std_logic_vector(0 downto 0);
rxdatarsch1 : out std_logic_vector(7 downto 0);
rxctlrsch1 : out std_logic_vector(0 downto 0);
rdenablesyncch0 : in std_logic_vector(0 downto 0);
txdatatcch0 : in std_logic_vector(7 downto 0);
txctltcch0 : in std_logic_vector(0 downto 0);
syncstatusch0 : in std_logic_vector(0 downto 0);
rdalignch0 : in std_logic_vector(1 downto 0);
aligndetsyncch0 : in std_logic_vector(1 downto 0);
fifordinch0 : in std_logic_vector(0 downto 0);
alignstatussyncch0 : in std_logic_vector(0 downto 0);
cgcomprddinch0 : in std_logic_vector(1 downto 0);
cgcompwrinch0 : in std_logic_vector(1 downto 0);
delcondmetinch0 : in std_logic_vector(0 downto 0);
fifoovrinch0 : in std_logic_vector(0 downto 0);
latencycompinch0 : in std_logic_vector(0 downto 0);
insertincompleteinch0 : in std_logic_vector(0 downto 0);
decdatach0 : in std_logic_vector(7 downto 0);
decctlch0 : in std_logic_vector(0 downto 0);
decdatavalidch0 : in std_logic_vector(0 downto 0);
runningdispch0 : in std_logic_vector(1 downto 0);
txdatatsch0 : out std_logic_vector(7 downto 0);
txctltsch0 : out std_logic_vector(0 downto 0);
fiforstrdqdch0 : out std_logic_vector(0 downto 0);
endskwqdch0 : out std_logic_vector(0 downto 0);
endskwrdptrsch0 : out std_logic_vector(0 downto 0);
alignstatusch0 : out std_logic_vector(0 downto 0);
alignstatussync0ch0 : out std_logic_vector(0 downto 0);
fifordoutcomp0ch0 : out std_logic_vector(0 downto 0);
cgcomprddallch0 : out std_logic_vector(0 downto 0);
cgcompwrallch0 : out std_logic_vector(0 downto 0);
delcondmet0ch0 : out std_logic_vector(0 downto 0);
insertincomplete0ch0 : out std_logic_vector(0 downto 0);
fifoovr0ch0 : out std_logic_vector(0 downto 0);
latencycomp0ch0 : out std_logic_vector(0 downto 0);
rxdatarsch0 : out std_logic_vector(7 downto 0);
rxctlrsch0 : out std_logic_vector(0 downto 0);
rdenablesyncbotch2 : in std_logic_vector(0 downto 0);
txdatatcbotch2 : in std_logic_vector(7 downto 0);
txctltcbotch2 : in std_logic_vector(0 downto 0);
syncstatusbotch2 : in std_logic_vector(0 downto 0);
rdalignbotch2 : in std_logic_vector(1 downto 0);
aligndetsyncbotch2 : in std_logic_vector(1 downto 0);
fifordinbotch2 : in std_logic_vector(0 downto 0);
alignstatussyncbotch2 : in std_logic_vector(0 downto 0);
cgcomprddinbotch2 : in std_logic_vector(1 downto 0);
cgcompwrinbotch2 : in std_logic_vector(1 downto 0);
delcondmetinbotch2 : in std_logic_vector(0 downto 0);
fifoovrinbotch2 : in std_logic_vector(0 downto 0);
latencycompinbotch2 : in std_logic_vector(0 downto 0);
insertincompleteinbotch2 : in std_logic_vector(0 downto 0);
decdatabotch2 : in std_logic_vector(7 downto 0);
decctlbotch2 : in std_logic_vector(0 downto 0);
decdatavalidbotch2 : in std_logic_vector(0 downto 0);
runningdispbotch2 : in std_logic_vector(1 downto 0);
txdatatsbotch2 : out std_logic_vector(7 downto 0);
txctltsbotch2 : out std_logic_vector(0 downto 0);
fiforstrdqdbotch2 : out std_logic_vector(0 downto 0);
endskwqdbotch2 : out std_logic_vector(0 downto 0);
endskwrdptrsbotch2 : out std_logic_vector(0 downto 0);
alignstatusbotch2 : out std_logic_vector(0 downto 0);
alignstatussync0botch2 : out std_logic_vector(0 downto 0);
fifordoutcomp0botch2 : out std_logic_vector(0 downto 0);
cgcomprddallbotch2 : out std_logic_vector(0 downto 0);
cgcompwrallbotch2 : out std_logic_vector(0 downto 0);
delcondmet0botch2 : out std_logic_vector(0 downto 0);
insertincomplete0botch2 : out std_logic_vector(0 downto 0);
fifoovr0botch2 : out std_logic_vector(0 downto 0);
latencycomp0botch2 : out std_logic_vector(0 downto 0);
rxdatarsbotch2 : out std_logic_vector(7 downto 0);
rxctlrsbotch2 : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_8g_pcs_aggregate
component stratixv_hssi_8g_rx_pcs
generic (
prot_mode : string := "gige";
tx_rx_parallel_loopback : string := "dis_plpbk";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
polarity_inversion : string := "dis_pol_inv";
wa_pd : string := "wa_pd_10";
wa_pd_data : bit_vector := B"0000000000000000000000000000000000000000";
wa_boundary_lock_ctrl : string := "bit_slip";
wa_pld_controlled : string := "dis_pld_ctrl";
wa_sync_sm_ctrl : string := "gige_sync_sm";
wa_rknumber_data : bit_vector := B"00000000";
wa_renumber_data : bit_vector := B"000000";
wa_rgnumber_data : bit_vector := B"00000000";
wa_rosnumber_data : bit_vector := B"00";
wa_kchar : string := "dis_kchar";
wa_det_latency_sync_status_beh : string := "assert_sync_status_non_imm";
wa_clk_slip_spacing : string := "min_clk_slip_spacing";
wa_clk_slip_spacing_data : bit_vector := B"0000010000";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
deskew_pattern : bit_vector := B"1101101000";
deskew_prog_pattern_only : string := "en_deskew_prog_pat_only";
rate_match : string := "dis_rm";
eightb_tenb_decoder : string := "dis_8b10b";
err_flags_sel : string := "err_flags_wa";
polinv_8b10b_dec : string := "dis_polinv_8b10b_dec";
eightbtenb_decoder_output_sel : string := "data_8b10b_decoder";
invalid_code_flag_only : string := "dis_invalid_code_only";
auto_error_replacement : string := "dis_err_replace";
pad_or_edb_error_replace : string := "replace_edb";
byte_deserializer : string := "dis_bds";
byte_order : string := "dis_bo";
re_bo_on_wa : string := "dis_re_bo_on_wa";
bo_pattern : bit_vector := B"00000000000000000000";
bo_pad : bit_vector := B"0000000000";
phase_compensation_fifo : string := "low_latency";
prbs_ver : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_ver : string := "dis_bist";
cdr_ctrl : string := "dis_cdr_ctrl";
cdr_ctrl_rxvalid_mask : string := "dis_rxvalid_mask";
wait_cnt : bit_vector := B"00000000";
mask_cnt : bit_vector := B"1111111111";
auto_deassert_pc_rst_cnt_data : bit_vector := B"00000";
auto_pc_en_cnt_data : bit_vector := B"0000000";
eidle_entry_sd : string := "dis_eidle_sd";
eidle_entry_eios : string := "dis_eidle_eios";
eidle_entry_iei : string := "dis_eidle_iei";
rx_rcvd_clk : string := "rcvd_clk_rcvd_clk";
rx_clk1 : string := "rcvd_clk_clk1";
rx_clk2 : string := "rcvd_clk_clk2";
rx_rd_clk : string := "pld_rx_clk";
dw_one_or_two_symbol_bo : string := "donot_care_one_two_bo";
comp_fifo_rst_pld_ctrl : string := "dis_comp_fifo_rst_pld_ctrl";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
agg_block_sel : string := "same_smrt_pack";
test_bus_sel : string := "test_bus_sel";
wa_rvnumber_data : bit_vector := B"0000000000000";
ctrl_plane_bonding_compensation : string := "dis_compensation";
clock_gate_rx : string := "dis_clk_gating";
prbs_ver_clr_flag : string := "dis_prbs_clr_flag";
hip_mode : string := "dis_hip";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
ctrl_plane_bonding_consumption : string := "individual";
pma_done_count : bit_vector := B"000000000000000000";
test_mode : string := "prbs";
bist_ver_clr_flag : string := "dis_bist_clr_flag";
wa_disp_err_flag : string := "dis_disp_err_flag";
wait_for_phfifo_cnt_data : bit_vector := B"000000";
runlength_check : string := "en_runlength_sw";
test_bus_sel_val : bit_vector := B"0000";
runlength_val : bit_vector := B"000000";
force_signal_detect : string := "en_force_signal_detect";
deskew : string := "dis_deskew";
rx_wr_clk : string := "rx_clk2_div_1_2_4";
rx_clk_free_running : string := "en_rx_clk_free_run";
rx_pcs_urst : string := "en_rx_pcs_urst";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
pipe_if_enable : string := "dis_pipe_rx";
pc_fifo_rst_pld_ctrl : string := "dis_pc_fifo_rst_pld_ctrl";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
ibm_invalid_code : string := "dis_ibm_invalid_code";
channel_number : string := "int";
rx_refclk : string := "dis_refclk_sel"
);
port (
hrdrst : in std_logic_vector(0 downto 0);
rxpcsrst : in std_logic_vector(0 downto 0);
rmfifouserrst : in std_logic_vector(0 downto 0);
phfifouserrst : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
enablecommadetect : in std_logic_vector(0 downto 0);
a1a2size : in std_logic_vector(0 downto 0);
bitslip : in std_logic_vector(0 downto 0);
rmfiforeadenable : in std_logic_vector(0 downto 0);
rmfifowriteenable : in std_logic_vector(0 downto 0);
pldrxclk : in std_logic_vector(0 downto 0);
softresetrclk1 : out std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
bitreversalenable : in std_logic_vector(0 downto 0);
bytereversalenable : in std_logic_vector(0 downto 0);
rcvdclkpma : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(19 downto 0);
sigdetfrompma : in std_logic_vector(0 downto 0);
fiforstrdqd : in std_logic_vector(0 downto 0);
endskwqd : in std_logic_vector(0 downto 0);
endskwrdptrs : in std_logic_vector(0 downto 0);
alignstatus : in std_logic_vector(0 downto 0);
fiforstrdqdtoporbot : in std_logic_vector(0 downto 0);
endskwqdtoporbot : in std_logic_vector(0 downto 0);
endskwrdptrstoporbot : in std_logic_vector(0 downto 0);
alignstatustoporbot : in std_logic_vector(0 downto 0);
datafrinaggblock : in std_logic_vector(7 downto 0);
ctrlfromaggblock : in std_logic_vector(0 downto 0);
rxdatarstoporbot : in std_logic_vector(7 downto 0);
rxcontrolrstoporbot : in std_logic_vector(0 downto 0);
rcvdclk0pma : in std_logic_vector(0 downto 0);
parallelloopback : in std_logic_vector(19 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
byteorder : in std_logic_vector(0 downto 0);
pxfifowrdisable : in std_logic_vector(0 downto 0);
pcfifordenable : in std_logic_vector(0 downto 0);
pmatestbus : in std_logic_vector(7 downto 0);
encodertestbus : in std_logic_vector(9 downto 0);
txctrltestbus : in std_logic_vector(9 downto 0);
phystatusinternal : in std_logic_vector(0 downto 0);
rxvalidinternal : in std_logic_vector(0 downto 0);
rxstatusinternal : in std_logic_vector(2 downto 0);
phystatuspcsgen3 : in std_logic_vector(0 downto 0);
rxvalidpcsgen3 : in std_logic_vector(0 downto 0);
rxstatuspcsgen3 : in std_logic_vector(2 downto 0);
rxdatavalidpcsgen3 : in std_logic_vector(3 downto 0);
rxblkstartpcsgen3 : in std_logic_vector(3 downto 0);
rxsynchdrpcsgen3 : in std_logic_vector(1 downto 0);
rxdatapcsgen3 : in std_logic_vector(63 downto 0);
pipepowerdown : in std_logic_vector(1 downto 0);
rateswitchcontrol : in std_logic_vector(0 downto 0);
gen2ngen1 : in std_logic_vector(0 downto 0);
gen2ngen1bundle : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
pipeloopbk : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
txdiv2syncoutpipeup : in std_logic_vector(0 downto 0);
fifoselectoutpipeup : in std_logic_vector(0 downto 0);
txwrenableoutpipeup : in std_logic_vector(0 downto 0);
txrdenableoutpipeup : in std_logic_vector(0 downto 0);
txdiv2syncoutpipedown : in std_logic_vector(0 downto 0);
fifoselectoutpipedown : in std_logic_vector(0 downto 0);
txwrenableoutpipedown : in std_logic_vector(0 downto 0);
txrdenableoutpipedown : in std_logic_vector(0 downto 0);
alignstatussync0 : in std_logic_vector(0 downto 0);
rmfifordincomp0 : in std_logic_vector(0 downto 0);
cgcomprddall : in std_logic_vector(0 downto 0);
cgcompwrall : in std_logic_vector(0 downto 0);
delcondmet0 : in std_logic_vector(0 downto 0);
fifoovr0 : in std_logic_vector(0 downto 0);
latencycomp0 : in std_logic_vector(0 downto 0);
insertincomplete0 : in std_logic_vector(0 downto 0);
alignstatussync0toporbot : in std_logic_vector(0 downto 0);
fifordincomp0toporbot : in std_logic_vector(0 downto 0);
cgcomprddalltoporbot : in std_logic_vector(0 downto 0);
cgcompwralltoporbot : in std_logic_vector(0 downto 0);
delcondmet0toporbot : in std_logic_vector(0 downto 0);
fifoovr0toporbot : in std_logic_vector(0 downto 0);
latencycomp0toporbot : in std_logic_vector(0 downto 0);
insertincomplete0toporbot : in std_logic_vector(0 downto 0);
alignstatussync : out std_logic_vector(0 downto 0);
fifordoutcomp : out std_logic_vector(0 downto 0);
cgcomprddout : out std_logic_vector(1 downto 0);
cgcompwrout : out std_logic_vector(1 downto 0);
delcondmetout : out std_logic_vector(0 downto 0);
fifoovrout : out std_logic_vector(0 downto 0);
latencycompout : out std_logic_vector(0 downto 0);
insertincompleteout : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(63 downto 0);
parallelrevloopback : out std_logic_vector(19 downto 0);
clocktopld : out std_logic_vector(0 downto 0);
bisterr : out std_logic_vector(0 downto 0);
clk2b : out std_logic_vector(0 downto 0);
rcvdclkpmab : out std_logic_vector(0 downto 0);
syncstatus : out std_logic_vector(0 downto 0);
decoderdatavalid : out std_logic_vector(0 downto 0);
decoderdata : out std_logic_vector(7 downto 0);
decoderctrl : out std_logic_vector(0 downto 0);
runningdisparity : out std_logic_vector(1 downto 0);
selftestdone : out std_logic_vector(0 downto 0);
selftesterr : out std_logic_vector(0 downto 0);
errdata : out std_logic_vector(15 downto 0);
errctrl : out std_logic_vector(1 downto 0);
prbsdone : out std_logic_vector(0 downto 0);
prbserrlt : out std_logic_vector(0 downto 0);
signaldetectout : out std_logic_vector(0 downto 0);
aligndetsync : out std_logic_vector(1 downto 0);
rdalign : out std_logic_vector(1 downto 0);
bistdone : out std_logic_vector(0 downto 0);
runlengthviolation : out std_logic_vector(0 downto 0);
rlvlt : out std_logic_vector(0 downto 0);
rmfifopartialfull : out std_logic_vector(0 downto 0);
rmfifofull : out std_logic_vector(0 downto 0);
rmfifopartialempty : out std_logic_vector(0 downto 0);
rmfifoempty : out std_logic_vector(0 downto 0);
pcfifofull : out std_logic_vector(0 downto 0);
pcfifoempty : out std_logic_vector(0 downto 0);
a1a2k1k2flag : out std_logic_vector(3 downto 0);
byteordflag : out std_logic_vector(0 downto 0);
rxpipeclk : out std_logic_vector(0 downto 0);
channeltestbusout : out std_logic_vector(9 downto 0);
rxpipesoftreset : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
pipedata : out std_logic_vector(63 downto 0);
rxdatavalid : out std_logic_vector(3 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
speedchange : out std_logic_vector(0 downto 0);
eidledetected : out std_logic_vector(0 downto 0);
wordalignboundary : out std_logic_vector(4 downto 0);
rxclkslip : out std_logic_vector(0 downto 0);
eidleexit : out std_logic_vector(0 downto 0);
earlyeios : out std_logic_vector(0 downto 0);
ltr : out std_logic_vector(0 downto 0);
pcswrapbackin : in std_logic_vector(69 downto 0);
rxdivsyncinchnlup : in std_logic_vector(1 downto 0);
rxdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
rxweinchnlup : in std_logic_vector(1 downto 0);
rxweinchnldown : in std_logic_vector(1 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
configselinchnlup : in std_logic_vector(0 downto 0);
configselinchnldown : in std_logic_vector(0 downto 0);
speedchangeinchnlup : in std_logic_vector(0 downto 0);
speedchangeinchnldown : in std_logic_vector(0 downto 0);
pcieswitch : out std_logic_vector(0 downto 0);
rxdivsyncoutchnlup : out std_logic_vector(1 downto 0);
rxweoutchnlup : out std_logic_vector(1 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
resetpcptrsoutchnlup : out std_logic_vector(0 downto 0);
speedchangeoutchnlup : out std_logic_vector(0 downto 0);
configseloutchnlup : out std_logic_vector(0 downto 0);
rxdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rxweoutchnldown : out std_logic_vector(1 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsoutchnldown : out std_logic_vector(0 downto 0);
speedchangeoutchnldown : out std_logic_vector(0 downto 0);
configseloutchnldown : out std_logic_vector(0 downto 0);
resetpcptrsinchnluppipe : out std_logic_vector(0 downto 0);
resetpcptrsinchnldownpipe : out std_logic_vector(0 downto 0);
speedchangeinchnluppipe : out std_logic_vector(0 downto 0);
speedchangeinchnldownpipe : out std_logic_vector(0 downto 0);
disablepcfifobyteserdes : out std_logic_vector(0 downto 0);
resetpcptrs : out std_logic_vector(0 downto 0);
rcvdclkagg : in std_logic_vector(0 downto 0);
rcvdclkaggtoporbot : in std_logic_vector(0 downto 0);
dispcbytegen3 : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
txfifordclkraw : in std_logic_vector(0 downto 0);
resetpcptrsgen3 : in std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_8g_rx_pcs
component stratixv_hssi_8g_tx_pcs
generic (
prot_mode : string := "basic";
hip_mode : string := "dis_hip";
pma_dw : string := "eight_bit";
pcs_bypass : string := "dis_pcs_bypass";
phase_compensation_fifo : string := "low_latency";
tx_compliance_controlled_disparity : string := "dis_txcompliance";
force_kchar : string := "dis_force_kchar";
force_echar : string := "dis_force_echar";
byte_serializer : string := "dis_bs";
data_selection_8b10b_encoder_input : string := "normal_data_path";
eightb_tenb_disp_ctrl : string := "dis_disp_ctrl";
eightb_tenb_encoder : string := "dis_8b10b";
prbs_gen : string := "dis_prbs";
cid_pattern : string := "cid_pattern_0";
cid_pattern_len : bit_vector := B"00000000";
bist_gen : string := "dis_bist";
bit_reversal : string := "dis_bit_reversal";
symbol_swap : string := "dis_symbol_swap";
polarity_inversion : string := "dis_polinv";
tx_bitslip : string := "dis_tx_bitslip";
agg_block_sel : string := "same_smrt_pack";
revloop_back_rm : string := "dis_rev_loopback_rx_rm";
phfifo_write_clk_sel : string := "pld_tx_clk";
ctrl_plane_bonding_consumption : string := "individual";
bypass_pipeline_reg : string := "dis_bypass_pipeline";
ctrl_plane_bonding_distribution : string := "not_master_chnl_distr";
test_mode : string := "prbs";
clock_gate_tx : string := "dis_clk_gating";
self_switch_dw_scaling : string := "dis_self_switch_dw_scaling";
ctrl_plane_bonding_compensation : string := "dis_compensation";
refclk_b_clk_sel : string := "tx_pma_clock";
auto_speed_nego_gen2 : string := "dis_auto_speed_nego_g2";
auto_speed_nego_gen3 : string := "dis_auto_speed_nego_g3";
channel_number : string := "int"
);
port (
txpcsreset : in std_logic_vector(0 downto 0);
refclkdig : in std_logic_vector(0 downto 0);
scanmode : in std_logic_vector(0 downto 0);
datain : in std_logic_vector(43 downto 0);
coreclk : in std_logic_vector(0 downto 0);
invpol : in std_logic_vector(0 downto 0);
xgmdatain : in std_logic_vector(7 downto 0);
xgmctrl : in std_logic_vector(0 downto 0);
xgmdataintoporbottom : in std_logic_vector(7 downto 0);
xgmctrltoporbottom : in std_logic_vector(0 downto 0);
txpmalocalclk : in std_logic_vector(0 downto 0);
enrevparallellpbk : in std_logic_vector(0 downto 0);
revparallellpbkdata : in std_logic_vector(19 downto 0);
phfifowrenable : in std_logic_vector(0 downto 0);
phfiforddisable : in std_logic_vector(0 downto 0);
phfiforeset : in std_logic_vector(0 downto 0);
detectrxloopin : in std_logic_vector(0 downto 0);
powerdn : in std_logic_vector(1 downto 0);
pipeenrevparallellpbkin : in std_logic_vector(0 downto 0);
pipetxswing : in std_logic_vector(0 downto 0);
pipetxdeemph : in std_logic_vector(0 downto 0);
pipetxmargin : in std_logic_vector(2 downto 0);
rxpolarityin : in std_logic_vector(0 downto 0);
polinvrxin : in std_logic_vector(0 downto 0);
elecidleinfersel : in std_logic_vector(2 downto 0);
rateswitch : in std_logic_vector(0 downto 0);
rateswitchbundle : in std_logic_vector(0 downto 0);
prbscidenable : in std_logic_vector(0 downto 0);
bitslipboundaryselect : in std_logic_vector(4 downto 0);
phfifooverflow : out std_logic_vector(0 downto 0);
phfifounderflow : out std_logic_vector(0 downto 0);
clkout : out std_logic_vector(0 downto 0);
clkoutgen3 : out std_logic_vector(0 downto 0);
xgmdataout : out std_logic_vector(7 downto 0);
xgmctrlenable : out std_logic_vector(0 downto 0);
dataout : out std_logic_vector(19 downto 0);
rdenablesync : out std_logic_vector(0 downto 0);
refclkb : out std_logic_vector(0 downto 0);
parallelfdbkout : out std_logic_vector(19 downto 0);
txpipeclk : out std_logic_vector(0 downto 0);
encodertestbus : out std_logic_vector(9 downto 0);
txctrltestbus : out std_logic_vector(9 downto 0);
txpipesoftreset : out std_logic_vector(0 downto 0);
txpipeelectidle : out std_logic_vector(0 downto 0);
detectrxloopout : out std_logic_vector(0 downto 0);
pipepowerdownout : out std_logic_vector(1 downto 0);
pipeenrevparallellpbkout : out std_logic_vector(0 downto 0);
phfifotxswing : out std_logic_vector(0 downto 0);
phfifotxdeemph : out std_logic_vector(0 downto 0);
phfifotxmargin : out std_logic_vector(2 downto 0);
txdataouttogen3 : out std_logic_vector(31 downto 0);
txdatakouttogen3 : out std_logic_vector(3 downto 0);
txdatavalidouttogen3 : out std_logic_vector(3 downto 0);
txblkstartout : out std_logic_vector(3 downto 0);
txsynchdrout : out std_logic_vector(1 downto 0);
txcomplianceout : out std_logic_vector(0 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
rxpolarityout : out std_logic_vector(0 downto 0);
polinvrxout : out std_logic_vector(0 downto 0);
grayelecidleinferselout : out std_logic_vector(2 downto 0);
txdivsyncinchnlup : in std_logic_vector(1 downto 0);
txdivsyncinchnldown : in std_logic_vector(1 downto 0);
wrenableinchnlup : in std_logic_vector(0 downto 0);
wrenableinchnldown : in std_logic_vector(0 downto 0);
rdenableinchnlup : in std_logic_vector(0 downto 0);
rdenableinchnldown : in std_logic_vector(0 downto 0);
fifoselectinchnlup : in std_logic_vector(1 downto 0);
fifoselectinchnldown : in std_logic_vector(1 downto 0);
resetpcptrs : in std_logic_vector(0 downto 0);
resetpcptrsinchnlup : in std_logic_vector(0 downto 0);
resetpcptrsinchnldown : in std_logic_vector(0 downto 0);
dispcbyte : in std_logic_vector(0 downto 0);
txdivsyncoutchnlup : out std_logic_vector(1 downto 0);
txdivsyncoutchnldown : out std_logic_vector(1 downto 0);
rdenableoutchnlup : out std_logic_vector(0 downto 0);
rdenableoutchnldown : out std_logic_vector(0 downto 0);
wrenableoutchnlup : out std_logic_vector(0 downto 0);
wrenableoutchnldown : out std_logic_vector(0 downto 0);
fifoselectoutchnlup : out std_logic_vector(1 downto 0);
fifoselectoutchnldown : out std_logic_vector(1 downto 0);
txfifordclkraw : out std_logic_vector(0 downto 0);
syncdatain : out std_logic_vector(0 downto 0);
observablebyteserdesclock : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_8g_tx_pcs
component stratixv_hssi_common_pcs_pma_interface
generic (
lpm_type : string := "stratixv_hssi_common_pcs_pma_interface";
auto_speed_ena : string := "dis_auto_speed_ena";
force_freqdet : string := "force_freqdet_dis";
func_mode : string := "disable";
pcie_gen3_cap : string := "non_pcie_gen3_cap";
pipe_if_g3pcs : string := "pipe_if_8gpcs";
pma_if_dft_en : string := "dft_dis";
pma_if_dft_val : string := "dft_0";
ppm_cnt_rst : string := "ppm_cnt_rst_dis";
ppm_deassert_early : string := "deassert_early_dis";
ppm_gen1_2_cnt : string := "cnt_32k";
ppm_post_eidle_delay : string := "cnt_200_cycles";
ppmsel : string := "ppmsel_default";
prot_mode : string := "disabled_prot_mode";
refclk_dig_sel : string := "refclk_dig_dis";
selectpcs : string := "eight_g_pcs";
sup_mode : string := "full_mode"
);
port (
fref : in std_logic;
clklow : in std_logic;
pmapcieswdone : in std_logic_vector(1 downto 0);
pmarxfound : in std_logic;
pmarxdetectvalid : in std_logic;
pmahclk : in std_logic;
pldoffcalen : in std_logic;
aggrcvdclkagg : in std_logic;
aggtxdatats : in std_logic_vector(7 downto 0);
aggtxctlts : in std_logic;
aggfiforstrdqd : in std_logic;
aggendskwqd : in std_logic;
aggendskwrdptrs : in std_logic;
aggalignstatus : in std_logic;
aggalignstatussync0 : in std_logic;
aggcgcomprddall : in std_logic;
aggcgcompwrall : in std_logic;
aggfifordincomp0 : in std_logic;
aggdelcondmet0 : in std_logic;
agginsertincomplete0 : in std_logic;
aggfifoovr0 : in std_logic;
agglatencycomp0 : in std_logic;
aggrxdatars : in std_logic_vector(7 downto 0);
aggrxcontrolrs : in std_logic;
aggrcvdclkaggtoporbot : in std_logic;
aggtxdatatstoporbot : in std_logic_vector(7 downto 0);
aggtxctltstoporbot : in std_logic;
aggfiforstrdqdtoporbot : in std_logic;
aggendskwqdtoporbot : in std_logic;
aggendskwrdptrstoporbot : in std_logic;
aggalignstatustoporbot : in std_logic;
aggalignstatussync0toporbot : in std_logic;
aggcgcomprddalltoporbot : in std_logic;
aggcgcompwralltoporbot : in std_logic;
aggfifordincomp0toporbot : in std_logic;
aggdelcondmet0toporbot : in std_logic;
agginsertincomplete0toporbot : in std_logic;
aggfifoovr0toporbot : in std_logic;
agglatencycomp0toporbot : in std_logic;
aggrxdatarstoporbot : in std_logic_vector(7 downto 0);
aggrxcontrolrstoporbot : in std_logic;
pcsgen3pmapcieswitch : in std_logic_vector(1 downto 0);
pcsgen3pmatxmargin : in std_logic_vector(2 downto 0);
pcsgen3pmatxdeemph : in std_logic;
pcsgen3pmatxswing : in std_logic;
pcsgen3pmacurrentcoeff : in std_logic_vector(17 downto 0);
pcsgen3pmacurrentrxpreset : in std_logic_vector(2 downto 0);
pcsgen3pmatxelecidle : in std_logic;
pcsgen3pmatxdetectrx : in std_logic;
pcsgen3ppmeidleexit : in std_logic;
pcsgen3pmaltr : in std_logic;
pcsgen3pmaearlyeios : in std_logic;
pcs8gpcieswitch : in std_logic;
pcs8gtxelecidle : in std_logic;
pcs8gtxdetectrx : in std_logic;
pcs8gearlyeios : in std_logic;
pcs8gtxdeemphpma : in std_logic;
pcs8gtxmarginpma : in std_logic_vector(2 downto 0);
pcs8gtxswingpma : in std_logic;
pcs8gltrpma : in std_logic;
pcs8geidleexit : in std_logic;
pcsaggtxpcsrst : in std_logic;
pcsaggrxpcsrst : in std_logic;
pcsaggtxdatatc : in std_logic_vector(7 downto 0);
pcsaggtxctltc : in std_logic;
pcsaggrdenablesync : in std_logic;
pcsaggsyncstatus : in std_logic;
pcsaggaligndetsync : in std_logic_vector(1 downto 0);
pcsaggrdalign : in std_logic_vector(1 downto 0);
pcsaggalignstatussync : in std_logic;
pcsaggfifordoutcomp : in std_logic;
pcsaggcgcomprddout : in std_logic_vector(1 downto 0);
pcsaggcgcompwrout : in std_logic_vector(1 downto 0);
pcsaggdelcondmetout : in std_logic;
pcsaggfifoovrout : in std_logic;
pcsagglatencycompout : in std_logic;
pcsagginsertincompleteout : in std_logic;
pcsaggdecdatavalid : in std_logic;
pcsaggdecdata : in std_logic_vector(7 downto 0);
pcsaggdecctl : in std_logic;
pcsaggrunningdisp : in std_logic_vector(1 downto 0);
pldrxclkslip : in std_logic;
pldhardreset : in std_logic;
pcsscanmoden : in std_logic;
pcsscanshiftn : in std_logic;
pcsrefclkdig : in std_logic;
pcsaggscanmoden : in std_logic;
pcsaggscanshiftn : in std_logic;
pcsaggrefclkdig : in std_logic;
pcsgen3gen3datasel : in std_logic;
pldlccmurstb : in std_logic;
pmaoffcaldonein : in std_logic;
pmarxpmarstb : in std_logic;
pmahardreset : out std_logic;
freqlock : out std_logic;
pmapcieswitch : out std_logic_vector(1 downto 0);
pmaearlyeios : out std_logic;
pmatxdetectrx : out std_logic;
pmatxelecidle : out std_logic;
pmatxdeemph : out std_logic;
pmatxswing : out std_logic;
pmatxmargin : out std_logic_vector(2 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmaoffcaldoneout : out std_logic;
pmalccmurstb : out std_logic;
pmaltr : out std_logic;
aggtxpcsrst : out std_logic;
aggrxpcsrst : out std_logic;
aggtxdatatc : out std_logic_vector(7 downto 0);
aggtxctltc : out std_logic;
aggrdenablesync : out std_logic;
aggsyncstatus : out std_logic;
aggaligndetsync : out std_logic_vector(1 downto 0);
aggrdalign : out std_logic_vector(1 downto 0);
aggalignstatussync : out std_logic;
aggfifordoutcomp : out std_logic;
aggcgcomprddout : out std_logic_vector(1 downto 0);
aggcgcompwrout : out std_logic_vector(1 downto 0);
aggdelcondmetout : out std_logic;
aggfifoovrout : out std_logic;
agglatencycompout : out std_logic;
agginsertincompleteout : out std_logic;
aggdecdatavalid : out std_logic;
aggdecdata : out std_logic_vector(7 downto 0);
aggdecctl : out std_logic;
aggrunningdisp : out std_logic_vector(1 downto 0);
pcsgen3pmarxdetectvalid : out std_logic;
pcsgen3pmarxfound : out std_logic;
pcsgen3pmapcieswdone : out std_logic_vector(1 downto 0);
pcsgen3pllfixedclk : out std_logic;
pcsaggrcvdclkagg : out std_logic;
pcsaggtxdatats : out std_logic_vector(7 downto 0);
pcsaggtxctlts : out std_logic;
pcsaggfiforstrdqd : out std_logic;
pcsaggendskwqd : out std_logic;
pcsaggendskwrdptrs : out std_logic;
pcsaggalignstatus : out std_logic;
pcsaggalignstatussync0 : out std_logic;
pcsaggcgcomprddall : out std_logic;
pcsaggcgcompwrall : out std_logic;
pcsaggfifordincomp0 : out std_logic;
pcsaggdelcondmet0 : out std_logic;
pcsagginsertincomplete0 : out std_logic;
pcsaggfifoovr0 : out std_logic;
pcsagglatencycomp0 : out std_logic;
pcsaggrxdatars : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrs : out std_logic;
pcsaggrcvdclkaggtoporbot : out std_logic;
pcsaggtxdatatstoporbot : out std_logic_vector(7 downto 0);
pcsaggtxctltstoporbot : out std_logic;
pcsaggfiforstrdqdtoporbot : out std_logic;
pcsaggendskwqdtoporbot : out std_logic;
pcsaggendskwrdptrstoporbot : out std_logic;
pcsaggalignstatustoporbot : out std_logic;
pcsaggalignstatussync0toporbot : out std_logic;
pcsaggcgcomprddalltoporbot : out std_logic;
pcsaggcgcompwralltoporbot : out std_logic;
pcsaggfifordincomp0toporbot : out std_logic;
pcsaggdelcondmet0toporbot : out std_logic;
pcsagginsertincomplete0toporbot : out std_logic;
pcsaggfifoovr0toporbot : out std_logic;
pcsagglatencycomp0toporbot : out std_logic;
pcsaggrxdatarstoporbot : out std_logic_vector(7 downto 0);
pcsaggrxcontrolrstoporbot : out std_logic;
pcs8grxdetectvalid : out std_logic;
pcs8gpmarxfound : out std_logic;
pcs8ggen2ngen1 : out std_logic;
pcs8gpowerstatetransitiondone : out std_logic;
ppmcntlatch : out std_logic_vector(7 downto 0);
pldhclkout : out std_logic;
aggscanmoden : out std_logic;
aggscanshiftn : out std_logic;
aggrefclkdig : out std_logic;
pmaoffcalen : out std_logic;
pmafrefout : out std_logic;
pmaclklowout : out std_logic
);
end component; --stratixv_hssi_common_pcs_pma_interface
component stratixv_hssi_common_pld_pcs_interface
generic (
lpm_type : string := "stratixv_hssi_common_pld_pcs_interface";
data_source : string := "pld";
emsip_enable : string := "emsip_disable";
selectpcs : string := "eight_g_pcs"
);
port (
pldhardresetin : in std_logic;
pldscanmoden : in std_logic;
pldscanshiftn : in std_logic;
pldgen3refclkdig : in std_logic;
pld10grefclkdig : in std_logic;
pld8grefclkdig : in std_logic;
pldaggrefclkdig : in std_logic;
pldpcspmaifrefclkdig : in std_logic;
pldrate : in std_logic_vector(1 downto 0);
pldeidleinfersel : in std_logic_vector(2 downto 0);
pld8gsoftresetallhssi : in std_logic;
pld8gplniotri : in std_logic;
pld8gprbsciden : in std_logic;
pld8gltr : in std_logic;
pld8gtxelecidle : in std_logic;
pld8gtxdetectrxloopback : in std_logic;
pld8gtxdeemph : in std_logic;
pld8gtxmargin : in std_logic_vector(2 downto 0);
pld8gtxswing : in std_logic;
pld8grxpolarity : in std_logic;
pld8gpowerdown : in std_logic_vector(1 downto 0);
pldgen3currentcoeff : in std_logic_vector(17 downto 0);
pldgen3currentrxpreset : in std_logic_vector(2 downto 0);
pcs10gtestdata : in std_logic_vector(19 downto 0);
pcs8gchnltestbusout : in std_logic_vector(9 downto 0);
pcs8grxvalid : in std_logic;
pcs8grxelecidle : in std_logic;
pcs8grxstatus : in std_logic_vector(2 downto 0);
pcs8gphystatus : in std_logic;
pldhclkin : in std_logic;
pcsgen3pldasyncstatus : in std_logic_vector(5 downto 0);
pcsgen3testout : in std_logic_vector(19 downto 0);
emsippcsreset : in std_logic_vector(2 downto 0);
emsippcsctrl : in std_logic_vector(38 downto 0);
pmafref : in std_logic;
pmaclklow : in std_logic;
pmaoffcaldone : in std_logic;
pldoffcalenin : in std_logic;
pcsgen3masktxpll : in std_logic;
rcomemsip : in std_logic;
rcomhipena : in std_logic;
rcomblocksel : in std_logic_vector(1 downto 0);
pldtestdata : out std_logic_vector(19 downto 0);
pld8grxvalid : out std_logic;
pld8grxelecidle : out std_logic;
pld8grxstatus : out std_logic_vector(2 downto 0);
pld8gphystatus : out std_logic;
pldgen3pldasyncstatus : out std_logic_vector(5 downto 0);
pcs10ghardresetn : out std_logic;
pcs10gscanmoden : out std_logic;
pcs10gscanshiftn : out std_logic;
pcs10grefclkdig : out std_logic;
pcs8ghardreset : out std_logic;
pcs8gsoftresetallhssi : out std_logic;
pcs8gplniotri : out std_logic;
pcs8gscanmoden : out std_logic;
pcs8gscanshiftn : out std_logic;
pcs8grefclkdig : out std_logic;
pcs8gprbsciden : out std_logic;
pcs8gltr : out std_logic;
pcs8gtxelecidle : out std_logic;
pcs8gtxdetectrxloopback : out std_logic;
pcs8gtxdeemph : out std_logic;
pcs8gtxmargin : out std_logic_vector(2 downto 0);
pcs8gtxswing : out std_logic;
pcs8grxpolarity : out std_logic;
pcs8grate : out std_logic;
pcs8gpowerdown : out std_logic_vector(1 downto 0);
pcs8geidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3pcsdigclk : out std_logic;
pcsgen3rate : out std_logic_vector(1 downto 0);
pcsgen3eidleinfersel : out std_logic_vector(2 downto 0);
pcsgen3scanmoden : out std_logic;
pcsgen3scanshiftn : out std_logic;
pcsgen3pldltr : out std_logic;
pldhardresetout : out std_logic;
pcsgen3currentcoeff : out std_logic_vector(17 downto 0);
pcsgen3currentrxpreset : out std_logic_vector(2 downto 0);
pcsaggrefclkdig : out std_logic;
pcspcspmaifrefclkdig : out std_logic;
pcsaggscanmoden : out std_logic;
pcsaggscanshiftn : out std_logic;
pcspcspmaifscanmoden : out std_logic;
pcspcspmaifscanshiftn : out std_logic;
emsippcsclkout : out std_logic_vector(2 downto 0);
emsippcsstatus : out std_logic_vector(13 downto 0);
pldfref : out std_logic;
pldclklow : out std_logic;
emsipenabledusermode : out std_logic;
pldoffcalenout : out std_logic;
pldoffcaldone : out std_logic;
pldgen3masktxpll : out std_logic
);
end component; --stratixv_hssi_common_pld_pcs_interface
component stratixv_hssi_pipe_gen1_2
generic (
prot_mode : string := "pipe_g1";
hip_mode : string := "dis_hip";
tx_pipe_enable : string := "dis_pipe_tx";
rx_pipe_enable : string := "dis_pipe_rx";
pipe_byte_de_serializer_en : string := "dont_care_bds";
txswing : string := "dis_txswing";
rxdetect_bypass : string := "dis_rxdetect_bypass";
error_replace_pad : string := "replace_edb";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle : string := "dis_phystatus_rst_toggle";
elecidle_delay : string := "elec_idle_delay";
elec_idle_delay_val : bit_vector := B"000";
phy_status_delay : string := "phystatus_delay";
phystatus_delay_val : bit_vector := B"000";
ctrl_plane_bonding_consumption : string := "individual";
byte_deserializer : string := "dis_bds"
);
port (
pipetxclk : in std_logic_vector(0 downto 0);
piperxclk : in std_logic_vector(0 downto 0);
refclkb : in std_logic_vector(0 downto 0);
txpipereset : in std_logic_vector(0 downto 0);
rxpipereset : in std_logic_vector(0 downto 0);
refclkbreset : in std_logic_vector(0 downto 0);
rrdwidthrx : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txelecidlein : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txswingport : in std_logic_vector(0 downto 0);
txdch : in std_logic_vector(43 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
sigdetni : in std_logic_vector(0 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdch : out std_logic_vector(63 downto 0);
phystatus : out std_logic_vector(0 downto 0);
revloopback : in std_logic_vector(0 downto 0);
polinvrx : in std_logic_vector(0 downto 0);
txd : out std_logic_vector(43 downto 0);
revloopbk : out std_logic_vector(0 downto 0);
revloopbkpcsgen3 : in std_logic_vector(0 downto 0);
rxelectricalidlepcsgen3 : in std_logic_vector(0 downto 0);
txelecidlecomp : in std_logic_vector(0 downto 0);
rindvrx : in std_logic_vector(0 downto 0);
rmasterrx : in std_logic_vector(1 downto 0);
speedchange : in std_logic_vector(0 downto 0);
speedchangechnlup : in std_logic_vector(0 downto 0);
speedchangechnldown : in std_logic_vector(0 downto 0);
rxd : in std_logic_vector(63 downto 0);
txelecidleout : out std_logic_vector(0 downto 0);
txdetectrx : out std_logic_vector(0 downto 0);
powerstate : out std_logic_vector(3 downto 0);
rxfound : in std_logic_vector(0 downto 0);
rxdetectvalid : in std_logic_vector(0 downto 0);
rxelectricalidle : in std_logic_vector(0 downto 0);
powerstatetransitiondone : in std_logic_vector(0 downto 0);
powerstatetransitiondoneena : in std_logic_vector(0 downto 0);
txdeemphint : out std_logic_vector(0 downto 0);
txmarginint : out std_logic_vector(2 downto 0);
txswingint : out std_logic_vector(0 downto 0);
rxelectricalidleout : out std_logic_vector(0 downto 0);
rxpolaritypcsgen3 : in std_logic_vector(0 downto 0);
polinvrxint : out std_logic_vector(0 downto 0);
speedchangeout : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_pipe_gen1_2
component stratixv_hssi_pipe_gen3
generic (
mode : string := "pipe_g1";
ctrl_plane_bonding : string := "individual";
pipe_clk_sel : string := "func_clk";
rate_match_pad_insertion : string := "dis_rm_fifo_pad_ins";
ind_error_reporting : string := "dis_ind_error_reporting";
phystatus_rst_toggle_g3 : string := "dis_phystatus_rst_toggle_g3";
phystatus_rst_toggle_g12 : string := "dis_phystatus_rst_toggle";
cdr_control : string := "en_cdr_ctrl";
cid_enable : string := "en_cid_mode";
parity_chk_ts1 : string := "en_ts1_parity_chk";
rxvalid_mask : string := "rxvalid_mask_en";
ph_fifo_reg_mode : string := "phfifo_reg_mode_dis";
test_mode_timers : string := "dis_test_mode_timers";
inf_ei_enable : string := "dis_inf_ei";
spd_chnge_g2_sel : string := "false";
cp_up_mstr : string := "false";
cp_dwn_mstr : string := "false";
cp_cons_sel : string := "cp_cons_default";
elecidle_delay_g12_data : bit_vector := B"000";
elecidle_delay_g12 : string := "elecidle_delay_g12";
elecidle_delay_g3_data : bit_vector := B"000";
elecidle_delay_g3 : string := "elecidle_delay_g3";
phy_status_delay_g12_data : bit_vector := B"000";
phy_status_delay_g12 : string := "phy_status_delay_g12";
phy_status_delay_g3_data : bit_vector := B"000";
phy_status_delay_g3 : string := "phy_status_delay_g3";
sigdet_wait_counter_data : bit_vector := B"00000000";
sigdet_wait_counter : string := "sigdet_wait_counter";
data_mask_count_val : bit_vector := B"0000000000";
data_mask_count : string := "data_mask_count";
pma_done_counter_data : bit_vector := B"000000000000000000";
pma_done_counter : string := "pma_done_count";
pc_en_counter_data : bit_vector := B"00000";
pc_en_counter : string := "pc_en_count";
pc_rst_counter_data : bit_vector := B"0000";
pc_rst_counter : string := "pc_rst_count";
phfifo_flush_wait_data : bit_vector := B"000000";
phfifo_flush_wait : string := "phfifo_flush_wait";
asn_clk_enable : string := "false";
free_run_clk_enable : string := "true";
asn_enable : string := "dis_asn"
);
port (
rcvdclk : in std_logic_vector(0 downto 0);
txpmaclk : in std_logic_vector(0 downto 0);
pcsdigclk : in std_logic_vector(0 downto 0);
pllfixedclk : in std_logic_vector(0 downto 0);
rtxgen3capen : in std_logic_vector(0 downto 0);
rrxgen3capen : in std_logic_vector(0 downto 0);
rtxdigclksel : in std_logic_vector(0 downto 0);
rrxdigclksel : in std_logic_vector(0 downto 0);
rxrstn : in std_logic_vector(0 downto 0);
txrstn : in std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
pldasyncstatus : out std_logic_vector(5 downto 0);
testout : out std_logic_vector(19 downto 0);
gen3datasel : out std_logic_vector(0 downto 0);
gen3clksel : out std_logic_vector(0 downto 0);
pcsrst : out std_logic_vector(0 downto 0);
dispcbyte : out std_logic_vector(0 downto 0);
resetpcprts : out std_logic_vector(0 downto 0);
shutdownclk : out std_logic_vector(0 downto 0);
txdata : in std_logic_vector(31 downto 0);
txdatak : in std_logic_vector(3 downto 0);
txdataskip : in std_logic_vector(0 downto 0);
txsynchdr : in std_logic_vector(1 downto 0);
txblkstart : in std_logic_vector(0 downto 0);
txelecidle : in std_logic_vector(0 downto 0);
txdetectrxloopback : in std_logic_vector(0 downto 0);
txcompliance : in std_logic_vector(0 downto 0);
rxpolarity : in std_logic_vector(0 downto 0);
powerdown : in std_logic_vector(1 downto 0);
rate : in std_logic_vector(1 downto 0);
txmargin : in std_logic_vector(2 downto 0);
txdeemph : in std_logic_vector(0 downto 0);
txswing : in std_logic_vector(0 downto 0);
eidleinfersel : in std_logic_vector(2 downto 0);
currentcoeff : in std_logic_vector(17 downto 0);
currentrxpreset : in std_logic_vector(2 downto 0);
rxupdatefc : in std_logic_vector(0 downto 0);
rxdataskip : out std_logic_vector(3 downto 0);
rxsynchdr : out std_logic_vector(1 downto 0);
rxblkstart : out std_logic_vector(3 downto 0);
rxvalid : out std_logic_vector(0 downto 0);
phystatus : out std_logic_vector(0 downto 0);
rxelecidle : out std_logic_vector(0 downto 0);
rxstatus : out std_logic_vector(2 downto 0);
rxdataint : in std_logic_vector(31 downto 0);
rxdatakint : in std_logic_vector(3 downto 0);
rxdataskipint : in std_logic_vector(0 downto 0);
rxsynchdrint : in std_logic_vector(1 downto 0);
rxblkstartint : in std_logic_vector(0 downto 0);
txdataint : out std_logic_vector(31 downto 0);
txdatakint : out std_logic_vector(3 downto 0);
txdataskipint : out std_logic_vector(0 downto 0);
txsynchdrint : out std_logic_vector(1 downto 0);
txblkstartint : out std_logic_vector(0 downto 0);
testinfei : out std_logic_vector(18 downto 0);
eidetint : in std_logic_vector(0 downto 0);
eipartialdetint : in std_logic_vector(0 downto 0);
idetint : in std_logic_vector(0 downto 0);
blkalgndint : in std_logic_vector(0 downto 0);
clkcompinsertint : in std_logic_vector(0 downto 0);
clkcompdeleteint : in std_logic_vector(0 downto 0);
clkcompoverflint : in std_logic_vector(0 downto 0);
clkcompundflint : in std_logic_vector(0 downto 0);
errdecodeint : in std_logic_vector(0 downto 0);
rcvlfsrchkint : in std_logic_vector(0 downto 0);
errencodeint : in std_logic_vector(0 downto 0);
rxpolarityint : out std_logic_vector(0 downto 0);
revlpbkint : out std_logic_vector(0 downto 0);
inferredrxvalidint : out std_logic_vector(0 downto 0);
rxd8gpcsin : in std_logic_vector(63 downto 0);
rxelecidle8gpcsin : in std_logic_vector(0 downto 0);
pldltr : in std_logic_vector(0 downto 0);
rxd8gpcsout : out std_logic_vector(63 downto 0);
revlpbk8gpcsout : out std_logic_vector(0 downto 0);
pmarxdetectvalid : in std_logic_vector(0 downto 0);
pmarxfound : in std_logic_vector(0 downto 0);
pmasignaldet : in std_logic_vector(0 downto 0);
pmapcieswdone : in std_logic_vector(1 downto 0);
pmapcieswitch : out std_logic_vector(1 downto 0);
pmatxmargin : out std_logic_vector(2 downto 0);
pmatxdeemph : out std_logic_vector(0 downto 0);
pmatxswing : out std_logic_vector(0 downto 0);
pmacurrentcoeff : out std_logic_vector(17 downto 0);
pmacurrentrxpreset : out std_logic_vector(2 downto 0);
pmatxelecidle : out std_logic_vector(0 downto 0);
pmatxdetectrx : out std_logic_vector(0 downto 0);
ppmeidleexit : out std_logic_vector(0 downto 0);
pmaltr : out std_logic_vector(0 downto 0);
pmaearlyeios : out std_logic_vector(0 downto 0);
pmarxdetpd : out std_logic_vector(0 downto 0);
bundlingindown : in std_logic_vector(9 downto 0);
bundlingoutdown : out std_logic_vector(9 downto 0);
rxpolarity8gpcsout : out std_logic_vector(0 downto 0);
speedchangeg2 : in std_logic_vector(0 downto 0);
bundlingoutup : out std_logic_vector(9 downto 0);
bundlinginup : in std_logic_vector(9 downto 0);
masktxpll : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_pipe_gen3
component stratixv_hssi_pma_cdr_refclk_select_mux
generic (
lpm_type : string := "stratixv_hssi_pma_cdr_refclk_select_mux";
channel_number : integer := 0;
refclk_select : string := "ref_iqclk0";
reference_clock_frequency : string := "0 ps"
);
port (
calclk : in std_logic;
ffplloutbot : in std_logic;
ffpllouttop : in std_logic;
pldclk : in std_logic;
refiqclk0 : in std_logic;
refiqclk1 : in std_logic;
refiqclk10 : in std_logic;
refiqclk2 : in std_logic;
refiqclk3 : in std_logic;
refiqclk4 : in std_logic;
refiqclk5 : in std_logic;
refiqclk6 : in std_logic;
refiqclk7 : in std_logic;
refiqclk8 : in std_logic;
refiqclk9 : in std_logic;
rxiqclk0 : in std_logic;
rxiqclk1 : in std_logic;
rxiqclk10 : in std_logic;
rxiqclk2 : in std_logic;
rxiqclk3 : in std_logic;
rxiqclk4 : in std_logic;
rxiqclk5 : in std_logic;
rxiqclk6 : in std_logic;
rxiqclk7 : in std_logic;
rxiqclk8 : in std_logic;
rxiqclk9 : in std_logic;
clkout : out std_logic
);
end component; --stratixv_hssi_pma_cdr_refclk_select_mux
component stratixv_hssi_pma_rx_buf
generic (
lpm_type : string := "stratixv_hssi_pma_rx_buf";
adce_pd : string := "false";
bypass_eqz_stages_123 : string := "all_stages_enabled";
eq_bw_sel : string := "bw_full_12p5";
input_vcm_sel : string := "high_vcm";
pdb_dfe : string := "false";
pdb_sd : string := "false";
qpi_enable : string := "false";
rx_dc_gain : string := "dc_gain_0db";
rx_sel_bias_source : string := "bias_vcmdrv";
sd_off : string := "clk_divrx_2";
sd_on : string := "data_pulse_6";
sd_threshold : string := "sdlv_30mv";
serial_loopback : string := "lpbkp_dis";
term_sel : string := "r_100ohm";
vccela_supply_voltage : string := "vccela_1p0v";
vcm_sel : string := "vtt_0p7v";
channel_number : integer := 0
);
port (
ck0sigdet : in std_logic;
datain : in std_logic;
fined2aout : in std_logic;
lpbkp : in std_logic;
occalen : in std_logic;
refclklpbk : in std_logic;
rstn : in std_logic;
rxqpipulldn : in std_logic;
slpbk : in std_logic;
dataout : out std_logic;
nonuserfrompmaux : out std_logic;
rdlpbkp : out std_logic;
rxpadce : out std_logic;
sd : out std_logic
);
end component; --stratixv_hssi_pma_rx_buf
component stratixv_hssi_pma_rx_deser
generic (
lpm_type : string := "stratixv_hssi_pma_rx_deser";
auto_negotiation : string := "false";
bit_slip_bypass : string := "false";
mode : integer := 8;
sdclk_enable : string := "false";
vco_bypass : string := "vco_bypass_normal";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
bslip : in std_logic;
clk90b : in std_logic;
clk270b : in std_logic;
deven : in std_logic;
dodd : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pfdmodelock : in std_logic;
rstn : in std_logic;
clk33pcs : out std_logic;
clkdivrx : out std_logic;
clkdivrxrx : out std_logic;
dout : out std_logic_vector(39 downto 0);
pciel : out std_logic;
pciem : out std_logic
);
end component; --stratixv_hssi_pma_rx_deser
component stratixv_hssi_pma_tx_buf
generic (
lpm_type : string := "stratixv_hssi_pma_tx_buf";
elec_idl_gate_ctrl : string := "true";
pre_emp_switching_ctrl_1st_post_tap : string := "fir_1pt_disabled";
pre_emp_switching_ctrl_2nd_post_tap : string := "fir_2pt_disabled";
pre_emp_switching_ctrl_pre_tap : string := "fir_pre_disabled";
qpi_en : string := "false";
rx_det : string := "mode_0";
rx_det_output_sel : string := "rx_det_pcie_out";
rx_det_pdb : string := "true";
sig_inv_2nd_tap : string := "false";
sig_inv_pre_tap : string := "false";
slew_rate_ctrl : string := "slew_30ps";
term_sel : string := "r_100ohm";
vod_switching_ctrl_main_tap : string := "fir_main_2p0ma";
channel_number : integer := 0
);
port (
datain : in std_logic;
rxdetclk : in std_logic;
txdetrx : in std_logic;
txelecidl : in std_logic;
txqpipulldn : in std_logic;
txqpipullup : in std_logic;
compass : out std_logic;
dataout : out std_logic;
detecton : out std_logic_vector(1 downto 0);
fixedclkout : out std_logic;
nonuserfrompmaux : out std_logic;
probepass : out std_logic;
rxdetectvalid : out std_logic;
rxfound : out std_logic
);
end component; --stratixv_hssi_pma_tx_buf
component stratixv_hssi_pma_tx_cgb
generic (
lpm_type : string := "stratixv_hssi_pma_tx_cgb";
auto_negotiation : string := "false";
x1_div_m_sel : integer := 1;
channel_number : integer := 0;
data_rate : string := "";
mode : integer := 8;
rx_iqclk_sel : string := "cgb_x1_n_div";
tx_mux_power_down : string := "normal";
x1_clock_source_sel : string := "x1_clk_unused";
xn_clock_source_sel : string := "cgb_xn_unused";
xn_network_driver : string := "enable_clock_entwork_driver";
cgb_iqclk_sel : string := "cgb_x1_n_div";
ht_delay_enable : string := "false"
);
port (
clkbcdr1adj : in std_logic;
clkbcdr1loc : in std_logic;
clkbcdrloc : in std_logic;
clkbdnseg : in std_logic;
clkbffpll : in std_logic;
clkblcb : in std_logic;
clkblct : in std_logic;
clkbupseg : in std_logic;
clkcdr1adj : in std_logic;
clkcdr1loc : in std_logic;
clkcdrloc : in std_logic;
clkdnseg : in std_logic;
clkffpll : in std_logic;
clklcb : in std_logic;
clklct : in std_logic;
clkupseg : in std_logic;
cpulsex6adj : in std_logic;
cpulsex6loc : in std_logic;
cpulsexndn : in std_logic;
cpulsexnup : in std_logic;
hfclknx6adj : in std_logic;
hfclknx6loc : in std_logic;
hfclknxndn : in std_logic;
hfclknxnup : in std_logic;
hfclkpx6adj : in std_logic;
hfclkpx6loc : in std_logic;
hfclkpxndn : in std_logic;
hfclkpxnup : in std_logic;
lfclknx6adj : in std_logic;
lfclknx6loc : in std_logic;
lfclknxndn : in std_logic;
lfclknxnup : in std_logic;
lfclkpx6adj : in std_logic;
lfclkpx6loc : in std_logic;
lfclkpxndn : in std_logic;
lfclkpxnup : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0x6adj : in std_logic;
pclk0x6loc : in std_logic;
pclk0xndn : in std_logic;
pclk0xnup : in std_logic;
pclk1x6adj : in std_logic;
pclk1x6loc : in std_logic;
pclk1xndn : in std_logic;
pclk1xnup : in std_logic;
pclkx6adj : in std_logic_vector(2 downto 0);
pclkx6loc : in std_logic_vector(2 downto 0);
pclkxndn : in std_logic_vector(2 downto 0);
pclkxnup : in std_logic_vector(2 downto 0);
rxclk : in std_logic;
txpmarstb : in std_logic;
txpmasyncp : in std_logic;
xnresetin : in std_logic;
cpulse : out std_logic;
cpulseout : out std_logic;
hfclkn : out std_logic;
hfclknout : out std_logic;
hfclkp : out std_logic;
hfclkpout : out std_logic;
lfclkn : out std_logic;
lfclknout : out std_logic;
lfclkp : out std_logic;
lfclkpout : out std_logic;
pcieswdone : out std_logic_vector(1 downto 0);
pclk0 : out std_logic;
pclk0out : out std_logic;
pclk1 : out std_logic;
pclk1out : out std_logic;
pclk : out std_logic_vector(2 downto 0);
pclkout : out std_logic_vector(2 downto 0);
rxiqclk : out std_logic;
xnresetout : out std_logic
);
end component; --stratixv_hssi_pma_tx_cgb
component stratixv_hssi_pma_tx_ser
generic (
lpm_type : string := "stratixv_hssi_pma_tx_ser";
auto_negotiation : string := "false";
clk_divtx_deskew : string := "deskew_delay1";
mode : integer := 8;
post_tap_1_en : string := "false";
post_tap_2_en : string := "false";
pre_tap_en : string := "false";
ser_loopback : string := "false";
pclksel : string := "local_pclk";
channel_number : integer := 0;
clk_forward_only_mode : string := "false"
);
port (
cpulse : in std_logic;
datain : in std_logic_vector(39 downto 0);
hfclk : in std_logic;
hfclkn : in std_logic;
lfclk : in std_logic;
lfclkn : in std_logic;
pciesw : in std_logic_vector(1 downto 0);
pclk0 : in std_logic;
pclk1 : in std_logic;
pclk2 : in std_logic;
pclk : in std_logic_vector(2 downto 0);
rstn : in std_logic;
clkdivtx : out std_logic;
dataout : out std_logic;
div5 : out std_logic;
lbvop : out std_logic
);
end component; --stratixv_hssi_pma_tx_ser
component stratixv_hssi_rx_pcs_pma_interface
generic (
lpm_type : string := "stratixv_hssi_rx_pcs_pma_interface";
clkslip_sel : string := "pld";
prot_mode : string := "other_protocols";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrompma : in std_logic_vector(39 downto 0);
pmasigdet : in std_logic;
pmasignalok : in std_logic;
pcs10grxclkiqout : in std_logic;
pcsgen3rxclkiqout : in std_logic;
pcs8grxclkiqout : in std_logic;
pcs8grxclkslip : in std_logic;
pmaclkdiv33txorrxin : in std_logic;
pmarxplllockin : in std_logic;
pldrxpmarstb : in std_logic;
pldrxclkslip : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxclkslipsel : in std_logic;
pmarxclkslip : out std_logic;
pmarxclkout : out std_logic;
clkoutto10gpcs : out std_logic;
dataoutto10gpcs : out std_logic_vector(39 downto 0);
pcs10gsignalok : out std_logic;
clockouttogen3pcs : out std_logic;
dataouttogen3pcs : out std_logic_vector(31 downto 0);
pcsgen3pmasignaldet : out std_logic;
clockoutto8gpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(19 downto 0);
pcs8gsigdetni : out std_logic;
pmaclkdiv33txorrxout : out std_logic;
pcs10gclkdiv33txorrx : out std_logic;
pmarxpmarstb : out std_logic;
pmarxplllockout : out std_logic
);
end component; --stratixv_hssi_rx_pcs_pma_interface
component stratixv_hssi_rx_pld_pcs_interface
generic (
lpm_type : string := "stratixv_hssi_rx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false";
selectpcs : string := "eight_g_pcs"
);
port (
pld10grxpldclk : in std_logic;
pld10grxpldrstn : in std_logic;
pld10grxalignen : in std_logic;
pld10grxalignclr : in std_logic;
pld10grxrden : in std_logic;
pld10grxdispclr : in std_logic;
pld10grxclrerrblkcnt : in std_logic;
pld10grxclrbercount : in std_logic;
pld10grxprbserrclr : in std_logic;
pld10grxbitslip : in std_logic;
pld8grxurstpma : in std_logic;
pld8grxurstpcs : in std_logic;
pld8gcmpfifourst : in std_logic;
pld8gphfifourstrx : in std_logic;
pld8gencdt : in std_logic;
pld8ga1a2size : in std_logic;
pld8gbitslip : in std_logic;
pld8grdenablermf : in std_logic;
pld8gwrenablermf : in std_logic;
pld8gpldrxclk : in std_logic;
pld8gpolinvrx : in std_logic;
pld8gbitlocreven : in std_logic;
pld8gbytereven : in std_logic;
pld8gbytordpld : in std_logic;
pld8gwrdisablerx : in std_logic;
pld8grdenablerx : in std_logic;
pldgen3rxrstn : in std_logic;
pldrxclkslipin : in std_logic;
pld8gpldextrain : in std_logic_vector(3 downto 0);
clockinfrom10gpcs : in std_logic;
pcs10grxdatavalid : in std_logic;
datainfrom10gpcs : in std_logic_vector(63 downto 0);
pcs10grxcontrol : in std_logic_vector(9 downto 0);
pcs10grxempty : in std_logic;
pcs10grxpempty : in std_logic;
pcs10grxpfull : in std_logic;
pcs10grxoflwerr : in std_logic;
pcs10grxalignval : in std_logic;
pcs10grxblklock : in std_logic;
pcs10grxhiber : in std_logic;
pcs10grxframelock : in std_logic;
pcs10grxrdpossts : in std_logic;
pcs10grxrdnegsts : in std_logic;
pcs10grxskipins : in std_logic;
pcs10grxrxframe : in std_logic;
pcs10grxpyldins : in std_logic;
pcs10grxsyncerr : in std_logic;
pcs10grxscrmerr : in std_logic;
pcs10grxskiperr : in std_logic;
pcs10grxdiagerr : in std_logic;
pcs10grxsherr : in std_logic;
pcs10grxmfrmerr : in std_logic;
pcs10grxcrc32err : in std_logic;
pcs10grxdiagstatus : in std_logic_vector(1 downto 0);
datainfrom8gpcs : in std_logic_vector(63 downto 0);
clockinfrom8gpcs : in std_logic;
pcs8gbisterr : in std_logic;
pcs8grcvdclkpmab : in std_logic;
pcs8gsignaldetectout : in std_logic;
pcs8gbistdone : in std_logic;
pcs8grlvlt : in std_logic;
pcs8gfullrmf : in std_logic;
pcs8gemptyrmf : in std_logic;
pcs8gfullrx : in std_logic;
pcs8gemptyrx : in std_logic;
pcs8ga1a2k1k2flag : in std_logic_vector(3 downto 0);
pcs8gbyteordflag : in std_logic;
pcs8gwaboundary : in std_logic_vector(4 downto 0);
pcs8grxdatavalid : in std_logic_vector(3 downto 0);
pcs8grxsynchdr : in std_logic_vector(1 downto 0);
pcs8grxblkstart : in std_logic_vector(3 downto 0);
pmaclkdiv33txorrx : in std_logic;
emsippcsrxclkin : in std_logic_vector(2 downto 0);
emsippcsrxreset : in std_logic_vector(6 downto 0);
emsippcsrxctrl : in std_logic_vector(24 downto 0);
pmarxplllock : in std_logic;
pldrxpmarstbin : in std_logic;
rrxblocksel : in std_logic_vector(1 downto 0);
rrxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10grxfifoinsert : in std_logic;
pld8gsyncsmeninput : in std_logic;
pcs10grxfifodel : in std_logic;
dataouttopld : out std_logic_vector(63 downto 0);
pld10grxclkout : out std_logic;
pld10grxdatavalid : out std_logic;
pld10grxcontrol : out std_logic_vector(9 downto 0);
pld10grxempty : out std_logic;
pld10grxpempty : out std_logic;
pld10grxpfull : out std_logic;
pld10grxoflwerr : out std_logic;
pld10grxalignval : out std_logic;
pld10grxblklock : out std_logic;
pld10grxhiber : out std_logic;
pld10grxframelock : out std_logic;
pld10grxrdpossts : out std_logic;
pld10grxrdnegsts : out std_logic;
pld10grxskipins : out std_logic;
pld10grxrxframe : out std_logic;
pld10grxpyldins : out std_logic;
pld10grxsyncerr : out std_logic;
pld10grxscrmerr : out std_logic;
pld10grxskiperr : out std_logic;
pld10grxdiagerr : out std_logic;
pld10grxsherr : out std_logic;
pld10grxmfrmerr : out std_logic;
pld10grxcrc32err : out std_logic;
pld10grxdiagstatus : out std_logic_vector(1 downto 0);
pld8grxclkout : out std_logic;
pld8gbisterr : out std_logic;
pld8grcvdclkpmab : out std_logic;
pld8gsignaldetectout : out std_logic;
pld8gbistdone : out std_logic;
pld8grlvlt : out std_logic;
pld8gfullrmf : out std_logic;
pld8gemptyrmf : out std_logic;
pld8gfullrx : out std_logic;
pld8gemptyrx : out std_logic;
pld8ga1a2k1k2flag : out std_logic_vector(3 downto 0);
pld8gbyteordflag : out std_logic;
pld8gwaboundary : out std_logic_vector(4 downto 0);
pld8grxdatavalid : out std_logic_vector(3 downto 0);
pld8grxsynchdr : out std_logic_vector(1 downto 0);
pld8grxblkstart : out std_logic_vector(3 downto 0);
pcs10grxpldclk : out std_logic;
pcs10grxpldrstn : out std_logic;
pcs10grxalignen : out std_logic;
pcs10grxalignclr : out std_logic;
pcs10grxrden : out std_logic;
pcs10grxdispclr : out std_logic;
pcs10grxclrerrblkcnt : out std_logic;
pcs10grxclrbercount : out std_logic;
pcs10grxprbserrclr : out std_logic;
pcs10grxbitslip : out std_logic;
pcs8grxurstpma : out std_logic;
pcs8grxurstpcs : out std_logic;
pcs8gcmpfifourst : out std_logic;
pcs8gphfifourstrx : out std_logic;
pcs8gencdt : out std_logic;
pcs8ga1a2size : out std_logic;
pcs8gbitslip : out std_logic;
pcs8grdenablermf : out std_logic;
pcs8gwrenablermf : out std_logic;
pcs8gpldrxclk : out std_logic;
pcs8gpolinvrx : out std_logic;
pcs8gbitlocreven : out std_logic;
pcs8gbytereven : out std_logic;
pcs8gbytordpld : out std_logic;
pcs8gwrdisablerx : out std_logic;
pcs8grdenablerx : out std_logic;
pcs8gpldextrain : out std_logic_vector(3 downto 0);
pcsgen3rxrstn : out std_logic;
pldrxclkslipout : out std_logic;
pldclkdiv33txorrx : out std_logic;
emsiprxdata : out std_logic_vector(63 downto 0);
emsippcsrxclkout : out std_logic_vector(3 downto 0);
emsippcsrxstatus : out std_logic_vector(63 downto 0);
pldrxpmarstbout : out std_logic;
pldrxplllock : out std_logic;
pld10grxfifodel : out std_logic;
pldrxiqclkout : out std_logic;
pld10grxfifoinsert : out std_logic;
pcs8gsyncsmenoutput : out std_logic
);
end component; --stratixv_hssi_rx_pld_pcs_interface
component stratixv_hssi_tx_pcs_pma_interface
generic (
lpm_type : string := "stratixv_hssi_tx_pcs_pma_interface";
selectpcs : string := "eight_g_pcs"
);
port (
clockinfrompma : in std_logic;
datainfrom10gpcs : in std_logic_vector(39 downto 0);
pcs10gtxclkiqout : in std_logic;
pcsgen3txclkiqout : in std_logic;
datainfromgen3pcs : in std_logic_vector(31 downto 0);
pcs8gtxclkiqout : in std_logic;
datainfrom8gpcs : in std_logic_vector(19 downto 0);
pmaclkdiv33lcin : in std_logic;
pmatxlcplllockin : in std_logic;
pmatxcmuplllockin : in std_logic;
rtxblocksel : in std_logic_vector(1 downto 0);
pcsgen3gen3datasel : in std_logic;
pldtxpmasyncp : in std_logic;
dataouttopma : out std_logic_vector(39 downto 0);
pmatxclkout : out std_logic;
clockoutto10gpcs : out std_logic;
clockoutto8gpcs : out std_logic;
pmaclkdiv33lcout : out std_logic;
pcs10gclkdiv33lc : out std_logic;
pmatxlcplllockout : out std_logic;
pmatxcmuplllockout : out std_logic;
pmatxpmasyncp : out std_logic
);
end component; --stratixv_hssi_tx_pcs_pma_interface
component stratixv_hssi_tx_pld_pcs_interface
generic (
lpm_type : string := "stratixv_hssi_tx_pld_pcs_interface";
data_source : string := "pld";
is_10g_0ppm : string := "false";
is_8g_0ppm : string := "false"
);
port (
datainfrompld : in std_logic_vector(63 downto 0);
pld10gtxpldclk : in std_logic;
pld10gtxpldrstn : in std_logic;
pld10gtxdatavalid : in std_logic;
pld10gtxcontrol : in std_logic_vector(8 downto 0);
pld10gtxbitslip : in std_logic_vector(6 downto 0);
pld10gtxdiagstatus : in std_logic_vector(1 downto 0);
pld10gtxwordslip : in std_logic;
pld10gtxbursten : in std_logic;
pld8gpldtxclk : in std_logic;
pld8gpolinvtx : in std_logic;
pld8grevloopbk : in std_logic;
pld8gwrenabletx : in std_logic;
pld8grddisabletx : in std_logic;
pld8gphfifoursttx : in std_logic;
pld8gtxboundarysel : in std_logic_vector(4 downto 0);
pld8gtxdatavalid : in std_logic_vector(3 downto 0);
pld8gtxsynchdr : in std_logic_vector(1 downto 0);
pld8gtxblkstart : in std_logic_vector(3 downto 0);
pldgen3txrstn : in std_logic;
pld8gtxurstpcs : in std_logic;
clockinfrom10gpcs : in std_logic;
pcs10gtxempty : in std_logic;
pcs10gtxpempty : in std_logic;
pcs10gtxpfull : in std_logic;
pcs10gtxfull : in std_logic;
pcs10gtxframe : in std_logic;
pcs10gtxburstenexe : in std_logic;
pcs10gtxwordslipexe : in std_logic;
pcs8gfulltx : in std_logic;
pcs8gemptytx : in std_logic;
clockinfrom8gpcs : in std_logic;
pmaclkdiv33lc : in std_logic;
emsiptxdata : in std_logic_vector(63 downto 0);
emsippcstxclkin : in std_logic_vector(2 downto 0);
emsippcstxreset : in std_logic_vector(5 downto 0);
emsippcstxctrl : in std_logic_vector(43 downto 0);
pmatxlcplllock : in std_logic;
pmatxcmuplllock : in std_logic;
pldtxpmarstbin : in std_logic;
pldlccmurstbin : in std_logic;
rtxemsip : in std_logic;
emsipenabledusermode : in std_logic;
pcs10gextraout : in std_logic_vector(3 downto 0);
pldtxpmasyncpin : in std_logic;
pcs10gtxfifoinsert : in std_logic;
pcs10gtxfifodel : in std_logic;
pld10gextrain : in std_logic_vector(3 downto 0);
pld10gtxclkout : out std_logic;
pld10gtxempty : out std_logic;
pld10gtxpempty : out std_logic;
pld10gtxpfull : out std_logic;
pld10gtxfull : out std_logic;
pld10gtxframe : out std_logic;
pld10gtxburstenexe : out std_logic;
pld10gtxwordslipexe : out std_logic;
pld8gfulltx : out std_logic;
pld8gemptytx : out std_logic;
pld8gtxclkout : out std_logic;
pcs10gtxpldclk : out std_logic;
pcs10gtxpldrstn : out std_logic;
pcs10gtxdatavalid : out std_logic;
dataoutto10gpcs : out std_logic_vector(63 downto 0);
pcs10gtxcontrol : out std_logic_vector(8 downto 0);
pcs10gtxbitslip : out std_logic_vector(6 downto 0);
pcs10gtxdiagstatus : out std_logic_vector(1 downto 0);
pcs10gtxwordslip : out std_logic;
pcs10gtxbursten : out std_logic;
pcs8gtxurstpcs : out std_logic;
dataoutto8gpcs : out std_logic_vector(43 downto 0);
pcs8gpldtxclk : out std_logic;
pcs8gpolinvtx : out std_logic;
pcs8grevloopbk : out std_logic;
pcs8gwrenabletx : out std_logic;
pcs8grddisabletx : out std_logic;
pcs8gphfifoursttx : out std_logic;
pcs8gtxboundarysel : out std_logic_vector(4 downto 0);
pcs8gtxdatavalid : out std_logic_vector(3 downto 0);
pcs8gtxsynchdr : out std_logic_vector(1 downto 0);
pcs8gtxblkstart : out std_logic_vector(3 downto 0);
pcsgen3txrstn : out std_logic;
pldclkdiv33lc : out std_logic;
emsippcstxclkout : out std_logic_vector(2 downto 0);
emsippcstxstatus : out std_logic_vector(16 downto 0);
pldtxpmarstbout : out std_logic;
pldlccmurstbout : out std_logic;
pldtxlcplllock : out std_logic;
pldtxcmuplllock : out std_logic;
pldtxiqclkout : out std_logic;
pcs10gextrain : out std_logic_vector(3 downto 0);
pld10gtxfifodel : out std_logic;
pldtxpmasyncpout : out std_logic;
pld10gtxfifoinsert : out std_logic;
pld10gextraout : out std_logic_vector(3 downto 0)
);
end component; --stratixv_hssi_tx_pld_pcs_interface
component stratixv_hssi_avmm_interface
port (
avmmrstn : in std_logic_vector(0 downto 0);
avmmclk : in std_logic_vector(0 downto 0);
avmmwrite : in std_logic_vector(0 downto 0);
avmmread : in std_logic_vector(0 downto 0);
avmmbyteen : in std_logic_vector(1 downto 0);
avmmaddress : in std_logic_vector(10 downto 0);
avmmwritedata : in std_logic_vector(15 downto 0);
blockselect : in std_logic_vector(90-1 downto 0);
readdatachnl : in std_logic_vector(90*16-1 downto 0);
avmmreaddata : out std_logic_vector(15 downto 0);
clkchnl : out std_logic_vector(0 downto 0);
rstnchnl : out std_logic_vector(0 downto 0);
writedatachnl : out std_logic_vector(15 downto 0);
regaddrchnl : out std_logic_vector(10 downto 0);
writechnl : out std_logic_vector(0 downto 0);
readchnl : out std_logic_vector(0 downto 0);
byteenchnl : out std_logic_vector(1 downto 0);
-- The following ports are not modelled. They exist to match the avmm interface atom interface
refclkdig : in std_logic_vector(0 downto 0);
avmmreserevdin : in std_logic_vector(0 downto 0);
avmmreservedout : out std_logic_vector(0 downto 0);
dpriorstntop : out std_logic_vector(0 downto 0);
dprioclktop : out std_logic_vector(0 downto 0);
mdiodistopchnl : out std_logic_vector(0 downto 0);
dpriorstnmid : out std_logic_vector(0 downto 0);
dprioclkmid : out std_logic_vector(0 downto 0);
mdiodismidchnl : out std_logic_vector(0 downto 0);
dpriorstnbot : out std_logic_vector(0 downto 0);
dprioclkbot : out std_logic_vector(0 downto 0);
mdiodisbotchnl : out std_logic_vector(0 downto 0);
dpriotestsitopchnl : out std_logic_vector(3 downto 0);
dpriotestsimidchnl : out std_logic_vector(3 downto 0);
dpriotestsibotchnl : out std_logic_vector(3 downto 0);
-- The following ports belong to pm_adce and pm_tst_mux blocks in the PMA
pmatestbus : out std_logic_vector(23 downto 0);
pmatestbussel : in std_logic_vector(11 downto 0);
pmaadcestandby : in std_logic_vector(2 downto 0);
pmaadcecapture : in std_logic_vector(2 downto 0)
);
end component; --stratixv_hssi_avmm_interface
end STRATIXV_HSSI_COMPONENTS;
| gpl-3.0 | 690baeee05959cdf24fe4aa72a189209 | 0.531574 | 3.273227 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_microbus.vhd | 1 | 7,476 | -------------------------------------------------------------------------------
--
-- Testbench for MICROBUS evaluation.
--
-- $Id: tb_microbus.vhd,v 1.1 2006-06-05 21:04:52 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_microbus is
end tb_microbus;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.t400_system_comp_pack.t420;
use work.tb_pack.all;
use work.t400_opt_pack.all;
architecture behav of tb_microbus is
-- 5 MHz clock
constant period_c : time := 200 ns;
signal ck_s : std_logic;
signal en_ck_s : std_logic := '0';
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal cs_n_s,
rd_n_s,
wr_n_s : std_logic;
signal tb_io_l_s : std_logic_vector(7 downto 0);
begin
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c,
opt_microbus_g => t400_opt_microbus_c
)
port map (
ck_i => ck_s,
ck_en_i => en_ck_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
io_in_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => tb_io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Generates the en_ck_s signal from the high frequency clock.
--
ck_div: process (ck_s)
variable cnt_v : natural := 0;
begin
if ck_s'event and ck_s = '1' then
en_ck_s <= '0';
if cnt_v = 25 then
cnt_v := 0;
en_ck_s <= '1';
else
cnt_v := cnt_v + 1;
end if;
end if;
end process ck_div;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process microbus
--
-- Purpose:
-- Implements the microbus testbench element.
-- a) sends twelve bytes of data to the DUT
-- HELLO WORLD!
-- b) reads twelve bytes from the DUT and compares them against
-- the original sequence
--
microbus: process
procedure tb_pass_fail(pass : in boolean) is
begin
tb_io_l_s <= "00000000";
wait for 1 us;
tb_io_l_s <= "10100000";
wait for 1 us;
tb_io_l_s <= "01010000";
wait for 1 us;
if pass then
tb_io_l_s <= "00000000";
else
tb_io_l_s <= "11110000";
end if;
wait for 1 us;
end;
constant msg_c : string := string'("HELLO WORLD!");
begin
-- default settings
cs_n_s <= '1';
rd_n_s <= '1';
wr_n_s <= '1';
io_l_s <= (others => 'H');
tb_io_l_s <= (others => '0');
--
-- send the message string
--
for idx in msg_c'range loop
wait until io_g_s(0)'event and io_g_s(0) = '1';
if idx mod 2 = 0 then
-- short wait for even positions
wait for 1 us;
else
-- long wait for odd positions
wait for 1 ms;
end if;
io_l_s <= std_logic_vector(to_unsigned(character'pos(msg_c(idx)), 8));
wait for 10 ns;
cs_n_s <= '0';
wr_n_s <= '0';
wait for 400 ns;
cs_n_s <= '1';
wr_n_s <= '1';
wait for 10 ns;
io_l_s <= (others => 'H');
end loop;
--
-- and receive it again
--
for idx in msg_c'range loop
wait until io_g_s(0)'event and io_g_s(0) = '1';
if idx mod 2 = 0 then
-- short wait for even positions
wait for 1 us;
else
-- long wait for odd positions
wait for 1 ms;
end if;
cs_n_s <= '0';
rd_n_s <= '0';
wait for 400 ns;
if character'pos(msg_c(idx)) /= to_integer(unsigned(io_l_s)) then
tb_pass_fail(pass => false);
end if;
cs_n_s <= '1';
rd_n_s <= '1';
-- ack with dummy write
wait for 1 us;
cs_n_s <= '0';
wr_n_s <= '0';
wait for 400 ns;
cs_n_s <= '1';
wr_n_s <= '1';
end loop;
tb_pass_fail(pass => true);
wait;
end process microbus;
--
io_in_s(1) <= rd_n_s;
io_in_s(2) <= cs_n_s;
io_in_s(3) <= wr_n_s;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 234c6bef8e3fa3fd9640442808dbe6f1 | 0.495185 | 3.561696 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiii_atoms.vhd | 1 | 936,841 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixiii_pllpack;
package body stratixiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_dffe : entity is TRUE;
end stratixiii_dffe;
-- architecture body --
architecture behave of stratixiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixiii_mux21 : entity is TRUE;
end stratixiii_mux21;
architecture AltVITAL of stratixiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_mux41 : entity is TRUE;
end stratixiii_mux41;
architecture AltVITAL of stratixiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and1 : entity is TRUE;
end stratixiii_and1;
-- architecture body --
architecture AltVITAL of stratixiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_jtag is
generic (
lpm_type : string := "stratixiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixiii_jtag;
architecture architecture_jtag of stratixiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixiii_crcblock;
architecture architecture_crcblock of stratixiii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_lcell_comb
--
-- Description : Stratix III LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lcell_comb : entity is TRUE;
end stratixiii_lcell_comb;
architecture vital_lcell_comb of stratixiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_routing_wire
--
-- Description : Stratix III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_routing_wire : entity is TRUE;
end stratixiii_routing_wire;
ARCHITECTURE behave of stratixiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lvds_tx_reg : ENTITY is TRUE;
END stratixiii_lvds_tx_reg;
ARCHITECTURE vital_stratixiii_lvds_tx_reg of stratixiii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_stratixiii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the Stratix III
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixiii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixiii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixiii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixiii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_transmitter
--
-- Description : Timing simulation model for the Stratix III LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) Stratix III_lvds_tx_parallel_register and
-- 3) Stratix III_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
USE work.stratixiii_lvds_tx_parallel_register;
USE work.stratixiii_lvds_tx_out_block;
USE work.stratixiii_lvds_tx_reg;
ENTITY stratixiii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixiii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixiii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixiii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixiii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixiii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixiii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then
dataout_tmp := dpaclkin_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- STRATIXIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end stratixiii_rublock;
architecture architecture_rublock of stratixiii_rublock is
begin
end architecture_rublock;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixiii_ram_register;
ARCHITECTURE reg_arch OF stratixiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_ram_pulse_generator:ENTITY IS TRUE;
END stratixiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_ram_register;
USE work.stratixiii_ram_pulse_generator;
ENTITY stratixiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixiii_ram_block;
ARCHITECTURE block_arch OF stratixiii_ram_block IS
COMPONENT stratixiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ff
--
-- Description : Stratix III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_and1;
entity stratixiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ff : entity is TRUE;
end stratixiii_ff;
architecture vital_lcell_ff of stratixiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: stratixiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: stratixiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: stratixiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIII_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_clkselect is
generic (
lpm_type : STRING := "stratixiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkselect : entity is TRUE;
end stratixiii_clkselect;
architecture vital_clkselect of stratixiii_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- stratixiii_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and2 : entity is TRUE;
end stratixiii_and2;
-- architecture body --
architecture AltVITAL of stratixiii_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ena_reg : entity is TRUE;
end stratixiii_ena_reg;
ARCHITECTURE behave of stratixiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- Stratix III_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ena_reg;
use work.stratixiii_and2;
entity stratixiii_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkena : entity is TRUE;
end stratixiii_clkena;
architecture vital_clkena of stratixiii_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component stratixiii_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component stratixiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : stratixiii_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : stratixiii_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : stratixiii_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_mlab_cell_pulse_generator:ENTITY IS TRUE;
END stratixiii_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_mlab_cell_pulse_generator;
ENTITY stratixiii_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END stratixiii_mlab_cell;
ARCHITECTURE block_arch OF stratixiii_mlab_cell IS
COMPONENT stratixiii_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : stratixiii_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_ibuf
--
-- Description : Stratix III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END stratixiii_io_ibuf;
ARCHITECTURE arch OF stratixiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_obuf
--
-- Description : Stratix III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_io_obuf;
ARCHITECTURE arch OF stratixiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_in
--
-- Description : Stratix III DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_in;
ARCHITECTURE arch OF stratixiii_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_oe
--
-- Description : Stratix III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_oe;
ARCHITECTURE arch OF stratixiii_ddio_oe IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : stratixiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_out
--
-- Description : Stratix III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_out;
ARCHITECTURE arch OF stratixiii_ddio_out IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : stratixiii_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: stratixiii_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY stratixiii_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END stratixiii_rt_sm;
ARCHITECTURE stratixiii_rt_sm_rtl OF stratixiii_rt_sm IS
CONSTANT STRATIXIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT STRATIXIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT STRATIXIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT STRATIXIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT STRATIXIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT STRATIXIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT STRATIXIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT STRATIXIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT STRATIXIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= STRATIXIII_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN STRATIXIII_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= STRATIXIII_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN STRATIXIII_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN STRATIXIII_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN STRATIXIII_RTOCT_DONE =>
next_state <= STRATIXIII_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= STRATIXIII_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END stratixiii_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY stratixiii_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END stratixiii_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF stratixiii_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination
--
-- Description : Stratix III Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
USE WORK.stratixiii_termination_aux_clock_div;
USE WORK.stratixiii_rt_sm;
ENTITY stratixiii_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END stratixiii_termination;
ARCHITECTURE stratixiii_oct_arch OF stratixiii_termination IS
COMPONENT stratixiii_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : stratixiii_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : stratixiii_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END stratixiii_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination_logic
--
-- Description : Stratix III Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END stratixiii_termination_logic;
ARCHITECTURE stratixiii_oct_logic_arch OF stratixiii_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END stratixiii_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package stratixiii_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end stratixiii_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end stratixiii_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_encoder;
ARCHITECTURE stratixiii_dll_gray_encoder_arch OF stratixiii_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END stratixiii_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_decoder;
ARCHITECTURE stratixiii_dll_gray_decoder_arch OF stratixiii_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END stratixiii_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END stratixiii_ddr_delay_chain_s;
ARCHITECTURE stratixiii_ddr_delay_chain_s_arch OF stratixiii_ddr_delay_chain_s IS
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END stratixiii_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ddr_io_reg : entity is TRUE;
end stratixiii_ddr_io_reg;
architecture vital_stratixiii_ddr_io_reg of stratixiii_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_stratixiii_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiii_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
ENTITY stratixiii_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END stratixiii_dll;
ARCHITECTURE vital_titandll of stratixiii_dll is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in stratixiii
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in stratixiii
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in stratixiii
signal pc_comp_range : integer := 0; -- new in stratixiii
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in stratixiii
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titandll;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END stratixiii_dll_offset_ctrl;
ARCHITECTURE vital_titanoffset of stratixiii_dll_offset_ctrl is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titanoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_delay_chain_arch OF stratixiii_dqs_delay_chain IS
-- component section
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_enable IS
GENERIC (
lpm_type : string := "stratixiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_arch OF stratixiii_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_ctrl_arch OF stratixiii_dqs_enable_ctrl IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : stratixiii_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_delay_chain_arch OF stratixiii_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END stratixiii_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_clock_divider_arch OF stratixiii_io_clock_divider IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END stratixiii_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_output_phase_alignment_arch OF stratixiii_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE stratixiii_input_phase_alignment_arch OF stratixiii_input_phase_alignment IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
ENTITY stratixiii_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_half_rate_input_arch OF stratixiii_half_rate_input IS
-- component section
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END stratixiii_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_config_arch OF stratixiii_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_config_arch OF stratixiii_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_bit_register --
-- Description: Stratix III MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_mac_bit_register;
ARCHITECTURE arch OF stratixiii_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_register --
-- Description: Stratix III MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END stratixiii_mac_register;
ARCHITECTURE arch OF stratixiii_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_multiplier --
-- Description: Stratix III MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END stratixiii_mac_multiplier;
ARCHITECTURE arch OF stratixiii_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_mult_atom --
-- Description: Simulation model for stratixiii mac mult atom. --
-- This model instantiates the following components. --
-- 1.stratixiii_mac_bit_register. --
-- 2.stratixiii_mac_register. --
-- 3.stratixiii_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_mac_mult;
ARCHITECTURE arch OF stratixiii_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : stratixiii_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_fsa_isse --
-- Description: Stratix III first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END stratixiii_fsa_isse;
ARCHITECTURE arch OF stratixiii_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_first_stage_add_sub --
-- Description: Stratix III First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_first_stage_add_sub;
ARCHITECTURE arch OF stratixiii_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_second_stage_add_accum --
-- Description: Stratix III Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END stratixiii_second_stage_add_accum;
ARCHITECTURE arch OF stratixiii_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_block --
-- Description: Stratix III round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_round_block;
ARCHITECTURE arch OF stratixiii_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_saturate_block --
-- Description: Stratix III saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END stratixiii_saturate_block;
ARCHITECTURE arch OF stratixiii_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_saturate_block --
-- Description: Stratix III round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.stratixiii_round_block. --
-- 2.stratixiii_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END stratixiii_round_saturate_block;
ARCHITECTURE arch OF stratixiii_round_saturate_block IS
COMPONENT stratixiii_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : stratixiii_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : stratixiii_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_rotate_shift_block --
-- Description: Stratix III roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_rotate_shift_block;
ARCHITECTURE arch OF stratixiii_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_carry_chain_adder --
-- Description: Stratix III carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END stratixiii_carry_chain_adder;
ARCHITECTURE arch OF stratixiii_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_out_atom --
-- Description: Simulation model for stratixiii mac out atom --
-- This model instantiates the following components --
-- 1.stratixiii_mac_bit_register --
-- 2.stratixiii_mac_register --
-- 3.stratixiii_fsa_isse --
-- 4.stratixiii_first_stage_add_sub --
-- 5.stratixiii_second_stage_add_accum --
-- 6.stratixiii_round_saturate_block --
-- 7.stratixiii_rotate_shift_block --
-- 8.stratixiii_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END stratixiii_mac_out;
ARCHITECTURE arch OF stratixiii_mac_out IS
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : stratixiii_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : stratixiii_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : stratixiii_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : stratixiii_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_io_pad
-- Description : Simulation model for stratixiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_io_pad IS
GENERIC (
lpm_type : string := "stratixiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END stratixiii_io_pad;
ARCHITECTURE arch OF stratixiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiii_mn_cntr;
ARCHITECTURE behave of stratixiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixiii_scale_cntr;
ARCHITECTURE behave of stratixiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--BEGIN MF PORTING DELETE
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixiii_pll_reg;
ARCHITECTURE behave of stratixiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--END MF PORTING DELETE
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
USE work.stratixiii_mn_cntr;
USE work.stratixiii_scale_cntr;
USE work.stratixiii_dffe;
USE work.stratixiii_pll_reg;
-- New Features : The list below outlines key new features in STRATIXIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY stratixiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "StratixIII";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END stratixiii_pll;
ARCHITECTURE vital_pll of stratixiii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT stratixiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : stratixiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : stratixiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : stratixiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixiii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : stratixiii_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : stratixiii_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : stratixiii_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : stratixiii_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_asmiblock
--
-- Description : Stratix III ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_asmiblock is
generic (
lpm_type : string := "stratixiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end stratixiii_asmiblock;
architecture architecture_asmiblock of stratixiii_asmiblock is
begin
end architecture_asmiblock; -- end of stratixiii_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixiii_lvds_reg;
ARCHITECTURE vital_stratixiii_lvds_reg of stratixiii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_fifo_sync_ram;
ENTITY stratixiii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixiii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixiii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_reg;
ENTITY stratixiii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixiii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixiii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixiii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_deser
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixiii_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END stratixiii_pclk_divider;
ARCHITECTURE arch OF stratixiii_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END stratixiii_select_ini_phase_dpaclk;
ARCHITECTURE trans OF stratixiii_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END stratixiii_dpa_retime_block;
ARCHITECTURE trans OF stratixiii_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.stratixiii_dpa_retime_block;
ENTITY stratixiii_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END stratixiii_dpa_block;
ARCHITECTURE trans OF stratixiii_dpa_block IS
COMPONENT stratixiii_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : stratixiii_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_LVDS_RECEIVER
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixiii_lvds_rx_fifo
-- 2) stratixiii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixiii_lvds_rx_parallel_reg
-- 5) stratixiii_pclk_divider
-- 6) stratixiii_select_ini_phase_dpaclk
-- 7) stratixiii_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_bitslip;
USE work.stratixiii_lvds_rx_fifo;
USE work.stratixiii_lvds_rx_deser;
USE work.stratixiii_lvds_rx_parallel_reg;
USE work.stratixiii_lvds_reg;
USE work.stratixiii_pclk_divider;
USE work.stratixiii_select_ini_phase_dpaclk;
USE work.stratixiii_dpa_block;
ENTITY stratixiii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixiii_lvds_receiver IS
COMPONENT stratixiii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT stratixiii_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
xhdl_12 <= devclrn OR devpor;
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: stratixiii_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixiii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: stratixiii_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: stratixiii_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : stratixiii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : stratixiii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : stratixiii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : stratixiii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixiii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: stratixiii_pseudo_diff_out --
--Description: Simulation model for Stratix III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_pseudo_diff_out;
ARCHITECTURE arch OF stratixiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_logic
--
-- Description : STRATIXIII Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_logic : ENTITY IS TRUE;
end stratixiii_bias_logic;
ARCHITECTURE vital_bias_logic of stratixiii_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_generator
--
-- Description : STRATIXIII Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_generator : ENTITY IS TRUE;
end stratixiii_bias_generator;
ARCHITECTURE vital_bias_generator of stratixiii_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 252;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_block
--
-- Description : STRATIXIII Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_block IS
GENERIC (
lpm_type : string := "stratixiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_block : ENTITY IS TRUE;
end stratixiii_bias_block;
ARCHITECTURE vital_bias_block of stratixiii_bias_block IS
COMPONENT stratixiii_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT stratixiii_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : stratixiii_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : stratixiii_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_tsdblock
--
-- Description : Stratix III TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end stratixiii_tsdblock;
architecture architecture_tsdblock of stratixiii_tsdblock is
begin
end architecture_tsdblock; -- end of stratixiii_tsdblock
| gpl-3.0 | 1b902d283687d114e7471303ad064007 | 0.469362 | 4.192658 | false | false | false | false |
EPiCS/reconos | pcores/reconos_memif_memory_controller_v1_00_a/hdl/vhdl/reconos_memif_memory_controller.vhd | 2 | 15,252 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF Memory controller - Top level entity
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory controller connectr the memory subsystem of
-- ReconOS to the memory bus of the system as an AXI
-- master.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
library reconos_memif_memory_controller_v1_00_a;
use reconos_memif_memory_controller_v1_00_a.user_logic;
entity reconos_memif_memory_controller is
generic (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH : integer := 32;
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_USE_MMU_PORT : boolean := true;
-- Bus protocol parameters, do not add to or delete
C_FAMILY : string := "virtex6";
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 32;
C_MAX_BURST_LEN : integer := 256;
C_ADDR_PIPE_DEPTH : integer := 1;
C_NATIVE_DATA_WIDTH : integer := 32;
C_LENGTH_WIDTH : integer := 12
);
port (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Hwt2Mem_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Empty : in std_logic;
MEMIF_FIFO_Hwt2Mem_RE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mem2Hwt_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Full : in std_logic;
MEMIF_FIFO_Mem2Hwt_WE : out std_logic;
CTRL_FIFO_Hwt_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Hwt_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Hwt_Empty : in std_logic;
CTRL_FIFO_Hwt_RE : out std_logic;
MEMIF_FIFO_Mmu_Data : out std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : in std_logic;
MEMIF_FIFO_Mmu_WE : out std_logic;
CTRL_FIFO_Mmu_Data : in std_logic_vector(C_MEMIF_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : in std_logic;
CTRL_FIFO_Mmu_RE : out std_logic;
MEMCTRL_Clk : in std_logic;
MEMCTRL_Rst : in std_logic;
-- Bus protocol ports, do not add to or delete
M_AXI_ACLK : in std_logic;
M_AXI_ARESETN : in std_logic;
MD_ERROR : out std_logic;
M_AXI_ARREADY : in std_logic;
M_AXI_ARVALID : out std_logic;
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_RREADY : out std_logic;
M_AXI_RVALID : in std_logic;
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_AWREADY : in std_logic;
M_AXI_AWVALID : out std_logic;
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_WREADY : in std_logic;
M_AXI_WVALID : out std_logic;
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector((C_M_AXI_DATA_WIDTH)/8 - 1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_BREADY : out std_logic;
M_AXI_BVALID : in std_logic;
M_AXI_BRESP : in std_logic_vector(1 downto 0);
M_AXI_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_ARUSER : out std_logic_vector(4 downto 0)
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of M_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of M_AXI_ARESETN : signal is "10000";
attribute SIGIS of M_AXI_ACLK : signal is "Clk";
attribute SIGIS of MEMCTRL_Clk : signal is "Clk";
attribute SIGIS of M_AXI_ARESETN : signal is "Rst";
attribute SIGIS of MEMCTRL_Rst : signal is "Rst";
end entity reconos_memif_memory_controller;
architecture implementation of reconos_memif_memory_controller is
constant USER_MST_AWIDTH : integer := C_M_AXI_ADDR_WIDTH;
constant USER_MST_DWIDTH : integer := C_M_AXI_DATA_WIDTH;
constant USER_MST_NATIVE_DATA_WIDTH : integer := C_NATIVE_DATA_WIDTH;
constant USER_LENGTH_WIDTH : integer := C_LENGTH_WIDTH;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_ip2bus_mstrd_req : std_logic;
signal ipif_ip2bus_mstwr_req : std_logic;
signal ipif_ip2bus_mst_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_ip2bus_mst_be : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_ip2bus_mst_length : std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
signal ipif_ip2bus_mst_type : std_logic;
signal ipif_ip2bus_mst_lock : std_logic;
signal ipif_ip2bus_mst_reset : std_logic;
signal ipif_bus2ip_mst_cmdack : std_logic;
signal ipif_bus2ip_mst_cmplt : std_logic;
signal ipif_bus2ip_mst_error : std_logic;
signal ipif_bus2ip_mst_rearbitrate : std_logic;
signal ipif_bus2ip_mst_cmd_timeout : std_logic;
signal ipif_bus2ip_mstrd_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal ipif_bus2ip_mstrd_rem : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_bus2ip_mstrd_sof_n : std_logic;
signal ipif_bus2ip_mstrd_eof_n : std_logic;
signal ipif_bus2ip_mstrd_src_rdy_n : std_logic;
signal ipif_bus2ip_mstrd_src_dsc_n : std_logic;
signal ipif_ip2bus_mstrd_dst_rdy_n : std_logic;
signal ipif_ip2bus_mstrd_dst_dsc_n : std_logic;
signal ipif_ip2bus_mstwr_d : std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
signal ipif_ip2bus_mstwr_rem : std_logic_vector((C_NATIVE_DATA_WIDTH)/8-1 downto 0);
signal ipif_ip2bus_mstwr_src_rdy_n : std_logic;
signal ipif_ip2bus_mstwr_src_dsc_n : std_logic;
signal ipif_ip2bus_mstwr_sof_n : std_logic;
signal ipif_ip2bus_mstwr_eof_n : std_logic;
signal ipif_bus2ip_mstwr_dst_rdy_n : std_logic;
signal ipif_bus2ip_mstwr_dst_dsc_n : std_logic;
signal ignore : std_logic_vector(3 downto 0);
begin
-- instantiate axi_master_burst
AXI_MASTER_BURST_I : entity axi_master_burst_v1_00_a.axi_master_burst
generic map (
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_MAX_BURST_LEN => C_MAX_BURST_LEN,
C_NATIVE_DATA_WIDTH => C_NATIVE_DATA_WIDTH,
C_LENGTH_WIDTH => C_LENGTH_WIDTH,
C_ADDR_PIPE_DEPTH => C_ADDR_PIPE_DEPTH,
C_FAMILY => C_FAMILY
)
port map
(
m_axi_aclk => M_AXI_ACLK,
m_axi_aresetn => M_AXI_ARESETN,
md_error => MD_ERROR,
m_axi_arready => M_AXI_ARREADY,
m_axi_arvalid => M_AXI_ARVALID,
m_axi_araddr => M_AXI_ARADDR,
m_axi_arlen => M_AXI_ARLEN,
m_axi_arsize => M_AXI_ARSIZE,
m_axi_arburst => M_AXI_ARBURST,
m_axi_arprot => M_AXI_ARPROT,
m_axi_arcache => ignore,
m_axi_rready => M_AXI_RREADY,
m_axi_rvalid => M_AXI_RVALID,
m_axi_rdata => M_AXI_RDATA,
m_axi_rresp => M_AXI_RRESP,
m_axi_rlast => M_AXI_RLAST,
m_axi_awready => M_AXI_AWREADY,
m_axi_awvalid => M_AXI_AWVALID,
m_axi_awaddr => M_AXI_AWADDR,
m_axi_awlen => M_AXI_AWLEN,
m_axi_awsize => M_AXI_AWSIZE,
m_axi_awburst => M_AXI_AWBURST,
m_axi_awprot => M_AXI_AWPROT,
m_axi_awcache => ignore,
m_axi_wready => M_AXI_WREADY,
m_axi_wvalid => M_AXI_WVALID,
m_axi_wdata => M_AXI_WDATA,
m_axi_wstrb => M_AXI_WSTRB,
m_axi_wlast => M_AXI_WLAST,
m_axi_bready => M_AXI_BREADY,
m_axi_bvalid => M_AXI_BVALID,
m_axi_bresp => M_AXI_BRESP,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_length => ipif_ip2bus_mst_length,
ip2bus_mst_type => ipif_ip2bus_mst_type,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_rem => ipif_bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
ip2bus_mstwr_rem => ipif_ip2bus_mstwr_rem,
ip2bus_mstwr_src_rdy_n => ipif_ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_ip2bus_mstwr_src_dsc_n,
ip2bus_mstwr_sof_n => ipif_ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_ip2bus_mstwr_eof_n,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_bus2ip_mstwr_dst_dsc_n
);
-- instantiate User Logic
USER_LOGIC_I : entity reconos_memif_memory_controller_v1_00_a.user_logic
generic map (
-- Memory controller parameters
C_MEMIF_FIFO_WIDTH => C_MEMIF_FIFO_WIDTH,
C_CTRL_FIFO_WIDTH => C_CTRL_FIFO_WIDTH,
C_MEMIF_LENGTH_WIDTH => C_MEMIF_LENGTH_WIDTH,
C_USE_MMU_PORT => C_USE_MMU_PORT,
-- Bus protocol parameters
C_MST_NATIVE_DATA_WIDTH => USER_MST_NATIVE_DATA_WIDTH,
C_LENGTH_WIDTH => USER_LENGTH_WIDTH,
C_MST_AWIDTH => USER_MST_AWIDTH
)
port map (
-- Memory controller ports
MEMIF_FIFO_Hwt2Mem_Data => MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_Fill => MEMIF_FIFO_Hwt2Mem_Fill,
MEMIF_FIFO_Hwt2Mem_Empty => MEMIF_FIFO_Hwt2Mem_Empty,
MEMIF_FIFO_Hwt2Mem_RE => MEMIF_FIFO_Hwt2Mem_RE,
MEMIF_FIFO_Mem2Hwt_Data => MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Rem => MEMIF_FIFO_Mem2Hwt_Rem,
MEMIF_FIFO_Mem2Hwt_Full => MEMIF_FIFO_Mem2Hwt_Full,
MEMIF_FIFO_Mem2Hwt_WE => MEMIF_FIFO_Mem2Hwt_WE,
CTRL_FIFO_Hwt_Data => CTRL_FIFO_Hwt_Data,
CTRL_FIFO_Hwt_Fill => CTRL_FIFO_Hwt_Fill,
CTRL_FIFO_Hwt_Empty => CTRL_FIFO_Hwt_Empty,
CTRL_FIFO_Hwt_RE => CTRL_FIFO_Hwt_RE,
MEMIF_FIFO_Mmu_Data => MEMIF_FIFO_Mmu_Data,
MEMIF_FIFO_Mmu_Rem => MEMIF_FIFO_Mmu_Rem,
MEMIF_FIFO_Mmu_Full => MEMIF_FIFO_Mmu_Full,
MEMIF_FIFO_Mmu_WE => MEMIF_FIFO_Mmu_WE,
CTRL_FIFO_Mmu_Data => CTRL_FIFO_Mmu_Data,
CTRL_FIFO_Mmu_Fill => CTRL_FIFO_Mmu_Fill,
CTRL_FIFO_Mmu_Empty => CTRL_FIFO_Mmu_Empty,
CTRL_FIFO_Mmu_RE => CTRL_FIFO_Mmu_RE,
MEMCTRL_Clk => MEMCTRL_Clk,
MEMCTRL_Rst => MEMCTRL_Rst,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
ip2bus_mstrd_req => ipif_ip2bus_mstrd_req,
ip2bus_mstwr_req => ipif_ip2bus_mstwr_req,
ip2bus_mst_addr => ipif_ip2bus_mst_addr,
ip2bus_mst_be => ipif_ip2bus_mst_be,
ip2bus_mst_length => ipif_ip2bus_mst_length,
ip2bus_mst_type => ipif_ip2bus_mst_type,
ip2bus_mst_lock => ipif_ip2bus_mst_lock,
ip2bus_mst_reset => ipif_ip2bus_mst_reset,
bus2ip_mst_cmdack => ipif_bus2ip_mst_cmdack,
bus2ip_mst_cmplt => ipif_bus2ip_mst_cmplt,
bus2ip_mst_error => ipif_bus2ip_mst_error,
bus2ip_mst_rearbitrate => ipif_bus2ip_mst_rearbitrate,
bus2ip_mst_cmd_timeout => ipif_bus2ip_mst_cmd_timeout,
bus2ip_mstrd_d => ipif_bus2ip_mstrd_d,
bus2ip_mstrd_rem => ipif_bus2ip_mstrd_rem,
bus2ip_mstrd_sof_n => ipif_bus2ip_mstrd_sof_n,
bus2ip_mstrd_eof_n => ipif_bus2ip_mstrd_eof_n,
bus2ip_mstrd_src_rdy_n => ipif_bus2ip_mstrd_src_rdy_n,
bus2ip_mstrd_src_dsc_n => ipif_bus2ip_mstrd_src_dsc_n,
ip2bus_mstrd_dst_rdy_n => ipif_ip2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_dst_dsc_n => ipif_ip2bus_mstrd_dst_dsc_n,
ip2bus_mstwr_d => ipif_ip2bus_mstwr_d,
ip2bus_mstwr_rem => ipif_ip2bus_mstwr_rem,
ip2bus_mstwr_src_rdy_n => ipif_ip2bus_mstwr_src_rdy_n,
ip2bus_mstwr_src_dsc_n => ipif_ip2bus_mstwr_src_dsc_n,
ip2bus_mstwr_sof_n => ipif_ip2bus_mstwr_sof_n,
ip2bus_mstwr_eof_n => ipif_ip2bus_mstwr_eof_n,
bus2ip_mstwr_dst_rdy_n => ipif_bus2ip_mstwr_dst_rdy_n,
bus2ip_mstwr_dst_dsc_n => ipif_bus2ip_mstwr_dst_dsc_n
);
ipif_Bus2IP_Clk <= M_AXI_ACLK;
ipif_Bus2IP_Resetn <= M_AXI_ARESETN;
M_AXI_AWCACHE <= (others => '1');
M_AXI_ARCACHE <= (others => '1');
M_AXI_AWUSER <= (others => '1');
M_AXI_ARUSER <= (others => '1');
end implementation;
| gpl-2.0 | 589a5bc54b2060d5e82c5b747bd9a802 | 0.577995 | 2.795784 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/arriaiigz_pcie_hip_components.vhd | 1 | 71,791 | -- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package ARRIAIIGZ_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- arriaiigz_pciehip_pciexp_dcfiforam
--
COMPONENT arriaiigz_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- arriaiigz_hssi_pcie_hip
--
COMPONENT arriaiigz_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "arriaiigz_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end arriaiigz_pcie_hip_components;
package body ARRIAIIGZ_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end ARRIAIIGZ_PCIE_HIP_COMPONENTS;
| gpl-3.0 | 7623300965d9b785b2e8a3c7397ade16 | 0.522781 | 4.296033 | false | false | false | false |
freecores/t400 | rtl/vhdl/system/t421.vhd | 1 | 7,609 | -------------------------------------------------------------------------------
--
-- T421 system toplevel.
--
-- $Id: t421.vhd,v 1.2 2008-08-23 11:19:20 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t421 is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_8_c;
opt_cko_g : integer := t400_opt_cko_crystal_c;
opt_l_out_type_7_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_6_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_5_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_4_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_l_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_d_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_3_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_2_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_1_g : integer := t400_opt_out_type_std_c;
opt_g_out_type_0_g : integer := t400_opt_out_type_std_c;
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
ck_i : in std_logic;
ck_en_i : in std_logic;
reset_n_i : in std_logic;
cko_i : in std_logic;
io_l_b : inout std_logic_vector(7 downto 0);
io_d_o : out std_logic_vector(3 downto 0);
io_g_b : inout std_logic_vector(3 downto 0);
si_i : in std_logic;
so_o : out std_logic;
sk_o : out std_logic
);
end t421;
use work.t400_system_comp_pack.t420_notri;
architecture struct of t421 is
signal io_l_from_t420_s,
io_l_en_s : std_logic_vector(7 downto 0);
signal io_d_from_t420_s,
io_d_en_s : std_logic_vector(3 downto 0);
signal io_g_from_t420_s,
io_g_en_s : std_logic_vector(3 downto 0);
signal so_s,
so_en_s : std_logic;
signal sk_s,
sk_en_s : std_logic;
signal vdd4_s : std_logic_vector(3 downto 0);
begin
vdd4_s <= (others => '1');
-----------------------------------------------------------------------------
-- T420 without tri-states in T421 configuration
-----------------------------------------------------------------------------
t420_notri_b : t420_notri
generic map (
opt_type_g => t400_opt_type_421_c,
opt_ck_div_g => opt_ck_div_g,
opt_cko_g => opt_cko_g,
opt_l_out_type_7_g => opt_l_out_type_7_g,
opt_l_out_type_6_g => opt_l_out_type_6_g,
opt_l_out_type_5_g => opt_l_out_type_5_g,
opt_l_out_type_4_g => opt_l_out_type_4_g,
opt_l_out_type_3_g => opt_l_out_type_3_g,
opt_l_out_type_2_g => opt_l_out_type_2_g,
opt_l_out_type_1_g => opt_l_out_type_1_g,
opt_l_out_type_0_g => opt_l_out_type_0_g,
opt_microbus_g => t400_opt_no_microbus_c,
opt_d_out_type_3_g => opt_d_out_type_3_g,
opt_d_out_type_2_g => opt_d_out_type_2_g,
opt_d_out_type_1_g => opt_d_out_type_1_g,
opt_d_out_type_0_g => opt_d_out_type_0_g,
opt_g_out_type_3_g => opt_g_out_type_3_g,
opt_g_out_type_2_g => opt_g_out_type_2_g,
opt_g_out_type_1_g => opt_g_out_type_1_g,
opt_g_out_type_0_g => opt_g_out_type_0_g,
opt_so_output_type_g => opt_so_output_type_g,
opt_sk_output_type_g => opt_sk_output_type_g
)
port map (
ck_i => ck_i,
ck_en_i => ck_en_i,
reset_n_i => reset_n_i,
cko_i => cko_i,
io_l_i => io_l_b,
io_l_o => io_l_from_t420_s,
io_l_en_o => io_l_en_s,
io_d_o => io_d_from_t420_s,
io_d_en_o => io_d_en_s,
io_g_i => io_g_b,
io_g_o => io_g_from_t420_s,
io_g_en_o => io_g_en_s,
io_in_i => vdd4_s,
si_i => si_i,
so_o => so_s,
so_en_o => so_en_s,
sk_o => sk_s,
sk_en_o => sk_en_s
);
-----------------------------------------------------------------------------
-- Tri-states for output drivers
-----------------------------------------------------------------------------
io_l_tri: for idx in 7 downto 0 generate
io_l_b(idx) <= io_l_from_t420_s(idx)
when io_l_en_s(idx) = '1' else
'Z';
end generate;
--
io_d_tri: for idx in 3 downto 0 generate
io_d_o(idx) <= io_d_from_t420_s(idx)
when io_d_en_s(idx) = '1' else
'Z';
end generate;
--
io_g_tri: for idx in 3 downto 0 generate
io_g_b(idx) <= io_g_from_t420_s(idx)
when io_g_en_s(idx) = '1' else
'Z';
end generate;
--
so_o <= so_s
when so_en_s = '1' else
'Z';
--
sk_o <= sk_s
when sk_en_s = '1' else
'Z';
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2006/06/11 13:47:24 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | cbba4d45f8042b9bd92d009b3acd4475 | 0.531344 | 2.979248 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/dio_mod.vhd | 1 | 9,422 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DIO_MOD is
generic (
-- IO-REQ: 2 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000010";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
OUT_EN: in std_logic;
SCLK_EDGE: in std_logic;
SCLK_STATE: in std_logic;
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
SV : inout std_logic_vector(10 downto 3)
);
end;
architecture rtl of DIO_MOD is
constant OUT_TEST_PATTERN: std_logic_vector(7 downto 0) := "10110010";
constant IN_TEST_PATTERN: std_logic_vector(7 downto 0) := "10101100";
signal wb_data_mux : std_logic_vector(31 downto 0);
signal shift_cnt: std_logic_vector(5 downto 0);
signal bitcnt_sync: std_logic;
signal bitcnt_top: std_logic;
signal ssync: std_logic;
signal sclk: std_logic;
signal output_fault: std_logic;
signal output_fault_in: std_logic;
signal output_fault_sync: std_logic_vector(1 downto 0);
signal output_fault_dly: std_logic_vector(9 downto 0) := (others => '1');
signal si_out: std_logic;
signal so_out: std_logic;
signal so_out_data: std_logic_vector(39 downto 0);
signal so_out_shift: std_logic_vector(47 downto 0);
signal si_out_shift: std_logic_vector(7 downto 0);
signal out_data_error: std_logic;
signal si_in: std_logic;
signal so_in: std_logic;
signal so_in_shift: std_logic_vector(7 downto 0);
signal si_in_shift: std_logic_vector(47 downto 0);
signal si_in_data: std_logic_vector(39 downto 0);
signal in_data_error: std_logic;
signal output_fault_reg: std_logic;
signal out_data_error_reg: std_logic;
signal in_data_error_reg: std_logic;
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= si_in_data(31 downto 0);
when WB_ADDR_OFFSET + 1 =>
wb_data_mux <= (others => '0');
wb_data_mux(7 downto 0) <= si_in_data(39 downto 32);
wb_data_mux(16) <= output_fault_reg;
wb_data_mux(17) <= out_data_error_reg;
wb_data_mux(18) <= in_data_error_reg;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
so_out_data <= (others => '0');
output_fault_reg <= '0';
out_data_error_reg <= '0';
in_data_error_reg <= '0';
elsif rising_edge(WB_CLK) then
-- reset error flags when output is disabled
if OUT_EN = '0' then
so_out_data <= (others => '0');
output_fault_reg <= '0';
out_data_error_reg <= '0';
in_data_error_reg <= '0';
end if;
-- set error flags on error
if output_fault = '1' then
output_fault_reg <= '1';
end if;
if out_data_error = '1' then
out_data_error_reg <= '1';
end if;
if in_data_error = '1' then
in_data_error_reg <= '1';
end if;
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
so_out_data(31 downto 0) <= WB_DATA_IN;
when WB_ADDR_OFFSET + 1 =>
so_out_data(39 downto 32) <= WB_DATA_IN(7 downto 0);
if WB_DATA_IN(16) = '1' then
output_fault_reg <= '0';
end if;
if WB_DATA_IN(17) = '1' then
out_data_error_reg <= '0';
end if;
if WB_DATA_IN(18) = '1' then
in_data_error_reg <= '0';
end if;
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- serial clock
----------------------------------------------------------
p_sclk: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
ssync <= '0';
sclk <= '1';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' then
ssync <= '0';
sclk <= '1';
if SCLK_STATE = '1' then
if bitcnt_sync = '1' then
ssync <= '1';
else
sclk <= '0';
end if;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- shift counter
----------------------------------------------------------
p_bitcnt_cnt: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
shift_cnt <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '1' then
if bitcnt_top = '1' then
shift_cnt <= (others => '0');
else
shift_cnt <= shift_cnt + 1;
end if;
end if;
end if;
end process;
bitcnt_sync <= '1' when shift_cnt = 47 else '0';
bitcnt_top <= '1' when shift_cnt = 48 else '0';
----------------------------------------------------------
--- output shift registers
----------------------------------------------------------
p_so_out_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
so_out_shift <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_top = '1' then
so_out_shift <= OUT_TEST_PATTERN & so_out_data;
else
so_out_shift <= so_out_shift(46 downto 0) & "1";
end if;
end if;
end if;
end process;
so_out <= so_out_shift(47);
p_si_out_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
si_out_shift <= (others => '0');
out_data_error <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_sync = '1' then
if si_out_shift /= OUT_TEST_PATTERN then
out_data_error <= '1';
else
out_data_error <= '0';
end if;
si_out_shift <= (others => '0');
else
si_out_shift <= si_out_shift(6 downto 0) & si_out;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- input shift registers
----------------------------------------------------------
p_so_in_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
so_in_shift <= (others => '0');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_top = '1' then
so_in_shift <= IN_TEST_PATTERN;
else
so_in_shift <= so_in_shift(6 downto 0) & "0";
end if;
end if;
end if;
end process;
so_in <= so_in_shift(7);
p_si_in_shift: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
si_in_data <= (others => '0');
si_in_shift <= (others => '0');
in_data_error <= '0';
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if bitcnt_sync = '1' then
if si_in_shift(7 downto 0) /= IN_TEST_PATTERN then
in_data_error <= '1';
else
in_data_error <= '0';
si_in_data <= si_in_shift(47 downto 8);
end if;
si_in_shift <= (others => '0');
else
si_in_shift <= si_in_shift(46 downto 0) & si_in;
end if;
end if;
end if;
end process;
----------------------------------------------------------
--- output fault delay
----------------------------------------------------------
p_output_fault_sync: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
output_fault_sync <= (others => '0');
elsif rising_edge(WB_CLK) then
output_fault_sync <= output_fault_in & output_fault_sync(1);
end if;
end process;
p_output_fault_dly: process(WB_CLK, WB_RST)
begin
if (WB_RST = '1') then
output_fault_dly <= (others => '1');
elsif rising_edge(WB_CLK) then
if SCLK_EDGE = '1' and SCLK_STATE = '0' then
if output_fault_sync(0) = '1' then
if output_fault = '0' then
output_fault_dly <= output_fault_dly - 1;
end if;
else
output_fault_dly <= (others => '1');
end if;
end if;
end if;
end process;
output_fault <= '1' when output_fault_dly = 0 else '0';
----------------------------------------------------------
--- output mapping
----------------------------------------------------------
output_fault_in <= not SV(3);
si_in <= SV(5);
si_out <= not SV(6);
SV(4) <= OUT_EN;
SV(7) <= ssync;
SV(8) <= sclk;
SV(9) <= so_in;
SV(10) <= not so_out;
end;
| gpl-3.0 | 2af6b992bdd640797fe82d5ddf6664c6 | 0.494375 | 3.324629 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/ip/base_zynq_design_axi_gpio_0_0/synth/base_zynq_design_axi_gpio_0_0.vhd | 1 | 10,099 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY base_zynq_design_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END base_zynq_design_axi_gpio_0_0;
ARCHITECTURE base_zynq_design_axi_gpio_0_0_arch OF base_zynq_design_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF base_zynq_design_axi_gpio_0_0_arch : ARCHITECTURE IS "base_zynq_design_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF base_zynq_design_axi_gpio_0_0_arch: ARCHITECTURE IS "base_zynq_design_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=5,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 5,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => gpio2_io_i
);
END base_zynq_design_axi_gpio_0_0_arch;
| gpl-3.0 | 117f89b553268d9c6c9d2251e7d6899b | 0.689177 | 3.161866 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/mdsio/wdt_mod.vhd | 1 | 3,618 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity WDT_MOD is
generic (
-- IO-REQ: 1 DWORD
WB_CONF_OFFSET: std_logic_vector(15 downto 2) := "00000000000000";
WB_CONF_DATA: std_logic_vector(15 downto 0) := "0000000000000001";
WB_ADDR_OFFSET: std_logic_vector(15 downto 2) := "00000000000000"
);
port (
WB_CLK: in std_logic;
WB_RST: in std_logic;
WB_ADDR: in std_logic_vector(15 downto 2);
WB_DATA_OUT: out std_logic_vector(31 downto 0);
WB_DATA_IN: in std_logic_vector(31 downto 0);
WB_STB_RD: in std_logic;
WB_STB_WR: in std_logic;
RUN: out std_logic;
OUT_EN: out std_logic
);
end;
architecture rtl of WDT_MOD is
constant RAND_SEED: std_logic_vector(15 downto 0) := "1111111111111000";
signal wb_data_mux : std_logic_vector(31 downto 0);
signal rand: std_logic_vector(15 downto 0) := RAND_SEED;
signal rand_ok: std_logic;
signal out_en_reg: std_logic;
signal timer: std_logic_vector(19 downto 0);
signal timeout: std_logic;
signal cycle_cnt: std_logic_vector(3 downto 0) := (others => '1');
signal cycle_ok: std_logic;
begin
----------------------------------------------------------
--- bus logic
----------------------------------------------------------
P_WB_RD : process(WB_ADDR)
begin
case WB_ADDR is
when WB_CONF_OFFSET =>
wb_data_mux(15 downto 0) <= WB_CONF_DATA;
wb_data_mux(31 downto 16) <= WB_ADDR_OFFSET & "00";
when WB_ADDR_OFFSET =>
wb_data_mux <= (others => '0');
wb_data_mux(15 downto 0) <= rand;
wb_data_mux(16) <= out_en_reg;
when others =>
wb_data_mux <= (others => '0');
end case;
end process;
P_WB_RD_REG : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
WB_DATA_OUT <= (others => '0');
elsif rising_edge(WB_CLK) then
if WB_STB_RD = '1' then
WB_DATA_OUT <= wb_data_mux;
end if;
end if;
end process;
P_PE_REG_WR : process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
out_en_reg <= '0';
rand <= RAND_SEED;
rand_ok <= '0';
elsif rising_edge(WB_CLK) then
rand_ok <= '0';
if WB_STB_WR = '1' then
case WB_ADDR is
when WB_ADDR_OFFSET =>
out_en_reg <= WB_DATA_IN(16);
if (WB_DATA_IN(15 downto 0) = rand) then
rand_ok <= '1';
end if;
rand <= rand(14 downto 0) & (rand(15) xor rand(10));
when others =>
end case;
end if;
end if;
end process;
----------------------------------------------------------
--- watchdog
----------------------------------------------------------
-- Timeout
P_WDT: process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
timer <= (others => '0');
elsif rising_edge(WB_CLK) then
if rand_ok = '1' then
timer <= (others => '1');
elsif timeout = '0' then
timer <= timer - 1;
end if;
end if;
end process;
timeout <= '1' when timer = 0 else '0';
-- initial cycle counter
P_CYCLE_CNT: process(WB_RST, WB_CLK)
begin
if WB_RST = '1' then
cycle_cnt <= (others => '1');
elsif rising_edge(WB_CLK) then
if timeout = '1' then
cycle_cnt <= (others => '1');
elsif rand_ok = '1' and cycle_ok = '0' then
cycle_cnt <= cycle_cnt - 1;
end if;
end if;
end process;
cycle_ok <= '1' when cycle_cnt = 0 else '0';
-- set outputs
RUN <= cycle_ok;
OUT_EN <= out_en_reg and cycle_ok;
end;
| gpl-3.0 | 66dfdedc85e4f349d2473ee092865600 | 0.52764 | 3.250674 | false | false | false | false |
google/myelin-acorn-electron-hardware | spi_sd_card/cpld/spi_sd_card.vhd | 1 | 6,889 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity spi_sd_card is
Port (
elk_D : inout std_logic_vector(7 downto 0);
elk_nINFC : in std_logic;
elk_A7 : in std_logic;
elk_A6 : in std_logic;
elk_A5 : in std_logic;
elk_A4 : in std_logic;
elk_A2 : in std_logic;
elk_A1 : in std_logic;
elk_A0 : in std_logic;
elk_nRST : in std_logic;
elk_RnW : in std_logic;
elk_PHI0 : in std_logic;
tube_A0 : out std_logic;
tube_A1 : out std_logic; -- serial TXD
tube_A2 : in std_logic; -- serial RXD
tube_D : inout std_logic_vector(7 downto 0);
-- D5 = /SS
-- D6 = MOSI
-- D7 = SCK
-- D0 = MISO
tube_nRST : out std_logic; -- serial RTS
tube_nTUBE : out std_logic;
tube_RnW : out std_logic;
tube_PHI0 : out std_logic
);
end spi_sd_card;
architecture Behavioural of spi_sd_card is
---- Serial port ----
signal TXD : std_logic := '1'; -- output from CPLD/Electron
signal RXD : std_logic; -- input to CPLD/Electron
signal RTS : std_logic := '1'; -- request for data from PC
signal CTS : std_logic; -- PC is allowing us to send
signal invert_serial : std_logic := '1'; -- invert serial port for UPURS
-- chip selects
signal nSERIAL_IO : std_logic; -- '0' when A = &FCB1
---- SPI ---
signal MOSI : std_logic := '1';
signal MISO : std_logic;
signal SCK : std_logic := '1';
signal nSS : std_logic := '0';
signal A_lower : std_logic_vector(7 downto 0);
---- Memory mapped SPI registers ----
-- chip selects
signal nSPI : std_logic; -- '0' when A = &FCD0
signal nSPI_STATUS : std_logic; -- '0' when A = &FCD1
-- data register
signal REG : std_logic_vector(7 downto 0) := x"00";
-- transfer in progress when '1'
signal transfer_in_progress : std_logic := '0';
-- transfer bit counter
signal bit_count : std_logic_vector(3 downto 0) := (others => '0');
-- delay bit, to make everything slower
signal delay : std_logic_vector(3 downto 0) := (others => '0');
---- Plus 1 workalike registers ----
-- chip selects
signal nDATA : std_logic; -- '0' when A = &FC71/FCC1
signal nSTATUS : std_logic; -- '0' when A = &FC72/FCC2
begin
-- mappings to actual pins
tube_D(5) <= nSS;
tube_D(6) <= MOSI;
tube_D(7) <= SCK;
MISO <= tube_D(0);
--tube_A1 <= elk_PHI0; -- DEBUG: show clock
--tube_A1 <= '1' when nSERIAL_IO='0' and elk_PHI0='1' else '0'; -- DEBUG: show reg accesses
tube_A1 <= TXD; -- tx output
RXD <= tube_A2; -- rx input
tube_nRST <= RTS; -- permit remote station to send when RTS=1
CTS <= '1'; -- assume we can always send to the remote station
-- address comparison convenience (note missing A3 in elk_pi_tube_direct r1)
A_lower <= elk_A7 & elk_A6 & elk_A5 & elk_A4 & '0' & elk_A2 & elk_A1 & elk_A0;
---- Bit-banged serial port for UPURS ---
nSERIAL_IO <= '0' when (elk_nINFC = '0' and A_lower = x"B1") else '1';
---- Memory-mapped SPI ----
nSPI <= '0' when (elk_nINFC = '0' and A_lower = x"D0") else '1';
nSPI_STATUS <= '0' when (elk_nINFC = '0' and A_lower = x"D1") else '1';
---- Plus 1 parallel port emulation ----
-- Uncomment to use the Plus 1 registers; this will conflict if you
-- are using this with a real Plus 1 though.
-- nDATA <= '0' when (elk_nINFC = '0' and A_lower = x"71") else '1';
-- nSTATUS <= '0' when (elk_nINFC = '0' and A_lower = x"72") else '1';
nDATA <= '0' when (elk_nINFC = '0' and A_lower = x"C1") else '1';
nSTATUS <= '0' when (elk_nINFC = '0' and A_lower = x"C2") else '1';
---- Data bus ----
elk_D <=
-- Serial port
(RXD xor invert_serial) & "11111" & CTS & "1" when (nSERIAL_IO = '0' and elk_RnW = '1') else
-- Memory-mapped SPI
x"4" & bit_count when (nSPI = '0' and elk_RnW = '1' and transfer_in_progress = '1') else
REG when (nSPI = '0' and elk_RnW = '1') else
"0000000" & transfer_in_progress when (nSPI_STATUS = '0' and elk_RnW = '1') else
-- Plus 1 parallel port
MISO & "0000000" when (nSTATUS = '0' and elk_RnW = '1') else
-- default
"ZZZZZZZZ";
-- handle writes
process (elk_PHI0)
begin
if falling_edge(elk_PHI0) then
-- Serial port: Electron is writing RTS and TXD bits
if nSERIAL_IO = '0' and elk_RnW = '0' then
RTS <= elk_D(6);
TXD <= elk_D(0) xor invert_serial;
--TXD <= elk_D(7) xor invert_serial; -- DEBUG allow upurs to echo chars back
end if;
-- Memory-mapped and bit-banged SPI
if transfer_in_progress = '1' then
-- first priority: service any current SPI transfers
if delay /= "0000" then
delay <= std_logic_vector(unsigned(delay) + 1);
else
delay <= "0000"; -- 0000 for no delay, 1111 for 1 cycle, ..., 0001 for 15 cycles
if SCK = '1' then
-- change MOSI on falling edge
MOSI <= REG(7);
SCK <= '0';
else
-- read MISO on rising edge
SCK <= '1';
REG <= REG(6 downto 0) & MISO;
if bit_count = "0111" then
transfer_in_progress <= '0';
else
bit_count <= std_logic_vector(unsigned(bit_count) + 1);
end if;
end if;
end if;
elsif nSPI = '0' and elk_RnW = '0' then
-- the Electron is writing to &FCD0 to start a transfer
REG <= elk_D;
transfer_in_progress <= '1';
bit_count <= "0000";
SCK <= '1';
elsif nDATA = '0' and elk_RnW = '0' then
-- the electron is writing to the data register (&FC71/&FCC1)
MOSI <= elk_D(0);
SCK <= elk_D(1);
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 959654299e3955c83c2f7e567d035b98 | 0.532733 | 3.434197 | false | false | false | false |
google/myelin-acorn-electron-hardware | fx2_tube_cartridge_adapter/cpld/fx2_tube_cartridge_adapter.vhd | 1 | 4,945 | -- Copyright 2017 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- This assumes that the board only has an FX2 fitted, and not a Raspberry
-- Pi. It also assumes that it's connected to an Electron, and the 16MHz
-- clock is present. This will not work yet when plugged into a BBC Micro's
-- Tube interface, and has not yet been tested as a BBC Master cartridge.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fx2_tube_cartridge_adapter is
Port (
cpu_D : inout std_logic_vector(7 downto 0);
cpu_A7 : in std_logic;
cpu_A6 : in std_logic;
cpu_A5 : in std_logic;
cpu_A4 : in std_logic;
cpu_A2 : in std_logic;
cpu_A1 : in std_logic;
cpu_A0 : in std_logic;
cpu_RnW : in std_logic;
cpu_CLK : in std_logic;
elk_nINFC : in std_logic;
elk_16MHz : in std_logic;
bbc_nTUBE : inout std_logic;
tube_A0 : out std_logic;
tube_A1 : out std_logic;
tube_A2 : out std_logic;
tube_D : inout std_logic_vector(7 downto 0);
tube_nRST : in std_logic; -- driven by a diode and resistor
tube_nTUBE : out std_logic;
tube_RnW : out std_logic;
tube_CLK : out std_logic
);
end fx2_tube_cartridge_adapter;
architecture Behavioural of fx2_tube_cartridge_adapter is
-- '0' when A = &FCEx: Tube memory space
signal nTUBE : std_logic;
-- true when the Pi can drive the bus
signal pi_may_drive_bus : boolean;
-- Reconstructed clock
signal out_CLK : std_logic;
signal clean_CLK : std_logic := '0';
signal clean_CLK_ignore : std_logic := '0';
-- Flag to say we should wait to drive the bus until the next rising clock edge
signal wait_for_pi_to_drop_bus : boolean := false;
-- Small counter to check for presence of 16MHz clock on the cartridge port
signal cart_detect_count : std_logic_vector(2 downto 0) := (others => '0');
-- Indicates cartridge port being used, rather than tube interface
signal cart_detect : std_logic;
begin
-- tube /CE signal: A = &FCEx
nTUBE <= '0' when cart_detect = '1' and elk_nINFC = '0' and cpu_A7 = '1' and cpu_A6 = '1' and cpu_A5 = '1' and cpu_A4 = '0' else
'0' when cart_detect = '0' and bbc_nTUBE = '0' else
'1';
tube_nTUBE <= nTUBE;
pi_may_drive_bus <= (nTUBE = '0' and cpu_RnW = '1');
-- copy across other signals
tube_RnW <= cpu_RnW;
tube_CLK <= out_CLK;
tube_A0 <= cpu_A0;
tube_A1 <= cpu_A1;
tube_A2 <= cpu_A2;
-- For PiTubeDirect: data goes both ways
-- See http://stardot.org.uk/forums/viewtopic.php?f=3&t=11325&p=189382#p189382
tube_D <=
-- Drop the bus when the Pi might be driving it
"ZZZZZZZZ" when wait_for_pi_to_drop_bus or pi_may_drive_bus else
-- Otherwise copy over the CPU bus for the FX2 to monitor
cpu_D;
cpu_D <=
tube_D when pi_may_drive_bus and out_CLK = '1' else
"ZZZZZZZZ";
-- Track when PiTubeDirect might possibly be still driving the bus
process (out_CLK)
begin
if rising_edge(out_CLK) then
wait_for_pi_to_drop_bus <= pi_may_drive_bus;
end if;
end process;
-- clean up cpu_CLK by ignoring falling edges for a while after a rising edge
process (elk_16MHz)
begin
-- 16MHz clock has period 62.5 ns, so two clocks = 125 ns and three clocks = 187.5 ns
-- Electron clock has min high time 250ns, and glitches for about 100ns sometimes.
-- So our process should be to set clean_CLK high as soon as cpu_CLK goes high, and
-- ignore any high-to-low transitions that happen in the next 16MHz clock cycle.
if rising_edge(elk_16MHz) then
if cart_detect = '0' then
cart_detect_count <= cart_detect_count + 1;
end if;
if clean_CLK_ignore = '1' then
clean_CLK_ignore <= '0';
else
if clean_CLK = '0' and cpu_CLK = '1' then
clean_CLK_ignore <= '1';
end if;
clean_CLK <= cpu_CLK;
end if;
end if;
end process;
cart_detect <= cart_detect_count(cart_detect_count'high);
out_CLK <= clean_CLK when cart_detect = '1' else cpu_CLK; -- mux with cpu_CLK if elk_16MHz isn't present
end Behavioural;
| apache-2.0 | 3b5eb1f9b923bfff99c0a2585e6f7906 | 0.617796 | 3.359375 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci_top.vhd | 1 | 12,391 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity pci_top is
generic (
BARS : string := "1BARMEM";
WBSIZE : integer := 32;
WBENDIAN : string := "LITTLE"
);
port (
-- onboard clock
onboard_clock : in std_logic;
-- PCI Target 32 bits
pclk : in std_logic;
rst_n : in std_logic;
ad : inout std_logic_vector(31 downto 0);
cbe_n : in std_logic_vector(3 downto 0);
par : inout std_logic;
frame_n : in std_logic;
irdy_n : in std_logic;
trdy_n : inout std_logic;
devsel_n : inout std_logic;
stop_n : inout std_logic;
idsel : in std_logic;
perr_n : inout std_logic;
serr_n : inout std_logic;
inta_n : out std_logic;
req_n : out std_logic;
gnt_n : in std_logic;
-- JTAG drive
-- tdi : in std_logic;
-- tms : out std_logic;
-- tck : out std_logic;
-- tdo : out std_logic;
-- CAN Transceivers
can1_tx : out std_logic;
can1_rx : in std_logic;
can2_tx : out std_logic;
can2_rx : in std_logic;
-- 2x40 Connector
LED_CONF : out std_logic;
LED_RUN : out std_logic;
SV1 : inout std_logic_vector(10 downto 3);
SV2 : inout std_logic_vector(10 downto 3);
SV3 : inout std_logic_vector(10 downto 3);
SV4 : inout std_logic_vector(10 downto 3);
SV5 : inout std_logic_vector(10 downto 3);
SV6 : inout std_logic_vector(10 downto 3);
SV7 : inout std_logic_vector(10 downto 3);
SV8 : inout std_logic_vector(10 downto 3);
SV9 : inout std_logic_vector(10 downto 3)
);
end pci_top;
architecture rtl of pci_top is
signal clk32ib : std_logic;
signal clk32ob : std_logic;
signal clk32 : std_logic;
signal clk8ob : std_logic;
signal clk8 : std_logic;
signal clk100ob : std_logic;
signal clk100 : std_logic;
signal dcm_locked : std_logic;
signal sclk_cnt : std_logic_vector(4 downto 0);
signal sclk_edge : std_logic;
signal sclk_state : std_logic;
signal wb_clk : std_logic;
signal wb_rst : std_logic;
signal wb_adr : std_logic_vector(24 downto 0);
signal wb_datrd : std_logic_vector(WBSIZE-1 downto 0);
signal wb_datwr : std_logic_vector(WBSIZE-1 downto 0);
signal wb_sel : std_logic_vector(((WBSIZE/8)-1) downto 0);
signal wb_we : std_logic;
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal wb_ack : std_logic;
signal wb_irq : std_logic;
signal pci_ad_out : std_logic_vector(31 downto 0);
signal pci_ad_oe : std_logic;
signal pci_par_out : std_logic;
signal pci_par_oe : std_logic;
signal pci_trdy_out : std_logic;
signal pci_devsel_out : std_logic;
signal pci_stop_out : std_logic;
signal pci_targ_oe : std_logic;
signal pci_perr_drv : std_logic;
signal pci_serr_drv : std_logic;
signal pci_inta_drv : std_logic;
signal pci_req_drv : std_logic;
signal mds_cs : std_logic;
signal mds_stb : std_logic;
signal mds_stb_wr : std_logic;
signal mds_stb_rd : std_logic;
signal mds_ack : std_logic;
signal mds_oe : std_logic;
signal mds_run : std_logic;
signal mds_addr : std_logic_vector(15 downto 2);
signal mds_datrd : std_logic_vector(31 downto 0);
signal mds_datrd1 : std_logic_vector(31 downto 0);
signal mds_datrd2 : std_logic_vector(31 downto 0);
signal mds_datrd3 : std_logic_vector(31 downto 0);
signal mds_datrd4 : std_logic_vector(31 downto 0);
signal mds_datrd5 : std_logic_vector(31 downto 0);
signal mds_datrd6 : std_logic_vector(31 downto 0);
signal mds_datrd7 : std_logic_vector(31 downto 0);
signal mds_datrd8 : std_logic_vector(31 downto 0);
begin
----------------------------------------------------------
-- Clock & Reset
----------------------------------------------------------
wb_rst <= (not rst_n) or (not dcm_locked);
U_CLKPCI_IBUFG : IBUFG port map ( I => pclk, O => wb_clk);
U_CLK32_IBUFG : IBUFG port map ( I => onboard_clock, O => clk32ib);
U_DCM : DCM
generic map(
CLKDV_DIVIDE => 4.0,
CLKFX_DIVIDE => 8,
CLKFX_MULTIPLY => 25,
CLKIN_PERIOD => 31.250,
FACTORY_JF => x"8080"
)
port map (
CLKFB => clk32,
CLKIN => clk32ib,
DSSEN => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => not rst_n,
CLKDV => clk8ob,
CLK0 => clk32ob,
CLKFX => clk100ob,
LOCKED => dcm_locked
);
U_CLK32_BUFG : BUFG port map ( I => clk32ob, O => clk32);
U_CLK8_BUFG : BUFG port map ( I => clk8ob, O => clk8);
U_CLK100_BUFG : BUFG port map ( I => clk100ob, O => clk100);
p_sclk: process(wb_rst, wb_clk)
begin
if (wb_rst = '1') then
sclk_cnt <= (others => '0');
elsif rising_edge(wb_clk) then
sclk_cnt <= sclk_cnt + 1;
end if;
end process;
sclk_edge <= '1' when sclk_cnt(3 downto 0) = 0 else '0';
sclk_state <= sclk_cnt(4);
----------------------------------------------------------
-- PCI <--> Whisbone Bridge
----------------------------------------------------------
-- PCI Interface
U_PCI: entity work.pci32tLite
generic map (
vendorID => x"4150",
deviceID => x"0007",
revisionID => x"00",
subsystemID => x"0202",
subsystemvID => x"1172",
classcodeID => x"068000",
BARS => BARS,
WBSIZE => WBSIZE,
WBENDIAN => WBENDIAN
)
port map (
--General
clk33 => wb_clk,
rst => wb_rst,
-- PCI target 32bits
ad_in => ad,
ad_out => pci_ad_out,
ad_oe => pci_ad_oe,
cbe => cbe_n,
par_in => par,
par_out => pci_par_out,
par_oe => pci_par_oe,
frame => frame_n,
irdy => irdy_n,
trdy_out => pci_trdy_out,
devsel_out => pci_devsel_out,
stop_out => pci_stop_out,
targ_oe => pci_targ_oe,
idsel => idsel,
perr_drv => pci_perr_drv,
serr_drv => pci_serr_drv,
inta_drv => pci_inta_drv,
req_drv => pci_req_drv,
gnt => gnt_n,
-- Master whisbone
wb_adr_o => wb_adr,
wb_dat_i => wb_datrd,
wb_dat_o => wb_datwr,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_stb_o => wb_stb,
wb_cyc_o => wb_cyc,
wb_ack_i => wb_ack,
wb_rty_i => '0',
wb_err_i => '0',
wb_int_i => wb_irq
);
-- pci open drain / tristate
ad <= pci_ad_out when pci_ad_oe = '1' else (others => 'Z');
par <= pci_par_out when pci_par_oe = '1' else 'Z';
trdy_n <= pci_trdy_out when pci_targ_oe = '1' else 'Z';
devsel_n <= pci_devsel_out when pci_targ_oe = '1' else 'Z';
stop_n <= pci_stop_out when pci_targ_oe = '1' else 'Z';
perr_n <= '0' when pci_perr_drv = '1' else 'Z';
serr_n <= '0' when pci_serr_drv = '1' else 'Z';
inta_n <= '0' when pci_inta_drv = '1' else 'Z';
req_n <= '0' when pci_req_drv = '1' else 'Z';
-- irq handling
wb_irq <= '0';
-- whichbone ack
wb_ack <= mds_ack;
----------------------------------------------------------
-- mdsio whisbone adapter
----------------------------------------------------------
mds_cs <= '1' when ((wb_stb = '1') and (wb_cyc = '1')) else '0';
mds_stb <= '1' when mds_cs = '1' and wb_ack = '0' else '0';
mds_stb_rd <= '1' when mds_stb = '1' and wb_we = '0' else '0';
mds_stb_wr <= '1' when mds_stb = '1' and wb_we = '1' else '0';
P_MDS_WB_ACK : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
mds_ack <= '0';
elsif rising_edge(wb_clk) then
mds_ack <= mds_cs;
end if;
end process;
wb_datrd <= mds_datrd;
mds_addr <= wb_adr(15 downto 2);
----------------------------------------------------------
-- mdsio instances
----------------------------------------------------------
U_DIO_MOD0: entity work.DIO_MOD
generic map (
WB_CONF_OFFSET => "00000000000000",
WB_ADDR_OFFSET => "00000000001001"
)
port map (
OUT_EN => mds_oe,
SCLK_EDGE => sclk_edge,
SCLK_STATE => sclk_state,
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd1,
WB_DATA_IN => wb_datwr,
WB_STB_RD => mds_stb_rd,
WB_STB_WR => mds_stb_wr,
SV => SV1
);
U_DAC_MOD0: entity work.DAC_MOD
generic map (
WB_CONF_OFFSET => "00000000000001",
WB_ADDR_OFFSET => "00000000001011"
)
port map (
OUT_EN => mds_oe,
SCLK_EDGE => sclk_edge,
SCLK_STATE => sclk_state,
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd2,
WB_DATA_IN => wb_datwr,
WB_STB_RD => mds_stb_rd,
WB_STB_WR => mds_stb_wr,
SV => SV2
);
U_PHPE_MOD0: entity work.PHPE_MOD
generic map (
WB_CONF_OFFSET => "00000000000010",
WB_ADDR_OFFSET => "00000000001110"
)
port map (
CLK100 => clk100,
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd3,
WB_DATA_IN => wb_datwr,
WB_STB_RD => mds_stb_rd,
WB_STB_WR => mds_stb_wr,
SV => SV3
);
U_PHPE_MOD1: entity work.PHPE_MOD
generic map (
WB_CONF_OFFSET => "00000000000011",
WB_ADDR_OFFSET => "00000000011101"
)
port map (
CLK100 => clk100,
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd4,
WB_DATA_IN => wb_datwr,
WB_STB_RD => mds_stb_rd,
WB_STB_WR => mds_stb_wr,
SV => SV4
);
U_ENC_MOD0: entity work.ENC_MOD
generic map (
WB_CONF_OFFSET => "00000000000100",
WB_ADDR_OFFSET => "00000000101100"
)
port map (
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd5,
WB_STB_RD => mds_stb_rd,
SV => SV5
);
U_ENC_MOD1: entity work.ENC_MOD
generic map (
WB_CONF_OFFSET => "00000000000101",
WB_ADDR_OFFSET => "00000000110011"
)
port map (
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd6,
WB_STB_RD => mds_stb_rd,
SV => SV6
);
U_STEP_MOD0: entity work.STEP_MOD
generic map (
WB_CONF_OFFSET => "00000000000110",
WB_ADDR_OFFSET => "00000000111010"
)
port map (
OUT_EN => mds_oe,
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd7,
WB_DATA_IN => wb_datwr,
WB_STB_RD => mds_stb_rd,
WB_STB_WR => mds_stb_wr,
SV => SV7
);
U_WDT_MOD0: entity work.WDT_MOD
generic map (
WB_CONF_OFFSET => "00000000000111",
WB_ADDR_OFFSET => "00000001001110"
)
port map (
WB_CLK => wb_clk,
WB_RST => wb_rst,
WB_ADDR => mds_addr,
WB_DATA_OUT => mds_datrd8,
WB_DATA_IN => wb_datwr,
WB_STB_RD => mds_stb_rd,
WB_STB_WR => mds_stb_wr,
RUN => mds_run,
OUT_EN => mds_oe
);
mds_datrd <= mds_datrd1 or mds_datrd2 or mds_datrd3 or mds_datrd4 or mds_datrd5 or mds_datrd6 or mds_datrd7 or mds_datrd8;
----------------------------------------------------------
-- Debug Stuff
----------------------------------------------------------
can1_tx <= '0';
can2_tx <= '0';
SV8 <= (others => '0');
SV9 <= (others => '0');
LED_CONF <= '1';
LED_RUN <= mds_run;
end rtl;
| gpl-3.0 | a7e6e640b856ff6c6d427e2b208e033a | 0.484465 | 3.19438 | false | false | false | false |
alvieboy/xtc-base | memory.vhd | 1 | 7,569 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
-- synthesis translate_off
use work.txt_util.all;
-- synthesis translate_on
entity memory is
port (
clk: in std_logic;
rst: in std_logic;
-- Memory interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(31 downto 0);
wb_dat_o: out std_logic_vector(31 downto 0);
wb_adr_o: out std_logic_vector(31 downto 0);
wb_tag_o: out std_logic_vector(31 downto 0);
wb_tag_i: in std_logic_vector(31 downto 0);
wb_err_i: in std_logic;
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_stall_i: in std_logic;
busy: out std_logic;
refetch: out std_logic;
dbgo: out memory_debug_type;
protw: in std_logic_vector(31 downto 0);
proten: in std_logic;
-- Input for previous stages
eui: in execute_output_type;
-- Output for next stages
muo: out memory_output_type
);
end entity memory;
architecture behave of memory is
signal mr: memory_regs_type;
signal mreg_q: regaddress_type;
signal wb_ack_i_q: std_logic;
signal cycle_fault:std_logic;
component reqcnt is
port (
clk: in std_logic;
rst: in std_logic;
stb: in std_logic;
cyc: in std_logic;
stall:in std_logic;
ack: in std_logic;
req: out std_logic;
count: out unsigned(2 downto 0)
);
end component;
signal req_pending: std_logic;
signal endcycle: std_logic;
-- debug only
signal busycnt: unsigned(31 downto 0);
signal faultw: std_logic;
begin
muo.r <= mr;
muo.fault <= mr.fault;
process(eui,mr,clk,rst,wb_ack_i, wb_ack_i_q, wb_dat_i, wb_stall_i, wb_tag_i, wb_err_i,
req_pending)
variable mw: memory_regs_type;
variable wmask: std_logic_vector(3 downto 0);
variable wdata: std_logic_vector(31 downto 0);
variable mdata: std_logic_vector(31 downto 0);
variable queue_request: boolean;
variable mrsel: std_logic_vector(4 downto 0);
begin
mw:=mr;
wdata := (others => DontCareValue);
wmask := (others => DontCareValue);
mw.fault := '0';
case eui.macc is
when M_BYTE | M_BYTE_POSTINC =>
case eui.data_address(1 downto 0) is
when "11" => wdata(7 downto 0) := eui.data_write(7 downto 0); wmask:="0001"; mrsel:="11X00";
when "10" => wdata(15 downto 8) := eui.data_write(7 downto 0); wmask:="0010"; mrsel:="11X01";
when "01" => wdata(23 downto 16) := eui.data_write(7 downto 0); wmask:="0100"; mrsel:="11X10";
when "00" => wdata(31 downto 24) := eui.data_write(7 downto 0); wmask:="1000"; mrsel:="11X11";
when others => null;
end case;
when M_HWORD | M_HWORD_POSTINC =>
case eui.data_address(1) is
when '1' => wdata(15 downto 0) := eui.data_write(15 downto 0); wmask:="0011"; mrsel:="10000";
when '0' => wdata(31 downto 16) := eui.data_write(15 downto 0); wmask:="1100"; mrsel:="10110";
when others => null;
end case;
when others =>
wdata := eui.data_write; wmask:="1111"; mrsel := "00000";
end case;
-- queue_request := false;
muo.mregwe <= '0';
muo.msprwe <= '0';
queue_request := true;
busy<='0';
if wb_stall_i='1' and mr.wb_stb='1' then
queue_request := false;
busy<='1';
end if;
-- Simplify tag.
case wb_tag_i(6 downto 5) is
when "00" => mdata(7 downto 0) := wb_dat_i(7 downto 0);
when "01" => mdata(7 downto 0) := wb_dat_i(15 downto 8);
when "10" => mdata(7 downto 0) := wb_dat_i(23 downto 16);
when "11" => mdata(7 downto 0) := wb_dat_i(31 downto 24);
when others =>
end case;
case wb_tag_i(8 downto 7) is
when "00" => mdata(15 downto 8) := wb_dat_i(15 downto 8);
when "01" => mdata(15 downto 8) := wb_dat_i(31 downto 24);
when others => mdata(15 downto 8) := (others => '0');-- Zero
end case;
case wb_tag_i(9) is
when '0' => mdata(31 downto 16) := wb_dat_i(31 downto 16);
when others => mdata(31 downto 16) := (others => '0');
end case;
if mr.wb_cyc='1' and wb_stall_i='0' then
mw.wb_cyc:='0';
end if;
if queue_request then
mw.wb_we := eui.data_writeenable;
mw.wb_dat := wdata;
mw.wb_adr := eui.data_address;
mw.wb_tago := (others => 'X');
mw.wb_tago(3 downto 0) := eui.mwreg(3 downto 0);
mw.wb_tago(4) := not eui.data_writeenable;
mw.wb_tago(9 downto 5) := mrsel;
mw.wb_tago(10) := eui.mwreg(4);
mw.macc := eui.macc;
mw.wb_sel := wmask;
mw.wb_stb := eui.data_access;
mw.wb_cyc := eui.data_access;
mw.sprwe := eui.sprwe and not eui.data_writeenable;
mw.regwe := (not eui.sprwe) and not eui.data_writeenable;
mw.dreg := eui.mwreg;
mw.pc := eui.npc;
if proten='1' and LOWPROTECTENABLE then
if eui.data_writeenable='1' and eui.data_access='1' then
if (unsigned(eui.data_address)<unsigned(protw)) then
mw.fault := '1';
mw.wb_stb := '0';
mw.faddr := std_logic_vector(eui.npc);
end if;
end if;
end if;
end if;
muo.mdata <= mdata;
muo.mreg <= wb_tag_i(10) & wb_tag_i(3 downto 0);
muo.mregwe <= wb_ack_i and wb_tag_i(4);
refetch <= wb_ack_i and wb_tag_i(4);
if queue_request and eui.clrreg='1' then
muo.mregwe<='1';
muo.mreg<=eui.mwreg;
end if;
if wb_err_i='1' then
mw.fault := '1';
end if;
if rst='1' then
mw.wb_cyc := '0';
mw.wb_stb := '0';
mw.fault := '0';
end if;
if rising_edge(clk) then
mr<=mw;
end if;
end process;
-- debug
dbgo.strobe <= mr.wb_stb and not wb_stall_i;
dbgo.write <= mr.wb_we;
dbgo.address <= unsigned(mr.wb_adr);
dbgo.data <= unsigned(mr.wb_dat);
dbgo.pc <= unsigned(mr.pc);
dbgo.faddr <= unsigned(mr.faddr);
-- Counter
endcycle <= wb_ack_i or wb_err_i;
cnt0: reqcnt port map (
clk => clk,
rst => rst,
stb => mr.wb_stb,
cyc => '1',
stall => wb_stall_i,
ack => endcycle,
req => req_pending,
count => open
);
wb_adr_o <= mr.wb_adr;
wb_stb_o <= mr.wb_stb;
wb_dat_o <= mr.wb_dat;
wb_we_o <= mr.wb_we;
wb_sel_o <= mr.wb_sel;
wb_tag_o <= mr.wb_tago;
wb_cyc_o <= req_pending or mr.wb_cyc;
faultcheck: if FAULTCHECKS generate
-- Internal fault...
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
busycnt<=(others =>'0');
else
if mr.wb_cyc='1' and endcycle='0' then
busycnt<=busycnt+1;
else
busycnt<=(others =>'0');
end if;
end if;
end if;
end process;
-- Cycle check.
cycle_fault<='1' when (req_pending or mr.wb_cyc) /= (req_pending or mr.wb_stb) else '0';
muo.internalfault<='1' when busycnt > 65535 or cycle_fault='1' else '0';
end generate;
nofaultcheck: if not FAULTCHECKS generate
cycle_fault<='0';
muo.internalfault<='0';
end generate;
end behave;
| bsd-3-clause | ab945ae2047457a7d04df064d7e6d873 | 0.539966 | 3.100778 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/hardcopyiii_components.vhd | 1 | 107,742 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyiii_atom_pack.all;
package hardcopyiii_components is
--
-- hardcopyiii_lcell_comb
--
COMPONENT hardcopyiii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "hardcopyiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_routing_wire
--
COMPONENT hardcopyiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_lvds_transmitter
--
COMPONENT hardcopyiii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false"; -- HARDCOPYIII
tx_output_path_delay_engineering_bits : Integer := -1; -- HARDCOPYIII
enable_dpaclk_to_lvdsout : string := "off"; -- HARDCOPYIII
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;-- HARDCOPYIII
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; -- HARDCOPYIII
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';-- HARDCOPYIII
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_ram_block
--
COMPONENT hardcopyiii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "On";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiii_ff
--
COMPONENT hardcopyiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "hardcopyiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_clkselect
--
COMPONENT hardcopyiii_clkselect
generic (
lpm_type : STRING := "hardcopyiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_clkena
--
COMPONENT hardcopyiii_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_hram
--
COMPONENT hardcopyiii_hram
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tipd_ena0 : VitalDelayType01 := DefpropDelay01;
tipd_clk1 : VitalDelayType01 := DefpropDelay01;
tipd_devclrn : VitalDelayType01 := DefpropDelay01;
tipd_clr0 : VitalDelayType01 := DefpropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_portabyteenamasks :VitalDelayArrayType01(1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portadatain :VitalDelayArrayType01(19 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clr1 : VitalDelayType01 := DefpropDelay01;
tipd_devpor : VitalDelayType01 := DefpropDelay01;
tipd_ena1 : VitalDelayType01 := DefpropDelay01;
tipd_ena2 : VitalDelayType01 := DefpropDelay01;
tipd_portaaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr :VitalDelayArrayType01(5 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_ena3 : VitalDelayType01 := DefpropDelay01;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01;
logical_ram_name : STRING := "hram";
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
init_file : STRING := "NONE";
data_width : INTEGER := 20;
address_width : INTEGER := 6;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
port_b_address_clock : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_data_out_clock : STRING := "none";
port_b_data_out_clear : STRING := "none";
lpm_type : STRING := "hardcopyiii_hram";
lpm_hint : STRING := "true";
mem_init0 : BIT_VECTOR := X"0";
mixed_port_feed_through_mode : STRING := "dont_care"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (others => '0');
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiii_io_ibuf
--
COMPONENT hardcopyiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "hardcopyiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_io_obuf
--
COMPONENT hardcopyiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "hardcopyiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_ddio_in
--
COMPONENT hardcopyiii_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "hardcopyiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiii_ddio_oe
--
COMPONENT hardcopyiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "hardcopyiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiii_ddio_out
--
COMPONENT hardcopyiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "hardcopyiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiii_termination
--
COMPONENT hardcopyiii_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "hardcopyiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- hardcopyiii_termination_logic
--
COMPONENT hardcopyiii_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "hardcopyiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- hardcopyiii_dll
--
COMPONENT hardcopyiii_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "hardcopyiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_dll_offset_ctrl
--
COMPONENT hardcopyiii_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "hardcopyiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyiii_dqs_delay_chain
--
COMPONENT hardcopyiii_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
test_enable : string := "false";
test_select : integer := 0;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_dqs_enable
--
COMPONENT hardcopyiii_dqs_enable
GENERIC (
lpm_type : string := "hardcopyiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_dqs_enable_ctrl
--
COMPONENT hardcopyiii_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_delay_chain
--
COMPONENT hardcopyiii_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "hardcopyiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_io_clock_divider
--
COMPONENT hardcopyiii_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_output_phase_alignment
--
COMPONENT hardcopyiii_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "hardcopyiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_input_phase_alignment
--
COMPONENT hardcopyiii_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "hardcopyiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_half_rate_input
--
COMPONENT hardcopyiii_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "hardcopyiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_io_config
--
COMPONENT hardcopyiii_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_dqs_config
--
COMPONENT hardcopyiii_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "hardcopyiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_mac_mult
--
COMPONENT hardcopyiii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiii_mac_out
--
COMPONENT hardcopyiii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "hardcopyiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiii_io_pad
--
COMPONENT hardcopyiii_io_pad
GENERIC (
lpm_type : string := "hardcopyiii_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- hardcopyiii_pll
--
COMPONENT hardcopyiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "HARDCOPYIII";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_asmiblock
--
COMPONENT hardcopyiii_asmiblock
generic (
lpm_type : string := "hardcopyiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- hardcopyiii_lvds_receiver
--
COMPONENT hardcopyiii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyiii_pseudo_diff_out
--
COMPONENT hardcopyiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "hardcopyiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- hardcopyiii_bias_block
--
COMPONENT hardcopyiii_bias_block
GENERIC (
lpm_type : string := "hardcopyiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
--
-- hardcopyiii_tsdblock
--
COMPONENT hardcopyiii_tsdblock
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "hardcopyiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
END COMPONENT;
--
-- hardcopyiii_jtag
--
COMPONENT hardcopyiii_jtag
generic (
lpm_type : string := "hardcopyiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- hardcopyiii_lcell_hsadder
--
COMPONENT hardcopyiii_lcell_hsadder
generic (
dataa_width : integer := 2;
datab_width : integer := 2;
cin_inverted : string := "off";
lpm_type : string := "hardcopyiii_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_datab_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_cin_sumout : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic_vector(dataa_width - 1 downto 0) := (OTHERS => '0');
datab : in std_logic_vector(datab_width - 1 downto 0) := (OTHERS => '0');
cin : in std_logic := '0';
sumout: out std_logic_vector((calc_sum_len(dataa_width, datab_width)) - 2 downto 0);
cout : out std_logic
);
END COMPONENT;
--
-- hardcopyiii_otp
--
COMPONENT hardcopyiii_otp
GENERIC
(
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
TimingChecksOn : Boolean := True;
tipd_otpclken : VitalDelayType01 := DefpropDelay01;
tipd_otpclk : VitalDelayType01 := DefpropDelay01;
tipd_otpshiftnld : VitalDelayType01 := DefpropDelay01;
tpd_otpshiftnld_otpdout : VitalDelayType01 := DefpropDelay01;
tsetup_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_otpshiftnld_otpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
data_width : INTEGER := 128;
init_data : STD_LOGIC_VECTOR(127 DOWNTO 0) := (OTHERS => '0');
init_file : STRING := "init_file.hex";
lpm_type : STRING := "hardcopyiii_otp";
lpm_hint : STRING := "true"
);
PORT
(
otpclken : IN STD_LOGIC := '1';
otpclk : IN STD_LOGIC := '0';
otpshiftnld : IN STD_LOGIC := '0';
otpdout : OUT STD_LOGIC
);
END COMPONENT;
end hardcopyiii_components;
| gpl-3.0 | 5156ac96534ea150a0dc8363d80bfcf9 | 0.47907 | 4.375487 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/maxii_atoms.vhd | 1 | 132,934 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package maxii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE maxii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end maxii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body maxii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end maxii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package maxii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end maxii_pllpack;
package body maxii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end maxii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxii_atom_pack.all;
entity maxii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of maxii_dffe : entity is TRUE;
end maxii_dffe;
-- architecture body --
architecture behave of maxii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- maxii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxii_atom_pack.all;
entity maxii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of maxii_mux21 : entity is TRUE;
end maxii_mux21;
architecture AltVITAL of maxii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- maxii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxii_atom_pack.all;
entity maxii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of maxii_mux41 : entity is TRUE;
end maxii_mux41;
architecture AltVITAL of maxii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- maxii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.maxii_atom_pack.all;
-- entity declaration --
entity maxii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of maxii_and1 : entity is TRUE;
end maxii_and1;
-- architecture body --
architecture AltVITAL of maxii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : maxii_jtag
--
-- Description : MAXII JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.maxii_atom_pack.all;
entity maxii_jtag is
generic (
lpm_type : string := "maxii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end maxii_jtag;
architecture architecture_jtag of maxii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : maxii_crcblock
--
-- Description : MAXII CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.maxii_atom_pack.all;
entity maxii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "maxii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end maxii_crcblock;
architecture architecture_crcblock of maxii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for MAXII Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : maxii_asynch_lcell
--
-- Description : VHDL simulation model for the asynchnous submodule of
-- MAXII Lcell.
--
-- Outputs : Asynchnous LUT function of MAXII Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.maxii_atom_pack.all;
ENTITY maxii_asynch_lcell is
GENERIC (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of maxii_asynch_lcell : ENTITY is TRUE;
END maxii_asynch_lcell;
ARCHITECTURE vital_le of maxii_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd : std_ulogic;
signal datab_ipd : std_ulogic;
signal datac_ipd : std_ulogic;
signal datad_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal cin_ipd : std_ulogic;
signal cin0_ipd : std_ulogic;
signal cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_ulogic;
variable tmp_cout : std_ulogic;
variable tmp_cout0 : std_ulogic;
variable tmp_cout1 : std_ulogic;
variable tmp_regin : std_ulogic;
variable lutb : std_ulogic;
variable cintmp : std_ulogic;
variable invertsig : std_ulogic := '0';
variable cinsel : std_ulogic;
variable cinsig : std_ulogic;
variable cin01sel : std_ulogic;
variable luta : std_ulogic;
variable lutc : std_ulogic;
variable lutd : std_ulogic;
variable datacsig : std_ulogic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or
(inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or
(cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or
(cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or
(cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or
(datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta)
);
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta)
);
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta)
);
tmp_cout := VitalMux2(VitalMux2(tmp_cout1,
tmp_cout0,
cin_ipd),
VitalMux2(tmp_cout1,
tmp_cout0,
inverta_ipd),
mode(3)
);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01
(
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_le;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : maxii_lcell_register
--
-- Description : VHDL simulation model for the register submodule of
-- MAXII Lcell.
--
-- Outputs : Registered output of MAXII Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxii_atom_pack.all;
ENTITY maxii_lcell_register is
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
attribute VITAL_LEVEL0 of maxii_lcell_register : ENTITY is TRUE;
end maxii_lcell_register;
ARCHITECTURE vital_le_reg of maxii_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant maxii_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
( R, x, x, H, x, H, x, x, H, x, H, x, H ), -- Sload
( R, x, x, x, x, H, x, x, H, x, H, x, U ), -- Sload
( R, x, x, x, L, H, x, x, x, H, x, x, L ), -- Cascade
( R, x, x, x, H, H, x, x, x, H, x, x, H ), -- Cascade
( R, x, x, x, x, H, x, x, x, H, x, x, U ), -- Cascade
( R, x, L, x, x, H, x, x, x, x, H, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, H, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, H, x, U ), -- Datain
( R, x, L, x, x, H, x, x, x, x, x, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, x, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, x, x, U ), -- Datain
( x, x, x, x, x, x, x, x, x, x, x, x, S )); -- Q=Q
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
regcascin_ipd, datain, sclr_ipd, ena_ipd,
sload_ipd, cena, xonv, smode)
variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;
-- variables for 'X' generation
variable Tviolation : std_ulogic := '0';
variable tmp_regout : STD_ULOGIC := '0';
variable PreviousData : STD_LOGIC_VECTOR(0 to 10);
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_regcascin_clk,
TimingData => TimingData_regcascin_clk,
TestSignal => regcascin_ipd,
TestSignalName => "REGCASCIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_regcascin_clk_noedge_posedge,
SetupLow => tsetup_regcascin_clk_noedge_posedge,
HoldHigh => thold_regcascin_clk_noedge_posedge,
HoldLow => thold_regcascin_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr_ipd) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
end if;
-------------------------
-- Functionality Section
-------------------------
Tviolation := Tviol_regcascin_clk or Tviol_datain_clk or
Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk;
VitalStateTable (
Result => tmp_regout,
PreviousDataIn => PreviousData,
StateTable => maxii_regtab,
DataIn => (CLK_ipd, ACLR_ipd, datain, datac_ipd,
regcascin_ipd, ENA_ipd, aload_ipd, sclr_ipd,
sload_ipd, cena, smode)
);
tmp_regout := (xonv AND Tviolation) XOR tmp_regout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbkout,
OutSignalName => "QFBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbkout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_qfbkout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_qfbkout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_qfbkout_posedge, TRUE)),
GlitchData => qfbkout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : maxii_lcell
--
-- Description : VHDL simulation model for MAXII Lcell.
--
-- Outputs : Output of MAXII Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxii_atom_pack.all;
use work.maxii_asynch_lcell;
use work.maxii_lcell_register;
ENTITY maxii_lcell is
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "maxii_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end maxii_lcell;
ARCHITECTURE vital_le_atom of maxii_lcell is
signal dffin : std_logic;
signal qfbkin : std_logic;
signal mode : std_logic_vector(5 downto 0);
COMPONENT maxii_asynch_lcell
GENERIC (
lms : std_logic_vector(15 downto 0);
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01
);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end COMPONENT;
COMPONENT maxii_lcell_register
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (
clk :in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
end COMPONENT;
signal aclr1, xonv, cena, smode : std_logic ;
begin
aclr1 <= aclr or (not devclrn) or (not devpor);
cena <= '1' when (register_cascade_mode = "on") else '0';
xonv <= '1' when (x_on_violation = "on") else '0';
smode <= '1' when (synch_mode = "on") else '0';
mode(0) <= '1' when operation_mode = "normal" else
'0'; -- operation_mode = "arithmetic"
mode(1) <= '1' when sum_lutc_input = "datac" else
'0' ; -- sum_lutc_input = "cin"
mode(2) <= '1' when sum_lutc_input = "qfbk" else
'0'; -- sum_lutc_input = "cin" or "datac"
mode(3) <= '1' when cin_used = "true" else
'0'; -- cin_used = "false"
mode(4) <= '1' when cin0_used = "true" else
'0'; -- cin0_used = "false"
mode(5) <= '1' when cin1_used = "true" else
'0'; -- cin1_used = "false"
lecomb: maxii_asynch_lcell
GENERIC map (
lms => str_to_bin(lut_mask)
)
PORT map (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
qfbkin => qfbkin,
inverta => map_x_to_0(inverta),
cin => cin,
cin0 => cin0,
cin1 => cin1,
mode => mode,
combout => combout,
cout => cout,
cout0 => cout0,
cout1 => cout1,
regin => dffin
);
lereg: maxii_lcell_register
PORT map (
clk => clk,
datain => dffin,
datac => datac,
smode => smode,
regcascin => regcascin,
aclr => aclr1,
aload => aload,
sclr => sclr,
sload => sload,
ena => ena,
cena => cena,
xonv => xonv,
regout => regout,
qfbkout => qfbkin
);
end vital_le_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- MAXII UFM ATOM
--
--
--/////////////////////////////////////////////////////////////////////////////
-- MODULE DECLARATION
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use std.textio.all;
use work.maxii_atom_pack.all;
entity maxii_ufm is
generic (
-- PARAMETER DECLARATION
address_width : integer := 9;
init_file : string := "none";
lpm_type : string := "maxii_ufm";
mem1 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem2 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem3 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem4 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem5 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem6 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem7 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem8 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem9 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem10 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem11 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem12 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem13 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem14 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem15 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
mem16 : std_logic_vector(511 downto 0) := (OTHERS=>'1');
osc_sim_setting : integer := 180000; -- default osc frequency to 5.56MHz
program_time : integer := 1600000; -- default program_time is 1600ns
erase_time : integer := 500000000; -- default erase time is 500us
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_program_busy_posedge: VitalDelayType01 := DefPropDelay01;
tpd_erase_busy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_drclk_drdout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_oscena_osc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_sbdin_sbdout : VitalDelayType01 := DefPropDelay01;
tsetup_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
tsetup_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_program_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_oscena_erase_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_arshft_arclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_ardin_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_drshft_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_drdin_drclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_program_drclk_noedge_posedge: VitalDelayType := DefSetupHoldCnst;
thold_erase_arclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_program_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_oscena_erase_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_program_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_erase_busy_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tipd_program : VitalDelayType01 := DefPropDelay01;
tipd_erase : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01;
tipd_arclk : VitalDelayType01 := DefPropDelay01;
tipd_arshft : VitalDelayType01 := DefPropDelay01;
tipd_ardin : VitalDelayType01 := DefPropDelay01;
tipd_drclk : VitalDelayType01 := DefPropDelay01;
tipd_drshft : VitalDelayType01 := DefPropDelay01;
tipd_drdin : VitalDelayType01 := DefPropDelay01;
tipd_sbdin : VitalDelayType01 := DefPropDelay01
);
port (
program : in std_logic := '0';
erase : in std_logic := '0';
oscena : in std_logic;
arclk : in std_logic;
arshft : in std_logic;
ardin : in std_logic;
drclk : in std_logic;
drshft : in std_logic;
drdin : in std_logic := '0';
sbdin : in std_logic := '0';
devclrn : in std_logic := '1'; -- simulation only port
devpor : in std_logic := '1'; -- simulation only port
ctrl_bgpbusy : in std_logic := '0'; -- simulation only port, to control
-- and emulate the output
-- behaviour of bgpbusy
busy : out std_logic;
osc : out std_logic := 'X';
drdout : out std_logic;
sbdout : out std_logic;
bgpbusy : out std_logic);
END maxii_ufm;
architecture behave of maxii_ufm is
-- CONSTANT DECLARATION
constant WIDTHDATA : integer := 16;
constant SECTOR0_RANGE : integer := (2**(address_width-1));
constant SECTOR_SIZE : integer := (WIDTHDATA * (2**(address_width-1)));
-- TYPE DECLARATION
type ufm_memory is array ((2**address_width)-1 downto 0) of std_logic_vector(WIDTHDATA-1 downto 0);
-- SIGNAL DECLARATION
signal addr_reg : std_logic_vector(address_width - 1 downto 0) := (OTHERS => '0');
signal data_reg : std_logic_vector((WIDTHDATA - 1) downto 0) := (OTHERS => 'X');
signal storage_output : std_logic_vector((WIDTHDATA - 1) downto 0) := (OTHERS => '1');
signal int_osc : std_logic := 'X';
signal program_pulse : std_logic := '0';
signal erase_pulse : std_logic := '0';
signal sys_busy : std_logic;
signal i : integer;
signal j : integer;
signal numwords : integer;
signal program_ipd : std_logic;
signal erase_ipd : std_logic;
signal oscena_ipd : std_logic;
signal arclk_ipd : std_logic;
signal arshft_ipd : std_logic;
signal ardin_ipd : std_logic;
signal drclk_ipd : std_logic;
signal drshft_ipd : std_logic;
signal drdin_ipd : std_logic;
signal sbdin_ipd : std_logic;
signal program_reg : std_logic;
signal erase_reg : std_logic;
signal busy_tmp : std_logic;
-- FUNCTION DECLARATION
-- convert std_logic_vector to integer
function convert_to_int(arg : in std_logic_vector) return integer is
variable result : integer := 0;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end convert_to_int;
begin
bgpbusy <= ctrl_bgpbusy; -- No delay necessary as for simulation only
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (program_ipd, program, tipd_program);
VitalWireDelay (erase_ipd, erase, tipd_erase);
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
VitalWireDelay (arclk_ipd, arclk, tipd_arclk);
VitalWireDelay (arshft_ipd, arshft, tipd_arshft);
VitalWireDelay (ardin_ipd, ardin, tipd_ardin);
VitalWireDelay (drclk_ipd, drclk, tipd_drclk);
VitalWireDelay (drshft_ipd, drshft, tipd_drshft);
VitalWireDelay (drdin_ipd, drdin, tipd_drdin);
VitalWireDelay (sbdin_ipd, sbdin, tipd_sbdin);
end block;
VITAL_sbdin : process (sbdin_ipd)
variable sbdout_tmp : std_logic;
variable sbdout_VitalGlitchData : VitalGlitchDataType;
begin
sbdout <= sbdin_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => sbdout,
OutSignalName => "SBDOUT",
OutTemp => sbdout_tmp,
Paths => (0 => (sbdin_ipd'last_event, tpd_sbdin_sbdout, TRUE)),
GlitchData => sbdout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Produce oscillation clock to UFM
VITAL_oscena : process (oscena_ipd, int_osc)
variable osc_VitalGlitchData : VitalGlitchDataType;
variable first_warning : boolean := true;
variable TOSCMN_PW : time := 90000 ps; --pulse width of osc - default to 1/2 of osc period
variable need_init : boolean := true;
begin
if (need_init = true) then
if (osc_sim_setting /= 0) then
TOSCMN_PW := (osc_sim_setting / 2) * 1 ps;
need_init := false;
end if;
end if;
if (oscena_ipd = '1') then
if (first_warning = true) then
assert FALSE
report "UFM oscillator can operate at any frequency between 3.33MHz to 5.56Mhz."
severity NOTE;
first_warning := false;
end if;
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after TOSCMN_PW;
else
int_osc <= '0' after TOSCMN_PW;
end if;
else
int_osc <= '1' after TOSCMN_PW;
end if;
VitalPathDelay01 (
OutSignal => osc,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_osc_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Shift address from LSB to MSB when arshft is '1'; else increment address.
-- (Using block statement to avoid race condition warning; therefore, the
-- order of assignments must be taken care to ensure correct behaviour)
VITAL_arclk : process (arclk_ipd, arshft_ipd, ardin_ipd, sys_busy, devclrn, devpor)
variable addr_reg_var : std_logic_vector(address_width-1 downto 0) := (OTHERS => '0');
variable Tviol_arshft_arclk : std_ulogic := '0';
variable Tviol_ardin_arclk : std_ulogic := '0';
variable TimingData_arshft_arclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ardin_arclk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- setup and hold time verification on ARSHFT
VitalSetupHoldCheck (
Violation => Tviol_arshft_arclk,
TimingData => TimingData_arshft_arclk,
TestSignal => arshft_ipd,
TestSignalName => "arshft",
RefSignal => arclk_ipd,
RefSignalName => "arclk",
SetupHigh => tsetup_arshft_arclk_noedge_posedge,
SetupLow => tsetup_arshft_arclk_noedge_posedge,
HoldHigh => thold_arshft_arclk_noedge_posedge,
HoldLow => thold_arshft_arclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Arshft VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setup and hold time verification on ARDIN
VitalSetupHoldCheck (
Violation => Tviol_ardin_arclk,
TimingData => TimingData_ardin_arclk,
TestSignal => ardin_ipd,
TestSignalName => "ardin",
RefSignal => arclk_ipd,
RefSignalName => "arclk",
SetupHigh => tsetup_ardin_arclk_noedge_posedge,
SetupLow => tsetup_ardin_arclk_noedge_posedge,
HoldHigh => thold_ardin_arclk_noedge_posedge,
HoldLow => thold_ardin_arclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Ardin VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
-- The behaviour of ARSHFT and ARDIN
if ((devpor = '0') or (devclrn = '0')) then
addr_reg_var := (OTHERS => '0');
elsif (arclk_ipd'event and arclk_ipd = '1' and sys_busy = '0') then
if (address_width /= 9) then
assert false
report "address_width parameter must be equal to 9."
severity error;
end if;
if (arshft_ipd = '1') then
for i in address_width-1 downto 1 loop
addr_reg_var(i) := addr_reg(i-1);
end loop;
addr_reg_var(0) := ardin_ipd;
else
addr_reg_var := addr_reg_var + '1';
end if;
end if;
addr_reg <= addr_reg_var;
end process;
-- Shift data from LSB to MSB when drshft is '1'; else load new data.
VITAL_drclk : process (drclk_ipd, drshft_ipd, drdin_ipd, sys_busy, devclrn, devpor)
variable drdout_tmp : std_logic;
variable data_reg_var : std_logic_vector((WIDTHDATA - 1) downto 0) := (OTHERS => 'X');
variable Tviol_drshft_drclk : std_ulogic := '0';
variable Tviol_drdin_drclk : std_ulogic := '0';
variable TimingData_drshft_drclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_drdin_drclk : VitalTimingDataType := VitalTimingDataInit;
variable drdout_VitalGlitchData : VitalGlitchDataType;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- setup and hold time verification on DRSHFT
VitalSetupHoldCheck (
Violation => Tviol_drshft_drclk,
TimingData => TimingData_drshft_drclk,
TestSignal => drshft_ipd,
TestSignalName => "drshft",
RefSignal => drclk_ipd,
RefSignalName => "drclk",
SetupHigh => tsetup_drshft_drclk_noedge_posedge,
SetupLow => tsetup_drshft_drclk_noedge_posedge,
HoldHigh => thold_drshft_drclk_noedge_posedge,
HoldLow => thold_drshft_drclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Drshft VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setup and hold time verification on DRDIN
VitalSetupHoldCheck (
Violation => Tviol_drdin_drclk,
TimingData => TimingData_drdin_drclk,
TestSignal => drdin_ipd,
TestSignalName => "drdin",
RefSignal => drclk_ipd,
RefSignalName => "drclk",
SetupHigh => tsetup_drdin_drclk_noedge_posedge,
SetupLow => tsetup_drdin_drclk_noedge_posedge,
HoldHigh => thold_drdin_drclk_noedge_posedge,
HoldLow => thold_drdin_drclk_noedge_posedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM Drdin VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
-- The behaviour of DRSHFT and DRDIN
if ((devpor = '0') or (devclrn = '0')) then
data_reg_var := (OTHERS => '0');
elsif (drclk_ipd'EVENT AND drclk_ipd = '1' and sys_busy = '0') then
if (drshft_ipd = '1') then
for j in WIDTHDATA-1 downto 1 loop
data_reg_var(j) := data_reg(j - 1);
end loop;
data_reg_var(0) := drdin_ipd;
else
data_reg_var := storage_output;
end if;
end if;
data_reg <= data_reg_var;
drdout_tmp := data_reg_var((WIDTHDATA - 1));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => drdout,
OutSignalName => "drdout",
OutTemp => drdout_tmp,
Paths => (0 => (InputChangeTime => drclk_ipd'last_event,
PathDelay => tpd_drclk_drdout_posedge,
PathCondition => (drclk_ipd = '1'))),
GlitchData => drdout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
REG_PROG_ERASE : process (int_osc)
begin
if(int_osc'event and int_osc = '1') then
program_reg <= program_ipd;
erase_reg <= erase_ipd;
end if;
end process;
VITAL_program_erase : process (program_ipd, erase_ipd, program_reg, erase_reg, drclk_ipd, arclk_ipd, oscena_ipd)
variable Tviol_erase_arclk : std_ulogic := '0';
variable Tviol_program_drclk : std_ulogic := '0';
variable Tviol_oscena_program : std_ulogic := '0';
variable Tviol_oscena_erase : std_ulogic := '0';
variable TimingData_erase_arclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_program_drclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_oscena_erase : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_oscena_program : VitalTimingDataType := VitalTimingDataInit;
variable TPPMX : time := 1600000 ps;
variable TEPMX : time := 500000000 ps;
variable need_init: boolean := true;
begin
if (need_init = true) then
if (program_time /= 0) then
TPPMX := (program_time * 1 ps);
end if;
if (erase_time /= 0) then
TEPMX := (erase_time/1000) * 1 ps;
end if;
need_init := false;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- hold time verification on DRCLK
VitalSetupHoldCheck (
Violation => Tviol_program_drclk,
TimingData => TimingData_program_drclk,
TestSignal => program_ipd,
TestSignalName => "program",
RefSignal => drclk_ipd,
RefSignalName => "drclk",
HoldHigh => thold_program_drclk_noedge_posedge,
HoldLow => thold_program_drclk_noedge_posedge,
RefTransition => '/',
HeaderMsg => "/UFM Program to Drclk VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- hold time verification on ARCLK
VitalSetupHoldCheck (
Violation => Tviol_erase_arclk,
TimingData => TimingData_erase_arclk,
TestSignal => erase_ipd,
TestSignalName => "erase",
RefSignal => arclk_ipd,
RefSignalName => "arclk",
HoldHigh => thold_erase_arclk_noedge_posedge,
HoldLow => thold_erase_arclk_noedge_posedge,
RefTransition => '/',
HeaderMsg => "/UFM Erase to Arclk VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setuphold check for oscena vs program
VitalSetupHoldCheck (
Violation => Tviol_oscena_program,
TimingData => TimingData_oscena_program,
TestSignal => oscena_ipd,
TestSignalName => "oscena",
RefSignal => program_ipd,
RefSignalName => "program",
SetupHigh => tsetup_oscena_program_noedge_posedge,
SetupLow => tsetup_oscena_program_noedge_posedge,
HoldHigh => thold_oscena_program_noedge_negedge,
HoldLow => thold_oscena_program_noedge_negedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM OSCENA to PROGRAM VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- setuphold check for oscena vs erase
VitalSetupHoldCheck (
Violation => Tviol_oscena_erase,
TimingData => TimingData_oscena_erase,
TestSignal => oscena_ipd,
TestSignalName => "oscena",
RefSignal => erase_ipd,
RefSignalName => "erase",
SetupHigh => tsetup_oscena_erase_noedge_posedge,
SetupLow => tsetup_oscena_erase_noedge_posedge,
HoldHigh => thold_oscena_erase_noedge_negedge,
HoldLow => thold_oscena_erase_noedge_negedge,
CheckEnabled => TO_X01(devpor AND devclrn) /= '0',
RefTransition => '/',
HeaderMsg => "/UFM OSCENA to ERASE VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
-- Pulse to indicate programming UFM for maxinum time of
-- TPPMX
if (program_reg'event and program_reg = '1') then
if (sys_busy = '0' and program_pulse = '0') then
program_pulse <= '1';
program_pulse <= transport '0' after TPPMX;
end if;
elsif (erase_reg'event and erase_reg = '1') then
-- Pulse to indicate erasing UFM for maxinum time of
-- TEPMX
if (sys_busy = '0' and erase_pulse = '0') then
erase_pulse <= '1';
erase_pulse <= transport '0' after (TEPMX * 1000);
end if;
end if;
end process;
-- Insert timing delay for Erase and Program to Busy
VITAL_pulse : process(program_pulse, erase_pulse, program_ipd, erase_ipd, busy_tmp)
variable Tviol_program_busy : std_ulogic := '0';
variable Tviol_erase_busy : std_ulogic := '0';
variable TimingData_program_busy : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_erase_busy : VitalTimingDataType := VitalTimingDataInit;
variable busy_VitalGlitchData : VitalGlitchDataType;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
-- hold time verification on PROGRAM from BUSY's falling edge
VitalSetupHoldCheck (
Violation => Tviol_program_busy,
TimingData => TimingData_program_busy,
TestSignal => program_ipd,
TestSignalName => "program",
RefSignal => busy_tmp,
RefSignalName => "busy",
HoldHigh => thold_program_busy_noedge_negedge,
HoldLow => thold_program_busy_noedge_negedge,
RefTransition => '/',
HeaderMsg => "/UFM Busy to Program VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
-- hold time verification on ERASE from BUSY's falling edge
VitalSetupHoldCheck (
Violation => Tviol_erase_busy,
TimingData => TimingData_erase_busy,
TestSignal => erase_ipd,
TestSignalName => "erase",
RefSignal => busy_tmp,
RefSignalName => "busy",
HoldHigh => thold_erase_busy_noedge_negedge,
HoldLow => thold_erase_busy_noedge_negedge,
RefTransition => '/',
HeaderMsg => "/UFM Busy to Erase VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
sys_busy <= busy_tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => busy,
OutSignalName => "busy",
OutTemp => busy_tmp,
Paths => (0 => (InputChangeTime => erase_ipd'last_event,
PathDelay => tpd_erase_busy_posedge,
PathCondition => (erase_pulse = '1')),
1 => (InputChangeTime => program_ipd'last_event,
PathDelay => tpd_program_busy_posedge,
PathCondition => (program_pulse = '1'))),
GlitchData => busy_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
VITAL_busy : process(program_pulse, erase_pulse)
begin
busy_tmp <= program_pulse or erase_pulse;
end process;
-- MEMORY PROCESSING BLOCK
MEMORY: process(program_pulse, erase_pulse, addr_reg)
variable ufm_storage : ufm_memory; -- UFM sector0 and sector1
variable ufm_initf_sec0 : std_logic_vector((SECTOR_SIZE-1) downto 0) := (OTHERS=>'1');
variable ufm_initf_sec1 : std_logic_vector((SECTOR_SIZE-1) downto 0) := (OTHERS=>'1');
variable init_word0 : std_logic_vector ((WIDTHDATA - 1) downto 0);
variable init_word1 : std_logic_vector ((WIDTHDATA - 1) downto 0);
variable storage_init : boolean := false;
variable i : integer := 0;
variable k : integer := 0;
variable mem_cnt : integer := 0;
variable bit_cnt : integer := 0;
begin
-- INITIALIZE --
if NOT(storage_init) then
-- INITIALIZE TO 1; UFM content is initially all 1's
for i in ufm_storage'low to ufm_storage'high loop
ufm_storage(i) := (OTHERS => '1');
end loop;
if (init_file = "none") then
assert FALSE
report "Not using any memory initialization file."
severity WARNING;
else
-- initialize UFM from memory initialization file (*.mif or *.hex)
-- the contents of the memory initialization file are passed in via the
-- mem* parameters
ufm_initf_sec0(SECTOR_SIZE-1 downto 0) := (mem8 & mem7 & mem6 & mem5 &
mem4 & mem3 & mem2 & mem1);
ufm_initf_sec1(SECTOR_SIZE-1 downto 0) := (mem16 & mem15 & mem14 & mem13 &
mem12 & mem11 & mem10 & mem9);
for mem_cnt in 1 to SECTOR0_RANGE loop
for bit_cnt in 0 to (WIDTHDATA-1) loop
init_word0(bit_cnt) := ufm_initf_sec0(((mem_cnt-1)*WIDTHDATA) + bit_cnt);
init_word1(bit_cnt) := ufm_initf_sec1(((mem_cnt-1)*WIDTHDATA) + bit_cnt);
end loop;
ufm_storage(mem_cnt-1) := init_word0;
ufm_storage((mem_cnt-1) + SECTOR0_RANGE) := init_word1;
end loop;
end if;
storage_init := TRUE;
end if; -- if NOT(storage_init)
-- MEMORY FUNCTION --
-- Programming data into the UFM
if (program_pulse'EVENT and program_pulse = '1') then
ufm_storage(convert_to_int(addr_reg)) := data_reg and
ufm_storage(convert_to_int(addr_reg));
elsif (erase_pulse'EVENT and erase_pulse = '1') then
-- Erasing data from selected sector of UFM
if (addr_reg(address_width - 1) = '0') then
for k in 0 to (SECTOR0_RANGE - 1) loop
ufm_storage(k) := (others => '1');
end loop;
else
for k in SECTOR0_RANGE to (SECTOR0_RANGE * 2 - 1) loop
ufm_storage(k) := (others => '1');
end loop;
end if;
end if;
storage_output <= ufm_storage(convert_to_int(addr_reg)) ;
end process; -- memory
END behave;
--
--
-- MAXII_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxii_atom_pack.all;
entity maxii_io is
generic(
lpm_type : STRING := "maxii_io";
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01
);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
padio : inout STD_LOGIC;
combout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of maxii_io : entity is TRUE;
end maxii_io;
architecture behave of maxii_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal oe_ipd : std_logic;
signal padio_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_logic;
variable tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
begin
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --for autotest
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
---------------------------------------------------------------------
--
-- Entity Name : maxii_routing_wire
--
-- Description : StratixII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.maxii_atom_pack.all;
ENTITY maxii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of maxii_routing_wire : entity is TRUE;
end maxii_routing_wire;
ARCHITECTURE behave of maxii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| gpl-3.0 | 61e742211952ab891b5a92009c89b98b | 0.500715 | 4.087761 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci32lite/pcipargen.vhd | 1 | 5,424 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pcipargen.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: PCI Parity Generator. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pcipargen is
port (
clk_i : in std_logic;
pcidatout_i : in std_logic_vector(31 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
par_o : out std_logic
);
end pcipargen;
architecture rtl of pcipargen is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal d : std_logic_vector(31 downto 0);
signal pardat : std_logic;
signal parcbe : std_logic;
signal par : std_logic;
begin
d <= pcidatout_i;
--+-------------------------------------------------------------------------+
--| building parity |
--+-------------------------------------------------------------------------+
pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor
d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor
d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor
d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);
parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3);
par <= pardat xor parcbe;
u1: entity work.sync port map ( clk => clk_i, d => par, q => par_o );
end rtl;
| gpl-3.0 | 644167bd55eda2945d7a40023061938c | 0.26899 | 6.14966 | false | false | false | false |
freecores/t400 | bench/vhdl/t410_rom-lpm-a.vhd | 1 | 3,518 | -------------------------------------------------------------------------------
--
-- T410 ROM wrapper for lpm_rom.
--
-- $Id: t410_rom-lpm-a.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
architecture lpm of t410_rom is
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string;
LPM_TYPE : string := "LPM_ROM";
LPM_HINT : string := "UNUSED"
);
port (
ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
Q : out STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0)
);
end component;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_WIDTHAD => 9,
LPM_OUTDATA => "UNREGISTERED",
LPM_FILE => "rom_41x.hex"
)
port map (
ADDRESS => addr_i,
INCLOCK => ck_i,
OUTCLOCK => ck_i,
MEMENAB => vdd_s,
Q => data_o
);
end lpm;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | 8d00b4f221f03ff9521ecd2b2adb5ec7 | 0.581865 | 4.370186 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci32lite/pcidmux.vhd | 1 | 13,265 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pcidmux.vhd |
--| |
--| Project: pci32tLite |
--| |
--| Description: Data Multiplex wb <-> regs <-> pci |
--| Data Multiplex D16 whisbone <-> D32 PCI. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pcidmux is
generic (
BARS : string := "1BARMEM";
WBSIZE : integer := 16;
WBENDIAN : string := "BIG"
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
--
d_in : in std_logic_vector(31 downto 0);
d_out : out std_logic_vector(31 downto 0);
--
wbdatLD_i : in std_logic;
rdcfg_i : in std_logic;
cbe_i : in std_logic_vector(3 downto 0);
--
wb_dat_i : in std_logic_vector((WBSIZE-1) downto 0);
wb_dat_o : out std_logic_vector((WBSIZE-1) downto 0);
rg_dat_i : in std_logic_vector(31 downto 0);
rg_dat_o : out std_logic_vector(31 downto 0)
);
end pcidmux;
architecture rtl of pcidmux is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal pcidatin : std_logic_vector(31 downto 0);
signal pcidatout : std_logic_vector(31 downto 0);
signal wb_dat_is : std_logic_vector((WBSIZE-1) downto 0);
signal wbrgdMX : std_logic;
signal wbdMX : std_logic_vector(1 downto 0);
begin
-- Mux control signals
wbrgdMX <= not rdcfg_i;
wbdMX(0) <= '0' when ( cbe_i(0) = '0' or cbe_i(2) = '0' ) else '1';
wbdMX(1) <= '0' when ( cbe_i(0) = '0' or cbe_i(1) = '0' ) else '1';
--+-------------------------------------------------------------------------+
--| Load Whisbone Datain |
--+-------------------------------------------------------------------------+
WBDATLD: process( rst_i, clk_i, wbdatLD_i, wb_dat_i )
begin
if( rst_i = '1' ) then
wb_dat_is <= ( others => '1' );
elsif( rising_edge(clk_i) ) then
if ( wbdatLD_i = '1' ) then
wb_dat_is <= wb_dat_i;
end if;
end if;
end process WBDATLD;
--+-------------------------------------------------------------------------+
--| Route PCI data in toward Registers and Whisbone |
--+-------------------------------------------------------------------------+
rg_dat_o <= pcidatin;
--+-------------------------------------------------------------------------+
--| PCI <-> WB Data route and swap |
--+-------------------------------------------------------------------------+
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Little endian)|
--| WB bus 32Bits |
--+-----------------------------------------+
dat32: if (WBSIZE = 32 and WBENDIAN = "LITTLE") generate
pcidatout(31 downto 0) <= wb_dat_is(31 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 0);
wb_dat_o(31 downto 0) <= pcidatin(31 downto 0);
end generate;
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Big endian) |
--| WB bus 16Bits |
--+-----------------------------------------+
dat16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
--pcidatout(31 downto 24) <= wb_dat_is(7 downto 0) when ( wbrgdMX_i = '1' ) else rg_dat_i(31 downto 24);
--pcidatout(23 downto 16) <= wb_dat_is(15 downto 8) when ( wbrgdMX_i = '1' ) else rg_dat_i(23 downto 16);
--pcidatout(15 downto 8) <= wb_dat_is(7 downto 0) when ( wbrgdMX_i = '1' ) else rg_dat_i(15 downto 8);
--pcidatout(7 downto 0) <= wb_dat_is(15 downto 8) when ( wbrgdMX_i = '1' ) else rg_dat_i(7 downto 0);
--wb_dat_o(15 downto 8) <= pcidatin(23 downto 16) when ( wbdMX_i(1) = '1' ) else pcidatin(7 downto 0);
--wb_dat_o(7 downto 0) <= pcidatin(31 downto 24) when ( wbdMX_i(1) = '1' ) else pcidatin(15 downto 8);
PCIWBMUX: process(cbe_i, pcidatin, wbrgdMX, wb_dat_is, rg_dat_i)
begin
case cbe_i is
when b"1100" =>
wb_dat_o(7 downto 0) <= pcidatin(7 downto 0);
wb_dat_o(15 downto 8) <= pcidatin(15 downto 8);
when b"0011" =>
wb_dat_o(7 downto 0) <= pcidatin(23 downto 16);
wb_dat_o(15 downto 8) <= pcidatin(31 downto 24);
when b"1110" =>
wb_dat_o(7 downto 0) <= (others => '1');
wb_dat_o(15 downto 8) <= pcidatin(7 downto 0);
when b"1101" =>
wb_dat_o(7 downto 0) <= pcidatin(15 downto 8);
wb_dat_o(15 downto 8) <= (others => '1');
when b"1011" =>
wb_dat_o(7 downto 0) <= (others => '1');
wb_dat_o(15 downto 8) <= pcidatin(23 downto 16);
when b"0111" =>
wb_dat_o(7 downto 0) <= pcidatin(31 downto 24);
wb_dat_o(15 downto 8) <= (others => '1');
when others =>
wb_dat_o(15 downto 0) <= pcidatin(15 downto 0);
end case;
if (wbrgdMX = '1') then
case cbe_i is
when b"1100" =>
pcidatout(31 downto 16) <= (others => '1');
pcidatout(15 downto 0) <= wb_dat_is(15 downto 0);
when b"0011" =>
pcidatout(31 downto 16) <= wb_dat_is(15 downto 0);
pcidatout(15 downto 0) <= (others => '1');
when b"1110" =>
pcidatout(31 downto 8) <= (others => '1');
pcidatout(7 downto 0) <= wb_dat_is(15 downto 8);
when b"1101" =>
pcidatout(31 downto 16) <= (others => '1');
pcidatout(15 downto 8) <= wb_dat_is(7 downto 0);
pcidatout(7 downto 0) <= (others => '1');
when b"1011" =>
pcidatout(31 downto 24) <= (others => '1');
pcidatout(23 downto 16) <= wb_dat_is(15 downto 8);
pcidatout(15 downto 0) <= (others => '1');
when b"0111" =>
pcidatout(31 downto 24) <= wb_dat_is(7 downto 0);
pcidatout(23 downto 0) <= (others => '1');
when others =>
pcidatout(15 downto 0) <= wb_dat_is(15 downto 0);
pcidatout(31 downto 16) <= (others => '1');
end case;
else
pcidatout(31 downto 0) <= rg_dat_i(31 downto 0);
end if;
end process PCIWBMUX;
end generate;
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Little endian)|
--| WB bus 16Bits |
--+-----------------------------------------+
dat16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
pcidatout(31 downto 16) <= wb_dat_is when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 16);
pcidatout(15 downto 0) <= wb_dat_is when ( wbrgdMX = '1' ) else rg_dat_i(15 downto 0);
wb_dat_o(15 downto 0) <= pcidatin(31 downto 16) when ( wbdMX(1) = '1' ) else pcidatin(15 downto 0);
end generate;
--+-----------------------------------------+
--| PCI(Little endian) <-> WB(Little endian)|
--| WB bus 8Bits |
--+-----------------------------------------+
dat8l: if (WBSIZE = 8 and WBENDIAN = "LITTLE") generate
--pcidatout(31 downto 24) <= wb_dat_is(7 downto 0);
--pcidatout(23 downto 16) <= wb_dat_is(7 downto 0);
--pcidatout(15 downto 8) <= wb_dat_is(7 downto 0);
--pcidatout(7 downto 0) <= wb_dat_is(7 downto 0);
pcidatout(31 downto 24) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 24);
pcidatout(23 downto 16) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(23 downto 16);
pcidatout(15 downto 8) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(15 downto 8);
pcidatout(7 downto 0) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(7 downto 0);
with wbdMX select
wb_dat_o(7 downto 0) <= pcidatin(7 downto 0) when "00",
pcidatin(15 downto 8) when "01",
pcidatin(23 downto 16) when "10",
pcidatin(31 downto 24) when "11",
(others => '0') when others;
end generate;
--+-------------------------------------------------------------------------+
--| PCI data in/out
--+-------------------------------------------------------------------------+
pcidatin <= d_in;
d_out <= pcidatout;
end rtl;
| gpl-3.0 | 7c0fd0aea6f485ea58ee9ffe75512a5e | 0.344591 | 4.634871 | false | false | false | false |
shvorin/pcie-emu | hdllib/common/util.vhd | 1 | 13,658 | -- Copyright (c) 2011-2014, Ailamazyan Program Systems Institute (Russian
-- Academy of Science). See COPYING in top-level directory.
-- This package contains common types and functions; not router-specific stuff.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc;
use work.types.all;
package util is
function maximum(constant t1, t2 : natural) return natural;
function maximum(constant a : integer_array) return integer;
function minimum(constant t1, t2 : natural) return natural;
function minimum(constant t1, t2 : std_logic_vector) return std_logic_vector;
function minimum(constant a : integer_array) return integer;
-- nearly the same as UNSIGNED_NUM_BITS from ieee.numeric_bit
-- NB: UNSIGNED_NUM_BITS seem to be incorrect ;)
function ceil_log2 (constant x : positive) return natural;
function nor_reduce(v : std_logic_vector) return std_logic;
function or_reduce(v : std_logic_vector) return std_logic;
function and_reduce(v : std_logic_vector) return std_logic;
function nand_reduce(v : std_logic_vector) return std_logic;
function nor_reduce(v : std_logic_vector) return boolean;
function or_reduce(v : std_logic_vector) return boolean;
function and_reduce(v : std_logic_vector) return boolean;
function nand_reduce(v : std_logic_vector) return boolean;
-- "unary logarithm": finds the highest set bit and drops all other bits;
-- if argument is zero the result is also zero
function unary_log (constant v : std_logic_vector) return std_logic_vector;
function "and" (constant arg : std_logic_vector; constant s : std_logic)
return std_logic_vector;
-- encodes bit range into binary representation (i.e. returns the number of
-- (the only) lit bit, otherwise result is meaningless). FIXME: why to
-- (re-)implement a simple library function?!
function encode (constant arg : std_logic_vector) return natural;
function to_stdl (constant v : in boolean) return std_logic;
-- drop all bits except the lowest fired
function lowest_fired (arg : std_logic_vector) return std_logic_vector;
function invert(arg : std_logic_vector) return std_logic_vector;
function singleton(arg : std_logic) return std_logic_vector;
function align2_down(v : std_logic_vector) return std_logic_vector;
function align8_down(v : std_logic_vector) return std_logic_vector;
function align8_up(v : std_logic_vector) return std_logic_vector;
-- treat segment descriptor
function desc2mask(x : std_logic_vector) return std_logic_vector;
function desc2base(x : std_logic_vector) return std_logic_vector;
--
-- optimized version; hint_logsize must be guaranteed to be no greater than
-- actual logsize
function desc2mask(x : std_logic_vector; hint_logsize : natural; exact : boolean := false) return std_logic_vector;
function desc2base(x : std_logic_vector; hint_logsize : natural; exact : boolean := false) return std_logic_vector;
function extend64(v : std_logic_vector) return qword;
function extend64(i : integer) return qword;
function extend(size : natural; v : std_logic_vector) return std_logic_vector;
-- from std_logic_1164_additions
function to_hstring (value : std_ulogic_vector) return string;
function to_hstring (value : std_logic_vector) return string;
function reverse(x : std_logic_vector) return std_logic_vector;
end util;
package body util is
function ceil_log2 (constant x : positive)
return natural is
function hlp (constant x : natural) return natural is
begin
if x < 1 then
return 0;
else
return 1 + hlp(x/2);
end if;
end;
begin -- ceil_log2
return hlp(x-1);
end ceil_log2;
function nor_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.nor_reduce(v);
end;
function or_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.or_reduce(v);
end;
function and_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.and_reduce(v);
end;
function nand_reduce(v : std_logic_vector) return std_logic is
begin
return std_logic_misc.nand_reduce(v);
end;
function nor_reduce(v : std_logic_vector) return boolean is
begin
return nor_reduce(v) = '1';
end;
function or_reduce(v : std_logic_vector) return boolean is
begin
return or_reduce(v) = '1';
end;
function and_reduce(v : std_logic_vector) return boolean is
begin
return and_reduce(v) = '1';
end;
function nand_reduce(v : std_logic_vector) return boolean is
begin
return nand_reduce(v) = '1';
end;
function unary_log (constant v : std_logic_vector)
return std_logic_vector is
alias u : std_logic_vector(v'high downto v'low) is v;
variable result : std_logic_vector(u'range);
begin
for i in u'range loop
if i = u'high then
result(i) := u(i);
else
result(i) := u(i) and nor_reduce(u(u'high downto i+1)); -- FIXME
end if;
end loop; -- i
return result;
end unary_log;
function maximum (constant t1, t2 : natural) return natural is
begin
if t1 > t2 then return t1; else return t2; end if;
end maximum;
function maximum (constant a : integer_array) return integer is
variable result : integer := a(a'low);
begin
for i in a'range loop
if a(i) > result then
result := a(i);
end if;
end loop;
return result;
end;
function minimum (constant t1, t2 : natural) return natural is
begin
if t1 < t2 then return t1; else return t2; end if;
end minimum;
function minimum (constant t1, t2 : std_logic_vector) return std_logic_vector is
begin
if t1 < t2 then return t1; else return t2; end if;
end;
function minimum (constant a : integer_array) return integer is
variable result : integer := a(a'low);
begin
for i in a'range loop
if a(i) < result then
result := a(i);
end if;
end loop;
return result;
end;
function "and" (constant arg : std_logic_vector; constant s : std_logic)
return std_logic_vector is
variable result : std_logic_vector(arg'range);
begin -- "and"
for i in arg'range loop
result(i) := arg(i) and s;
end loop; -- i
return result;
end "and";
function encode (constant arg : std_logic_vector) return natural is
alias xarg : std_logic_vector(0 to arg'length-1) is arg;
constant sz : natural := ceil_log2(xarg'length);
variable result : std_logic_vector(sz-1 downto 0);
variable sum : std_logic;
variable b, p : natural;
variable t : natural := 1;
begin
for i in 0 to sz-1 loop
b := t;
t := 2 * t;
p := t;
sum := '0';
eval_result_i : loop
exit when b > xarg'high;
sum := sum or not nor_reduce(xarg(xarg'low + b
to xarg'low + minimum(p-1, xarg'high)));
b := b + t;
p := p + t;
end loop eval_result_i;
result(i) := sum;
end loop; -- i
return conv_integer(result);
end;
function to_stdl (constant v : in boolean) return std_logic is
begin
if v then
return '1';
else
return '0';
end if;
end;
function lowest_fired (arg : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(arg'range);
function no_competitors(i : integer) return std_logic is
begin
if i = arg'low then
return '1';
end if;
if arg'ascending then
return nor_reduce(arg(arg'low to i-1));
else
return nor_reduce(arg(i-1 downto arg'low));
end if;
end;
begin
for i in arg'range loop
result(i) := arg(i) and no_competitors(i);
end loop;
return result;
end;
function invert(arg : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(arg'range);
begin
for i in arg'range loop
result(i) := arg(arg'left + arg'right - i);
end loop;
return result;
end;
function singleton(arg : std_logic) return std_logic_vector is
begin
return (0 => arg);
end;
function align8_down(v : std_logic_vector) return std_logic_vector is
begin
return v(v'high downto v'low + 3) & "000";
end;
function align2_down(v : std_logic_vector) return std_logic_vector is
begin
return v(v'high downto v'low + 1) & "0";
end;
function align8_up(v : std_logic_vector) return std_logic_vector is
constant v1 : std_logic_vector(v'range) := v + "111";
begin
return v1(v'high downto v'low + 3) & "000";
end;
-- treat segment descriptor
function desc2mask(x : std_logic_vector) return std_logic_vector is
begin
return (x-1) xor x;
end;
function desc2base(x : std_logic_vector) return std_logic_vector is
begin
return (x-1) and x;
end;
function desc2mask(x : std_logic_vector; hint_logsize : natural; exact : boolean := false)
return std_logic_vector
is
subtype hi_range is integer range x'high downto x'low + hint_logsize;
subtype lo_range is integer range x'low + hint_logsize - 1 downto x'low;
variable result : std_logic_vector(x'range);
begin
result(lo_range) := (others => '1');
if exact then
result(hi_range) := (others => '0');
else
result(hi_range) := desc2mask(x(hi_range));
end if;
return result;
end;
function desc2base(x : std_logic_vector; hint_logsize : natural; exact : boolean := false)
return std_logic_vector
is
constant tail : std_logic_vector(hint_logsize - 1 downto 0) := (others => '0');
begin
if exact then
return x(x'high downto x'low + hint_logsize) & tail;
else
return desc2base(x(x'high downto x'low + hint_logsize)) & tail;
end if;
end;
function extend64(v : std_logic_vector) return qword is
variable result : qword := (others => '0');
begin
result(v'length - 1 downto 0) := v;
return result;
end;
function extend64(i : integer) return qword is
begin
return conv_std_logic_vector(i, 64);
end;
function extend(size : natural; v : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(size - 1 downto 0) := (others => '0');
begin
result(v'length - 1 downto 0) := v;
return result;
end;
function to_hstring (value : std_ulogic_vector) return string is
constant ne : integer := (value'length+3)/4;
variable pad : std_ulogic_vector(0 to (ne*4 - value'length) - 1);
variable ivalue : std_ulogic_vector(0 to ne*4 - 1);
variable result : string(1 to ne);
variable quad : std_ulogic_vector(0 to 3);
begin
if value'length < 1 then
return "";
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_hstring (value : std_logic_vector) return string is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function reverse(x : std_logic_vector) return std_logic_vector is
variable result : std_logic_vector(x'range);
begin
for i in x'range loop
result(i) := x(x'high + x'low - i);
end loop;
return result;
end;
end util;
| bsd-3-clause | 971e88c2d34b14365904507e79b72b10 | 0.570069 | 3.707383 | false | false | false | false |
freecores/t400 | rtl/tech/cyclone/t400_por.vhd | 1 | 3,981 | -------------------------------------------------------------------------------
--
-- T400 Core
--
-- $Id: t400_por.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Wrapper for technology dependent power-on reset circuitry.
--
-- Altera Cyclone flavor.
--
-- Generate a reset upon power-on for specified number of clocks.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t400_por is
generic (
delay_g : integer := 4;
cnt_width_g : integer := 2
);
port (
clk_i : in std_logic;
por_n_o : out std_logic
);
end t400_por;
library ieee;
use ieee.numeric_std.all;
architecture cyclone of t400_por is
signal por_cnt_q : unsigned(cnt_width_g-1 downto 0)
-- pragma translate_off
-- initialize for simulation only
:= (others => '0')
-- pragma translate_on
;
signal por_n_q : std_logic
-- pragma translate_off
-- initialize for simulation only
:= '0'
-- pragma translate_on
;
-- Specify power-up level of por counter and por source.
-- Refer to "Quartus II Integrated Synthesis", section "Altera Attribute".
attribute altera_attribute : string;
attribute altera_attribute of por_cnt_q : signal is "-name POWER_UP_LEVEL LOW";
attribute altera_attribute of por_n_q : signal is "-name POWER_UP_LEVEL LOW";
begin
-----------------------------------------------------------------------------
-- Process por_cnt
--
-- Purpose:
-- Generate a power-on reset for the specifiec number of clocks.
--
por_cnt: process (clk_i)
begin
if clk_i'event and clk_i = '1' then
if por_cnt_q = delay_g-1 then
por_n_q <= '1';
else
por_cnt_q <= por_cnt_q + 1;
end if;
end if;
end process por_cnt;
--
-----------------------------------------------------------------------------
por_n_o <= por_n_q;
end cyclone;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 | a211805dd91676ba9acd1ada4984ea1e | 0.6001 | 4.374725 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci32lite/onalib.vhd | 1 | 13,647 | --+-------------------------------------------------------------------------------------------------+
--| |
--| Fileo: onalib.vhd |
--| |
--| Project: onalib |
--| |
--| Description: Libreria de componentes en VHDL. |
--| |
--+-------------------------------------------------------------------------------------------------+
--| Component | Descripcion |
--+-------------------------------------------------------------------------------------------------+
--| sync(clk, d, q) | Sincronizacion de una señal a traves de un FF. |
--| | Sin reset. |
--+-------------------------------------------------------------------------------------------------+
--| sync2(clk, d, q) | Doble Sincronizacion de una señal a traves de dos |
--| | FF. Sin reset. |
--+-------------------------------------------------------------------------------------------------+
--| sync2h(clk, rst, d, q) | Doble Sincronizacion de una señal a traves de dos |
--| | FF. Con reset e inicializacion a '1'. |
--+-------------------------------------------------------------------------------------------------+
--| sync2l(clk, rst, d, q) | Doble Sincronizacion de una señal a traves de dos |
--| | FF. Con reset e inicializacion a '0'. |
--+-------------------------------------------------------------------------------------------------+
--| syncrsld(clk, rst, ld, d, q) | Sincronizacion de una señal a traves de un FF |
--| | con reset y load. |
--+-------------------------------------------------------------------------------------------------+
--| syncv(size)(clock, d, q) | Sincronizacion de un vector (generic) |
--| | con reset y load. |
--+-------------------------------------------------------------------------------------------------+
--| decoder3to8(i, o) | Decoder 3 to 8 |
--+-------------------------------------------------------------------------------------------------+
--| pfs(clk, a, y) | Pulso a '1' en Flanco de Subida |
--+-------------------------------------------------------------------------------------------------+
--| pfb(clk, a, y) | Pulso a '1' en Flanco de bajada |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| ENTITY & ARCHITECTURE |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------+
--| sync |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity sync is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end sync;
architecture rtl of sync is
begin
SYNCP: process( clk, d )
begin
if ( rising_edge(clk) ) then
q <= d;
end if;
end process SYNCP;
end rtl;
--+-----------------------------------------+
--| synch |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity synch is
port (
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end synch;
architecture rtl of synch is
begin
SYNCHP: process( clk, rst, d )
begin
if (rst = '1') then
q <= '1';
elsif ( rising_edge(clk) ) then
q <= d;
end if;
end process SYNCHP;
end rtl;
--+-----------------------------------------+
--| syncl |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity syncl is
port (
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end syncl;
architecture rtl of syncl is
begin
SYNCLP: process( clk, rst, d )
begin
if (rst = '1') then
q <= '0';
elsif ( rising_edge(clk) ) then
q <= d;
end if;
end process SYNCLP;
end rtl;
--+-----------------------------------------+
--| sync2 |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity sync2 is
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end sync2;
architecture rtl of sync2 is
signal tmp: std_logic;
begin
SYNC2P: process ( clk, d, tmp)
begin
if ( rising_edge(clk) ) then
tmp <= d;
q <= tmp;
end if;
end process SYNC2P;
end rtl;
--+-----------------------------------------+
--| sync2h |
--+-----------------------------------------+
-- sync2 con inicializacion a '1' con el reset
library ieee;
use ieee.std_logic_1164.all;
entity sync2h is
port (
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end sync2h;
architecture rtl of sync2h is
signal tmp: std_logic;
begin
SYNC2HP: process ( clk, rst, d, tmp)
begin
if (rst = '1') then
tmp <= '1';
q <= '1';
elsif ( rising_edge(clk) ) then
tmp <= d;
q <= tmp;
end if;
end process SYNC2HP;
end rtl;
--+-----------------------------------------+
--| sync2l |
--+-----------------------------------------+
-- sync2 con inicializacion a '0' con el reset
library ieee;
use ieee.std_logic_1164.all;
entity sync2l is
port (
clk : in std_logic;
rst : in std_logic;
d : in std_logic;
q : out std_logic
);
end sync2l;
architecture rtl of sync2l is
signal tmp: std_logic;
begin
SYNC2LP: process ( clk, rst, d, tmp)
begin
if (rst = '1') then
tmp <= '0';
q <= '0';
elsif ( rising_edge(clk) ) then
tmp <= d;
q <= tmp;
end if;
end process SYNC2LP;
end rtl;
--+-----------------------------------------+
--| syncv |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity syncv is
generic ( size: integer := 8 );
port (
clk : in std_logic;
d : in std_logic_vector(size-1 downto 0);
q : out std_logic_vector(size-1 downto 0)
);
end syncv;
architecture rtl of syncv is
begin
SYNCVP: process( clk, d )
begin
if ( rising_edge(clk) ) then
q <= d;
end if;
end process SYNCVP;
end rtl;
--+-----------------------------------------+
--| syncv2h |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity syncv2h is
generic ( size: integer := 8 );
port (
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector(size-1 downto 0);
q : out std_logic_vector(size-1 downto 0)
);
end syncv2h;
architecture rtl of syncv2h is
signal tmp: std_logic_vector(size-1 downto 0);
begin
SYNCV2HP: process( clk, d, rst )
begin
if (rst = '1') then
tmp <= (others => '1');
q <= (others => '1');
elsif ( rising_edge(clk) ) then
tmp <= d;
q <= tmp;
end if;
end process SYNCV2HP;
end rtl;
--+-----------------------------------------+
--| decoder3to8 |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity decoder3to8 is
port (
i : in std_logic_vector(2 downto 0);
o : out std_logic_vector(7 downto 0)
);
end decoder3to8;
architecture rtl of decoder3to8 is
begin
DECOD3TO8P: process( i )
begin
if ( i = "111" ) then o <= "01111111";
elsif ( i = "110" ) then o <= "10111111";
elsif ( i = "101" ) then o <= "11011111";
elsif ( i = "100" ) then o <= "11101111";
elsif ( i = "011" ) then o <= "11110111";
elsif ( i = "010" ) then o <= "11111011";
elsif ( i = "001" ) then o <= "11111101";
elsif ( i = "000" ) then o <= "11111110";
else
o <= "11111111";
end if;
end process DECOD3TO8P;
end rtl;
--+-----------------------------------------+
--| pfs |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity pfs is
port (
clk : in std_logic;
rst : in std_logic;
a : in std_logic;
y : out std_logic
);
end pfs;
architecture rtl of pfs is
signal a_s : std_logic;
signal a_s2 : std_logic;
begin
PFSP: process( clk, rst, a )
begin
if ( rst = '1' ) then
a_s <= '0';
a_s2 <= '1';
elsif ( rising_edge(clk) ) then
a_s <= a;
a_s2 <= a_s;
end if;
end process PFSP;
y <= a_s and (not a_s2);
end rtl;
--+-----------------------------------------+
--| pfb |
--+-----------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
entity pfb is
port (
clk : in std_logic;
rst : in std_logic;
a : in std_logic;
y : out std_logic
);
end pfb;
architecture rtl of pfb is
signal a_s : std_logic;
signal a_s2 : std_logic;
begin
PFBP: process( clk, rst, a )
begin
if ( rst = '1' ) then
a_s <= '1';
a_s2 <= '0';
elsif ( rising_edge(clk) ) then
a_s <= a;
a_s2 <= a_s;
end if;
end process PFBP;
y <= (not a_s) and a_s2;
end rtl;
| gpl-3.0 | f2a78d45673d5bf769deb7887ecbd4b2 | 0.322195 | 4.791784 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/cycloneiii_components.vhd | 1 | 37,942 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package cycloneiii_components is
--
-- cycloneiii_lcell_comb
--
COMPONENT cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
END COMPONENT;
--
-- cycloneiii_routing_wire
--
COMPONENT cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- cycloneiii_pll
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
family_name : string := "Cyclone III";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_ff
--
COMPONENT cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- cycloneiii_ram_block
--
COMPONENT cycloneiii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
COMPONENT cycloneiii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_mac_out
--
COMPONENT cycloneiii_mac_out
GENERIC (
dataa_width : integer := 1;
output_clock : string := "none";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_io_ibuf
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- cycloneiii_io_obuf
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(15 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiii_ddio_oe
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_ddio_out
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_pseudo_diff_out
--
COMPONENT cycloneiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- cycloneiii_io_pad
--
COMPONENT cycloneiii_io_pad
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- cycloneiii_clkctrl
--
COMPONENT cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- cycloneiii_rublock
--
COMPONENT cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiii_apfcontroller
--
COMPONENT cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic;
nceout : out std_logic
);
END COMPONENT;
--
-- cycloneiii_termination
--
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- cycloneiii_jtag
--
COMPONENT cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- cycloneiii_crcblock
--
COMPONENT cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- cycloneiii_oscillator
--
COMPONENT cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
END COMPONENT;
end cycloneiii_components;
| gpl-3.0 | ea566bf62e5d7cbfe48c4e153656153a | 0.474698 | 4.344172 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixgx_atoms.vhd | 1 | 493,397 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixgx_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixgx_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixgx_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixgx_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixgx_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixgx_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixgx_pllpack;
package body stratixgx_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixgx_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixgx_dffe : entity is TRUE;
end stratixgx_dffe;
-- architecture body --
architecture behave of stratixgx_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixgx_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixgx_mux21 : entity is TRUE;
end stratixgx_mux21;
architecture AltVITAL of stratixgx_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixgx_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_mux41 : entity is TRUE;
end stratixgx_mux41;
architecture AltVITAL of stratixgx_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixgx_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixgx_atom_pack.all;
-- entity declaration --
entity stratixgx_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixgx_and1 : entity is TRUE;
end stratixgx_and1;
-- architecture body --
architecture AltVITAL of stratixgx_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Models for STRATIXGX Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_asynch_lcell
--
-- Description : VHDL simulation model for the asynchnous submodule of
-- STRATIXGX Lcell.
--
-- Outputs : Asynchnous LUT function of STRATIXGX Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
ENTITY stratixgx_asynch_lcell is
GENERIC (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_asynch_lcell : ENTITY is TRUE;
END stratixgx_asynch_lcell;
ARCHITECTURE vital_le of stratixgx_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : ARCHITECTURE is TRUE;
signal dataa_ipd : std_ulogic;
signal datab_ipd : std_ulogic;
signal datac_ipd : std_ulogic;
signal datad_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal cin_ipd : std_ulogic;
signal cin0_ipd : std_ulogic;
signal cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout : std_ulogic;
variable tmp_cout : std_ulogic;
variable tmp_cout0 : std_ulogic;
variable tmp_cout1 : std_ulogic;
variable tmp_regin : std_ulogic;
variable lutb : std_ulogic;
variable cintmp : std_ulogic;
variable invertsig : std_ulogic := '0';
variable cinsel : std_ulogic;
variable cinsig : std_ulogic;
variable cin01sel : std_ulogic;
variable luta : std_ulogic;
variable lutc : std_ulogic;
variable lutd : std_ulogic;
variable datacsig : std_ulogic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or
(inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or
(cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or
(cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or
(cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or
(datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta)
);
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta)
);
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta)
);
tmp_cout := VitalMux2(VitalMux2(tmp_cout1,
tmp_cout0,
cin_ipd),
VitalMux2(tmp_cout1,
tmp_cout0,
inverta_ipd),
mode(3)
);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01
(
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_le;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lcell_register
--
-- Description : VHDL simulation model for the register submodule of
-- STRATIXGX Lcell.
--
-- Outputs : Registered output of STRATIXGX Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_lcell_register is
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_lcell_register : ENTITY is TRUE;
end stratixgx_lcell_register;
ARCHITECTURE vital_le_reg of stratixgx_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : ARCHITECTURE is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant stratixgx_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
( R, x, x, H, x, H, x, x, H, x, H, x, H ), -- Sload
( R, x, x, x, x, H, x, x, H, x, H, x, U ), -- Sload
( R, x, x, x, L, H, x, x, x, H, x, x, L ), -- Cascade
( R, x, x, x, H, H, x, x, x, H, x, x, H ), -- Cascade
( R, x, x, x, x, H, x, x, x, H, x, x, U ), -- Cascade
( R, x, L, x, x, H, x, x, x, x, H, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, H, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, H, x, U ), -- Datain
( R, x, L, x, x, H, x, x, x, x, x, x, L ), -- Datain
( R, x, H, x, x, H, x, x, x, x, x, x, H ), -- Datain
( R, x, x, x, x, H, x, x, x, x, x, x, U ), -- Datain
( x, x, x, x, x, x, x, x, x, x, x, x, S )); -- Q=Q
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (regcascin_ipd, regcascin, tipd_regcascin);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process(clk_ipd, aclr_ipd, aload_ipd, datac_ipd,
regcascin_ipd, datain, sclr_ipd, ena_ipd,
sload_ipd, cena, xonv, smode)
variable Tviol_regcascin_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_datac_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_regcascin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_datac_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable qfbkout_VitalGlitchData : VitalGlitchDataType;
-- variables for 'X' generation
variable Tviolation : std_ulogic := '0';
variable tmp_regout : STD_ULOGIC := '0';
variable PreviousData : STD_LOGIC_VECTOR(0 to 10);
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_regcascin_clk,
TimingData => TimingData_regcascin_clk,
TestSignal => regcascin_ipd,
TestSignalName => "REGCASCIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_regcascin_clk_noedge_posedge,
SetupLow => tsetup_regcascin_clk_noedge_posedge,
HoldHigh => thold_regcascin_clk_noedge_posedge,
HoldLow => thold_regcascin_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_datac_clk,
TimingData => TimingData_datac_clk,
TestSignal => datac_ipd,
TestSignalName => "DATAC",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datac_clk_noedge_posedge,
SetupLow => tsetup_datac_clk_noedge_posedge,
HoldHigh => thold_datac_clk_noedge_posedge,
HoldLow => thold_datac_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr_ipd) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => TRUE,
MsgOn => TRUE );
end if;
-------------------------
-- Functionality Section
-------------------------
Tviolation := Tviol_regcascin_clk or Tviol_datain_clk or
Tviol_datac_clk or Tviol_ena_clk or
Tviol_sclr_clk or Tviol_sload_clk;
VitalStateTable (
Result => tmp_regout,
PreviousDataIn => PreviousData,
StateTable => stratixgx_regtab,
DataIn => (CLK_ipd, ACLR_ipd, datain, datac_ipd,
regcascin_ipd, ENA_ipd, aload_ipd, sclr_ipd,
sload_ipd, cena, smode)
);
tmp_regout := (xonv AND Tviolation) XOR tmp_regout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => qfbkout,
OutSignalName => "QFBKOUT",
OutTemp => tmp_regout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_qfbkout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_qfbkout_posedge, TRUE),
2 => (datac_ipd'last_event, tpd_datac_qfbkout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_qfbkout_posedge, TRUE)),
GlitchData => qfbkout_VitalGlitchData,
Mode => OnEvent,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le_reg;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lcell
--
-- Description : VHDL simulation model for STRATIXGX Lcell.
--
-- Outputs : Output of STRATIXGX Lcell.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_asynch_lcell;
use work.stratixgx_lcell_register;
ENTITY stratixgx_lcell is
GENERIC (
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin_used : string := "false";
cin0_used : string := "false";
cin1_used : string := "false";
output_mode : string := "reg_and_comb";
x_on_violation : string := "on";
lpm_type : string := "stratixgx_lcell"
);
PORT (
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end stratixgx_lcell;
ARCHITECTURE vital_le_atom of stratixgx_lcell is
signal dffin : std_logic;
signal qfbkin : std_logic;
signal mode : std_logic_vector(5 downto 0);
COMPONENT stratixgx_asynch_lcell
GENERIC (
lms : std_logic_vector(15 downto 0);
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01
);
PORT (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_lcell_register
GENERIC (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01
);
PORT (
clk :in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic
);
end COMPONENT;
signal aclr1, xonv, cena, smode : std_logic ;
begin
aclr1 <= aclr or (not devclrn) or (not devpor);
cena <= '1' when (register_cascade_mode = "on") else '0';
xonv <= '1' when (x_on_violation = "on") else '0';
smode <= '1' when (synch_mode = "on") else '0';
mode(0) <= '1' when operation_mode = "normal" else
'0'; -- operation_mode = "arithmetic"
mode(1) <= '1' when sum_lutc_input = "datac" else
'0' ; -- sum_lutc_input = "cin"
mode(2) <= '1' when sum_lutc_input = "qfbk" else
'0'; -- sum_lutc_input = "cin" or "datac"
mode(3) <= '1' when cin_used = "true" else
'0'; -- cin_used = "false"
mode(4) <= '1' when cin0_used = "true" else
'0'; -- cin0_used = "false"
mode(5) <= '1' when cin1_used = "true" else
'0'; -- cin1_used = "false"
lecomb: stratixgx_asynch_lcell
GENERIC map (
lms => str_to_bin(lut_mask)
)
PORT map (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
qfbkin => qfbkin,
inverta => map_x_to_0(inverta),
cin => cin,
cin0 => cin0,
cin1 => cin1,
mode => mode,
combout => combout,
cout => cout,
cout0 => cout0,
cout1 => cout1,
regin => dffin
);
lereg: stratixgx_lcell_register
PORT map (
clk => clk,
datain => dffin,
datac => datac,
smode => smode,
regcascin => regcascin,
aclr => aclr1,
aload => aload,
sclr => sclr,
sload => sload,
ena => ena,
cena => cena,
xonv => xonv,
regout => regout,
qfbkout => qfbkin
);
end vital_le_atom;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_ASYNCH_IO
--
-- Description : Timing simulation model for the asynchronous submodule
-- of STRATIXGX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_asynch_io is
GENERIC (
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
phase_shift_delay : time := 0 ps;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsundelayedout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_delayctrlin : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
delayctrlin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout: out STD_LOGIC;
dqsundelayedout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of stratixgx_asynch_io : ENTITY is TRUE;
end stratixgx_asynch_io;
ARCHITECTURE behave of stratixgx_asynch_io is
attribute VITAL_LEVEL0 of behave : ARCHITECTURE is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_ipd, delayctrlin, tipd_delayctrlin);
end block;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, delayctrlin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable dqsundelayedout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable combout_tmp : std_logic;
variable dqs_delay : VitalDelayType01 := (0 ps, 0 ps);
variable warn_x : boolean := false;
variable combout_delay : VitalDelayType01;
variable dqs_delay_is_applied : boolean := false;
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (delayctrlin_ipd = '1') then
if (not dqs_delay_is_applied) then
for i in combout_delay'range loop
combout_delay(i) := combout_delay(i) + phase_shift_delay;
end loop;
dqs_delay_is_applied := true;
end if;
warn_x := false;
elsif (delayctrlin_ipd = '0') then
combout_delay := tpd_padio_combout;
dqs_delay_is_applied := false;
warn_x := false;
elsif (delayctrlin_ipd'event) then
combout_delay := tpd_padio_combout;
dqs_delay_is_applied := false;
if (not warn_x) then
assert false report "Illegal value detected on input DELAYCTRLIN" severity warning;
warn_x := true;
end if;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsundelayedout,
OutSignalName => "dqsundelayedout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, tpd_padio_dqsundelayedout, TRUE)),
GlitchData => dqsundelayedout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_IO_REGISTER
--
-- Description : Timing simulation model for the register submodule
-- of STRATIXGX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_io_register is
GENERIC (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_io_register : ENTITY is TRUE;
end stratixgx_io_register;
ARCHITECTURE vital_io_reg of stratixgx_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : ARCHITECTURE is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd,
areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_IO
--
-- Description : Timing simulation model for STRATIXGX IO.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_pllpack.all;
use work.stratixgx_asynch_io;
use work.stratixgx_io_register;
use work.stratixgx_mux21;
use work.stratixgx_and1;
ENTITY stratixgx_io is
GENERIC (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratixgx_io"
);
PORT (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
end stratixgx_io;
ARCHITECTURE structure of stratixgx_io is
COMPONENT stratixgx_asynch_io
GENERIC
(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
phase_shift_delay : time := 0 ps);
PORT
(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
delayctrlin : in std_logic;
padio : inout STD_LOGIC;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC;
dqsundelayedout : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_io_register
GENERIC
(
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01);
PORT
(
clk : in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_mux21
GENERIC
(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
PORT
(
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_and1
GENERIC
(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
PORT
(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end COMPONENT;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
constant phase_shift_delay : time := (dqs_str2int(sim_dll_phase_shift) * dqs_str2int(sim_dqs_input_frequency) * 1 ps) / 360;
begin
not_inclk <= not inclk;
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up
)
PORT map
(
regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- in_ddio0_reg
in_ddio0_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up
)
PORT map
(
regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- in_ddio1_reg
-- this register does not have sync_reset
in_ddio1_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => input_async_reset,
SYNC_RESET => "none",
POWER_UP => input_power_up
)
PORT map
(
regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn
);
-- out_reg
out_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up
)
PORT map
(
regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- out ddio reg
out_ddio_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
PORT map
(
regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- oe reg
oe_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up
)
PORT map
(
regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
-- oe_pulse reg
oe_pulse_reg : stratixgx_io_register
GENERIC map
(
ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up
)
PORT map
(
regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn
);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : stratixgx_and1
PORT map
(
Y => outclk_delayed,
IN1 => outclk
);
ddio_data_mux : stratixgx_mux21
PORT map
(
MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed
);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or
ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : stratixgx_asynch_io
GENERIC map
(
OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
PHASE_SHIFT_DELAY => phase_shift_delay
)
PORT map
(
datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
delayctrlin => delayctrlin,
padio => padio,
combout => combout,
regout => regout,
ddioregout => ddioregout,
dqsundelayedout => dqsundelayedout
);
end structure;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_BIT_REGISTER
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mac_bit_register is
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end stratixgx_mac_bit_register;
architecture reg_arch OF stratixgx_mac_bit_register IS
signal data_ipd : STD_LOGIC := '0';
signal clk_ipd : STD_LOGIC := '0';
signal aclr_ipd : STD_LOGIC := '0';
signal ena_ipd : STD_LOGIC := '0';
signal dataout_tmp : STD_LOGIC := '0';
begin
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_sig : STD_LOGIC := '0';
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
begin
if async = '1' then
dataout_sig := data_ipd;
elsif (aclr_ipd = '1') then
dataout_sig := '0';
elsif (clk_ipd'EVENT AND clk_ipd = '1') then
if ena_ipd = '1' then
dataout_sig := data_ipd;
else
dataout_sig := dataout_sig;
end if;
end if;
dataout_tmp <= dataout_sig;
if (async = '0') then
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_data_clk_noedge_posedge,
SetupLow => tsetup_data_clk_noedge_posedge,
HoldHigh => thold_data_clk_noedge_posedge,
HoldLow => thold_data_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
end process;
-- Path Delay Selection
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
end reg_arch;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_REGISTER
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mac_register is
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end stratixgx_mac_register;
architecture reg_arch OF stratixgx_mac_register IS
signal data_ipd : STD_LOGIC_VECTOR (71 downto 0) := (others => '0');
signal clk_ipd : STD_LOGIC := '0';
signal aclr_ipd : STD_LOGIC := '0';
signal ena_ipd : STD_LOGIC := '0';
signal dataout_tmp : STD_LOGIC_VECTOR (71 downto 0):= (others => '0');
begin
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_sig : STD_LOGIC_VECTOR (71 downto 0):= (others => '0');
begin
if async = '1' then
dataout_sig := data_ipd;
elsif (aclr_ipd = '1') then
dataout_sig := (others => '0');
elsif (clk_ipd'EVENT AND clk_ipd = '1') then
if ena_ipd = '1' then
dataout_sig := data_ipd;
else
dataout_sig := dataout_sig;
end if;
end if;
dataout_tmp <= dataout_sig;
end process;
sh: block
begin
g0 : for i in data'range generate
process(data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
begin
if (async = '0') then
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "data(i)",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => TRUE,
MsgOn => TRUE );
end if;
END PROCESS;
end generate g0;
end block;
-- Path Delay Selection
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
end reg_arch;
-- ///////////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_MULT_INTERNAL
-- //
-- ///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_mac_mult_internal is
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_scanouta :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_scanoutb :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
port
(
dataa : IN std_logic_vector (dataa_width - 1 downto 0) := (others => '0');
datab : IN std_logic_vector (datab_width - 1 downto 0) := (others => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
scanouta : OUT std_logic_vector (dataa_width-1 downto 0);
scanoutb : OUT std_logic_vector (datab_width-1 downto 0);
dataout : OUT std_logic_vector (dataa_width+datab_width-1 downto 0)
);
end stratixgx_mac_mult_internal;
architecture mult_internal_arch OF stratixgx_mac_mult_internal IS
signal dataa_ipd : std_logic_vector (dataa_width-1 downto 0) := (others => '0');
signal datab_ipd : std_logic_vector (datab_width-1 downto 0) := (others => '0');
signal dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
constant DefGlitchMode : VitalGlitchKindType := OnEvent;
begin
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
process(dataa_ipd, datab_ipd, signa, signb)
begin
if((signa = '0') and (signb = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa = '1') and (signb = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa = '1') and (signb = '1')) then
dataout_tmp(dataa_width + datab_width -1 downto 0) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa = '0') and (signb = '0')) then
dataout_tmp(dataa_width + datab_width -1 downto 0) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
PathDelay :block
begin
g1: for i in dataa_width + datab_width -1 downto 0 generate
p1: process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
constant DefGlitchMode : VitalGlitchKindType := OnEvent;
begin -- process p1
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process p1;
a: if i < dataa_width generate
p2: PROCESS(dataa_ipd(i))
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process p2;
end generate a;
b: if i < datab_width generate
p3: PROCESS(datab_ipd(i))
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process p3;
end generate b;
end generate g1;
end block;
end mult_internal_arch;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_OUT_INTERNAL
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_mac_out_internal IS
GENERIC
(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
dataout_width : integer := 72;
signa_clock : string := "none";
signb_clock : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
dataout_global : in std_logic_vector (dataout_width-1 downto 0) := (others => '0');
signx : in std_logic := '1';
signy : in std_logic := '1';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
zeroacc : in std_logic := '0';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
-- /////////////////////////////////////////////////////////////////////////////
-- //
-- // ADD_OR_SUB_ACCUM
-- //
-- /////////////////////////////////////////////////////////////////////////////
function add_or_sub_accum
(
sign_a : in std_logic := '0';
data_a : in std_logic_vector(dataout_width-1 downto 0)
:= (others => '0');
sign_b : in std_logic := '0';
data_b : in std_logic_vector(dataa_width-1 downto 0)
:= (others => '0');
operation : in string
) return std_logic_vector is
variable sign : std_logic := '0';
variable unsigned_add : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable unsigned_sub : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable signed_add : std_logic_vector(dataout_width downto 0)
:= (others => '0');
variable signed_sub : std_logic_vector(dataout_width downto 0)
:= (others => '0');
begin
-- signed or unsigned
sign := ((data_a(dataout_width-1) and (sign_a))
or (data_b(dataa_width-1) and (sign_b)));
if(sign = '1') then
signed_add(dataout_width downto 0) :=
sxt((signed(data_a) + signed(data_b)), dataout_width+1);
signed_sub(dataout_width downto 0) :=
sxt((signed(data_a) - signed(data_b)), dataout_width+1);
else
unsigned_add(dataout_width downto 0) :=
ext((unsigned('0' & data_a) + unsigned('0' & data_b)), dataout_width+1);
unsigned_sub(dataout_width downto 0) :=
sxt((unsigned('0' & data_a) - unsigned('0' & data_b)), dataout_width+1);
end if;
if (operation = "ADD") then
if (sign = '1') then
return signed_add(dataout_width downto 0);
else
return unsigned_add(dataout_width downto 0);
end if;
elsif (operation = "SUB") then
if (sign = '1') then
return signed_sub(dataout_width downto 0);
else
return unsigned_sub(dataout_width downto 0);
end if;
end if;
end add_or_sub_accum;
end stratixgx_mac_out_internal;
ARCHITECTURE mac_add OF stratixgx_mac_out_internal IS
signal dataa_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datab_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datac_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal datad_ipd : std_logic_vector(35 downto 0) := (others => '0');
signal dataa_u : std_logic_vector(71 downto 0) := (others => '0');
signal datab_u : std_logic_vector(71 downto 0) := (others => '0');
signal datab_s : std_logic_vector(71 downto 0) := (others => '0');
signal datac_u : std_logic_vector(71 downto 0) := (others => '0');
signal datac_s : std_logic_vector(71 downto 0) := (others => '0');
signal datad_u : std_logic_vector(71 downto 0) := (others => '0');
signal datad_s : std_logic_vector(71 downto 0) := (others => '0');
signal signx_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal signy_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal addnsub0_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal addnsub1_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal zeroacc_tmp : std_logic_vector(0 downto 0) := (others => '0');
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
signal dataout_t : std_logic_vector(72 downto 0) := (others => '0');
signal next_dataout : std_logic_vector(72 downto 0) := (others => '0');
signal sll_36 : std_logic_vector(35 downto 0) := (others => '0');
signal sll_18 : std_logic_vector(17 downto 0) := (others => '0');
signal accoverflow_tmp: std_logic := '0';
signal sign_a_or_b : std_logic := '0';
begin
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 : for i in datac'range generate
VitalWireDelay (datac_ipd(i), datac(i), tipd_datac(i));
end generate;
g4 : for i in datad'range generate
VitalWireDelay (datad_ipd(i), datad(i), tipd_datad(i));
end generate;
end block;
signx_tmp(0) <= signx;
signy_tmp(0) <= signy;
addnsub0_tmp(0) <= addnsub0;
addnsub1_tmp(0) <= addnsub1;
zeroacc_tmp(0) <= zeroacc;
sign_a_or_b <= '1' when ((signx_tmp(0) = '1') or (signy_tmp(0) = '1'))
else '0';
main : process (dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
signx_tmp, signy_tmp, addnsub0_tmp, addnsub1_tmp,
dataout_t, zeroacc_tmp, dataout_global,
sign_a_or_b, next_dataout, dataa_u, datab_u, datac_u,
datad_u, datab_s, datac_s, datad_s)
begin
if operation_mode = "output_only" then
dataout_tmp(dataa_width-1 downto 0) <= dataa_ipd(dataa_width-1 downto 0);
elsif operation_mode = "accumulator" then
if(zeroacc_tmp(0) = '0') then
if(addnsub0_tmp(0) = '0') then
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b,
dataout_global(dataout_width-1 downto 0),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"SUB");
else
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b,
dataout_global(dataout_width-1 downto 0),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"ADD");
end if;
else
if(addnsub0_tmp(0) = '0') then
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b, (others => '0'),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"SUB");
else
next_dataout(dataout_width downto 0) <=
add_or_sub_accum(sign_a_or_b, (others => '0'),
sign_a_or_b, dataa_ipd(dataa_width-1 downto 0),
"ADD");
end if;
end if;
dataout_tmp(dataout_width-1 downto 0) <=
next_dataout(dataout_width-1 downto 0);
if(sign_a_or_b = '1') then
accoverflow_tmp <=
next_dataout(dataa_width+16) xor next_dataout(dataa_width+15);
else
accoverflow_tmp <= next_dataout(dataa_width+16);
end if;
elsif operation_mode = "one_level_adder" then
if(addnsub0_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+1));
else
dataout_tmp(dataa_width downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+1));
end if;
else
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+1));
else
dataout_tmp(dataa_width downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+1));
end if;
end if;
elsif operation_mode = "two_level_adder" then
-- dataout = (dataa - datab) + (datac - datad);
if(addnsub0_tmp(0) = '0' and addnsub1_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa + datab) + (datac - datad);
elsif(addnsub0_tmp(0) = '1' and addnsub1_tmp(0) = '0') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa - datab) + (datac + datad);
elsif(addnsub0_tmp(0) = '0' and addnsub1_tmp(0) = '1') then
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) -
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
-- dataout = (dataa + datab) + (datac + datad);
else
if (sign_a_or_b = '1') then
dataout_tmp(dataa_width+1 downto 0) <=
signed(sxt(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
signed(sxt(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
signed(sxt(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
signed(sxt(datad_ipd(datad_width-1 downto 0), dataa_width+2));
else
dataout_tmp(dataa_width+1 downto 0) <=
unsigned(ext(dataa_ipd(dataa_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datab_ipd(datab_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datac_ipd(datac_width-1 downto 0), dataa_width+2)) +
unsigned(ext(datad_ipd(datad_width-1 downto 0), dataa_width+2));
end if;
end if;
elsif operation_mode = "36_bit_multiply" then
dataa_u <= (others => '0');
datab_u <= (others => '0');
datac_u <= (others => '0');
datad_u <= (others => '0');
datab_s <= (others => '0');
datac_s <= (others => '0');
sll_36 <= (others => '0');
sll_18 <= (others => '0');
dataa_u(35 downto 0) <= dataa_ipd;
datab_u(71 downto 36) <= datab_ipd;
datab_s(71 downto 36) <= datab_ipd;
datac_u(53 downto 18) <= datac_ipd;
datac_s(71 downto 18) <= sxt(datac_ipd(datac_width-1 downto 0), 54);
datad_u(53 downto 18) <= datad_ipd;
datad_s(71 downto 18) <= sxt(datad_ipd(datad_width-1 downto 0), 54);
if((signx_tmp(0) = '0') and (signy_tmp(0) = '0')) then
dataout_tmp <= unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signx_tmp(0) = '0') and (signy_tmp(0) = '1')) then
dataout_t <= signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
elsif((signx_tmp(0) = '1') and (signy_tmp(0) = '0')) then
dataout_t <= signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
elsif((signx_tmp(0) = '1') and (signy_tmp(0) = '1')) then
dataout_t <= signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp <= dataout_t(71 downto 0);
end if;
end if;
end process;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx_tmp'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy_tmp'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0_tmp'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1_tmp'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc_tmp'last_event, tpd_zeroacc_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate g1;
g2 : for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx_tmp'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy_tmp'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0_tmp'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1_tmp'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc_tmp'last_event, tpd_zeroacc_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
end generate g2;
end block;
END mac_add;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_MULT
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_mac_register;
use work.stratixgx_mac_mult_internal;
entity stratixgx_mac_mult IS
generic
(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_mult"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector((dataa_width+datab_width)-1 downto 0);
scanouta : out std_logic_vector(dataa_width-1 downto 0);
scanoutb : out std_logic_vector(datab_width-1 downto 0)
);
-- SELECT THE CLOCK, CLEAR, or ENABLE LINE FUNCTION
function select_the(constant string_name : string)
return natural is
begin
if string_name = "0" then
return 0;
elsif string_name = "1" then
return 1;
elsif string_name = "2" then
return 2;
elsif string_name = "3" then
return 3;
else
return 0;
end if;
end select_the;
END stratixgx_mac_mult;
architecture mult_arch OF stratixgx_mac_mult IS
component stratixgx_mac_bit_register
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end component;
component stratixgx_mac_register
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0):= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
ena : IN STD_LOGIC;
async : IN STD_LOGIC;
if_aclr : IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end component;
component stratixgx_mac_mult_internal
GENERIC
(
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout :VitalDelayArrayType01(18*36-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_scanouta :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_scanoutb :VitalDelayArrayType01(18*18-1 downto 0) := (OTHERS => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT
(
dataa : IN std_logic_vector (dataa_width-1 downto 0) := (others => '0');
datab : IN std_logic_vector (datab_width-1 downto 0) := (others => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
scanouta : OUT std_logic_vector (dataa_width-1 downto 0);
scanoutb : OUT std_logic_vector (datab_width-1 downto 0);
dataout : OUT std_logic_vector (dataa_width+datab_width-1 downto 0)
);
end component;
signal mult_output : std_logic_vector(71 downto 0) := (others => '0');
signal scanouta_tmp : std_logic_vector(71 downto 0) := (others => '0');
signal scanoutb_tmp : std_logic_vector(71 downto 0) := (others => '0') ;
signal signa_out : std_logic := '1';
signal signb_out : std_logic := '1';
signal dataa_tmp : std_logic_vector(71 downto 0);
signal datab_tmp : std_logic_vector(71 downto 0);
signal dataout_tmp : std_logic_vector(71 downto 0);
signal dataa_async : std_logic := '0';
signal datab_async : std_logic := '0';
signal signa_async : std_logic := '1';
signal signb_async : std_logic := '1';
signal dataout_async : std_logic := '0';
signal signa_internally : std_logic := '0';
signal signb_internally : std_logic := '0';
signal clk_dataa : std_logic;
signal aclr_dataa : std_logic;
signal ena_dataa : std_logic;
signal clk_datab : std_logic;
signal aclr_datab : std_logic;
signal ena_datab : std_logic;
signal clk_signa : std_logic;
signal aclr_signa : std_logic;
signal ena_signa : std_logic;
signal clk_signb : std_logic;
signal aclr_signb : std_logic;
signal ena_signb : std_logic;
signal clk_dataout : std_logic;
signal aclr_dataout : std_logic;
signal ena_dataout : std_logic;
signal dataa_if_clear : std_logic;
signal datab_if_clear : std_logic;
signal signa_if_clear : std_logic;
signal signb_if_clear : std_logic;
signal dataout_if_clear : std_logic;
signal signa_tmp : std_logic;
signal signb_tmp : std_logic;
begin
signa_tmp <= signa;
signb_tmp <= signb;
dataa_async <= '1' when (dataa_clock = "none" or dataa_clear = "none") else '0';
datab_async <= '1' when (datab_clock = "none" or datab_clear = "none") else '0';
signa_async <= '1' when (signa_clock = "none" or signa_clear = "none") else '0';
signb_async <= '1' when (signb_clock = "none" or signb_clear = "none") else '0';
dataout_async <=
'1' when (output_clock = "none" or output_clear = "none") else '0';
signa_internally <= signa_out when (signa_internally_grounded = "false") else '0';
signb_internally <= signb_out when (signb_internally_grounded = "false") else '0';
--Assign the values for if_aclr ports
dataa_if_clear <= '1' when (dataa_clear /= "none") else '0';
datab_if_clear <= '1' when (datab_clear /= "none") else '0';
signa_if_clear <= '1' when (signa_clear /= "none") else '0';
signb_if_clear <= '1' when (signb_clear /= "none") else '0';
dataout_if_clear <='1' when (output_clear /= "none") else '0';
dataa_tmp(dataa_width-1 downto 0) <= dataa;
datab_tmp(datab_width-1 downto 0) <= datab;
dataout <= dataout_tmp((dataa_width+datab_width)-1 downto 0);
clk_dataa <= clk(select_the(dataa_clock));
aclr_dataa <= aclr(select_the(dataa_clear))or not(devclrn) or not(devpor);
ena_dataa <= ena(select_the(dataa_clock));
dataa_mac_reg : stratixgx_mac_register
generic map (data_width => dataa_width)
port map (data => dataa_tmp,
clk => clk_dataa,
aclr => aclr_dataa,
ena => ena_dataa,
if_aclr => dataa_if_clear,
dataout => scanouta_tmp,
async => dataa_async);
clk_datab <= clk(select_the(datab_clock));
aclr_datab <= aclr(select_the(datab_clear)) or not(devclrn) or not(devpor);
ena_datab <= ena(select_the(datab_clock));
datab_mac_reg : stratixgx_mac_register
generic map (data_width => datab_width)
port map (data => datab_tmp,
clk => clk_datab,
aclr => aclr_datab,
ena => ena_datab,
if_aclr => datab_if_clear,
dataout => scanoutb_tmp,
async => datab_async);
clk_signa <= clk(select_the(signa_clock));
aclr_signa <= aclr(select_the(signa_clear))or not(devclrn) or not(devpor);
ena_signa <= ena(select_the(signa_clock));
signa_mac_reg : stratixgx_mac_bit_register
port map (data => signa_tmp,
clk => clk_signa,
aclr => aclr_signa,
ena => ena_signa,
if_aclr => signa_if_clear,
dataout => signa_out,
async => signa_async);
clk_signb <= clk(select_the(signb_clock));
aclr_signb <= aclr(select_the(signb_clear))or not(devclrn) or not(devpor);
ena_signb <= ena(select_the(signb_clock));
signb_mac_reg : stratixgx_mac_bit_register
port map (data => signb_tmp,
clk => clk_signb,
aclr => aclr_signb,
ena => ena_signb,
if_aclr => signb_if_clear,
dataout => signb_out,
async => signb_async);
mac_multiply : stratixgx_mac_mult_internal
generic map (dataa_width => dataa_width,
datab_width => datab_width)
port map(dataa => scanouta_tmp(dataa_width-1 downto 0),
datab => scanoutb_tmp(datab_width-1 downto 0),
signa => signa_internally,
signb => signb_internally,
scanouta => scanouta,
scanoutb => scanoutb,
dataout => mult_output(dataa_width+datab_width-1 downto 0)
);
clk_dataout <= clk(select_the(output_clock));
aclr_dataout <= aclr(select_the(output_clear))or not(devclrn) or not(devpor);
ena_dataout <= ena(select_the(output_clock));
dataout_mac_reg : stratixgx_mac_register
generic map (data_width => (dataa_width+datab_width))
port map (data => mult_output,
clk => clk_dataout,
aclr => aclr_dataout,
ena => ena_dataout,
if_aclr => dataout_if_clear,
dataout => dataout_tmp,
async => dataout_async);
END mult_arch;
-- //////////////////////////////////////////////////////////////////////
-- //
-- // STRATIXGX_MAC_OUT
-- //
-- //////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use work.stratixgx_mac_register;
use work.stratixgx_mac_out_internal;
entity stratixgx_mac_out IS
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 36;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0) := (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratixgx_mac_out"
);
port
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector(3 downto 0) := "0000";
aclr : in std_logic_vector(3 downto 0) := "0000";
ena : in std_logic_vector(3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (dataout_width-1 downto 0);
accoverflow : out std_logic
);
function select_the(constant string_name : string)
return natural is
begin
if string_name = "0" then
return 0;
elsif string_name = "1" then
return 1;
elsif string_name = "2" then
return 2;
elsif string_name = "3" then
return 3;
else
return 0;
end if;
end select_the;
END stratixgx_mac_out;
ARCHITECTURE out_arch OF stratixgx_mac_out IS
component stratixgx_mac_bit_register
generic
(
tipd_data : VitalDelayType01:= DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC;
clk : IN std_logic;
aclr : IN std_logic;
if_aclr : IN std_logic ;
ena : IN std_logic;
async : IN std_logic;
dataout : OUT STD_LOGIC
);
end component;
component stratixgx_mac_register
generic
(
data_width : integer := 18;
tipd_data : VitalDelayArrayType01(71 downto 0):= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
port
(
data : IN STD_LOGIC_VECTOR (71 downto 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
ena : IN STD_LOGIC;
async : IN STD_LOGIC;
if_aclr: IN STD_LOGIC;
dataout : OUT STD_LOGIC_VECTOR (71 downto 0)
);
end component;
component stratixgx_mac_out_internal
GENERIC
(
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
dataout_width : integer := 72;
signa_clock : string := "none";
signb_clock : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(36*72 -1 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (OTHERS => DefPropDelay01);
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT
(
dataa : in std_logic_vector(dataa_width-1 downto 0) := (others => '0');
datab : in std_logic_vector(datab_width-1 downto 0) := (others => '0');
datac : in std_logic_vector(datac_width-1 downto 0) := (others => '0');
datad : in std_logic_vector(datad_width-1 downto 0) := (others => '0');
dataout_global : in std_logic_vector (dataout_width-1 downto 0)
:= (others => '0');
signx : in std_logic := '1';
signy : in std_logic := '1';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
zeroacc : in std_logic := '0';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
end component;
signal signa_pipe : std_logic;
signal signb_pipe : std_logic;
signal zeroacc_pipe : std_logic;
signal addnsub0_pipe : std_logic;
signal addnsub1_pipe : std_logic;
signal signa_out : std_logic;
signal signb_out : std_logic;
signal zeroacc_out : std_logic;
signal addnsub0_out : std_logic;
signal addnsub1_out : std_logic;
signal dataout_sig : std_logic_vector (71 downto 0);
signal accoverflow_sig : std_logic;
signal signa_async : std_logic := '1';
signal signb_async : std_logic := '1';
signal zeroacc_async : std_logic := '0';
signal addnsub0_async : std_logic := '1';
signal addnsub1_async : std_logic := '1';
signal dataout_async : std_logic := '0';
signal accoverflow_async : std_logic := '0';
signal signa_pipeline_async : std_logic := '0';
signal signb_pipeline_async : std_logic := '0';
signal zeroacc_pipeline_async : std_logic := '0';
signal addnsub0_pipeline_async : std_logic := '1';
signal addnsub1_pipeline_async : std_logic := '1';
signal dataout_tmp : std_logic_vector(71 downto 0);
signal clk_signa : std_logic;
signal aclr_signa : std_logic;
signal ena_signa : std_logic;
signal clk_signb : std_logic;
signal aclr_signb : std_logic;
signal ena_signb : std_logic;
signal clk_zeroacc : std_logic;
signal aclr_zeroacc : std_logic;
signal ena_zeroacc : std_logic;
signal clk_addnsub0 : std_logic;
signal aclr_addnsub0 : std_logic;
signal ena_addnsub0 : std_logic;
signal clk_addnsub1 : std_logic;
signal aclr_addnsub1 : std_logic;
signal ena_addnsub1 : std_logic;
signal clk_signa_pipeline : std_logic;
signal aclr_signa_pipeline : std_logic;
signal ena_signa_pipeline : std_logic;
signal clk_signb_pipeline : std_logic;
signal aclr_signb_pipeline : std_logic;
signal ena_signb_pipeline : std_logic;
signal clk_zeroacc_pipeline : std_logic;
signal aclr_zeroacc_pipeline : std_logic;
signal ena_zeroacc_pipeline : std_logic;
signal clk_addnsub0_pipeline : std_logic;
signal aclr_addnsub0_pipeline : std_logic;
signal ena_addnsub0_pipeline : std_logic;
signal clk_addnsub1_pipeline : std_logic;
signal aclr_addnsub1_pipeline : std_logic;
signal ena_addnsub1_pipeline : std_logic;
signal clk_dataout : std_logic;
signal aclr_dataout : std_logic;
signal ena_dataout : std_logic;
signal clk_accoverflow : std_logic;
signal aclr_accoverflow : std_logic;
signal ena_accoverflow : std_logic;
signal signa_if_clear : std_logic;
signal signb_if_clear : std_logic;
signal signa_pip_if_clear : std_logic;
signal signb_pip_if_clear : std_logic;
signal zeroacc_if_clear : std_logic;
signal zeroacc_pip_if_clear : std_logic;
signal addnsub0_if_clear : std_logic;
signal addnsub1_if_clear : std_logic;
signal addnsub0_pip_if_clear : std_logic;
signal addnsub1_pip_if_clear : std_logic;
signal accoverflow_if_clear : std_logic;
signal dataout_if_clear : std_logic;
signal accoverflow_tmp : std_logic;
signal signa_tmp : std_logic;
signal signb_tmp : std_logic;
signal addnsub0_tmp : std_logic;
signal addnsub1_tmp : std_logic;
signal zeroacc_tmp : std_logic;
BEGIN
signa_tmp <= signa ;
signb_tmp <= signb ;
addnsub0_tmp <= addnsub0 ;
addnsub1_tmp <= addnsub1 ;
zeroacc_tmp <= zeroacc ;
signa_async <= '1' when (signa_clock = "none" or signa_clear = "none") else '0';
signb_async <= '1' when (signb_clock = "none" or signb_clear = "none") else '0';
addnsub0_async <= '1' when
(addnsub0_clock = "none" or addnsub0_clear = "none") else '0';
addnsub1_async <= '1' when
(addnsub1_clock = "none" or addnsub1_clear = "none") else '0';
zeroacc_async <= '1' when
(zeroacc_clock = "none" or zeroacc_clear = "none") else '0';
signa_pipeline_async <= '1' when
(signa_pipeline_clock = "none" or signa_pipeline_clear = "none") else '0';
signb_pipeline_async <= '1' when
(signb_pipeline_clock = "none" or signb_pipeline_clear = "none") else '0';
addnsub0_pipeline_async <= '1' when
(addnsub0_pipeline_clock = "none" or addnsub0_pipeline_clear = "none") else '0';
addnsub1_pipeline_async <= '1' when
(addnsub1_pipeline_clock = "none" or addnsub1_pipeline_clear = "none") else '0';
zeroacc_pipeline_async <= '1' when
(zeroacc_pipeline_clock = "none" or zeroacc_pipeline_clear = "none") else '0';
dataout_async <= '1' when
(output_clock = "none" or output_clear = "none") else '0';
accoverflow_async <= '1' when
(output_clock = "none" or output_clear = "none") else '0';
clk_signa <= clk(select_the(signa_clock));
aclr_signa <= aclr(select_the(signa_clear));
ena_signa <= ena(select_the(signa_clock));
signa_if_clear <= '1' when (signa_clear /= "none") else '0';
signb_if_clear <= '1' when (signb_clear /= "none") else '0';
signa_pip_if_clear <= '1' when (signa_pipeline_clear /= "none") else '0';
signb_pip_if_clear <= '1' when (signb_pipeline_clear /= "none") else '0';
zeroacc_if_clear <= '1' when (zeroacc_clear /= "none") else '0';
zeroacc_pip_if_clear <= '1' when (zeroacc_pipeline_clear /= "none") else '0';
addnsub0_if_clear <= '1' when (addnsub0_clear /= "none") else '0';
addnsub0_pip_if_clear <= '1' when (addnsub0_pipeline_clear /= "none") else '0';
addnsub1_if_clear <= '1' when (addnsub1_clear /= "none") else '0';
addnsub1_pip_if_clear <= '1' when (addnsub1_pipeline_clear /= "none") else '0';
dataout_if_clear <='1' when (output_clear /= "none") else '0';
accoverflow_if_clear <='1' when (output_clear /= "none") else '0';
signa_mac_reg : stratixgx_mac_bit_register
port map (data => signa_tmp,
clk => clk_signa,
aclr => aclr_signa,
ena => ena_signa,
if_aclr => signa_if_clear,
dataout => signa_pipe,
async => signa_async);
clk_signb <= clk(select_the(signb_clock));
aclr_signb <= aclr(select_the(signb_clear)) or not(devclrn) or not(devpor) ;
ena_signb <= ena(select_the(signb_clock));
signb_mac_reg : stratixgx_mac_bit_register
port map (data => signb_tmp,
clk => clk_signb,
aclr => aclr_signb,
ena => ena_signb,
if_aclr => signb_if_clear,
dataout => signb_pipe,
async => signb_async);
clk_zeroacc <= clk(select_the(zeroacc_clock));
aclr_zeroacc <= aclr(select_the(zeroacc_clear)) or not(devclrn) or not(devpor);
ena_zeroacc <= ena(select_the(zeroacc_clock));
zeroacc_mac_reg : stratixgx_mac_bit_register
port map (data => zeroacc_tmp,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
ena => ena_zeroacc,
if_aclr => zeroacc_if_clear,
dataout => zeroacc_pipe,
async => zeroacc_async);
clk_addnsub0 <= clk(select_the(addnsub0_clock));
aclr_addnsub0 <= aclr(select_the(addnsub0_clear)) or not(devclrn) or not(devpor);
ena_addnsub0 <= ena(select_the(addnsub0_clock));
addnsub0_mac_reg : stratixgx_mac_bit_register
port map (data => addnsub0_tmp,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
ena => ena_addnsub0,
if_aclr => addnsub0_if_clear,
dataout => addnsub0_pipe,
async => addnsub0_async);
clk_addnsub1 <= clk(select_the(addnsub1_clock));
aclr_addnsub1 <= aclr(select_the(addnsub1_clear)) or not(devclrn) or not(devpor);
ena_addnsub1 <= ena(select_the(addnsub1_clock));
addnsub1_mac_reg : stratixgx_mac_bit_register
port map (data => addnsub1_tmp,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
ena => ena_addnsub1,
if_aclr => addnsub1_if_clear,
dataout => addnsub1_pipe,
async => addnsub1_async);
clk_signa_pipeline <= clk(select_the(signa_pipeline_clock));
aclr_signa_pipeline <= aclr(select_the(signa_pipeline_clear)) or not(devclrn) or not(devpor);
ena_signa_pipeline <= ena(select_the(signa_pipeline_clock));
signa_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
ena => ena_signa_pipeline,
if_aclr => signa_pip_if_clear,
dataout => signa_out,
async => signa_pipeline_async);
clk_signb_pipeline <= clk(select_the(signb_pipeline_clock));
aclr_signb_pipeline <= aclr(select_the(signb_pipeline_clear)) or not(devclrn) or not(devpor);
ena_signb_pipeline <= ena(select_the(signb_pipeline_clock));
signb_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
ena => ena_signb_pipeline,
if_aclr => signb_pip_if_clear,
dataout => signb_out,
async => signb_pipeline_async);
clk_zeroacc_pipeline <= clk(select_the(zeroacc_pipeline_clock));
aclr_zeroacc_pipeline <= aclr(select_the(zeroacc_pipeline_clear)) or not(devclrn) or not(devpor);
ena_zeroacc_pipeline <= ena(select_the(zeroacc_pipeline_clock));
zeroacc_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
if_aclr => zeroacc_pip_if_clear,
dataout => zeroacc_out,
async => zeroacc_pipeline_async);
clk_addnsub0_pipeline <= clk(select_the(addnsub0_pipeline_clock));
aclr_addnsub0_pipeline <= aclr(select_the(addnsub0_pipeline_clear)) or not(devclrn) or not(devpor);
ena_addnsub0_pipeline <= ena(select_the(addnsub0_pipeline_clock));
addnsub0_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
if_aclr => addnsub0_pip_if_clear,
dataout => addnsub0_out,
async => addnsub0_pipeline_async);
clk_addnsub1_pipeline <= clk(select_the(addnsub1_pipeline_clock));
aclr_addnsub1_pipeline <= aclr(select_the(addnsub1_pipeline_clear)) or not(devclrn) or not(devpor);
ena_addnsub1_pipeline <= ena(select_the(addnsub1_pipeline_clock));
addnsub1_mac_pipeline_reg : stratixgx_mac_bit_register
port map (data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
if_aclr => addnsub1_pip_if_clear,
dataout => addnsub1_out,
async => addnsub1_pipeline_async);
mac_adder : stratixgx_mac_out_internal
generic map (operation_mode => operation_mode,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
signa_clock => signa_clock,
signb_clock => signb_clock,
signa_clear => signa_clear,
signb_clear => signb_clear,
output_clock => output_clock,
output_clear => output_clear)
port map (dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
dataout_global => dataout_tmp(dataout_width-1 downto 0),
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
zeroacc => zeroacc_out,
dataout => dataout_sig,
accoverflow => accoverflow_sig
);
clk_dataout <= clk(select_the(output_clock));
aclr_dataout <= aclr(select_the(output_clear)) or not(devclrn) or not(devpor);
ena_dataout <= ena(select_the(output_clock));
dataout_out_reg : stratixgx_mac_register
generic map (data_width => 72)
port map (data => dataout_sig,
clk => clk_dataout,
aclr => aclr_dataout,
ena => ena_dataout,
if_aclr => dataout_if_clear,
dataout => dataout_tmp,
async => dataout_async);
clk_accoverflow <= clk(select_the(output_clock));
aclr_accoverflow <=aclr(select_the(output_clear)) or not(devclrn) or not(devpor);
ena_accoverflow <= ena(select_the(output_clock));
accoverflow_out_reg : stratixgx_mac_bit_register
port map (data => accoverflow_sig,
clk => clk_accoverflow,
aclr => aclr_accoverflow,
ena => ena_accoverflow,
if_aclr => accoverflow_if_clear,
dataout => accoverflow_tmp,
async => accoverflow_async);
dataout <= dataout_tmp(dataout'range) xor data_out_programmable_invert(dataout'range);
accoverflow <= accoverflow_tmp xor overflow_programmable_invert;
END out_arch;
----------------------------------------------------------------------------
-- Module Name : stratixgx_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
ENTITY stratixgx_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixgx_ram_register;
ARCHITECTURE reg_arch OF stratixgx_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixgx_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
ENTITY stratixgx_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixgx_ram_pulse_generator:ENTITY IS TRUE;
END stratixgx_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixgx_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
USE work.stratixgx_ram_register;
USE work.stratixgx_ram_pulse_generator;
ENTITY stratixgx_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
lpm_type : string := "stratixgx_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixgx_ram_block;
ARCHITECTURE block_arch OF stratixgx_ram_block IS
COMPONENT stratixgx_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixgx_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= ena0;
active_b_in <= ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : stratixgx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : stratixgx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixgx_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : stratixgx_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixgx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixgx_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : stratixgx_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : stratixgx_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixgx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixgx_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixgx_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : stratixgx_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : stratixgx_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixgx_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixgx_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_m_cntr
--
-- Description : Timing simulation model for the M counter. This is a
-- model for the loop feedback counter of the STRATIXGX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixgx_m_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0);
END stratixgx_m_cntr;
ARCHITECTURE behave of stratixgx_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_n_cntr
--
-- Description : Timing simulation model for the N counter. This is a
-- model for the input counter of the STRATIXGX PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixgx_n_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END stratixgx_n_cntr;
ARCHITECTURE behave of stratixgx_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on STRATIXGX PLL input clk. This edge will be ignored" severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge and (clk_last_valid_value /= clk)) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the L0, L1, G0, G1, G2, G3, E0,
-- E1, E2 and E3 output counters of the STRATIXGX PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixgx_scale_cntr is
PORT ( clk : IN std_logic;
reset : IN std_logic;
initial : IN integer;
high : IN integer;
low : IN integer;
mode : IN string := "bypass";
time_delay : IN integer;
ph_tap : IN natural;
cout : OUT std_logic);
END stratixgx_scale_cntr;
ARCHITECTURE behave of stratixgx_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 0;
variable first_rising_edge : boolean := false;
variable high_reg : integer := 0;
variable low_reg : integer := 0;
variable init : boolean := true;
variable high_cnt_xfer_done : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 0;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (init) then
init := false;
high_reg := high;
low_reg := low;
end if;
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
elsif (not first_rising_edge) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high_reg*2) + 1)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (mode = " odd" and (count = high_reg*2)) then
tmp_cout := '0';
if (high_cnt_xfer_done) then
low_reg := low;
high_cnt_xfer_done := false;
end if;
elsif (count = (high_reg + low_reg)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
if (high_reg /= high) then
high_cnt_xfer_done := true;
high_reg := high;
end if;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixgx_pll_reg is
PORT ( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic);
end stratixgx_pll_reg;
ARCHITECTURE behave of stratixgx_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_pll
--
-- Description : Timing simulation model for the STRATIXGX STRATIXGXGX PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixgx_atom_pack.all;
USE work.stratixgx_pllpack.all;
USE work.stratixgx_m_cntr;
USE work.stratixgx_n_cntr;
USE work.stratixgx_scale_cntr;
USE work.stratixgx_dffe;
USE work.stratixgx_pll_reg;
ENTITY stratixgx_pll is
GENERIC ( operation_mode : string := "normal";
qualify_conf_done : string := "off";
compensate_clock : string := "clk0";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
scan_chain : string := "long";
lpm_type : string := "stratixgx_pll";
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_time_delay : string := "0";
clk0_duty_cycle : integer := 50;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_time_delay : string := "0";
clk1_duty_cycle : integer := 50;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_time_delay : string := "0";
clk2_duty_cycle : integer := 50;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_time_delay : string := "0";
clk3_duty_cycle : integer := 50;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_time_delay : string := "0";
clk4_duty_cycle : integer := 50;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_time_delay : string := "0";
clk5_duty_cycle : integer := 50;
extclk0_multiply_by : integer := 1;
extclk0_divide_by : integer := 1;
extclk0_phase_shift : string := "0";
extclk0_time_delay : string := "0";
extclk0_duty_cycle : integer := 50;
extclk1_multiply_by : integer := 1;
extclk1_divide_by : integer := 1;
extclk1_phase_shift : string := "0";
extclk1_time_delay : string := "0";
extclk1_duty_cycle : integer := 50;
extclk2_multiply_by : integer := 1;
extclk2_divide_by : integer := 1;
extclk2_phase_shift : string := "0";
extclk2_time_delay : string := "0";
extclk2_duty_cycle : integer := 50;
extclk3_multiply_by : integer := 1;
extclk3_divide_by : integer := 1;
extclk3_phase_shift : string := "0";
extclk3_time_delay : string := "0";
extclk3_duty_cycle : integer := 50;
primary_clock : string := "inclk0";
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
valid_lock_multiplier : integer := 5;
invalid_lock_multiplier : integer := 5;
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
feedback_source : string := "extclk0";
bandwidth_type : string := "auto";
bandwidth : integer := 0;
spread_frequency : integer := 0;
down_spread : string := "0.0";
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
l0_high : integer := 1;
l0_low : integer := 1;
l0_initial : integer := 1;
l0_mode : string := "bypass";
l0_ph : integer := 0;
l0_time_delay : integer := 0;
l1_high : integer := 1;
l1_low : integer := 1;
l1_initial : integer := 1;
l1_mode : string := "bypass";
l1_ph : integer := 0;
l1_time_delay : integer := 0;
g0_high : integer := 1;
g0_low : integer := 1;
g0_initial : integer := 1;
g0_mode : string := "bypass";
g0_ph : integer := 0;
g0_time_delay : integer := 0;
g1_high : integer := 1;
g1_low : integer := 1;
g1_initial : integer := 1;
g1_mode : string := "bypass";
g1_ph : integer := 0;
g1_time_delay : integer := 0;
g2_high : integer := 1;
g2_low : integer := 1;
g2_initial : integer := 1;
g2_mode : string := "bypass";
g2_ph : integer := 0;
g2_time_delay : integer := 0;
g3_high : integer := 1;
g3_low : integer := 1;
g3_initial : integer := 1;
g3_mode : string := "bypass";
g3_ph : integer := 0;
g3_time_delay : integer := 0;
e0_high : integer := 1;
e0_low : integer := 1;
e0_initial : integer := 1;
e0_mode : string := "bypass";
e0_ph : integer := 0;
e0_time_delay : integer := 0;
e1_high : integer := 1;
e1_low : integer := 1;
e1_initial : integer := 1;
e1_mode : string := "bypass";
e1_ph : integer := 0;
e1_time_delay : integer := 0;
e2_high : integer := 1;
e2_low : integer := 1;
e2_initial : integer := 1;
e2_mode : string := "bypass";
e2_ph : integer := 0;
e2_time_delay : integer := 0;
e3_high : integer := 1;
e3_low : integer := 1;
e3_initial : integer := 1;
e3_mode : string := "bypass";
e3_ph : integer := 0;
e3_time_delay : integer := 0;
m_ph : integer := 0;
m_time_delay : integer := 0;
n_time_delay : integer := 0;
extclk0_counter : string := "e0";
extclk1_counter : string := "e1";
extclk2_counter : string := "e2";
extclk3_counter : string := "e3";
clk0_counter : string := "g0";
clk1_counter : string := "g1";
clk2_counter : string := "g2";
clk3_counter : string := "g3";
clk4_counter : string := "l0";
clk5_counter : string := "l1";
-- LVDS mode parameters
enable0_counter : string := "l0";
enable1_counter : string := "l0";
charge_pump_current : integer := 0;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 1;
common_rx_tx : string := "off";
rx_outclock_resource : string := "auto";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "timing";
source_is_pll : string := "off";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
extclk0_use_even_counter_mode : string := "off";
extclk1_use_even_counter_mode : string := "off";
extclk2_use_even_counter_mode : string := "off";
extclk3_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
extclk0_use_even_counter_value : string := "off";
extclk1_use_even_counter_value : string := "off";
extclk2_use_even_counter_value : string := "off";
extclk3_use_even_counter_value : string := "off";
scan_chain_mif_file : string := "";
-- Simulation only generics
family_name : string := "STRATIXGX";
skip_vco : string := "off";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkena : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_extclkena : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanaclr : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_comparator : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01
);
PORT ( inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
clkena : in std_logic_vector(5 downto 0) := "111111";
extclkena : in std_logic_vector(3 downto 0) := "1111";
scanaclr : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
clk : out std_logic_vector(5 downto 0);
extclk : out std_logic_vector(3 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
-- lvds specific ports
comparator : in std_logic := '0';
enable0 : out std_logic;
enable1 : out std_logic
);
END stratixgx_pll;
ARCHITECTURE vital_pll of stratixgx_pll is
-- internal advanced parameter signals
signal i_vco_min : natural;
signal i_vco_max : natural;
signal i_vco_center : natural;
signal i_pfd_min : natural;
signal i_pfd_max : natural;
signal l0_ph_val : natural;
signal l1_ph_val : natural;
signal g0_ph_val : natural;
signal g1_ph_val : natural;
signal g2_ph_val : natural;
signal g3_ph_val : natural;
signal e0_ph_val : natural;
signal e1_ph_val : natural;
signal e2_ph_val : natural;
signal e3_ph_val : natural;
signal i_extclk3_counter : string(1 to 2) := "e3";
signal i_extclk2_counter : string(1 to 2) := "e2";
signal i_extclk1_counter : string(1 to 2) := "e1";
signal i_extclk0_counter : string(1 to 2) := "e0";
signal i_clk5_counter : string(1 to 2) := "l1";
signal i_clk4_counter : string(1 to 2) := "l0";
signal i_clk3_counter : string(1 to 2) := "g3";
signal i_clk2_counter : string(1 to 2) := "g2";
signal i_clk1_counter : string(1 to 2) := "g1";
signal i_clk0_counter : string(1 to 2) := "g0";
signal i_charge_pump_current : natural;
signal i_loop_filter_r : natural;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT EGPP_SCAN_CHAIN : integer := 289;
CONSTANT GPP_SCAN_CHAIN : integer := 193;
CONSTANT TRST : time := 5000 ps;
CONSTANT TRSTCLK : time := 5000 ps;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal l0_clk : std_logic;
signal l1_clk : std_logic;
signal g0_clk : std_logic;
signal g1_clk : std_logic;
signal g2_clk : std_logic;
signal g3_clk : std_logic;
signal e0_clk : std_logic;
signal e1_clk : std_logic;
signal e2_clk : std_logic;
signal e3_clk : std_logic;
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal m_val_tmp : integer := 1;
signal m2_val : integer := 1;
signal n_val : integer := 1;
signal n_val_tmp : integer := 1;
signal n2_val : integer := 1;
signal m_time_delay_val, n_time_delay_val : integer := 0;
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal l0_initial_val : integer := l0_initial;
signal l1_initial_val : integer := l1_initial;
signal l0_high_val : integer := l0_high;
signal l1_high_val : integer := l1_high;
signal l0_low_val : integer := l0_low;
signal l1_low_val : integer := l1_low;
signal l0_mode_val : string(1 to 6) := "bypass";
signal l1_mode_val : string(1 to 6) := "bypass";
signal l0_time_delay_val : integer := l0_time_delay;
signal l1_time_delay_val : integer := l1_time_delay;
signal g0_initial_val : integer := g0_initial;
signal g1_initial_val : integer := g1_initial;
signal g2_initial_val : integer := g2_initial;
signal g3_initial_val : integer := g3_initial;
signal g0_high_val : integer := g0_high;
signal g1_high_val : integer := g1_high;
signal g2_high_val : integer := g2_high;
signal g3_high_val : integer := g3_high;
signal g0_mode_val : string(1 to 6) := "bypass";
signal g1_mode_val : string(1 to 6) := "bypass";
signal g2_mode_val : string(1 to 6) := "bypass";
signal g3_mode_val : string(1 to 6) := "bypass";
signal g0_low_val : integer := g0_low;
signal g1_low_val : integer := g1_low;
signal g2_low_val : integer := g2_low;
signal g3_low_val : integer := g3_low;
signal g0_time_delay_val : integer := g0_time_delay;
signal g1_time_delay_val : integer := g1_time_delay;
signal g2_time_delay_val : integer := g2_time_delay;
signal g3_time_delay_val : integer := g3_time_delay;
signal e0_initial_val : integer := e0_initial;
signal e1_initial_val : integer := e1_initial;
signal e2_initial_val : integer := e2_initial;
signal e3_initial_val : integer := e3_initial;
signal e0_high_val : integer := e0_high;
signal e1_high_val : integer := e1_high;
signal e2_high_val : integer := e2_high;
signal e3_high_val : integer := e3_high;
signal e0_low_val : integer := e0_low;
signal e1_low_val : integer := e1_low;
signal e2_low_val : integer := e2_low;
signal e3_low_val : integer := e3_low;
signal e0_time_delay_val : integer := e0_time_delay;
signal e1_time_delay_val : integer := e1_time_delay;
signal e2_time_delay_val : integer := e2_time_delay;
signal e3_time_delay_val : integer := e3_time_delay;
signal e0_mode_val : string(1 to 6) := "bypass";
signal e1_mode_val : string(1 to 6) := "bypass";
signal e2_mode_val : string(1 to 6) := "bypass";
signal e3_mode_val : string(1 to 6) := "bypass";
signal m_mode_val : string(1 to 6) := " ";
signal m2_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal n2_mode_val : string(1 to 6) := " ";
signal cntr_e0_initial : integer := 1;
signal cntr_e1_initial : integer := 1;
signal cntr_e2_initial : integer := 1;
signal cntr_e3_initial : integer := 1;
signal ext_fbk_delay : integer := 0;
signal cntr_e0_delay : integer := 0;
signal cntr_e1_delay : integer := 0;
signal cntr_e2_delay : integer := 0;
signal cntr_e3_delay : integer := 0;
signal transfer : std_logic := '0';
signal scan_data : std_logic_vector(288 downto 0) := (OTHERS => '0');
signal ena0 : std_logic;
signal ena1 : std_logic;
signal ena2 : std_logic;
signal ena3 : std_logic;
signal ena4 : std_logic;
signal ena5 : std_logic;
signal extena0 : std_logic;
signal extena1 : std_logic;
signal extena2 : std_logic;
signal extena3 : std_logic;
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal extclk0_tmp : std_logic;
signal extclk1_tmp : std_logic;
signal extclk2_tmp : std_logic;
signal extclk3_tmp : std_logic;
signal not_clk0_tmp : std_logic;
signal not_clk1_tmp : std_logic;
signal not_clk2_tmp : std_logic;
signal not_clk3_tmp : std_logic;
signal not_clk4_tmp : std_logic;
signal not_clk5_tmp : std_logic;
signal not_extclk0_tmp : std_logic;
signal not_extclk1_tmp : std_logic;
signal not_extclk2_tmp : std_logic;
signal not_extclk3_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal quiet_period_violation : boolean := false;
signal reconfig_err : boolean := false;
signal scanclr_violation : boolean := false;
signal scanclr_clk_violation : boolean := false;
signal inclk_l0 : std_logic;
signal inclk_l1 : std_logic;
signal inclk_g0 : std_logic;
signal inclk_g1 : std_logic;
signal inclk_g2 : std_logic;
signal inclk_g3 : std_logic;
signal inclk_e0 : std_logic;
signal inclk_e1 : std_logic;
signal inclk_e2 : std_logic;
signal inclk_e3 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal comparator_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal clkena0_ipd : std_logic;
signal clkena1_ipd : std_logic;
signal clkena2_ipd : std_logic;
signal clkena3_ipd : std_logic;
signal clkena4_ipd : std_logic;
signal clkena5_ipd : std_logic;
signal extclkena0_ipd : std_logic;
signal extclkena1_ipd : std_logic;
signal extclkena2_ipd : std_logic;
signal extclkena3_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanaclr_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal lvds_dffa_clk : std_logic;
signal lvds_dffb_clk : std_logic;
signal lvds_dffc_clk : std_logic;
signal lvds_dffd_clk : std_logic;
signal dffa_out : std_logic := '0';
signal dffb_out : std_logic := '0';
signal dffc_out : std_logic := '0';
signal dffd_out : std_logic := '0';
signal nce_temp : std_logic := '0';
signal nce_l0 : std_logic := '0';
signal nce_l1 : std_logic := '0';
signal inclk_l0_dly1 : std_logic := '0';
signal inclk_l0_dly2 : std_logic := '0';
signal inclk_l0_dly3 : std_logic := '0';
signal inclk_l0_dly4 : std_logic := '0';
signal inclk_l0_dly5 : std_logic := '0';
signal inclk_l0_dly6 : std_logic := '0';
signal inclk_l1_dly1 : std_logic := '0';
signal inclk_l1_dly2 : std_logic := '0';
signal inclk_l1_dly3 : std_logic := '0';
signal inclk_l1_dly4 : std_logic := '0';
signal inclk_l1_dly5 : std_logic := '0';
signal inclk_l1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal sig_current_clock : string(1 to 6);
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal sig_curr_clock : string(1 to 6) := primary_clock;
signal scan_chain_length : integer := GPP_SCAN_CHAIN;
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_delay : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "e0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal sdataout_trig : std_logic := '0';
signal sdataout_rst_trig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal done_with_param_calc : boolean := false;
COMPONENT stratixgx_m_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer;
time_delay : IN integer;
ph : IN integer := 0 );
END COMPONENT;
COMPONENT stratixgx_n_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
modulus : IN integer;
time_delay : IN integer);
END COMPONENT;
COMPONENT stratixgx_scale_cntr
PORT ( clk : IN std_logic;
reset : IN std_logic;
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
time_delay : IN integer := 0;
ph_tap : IN natural );
END COMPONENT;
COMPONENT stratixgx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixgx_pll_reg
PORT ( Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (clkena0_ipd, clkena(0), tipd_clkena(0));
VitalWireDelay (clkena1_ipd, clkena(1), tipd_clkena(1));
VitalWireDelay (clkena2_ipd, clkena(2), tipd_clkena(2));
VitalWireDelay (clkena3_ipd, clkena(3), tipd_clkena(3));
VitalWireDelay (clkena4_ipd, clkena(4), tipd_clkena(4));
VitalWireDelay (clkena5_ipd, clkena(5), tipd_clkena(5));
VitalWireDelay (extclkena0_ipd, extclkena(0), tipd_extclkena(0));
VitalWireDelay (extclkena1_ipd, extclkena(1), tipd_extclkena(1));
VitalWireDelay (extclkena2_ipd, extclkena(2), tipd_extclkena(2));
VitalWireDelay (extclkena3_ipd, extclkena(3), tipd_extclkena(3));
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanaclr_ipd, scanaclr, tipd_scanaclr);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (comparator_ipd, comparator, tipd_comparator);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
-- User to Advanced parameter conversion
i_extclk3_counter <= "e3" when m=0 else extclk3_counter;
i_extclk2_counter <= "e2" when m=0 else extclk2_counter;
i_extclk1_counter <= "e1" when m=0 else extclk1_counter;
i_extclk0_counter <= "e0" when m=0 else extclk0_counter;
i_clk5_counter <= "l1" when m=0 else clk5_counter;
i_clk4_counter <= "l0" when m=0 else clk4_counter;
i_clk3_counter <= "g3" when m=0 else clk3_counter;
i_clk2_counter <= "g2" when m=0 else clk2_counter;
i_clk1_counter <= "g1" when m=0 else clk1_counter;
i_clk0_counter <= "l0" when m=0 and pll_type = "lvds" else
"g0" when m=0 else clk0_counter;
-- end parameter conversion
inclk_m <= extclk0_tmp when operation_mode = "external_feedback" and feedback_source = "extclk0" else
extclk1_tmp when operation_mode = "external_feedback" and feedback_source = "extclk1" else
extclk2_tmp when operation_mode = "external_feedback" and feedback_source = "extclk2" else
extclk3_tmp when operation_mode = "external_feedback" and feedback_source = "extclk3" else
vco_out(m_ph_val);
ext_fbk_cntr <= "e0" when (feedback_source = "extclk0" and extclk0_counter = "e0") or (feedback_source = "extclk1" and extclk1_counter = "e0") or (feedback_source = "extclk2" and extclk2_counter = "e0") or (feedback_source = "extclk3" and extclk3_counter = "e0") else
"e1" when (feedback_source = "extclk0" and extclk0_counter = "e1") or (feedback_source = "extclk1" and extclk1_counter = "e1") or (feedback_source = "extclk2" and extclk2_counter = "e1") or (feedback_source = "extclk3" and extclk3_counter = "e1") else
"e2" when (feedback_source = "extclk0" and extclk0_counter = "e2") or (feedback_source = "extclk1" and extclk1_counter = "e2") or (feedback_source = "extclk2" and extclk2_counter = "e2") or (feedback_source = "extclk3" and extclk3_counter = "e2") else
"e3" when (feedback_source = "extclk0" and extclk0_counter = "e3") or (feedback_source = "extclk1" and extclk1_counter = "e3") or (feedback_source = "extclk2" and extclk2_counter = "e3") or (feedback_source = "extclk3" and extclk3_counter = "e3") else
"e0";
ext_fbk_cntr_high <= e0_high_val when ext_fbk_cntr = "e0" else
e1_high_val when ext_fbk_cntr = "e1" else
e2_high_val when ext_fbk_cntr = "e2" else
e3_high_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_low <= e0_low_val when ext_fbk_cntr = "e0" else
e1_low_val when ext_fbk_cntr = "e1" else
e2_low_val when ext_fbk_cntr = "e2" else
e3_low_val when ext_fbk_cntr = "e3" else
1;
ext_fbk_cntr_delay <= e0_time_delay_val when ext_fbk_cntr = "e0" else
e1_time_delay_val when ext_fbk_cntr = "e1" else
e2_time_delay_val when ext_fbk_cntr = "e2" else
e3_time_delay_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_ph <= e0_ph_val when ext_fbk_cntr = "e0" else
e1_ph_val when ext_fbk_cntr = "e1" else
e2_ph_val when ext_fbk_cntr = "e2" else
e3_ph_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_initial <= e0_initial_val when ext_fbk_cntr = "e0" else
e1_initial_val when ext_fbk_cntr = "e1" else
e2_initial_val when ext_fbk_cntr = "e2" else
e3_initial_val when ext_fbk_cntr = "e3" else
0;
ext_fbk_cntr_mode <= e0_mode_val when ext_fbk_cntr = "e0" else
e1_mode_val when ext_fbk_cntr = "e1" else
e2_mode_val when ext_fbk_cntr = "e2" else
e3_mode_val when ext_fbk_cntr = "e3" else
e0_mode_val;
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
m1 : stratixgx_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay,
ph => m_ph_val );
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
n1 : stratixgx_n_cntr
port map ( clk => clkin,
reset => areset_ipd,
cout => refclk,
modulus => n_val,
time_delay => n_time_delay_val);
inclk_l0 <= vco_out(l0_ph_val);
l0 : stratixgx_scale_cntr
port map ( clk => inclk_l0,
reset => areset_ena_sig,
cout => l0_clk,
initial => l0_initial_val,
high => l0_high_val,
low => l0_low_val,
mode => l0_mode_val,
time_delay => l0_time_delay_val,
ph_tap => l0_ph_val);
inclk_l1 <= vco_out(l1_ph_val);
l1 : stratixgx_scale_cntr
port map ( clk => inclk_l1,
reset => areset_ena_sig,
cout => l1_clk,
initial => l1_initial_val,
high => l1_high_val,
low => l1_low_val,
mode => l1_mode_val,
time_delay => l1_time_delay_val,
ph_tap => l1_ph_val);
inclk_g0 <= vco_out(g0_ph_val);
g0 : stratixgx_scale_cntr
port map ( clk => inclk_g0,
reset => areset_ena_sig,
cout => g0_clk,
initial => g0_initial_val,
high => g0_high_val,
low => g0_low_val,
mode => g0_mode_val,
time_delay => g0_time_delay_val,
ph_tap => g0_ph_val);
process(g0_clk, l0_clk, l1_clk)
begin
if (g0_clk'event and g0_clk = '1') then
dffa_out <= comparator_ipd;
end if;
if (l0_clk'event and l0_clk = '1' and enable0_counter = "l0") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
if (l1_clk'event and l1_clk = '1' and enable0_counter = "l1") then
dffb_out <= dffa_out;
dffc_out <= dffb_out;
dffd_out <= nce_temp;
end if;
end process;
nce_temp <= (not dffc_out) and dffb_out;
nce_l0 <= dffd_out when enable0_counter = "l0" else '0';
nce_l1 <= dffd_out when enable0_counter = "l1" else '0';
inclk_g1 <= vco_out(g1_ph_val);
g1 : stratixgx_scale_cntr
port map ( clk => inclk_g1,
reset => areset_ena_sig,
cout => g1_clk,
initial => g1_initial_val,
high => g1_high_val,
low => g1_low_val,
mode => g1_mode_val,
time_delay => g1_time_delay_val,
ph_tap => g1_ph_val);
inclk_g2 <= vco_out(g2_ph_val);
g2 : stratixgx_scale_cntr
port map ( clk => inclk_g2,
reset => areset_ena_sig,
cout => g2_clk,
initial => g2_initial_val,
high => g2_high_val,
low => g2_low_val,
mode => g2_mode_val,
time_delay => g2_time_delay_val,
ph_tap => g2_ph_val);
inclk_g3 <= vco_out(g3_ph_val);
g3 : stratixgx_scale_cntr
port map ( clk => inclk_g3,
reset => areset_ena_sig,
cout => g3_clk,
initial => g3_initial_val,
high => g3_high_val,
low => g3_low_val,
mode => g3_mode_val,
time_delay => g3_time_delay_val,
ph_tap => g3_ph_val);
inclk_e0 <= vco_out(e0_ph_val);
cntr_e0_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else e0_initial_val;
cntr_e0_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e0" else
e0_time_delay_val;
e0 : stratixgx_scale_cntr
port map ( clk => inclk_e0,
reset => areset_ena_sig,
cout => e0_clk,
initial => cntr_e0_initial,
high => e0_high_val,
low => e0_low_val,
mode => e0_mode_val,
time_delay => cntr_e0_delay,
ph_tap => e0_ph_val);
inclk_e1 <= vco_out(e1_ph_val);
cntr_e1_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else e1_initial_val;
cntr_e1_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e1" else
e1_time_delay_val;
e1 : stratixgx_scale_cntr
port map ( clk => inclk_e1,
reset => areset_ena_sig,
cout => e1_clk,
initial => cntr_e1_initial,
high => e1_high_val,
low => e1_low_val,
mode => e1_mode_val,
time_delay => cntr_e1_delay,
ph_tap => e1_ph_val);
inclk_e2 <= vco_out(e2_ph_val);
cntr_e2_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else e2_initial_val;
cntr_e2_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e2" else
e2_time_delay_val;
e2 : stratixgx_scale_cntr
port map ( clk => inclk_e2,
reset => areset_ena_sig,
cout => e2_clk,
initial => cntr_e2_initial,
high => e2_high_val,
low => e2_low_val,
mode => e2_mode_val,
time_delay => cntr_e2_delay,
ph_tap => e2_ph_val);
inclk_e3 <= vco_out(e3_ph_val);
cntr_e3_initial <= 1 when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else e3_initial_val;
cntr_e3_delay <= ext_fbk_delay when operation_mode = "external_feedback" and
ext_fbk_cntr = "e3" else
e3_time_delay_val;
e3 : stratixgx_scale_cntr
port map ( clk => inclk_e3,
reset => areset_ena_sig,
cout => e3_clk,
initial => cntr_e3_initial,
high => e3_high_val,
low => e3_low_val,
mode => e3_mode_val,
time_delay => cntr_e3_delay,
ph_tap => e3_ph_val);
inclk_l0_dly1 <= inclk_l0;
inclk_l0_dly2 <= inclk_l0_dly1;
inclk_l0_dly3 <= inclk_l0_dly2;
inclk_l0_dly4 <= inclk_l0_dly3;
inclk_l0_dly5 <= inclk_l0_dly4;
inclk_l0_dly6 <= inclk_l0_dly5;
inclk_l1_dly1 <= inclk_l1;
inclk_l1_dly2 <= inclk_l1_dly1;
inclk_l1_dly3 <= inclk_l1_dly2;
inclk_l1_dly4 <= inclk_l1_dly3;
inclk_l1_dly5 <= inclk_l1_dly4;
inclk_l1_dly6 <= inclk_l1_dly5;
process(inclk_l0_dly6, inclk_l1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable l0_got_first_rising_edge : boolean := false;
variable l0_count : integer := 1;
variable l0_tmp, l1_tmp : std_logic := '0';
variable l1_got_first_rising_edge : boolean := false;
variable l1_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
l0_count := 1;
l1_count := 1;
l0_got_first_rising_edge := false;
l1_got_first_rising_edge := false;
else
if (nce_l0 = '0') then
if (not l0_got_first_rising_edge) then
if (inclk_l0_dly6'event and inclk_l0_dly6 = '1') then
l0_got_first_rising_edge := true;
end if;
elsif (inclk_l0_dly6'event) then
l0_count := l0_count + 1;
if (l0_count = (l0_high_val + l0_low_val) * 2) then
l0_count := 1;
end if;
end if;
end if;
if (inclk_l0_dly6'event and inclk_l0_dly6 = '0') then
if (l0_count = 1) then
l0_tmp := '1';
l0_got_first_rising_edge := false;
else
l0_tmp := '0';
end if;
end if;
if (nce_l1 = '0') then
if (not l1_got_first_rising_edge) then
if (inclk_l1_dly6'event and inclk_l1_dly6 = '1') then
l1_got_first_rising_edge := true;
end if;
elsif (inclk_l1_dly6'event) then
l1_count := l1_count + 1;
if (l1_count = (l1_high_val + l1_low_val) * 2) then
l1_count := 1;
end if;
end if;
end if;
if (inclk_l1_dly6'event and inclk_l1_dly6 = '0') then
if (l1_count = 1) then
l1_tmp := '1';
l1_got_first_rising_edge := false;
else
l1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "l0") then
enable0_tmp <= l0_tmp;
elsif (enable0_counter = "l1") then
enable0_tmp <= l1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "l0") then
enable1_tmp <= l0_tmp;
elsif (enable1_counter = "l1") then
enable1_tmp <= l1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (count = gate_lock_counter) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (transfer)
variable init : boolean := true;
variable low, high : std_logic_vector(8 downto 0);
variable delay_chain : std_logic_vector(3 downto 0);
variable mn_delay_chain : std_logic_vector(0 to 3);
variable mode : string(1 to 6) := "bypass";
variable delay_val : integer := 0;
variable is_error : boolean := false;
variable buf : line;
-- user to advanced variables
variable i_m_initial : natural;
variable i_m : integer := 1;
variable i_n : natural := 1;
variable i_m2 : natural;
variable i_n2 : natural;
variable i_ss : natural;
variable i_l0_high : natural;
variable i_l1_high : natural;
variable i_g0_high : natural;
variable i_g1_high : natural;
variable i_g2_high : natural;
variable i_g3_high : natural;
variable i_e0_high : natural;
variable i_e1_high : natural;
variable i_e2_high : natural;
variable i_e3_high : natural;
variable i_l0_low : natural;
variable i_l1_low : natural;
variable i_g0_low : natural;
variable i_g1_low : natural;
variable i_g2_low : natural;
variable i_g3_low : natural;
variable i_e0_low : natural;
variable i_e1_low : natural;
variable i_e2_low : natural;
variable i_e3_low : natural;
variable i_l0_initial : natural;
variable i_l1_initial : natural;
variable i_g0_initial : natural;
variable i_g1_initial : natural;
variable i_g2_initial : natural;
variable i_g3_initial : natural;
variable i_e0_initial : natural;
variable i_e1_initial : natural;
variable i_e2_initial : natural;
variable i_e3_initial : natural;
variable i_l0_mode : string(1 to 6);
variable i_l1_mode : string(1 to 6);
variable i_g0_mode : string(1 to 6);
variable i_g1_mode : string(1 to 6);
variable i_g2_mode : string(1 to 6);
variable i_g3_mode : string(1 to 6);
variable i_e0_mode : string(1 to 6);
variable i_e1_mode : string(1 to 6);
variable i_e2_mode : string(1 to 6);
variable i_e3_mode : string(1 to 6);
variable max_neg_abs : integer := 0;
variable i_l0_time_delay : natural;
variable i_l1_time_delay : natural;
variable i_g0_time_delay : natural;
variable i_g1_time_delay : natural;
variable i_g2_time_delay : natural;
variable i_g3_time_delay : natural;
variable i_e0_time_delay : natural;
variable i_e1_time_delay : natural;
variable i_e2_time_delay : natural;
variable i_e3_time_delay : natural;
variable i_m_time_delay : natural;
variable i_n_time_delay : natural;
variable i_l0_ph : natural;
variable i_l1_ph : natural;
variable i_g0_ph : natural;
variable i_g1_ph : natural;
variable i_g2_ph : natural;
variable i_g3_ph : natural;
variable i_e0_ph : natural;
variable i_e1_ph : natural;
variable i_e2_ph : natural;
variable i_e3_ph : natural;
variable i_m_ph : natural;
variable output_count : natural;
variable new_divisor : natural;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_extclk0_mult_by : integer := 1;
variable i_extclk0_div_by : integer := 1;
variable i_extclk1_mult_by : integer := 1;
variable i_extclk1_div_by : integer := 1;
variable i_extclk2_mult_by : integer := 1;
variable i_extclk2_div_by : integer := 1;
variable i_extclk3_mult_by : integer := 1;
variable i_extclk3_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
begin
if (init) then
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(extclk0_multiply_by, extclk0_divide_by,
max_d_value, i_extclk0_mult_by, i_extclk0_div_by);
find_simple_integer_fraction(extclk1_multiply_by, extclk1_divide_by,
max_d_value, i_extclk1_mult_by, i_extclk1_div_by);
find_simple_integer_fraction(extclk2_multiply_by, extclk2_divide_by,
max_d_value, i_extclk2_mult_by, i_extclk2_div_by);
find_simple_integer_fraction(extclk3_multiply_by, extclk3_divide_by,
max_d_value, i_extclk3_mult_by, i_extclk3_div_by);
i_n := 1;
if (pll_type = "lvds") then
i_m := clk0_multiply_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
i_extclk0_mult_by,
i_extclk1_mult_by, i_extclk2_mult_by,
i_extclk3_mult_by, inclk0_input_frequency);
end if;
i_m_time_delay := maxnegabs ( str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
i_n_time_delay := mintimedelay(str2int(clk0_time_delay),
str2int(clk1_time_delay),
str2int(clk2_time_delay),
str2int(clk3_time_delay),
str2int(clk4_time_delay),
str2int(clk5_time_delay),
str2int(extclk0_time_delay),
str2int(extclk1_time_delay),
str2int(extclk2_time_delay),
str2int(extclk3_time_delay));
if (pll_type = "lvds") then
i_g0_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
else
i_g0_time_delay := counter_time_delay ( str2int(clk0_time_delay),
i_m_time_delay,i_n_time_delay);
end if;
i_g1_time_delay := counter_time_delay ( str2int(clk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_g2_time_delay := counter_time_delay ( str2int(clk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_g3_time_delay := counter_time_delay ( str2int(clk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "lvds") then
i_l0_time_delay := i_g0_time_delay;
i_l1_time_delay := i_g0_time_delay;
else
i_l0_time_delay := counter_time_delay ( str2int(clk4_time_delay),
i_m_time_delay, i_n_time_delay);
i_l1_time_delay := counter_time_delay ( str2int(clk5_time_delay),
i_m_time_delay, i_n_time_delay);
end if;
i_e0_time_delay := counter_time_delay ( str2int(extclk0_time_delay),
i_m_time_delay, i_n_time_delay);
i_e1_time_delay := counter_time_delay ( str2int(extclk1_time_delay),
i_m_time_delay, i_n_time_delay);
i_e2_time_delay := counter_time_delay ( str2int(extclk2_time_delay),
i_m_time_delay, i_n_time_delay);
i_e3_time_delay := counter_time_delay ( str2int(extclk3_time_delay),
i_m_time_delay, i_n_time_delay);
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(extclk0_phase_shift),
str2int(extclk1_phase_shift),
str2int(extclk2_phase_shift),
str2int(extclk3_phase_shift));
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
else
i_g0_ph := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_g1_ph := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g2_ph := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_g3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_ph := i_g0_ph;
i_l1_ph := i_g0_ph;
else
i_l0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_l1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
end if;
i_e0_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e1_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e2_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_e3_ph := counter_ph(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_high := counter_high ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_high := counter_high ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_high := counter_high ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_high := counter_high ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_high := i_g0_high;
i_l1_high := i_g0_high;
else
i_l0_high := counter_high ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_high := counter_high ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_high := counter_high ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_high := counter_high ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_high := counter_high ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_high := counter_high ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
if (pll_type = "lvds") then
i_g0_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
else
i_g0_low := counter_low ( output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
end if;
i_g1_low := counter_low ( output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_g2_low := counter_low ( output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_g3_low := counter_low ( output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
if (pll_type = "lvds") then
i_l0_low := i_g0_low;
i_l1_low := i_g0_low;
else
i_l0_low := counter_low ( output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_l1_low := counter_low ( output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
end if;
i_e0_low := counter_low ( output_counter_value(i_extclk0_div_by,
i_extclk0_mult_by, i_m, i_n), extclk0_duty_cycle);
i_e1_low := counter_low ( output_counter_value(i_extclk1_div_by,
i_extclk1_mult_by, i_m, i_n), extclk1_duty_cycle);
i_e2_low := counter_low ( output_counter_value(i_extclk2_div_by,
i_extclk2_mult_by, i_m, i_n), extclk2_duty_cycle);
i_e3_low := counter_low ( output_counter_value(i_extclk3_div_by,
i_extclk3_mult_by, i_m, i_n), extclk3_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
if (pll_type = "lvds") then
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
else
i_g0_initial := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_g1_initial := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g2_initial := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_g3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_l0_initial := i_g0_initial;
i_l1_initial := i_g0_initial;
else
i_l0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_l1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
end if;
i_e0_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk0_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e1_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk1_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e2_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk2_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_e3_initial := counter_initial(get_phase_degree(ph_adjust(str2int(extclk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
if (pll_type = "lvds") then
i_g0_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
else
i_g0_mode := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
end if;
i_g1_mode := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_g2_mode := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_g3_mode := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
if (pll_type = "lvds") then
i_l0_mode := "bypass";
i_l1_mode := "bypass";
else
i_l0_mode := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_l1_mode := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
end if;
i_e0_mode := counter_mode(extclk0_duty_cycle, output_counter_value(i_extclk0_div_by, i_extclk0_mult_by, i_m, i_n));
i_e1_mode := counter_mode(extclk1_duty_cycle, output_counter_value(i_extclk1_div_by, i_extclk1_mult_by, i_m, i_n));
i_e2_mode := counter_mode(extclk2_duty_cycle, output_counter_value(i_extclk2_div_by, i_extclk2_mult_by, i_m, i_n));
i_e3_mode := counter_mode(extclk3_duty_cycle, output_counter_value(i_extclk3_div_by, i_extclk3_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (feedback_source = "extclk0") then
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
elsif (feedback_source = "extclk1") then
if (i_e1_mode = "bypass") then
output_count := 1;
else
output_count := i_e1_high + i_e1_low;
end if;
elsif (feedback_source = "extclk2") then
if (i_e2_mode = "bypass") then
output_count := 1;
else
output_count := i_e2_high + i_e2_low;
end if;
elsif (feedback_source = "extclk3") then
if (i_e3_mode = "bypass") then
output_count := 1;
else
output_count := i_e3_high + i_e3_low;
end if;
else -- default to e0
if (i_e0_mode = "bypass") then
output_count := 1;
else
output_count := i_e0_high + i_e0_low;
end if;
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_time_delay := m_time_delay;
i_n_time_delay := n_time_delay;
i_l0_time_delay := l0_time_delay;
i_l1_time_delay := l1_time_delay;
i_g0_time_delay := g0_time_delay;
i_g1_time_delay := g1_time_delay;
i_g2_time_delay := g2_time_delay;
i_g3_time_delay := g3_time_delay;
i_e0_time_delay := e0_time_delay;
i_e1_time_delay := e1_time_delay;
i_e2_time_delay := e2_time_delay;
i_e3_time_delay := e3_time_delay;
i_m_ph := m_ph;
i_l0_ph := l0_ph;
i_l1_ph := l1_ph;
i_g0_ph := g0_ph;
i_g1_ph := g1_ph;
i_g2_ph := g2_ph;
i_g3_ph := g3_ph;
i_e0_ph := e0_ph;
i_e1_ph := e1_ph;
i_e2_ph := e2_ph;
i_e3_ph := e3_ph;
i_l0_high := l0_high;
i_l1_high := l1_high;
i_g0_high := g0_high;
i_g1_high := g1_high;
i_g2_high := g2_high;
i_g3_high := g3_high;
i_e0_high := e0_high;
i_e1_high := e1_high;
i_e2_high := e2_high;
i_e3_high := e3_high;
i_l0_low := l0_low;
i_l1_low := l1_low;
i_g0_low := g0_low;
i_g1_low := g1_low;
i_g2_low := g2_low;
i_g3_low := g3_low;
i_e0_low := e0_low;
i_e1_low := e1_low;
i_e2_low := e2_low;
i_e3_low := e3_low;
i_l0_initial := l0_initial;
i_l1_initial := l1_initial;
i_g0_initial := g0_initial;
i_g1_initial := g1_initial;
i_g2_initial := g2_initial;
i_g3_initial := g3_initial;
i_e0_initial := e0_initial;
i_e1_initial := e1_initial;
i_e2_initial := e2_initial;
i_e3_initial := e3_initial;
i_l0_mode := translate_string(l0_mode);
i_l1_mode := translate_string(l1_mode);
i_g0_mode := translate_string(g0_mode);
i_g1_mode := translate_string(g1_mode);
i_g2_mode := translate_string(g2_mode);
i_g3_mode := translate_string(g3_mode);
i_e0_mode := translate_string(e0_mode);
i_e1_mode := translate_string(e1_mode);
i_e2_mode := translate_string(e2_mode);
i_e3_mode := translate_string(e3_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val_tmp <= i_n;
m_val_tmp <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
end if;
-- NOTE: m_time_delay (vco time delay) not supported for external
-- feedback mode
-- in feedback mode, m_time_delay = delay of feedback loop tap
m_time_delay_val <= i_m_time_delay;
n_time_delay_val <= i_n_time_delay;
m_ph_val <= i_m_ph;
m2_val <= m2;
n2_val <= n2;
if (m2 = 1) then
m2_mode_val <= "bypass";
end if;
if (n2 = 1) then
n2_mode_val <= "bypass";
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
m_initial_val <= 1;
m_time_delay_val <= 0;
m_ph_val <= 0;
end if;
l0_ph_val <= i_l0_ph;
l1_ph_val <= i_l1_ph;
g0_ph_val <= i_g0_ph;
g1_ph_val <= i_g1_ph;
g2_ph_val <= i_g2_ph;
g3_ph_val <= i_g3_ph;
e0_ph_val <= i_e0_ph;
e1_ph_val <= i_e1_ph;
e2_ph_val <= i_e2_ph;
e3_ph_val <= i_e3_ph;
l0_initial_val <= i_l0_initial;
l0_high_val <= i_l0_high;
l0_low_val <= i_l0_low;
l0_mode_val <= i_l0_mode;
l0_time_delay_val <= i_l0_time_delay;
l1_initial_val <= i_l1_initial;
l1_high_val <= i_l1_high;
l1_low_val <= i_l1_low;
l1_mode_val <= i_l1_mode;
l1_time_delay_val <= i_l1_time_delay;
g0_initial_val <= i_g0_initial;
g0_high_val <= i_g0_high;
g0_low_val <= i_g0_low;
g0_mode_val <= i_g0_mode;
g0_time_delay_val <= i_g0_time_delay;
g1_initial_val <= i_g1_initial;
g1_high_val <= i_g1_high;
g1_low_val <= i_g1_low;
g1_mode_val <= i_g1_mode;
g1_time_delay_val <= i_g1_time_delay;
g2_initial_val <= i_g2_initial;
g2_high_val <= i_g2_high;
g2_low_val <= i_g2_low;
g2_mode_val <= i_g2_mode;
g2_time_delay_val <= i_g2_time_delay;
g3_initial_val <= i_g3_initial;
g3_high_val <= i_g3_high;
g3_low_val <= i_g3_low;
g3_mode_val <= i_g3_mode;
g3_time_delay_val <= i_g3_time_delay;
if (scan_chain = "long") then
e0_initial_val <= i_e0_initial;
e0_high_val <= i_e0_high;
e0_low_val <= i_e0_low;
e0_mode_val <= i_e0_mode;
e0_time_delay_val <= i_e0_time_delay;
e1_initial_val <= i_e1_initial;
e1_high_val <= i_e1_high;
e1_low_val <= i_e1_low;
e1_mode_val <= i_e1_mode;
e1_time_delay_val <= i_e1_time_delay;
e2_initial_val <= i_e2_initial;
e2_high_val <= i_e2_high;
e2_low_val <= i_e2_low;
e2_mode_val <= i_e2_mode;
e2_time_delay_val <= i_e2_time_delay;
e3_initial_val <= i_e3_initial;
e3_high_val <= i_e3_high;
e3_low_val <= i_e3_low;
e3_mode_val <= i_e3_mode;
e3_time_delay_val <= i_e3_time_delay;
scan_chain_length <= EGPP_SCAN_CHAIN;
end if;
init := false;
done_with_param_calc <= true;
elsif (transfer'event and transfer = '1') then
reconfig_err <= false;
ASSERT false REPORT "Reconfiguring PLL" severity note;
if (scan_chain = "long") then
-- cntr e3
delay_chain := scan_data(287 downto 284);
if (scan_data(273) = '1') then
e3_mode_val <= "bypass";
if (scan_data(283) = '1') then
e3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(283) = '1') then
e3_mode_val <= " odd";
else
e3_mode_val <= " even";
end if;
high := scan_data(272 downto 264);
low := scan_data(282 downto 274);
e3_low_val <= alt_conv_integer(low);
e3_high_val <= alt_conv_integer(high);
-- count value of 0 is actually 512
if (alt_conv_integer(high) = 0) then
e3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e3_time_delay_val <= delay_val;
-- cntr e2
delay_chain := scan_data(263 downto 260);
if (scan_data(249) = '1') then
e2_mode_val <= "bypass";
if (scan_data(259) = '1') then
e2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(259) = '1') then
e2_mode_val <= " odd";
else
e2_mode_val <= " even";
end if;
high := scan_data(248 downto 240);
low := scan_data(258 downto 250);
e2_low_val <= alt_conv_integer(low);
e2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e2_time_delay_val <= delay_val;
-- cntr e1
delay_chain := scan_data(239 downto 236);
if (scan_data(225) = '1') then
e1_mode_val <= "bypass";
if (scan_data(235) = '1') then
e1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(235) = '1') then
e1_mode_val <= " odd";
else
e1_mode_val <= " even";
end if;
high := scan_data(224 downto 216);
low := scan_data(234 downto 226);
e1_low_val <= alt_conv_integer(low);
e1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e1_time_delay_val <= delay_val;
-- cntr e0
delay_chain := scan_data(215 downto 212);
if (scan_data(201) = '1') then
e0_mode_val <= "bypass";
if (scan_data(211) = '1') then
e0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the E0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(211) = '1') then
e0_mode_val <= " odd";
else
e0_mode_val <= " even";
end if;
high := scan_data(200 downto 192);
low := scan_data(210 downto 202);
e0_low_val <= alt_conv_integer(low);
e0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
e0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
e0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
e0_time_delay_val <= delay_val;
end if;
-- cntr l1
delay_chain := scan_data(191 downto 188);
if (scan_data(177) = '1') then
l1_mode_val <= "bypass";
if (scan_data(187) = '1') then
l1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(187) = '1') then
l1_mode_val <= " odd";
else
l1_mode_val <= " even";
end if;
high := scan_data(176 downto 168);
low := scan_data(186 downto 178);
l1_low_val <= alt_conv_integer(low);
l1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l1_time_delay_val <= delay_val;
-- cntr l0
delay_chain := scan_data(167 downto 164);
if (scan_data(153) = '1') then
l0_mode_val <= "bypass";
if (scan_data(163) = '1') then
l0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the L0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(163) = '1') then
l0_mode_val <= " odd";
else
l0_mode_val <= " even";
end if;
high := scan_data(152 downto 144);
low := scan_data(162 downto 154);
l0_low_val <= alt_conv_integer(low);
l0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
l0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
l0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
l0_time_delay_val <= delay_val;
-- cntr g3
delay_chain := scan_data(143 downto 140);
if (scan_data(129) = '1') then
g3_mode_val <= "bypass";
if (scan_data(139) = '1') then
g3_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G3 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(139) = '1') then
g3_mode_val <= " odd";
else
g3_mode_val <= " even";
end if;
high := scan_data(128 downto 120);
low := scan_data(138 downto 130);
g3_low_val <= alt_conv_integer(low);
g3_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g3_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g3_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g3_time_delay_val <= delay_val;
-- cntr g2
delay_chain := scan_data(119 downto 116);
if (scan_data(105) = '1') then
g2_mode_val <= "bypass";
if (scan_data(115) = '1') then
g2_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G2 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(115) = '1') then
g2_mode_val <= " odd";
else
g2_mode_val <= " even";
end if;
high := scan_data(104 downto 96);
low := scan_data(114 downto 106);
g2_low_val <= alt_conv_integer(low);
g2_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g2_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g2_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g2_time_delay_val <= delay_val;
-- cntr g1
delay_chain := scan_data(95 downto 92);
if (scan_data(81) = '1') then
g1_mode_val <= "bypass";
if (scan_data(91) = '1') then
g1_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G1 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(91) = '1') then
g1_mode_val <= " odd";
else
g1_mode_val <= " even";
end if;
high := scan_data(80 downto 72);
low := scan_data(90 downto 82);
g1_low_val <= alt_conv_integer(low);
g1_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g1_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g1_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g1_time_delay_val <= delay_val;
-- cntr g0
delay_chain := scan_data(71 downto 68);
if (scan_data(57) = '1') then
g0_mode_val <= "bypass";
if (scan_data(67) = '1') then
g0_mode_val <= " off";
ASSERT false REPORT "The specified bit settings will turn OFF the G0 counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (scan_data(67) = '1') then
g0_mode_val <= " odd";
else
g0_mode_val <= " even";
end if;
high := scan_data(56 downto 48);
low := scan_data(66 downto 58);
g0_low_val <= alt_conv_integer(low);
g0_high_val <= alt_conv_integer(high);
if (alt_conv_integer(high) = 0) then
g0_high_val <= 512;
end if;
if (alt_conv_integer(low) = 0) then
g0_low_val <= 512;
end if;
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
g0_time_delay_val <= delay_val;
-- cntr M
is_error := false;
-- 'low' contains modulus for m_cntr(spread_spectrum disabled)
low := scan_data(32 downto 24);
m_val_tmp <= alt_conv_integer(low);
if (scan_data(33) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m_val_tmp <= 512;
end if;
if (not is_error) then
if (m_mode_val = "bypass") then
ASSERT false REPORT "M counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m_mode_val <= " ";
end if;
elsif (scan_data(33) = '1') then
if (scan_data(24) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val /= "bypass") then
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M modulus = "));
write (buf, 1);
writeline (output, buf);
m_val_tmp <= 1;
m_mode_val <= "bypass";
end if;
end if;
if (skip_vco = "on") then
m_val_tmp <= 1;
ASSERT FALSE REPORT "VCO is bypassed, setting M modulus = 1, M time delay = 0" severity note;
end if;
-- cntr M2
if (ss > 0) then
is_error := false;
low := scan_data(42 downto 34);
m2_val <= alt_conv_integer(low);
if (scan_data(43) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for M2 counter. Instead, M counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
m2_val <= 512;
end if;
if (not is_error) then
if (m2_mode_val = "bypass") then
ASSERT false REPORT "M2 counter switched from BYPASS mode to enabled (M2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" M2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
m2_mode_val <= " ";
end if;
elsif (scan_data(43) = '1') then
if (scan_data(34) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for M2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m2_mode_val /= "bypass") then
ASSERT false REPORT "M2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" M2 modulus = "));
write (buf, 1);
writeline (output, buf);
m2_val <= 1;
m2_mode_val <= "bypass";
end if;
end if;
if (m_mode_val /= m2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for M1/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(47 downto 44);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
m_time_delay_val <= delay_val;
if (skip_vco = "on") then
m_time_delay_val <= 0;
delay_val := 0;
end if;
write (buf, string'(" M time delay = "));
write (buf, delay_val);
writeline (output, buf);
-- cntr N
is_error := false;
-- 'low' contains modulus for n_cntr(spread_spectrum disabled)
low := scan_data(8 downto 0);
n_val_tmp <= alt_conv_integer(low);
if (scan_data(9) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n_val_tmp <= 512;
write (buf, string'(" N modulus = "));
write (buf, 512);
writeline (output, buf);
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
if (not is_error) then
if (n_mode_val = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n_mode_val <= " ";
end if;
elsif (scan_data(9) = '1') then
if (scan_data(0) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val /= "bypass") then
ASSERT false REPORT "N counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N modulus = "));
write (buf, 1);
writeline (output, buf);
n_val_tmp <= 1;
n_mode_val <= "bypass";
end if;
end if;
-- cntr N2
if (ss > 0) then
is_error := false;
low := scan_data(18 downto 10);
n2_val <= alt_conv_integer(low);
if (scan_data(19) /= '1') then
if (alt_conv_integer(low) = 1) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal 1 value for N2 counter. Instead, N counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(low) = 0) then
n2_val <= 512;
end if;
if (not is_error) then
if (n2_mode_val = "bypass") then
ASSERT false REPORT "N2 counter switched from BYPASS mode to enabled (N2 modulus = " &int2str(alt_conv_integer(low))& "). PLL may lose lock." severity warning;
else
write (buf, string'(" N2 modulus = "));
write (buf, alt_conv_integer(low));
writeline (output, buf);
end if;
n2_mode_val <= " ";
end if;
elsif (scan_data(19) = '1') then
if (scan_data(10) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Illegal value for N2 counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n2_mode_val /= "bypass") then
ASSERT false REPORT "N2 counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
write (buf, string'(" N2 modulus = "));
write (buf, 1);
writeline (output, buf);
n2_val <= 1;
n2_mode_val <= "bypass";
end if;
end if;
if (n_mode_val /= n2_mode_val) then
is_error := true;
reconfig_err <= true;
ASSERT false REPORT "Incompatible modes for N1/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
delay_chain := scan_data(23 downto 20);
delay_val := alt_conv_integer(delay_chain);
delay_val := delay_val * 250;
if (delay_val > 3000) then
delay_val := 3000;
end if;
n_time_delay_val <= delay_val;
write (buf, string'(" N time delay = "));
write (buf, delay_val);
writeline (output, buf);
else
if (scan_chain = "long") then
write (buf, string'(" E3 high = "));
write (buf, e3_high_val);
write (buf, string'(" , E3 low = "));
write (buf, e3_low_val);
write (buf, string'(" , E3 mode = "));
write (buf, e3_mode_val);
write (buf, string'(" , E3 time delay = "));
write (buf, e3_time_delay_val);
writeline(output, buf);
write (buf, string'(" E2 high = "));
write (buf, e2_high_val);
write (buf, string'(" , E2 low = "));
write (buf, e2_low_val);
write (buf, string'(" , E2 mode = "));
write (buf, e2_mode_val);
write (buf, string'(" , E2 time delay = "));
write (buf, e2_time_delay_val);
writeline(output, buf);
write (buf, string'(" E1 high = "));
write (buf, e1_high_val);
write (buf, string'(" , E1 low = "));
write (buf, e1_low_val);
write (buf, string'(" , E1 mode = "));
write (buf, e1_mode_val);
write (buf, string'(" , E1 time delay = "));
write (buf, e1_time_delay_val);
writeline(output, buf);
write (buf, string'(" E0 high = "));
write (buf, e0_high_val);
write (buf, string'(" , E0 low = "));
write (buf, e0_low_val);
write (buf, string'(" , E0 mode = "));
write (buf, e0_mode_val);
write (buf, string'(" , E0 time delay = "));
write (buf, e0_time_delay_val);
writeline(output, buf);
end if;
write (buf, string'(" L1 high = "));
write (buf, l1_high_val);
write (buf, string'(" , L1 low = "));
write (buf, l1_low_val);
write (buf, string'(" , L1 mode = "));
write (buf, l1_mode_val);
write (buf, string'(" , L1 time delay = "));
write (buf, l1_time_delay_val);
writeline(output, buf);
write (buf, string'(" L0 high = "));
write (buf, l0_high_val);
write (buf, string'(" , L0 low = "));
write (buf, l0_low_val);
write (buf, string'(" , L0 mode = "));
write (buf, l0_mode_val);
write (buf, string'(" , L0 time delay = "));
write (buf, l0_time_delay_val);
writeline(output, buf);
write (buf, string'(" G3 high = "));
write (buf, g3_high_val);
write (buf, string'(" , G3 low = "));
write (buf, g3_low_val);
write (buf, string'(" , G3 mode = "));
write (buf, g3_mode_val);
write (buf, string'(" , G3 time delay = "));
write (buf, g3_time_delay_val);
writeline(output, buf);
write (buf, string'(" G2 high = "));
write (buf, g2_high_val);
write (buf, string'(" , G2 low = "));
write (buf, g2_low_val);
write (buf, string'(" , G2 mode = "));
write (buf, g2_mode_val);
write (buf, string'(" , G2 time delay = "));
write (buf, g2_time_delay_val);
writeline(output, buf);
write (buf, string'(" G1 high = "));
write (buf, g1_high_val);
write (buf, string'(" , G1 low = "));
write (buf, g1_low_val);
write (buf, string'(" , G1 mode = "));
write (buf, g1_mode_val);
write (buf, string'(" , G1 time delay = "));
write (buf, g1_time_delay_val);
writeline(output, buf);
write (buf, string'(" G0 high = "));
write (buf, g0_high_val);
write (buf, string'(" , G0 low = "));
write (buf, g0_low_val);
write (buf, string'(" , G0 mode = "));
write (buf, g0_mode_val);
write (buf, string'(" , G0 time delay = "));
write (buf, g0_time_delay_val);
writeline(output, buf);
end if;
end process;
process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, inclk0_ipd, inclk1_ipd, clkswitch_ipd, done_with_param_calc)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable primary_clock_frequency : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable schedule_offset : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_ext_fbk_cntr : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable init_clks : boolean := true;
variable ext_fbk_cntr_modulus : integer := 1;
variable pll_is_in_reset : boolean := false;
-- clkswitch variables
variable other_clock_value : std_logic := '0';
variable other_clock_last_value : std_logic;
variable current_clock : string(1 to 6) := primary_clock;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (init and done_with_param_calc) then
if (pll_type = "fast") then
locked_tmp := '1';
end if;
m_val <= m_val_tmp;
n_val <= n_val_tmp;
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
-- merged from separate process
if (now = 0 ps) then
if (current_clock = "inclk1") then
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
external_switch := true;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
if (current_clock /= "inclk0") then
other_clock_value := inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event) then
if (current_clock /= "inclk1") then
other_clock_value := inclk1_ipd;
end if;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
if (current_clock = "inclk0") then
current_clk_is_bad := false;
end if;
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = "inclk1") then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_ipd'event and inclk1_ipd = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
if (current_clock = "inclk1") then
current_clk_is_bad := false;
end if;
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = "inclk0") then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if ((primary_clock = "inclk0" and clk0_is_bad = '1') or (primary_clock = "inclk1" and clk1_is_bad = '1')) then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = "inclk0") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
end if;
if (inclk1_ipd'event and current_clock = "inclk1") then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_ipd;
end if;
else
clkin <= transport inclk1_ipd;
end if;
end if;
if (inclk0_ipd'event or inclk1_ipd'event) then
if ( (other_clock_value = '1') and
(other_clock_value /= other_clock_last_value) and
(switch_over_on_lossclk = "on") and
(enable_switch_over_counter = "on") and
(primary_clk_is_bad) ) then
switch_over_count := switch_over_count + 1;
end if;
if ((other_clock_value = '0') and (other_clock_value /= other_clock_last_value)) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = "inclk0") then
current_clock := "inclk1";
else
current_clock := "inclk0";
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
other_clock_last_value := other_clock_value;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
-- end -- clkswitch
if (schedule_vco'event) then
if (init_clks) then
if (primary_clock = "inclk0") then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk0_input_frequency * 1 ps;
elsif (primary_clock = "inclk1") then
refclk_period := inclk1_input_frequency * n_val * 1 ps;
primary_clock_frequency := inclk1_input_frequency * 1 ps;
end if;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
end if;
-- areset deasserted
if (areset_ipd'event and areset_ipd = '0') then
if (scandataout_tmp = '1') then
sdataout_rst_trig <= transport not sdataout_rst_trig;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
end if;
if (schedule_vco'event and (areset_ipd = '1' or ena_ipd = '0' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
schedule_offset := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or ena_ipd'event or areset_ipd'event) and areset_ipd = '0' and ena_ipd = '1' and (not stop_vco) and (now > 0 ps)) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
loop_time_delay := m_time_delay_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * (ext_fbk_cntr_modulus));
loop_time_delay := m_time_delay_val + ext_fbk_cntr_delay;
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_ext_fbk_cntr := ext_fbk_cntr_delay + (ext_fbk_cntr_initial - 1) * (m_times_vco_period/loop_xplier)/1 ps + fbk_phase;
while (pull_back_ext_fbk_cntr > refclk_period/1 ps) loop
pull_back_ext_fbk_cntr := pull_back_ext_fbk_cntr - refclk_period/ 1 ps;
end loop;
pull_back_M := m_time_delay_val + (m_initial_val - 1) * (ext_fbk_cntr_modulus) * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_ext_fbk_cntr := 0;
pull_back_M := initial_delay/1 ps + m_time_delay_val + fbk_phase;
end if;
total_pull_back := pull_back_M + pull_back_ext_fbk_cntr;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
ext_fbk_delay <= transport (pull_back_ext_fbk_cntr - fbk_phase) after 1 ps;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- add offset
if (schedule_offset) then
sched_time := sched_time + offset;
schedule_offset := false;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
if (sched_time > 0 ps) then
schedule_vco <= transport not schedule_vco after sched_time;
end if;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
n_val <= n_val_tmp;
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ((vco_max /= 0 and vco_min /= 0 and skip_vco = "off" and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
-- unlock
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert false report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= transport m_val_tmp after 1 ps;
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ((now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert (quiet_period_violation) report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
if (pll_type = "fast") then
locked_tmp := '0';
end if;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
if (pll_type = "fast") then
locked_tmp := '1';
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
assert (quiet_period_violation) report family_name & " PLL lost lock" severity note;
first_schedule := true;
schedule_offset := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped; do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
locked_tmp := 'X';
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (quiet_period_violation or reconfig_err or scanclr_violation or scanclr_clk_violation) then
lock <= '0';
if (pll_type = "fast") then
lock <= '1';
end if;
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
sig_current_clock <= current_clock;
-- signals for debugging
sig_offset <= offset;
sig_refclk_time <= refclk_time;
sig_fbclk_time <= fbclk_time;
sig_fbclk_period <= fbclk_period;
sig_vco_period_was_phase_adjusted <= vco_period_was_phase_adjusted;
sig_phase_adjust_was_scheduled <= phase_adjust_was_scheduled;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
sig_m_times_vco_period <= m_times_vco_period;
sig_new_m_times_vco_period <= new_m_times_vco_period;
sig_got_refclk_posedge <= got_refclk_posedge;
sig_got_fbclk_posedge <= got_fbclk_posedge;
sig_got_second_refclk <= got_second_refclk;
end process;
process (scanclk_ipd, scanaclr_ipd, scan_data, transfer, sdataout_trig, sdataout_rst_trig)
variable j : integer := 0;
variable pll_in_quiet_period : boolean := false;
variable start_quiet_time : time := 0 ps;
variable quiet_time : time := 0 ps;
variable scanclr_rising_time : time := 0 ps;
variable scanclr_falling_time : time := 0 ps;
variable got_first_scanclk_after_scanclr_inactive_edge : boolean := false;
variable scan_chain_being_reset : boolean := false;
function slowest_clk ( L0 : integer; L0_mode : string(1 to 6);
L1 : integer; L1_mode : string(1 to 6);
G0 : integer; G0_mode : string(1 to 6);
G1 : integer; G1_mode : string(1 to 6);
G2 : integer; G2_mode : string(1 to 6);
G3 : integer; G3_mode : string(1 to 6);
E0 : integer; E0_mode : string(1 to 6);
E1 : integer; E1_mode : string(1 to 6);
E2 : integer; E2_mode : string(1 to 6);
E3 : integer; E3_mode : string(1 to 6);
scan_chain : string;
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (L0_mode /= "bypass" and L0_mode /= " off") then
max_modulus := L0;
end if;
if (L1 > max_modulus and L1_mode /= "bypass" and L1_mode /= " off") then
max_modulus := L1;
end if;
if (G0 > max_modulus and G0_mode /= "bypass" and G0_mode /= " off") then
max_modulus := G0;
end if;
if (G1 > max_modulus and G1_mode /= "bypass" and G1_mode /= " off") then
max_modulus := G1;
end if;
if (G2 > max_modulus and G2_mode /= "bypass" and G2_mode /= " off") then
max_modulus := G2;
end if;
if (G3 > max_modulus and G3_mode /= "bypass" and G3_mode /= " off") then
max_modulus := G3;
end if;
if (scan_chain = "long") then
if (E0 > max_modulus and E0_mode /= "bypass" and E0_mode /= " off") then
max_modulus := E0;
end if;
if (E1 > max_modulus and E1_mode /= "bypass" and E1_mode /= " off") then
max_modulus := E1;
end if;
if (E2 > max_modulus and E2_mode /= "bypass" and E2_mode /= " off") then
max_modulus := E2;
end if;
if (E3 > max_modulus and E3_mode /= "bypass" and E3_mode /= " off") then
max_modulus := E3;
end if;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := ((refclk_int/m_mod) * max_modulus) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
begin
if (transfer'event) then
if (transfer = '0') then
-- clear the chain
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
elsif (scanaclr_ipd'event and scanaclr_ipd = '1') then
-- scanaclr rising
scanclr_rising_time := now;
scan_chain_being_reset := true;
elsif (scanaclr_ipd'event and scanaclr_ipd = '0') then
-- scanaclr falling
scanclr_falling_time := now;
if (scan_chain_being_reset and (now - scanclr_rising_time < TRST)) then
scanclr_violation <= true;
ASSERT false REPORT "Detected SCANACLR ACTIVE pulse width violation. Required is 5000 ps, actual is "& int2str((now - scanclr_rising_time) / 1 ps) &". The PLL may not function correctly." severity warning;
else
scanclr_violation <= false;
for i in scan_data'range loop
scan_data(i) <= '0';
end loop;
end if;
scan_chain_being_reset := false;
got_first_scanclk_after_scanclr_inactive_edge := false;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and not got_first_scanclk_after_scanclr_inactive_edge and (now - scanclr_falling_time < TRSTCLK)) then
scanclr_clk_violation <= true;
got_first_scanclk_after_scanclr_inactive_edge := true;
ASSERT false REPORT "Detected SCANACLR INACTIVE time violation before rising edge of SCANCLK. Required is 5000 ps, actual is "& int2str((now - scanclr_falling_time) / 1 ps) &". Reconfiguration may not work." severity warning;
elsif (scanclk_ipd'event and scanclk_ipd = '1' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
else
pll_in_quiet_period := false;
for j in scan_chain_length-1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
if (not got_first_scanclk_after_scanclr_inactive_edge) then
got_first_scanclk_after_scanclr_inactive_edge := true;
scanclr_clk_violation <= false;
end if;
elsif (scanclk_ipd'event and scanclk_ipd = '0' and scanaclr_ipd = '0') then
if (pll_in_quiet_period and (now - start_quiet_time < quiet_time)) then
ASSERT false REPORT "Detected transition on SCANCLK during quiet period. The PLL may not function correctly." severity warning;
quiet_period_violation <= true;
elsif (scan_data(scan_chain_length-1) = '1') then
-- reset violation flag only after another reconfig seq.
quiet_period_violation <= false;
-- initiate transfer
transfer <= '1';
transfer <= transport '0' after 1 ps;
scandataout_tmp <= '1';
pll_in_quiet_period := true;
start_quiet_time := now;
quiet_time := slowest_clk ( l0_high_val+l0_low_val, l0_mode_val,
l1_high_val+l1_low_val, l1_mode_val,
g0_high_val+g0_low_val, g0_mode_val,
g1_high_val+g1_low_val, g1_mode_val,
g2_high_val+g2_low_val, g2_mode_val,
g3_high_val+g3_low_val, g3_mode_val,
e0_high_val+e0_low_val, e0_mode_val,
e1_high_val+e1_low_val, e1_mode_val,
e2_high_val+e2_low_val, e2_mode_val,
e3_high_val+e3_low_val, e3_mode_val,
scan_chain, sig_refclk_period, m_val);
sdataout_trig <= transport not sdataout_trig after quiet_time;
end if;
elsif (sdataout_trig'event) then
if (areset_ipd = '0') then
scandataout_tmp <= transport '0';
end if;
elsif (sdataout_rst_trig'event) then
scandataout_tmp <= transport '0' after quiet_time;
end if;
end process;
clk0_tmp <= l0_clk when i_clk0_counter = "l0" else
l1_clk when i_clk0_counter = "l1" else
g0_clk when i_clk0_counter = "g0" else
g1_clk when i_clk0_counter = "g1" else
g2_clk when i_clk0_counter = "g2" else
g3_clk when i_clk0_counter = "g3" else
'0';
not_clk0_tmp <= not clk0_tmp;
ena0_reg : stratixgx_dffe
port map ( D => clkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0_tmp,
Q => ena0 );
clk(0) <= ena0 and clk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena0 and 'X';
clk1_tmp <= l0_clk when i_clk1_counter = "l0" else
l1_clk when i_clk1_counter = "l1" else
g0_clk when i_clk1_counter = "g0" else
g1_clk when i_clk1_counter = "g1" else
g2_clk when i_clk1_counter = "g2" else
g3_clk when i_clk1_counter = "g3" else
'0';
not_clk1_tmp <= not clk1_tmp;
ena1_reg : stratixgx_dffe
port map ( D => clkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk1_tmp,
Q => ena1 );
clk(1) <= ena1 and clk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena1 and 'X';
clk2_tmp <= l0_clk when i_clk2_counter = "l0" else
l1_clk when i_clk2_counter = "l1" else
g0_clk when i_clk2_counter = "g0" else
g1_clk when i_clk2_counter = "g1" else
g2_clk when i_clk2_counter = "g2" else
g3_clk when i_clk2_counter = "g3" else
'0';
not_clk2_tmp <= not clk2_tmp;
ena2_reg : stratixgx_dffe
port map ( D => clkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk2_tmp,
Q => ena2 );
clk(2) <= ena2 and clk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena2 and 'X';
clk3_tmp <= l0_clk when i_clk3_counter = "l0" else
l1_clk when i_clk3_counter = "l1" else
g0_clk when i_clk3_counter = "g0" else
g1_clk when i_clk3_counter = "g1" else
g2_clk when i_clk3_counter = "g2" else
g3_clk when i_clk3_counter = "g3" else
'0';
not_clk3_tmp <= not clk3_tmp;
ena3_reg : stratixgx_dffe
port map ( D => clkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk3_tmp,
Q => ena3 );
clk(3) <= ena3 and clk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena3 and 'X';
clk4_tmp <= l0_clk when i_clk4_counter = "l0" else
l1_clk when i_clk4_counter = "l1" else
g0_clk when i_clk4_counter = "g0" else
g1_clk when i_clk4_counter = "g1" else
g2_clk when i_clk4_counter = "g2" else
g3_clk when i_clk4_counter = "g3" else
'0';
not_clk4_tmp <= not clk4_tmp;
ena4_reg : stratixgx_dffe
port map ( D => clkena(4),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk4_tmp,
Q => ena4 );
clk(4) <= ena4 and clk4_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena4 and 'X';
clk5_tmp <= l0_clk when i_clk5_counter = "l0" else
l1_clk when i_clk5_counter = "l1" else
g0_clk when i_clk5_counter = "g0" else
g1_clk when i_clk5_counter = "g1" else
g2_clk when i_clk5_counter = "g2" else
g3_clk when i_clk5_counter = "g3" else
'0';
not_clk5_tmp <= not clk5_tmp;
ena5_reg : stratixgx_dffe
port map ( D => clkena(5),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk5_tmp,
Q => ena5 );
clk(5) <= ena5 and clk5_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
ena5 and 'X';
extclk0_tmp <= e0_clk when i_extclk0_counter = "e0" else
e1_clk when i_extclk0_counter = "e1" else
e2_clk when i_extclk0_counter = "e2" else
e3_clk when i_extclk0_counter = "e3" else
g0_clk when i_extclk0_counter = "g0" else
'0';
not_extclk0_tmp <= not extclk0_tmp;
extena0_reg : stratixgx_dffe
port map ( D => extclkena(0),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk0_tmp,
Q => extena0 );
extclk(0) <= extena0 and extclk0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena0 and 'X';
extclk1_tmp <= e0_clk when i_extclk1_counter = "e0" else
e1_clk when i_extclk1_counter = "e1" else
e2_clk when i_extclk1_counter = "e2" else
e3_clk when i_extclk1_counter = "e3" else
g0_clk when i_extclk1_counter = "g0" else
'0';
not_extclk1_tmp <= not extclk1_tmp;
extena1_reg : stratixgx_dffe
port map ( D => extclkena(1),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk1_tmp,
Q => extena1 );
extclk(1) <= extena1 and extclk1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena1 and 'X';
extclk2_tmp <= e0_clk when i_extclk2_counter = "e0" else
e1_clk when i_extclk2_counter = "e1" else
e2_clk when i_extclk2_counter = "e2" else
e3_clk when i_extclk2_counter = "e3" else
g0_clk when i_extclk2_counter = "g0" else
'0';
not_extclk2_tmp <= not extclk2_tmp;
extena2_reg : stratixgx_dffe
port map ( D => extclkena(2),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk2_tmp,
Q => extena2 );
extclk(2) <= extena2 and extclk2_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena2 and 'X';
extclk3_tmp <= e0_clk when i_extclk3_counter = "e0" else
e1_clk when i_extclk3_counter = "e1" else
e2_clk when i_extclk3_counter = "e2" else
e3_clk when i_extclk3_counter = "e3" else
g0_clk when i_extclk3_counter = "g0" else
'0';
not_extclk3_tmp <= not extclk3_tmp;
extena3_reg : stratixgx_dffe
port map ( D => extclkena(3),
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_extclk3_tmp,
Q => extena3 );
extclk(3) <= extena3 and extclk3_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
extena3 and 'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0') or (about_to_lock and (not quiet_period_violation) and (not reconfig_err) and (not scanclr_violation) and (not scanclr_clk_violation)) else
'X';
scandataout <= scandataout_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_dll
--
-- Description : Simulation model for the STRATIXGX DLL.
--
-- Outputs : Delayctrlout output (active high) indicates when the
-- DLL locks to the incoming clock
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixgx_atom_pack.all;
USE work.stratixgx_pllpack.all;
ENTITY stratixgx_dll is
GENERIC ( input_frequency : string := "10000 ps";
phase_shift : string := "0";
sim_valid_lock : integer := 1;
sim_invalid_lock : integer := 5;
lpm_type : string := "stratixgx_dll";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
delayctrlout : OUT std_logic
);
END stratixgx_dll;
ARCHITECTURE vital_dll of stratixgx_dll is
signal clk_detect : std_logic := '0';
signal clk_ipd : std_logic;
begin
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
process (clk_ipd, clk_detect)
variable got_first_rising_edge : boolean := false;
variable got_first_falling_edge : boolean := false;
variable clk_ipd_last_rising_edge : time := 0 ps;
variable clk_ipd_last_falling_edge : time := 0 ps;
variable inclk_ps : time := 0 ps;
variable duty_cycle : time := 0 ps;
variable clk_per_tolerance : time := 0 ps;
variable clk_detect_count : integer := 0;
variable start_clk_detect : boolean := false;
variable half_cycles_to_lock : integer := 0;
variable half_cycles_to_keep_lock : integer := 0;
variable violation : boolean := false;
variable dll_is_locked : std_logic := '0';
variable init : boolean := true;
variable input_freq_warn : boolean := true;
variable duty_cycle_warn : boolean := true;
begin
if (init) then
-- convert the frequency in string form to integer
inclk_ps := dqs_str2int(input_frequency) * 1 ps;
duty_cycle := inclk_ps/2;
clk_per_tolerance := inclk_ps * 0.1;
-- if sim_valid_lock = 0, dll starts out locked
if (sim_valid_lock = 0) then
dll_is_locked := '1';
end if;
init := false;
end if;
if (clk_ipd'event and clk_ipd = '1') then
if (not got_first_rising_edge) then
got_first_rising_edge := true;
half_cycles_to_lock := half_cycles_to_lock + 1;
if (sim_valid_lock > 0 and half_cycles_to_lock >= sim_valid_lock and not violation) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
-- start the internal clock that will monitor
-- the input clock
if (not start_clk_detect) then
start_clk_detect := true;
clk_detect <= '1';
end if;
else
-- reset clk_event counter
clk_detect_count := 0;
-- check for clk period violation
if ( ((now - clk_ipd_last_rising_edge) < (inclk_ps - clk_per_tolerance)) or ((now - clk_ipd_last_rising_edge) > (inclk_ps + clk_per_tolerance)) ) then
violation := true;
if (input_freq_warn) then
assert false report "Input frequency violation." severity warning;
input_freq_warn := false;
end if;
elsif ( ((now - clk_ipd_last_falling_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_falling_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (violation and dll_is_locked = '1') then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (violation) then
half_cycles_to_lock := 0;
elsif (not violation and dll_is_locked = '0') then
-- increment lock counter
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock > sim_valid_lock) then
dll_is_locked := '1';
assert false report "DLL locked to incoming clock" severity note;
end if;
else
half_cycles_to_keep_lock := 0;
end if;
end if;
clk_ipd_last_rising_edge := now;
elsif (clk_ipd'event and clk_ipd = '0') then
-- reset clk_event counter
clk_detect_count := 0;
got_first_falling_edge := true;
if (got_first_rising_edge) then
-- check for duty cycle violation
if ( ((now - clk_ipd_last_rising_edge) < (duty_cycle - clk_per_tolerance/2)) or ((now - clk_ipd_last_rising_edge) > (duty_cycle + clk_per_tolerance/2)) ) then
violation := true;
if (duty_cycle_warn) then
assert false report "Duty cycle violation." severity warning;
duty_cycle_warn := false;
end if;
else
violation := false;
end if;
if (dll_is_locked = '1' and violation) then
half_cycles_to_keep_lock := half_cycles_to_keep_lock + 1;
if (half_cycles_to_keep_lock > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to Input Frequency / Duty Cycle violation" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
end if;
elsif (dll_is_locked = '1') then
half_cycles_to_keep_lock := 0;
elsif (dll_is_locked = '0' and violation) then
half_cycles_to_lock := 0;
else
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
else
-- first clk edge is falling edge, do nothing
end if;
clk_ipd_last_falling_edge := now;
else
if (clk_ipd'event) then
-- illegal value
if (got_first_rising_edge or got_first_falling_edge) then
if (dll_is_locked = '1') then
dll_is_locked := '0';
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
assert false report "Illegal value detected on input clock. DLL will lose lock." severity error;
else
-- clock started up, then went to 'X'
-- this is to weed out the 'X' at start of simulation.
assert false report "Illegal value detected on input clock." severity error;
-- reset lock counter
half_cycles_to_lock := 0;
end if;
end if;
end if;
end if;
-- ********************************************************************
-- The following block generates the internal clock that is used to
-- track loss of input clock. A counter counts events on this internal
-- clock, and is reset to 0 on event on input clock. If input clock
-- flatlines, the counter will exceed the limit and DLL will lose lock.
-- Events on internal clock are scheduled at the max. allowable input
-- clock tolerance, to allow 'sim_invalid_lock' parameter value = 1.
-- ********************************************************************
if (start_clk_detect) then
if (clk_detect'event and clk_detect /= clk_detect'last_value) then
-- increment clock event counter
clk_detect_count := clk_detect_count + 1;
if (dll_is_locked = '1') then
if (clk_detect_count > sim_invalid_lock) then
dll_is_locked := '0';
assert false report "DLL lost lock due to loss of input clock" severity warning;
-- reset lock and unlock counters
half_cycles_to_lock := 0;
half_cycles_to_keep_lock := 0;
got_first_rising_edge := false;
got_first_falling_edge := false;
clk_detect_count := 0;
start_clk_detect := false;
clk_detect <= transport '0' after inclk_ps/2;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
elsif (clk_detect_count > 10) then
assert false report "No input clock : DLL will not lock" severity warning;
clk_detect_count := 0;
else
clk_detect <= transport not clk_detect after (inclk_ps/2 + clk_per_tolerance/2);
end if;
end if;
end if;
delayctrlout <= dll_is_locked;
end process;
end vital_dll;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_TX_PARALLEL_REGISTER
--
-- Description : Timing simulation model for parallel register submodule
-- of STRATIXGX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_tx_parallel_register is
GENERIC (
channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratixgx_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixgx_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXGX_TRANSMITTER",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_TX_OUT_BLOCK
--
-- Description : Timing simulation model for output block submodule
-- of STRATIXGX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_tx_parallel_register;
use work.stratixgx_dffe;
ENTITY stratixgx_lvds_tx_out_block is
GENERIC (
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end stratixgx_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixgx_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_TRANSMITTER
--
-- Description : Timing simulation model for STRATIXGX_LVDS_TX
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_tx_out_block;
ENTITY stratixgx_lvds_transmitter is
GENERIC (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratixgx_lvds_transmitter";
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end stratixgx_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixgx_lvds_transmitter is
signal clk0_ipd : std_logic;
signal not_clk0 : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal txload1 : std_logic;
signal txload2 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly5 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
COMPONENT stratixgx_lvds_tx_parallel_register
GENERIC (
channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_lvds_tx_out_block
GENERIC (
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
end COMPONENT;
COMPONENT stratixgx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01
);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
end block;
txload0_reg: stratixgx_dffe
PORT map(D => enable0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0_dly2,
Q => txload0);
txload1_reg: stratixgx_dffe
PORT map(D => txload0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0_dly1,
Q => txload1);
not_clk0 <= not clk0_dly0;
txload2_reg: stratixgx_dffe
PORT map(D => txload1,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0,
Q => txload2);
input_reg: stratixgx_lvds_tx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor);
output_module: stratixgx_lvds_tx_out_block
GENERIC map(bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT map(clk => clk0_dly2,
datain => shift_out,
dataout => dataout,
devclrn => devclrn,
devpor => devpor);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly5 <= datain_dly4;
end process;
data_delay2: process (datain_dly5)
begin
datain_dly <= datain_dly5;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable i : integer := 0;
variable dataout_tmp : std_logic;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
dataout_tmp := '0';
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := '0';
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload2 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
end vital_transmitter_atom;
-------------------------------------------------------------------
--
-- Entity Name : stratixgx_jtag
--
-- Description : STRATIXGX JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_jtag is
generic (
lpm_type : string := "stratixgx_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixgx_jtag;
architecture architecture_jtag of stratixgx_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixgx_crcblock
--
-- Description : STRATIXGX CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixgx_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixgx_crcblock;
architecture architecture_crcblock of stratixgx_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixgx_rublock
--
-- Description : STRATIXGX RUBLOCK VHDL Simulation model
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixgx_atom_pack.all;
entity stratixgx_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixgx_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end stratixgx_rublock;
architecture architecture_rublock of stratixgx_rublock is
signal update_reg : std_logic_vector(16 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(21 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is inverted output of shift-reg bit 0
regout <= not shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(16 downto 5) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(4) <= '1';
else
update_reg(4) <= '0';
end if;
-- PGM[] field
update_reg(3 downto 1) <= conv_std_logic_vector(sim_init_page_select, 3);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[3:1]);
--report " -> Field User Watchdog is set to %s", update_reg[4] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 20 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(21) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and operation_mode = "remote") then
-- every bit in Update Reg gets updated
update_reg(16 downto 0) <= shift_reg(21 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[8:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[9] == 1) ? "Enableds" : (shift_reg[9] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[21:10];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(16 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
else
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[3:1];
--report " -> Field User Watchdog is set to %s", (update_reg[4] == 1) ? "Enabled" : (update_reg[4] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[16:5];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
---------------------------------------------------------------------
--
-- Entity Name : stratixgx_routing_wire
--
-- Description : STRATIXGXII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
ENTITY stratixgx_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixgx_routing_wire : entity is TRUE;
end stratixgx_routing_wire;
ARCHITECTURE behave of stratixgx_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_deserializer
--
-- Description : Timing simulation model for deserializer submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_deserializer is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk0_pclk_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
clk0 : IN std_logic := '0';
coreclk : IN std_logic := '0';
datain : IN std_logic := '0';
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 downto 0);
pclk : OUT std_logic
);
end stratixgx_lvds_rx_deserializer;
ARCHITECTURE vital_stratixgx_lvds_rx_deserializer of stratixgx_lvds_rx_deserializer is
signal clk0_in : std_logic;
signal coreclk_in : std_logic;
signal coreclk_in_pre : std_logic;
signal datain_in : std_logic;
signal reset_in : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (coreclk_in_pre, coreclk, tipd_coreclk);
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (reset_in, reset, tipd_reset);
end block;
coreclk_delta : process (coreclk_in_pre)
begin
coreclk_in <= coreclk_in_pre;
end process;
vital : process (clk0_in, coreclk_in, reset_in)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable pclk_VitalGlitchData : VitalGlitchDataType;
variable datain_pos : std_logic;
variable datain_neg : std_logic;
variable sync_reset : std_logic;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable clkout_tmp : std_logic := '0';
variable deser_data_arr : std_logic_vector(channel_width - 1 downto 0);
variable clk_count : integer;
variable clk_count_neg : integer;
variable clk0_last_value : std_logic;
variable coreclk_last_value : std_logic;
variable clkout_last_value : std_logic;
variable i : integer;
VARIABLE CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
i := 0;
clk_count := channel_width;
clk_count_neg := 0;
clkout_last_value := '0';
coreclk_last_value := '0';
dataout_tmp := (OTHERS => '0');
datain_pos := '0';
datain_neg := '0';
sync_reset := '0';
for i in channel_width - 1 downto 0 loop
deser_data_arr(i) := '0';
end loop;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value /= clk0_in) then
if (clk_count = channel_width) then
clk_count := 0;
if (sync_reset = '0') then
clkout_tmp := NOT clkout_last_value;
end if;
else
if (clk_count = (channel_width + 1) / 2) then
if (sync_reset = '0') then
clkout_tmp := NOT clkout_last_value;
end if;
else
if (clk_count < channel_width) then
if (sync_reset = '0') then
clkout_tmp := clkout_last_value;
end if;
end if;
end if;
end if;
clk_count := clk_count + 1;
if (sync_reset = '1') then
dataout_tmp := (OTHERS => '0');
elsif (clk_count_neg = 2) then
dataout_tmp := deser_data_arr;
end if;
datain_pos := datain_neg;
for i in channel_width-1 downto 1 loop
deser_data_arr(i) := deser_data_arr(i - 1);
end loop;
deser_data_arr(0) := datain_pos;
end if;
if (clk0_in'event and (clk0_in = '0')) then
clk_count_neg := clk_count_neg + 1;
datain_neg := datain_in;
end if;
if (coreclk_in'event and (coreclk_in = '1')) then
if (reset_in = '1') then
sync_reset := '1';
else
sync_reset := '0';
clk_count_neg := 0;
end if;
end if;
if (clkout_tmp /= 'U') then
clkout_last_value := clkout_tmp;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => pclk,
OutsignalName => "PCLK",
OutTemp => clkout_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_pclk_posedge, TRUE)),
GlitchData => pclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
CQDelay := SelectDelay (
Paths => (
(0 => (clk0_in'LAST_EVENT,tpd_clk0_dataout_posedge, TRUE))
)
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_deserializer;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_RX_PARALLEL_REGISTER
--
-- Description : Timing simulation model for parallel register submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_parallel_register is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
reset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratixgx_lvds_rx_parallel_register;
ARCHITECTURE vital_stratixgx_lvds_rx_parallel_register of stratixgx_lvds_rx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, devpor, devclrn)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (reset = '1') then
dataout_tmp := (OTHERS => '0');
elsif (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_parallel_register;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_fifo_sync_ram
--
-- Description : Timing simulation model for FIFO SYNC RAM submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_fifo_sync_ram is
GENERIC (
ram_width : integer := 10
);
PORT (
clk : in std_logic := '0';
datain : in std_logic_vector(ram_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : in std_logic := '0';
waddr : in std_logic_vector(1 DOWNTO 0) := "00";
raddr : in std_logic_vector(1 DOWNTO 0) := "00";
we : in std_logic := '0';
dataout : out std_logic_vector(ram_width - 1 DOWNTO 0)
);
end stratixgx_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_stratixgx_lvds_rx_fifo_sync_ram OF stratixgx_lvds_rx_fifo_sync_ram IS
signal ram_d0 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_d1 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_d2 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_d3 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q0 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q1 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q2 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal ram_q3 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg0 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg1 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg2 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal data_reg3 : std_logic_vector(ram_width - 1 DOWNTO 0);
signal dataout_tmp : std_logic_vector(ram_width - 1 DOWNTO 0);
begin
data_reg0 <= datain WHEN (waddr = "00") ELSE ram_q0 ;
data_reg1 <= datain WHEN (waddr = "01") ELSE ram_q1 ;
data_reg2 <= datain WHEN (waddr = "10") ELSE ram_q2 ;
data_reg3 <= datain WHEN (waddr = "11") ELSE ram_q3 ;
dataout <= dataout_tmp;
process (clk, reset)
begin
if (now = 0 ns) then
ram_q0 <= (OTHERS => '0');
ram_q1 <= (OTHERS => '0');
ram_q2 <= (OTHERS => '0');
ram_q3 <= (OTHERS => '0');
end if;
if (reset = '1') then
ram_q0 <= (OTHERS => '0');
ram_q1 <= (OTHERS => '0');
ram_q2 <= (OTHERS => '0');
ram_q3 <= (OTHERS => '0');
elsif (clk'event and clk = '1') then
ram_q0 <= ram_d0;
ram_q1 <= ram_d1;
ram_q2 <= ram_d2;
ram_q3 <= ram_d3;
end if;
end process;
process (we, data_reg0, data_reg1, data_reg2, data_reg3, ram_q0, ram_q1, ram_q2, ram_q3)
begin
if (we = '1') then
ram_d0 <= data_reg0;
ram_d1 <= data_reg1;
ram_d2 <= data_reg2;
ram_d3 <= data_reg3;
else
ram_d0 <= ram_q0;
ram_d1 <= ram_q1;
ram_d2 <= ram_q2;
ram_d3 <= ram_q3;
end if;
end process;
process (ram_q0, ram_q1, ram_q2, ram_q3, we, waddr, raddr)
begin
if (now = 0 ns) then
dataout_tmp <= (OTHERS => '0');
end if;
case raddr is
WHEN "00" =>
dataout_tmp <= ram_q0;
WHEN "01" =>
dataout_tmp <= ram_q1;
WHEN "10" =>
dataout_tmp <= ram_q2;
WHEN "11" =>
dataout_tmp <= ram_q3;
WHEN OTHERS =>
NULL;
end case;
end process;
END vital_stratixgx_lvds_rx_fifo_sync_ram;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_fifo
--
-- Description : Timing simulation model for RX FIFO submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_rx_fifo_sync_ram;
ENTITY stratixgx_lvds_rx_fifo is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
reset : IN std_logic := '0';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end stratixgx_lvds_rx_fifo;
ARCHITECTURE vital_stratixgx_lvds_rx_fifo of stratixgx_lvds_rx_fifo is
signal wclk_in : std_logic;
signal rclk_in : std_logic;
signal reset_in : std_logic;
signal datain_in : std_logic_vector(channel_width - 1 downto 0);
signal rdAddr : std_logic_vector(1 downto 0);
signal rdPtr : std_logic_vector(1 downto 0);
signal wrPtr : std_logic_vector(1 downto 0);
signal ram_datain : std_logic_vector(channel_width - 1 downto 0);
signal ram_dataout : std_logic_vector(channel_width - 1 downto 0);
signal ram_we : std_logic;
signal sync_reset : std_logic := '0';
COMPONENT stratixgx_lvds_rx_fifo_sync_ram
GENERIC (
ram_width : integer := 10
);
PORT (
clk : in std_logic := '0';
datain : in std_logic_vector(ram_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : in std_logic := '0';
waddr : in std_logic_vector(1 DOWNTO 0) := "00";
raddr : in std_logic_vector(1 DOWNTO 0) := "00";
we : in std_logic := '0';
dataout : out std_logic_vector(ram_width - 1 DOWNTO 0)
);
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (reset_in, reset, tipd_reset);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixgx_lvds_rx_fifo_sync_ram
GENERIC map (
ram_width => channel_width
)
PORT map (
clk => wclk_in,
datain => ram_datain,
reset => sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, sync_reset)
begin
if (now = 0 ns) then
wrPtr <= "00";
ram_datain <= (OTHERS => '0');
ram_we <= '0';
end if;
if (sync_reset = '1') then
wrPtr <= "00";
ram_we <= '0';
elsif (wclk_in'event and wclk_in = '1') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "00" => wrPtr <= "01";
when "01" => wrPtr <= "10";
when "10" => wrPtr <= "11";
when "11" => wrPtr <= "00";
when others => wrPtr <= "00";
end case;
end if;
end process;
process (rclk_in)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable dataout_tmp : std_logic_vector(channel_width - 1 DOWNTO 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
rdPtr <= "10";
dataout_tmp := (OTHERS => '0');
end if;
if (rclk_in'event and rclk_in = '1' and rclk_in'last_value = '0') then
if (reset_in = '1') then
sync_reset <= '1';
rdPtr <= "10";
dataout_tmp := (OTHERS => '0');
else
if (sync_reset = '1') then
rdPtr <= "10";
dataout_tmp := (OTHERS => '0');
else
dataout_tmp := ram_dataout;
case rdPtr is
when "00" => rdPtr <= "01";
when "01" => rdPtr <= "10";
when "10" => rdPtr <= "11";
when "11" => rdPtr <= "00";
when others => rdPtr <= "00";
end case;
end if;
sync_reset <= '0';
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_fifo;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_lvds_rx_bitslip
--
-- Description : Timing simulation model for Bitslip submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
ENTITY stratixgx_lvds_rx_bitslip is
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
coreclk : IN std_logic := '0';
bitslip : IN std_logic := '0';
rxpdat2 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpdat3 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end stratixgx_lvds_rx_bitslip;
ARCHITECTURE vital_stratixgx_lvds_rx_bitslip of stratixgx_lvds_rx_bitslip is
signal bitslip_in : std_logic;
signal bitslip0 : std_logic;
signal bitslip1 : std_logic;
signal bitslip_cntl : std_logic;
signal coreclk_in : std_logic;
signal slip_count_sig : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (coreclk_in, coreclk, tipd_coreclk);
VitalWireDelay (bitslip_in, bitslip, tipd_bitslip);
end block;
vital : process (coreclk_in)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable slip_count : integer;
variable dataout_tmp : std_logic_vector(channel_width - 1 DOWNTO 0);
variable i : integer;
variable j : integer;
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
slip_count := 0;
bitslip0 <= '0';
bitslip1 <= '0';
dataout_tmp := (OTHERS => '0');
end if;
if (coreclk_in'event and coreclk_in = '1') then
if (reset = '1') then
slip_count := 0;
bitslip0 <= '0';
bitslip1 <= '0';
bitslip_cntl <= '0';
dataout_tmp := (OTHERS => '0');
else
bitslip_cntl <= bitslip1 AND (NOT bitslip0);
bitslip0 <= bitslip1;
bitslip1 <= bitslip_in;
if (bitslip_cntl = '1') then
slip_count := slip_count + 1;
if (slip_count = channel_width) then
slip_count := 0;
end if;
end if;
if (slip_count = 0) then
dataout_tmp := rxpdat3;
else
j := 0;
for i in (channel_width - slip_count) to (channel_width - 1) loop
dataout_tmp(j) := rxpdat2(i);
j := j + 1;
end loop;
for i in 0 to ((channel_width - slip_count) - 1) loop
dataout_tmp(j) := rxpdat3(i);
j := j + 1;
end loop;
end if;
end if;
end if;
slip_count_sig <= slip_count;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
Paths => (
(0 => (coreclk_in'LAST_EVENT,tpd_coreclk_dataout_posedge,TRUE))
)
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_stratixgx_lvds_rx_bitslip;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_DPA_RECEIVER
--
-- Description : Timing simulation model for DPA_RECEIVER submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_rx_deserializer;
use work.stratixgx_lvds_rx_parallel_register;
use work.stratixgx_lvds_rx_fifo;
use work.stratixgx_lvds_rx_bitslip;
ENTITY stratixgx_dpa_receiver is
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
end stratixgx_dpa_receiver;
ARCHITECTURE vital_stratixgx_dpa_receiver of stratixgx_dpa_receiver is
signal dpllreset_in : std_logic;
signal dpareset_in : std_logic;
-- internal reset signal
signal reset_int : std_logic;
-- output from rx_deserializer
signal deser_dataout : std_logic_vector(channel_width - 1 downto 0);
signal deser_pclk : std_logic;
-- input/output of FIFO
signal fifo_datain : std_logic_vector(channel_width - 1 downto 0);
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_dataout : std_logic_vector(channel_width - 1 downto 0);
-- input/output of RXPDAT2
signal rxpdat2_datain : std_logic_vector(channel_width - 1 downto 0);
signal rxpdat2_dataout : std_logic_vector(channel_width - 1 downto 0);
-- input/output of RXPDAT3
signal rxpdat3_datain : std_logic_vector(channel_width - 1 downto 0);
signal rxpdat3_dataout : std_logic_vector(channel_width - 1 downto 0);
-- input/output of bitslip
signal slip_pdat2 : std_logic_vector(channel_width - 1 downto 0);
signal slip_pdat3 : std_logic_vector(channel_width - 1 downto 0);
signal dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
signal dpalock_tmp : std_logic := '1';
signal vcc : std_logic := '1';
COMPONENT stratixgx_lvds_rx_deserializer
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk0_pclk_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
clk0 : IN std_logic := '0';
coreclk : IN std_logic := '0';
datain : IN std_logic := '0';
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 downto 0);
pclk : OUT std_logic
);
end COMPONENT;
COMPONENT stratixgx_lvds_rx_parallel_register
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
reset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_lvds_rx_fifo
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
reset : IN std_logic := '0';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end COMPONENT;
COMPONENT stratixgx_lvds_rx_bitslip
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_coreclk : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_reset : VitalDelayType01 := DefpropDelay01;
tpd_coreclk_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT (
coreclk : IN std_logic := '0';
bitslip : IN std_logic := '0';
rxpdat2 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
rxpdat3 : IN std_logic_vector(channel_width - 1 DOWNTO 0) := (OTHERS => '0');
reset : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0)
);
end COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (dpareset_in, dpareset, tipd_dpareset);
VitalWireDelay (dpllreset_in, dpllreset, tipd_dpllreset);
end block;
reset_int <= (NOT devpor) OR (NOT devclrn) OR dpareset_in OR dpllreset_in ;
-- FIFO inputs
fifo_datain <= deser_dataout ;
fifo_wclk <= deser_pclk ;
fifo_rclk <= coreclk ;
-- RXPDAT2/3 inputs
rxpdat2_datain <= fifo_dataout WHEN (enable_fifo = "on") else deser_dataout ;
rxpdat3_datain <= rxpdat2_dataout ;
-- bitslip inputs
slip_pdat2 <= rxpdat2_dataout ;
slip_pdat3 <= rxpdat3_dataout ;
-- set output
dataout <= dataout_tmp;
dpalock <= dpalock_tmp;
-- sub modules
s_deserializer : stratixgx_lvds_rx_deserializer
GENERIC map (
channel_width => channel_width
)
PORT map (
clk0 => clk0,
coreclk => coreclk,
datain => datain,
reset => reset_int,
dataout => deser_dataout,
pclk => deser_pclk
);
s_fifo : stratixgx_lvds_rx_fifo
GENERIC map (
channel_width => channel_width
)
PORT map (
wclk => fifo_wclk,
rclk => fifo_rclk,
reset => reset_int,
datain => fifo_datain,
dataout => fifo_dataout
);
s_rxpdat2 : stratixgx_lvds_rx_parallel_register
GENERIC map (
channel_width => channel_width
)
PORT map (
clk => coreclk,
datain => rxpdat2_datain,
enable => vcc,
reset => reset_int,
devpor => vcc,
devclrn => vcc,
dataout => rxpdat2_dataout
);
s_rxpdat3 : stratixgx_lvds_rx_parallel_register
GENERIC map (
channel_width => channel_width
)
PORT map (
clk => coreclk,
datain => rxpdat3_datain,
enable => vcc,
reset => reset_int,
devpor => vcc,
devclrn => vcc,
dataout => rxpdat3_dataout
);
s_bitslip : stratixgx_lvds_rx_bitslip
GENERIC map (
channel_width => channel_width
)
PORT map (
coreclk => coreclk,
bitslip => bitslip,
rxpdat2 => slip_pdat2,
rxpdat3 => slip_pdat3,
reset => reset_int,
dataout => dataout_tmp
);
end vital_stratixgx_dpa_receiver;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixgx_nondpa_lvds_receiver
--
-- Description : Timing simulation model for NONDPA_RECEIVER submodule
-- in Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_lvds_rx_parallel_register;
use work.stratixgx_dffe;
use work.stratixgx_and1;
ENTITY stratixgx_nondpa_lvds_receiver is
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
enable1 : in std_logic := '0';
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end stratixgx_nondpa_lvds_receiver;
ARCHITECTURE vital_receiver_atom of stratixgx_nondpa_lvds_receiver is
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal not_clk0 : std_logic;
signal txload_in : std_logic;
signal rxload0 : std_logic;
signal rxload1 : std_logic;
signal rxload2 : std_logic;
signal shift_data : std_logic_vector(channel_width - 1 downto 0);
signal load_data : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal gnd : std_logic := '0';
COMPONENT stratixgx_lvds_rx_parallel_register
GENERIC (
channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT (
clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
reset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
end COMPONENT;
COMPONENT stratixgx_and1
GENERIC (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
PORT (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end COMPONENT;
begin
clkdelaybuffer: stratixgx_and1
PORT map(IN1 => clk0,
Y => clk0_ipd);
dataindelaybuffer: stratixgx_and1
PORT map(IN1 => datain,
Y => datain_ipd);
rxload0_reg: stratixgx_dffe
PORT map(D => enable0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0,
Q => rxload0);
rxload1_reg: stratixgx_dffe
PORT map(D => rxload0,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => clk0,
Q => rxload1);
not_clk0 <= not clk0;
rxload2_reg: stratixgx_dffe
PORT map(D => rxload1,
CLRN => vcc,
PRN => vcc,
ENA => vcc,
CLK => not_clk0,
Q => rxload2);
txload_in <= enable1 when use_enable1 = "true" else
enable0;
load_reg: stratixgx_lvds_rx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => not_clk0,
enable => rxload2,
datain => shift_data,
reset => gnd,
dataout => load_data,
devclrn => devclrn,
devpor => devpor);
output_reg: stratixgx_lvds_rx_parallel_register
GENERIC map(channel_width => channel_width)
PORT map(clk => clk0,
enable => txload_in,
datain => load_data,
reset => gnd,
dataout => dataout,
devclrn => devclrn,
devpor => devpor);
VITAL: process (clk0_ipd, devpor, devclrn)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable shift_out : std_logic;
begin
if (now = 0 ns) then
shift_data <= (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data <= (OTHERS => '0');
else
if (clk0_ipd'event and clk0_ipd = '0') then
for i in channel_width-1 downto 1 loop
shift_data(i) <= shift_data(i-1);
end loop;
shift_data(0) <= datain_ipd;
end if;
end if;
end process;
end vital_receiver_atom;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : STRATIXGX_LVDS_RECEIVER
--
-- Description : Timing simulation model for Stratixgx LVDS_RX.
--
--////////////////////////////////////////////////////////////////////////////--
LIBRARY IEEE, std;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixgx_atom_pack.all;
use std.textio.all;
use work.stratixgx_nondpa_lvds_receiver;
use work.stratixgx_dpa_receiver;
ENTITY stratixgx_lvds_receiver is
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
end stratixgx_lvds_receiver;
ARCHITECTURE vital_stratixgx_lvds_receiver of stratixgx_lvds_receiver is
-- signals for DPA mode
signal dpa_clk0 : std_logic;
signal dpa_coreclk : std_logic;
signal dpa_datain : std_logic;
signal dpa_enable0 : std_logic;
signal dpa_enable1 : std_logic;
signal dpa_dpareset : std_logic;
signal dpa_dpllreset: std_logic;
signal dpa_bitslip : std_logic;
signal dpa_devclrn : std_logic;
signal dpa_devpor : std_logic;
signal dpa_dpalock : std_logic;
signal dpa_dataout : std_logic_vector(channel_width - 1 downto 0);
-- signals for NONDPA mode
signal nondpa_clk0 : std_logic;
signal nondpa_datain : std_logic;
signal nondpa_enable0 : std_logic;
signal nondpa_enable1 : std_logic;
signal nondpa_devclrn : std_logic;
signal nondpa_devpor : std_logic;
signal nondpa_dataout : std_logic_vector(channel_width - 1 downto 0);
signal gnd : std_logic := '0';
COMPONENT stratixgx_nondpa_lvds_receiver
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_enable1 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic;
enable0 : in std_logic;
enable1 : in std_logic := '0';
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
end COMPONENT;
COMPONENT stratixgx_dpa_receiver
GENERIC (
channel_width : integer := 10;
use_enable1 : String := "false";
enable_dpa : String := "off";
dpll_rawperror : String := "off";
dpll_lockwin : integer := 100;
dpll_lockcnt : integer := 1;
enable_fifo : String := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_dpllreset : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01
);
PORT (
clk0 : in std_logic := '0';
coreclk : in std_logic := '0';
enable0 : in std_logic := '0';
enable1 : in std_logic := '0';
datain : in std_logic := '0';
dpareset : in std_logic := '0';
dpllreset : in std_logic := '0';
bitslip : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0);
dpalock : out std_logic
);
end COMPONENT;
begin
-- DPA mode inputs
dpa_clk0 <= clk0 WHEN (enable_dpa = "on") ELSE gnd;
dpa_coreclk <= coreclk WHEN (enable_dpa = "on") ELSE gnd;
dpa_datain <= datain WHEN (enable_dpa = "on") ELSE gnd;
dpa_enable0 <= gnd;
dpa_enable1 <= gnd;
dpa_dpareset <= dpareset WHEN (enable_dpa = "on") ELSE gnd;
dpa_dpllreset <= dpllreset WHEN (enable_dpa = "on") ELSE gnd;
dpa_bitslip <= bitslip WHEN (enable_dpa = "on") ELSE gnd;
dpa_devpor <= devpor WHEN (enable_dpa = "on") ELSE gnd;
dpa_devclrn <= devclrn WHEN (enable_dpa = "on") ELSE gnd;
-- NONDPA mode inputs
nondpa_clk0 <= clk0 WHEN (enable_dpa = "off") ELSE gnd;
nondpa_datain <= datain WHEN (enable_dpa = "off") ELSE gnd;
nondpa_enable0 <= enable0 WHEN (enable_dpa = "off") ELSE gnd;
nondpa_enable1 <= enable1 WHEN (enable_dpa = "off") ELSE gnd;
nondpa_devpor <= devpor WHEN (enable_dpa = "off") ELSE gnd;
nondpa_devclrn <= devclrn WHEN (enable_dpa = "off") ELSE gnd;
-- sub modules
s_nondpa_receiver : stratixgx_nondpa_lvds_receiver
GENERIC map
(
channel_width => channel_width,
use_enable1 => use_enable1,
MsgOn => MsgOn,
XOn => XOn,
MsgOnChecks => MsgOnChecks,
XOnChecks => XOnChecks,
InstancePath => InstancePath,
tpd_clk0_dataout_posedge => tpd_clk0_dataout_posedge,
tipd_clk0 => tipd_clk0,
tipd_enable0 => tipd_enable0,
tipd_enable1 => tipd_enable1,
tipd_datain => tipd_datain
)
PORT map
(
clk0 => nondpa_clk0,
enable0 => nondpa_enable0,
enable1 => nondpa_enable1,
datain => nondpa_datain,
devclrn => nondpa_devclrn,
devpor => nondpa_devpor,
dataout => nondpa_dataout
);
s_dpa_receiver : stratixgx_dpa_receiver
GENERIC map
(
channel_width => channel_width,
use_enable1 => use_enable1,
enable_dpa => enable_dpa,
dpll_rawperror => dpll_rawperror,
dpll_lockwin => dpll_lockwin,
dpll_lockcnt => dpll_lockcnt,
enable_fifo => enable_fifo,
MsgOn => MsgOn,
XOn => XOn,
MsgOnChecks => MsgOnChecks,
XOnChecks => XOnChecks,
InstancePath => InstancePath,
tpd_clk0_dataout_posedge => tpd_clk0_dataout_posedge,
tipd_clk0 => tipd_clk0,
tipd_dpllreset => tipd_dpllreset,
tipd_dpareset => tipd_dpareset
)
PORT map
(
clk0 => clk0,
coreclk => coreclk,
enable0 => enable0,
enable1 => enable1,
datain => datain,
dpareset => dpareset,
dpllreset => dpllreset,
bitslip => bitslip,
devclrn => dpa_devclrn,
devpor => dpa_devpor,
dataout => dpa_dataout,
dpalock => dpa_dpalock
);
-- generate output
dataout <= dpa_dataout WHEN (enable_dpa = "on") ELSE nondpa_dataout;
dpalock <= dpa_dpalock WHEN (enable_dpa = "on") ELSE gnd;
end vital_stratixgx_lvds_receiver;
| gpl-3.0 | 81d4a901dd332cf33aad498486cf3ac9 | 0.500775 | 3.89007 | false | false | false | false |
google/myelin-acorn-electron-hardware | standalone_cartridge_programmer/cpld/standalone_programmer.vhd | 1 | 6,410 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity standalone_programmer is
Port (
-- cartridge address
cart_nINFC,
cart_nINFD,
cart_ROMQA : out std_logic;
cart_A : out std_logic_vector (13 downto 0);
-- cartridge data
cart_D : inout std_logic_vector(7 downto 0);
-- cartridge clock and memory control
cart_PHI0,
cart_16MHZ,
cart_RnW,
cart_nOE,
cart_nOE2 : out std_logic;
-- avr SPI signals
avr_MOSI,
avr_SCK,
cpld_SS : in std_logic;
avr_MISO : out std_logic
--DEBUG avr_MISO2 : in std_logic
);
end standalone_programmer;
architecture Behavioural of standalone_programmer is
--DEBUG signal avr_MISO : std_logic; --DEBUG
--
signal CTL : std_logic_vector (6 downto 0);
signal A : std_logic_vector (15 downto 0);
signal D_from_SPI : std_logic_vector(7 downto 0);
signal D_from_cart : std_logic_vector (7 downto 0);
signal spi_bit_count : std_logic_vector (4 downto 0) := "00000";
signal memory_access : std_logic := '0';
signal read_nwrite : std_logic := '1';
begin
-- hackily using the AVR's SPI clock for both the PHI0 and 16MHZ lines.
cart_PHI0 <= avr_SCK;
cart_16MHZ <= avr_SCK;
-- always drive A, only drive D/nOE/nOE2 during memory access
cart_ROMQA <= A(14);
cart_A <= A(13 downto 0);
cart_RnW <= read_nwrite;
-- nINFC and nINFD for when we're accessing &FCxx or &FDxx
cart_nINFC <= '0' when (memory_access = '1' and A(15 downto 8) = x"FC" and avr_SCK = '1') else '1';
cart_nINFD <= '0' when (memory_access = '1' and A(15 downto 8) = x"FD" and avr_SCK = '1') else '1';
-- nOE for A(15:14) in "00", "01"
cart_nOE <= '0' when (memory_access = '1' and A(15) = '0' and avr_SCK = '1') else '1';
-- nOE2 for A(15:14) = "10"
cart_nOE2 <= '0' when (memory_access = '1' and A(15 downto 14) = "10" and avr_SCK = '1') else '1';
-- D driven on writes, tristated on reads
cart_D <= D_from_SPI when memory_access = '1' and read_nwrite = '0' else "ZZZZZZZZ";
-- AVR sends 0x80 for read, 0x00 for write
read_nwrite <= CTL(6);
process (avr_SCK, cpld_SS)
begin
-- SPI timing with AVR defaults: CPOL=0, CPHA=0
-- Sample on SCK rising edge, setup on SCK falling edge.
-- SS \_____________________________________________________________________________...
-- SCK ___/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__/^^\__
-- MOSI x00000111111222222333333444444555555666666777777000000111111222222333333444444...
-- MISO x00000111111222222333333444444555555666666777777000000111111222222333333444444...
-- This means we get barely any time to think in between bytes -- just the high period of
-- SCK after the 8th bit. We need to set up MISO on the falling edge of avr_SCK.
if cpld_SS = '1' then
-- asynchronous reset (must not happen on an avr_SCK edge)
CTL <= "1111111";
spi_bit_count <= "00000";
A <= "0000000000000000";
D_from_SPI <= "00000000";
elsif rising_edge(avr_SCK) then
-- to read: clock in "1000000" & A15, A14-7, A6-0 & 0, 0x00, and the data byte will come out in the 4th byte
-- to write: clock in "0000000" & A15, A14-7 A6-0 & 0, D, and the byte will be written on the final clock.
-- increment the count each time
spi_bit_count <= std_logic_vector(unsigned(spi_bit_count) + 1);
-- clock in a bit, depending on spi_bit_count
if spi_bit_count(4 downto 3) = "00" then
-- reading CTL (outputting 1 on MISO) and A15
CTL <= CTL(5 downto 0) & A(15);
A(15) <= avr_MOSI;
elsif spi_bit_count(4 downto 3) = "01" or spi_bit_count(4 downto 3) = "10" then
-- reading A (outputting 0 on MISO)
if spi_bit_count /= "10111" then
A(14 downto 0) <= A(13 downto 0) & avr_MOSI;
end if;
else
-- reading or writing data; spi_bit_count(4 downto 3) = "11"
D_from_SPI <= D_from_SPI(6 downto 0) & avr_MOSI;
if spi_bit_count = "11111" then
-- we've just received the last bit of the data byte, which means we should
end if;
end if;
end if;
if cpld_SS = '1' then
avr_MISO <= '0';
D_from_cart <= "10101010";
memory_access <= '0';
elsif falling_edge(avr_SCK) then
-- We always update MISO on an avr_SCK falling edge.
-- memory_access is set to 1 on the falling edge when the avr is setting up
-- the final bit of the address, then back to 0 on the next falling edge.
-- This is so we generate a clean pulse on cart_nOE and cart_nOE2, by ANDing
-- with avr_SCK.
memory_access <= '0';
if spi_bit_count(4 downto 3) = "00" then
-- reading CTL, outputting 1
avr_MISO <= '1';
elsif spi_bit_count(4 downto 3) = "01" or spi_bit_count(4 downto 3) = "10" then
-- reading A, outputting 0
avr_MISO <= '0';
if spi_bit_count = "10110" and read_nwrite = '1' then
-- the AVR is setting up a 0 bit (it's finished sending us the address), so we set
-- memory_access = '1', and the access will occur once avr_SCK goes high again.
memory_access <= '1';
elsif spi_bit_count = "10111" and read_nwrite = '1' then
D_from_cart <= cart_D; -- actually perform the read
end if;
else
-- reading out data register (happens even when nothing is going on)
avr_MISO <= D_from_cart(7);
D_from_cart <= D_from_cart(6 downto 0) & '0';
if spi_bit_count = "11111" and read_nwrite = '0' then
-- we're about to receive the last data bit, and we're doing a write, so we need
-- to get ready to enable nOE etc.
memory_access <= '1';
end if;
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 50b0d897a39e7aaeca87a3b61b613477 | 0.60546 | 3.342023 | false | false | false | false |
migueljiarr/RV32I | src/left_XLEN_barrel_shifter.vhd | 1 | 1,157 | library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity left_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end left_XLEN_barrel_shifter;
architecture structural of left_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= i (30 downto 0) & '0';
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= s1 (29 downto 0) & "00";
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= s2 (27 downto 0) & "0000";
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= s3 (23 downto 0) & "00000000";
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= s4 (15 downto 0) & "0000000000000000";
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
| mit | 96fdbbce80666bb03ef4fddafc49fca1 | 0.618842 | 2.576837 | false | false | false | false |
alvieboy/xtc-base | mt48lc16m16a2.vhd | 1 | 67,726 |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
use work.txt_util.all;
use work.sim.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "sdram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 7 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*4-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hexread(l, rectype);
hexread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hexread(l, recaddr(15 downto 0));
when "0010" =>
hexread(l, recaddr(23 downto 0));
when "0011" =>
hexread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if true then
hexread(l, recdata);
-- Bank_Load := recaddr(25 downto 24);
-- Rows_Load := recaddr(23 downto 11);
-- Cols_Load := recaddr(10 downto 2);
Bank_Load := recaddr(10 downto 9);
Rows_Load := recaddr(23 downto 11); -- 11:0
Cols_Load := recaddr(8 downto 2) & '0';
Init_Mem (Bank_Load, To_Integer(Rows_Load));
-- report "Bank " & str(To_Integer(Bank_Load)) & " Row " & str(To_Integer(Rows_Load)) & " Col " & str(To_Integer(Cols_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
-- report str(To_Integer(Cols_Load)+i)
-- & " "
-- & hstr(std_logic_vector( conv_unsigned((To_Integer(Cols_Load)+i)*2, 32)))
-- & " "
-- & hstr(TO_STDLOGICVECTOR(recdata(i*16+index to i*16+index+15)));
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16+index to i*16+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16+index to i*16+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16+index to i*16+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16+index to i*16+index+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
| bsd-3-clause | d47b06204ed97d847d007549dec25de4 | 0.430366 | 4.0927 | false | false | false | false |
alvieboy/xtc-base | xtc_top_ppro_sdram.vhd | 1 | 6,923 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_top_ppro_sdram is
port (
CLK: in std_logic;
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
DRAM_ADDR : OUT STD_LOGIC_VECTOR (12 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
-- SPI flash
MOSI: out std_logic;
MISO: in std_logic;
SCK: out std_logic;
NCS: out std_logic;
--NNMI: in std_logic;
-- SD card
SDMOSI: out std_logic;
SDMISO: in std_logic;
SDSCK: out std_logic;
SDNCS: out std_logic;
HSYNC: out std_logic;
VSYNC: out std_logic;
BLUE: out std_logic_vector(3 downto 0);
GREEN: out std_logic_vector(3 downto 0);
RED: out std_logic_vector(3 downto 0);
JOY_FIRE2: in std_logic;
JOY_FIRE1: in std_logic;
JOY_LEFT: in std_logic;
JOY_RIGHT: in std_logic;
JOY_SEL: in std_logic;
JOY_UP: in std_logic;
JOY_DOWN: in std_logic;
AUDIO: out std_logic_vector(1 downto 0);
RESET: in std_logic
-- The LED
--LED: out std_logic
);
end entity xtc_top_ppro_sdram;
architecture behave of xtc_top_ppro_sdram is
signal sysrst: std_logic;
signal sysclk: std_logic;
signal clkgen_rst: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal clk_off_3ns: std_ulogic;
signal wbi: wb_mosi_type;
signal wbo: wb_miso_type;
signal dmawbi: wb_mosi_type;
signal dmawbo: wb_miso_type;
signal syscon: wb_syscon_type;
signal swbi: slot_wbi;
signal swbo: slot_wbo;
signal sids: slot_ids;
signal nmi, nmi_q, nmiack, rstreq,rstreq_q, do_reset: std_logic;
signal vgaclk: std_logic;
begin
AUDIO(0) <= '0';
AUDIO(1) <= '0';
process(sysclk)
begin
if rising_edge(sysclk) then
if sysrst='1' then
rstreq_q<='0';
else
rstreq_q<=rstreq;
end if;
end if;
end process;
do_reset<='1' when rstreq_q='0' and rstreq='1' else '0';
syscon.clk<=sysclk;
syscon.rst<=sysrst or do_reset;
cpu: entity work.xtc_top_sdram
port map (
wb_syscon => syscon,
iowbi => wbo,
iowbo => wbi,
nmi => nmi,
nmiack => nmiack,
rstreq => rstreq,
dmawbi => dmawbi,
dmawbo => dmawbo,
-- extra clocking
clk_off_3ns => clk_off_3ns,
-- SDRAM signals
DRAM_ADDR => DRAM_ADDR(11 downto 0),
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
--DRAM_ADDR(12)<='0';
ioctrl: entity work.xtc_ioctrl
port map (
syscon => syscon,
wbi => wbi,
wbo => wbo,
swbi => swbi,
swbo => swbo,
sids => sids
);
myrom: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(0),
wbo => swbi(0)
);
myuart: entity work.uart
generic map (
bits => 11
)
port map (
syscon => syscon,
wbi => swbo(1),
wbo => swbi(1),
tx => TXD,
rx => RXD
);
flashspi: entity work.spi
generic map (
INTERNAL_SPI => true
)
port map (
syscon => syscon,
wbi => swbo(2),
wbo => swbi(2),
mosi => MOSI,
miso => MISO,
sck => SCK,
cs => NCS
);
sdspi: entity work.spi
generic map (
INTERNAL_SPI => false
)
port map (
syscon => syscon,
wbi => swbo(3),
wbo => swbi(3),
mosi => SDMOSI,
miso => SDMISO,
sck => SDSCK,
cs => SDNCS
);
vgaenabled: if false generate
vga: entity work.vga_320_240_idx
port map (
wb_clk_i => syscon.clk,
wb_rst_i => syscon.rst,
wb_dat_o => swbi(4).dat,
wb_dat_i => swbo(4).dat,
wb_adr_i => swbo(4).adr(31 downto 2),
wb_we_i => swbo(4).we,
wb_cyc_i => swbo(4).cyc,
wb_stb_i => swbo(4).stb,
wb_ack_o => swbi(4).ack,
-- Wishbone MASTER interface
mi_wb_dat_i => dmawbo.dat,
mi_wb_dat_o => dmawbi.dat,
mi_wb_adr_o => dmawbi.adr,
mi_wb_sel_o => dmawbi.sel,
--mi_wb_cti_o => dmawbi.cti,
mi_wb_we_o => dmawbi.we,
mi_wb_cyc_o => dmawbi.cyc,
mi_wb_stb_o => dmawbi.stb,
mi_wb_ack_i => dmawbo.ack,
mi_wb_stall_i => dmawbo.stall,
-- VGA signals
vgaclk => vgaclk,
vga_hsync => HSYNC,
vga_vsync => VSYNC,
vga_b(0) => open,
vga_b(4 downto 1) => BLUE,
vga_r(0) => open,
vga_r(4 downto 1) => RED,
vga_g(0) => open,
vga_g(4 downto 1) => GREEN,
blank => open
);
end generate;
vgadisabled: if true generate
eslot: entity work.sinkdev
port map (
syscon => syscon,
wbi => swbo(4),
wbo => swbi(4)
);
dmawbi.dat <= (others => 'X');
dmawbi.adr <= (others => 'X');
dmawbi.sel <= (others => 'X');
dmawbi.we <='0';
dmawbi.cyc<='0';
dmawbi.stb<='0';
RED<=(others => '0');
GREEN<=(others => '0');
BLUE<=(others => '0');
HSYNC<='0';
VSYNC<='0';
end generate;
emptyslots: for N in 5 to 15 generate
eslot: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(N),
wbo => swbi(N)
);
--swbi(N) <= wb_miso_default;
end generate;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
rstgen: entity work.xtc_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => RXD,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: entity work.clkgen
port map (
clkin => clk,
rstin => '0' ,
clkout => sysclk,
clkout1 => clk_off_3ns,
vgaclk => vgaclk,
rstout => clkgen_rst
);
-- NMI
process (sysclk)
begin
if rising_edge(sysclk) then
if sysrst='1' then
nmi <= '0';
else
if RESET='1' then
nmi<='1';
elsif nmiack='1' then
nmi<='0';
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | 2554e8b0e801bf87f0a44a209eca859e | 0.502239 | 3.051124 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_skip.vhd | 1 | 8,083 | -------------------------------------------------------------------------------
--
-- The skip unit.
-- Skip conditions are checked here and communicated to the decoder unit.
--
-- $Id: t400_skip.vhd,v 1.5 2006-06-05 14:20:34 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_skip is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in skip_op_t;
dec_data_i : in dec_data_t;
carry_i : in std_logic;
c_i : in std_logic;
bd_i : in dw_t;
is_lbi_i : in boolean;
skip_o : out boolean;
skip_lbi_o : out boolean;
-- Data Interface ---------------------------------------------------------
a_i : in dw_t;
m_i : in dw_t;
g_i : in dw_t;
tim_c_i : in boolean
);
end t400_skip;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_skip is
signal skip_q,
skip_next_q : boolean;
signal skip_lbi_q : boolean;
signal skip_int_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process skip
--
-- Purpose:
-- Implements the skip logic.
--
skip: process (ck_i, por_i)
variable t420_type_v : boolean;
begin
if por_i then
skip_next_q <= false;
skip_q <= false;
skip_lbi_q <= false;
skip_int_q <= false;
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
skip_next_q <= false;
skip_q <= false;
skip_lbi_q <= false;
skip_int_q <= false;
elsif ck_en_i then
t420_type_v := opt_type_g = t400_opt_type_420_c;
if ck_en_i then
case op_i is
-- update skip information ----------------------------------------
when SKIP_UPDATE =>
skip_q <= skip_next_q;
-- also reset skip_next flag
skip_next_q <= false;
-- reset skip-on-lbi flag when this was not an LBI
if not is_lbi_i then
skip_lbi_q <= false;
end if;
-- skip always ----------------------------------------------------
when SKIP_NOW =>
skip_next_q <= true;
-- skip on carry --------------------------------------------------
when SKIP_CARRY =>
skip_next_q <= carry_i = '1';
-- skip on C ------------------------------------------------------
when SKIP_C =>
skip_next_q <= c_i = '1';
-- skip on BD underflow ------------------------------------------
when SKIP_BD_UFLOW =>
skip_next_q <= unsigned(bd_i) = 15;
-- skip on BD overflow -------------------------------------------
when SKIP_BD_OFLOW =>
skip_next_q <= unsigned(bd_i) = 0;
-- skip on LBI instruction ----------------------------------------
when SKIP_LBI =>
skip_lbi_q <= true;
-- skip on A and M equal ------------------------------------------
when SKIP_A_M =>
skip_next_q <= unsigned(a_i) = unsigned(m_i);
-- skip on G zero -------------------------------------------------
when SKIP_G_ZERO =>
skip_next_q <= unsigned(g_i) = 0;
-- skip on G bit --------------------------------------------------
when SKIP_G_BIT =>
skip_next_q <= unsigned(g_i and dec_data_i(dw_range_t)) = 0;
-- skip on M bit --------------------------------------------------
when SKIP_M_BIT =>
skip_next_q <= unsigned(m_i and dec_data_i(dw_range_t)) = 0;
-- skip on timer carry --------------------------------------------
when SKIP_TIMER =>
skip_next_q <= tim_c_i;
null;
-- push skip state when vectoring to interrupt routine ------------
when SKIP_PUSH =>
if t420_type_v then
-- save next skip flag
skip_int_q <= skip_next_q;
skip_next_q <= false;
-- never skip first instruction of interrupt routine
skip_q <= false;
end if;
-- pop skip state for RET from interrupt routine ------------------
when SKIP_POP =>
if t420_type_v then
-- push'ed info must be pop'ed to skip_next_q as pop'ing
-- happens during RET of interrupt routine
-- skip info is valid for next instruction
skip_next_q <= skip_int_q;
skip_int_q <= false;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process skip;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
skip_o <= skip_q;
skip_lbi_o <= skip_lbi_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/05/28 15:35:33 arniml
-- fix pop'ing of skip flag
--
-- Revision 1.3 2006/05/27 19:16:52 arniml
-- interrupt functionality added
--
-- Revision 1.2 2006/05/20 02:47:52 arniml
-- skip-on-timer implemented
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | 6873c5b5f6267d8187cb05bead773cc1 | 0.469133 | 4.421772 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/alt_dspbuilder_package.vhd | 1 | 50,563 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 7.2)
-- Quartus II development tool and MATLAB/Simulink Interface
--------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package alt_dspbuilder_package is
constant M_MAX : NATURAL := 64;
constant MAXROM : positive := 4096;
constant altversion : string := "DSP Builder - Quartus II development tool and MATLAB/Simulink Interface - Version 7.2";
constant DSPBuilderQTB : string := "on";
constant DSPBuilderVersion : string := "7.2";
constant DSPBuilderProduct : string := "DSP Builder";
Subtype max_vector is Std_Logic_Vector(M_MAX downto 0);
type vector_2D is array(NATURAL RANGE <>) of max_vector;
type STD_LOGIC_2DSPBUILDER is array (NATURAL RANGE <>, NATURAL RANGE <>)of std_logic ;
type STD_LOGIC_3D is array (NATURAL RANGE <>, NATURAL RANGE <>,NATURAL RANGE <>) of std_logic;
type integer_2D is array(NATURAL RANGE <>) of integer;
type LogicalOperator is (AltAND, AltOR, AltXOR, AltNAND, ALtNOR, AltNOT, AltShiftLeft, AltShiftRight, AltRotateRight, AltRotateLeft);
type CompareOperator is (Altaeb, Altaneb, Altagb, Altageb, Altalb, Altaleb);
type AddSubOperator is (AddAdd, AddSub, SubAdd, SubSub);
type BusArithm is (BusIsSigned, BusIsUnsigned, RoundLsb ,TruncateLsb, SaturMsb, TruncateMsb);
type RegisterStructure is (None, DataInputs, MultiplierOutput, DataInputsandMultiplier,
NoRegister, InputsOnly, MultiplierOnly, AdderOnly, InputsandMultiplier,
InputsandAdder,MultiplierandAdder,InputsMultiplierandAdder);
function nbitnecessary(value: integer) return integer;
function Nstd_bitnecessary(DSigned : std_logic_vector) return integer;
function nSignbitnecessary(value: integer) return integer;
function int2ustd(value : integer; width : integer) return std_logic_vector;
function bitvec2std(bv : bit_vector) return std_logic_vector;
function int2sstd(value : integer; width : integer) return std_logic_vector;
function int2bit(value : integer) return std_logic;
function cal_width_lpm_mult(b: boolean ; w : integer) return positive;
function integer_is_even(i: integer ) return boolean;
function ceil_divide(i:integer;d:integer) return integer;
function floor_divide(i:integer;d:integer) return integer;
function ToNatural(i:integer) return integer;
function To_String (Value: Integer) return STRING;
function To_String (Value: Std_logic_vector) return String;
function To_Character (Value: Std_logic) return Character;
function cp_str(s1: string; s2: string) return boolean;
function StdPowerOfTwo(DSigned : std_logic_vector) return integer; -- return -1 if not power of tow otherwisse return power of two
component alt_dspbuilder_SBF
generic (
width_inl : natural ;
width_inr : natural ;
width_outl : natural ;
width_outr : natural ;
round : natural ;
satur : natural ;
lpm_signed : BusArithm
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end component ;
component alt_dspbuilder_SRED
generic (
widthin : natural ;
widthout : natural ;
msb : natural ;
lsb : natural ;
round : natural ;
satur : natural ;
lpm_signed : BusArithm
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component ;
component alt_dspbuilder_SDelay
generic (
lpm_width : positive ;
lpm_delay : positive ;
SequenceLength : positive ;
SequenceValue : std_logic_vector
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_SInitDelay
generic (
lpm_width : positive ;
lpm_delay : positive ;
SequenceLength : positive ;
SequenceValue : std_logic_vector;
ResetValue : std_logic_vector
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_sAltrPropagate
generic (
WIDTH : positive ;
QTB : string;
QTB_PRODUCT : string;
QTB_VERSION : string
);
port (
d : in std_logic_vector(WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0)
);
end component ;
component alt_dspbuilder_sAltrBitPropagate
generic (
QTB : string;
QTB_PRODUCT : string;
QTB_VERSION : string
);
port (
d : in std_logic;
r : out std_logic
);
end component ;
component alt_dspbuilder_UpsampleAltr
generic (
lpm_width : positive ;
SamplingFactor : positive
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component;
component alt_dspbuilder_SDownSampleAltr
generic (
lpm_width : positive ;
SamplingFactor : positive
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component;
component alt_dspbuilder_sBin2BcdAltr
port
(
d : in std_logic_vector (3 downto 0);
r : out std_logic_vector (6 downto 0)
);
end component;
component alt_dspbuilder_SBitLogical
generic (
lpm_width : positive ;
lop : LogicalOperator
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end component;
component alt_dspbuilder_SBusLogical
generic (
lpm_width : positive ;
lop : LogicalOperator ;
mask : natural;
valmask : std_logic_vector;
sgnext_rshift : natural
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_AltiMult
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
dspb_widthr : positive ;
lpm_hint : string ;
cst_val : std_logic_vector ;
one_input : integer ;
pipeline : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector;
lpm : natural );
port (
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0) :=(others=>'0');
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
part_sclr : in std_logic := '0';
result : out std_logic_vector(dspb_widthr-1 downto 0)
);
end component ;
component alt_dspbuilder_BEXT
generic (
delay : integer ;
widthin : positive;
widthout : positive
);
port (
din : in std_logic_vector(widthin-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
sclr : in std_logic;
ena : in std_logic;
dout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_nBEXT
generic (
delay : integer ;
widthin : positive;
widthout : positive
);
port (
din : in std_logic_vector(widthin-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
sclr : in std_logic;
ena : in std_logic;
dout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_IncDecAltr
generic (
lpm_width : positive ;
cst_val : std_logic_vector ;
direction : integer ;
lpm : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector ;
Isunsigned : natural
);
port (
clock : in std_logic :='0';
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_AROUND
generic (
widthin : natural ;
widthout : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component ;
component alt_dspbuilder_SAdderSub
generic (
lpm_width : positive ; -- input bus width
pipeline : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector ;
AddSubVal : AddSubOperator :=AddAdd -- SubSub is illegal
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0) ;
datab : in std_logic_vector(lpm_width-1 downto 0) ;
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
seq_sclr : in std_logic := '0';
result : out std_logic_vector(lpm_width downto 0)
);
end component;
component alt_dspbuilder_ASAT
generic (
widthin : natural ;
widthout : natural ;
lpm_signed : BusArithm
);
port
(
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component ;
component alt_dspbuilder_comparatorAltr
generic (
lpm_width : natural ;
direction : CompareOperator ;
lpm : integer
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic
);
end component ;
component alt_dspbuilder_vecseq
generic (
SequenceLength : positive ;
SequenceValue : std_logic_vector
);
port (
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
sclr : in std_logic ;
yout : out std_logic
);
end component ;
component alt_dspbuilder_seq
generic (
SequenceLength : positive ;
SequenceValue : positive
);
port (
clock : in std_logic ;
ena : in std_logic ;
aclr : in std_logic ;
sclr : in std_logic ;
yout : out std_logic
);
end component ;
component alt_dspbuilder_sync_dpram_single_clock
generic (
lpm_widthad : integer ;
lpm_width : integer
);
port (
wraddress : in std_logic_vector(lpm_widthad-1 downto 0);
rdaddress : in std_logic_vector(lpm_widthad-1 downto 0);
data : in std_logic_vector(lpm_width-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0);
wr : in std_logic ;
rden : in std_logic ;
clock : in std_logic
);
end component;
component alt_dspbuilder_SDpram
generic (
LPM_WIDTH : positive ;
LPM_WIDTHAD : positive ;
ram_block_type : STRING ;
SequenceLength : positive ;
SequenceValue : std_logic_vector
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdaddress : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
wraddress : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
clock : in std_logic ;
wren : in std_logic ;
sclr : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
q : out std_logic_vector(lpm_width-1 downto 0)
);
end component ;
component alt_dspbuilder_SLRom_AltSyncRam
generic
(
width_a : natural ;
widthad_a : natural ;
register_output : string ;
intended_device_family : string ;
init_file : string
);
port
(
address : in std_logic_vector (widthad_a-1 downto 0);
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
clock : in std_logic ;
q : out std_logic_vector (width_a-1 downto 0)
);
end component;
component alt_dspbuilder_SLRom
generic (
LPM_WIDTH : positive;
LPM_WIDTHAD : positive;
SequenceLength : positive;
SequenceValue : std_logic_vector;
XFILE : string;
intended_device_family : string;
stratix_type : natural;
is_unsigned : natural
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
ena : in std_logic :='1';
q : out std_logic_vector(lpm_width+is_unsigned-1 downto 0)
);
end component ;
component alt_dspbuilder_SUsgn
generic (
LPM_WIDTHL : positive ;
LPM_WIDTHR : positive
);
port (
data : in std_logic_vector(LPM_WIDTHL+LPM_WIDTHR-1 downto 0);
q : out std_logic_vector(LPM_WIDTHL downto 0)
);
end component ;
component alt_dspbuilder_SShiftTap
generic (
width : positive ;
number_of_taps : positive ;
use_dedicated_circuitry : natural;
lpm_hint : string ;
tap_distance : positive
);
port (
data : in std_logic_vector(width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
ena : in std_logic;
taps : out std_logic_vector(width*number_of_taps-1 downto 0);
shiftout : out std_logic_vector(width-1 downto 0)
);
end component ;
component alt_dspbuilder_AltiSMac
generic (
width_a : positive ;
width_b : positive ;
width_result : positive ;
use_dedicated_circuitry : natural ;
RegStruct : RegisterStructure
);
port (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC := '1';
accum_sload : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
aclr : IN STD_LOGIC := '0';
result : out STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
overflow : OUT STD_LOGIC
);
end component ;
component alt_dspbuilder_AltiSMacMF
generic (
width_a : positive ;
width_b : positive ;
width_result : positive ;
RegStruct : RegisterStructure
);
port (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC := '1';
accum_sload : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
aclr : IN STD_LOGIC := '0';
result : out STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
overflow : OUT STD_LOGIC
);
end component ;
component alt_dspbuilder_AltiSMacUsg
generic (
width_a : positive ;
width_b : positive ;
width_result : positive ;
use_dedicated_circuitry : natural ;
RegStruct : RegisterStructure
);
port (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC := '1';
accum_sload : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '1';
ena : IN STD_LOGIC := '1';
aclr : IN STD_LOGIC := '0';
user_aclr : IN STD_LOGIC := '0';
result : out STD_LOGIC_VECTOR (width_result-1 DOWNTO 0);
overflow : OUT STD_LOGIC
);
end component ;
component alt_dspbuilder_CST_MULT is
GENERIC (
widthin : positive ;
widthcoef : positive ;
widthr : positive ;
cst : std_logic_vector ;
lpm_hint : string ;
pipeline : natural );
PORT (
clock : in std_logic;
aclr : in std_logic;
part_sclr : in std_logic := '0';
ena : in std_logic;
data : in std_logic_vector (widthin-1 DOWNTO 0);
result : out std_logic_vector (widthr-1 DOWNTO 0)
);
end component ;
component alt_dspbuilder_MultAdd
generic (
width_a : positive ;
width_r : positive ;
direction : AddSubOperator ;
nMult : positive ;
intended_device_family : string;
use_dedicated_circuitry : natural ;
representation : string ;
regstruct : registerstructure
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat3ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
clock : in std_logic := '1';
ena : in std_logic := '1';
part_sclr : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
result : out std_logic_vector (width_r-1 downto 0)
);
end component ;
component alt_dspbuilder_MultAddMF
generic (
width_a : positive ;
width_r : positive ;
direction : AddSubOperator ;
nMult : positive ;
intended_device_family : string ;
representation : string ;
regstruct : registerstructure
);
port (
dat1aa : in std_logic_vector (width_a-1 downto 0);
dat1ab : in std_logic_vector (width_a-1 downto 0);
dat2aa : in std_logic_vector (width_a-1 downto 0);
dat2ab : in std_logic_vector (width_a-1 downto 0);
dat3aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat3ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4aa : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
dat4ab : in std_logic_vector (width_a-1 downto 0):=(others=>'0');
clock : in std_logic := '1';
ena : in std_logic := '1';
aclr : in std_logic := '0';
result : out std_logic_vector (width_r-1 downto 0)
);
end component ;
component alt_dspbuilder_signaltapunit
generic (upper_limit: integer ;
lower_limit: integer );
port(
data_in : in std_logic_vector(upper_limit downto lower_limit);
data_out : out std_logic_vector(upper_limit downto lower_limit));
end component ;
component alt_dspbuilder_CplxMult
generic (
width : positive
);
port (
dataareal : in std_logic_vector (width-1 downto 0);
dataaimag : in std_logic_vector (width-1 downto 0);
databreal : in std_logic_vector (width-1 downto 0);
databimag : in std_logic_vector (width-1 downto 0);
resultreal : out std_logic_vector (2*width downto 0):=(others=>'0');
resultimag : out std_logic_vector (2*width downto 0):=(others=>'0')
);
end component ;
component alt_dspbuilder_AltMultConst
generic (
CA : std_logic_vector ;
CB : std_logic_vector ;
CC : std_logic_vector ;
CD : std_logic_vector ;
width_a : positive ;
width_r : positive ;
regstruct : registerstructure :=NoRegister
);
port (
datain : in std_logic_vector (width_a-1 downto 0);
datbin : in std_logic_vector (width_a-1 downto 0);
datcin : in std_logic_vector (width_a-1 downto 0);
datdin : in std_logic_vector (width_a-1 downto 0);
dataout : out std_logic_vector (width_r-1 downto 0);
clock : in std_logic := '1';
ena : in std_logic := '1';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic := '0'
);
end component ;
component alt_dspbuilder_Par2Ser
generic (
msbfirst : boolean ;
repeatlastbit : boolean ;
widthin : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0):=(others=>'0');
ena : in std_logic :='1';
load : in std_logic :='0';
clock : in std_logic;
aclr : in std_logic :='0';
sclr : in std_logic :='0';
sout : out std_logic
);
end component;
component alt_dspbuilder_Ser2Par
generic (
msbfirst : boolean ;
widthin : natural
);
port (
sin : in std_logic :='0';
clock : in std_logic ;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
xout : out std_logic_vector(widthin-1 downto 0)
);
end component ;
component alt_dspbuilder_dividerAltr
generic (
widthin : natural;
isunsigned : natural ;
pipeline : natural
);
port
(
clock : in std_logic := '0';
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
clken : in std_logic := '1';
numer : in std_logic_vector (widthin-1 downto 0);
denom : in std_logic_vector (widthin-1 downto 0);
quotient : out std_logic_vector (widthin-1 downto 0);
remain : out std_logic_vector (widthin-1 downto 0)
);
end component ;
component alt_dspbuilder_butterflyAltr
generic (
WidthIn : positive ;
WidthOut : positive ;
WidthOutLsb : natural ;
pipeline : natural;
W_is_constant : natural;
W_real : std_logic_vector;
W_imag : std_logic_vector;
lpm_hint : string;
DecimationInTime : natural
);
port (
clock : in std_logic:= '0';
aclr : in std_logic:= '0' ;
user_aclr : in std_logic:= '0' ;
ena : in std_logic:= '1' ;
part_sclr : in std_logic:= '0' ;
areal : in std_logic_vector (WidthIn-1 downto 0);
aimag : in std_logic_vector (WidthIn-1 downto 0);
breal : in std_logic_vector (WidthIn-1 downto 0);
bimag : in std_logic_vector (WidthIn-1 downto 0);
wreal : in std_logic_vector (WidthIn-1 downto 0);
wimag : in std_logic_vector (WidthIn-1 downto 0);
rAreal : out std_logic_vector (WidthOut-1 downto 0);
rAimag : out std_logic_vector (WidthOut-1 downto 0);
rBreal : out std_logic_vector (WidthOut-1 downto 0);
rBimag : out std_logic_vector (WidthOut-1 downto 0)
);
end component ;
component alt_dspbuilder_sLpmAddSub
generic
(
width : positive;
isunsigned : natural;
pipeline : natural
);
port
(
add_sub : in std_logic ;
dataa : in std_logic_vector (width-1 downto 0);
datab : in std_logic_vector (width-1 downto 0);
cin : in std_logic :='0';
clock : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
clken : in std_logic :='1';
result : out std_logic_vector (width-1 downto 0);
cout : out std_logic
);
end component;
component alt_dspbuilder_sLpmCount
GENERIC
(
width : NATURAL ;
modulus : NATURAL
);
PORT
(
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
sload : IN STD_LOGIC ;
updown : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sIntegratorAltr
GENERIC
(
width : natural ;
depth : positive
);
PORT
(
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clk_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sdecoderaltr
GENERIC
(
width : NATURAL ;
pipeline : NATURAL ;
decode : std_logic_vector
);
PORT
(
clock : in std_logic;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
dec : OUT STD_LOGIC
);
end component;
component alt_dspbuilder_sDifferentiatorAltr
GENERIC
(
width : natural ;
depth : positive
);
PORT
(
data : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clk_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sFir4TapCoefSerialAltr
GENERIC
(
representation : STRING;
width : NATURAL
);
PORT
(
clock0 : IN STD_LOGIC ;
dataa_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
datab_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
ena0 : IN STD_LOGIC ;
shiftouta : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
shiftoutb : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (2*width+1 DOWNTO 0)
);
end component;
component alt_dspbuilder_sFir4TapCoefParAltr
GENERIC
(
representation : STRING;
Ntap : NATURAL;
width : NATURAL
);
PORT
(
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
ena : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
coef_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
coef_1 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
coef_2 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
coef_3 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
sout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (2*width+1 DOWNTO 0)
);
end component;
component alt_dspbuilder_sFir2TapCoefParAltr
GENERIC
(
representation : STRING;
Ntap : NATURAL;
width : NATURAL
);
PORT
(
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
user_aclr : IN STD_LOGIC ;
ena : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
coef_0 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
coef_1 : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) ;
sout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (2*width DOWNTO 0)
);
end component;
component alt_dspbuilder_DFFEALTR
GENERIC
(
width : NATURAL
);
PORT
(
d : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
clock : IN STD_LOGIC;
ena : IN STD_LOGIC;
prn : IN STD_LOGIC;
clrn : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_TFFEALTR
GENERIC
(
width : NATURAL
);
PORT
(
t : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
clock : IN STD_LOGIC;
ena : IN STD_LOGIC;
prn : IN STD_LOGIC;
clrn : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width-1 DOWNTO 0)
);
END component;
component alt_dspbuilder_sCFifoAltr
generic
(
width : natural ;
widthud : natural ;
numwords : natural ;
lpm_hint : string ;
intended_device_family : string ;
showahead_mode : string ;
use_eab : string
);
port
(
data : in std_logic_vector (width-1 downto 0);
wrreq : in std_logic ;
rdreq : in std_logic ;
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
sclr : in std_logic ;
q : out std_logic_vector (width-1 downto 0);
full : out std_logic ;
empty : out std_logic ;
usedw : out std_logic_vector (widthud-1 downto 0)
);
end component;
component alt_dspbuilder_sRounderAltr
generic (
widthin : natural;
widthout : natural ;
bround : natural ;
pipeline : natural ;
lpm_representation: string
);
port (
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_ASATPIPE
generic (
widthin : natural ;
widthout : natural ;
bsat : natural ;
lpm_signed : BusArithm ;
pipeline : natural ;
UseCustomValue : natural ;
UpperValue : std_logic_vector ;
LowerValue : std_logic_vector
);
port (
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
ena : in std_logic;
sclr : in std_logic;
xin : in std_logic_vector(widthin-1 downto 0);
sat_flag : out std_logic;
yout : out std_logic_vector(widthout-1 downto 0)
);
end component;
component alt_dspbuilder_BarrelShiftAltr
generic (
widthin : natural ;
widthd : natural ;
pipeline : natural ;
ndirection : natural ;
use_dedicated_circuitry : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
ena : in std_logic;
clock : in std_logic;
aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end component;
component alt_dspbuilder_BarrelShiftAltrUsg
generic (
widthin : natural ;
widthd : natural ;
pipeline : natural ;
ndirection : natural ;
use_dedicated_circuitry : natural
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
distance : in std_logic_vector(widthd-1 downto 0);
sclr : in std_logic;
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
direction : in std_logic;
yout : out std_logic_vector(widthin-1 downto 0)
);
end component;
component alt_dspbuilder_sLFSRAltr
generic (
width : natural ;
LFSRPrimPoly : std_logic_vector ;
RegisterInitialValuesBin : std_logic_vector ;
LFSRstructure : natural;
XorType : natural
);
port (
sclr : in std_logic;
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
ena : in std_logic;
sout : out std_logic;
pout : out std_logic_vector(width-1 downto 0)
);
end component;
component alt_dspbuilder_sMultiBitAddSub
generic (
NumberOfInputBits : positive ;
dspb_widthr : positive ;
pipeline : natural ;
lpm_widthcoef : positive ;
coef0 : std_logic_vector ;
coef1 : std_logic_vector ;
coef2 : std_logic_vector ;
coef3 : std_logic_vector ;
coef4 : std_logic_vector ;
coef5 : std_logic_vector ;
coef6 : std_logic_vector ;
coef7 : std_logic_vector
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
sclr : in std_logic;
dataa : in std_logic_vector(NumberOfInputBits-1 downto 0);
result : out std_logic_vector(dspb_widthr-1 downto 0)
);
end component;
component alt_dspbuilder_sDAMultAddAltr
generic (
nTap : positive ;
widthdata : positive ;
widthrbit : positive ;
widthr : positive ;
widtho : positive ;
vlsb : natural ;
pipeline : natural ;
widthcoef : positive ;
lpm_hint : string ;
coef0 : std_logic_vector ;
coef1 : std_logic_vector ;
coef2 : std_logic_vector ;
coef3 : std_logic_vector ;
coef4 : std_logic_vector ;
coef5 : std_logic_vector ;
coef6 : std_logic_vector ;
coef7 : std_logic_vector
);
port (
clock : in std_logic:='0';
ena : in std_logic:='1';
user_aclr : in std_logic:='0';
aclr : in std_logic:='0';
part_sclr : in std_logic:='0';
dataa0 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa1 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa2 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa3 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa4 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa5 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa6 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
dataa7 : in std_logic_vector(widthdata-1 downto 0):=(others=>'0');
result : out std_logic_vector(widtho-vlsb-1 downto 0)
);
end component;
component alt_dspbuilder_sMultAltr
generic (
lpm_widtha : positive ;
lpm_widthb : positive ;
lpm_representation : string ;
lpm_hint : string ;
OutputMsb : natural ;
OutputLsb : natural ;
pipeline : natural
);
port (
clock : in std_logic;
ena : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
datab : in std_logic_vector(lpm_widthb-1 downto 0);
result : out std_logic_vector(OutputMsb-OutputLsb downto 0)
);
end component;
component alt_dspbuilder_sBitWiseBusOpaltr
generic (
lpm_width : positive ;
Lop : LogicalOperator
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end component;
component alt_dspbuilder_sPaddAltr
generic (
width : positive ;
size : positive ;
pipeline : natural ;
SequenceLength : positive ;
SequenceValue : std_logic_vector ;
widthr : positive
);
port (
dataa : in std_logic_vector(width*size-1 downto 0);
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
result : out std_logic_vector(widthr-1 downto 0)
);
end component;
component alt_dspbuilder_sMuxAltr
generic ( lpm_pipeline : NATURAL:=0;
lpm_size : positive;
lpm_widths : positive;
lpm_width : positive;
SelOneHot : natural);
PORT ( clock : in std_logic ;
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
ena : in std_logic := '1';
data : in std_logic_vector (lpm_width*lpm_size-1 downto 0);
sel : in std_logic_vector (lpm_widths-1 downto 0);
result : out std_logic_vector (lpm_width-1 downto 0));
end component;
component alt_dspbuilder_ClkDivAltr
GENERIC
(
widthcnt : NATURAL
);
PORT
(
aclr : IN STD_LOGIC;
clock : IN STD_LOGIC ;
clock_out : out STD_LOGIC
);
end component;
COMPONENT alt_dspbuilder_parallel_add_db
GENERIC (
width : NATURAL;
representation : STRING;
size : NATURAL;
msw_subtract : STRING;
pipeline : NATURAL;
result_alignment : STRING;
widthr : NATURAL;
shift : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_2DSPBUILDER (size-1 DOWNTO 0, width-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (widthr-1 DOWNTO 0)
);
END COMPONENT;
component alt_dspbuilder_SDemuxAltr
generic (
width : natural ;
widthsel : natural ;
size : natural
);
port (
din : in std_logic_vector(width-1 downto 0);
sel : in std_logic_vector(widthsel-1 downto 0);
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
result : out std_logic_vector(size*width-1 downto 0)
);
end component ;
component alt_dspbuilder_sDcFifoAltr
generic (
intended_device_family : STRING;
lpm_width : NATURAL;
lpm_numwords : NATURAL;
lpm_hint : STRING;
clocks_are_synchronized : STRING;
lpm_widthu : NATURAL);
port (data : in STD_LOGIC_VECTOR (lpm_width-1 downto 0);
wrclk : in STD_LOGIC ;
aclr : in STD_LOGIC ;
user_aclr : in STD_LOGIC ;
rdreq : in STD_LOGIC ;
wrreq : in STD_LOGIC ;
rdclk : in STD_LOGIC ;
rdfull : out STD_LOGIC ;
rdempty : out STD_LOGIC ;
wrusedw : out STD_LOGIC_VECTOR (lpm_widthu-1 downto 0):=(others=>'0');
wrfull : out STD_LOGIC ;
wrempty : out STD_LOGIC ;
q : out STD_LOGIC_VECTOR (lpm_width-1 downto 0);
rdusedw : out STD_LOGIC_VECTOR (lpm_widthu-1 downto 0):=(others=>'0'));
end component;
component alt_dspbuilder_sSqrAltr
generic ( lpm_width : positive;
q_port_width : positive;
r_port_width : positive;
pipeline : NATURAL);
port ( radical : in STD_LOGIC_VECTOR (lpm_width-1 downto 0);
clock : in STD_LOGIC;
aclr : in STD_LOGIC;
user_aclr : in STD_LOGIC;
ena : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (q_port_width-1 downto 0);
remainder : out STD_LOGIC_VECTOR (r_port_width-1 downto 0));
end component;
component alt_dspbuilder_sStepAltr
generic (
StepDelay : positive ;
direction : natural
);
port (
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulse11Altr
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulse1nAltr
generic (
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulsen1Altr
generic (
Impulsedelay : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulsennAltr
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic ;
ena : in std_logic ;
sclr : in std_logic ;
aclr : in std_logic :='0';
q : out std_logic
);
end component ;
component alt_dspbuilder_sImpulseAltr
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic;
sclr : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
q : out std_logic
);
end component ;
component alt_dspbuilder_jtag_node is
generic (
width : positive := 8;
-- Node Info ID that uniquely identifies a instance of the node.
-- MFG ID: 110 (0x6E)
-- NODE ID: 6 (0x6) (HIL)
-- Version: 0 (0x0)
-- Instance ID: 0 (0x0)
sld_node_info : positive := 3173888); -- 0x00306E00
port (
-- Shared JTAG ports
raw_tck : in std_logic; -- JTAG test clock
raw_tms : in std_logic; -- JTAG test mode select signal
tdi : in std_logic; -- JTAG test data input, comes LSB first
jtag_state_tlr : in std_logic; -- Signals that the JSM is in the Test_Logic_Reset state
jtag_state_rti : in std_logic; -- Signals that the JSM is in the Run_Test/Idle state
jtag_state_sdrs : in std_logic; -- Signals that the JSM is in the Select_DR_Scan state
jtag_state_cdr : in std_logic; -- Signals that the JSM is in the Capture_DR state
jtag_state_sdr : in std_logic; -- Signals that the JSM is in the Shift_DR state
jtag_state_e1dr : in std_logic; -- Signals that the JSM is in the Exit1_DR state
jtag_state_pdr : in std_logic; -- Signals that the JSM is in the Pause_DR state
jtag_state_e2dr : in std_logic; -- Signals that the JSM is in the Exit2_DR state
jtag_state_udr : in std_logic; -- Signals that the JSM is in the Update_DR state
jtag_state_sirs : in std_logic; -- Signals that the JSM is in the Select_IR_Scan state
jtag_state_cir : in std_logic; -- Signals that the JSM is in the Capture_IR state
jtag_state_sir : in std_logic; -- Signals that the JSM is in the Shift_IR state
jtag_state_e1ir : in std_logic; -- Signals that the JSM is in the Exit1_IR state
jtag_state_pir : in std_logic; -- Signals that the JSM is in the Pause_IR state
jtag_state_e2ir : in std_logic; -- Signals that the JSM is in the Exit2_IR state
jtag_state_uir : in std_logic; -- Signals that the JSM is in the Update_IR state
usr1 : in std_logic; -- Signals that the current instruction in the JSM is the USER1 instruction
clrn : in std_logic; -- Asynchronous clear
-- Node-specific JTAG ports
ena : in std_logic; -- Indicates that the current instruction in the Hub is for Node i
ir_in : in std_logic_vector(width-1 downto 0); -- Node i IR
tdo : out std_logic; -- Node i JTAG test data out
ir_out : out std_logic_vector(width-1 downto 0); -- Node i IR capture port
-- Interface to node
user_clk : in std_logic;
user_tck : out std_logic;
node_state_uir : out std_logic;
node_state_sdr : out std_logic;
user_tdi : out std_logic;
user_tdo : out std_logic;
user_IRin : out std_logic_vector(width-1 downto 0);
user_IRout : in std_logic_vector(width-1 downto 0);
user_cir : out std_logic; -- Capture IR
user_sir : out std_logic; -- Shift IR
user_uir : out std_logic; -- Update IR
user_cdr : out std_logic; -- Capture DR
user_sdr : out std_logic; -- Shift DR
user_udr : out std_logic); -- Update DR
end component;
component alt_dspbuilder_clock_crossing_enable is
port (
source_clk : in std_logic;
source_ena : in std_logic;
dest_clk : in std_logic;
dest_ena : out std_logic);
end component;
end alt_dspbuilder_package ;
package body alt_dspbuilder_package is
function nbitnecessary(value: integer) return integer is
-- return the number of bit necessary to code the positive value-1
variable inc: integer ;
variable tmp: integer ;
begin
tmp := value-1;
inc := 0;
if (tmp>0) then
for i in 0 to value+1 loop
if (tmp > 0 ) then
tmp := tmp / 2;
inc := inc +1;
end if ;
end loop ;
else
inc :=0;
end if ;
return inc;
end nbitnecessary;
function nSignbitnecessary(value: integer) return integer is
-- return the number of bit necessary to code value-1
variable inc: integer ;
variable ttmp: integer ;
variable tmp: integer ;
begin
if (value<0) then
ttmp:=-value;
else
ttmp:=value;
end if;
tmp := ttmp;
inc := 0;
if (ttmp>0) then
for i in 0 to ttmp+2 loop
if (tmp > 0 ) then
tmp := tmp / 2;
inc := inc +1;
end if ;
end loop ;
else
inc :=1;
end if ;
return inc+1;
end nSignbitnecessary;
function Nstd_bitnecessary(DSigned : std_logic_vector) return integer is
-- return the number of bit necessary for teh signed inpt constant
-- of type std_logic_vector
constant w : integer :=DSigned'Length;
variable r : integer :=w;
variable d : integer :=w-2;
constant svec : std_logic_vector(w-1 downto 0):=DSigned;
begin
if (d>0) then
if (svec(w-1)='0') then
while (svec(d)='0' and d>0) loop
d:=d-1;
end loop;
else
while (svec(d)='1' and d>0) loop
d:=d-1;
end loop;
end if;
d:=d+2;
if (d<r) then
r := d;
end if;
end if;
return r;
end Nstd_bitnecessary;
function StdPowerOfTwo(DSigned : std_logic_vector) return integer is -- return 0 if not power of tow otherwisse return power of two
constant w : integer :=DSigned'Length;
variable r : integer :=0;
variable p : integer :=0;
variable np : integer :=0;
constant svec : std_logic_vector(w-1 downto 0):=DSigned;
begin
for i in 0 to w-1 loop
if svec(i) = '1' then
p:=i;
np:=np+1;
end if;
end loop;
if (np=1) then
r:= p;
end if;
return r;
end;
function int2ustd(value : integer; width : integer) return std_logic_vector is
-- convert integer to unsigned std_logicvector
begin
return conv_std_logic_vector(CONV_UNSIGNED(value, width ), width);
end int2ustd;
function int2sstd(value : integer; width : integer) return std_logic_vector is
-- convert integer to signed std_logicvector
begin
if (value<0) then
return conv_std_logic_vector(CONV_UNSIGNED(((2**(width))+value), width ), width);
else
return conv_std_logic_vector(CONV_UNSIGNED(value, width ), width);
end if;
end int2sstd;
function int2bit(value : integer) return std_logic is
-- convert integer to signed std_logicvector
begin
if (value>0) then
return '1';
else
return '0';
end if;
end int2bit;
function bitvec2std(bv : bit_vector) return std_logic_vector is
-- convert bit_vector to std_logic_vector
variable s : std_logic_vector(bv'length-1 downto 0) :=(others=>'0');
begin
for i in 0 to bv'length-1 loop
if '1'=bv(i) then
s(i) :='1';
else
s(i) :='0';
end if;
end loop;
return s;
end bitvec2std;
function cal_width_lpm_mult(b: boolean ; w : integer) return positive is
-- Check if the multipler reach the max negative number
variable i : positive;
begin
if b then
i := w-1;
else
i := w;
end if;
return i;
end cal_width_lpm_mult;
function integer_is_even(i: integer ) return boolean is
variable even : boolean;
begin
even:= ((i+1)/2) = (i/2);
return even;
end integer_is_even;
function ceil_divide(i:integer;d:integer) return integer is
variable res : integer;
begin
if d/=0 then
if ((i rem d)>0) then
res := i/d+1;
else
res := i/d;
end if ;
else
res :=0;
end if ;
return res;
end ;
function floor_divide(i:integer;d:integer) return integer is
begin
if d/=0 then
return i/d;
else
return 0;
end if ;
end ;
function ToNatural(i:integer) return integer is
variable inc: integer ;
begin
if (i<0) then
inc := 0;
else
inc :=i;
end if ;
return inc;
end ;
function To_String (Value: Integer) return String is
variable V: Integer;
variable Result: String(1 to 11);
variable Width: Natural := 0;
begin
V := abs Value;
for I in Result'Reverse_range loop
case V mod 10 is
when 0 => Result(I) := '0';
when 1 => Result(I) := '1';
when 2 => Result(I) := '2';
when 3 => Result(I) := '3';
when 4 => Result(I) := '4';
when 5 => Result(I) := '5';
when 6 => Result(I) := '6';
when 7 => Result(I) := '7';
when 8 => Result(I) := '8';
when 9 => Result(I) := '9';
when others =>
Result(I) := '?';
end case;
if V > 0 then
Width := Width + 1;
end if;
V := V / 10;
end loop;
if Width = 0 then
Width := 1;
end if;
if Value < 0 then
Result(Result'Length - Width) := '-';
Width := Width + 1;
end if;
return Result(Result'Length - Width + 1 to Result'Length);
end To_String;
function To_Character (Value: Std_logic) return Character is
begin
case Value is
when 'U' => return 'U';
when 'X' => return 'X';
when '0' => return '0';
when '1' => return '1';
when 'W' => return 'W';
when 'L' => return 'L';
when 'H' => return 'H';
when 'Z' => return 'Z';
when '-' => return '-';
end case;
end To_Character;
function To_String (Value: Std_logic_vector) return String is
constant V: Std_logic_vector(1 to Value'Length) := Value;
variable Result: String(1 to Value'Length);
begin
for I in Result'Range loop
Result(I) := To_character(V(I));
end loop;
return Result;
end To_String;
function cp_str(s1: string; s2: string) return boolean is
variable b : boolean :=false;
begin
if (s1'Length=s2'Length) then
if s1=s2 then
b:=true;
end if;
end if;
return b;
end cp_str;
end alt_dspbuilder_package;
| gpl-3.0 | 92e9d4c095d304264c6b17fe3a44a33f | 0.582738 | 2.98871 | false | false | false | false |
alvieboy/xtc-base | tb_sdram.vhd | 1 | 4,974 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
use work.wishbonepkg.all;
entity tb_sdram_flash is
end entity tb_sdram_flash;
architecture sim of tb_sdram_flash is
constant period: time := 10 ns;--9.615 ns;
signal w_clk: std_logic := '0';
signal w_clk_2x: std_logic := '1';
signal w_rst: std_logic := '0';
-- SDRAM signals
signal DRAM_ADDR : STD_LOGIC_VECTOR (12 downto 0);
signal DRAM_BA : STD_LOGIC_VECTOR (1 downto 0);
signal DRAM_CAS_N : STD_LOGIC;
signal DRAM_CKE : STD_LOGIC;
signal DRAM_CLK : STD_LOGIC;
signal DRAM_CS_N : STD_LOGIC;
signal DRAM_DQ : STD_LOGIC_VECTOR(15 downto 0);
signal DRAM_DQM : STD_LOGIC_VECTOR(1 downto 0);
signal DRAM_RAS_N : STD_LOGIC;
signal DRAM_WE_N : STD_LOGIC;
signal txd, rxd: std_logic;
signal w_clk_3ns: std_logic;
signal miso, mosi, sck, sel: std_logic;
signal vcc: real := 0.0;
signal wbi: wb_mosi_type;
signal wbo: wb_miso_type;
signal syscon: wb_syscon_type;
signal swbi: slot_wbi;
signal swbo: slot_wbo;
signal sids: slot_ids;
signal nmi, nmiack: std_logic;
begin
rxd <= '1';
w_clk <= not w_clk after period/2;
w_clk_3ns<=transport w_clk after 3 ns;
wbo.stall <= '0';
syscon.clk<=w_clk;
syscon.rst<=w_rst;
cpu: entity work.xtc_top_sdram
port map (
wb_syscon => syscon,
-- Master wishbone interface
iowbi => wbo,
iowbo => wbi,
nmi => nmi,
nmiack => nmiack,
dmawbi.dat => (others => 'X'),
dmawbi.adr => (others => 'X'),
dmawbi.tag => (others => 'X'),
dmawbi.cyc => '0',
dmawbi.bte => BTE_BURST_LINEAR,
dmawbi.cti => CTI_CYCLE_CLASSIC,
dmawbi.stb => '0',
dmawbi.we => '0',
dmawbi.sel => "0000",
clk_off_3ns => w_clk_3ns,
DRAM_ADDR => DRAM_ADDR(11 downto 0),
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N
);
DRAM_ADDR(12)<='0';
sdram: entity work.mt48lc16m16a2
GENERIC MAP (
addr_bits => 13,
data_bits => 16,
col_bits => 8,
index => 0,
fname => "sdram.srec"
)
PORT MAP (
Dq => DRAM_DQ,
Addr => DRAM_ADDR(12 downto 0),
Ba => DRAM_BA,
Clk => DRAM_CLK,
Cke => DRAM_CKE,
Cs_n => DRAM_CS_N,
Ras_n => DRAM_RAS_N,
Cas_n => DRAM_CAS_N,
We_n => DRAM_WE_N,
Dqm => DRAM_DQM
);
ioctrl: entity work.xtc_ioctrl
port map (
syscon => syscon,
wbi => wbi,
wbo => wbo,
swbi => swbi,
swbo => swbo,
sids => sids
);
nodev0: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(0),
wbo => swbi(0)
);
myuart: entity work.uart
port map (
syscon => syscon,
wbi => swbo(1),
wbo => swbi(1),
tx => open,
rx => 'X'
);
flashspi: entity work.spi
generic map (
INTERNAL_SPI => true
)
port map (
syscon => syscon,
wbi => swbo(2),
wbo => swbi(2),
mosi => mosi,
miso => miso,
sck => sck,
cs => sel
);
sdspi: entity work.spi
generic map (
INTERNAL_SPI => false
)
port map (
syscon => syscon,
wbi => swbo(3),
wbo => swbi(3),
mosi => open,
miso => '0',
sck => open,
cs => open
);
emptyslots: for N in 4 to 15 generate
eslot: entity work.nodev
port map (
syscon => syscon,
wbi => swbo(N),
wbo => swbi(N)
);
end generate;
flash: entity work.M25P16
PORT map (
VCC => vcc,
C => sck,
D => mosi,
S => sel,
W => '1',
HOLD => '1',
Q => miso);
vcc<=3.3 after 10 ns;
-- Reset procedure
process
begin
w_rst<='0';
wait for period;
w_rst<='1';
wait for period;
w_rst<='0';
wait;
end process;
-- Interrupt test
--process
--begin
-- wbo.int <= '0';
-- wait for 2060 ns;
-- wbo.int <= '1';
-- wait for 150 ns;
-- wbo.int <= '0';
--end process;
-- NMI test
--process
--begin
-- nmi<='0';
-- wait for 8000 ns;
-- wait until rising_edge(w_clk);
-- nmi<='1';
-- wait until nmiack='1';
-- wait until rising_edge(w_clk);
-- nmi<='0';
-- wait for 10000 ns;
-- nmi<='1';
-- wait until nmiack='1';
-- wait until rising_edge(w_clk);
-- nmi<='0';
-- wait;
--end process;
end sim;
| bsd-3-clause | dc46cac4f2bf434575d6ba9c59adfd01 | 0.483916 | 3.083695 | false | false | false | false |
freecores/t400 | rtl/vhdl/t400_sio.vhd | 1 | 9,100 | -------------------------------------------------------------------------------
--
-- The serial input/output unit.
--
-- $Id: t400_sio.vhd,v 1.3 2006-05-07 02:24:16 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
use work.t400_opt_pack.all;
entity t400_sio is
generic (
opt_so_output_type_g : integer := t400_opt_out_type_std_c;
opt_sk_output_type_g : integer := t400_opt_out_type_std_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
phi1_i : in std_logic;
out_en_i : in boolean;
in_en_i : in boolean;
-- Control Interface ------------------------------------------------------
op_i : in sio_op_t;
en0_i : in std_logic;
en3_i : in std_logic;
-- SIO Interface ----------------------------------------------------------
a_i : in dw_t;
c_i : in std_logic;
sio_o : out dw_t;
-- Pad Interface ----------------------------------------------------------
si_i : in std_logic;
so_o : out std_logic;
so_en_o : out std_logic;
sk_o : out std_logic;
sk_en_o : out std_logic
);
end t400_sio;
library ieee;
use ieee.numeric_std.all;
use work.t400_io_pack.all;
architecture rtl of t400_sio is
signal si_q : std_logic;
type si_flt_t is (SI_LOW_0, SI_LOW_1,
SI_HIGH_0, SI_HIGH_1);
signal si_flt_s,
si_flt_q : si_flt_t;
signal si_0_ok_s,
si_1_ok_s : boolean;
signal si_0_ok_q,
si_1_ok_q : boolean;
signal dec_sio_s : boolean;
signal new_sio_s,
sio_q : unsigned(dw_range_t);
signal skl_q : std_logic;
signal phi1_en_q : std_logic;
signal so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements.
--
seq: process (ck_i, por_i)
begin
if por_i then
sio_q <= (others => '0');
skl_q <= '1';
phi1_en_q <= '1';
si_q <= '1';
si_flt_q <= SI_LOW_0;
si_0_ok_q <= false;
si_1_ok_q <= false;
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
skl_q <= '1';
phi1_en_q <= '1';
else
if in_en_i then
-- sample asynchronous SI input
si_q <= si_i;
end if;
if out_en_i then
-- SI filter FSM
si_flt_q <= si_flt_s;
-- SI low/high markers
si_0_ok_q <= si_0_ok_s;
si_1_ok_q <= si_1_ok_s;
end if;
-- SIO shift register / counter
if op_i = SIO_LOAD and ck_en_i then
-- parallel update has priority
sio_q <= unsigned(a_i);
skl_q <= c_i;
else
sio_q <= new_sio_s;
end if;
if ck_en_i then
-- delay enable of PHI1 by one clock cycle
-- this prevents glitches on sk_o when enabling/disabling
-- sk_o as a clock output
phi1_en_q <= skl_q;
end if;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process new_sio
--
-- Purpose:
-- Calculates the new value of SIO.
-- Splitting this from the sequential process is required to deliver
-- the transient new value of SIO to sio_o upon reading SIO.
--
new_sio: process (out_en_i,
en0_i,
sio_q,
si_q,
dec_sio_s)
begin
-- default value
new_sio_s <= sio_q;
if out_en_i then
if en0_i = '0' then
-- shift register mode
new_sio_s(3 downto 1) <= sio_q(2 downto 0);
new_sio_s(0) <= si_q;
else
-- counter mode
if dec_sio_s then
new_sio_s <= sio_q - 1;
end if;
end if;
end if;
end process new_sio;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process si_sample
--
-- Purpose:
-- Implements the low pass filter on SI for low and high levels.
--
si_sample: process (si_q,
si_flt_q,
si_0_ok_q, si_1_ok_q)
begin
-- default assignments
si_flt_s <= si_flt_q;
si_0_ok_s <= si_0_ok_q;
si_1_ok_s <= si_1_ok_q;
dec_sio_s <= false;
case si_flt_q is
when SI_LOW_0 =>
if si_q = '0' then
si_flt_s <= SI_LOW_1;
else
si_flt_s <= SI_HIGH_0;
end if;
when SI_LOW_1 =>
if si_q = '0' then
si_0_ok_s <= true; -- enough '0' on SI
if not si_0_ok_q and si_1_ok_q then
-- decrement counter if durations of high and low phases
-- were long enough
dec_sio_s <= true;
end if;
else
si_flt_s <= SI_HIGH_0;
si_1_ok_s <= false; -- restart measuring
end if;
when SI_HIGH_0 =>
si_1_ok_s <= false; -- restart marker
if si_q = '1' then
si_flt_s <= SI_HIGH_1;
else
si_flt_s <= SI_LOW_0;
end if;
when SI_HIGH_1 =>
if si_q = '1' then
si_1_ok_s <= true; -- enough '1' on SI
else
si_flt_s <= SI_LOW_0;
si_0_ok_s <= false; -- restart measuring
end if;
when others =>
null;
end case;
end process si_sample;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
sio_o <= std_logic_vector(new_sio_s);
so_s <= en3_i and (en0_i or sio_q(3));
sk_s <= phi1_en_q and (en0_i or phi1_i);
so_o <= io_out_f(dat => so_s, opt => opt_so_output_type_g);
so_en_o <= io_en_f (en => vdd_s,
dat => so_s, opt => opt_so_output_type_g);
sk_o <= io_out_f(dat => sk_s, opt => opt_sk_output_type_g);
sk_en_o <= io_en_f (en => vdd_s,
dat => sk_s, opt => opt_sk_output_type_g);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/06 13:34:58 arniml
-- phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 | d8ed483225f1dc08c98ea255bd966ed0 | 0.478901 | 3.663446 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixii_atoms.vhd | 1 | 672,856 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixii_pllpack;
package body stratixii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixii_dffe : entity is TRUE;
end stratixii_dffe;
-- architecture body --
architecture behave of stratixii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
entity stratixii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixii_mux21 : entity is TRUE;
end stratixii_mux21;
architecture AltVITAL of stratixii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
entity stratixii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_mux41 : entity is TRUE;
end stratixii_mux41;
architecture AltVITAL of stratixii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixii_atom_pack.all;
-- entity declaration --
entity stratixii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixii_and1 : entity is TRUE;
end stratixii_and1;
-- architecture body --
architecture AltVITAL of stratixii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
----------------------------------------------------------------------------
-- Module Name : stratixii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixii_ram_register;
ARCHITECTURE reg_arch OF stratixii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixii_ram_pulse_generator:ENTITY IS TRUE;
END stratixii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_ram_register;
USE work.stratixii_ram_pulse_generator;
ENTITY stratixii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixii_ram_block;
ARCHITECTURE block_arch OF stratixii_ram_block IS
COMPONENT stratixii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := (ram_block_type = "M-RAM" OR ram_block_type = "m-ram" OR ram_block_type = "MegaRAM" OR
(ram_block_type = "auto" AND mixed_port_feed_through_mode = "dont_care" AND port_b_read_enable_write_enable_clock = "clock0"));
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,rewe_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,rewe_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL rewe_b_reg : STD_LOGIC;
SIGNAL rewe_b_reg_in,rewe_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_in_vec,active_b_in_vec,active_a_out,active_b_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_a,active_b : BOOLEAN;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0' WHEN (port_a_data_in_clear = "none" OR port_a_data_in_clear = "UNUSED") ELSE clr0;
datain_b_clr_in <= '0' WHEN (port_b_data_in_clear = "none" OR port_b_data_in_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_in_clear = "clear0") ELSE clr1;
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0' WHEN (port_a_byte_enable_clear = "none" OR port_a_byte_enable_clear = "UNUSED") ELSE clr0;
byteena_b_clr_in <= '0' WHEN (port_b_byte_enable_clear = "none" OR port_b_byte_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_byte_enable_clear = "clear0") ELSE clr1;
we_a_clr_in <= '0' WHEN (port_a_write_enable_clear = "none" OR port_a_write_enable_clear = "UNUSED") ELSE clr0;
rewe_b_clr_in <= '0' WHEN (port_b_read_enable_write_enable_clear = "none" OR port_b_read_enable_write_enable_clear = "UNUSED") ELSE
clr0 WHEN (port_b_read_enable_write_enable_clear = "clear0") ELSE clr1;
active_a_in <= '1' WHEN (port_a_disable_ce_on_input_registers = "on") ELSE ena0;
active_b_in <= '1' WHEN (port_b_disable_ce_on_input_registers = "on") ELSE
ena0 WHEN (port_b_read_enable_write_enable_clock = "clock0") ELSE ena1;
-- Store clock enable value for SEAB/MEAB
-- A port active
active_a_in_vec(0) <= active_a_in;
active_port_a : stratixii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_out
);
active_a <= (active_a_out(0) = '1');
active_write_a <= active_a AND (byteena_a_reg /= bytes_a_disabled);
-- B port active
active_b_in_vec(0) <= active_b_in;
active_port_b : stratixii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
stall => wire_gnd,
ena => wire_vcc,
q => active_b_out
);
active_b <= (active_b_out(0) = '1');
active_write_b <= active_b AND (byteena_b_reg /= bytes_b_disabled);
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_in,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- address
addr_a_register : stratixii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read/write enable
rewe_b_reg_in(0) <= portbrewe;
rewe_b_register : stratixii_ram_register
GENERIC MAP (
width => 1,
preset => bool_to_std_logic(mode_is_dp)
)
PORT MAP (
d => rewe_b_reg_in,
clk => clk_b_in,
aclr => rewe_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => rewe_b_reg_out,
aclrout => rewe_b_clr
);
rewe_b_reg <= rewe_b_reg_out(0);
-- address
addr_b_register : stratixii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in WHEN ram_type ELSE (NOT clk_a_in);
wpgen_a_clkena <= '1' WHEN (active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in WHEN ram_type ELSE (NOT clk_b_in);
wpgen_b_clkena <= '1' WHEN (active_write_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
wpgen_b : stratixii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN (active_b AND mode_is_dp AND (rewe_b_reg = '1')) OR
(active_b AND mode_is_bdp AND (rewe_b_reg = '0'))
ELSE '0';
rpgen_b : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
pulse => read_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a AND (NOT mode_is_dp) AND (we_a_reg = '1')) ELSE '0';
ftpgen_a : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b AND mode_is_bdp AND (rewe_b_reg = '1')) ELSE '0';
ftpgen_b : stratixii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a AND we_a_reg = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,rewe_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_b AND ((mode_is_dp AND rewe_b_reg = '1') OR (mode_is_bdp AND rewe_b_reg = '0'))) THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((rewe_b_clr'EVENT AND rewe_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (rewe_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- ------ Output registers
clkena_a_out <= '1' WHEN (port_a_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_a_data_out_clock = "clock0") ELSE ena1;
clkena_b_out <= '1' WHEN (port_b_disable_ce_on_output_registers = "on") ELSE
ena0 WHEN (port_b_data_out_clock = "clock0") ELSE ena1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-------------------------------------------------------------------
--
-- Entity Name : stratixii_jtag
--
-- Description : StratixII JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
entity stratixii_jtag is
generic (
lpm_type : string := "stratixii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixii_jtag;
architecture architecture_jtag of stratixii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixii_crcblock
--
-- Description : StratixII CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
entity stratixii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "stratixii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixii_crcblock;
architecture architecture_crcblock of stratixii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
-------------------------------------------------------------------
--
-- Entity Name : stratixii_asmiblock
--
-- Description : StratixII ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixii_atom_pack.all;
entity stratixii_asmiblock is
generic (
lpm_type : string := "stratixii_asmiblock"
);
port (dclkin : in std_logic;
scein : in std_logic;
sdoin : in std_logic;
oe : in std_logic;
data0out: out std_logic);
end stratixii_asmiblock;
architecture architecture_asmiblock of stratixii_asmiblock is
begin
process(dclkin, scein, sdoin, oe)
begin
end process;
end architecture_asmiblock; -- end of stratixii_asmiblock
---------------------------------------------------------------------
--
-- Entity Name : stratixii_lcell_ff
--
-- Description : StratixII LCELL_FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_and1;
entity stratixii_lcell_ff is
generic (
x_on_violation : string := "on";
lpm_type : string := "stratixii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_lcell_ff : entity is TRUE;
end stratixii_lcell_ff;
architecture vital_lcell_ff of stratixii_lcell_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal datain_dly : std_logic;
signal adatasdata_ipd : std_logic;
signal adatasdata_dly : std_logic;
signal adatasdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal aclr_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
dataindelaybuffer: stratixii_and1
port map(IN1 => datain_ipd,
Y => datain_dly);
adatasdatadelaybuffer: stratixii_and1
port map(IN1 => adatasdata_ipd,
Y => adatasdata_dly);
adatasdatadelaybuffer1: stratixii_and1
port map(IN1 => adatasdata_dly,
Y => adatasdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (adatasdata_ipd, adatasdata, tipd_adatasdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, datain_dly, adatasdata_dly1,
sclr_ipd, sload_ipd, aclr_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_adatasdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_adatasdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(aload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_adatasdata_clk,
TimingData => TimingData_adatasdata_clk,
TestSignal => adatasdata_ipd,
TestSignalName => "ADATASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_adatasdata_clk_noedge_posedge,
SetupLow => tsetup_adatasdata_clk_noedge_posedge,
HoldHigh => thold_adatasdata_clk_noedge_posedge,
HoldLow => thold_adatasdata_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_adatasdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (aclr_ipd = '1')) then
iregout := '0';
elsif (aload_ipd = '1') then
iregout := adatasdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iregout := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iregout := '0';
elsif (sload_ipd = '1') then
iregout := adatasdata_dly1;
else
iregout := datain_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => iregout,
Paths => (0 => (aclr_ipd'last_event, tpd_aclr_regout_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_regout_posedge, TRUE),
2 => (adatasdata_ipd'last_event, tpd_adatasdata_regout, TRUE),
3 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
---------------------------------------------------------------------
--
-- Entity Name : stratixii_lcell_comb
--
-- Description : StratixII LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "stratixii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_lcell_comb : entity is TRUE;
end stratixii_lcell_comb;
architecture vital_lcell_comb of stratixii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_ena_reg : entity is TRUE;
end stratixii_ena_reg;
ARCHITECTURE behave of stratixii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/ENA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for StratixII CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_ena_reg;
entity stratixii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_clkctrl : entity is TRUE;
end stratixii_clkctrl;
architecture vital_clkctrl of stratixii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component stratixii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : stratixii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg_out
);
outclk <= cereg_out AND clkmux_out;
end vital_clkctrl;
--
--
-- STRATIXII_ASYNCH_IO Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_asynch_io is
generic(
operation_mode : STRING := "input";
open_drain_output : STRING := "false";
bus_hold : STRING := "false";
dqs_input_frequency : STRING := "10000 ps";
dqs_out_mode : STRING := "none";
dqs_delay_buffer_mode : STRING := "low";
dqs_phase_shift : INTEGER := 0;
dqs_offsetctrl_enable : STRING := "false";
dqs_ctrl_latches_enable : STRING := "false";
dqs_edge_detect_enable : STRING := "false";
gated_dqs : STRING := "false";
sim_dqs_intrinsic_delay : INTEGER := 0;
sim_dqs_delay_increment : INTEGER := 0;
sim_dqs_offset_increment : INTEGER := 0;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_datain_padio : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_posedge : VitalDelayType01 := DefPropDelay01;
tpd_oe_padio_negedge : VitalDelayType01 := DefPropDelay01;
tpd_padio_combout : VitalDelayType01 := DefPropDelay01;
tpd_regin_regout : VitalDelayType01 := DefPropDelay01;
tpd_ddioregin_ddioregout : VitalDelayType01 := DefPropDelay01;
tpd_padio_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_regin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_padio : VitalDelayType01 := DefPropDelay01;
tipd_dqsupdateen : VitalDelayType01 := DefPropDelay01;
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01));
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout : out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC
);
attribute VITAL_LEVEL0 of stratixii_asynch_io : entity is TRUE;
end stratixii_asynch_io;
architecture behave of stratixii_asynch_io is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd, oe_ipd, padio_ipd: std_logic;
signal delayctrlin_in : std_logic_vector(5 downto 0);
signal offsetctrlin_in : std_logic_vector(5 downto 0);
signal dqsupdateen_in : std_logic;
signal dqs_delay_int : integer := 0;
signal tmp_dqsbusout : std_logic;
signal dqs_ctrl_latches_ena : std_logic := '1';
signal combout_tmp_sig : std_logic := '0';
signal dqsbusout_tmp_sig : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (padio_ipd, padio, tipd_padio);
VitalWireDelay (delayctrlin_in(5), delayctrlin(5), tipd_delayctrlin(5));
VitalWireDelay (delayctrlin_in(4), delayctrlin(4), tipd_delayctrlin(4));
VitalWireDelay (delayctrlin_in(3), delayctrlin(3), tipd_delayctrlin(3));
VitalWireDelay (delayctrlin_in(2), delayctrlin(2), tipd_delayctrlin(2));
VitalWireDelay (delayctrlin_in(1), delayctrlin(1), tipd_delayctrlin(1));
VitalWireDelay (delayctrlin_in(0), delayctrlin(0), tipd_delayctrlin(0));
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
VitalWireDelay (offsetctrlin_in(5), offsetctrlin(5), tipd_offsetctrlin(5));
VitalWireDelay (offsetctrlin_in(4), offsetctrlin(4), tipd_offsetctrlin(4));
VitalWireDelay (offsetctrlin_in(3), offsetctrlin(3), tipd_offsetctrlin(3));
VitalWireDelay (offsetctrlin_in(2), offsetctrlin(2), tipd_offsetctrlin(2));
VitalWireDelay (offsetctrlin_in(1), offsetctrlin(1), tipd_offsetctrlin(1));
VitalWireDelay (offsetctrlin_in(0), offsetctrlin(0), tipd_offsetctrlin(0));
end block;
dqs_ctrl_latches_ena <= '1' when dqs_ctrl_latches_enable = "false" ELSE
dqsupdateen_in when dqs_edge_detect_enable = "false" ELSE
(not (combout_tmp_sig xor tmp_dqsbusout) and dqsupdateen_in);
process(delayctrlin_in, offsetctrlin_in, dqs_ctrl_latches_ena)
variable tmp_delayctrl : integer := 0;
variable tmp_offsetctrl : integer := 0;
begin
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
tmp_delayctrl := 31;
else
tmp_delayctrl := alt_conv_integer(delayctrlin_in);
end if;
if (dqs_offsetctrl_enable = "true") then
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
tmp_offsetctrl := 31;
else
tmp_offsetctrl := alt_conv_integer(offsetctrlin_in);
end if;
else
tmp_offsetctrl := 0;
end if;
if (dqs_ctrl_latches_ena = '1') THEN
dqs_delay_int <= sim_dqs_intrinsic_delay + sim_dqs_delay_increment*tmp_delayctrl + sim_dqs_offset_increment*tmp_offsetctrl;
end if;
if ((dqs_delay_buffer_mode = "high") AND (delayctrlin_in(5) = '1')) THEN
assert false report "DELAYCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
if ((dqs_delay_buffer_mode = "high") AND (offsetctrlin_in(5) = '1')) THEN
assert false report "OFFSETCTRLIN of DQS I/O exceeds 5-bit range in high-frequency mode" severity warning;
end if;
end process;
VITAL: process(padio_ipd, datain_ipd, oe_ipd, regin, ddioregin, tmp_dqsbusout)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
variable padio_VitalGlitchData : VitalGlitchDataType;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable ddioregout_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_padio : std_logic;
variable prev_value : std_logic := 'H';
variable dqsbusout_tmp : std_logic;
variable combout_delay : VitalDelayType01 := (0 ps, 0 ps);
variable init : boolean := true;
begin
if (init) then
combout_delay := tpd_padio_combout;
init := false;
end if;
if (bus_hold = "true" ) then
if ( operation_mode = "input") then
if ( padio_ipd = 'Z') then
tmp_combout := to_x01z(prev_value);
else
if ( padio_ipd = '1') then
prev_value := 'H';
elsif ( padio_ipd = '0') then
prev_value := 'L';
else
prev_value := 'W';
end if;
tmp_combout := to_x01z(padio_ipd);
end if;
tmp_padio := 'Z';
elsif ( operation_mode = "output" or operation_mode = "bidir") then
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
prev_value := 'L';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
prev_value := 'W';
else -- 'Z'
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
end if;
else
tmp_padio := datain_ipd;
if ( datain_ipd = '1') then
prev_value := 'H';
elsif (datain_ipd = '0' ) then
prev_value := 'L';
elsif ( datain_ipd = 'X') then
prev_value := 'W';
else
prev_value := datain_ipd;
end if;
end if; -- end open_drain_output
elsif ( oe_ipd = '0' ) then
-- need to update prev_value
if (padio_ipd = '1') then
prev_value := 'H';
elsif (padio_ipd = '0') then
prev_value := 'L';
elsif (padio_ipd = 'X') then
prev_value := 'W';
end if;
tmp_padio := prev_value;
else
tmp_padio := 'X';
prev_value := 'W';
end if; -- end oe_in
if ( operation_mode = "bidir") then
tmp_combout := to_x01z(padio_ipd);
else
tmp_combout := 'Z';
end if;
end if;
if ( now <= 1 ps AND prev_value = 'W' ) then --hack for autotest to pass
prev_value := 'L';
end if;
else -- bus_hold is false
if ( operation_mode = "input") then
tmp_combout := padio_ipd;
tmp_padio := 'Z';
elsif (operation_mode = "output" or operation_mode = "bidir" ) then
if ( operation_mode = "bidir") then
tmp_combout := padio_ipd;
else
tmp_combout := 'Z';
end if;
if ( oe_ipd = '1') then
if ( open_drain_output = "true" ) then
if (datain_ipd = '0') then
tmp_padio := '0';
elsif (datain_ipd = 'X') then
tmp_padio := 'X';
else
tmp_padio := 'Z';
end if;
else
tmp_padio := datain_ipd;
end if;
elsif ( oe_ipd = '0' ) then
tmp_padio := 'Z';
else
tmp_padio := 'X';
end if;
end if;
end if; -- end bus_hold
tmp_dqsbusout <= transport tmp_combout after (dqs_delay_int * 1 ps);
if (gated_dqs = "true") then
dqsbusout_tmp := tmp_dqsbusout AND regin;
else
dqsbusout_tmp := tmp_dqsbusout;
end if;
-- for dqs delay ctrl latches enable
dqsbusout_tmp_sig <= dqsbusout_tmp;
combout_tmp_sig <= tmp_combout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "combout",
OutTemp => tmp_combout,
Paths => (1 => (padio_ipd'last_event, combout_delay, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => dqsbusout_tmp,
Paths => (1 => (tmp_dqsbusout'last_event, tpd_padio_dqsbusout, TRUE),
2 => (regin'last_event, tpd_regin_dqsbusout, gated_dqs = "true")),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => padio,
OutSignalName => "padio",
OutTemp => tmp_padio,
Paths => (1 => (datain_ipd'last_event, tpd_datain_padio, TRUE),
2 => (oe_ipd'last_event, tpd_oe_padio_posedge, oe_ipd = '1'),
3 => (oe_ipd'last_event, tpd_oe_padio_negedge, oe_ipd = '0')),
GlitchData => padio_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "regout",
OutTemp => regin,
Paths => (1 => (regin'last_event, tpd_regin_regout, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => ddioregout,
OutSignalName => "ddioregout",
OutTemp => ddioregin,
Paths => (1 => (ddioregin'last_event, tpd_ddioregin_ddioregout, TRUE)),
GlitchData => ddioregout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
-- STRATIXII_IO_REGISTER
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_io_register is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_io_register : entity is TRUE;
end stratixii_io_register;
architecture vital_io_reg of stratixii_io_register is
attribute VITAL_LEVEL0 of vital_io_reg : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_reg;
--
-- STRATIXII_IO_LATCH
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
entity stratixii_io_latch is
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_io_latch : entity is TRUE;
end stratixii_io_latch;
architecture vital_io_latch of stratixii_io_latch is
attribute VITAL_LEVEL0 of vital_io_latch : architecture is TRUE;
signal datain_ipd, ena_ipd, sreset_ipd : std_logic;
signal clk_ipd, areset_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
VitalWireDelay (areset_ipd, areset, tipd_areset);
end block;
VITALtiming : process(clk_ipd, datain_ipd, ena_ipd, sreset_ipd, areset_ipd, devclrn, devpor)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable Tviol_sreset_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sreset_clk : VitalTimingDataType := VitalTimingDataInit;
variable regout_VitalGlitchData : VitalGlitchDataType;
variable iregout : std_logic;
variable idata : std_logic := '0';
variable tmp_regout : std_logic;
variable tmp_reset : std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
end if;
if ( async_reset /= "none") then
tmp_reset := areset_ipd; -- this is used to enable timing check.
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sreset_clk,
TimingData => TimingData_sreset_clk,
TestSignal => sreset_ipd,
TestSignalName => "SRESET",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sreset_clk_noedge_posedge,
SetupLow => tsetup_sreset_clk_noedge_posedge,
HoldHigh => thold_sreset_clk_noedge_posedge,
HoldLow => thold_sreset_clk_noedge_posedge,
CheckEnabled => TO_X01((tmp_reset) OR (NOT devpor) OR (NOT devclrn) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_datain_clk or Tviol_ena_clk or Tviol_sreset_clk;
if (devpor = '0') then
if (power_up = "low") then
iregout := '0';
elsif (power_up = "high") then
iregout := '1';
end if;
elsif (devclrn = '0') then
iregout := '0';
elsif (async_reset = "clear" and areset_ipd = '1') then
iregout := '0';
elsif ( async_reset = "preset" and areset_ipd = '1') then
iregout := '1';
elsif (violation = 'X') then
iregout := 'X';
elsif (ena_ipd = '1' and clk_ipd = '1') then
if (sync_reset = "clear" and sreset_ipd = '1' ) then
iregout := '0';
elsif (sync_reset = "preset" and sreset_ipd = '1' ) then
iregout := '1';
else
iregout := to_x01z(datain_ipd);
end if;
end if;
tmp_regout := iregout;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => regout,
OutSignalName => "REGOUT",
OutTemp => tmp_regout,
Paths => (0 => (areset_ipd'last_event, tpd_areset_regout_posedge, async_reset /= "none"),
1 => (clk_ipd'last_event, tpd_clk_regout_posedge, TRUE)),
GlitchData => regout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_io_latch;
--
-- STRATIXII_IO
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_asynch_io;
use work.stratixii_io_register;
use work.stratixii_io_latch;
use work.stratixii_mux21;
use work.stratixii_and1;
entity stratixii_io is
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "stratixii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
end stratixii_io;
architecture structure of stratixii_io is
component stratixii_asynch_io
generic(
operation_mode : string := "input";
open_drain_output : string := "false";
bus_hold : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0);
port(
datain : in STD_LOGIC := '0';
oe : in STD_LOGIC := '1';
regin : in std_logic;
ddioregin : in std_logic;
padio : inout STD_LOGIC;
delayctrlin : in std_logic_vector(5 downto 0);
offsetctrlin : in std_logic_vector(5 downto 0);
dqsupdateen : in std_logic;
dqsbusout : out std_logic;
combout: out STD_LOGIC;
regout : out STD_LOGIC;
ddioregout : out STD_LOGIC);
end component;
component stratixii_io_register
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component stratixii_io_latch
generic (
async_reset : string := "none";
sync_reset : string := "none";
power_up : string := "low";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sreset_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_areset_regout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01
);
port (
clk :in std_logic := '0';
datain : in std_logic := '0';
ena : in std_logic := '1';
sreset : in std_logic := '0';
areset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
end component;
component stratixii_mux21
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component stratixii_and1
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (
Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
signal oe_out : std_logic;
signal in_reg_out, in_ddio0_reg_out, in_ddio1_reg_out: std_logic;
signal oe_reg_out, oe_pulse_reg_out : std_logic;
signal out_reg_out, out_ddio_reg_out: std_logic;
signal tmp_datain : std_logic;
signal not_inclk, not_outclk : std_logic;
-- for DDIO
signal ddio_data : std_logic;
signal outclk_delayed : std_logic;
signal out_clk_ena, oe_clk_ena : std_logic;
begin
not_inclk <= (ddioinclk) WHEN (ddioinclk_input = "dqsb_bus") ELSE (not inclk);
not_outclk <= not outclk;
out_clk_ena <= '1' WHEN tie_off_output_clock_enable = "true" ELSE outclkena;
oe_clk_ena <= '1' WHEN tie_off_oe_clock_enable = "true" ELSE outclkena;
--input register
in_reg : stratixii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map ( regout => in_reg_out,
clk => inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio0_reg
in_ddio0_reg : stratixii_io_register
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => input_sync_reset,
POWER_UP => input_power_up)
port map (regout => in_ddio0_reg_out,
clk => not_inclk,
ena => inclkena,
datain => padio,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- in_ddio1_latch
in_ddio1_reg : stratixii_io_latch
generic map ( ASYNC_RESET => input_async_reset,
SYNC_RESET => "none", -- this register does not have sync_reset
POWER_UP => input_power_up)
port map (regout => in_ddio1_reg_out,
clk => inclk,
ena => inclkena,
datain => in_ddio0_reg_out,
areset => areset,
devpor => devpor,
devclrn => devclrn);
-- out_reg
out_reg : stratixii_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => datain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- out ddio reg
out_ddio_reg : stratixii_io_register
generic map ( ASYNC_RESET => output_async_reset,
SYNC_RESET => output_sync_reset,
POWER_UP => output_power_up)
port map (regout => out_ddio_reg_out,
clk => outclk,
ena => out_clk_ena,
datain => ddiodatain,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe reg
oe_reg : stratixii_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_reg_out,
clk => outclk,
ena => oe_clk_ena,
datain => oe,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
-- oe_pulse reg
oe_pulse_reg : stratixii_io_register
generic map (ASYNC_RESET => oe_async_reset,
SYNC_RESET => oe_sync_reset,
POWER_UP => oe_power_up)
port map (regout => oe_pulse_reg_out,
clk => not_outclk,
ena => oe_clk_ena,
datain => oe_reg_out,
areset => areset,
sreset => sreset,
devpor => devpor,
devclrn => devclrn);
oe_out <= (oe_pulse_reg_out and oe_reg_out) WHEN (extend_oe_disable = "true") ELSE oe_reg_out WHEN (oe_register_mode = "register") ELSE oe;
sel_delaybuf : stratixii_and1
port map (Y => outclk_delayed,
IN1 => outclk);
ddio_data_mux : stratixii_mux21
port map (MO => ddio_data,
A => out_ddio_reg_out,
B => out_reg_out,
S => outclk_delayed);
tmp_datain <= ddio_data WHEN (ddio_mode = "output" or ddio_mode = "bidir") ELSE
out_reg_out WHEN (output_register_mode = "register") ELSE
datain;
-- timing info in case output and/or input are not registered.
inst1 : stratixii_asynch_io
generic map ( OPERATION_MODE => operation_mode,
OPEN_DRAIN_OUTPUT => open_drain_output,
BUS_HOLD => bus_hold,
dqs_input_frequency => dqs_input_frequency,
dqs_out_mode => dqs_out_mode,
dqs_delay_buffer_mode => dqs_delay_buffer_mode,
dqs_phase_shift => dqs_phase_shift,
dqs_offsetctrl_enable => dqs_offsetctrl_enable,
dqs_ctrl_latches_enable => dqs_ctrl_latches_enable,
dqs_edge_detect_enable => dqs_edge_detect_enable,
gated_dqs => gated_dqs,
sim_dqs_intrinsic_delay => sim_dqs_intrinsic_delay,
sim_dqs_delay_increment => sim_dqs_delay_increment,
sim_dqs_offset_increment => sim_dqs_offset_increment)
port map( datain => tmp_datain,
oe => oe_out,
regin => in_reg_out,
ddioregin => in_ddio1_reg_out,
padio => padio,
delayctrlin => delayctrlin,
offsetctrlin => offsetctrlin,
dqsupdateen => dqsupdateen,
dqsbusout => dqsbusout,
combout => combout,
regout => regout,
ddioregout => ddioregout);
end structure;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_m_cntr
--
-- Description : Timing simulation model for the M counter. M is the loop
-- feedback counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixii_m_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixii_m_cntr;
ARCHITECTURE behave of stratixii_m_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_n_cntr
--
-- Description : Timing simulation model for the N counter. N is the
-- input counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixii_n_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixii_n_cntr;
ARCHITECTURE behave of stratixii_n_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
variable clk_last_valid_value : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = 'X') then
ASSERT FALSE REPORT "Invalid transition to 'X' detected on PLL input clk. This edge will be ignored." severity warning;
elsif (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
if (clk /= 'X') then
clk_last_valid_value := clk;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixii_scale_cntr;
ARCHITECTURE behave of stratixii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixii_pll_reg;
ARCHITECTURE behave of stratixii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 6 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad, clkloss and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_pllpack.all;
USE work.stratixii_m_cntr;
USE work.stratixii_n_cntr;
USE work.stratixii_scale_cntr;
USE work.stratixii_dffe;
USE work.stratixii_pll_reg;
ENTITY stratixii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
-- LVDS mode parameters
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixii_pll";
-- Simulation only generics
family_name : string := "StratixII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
-- lvds specific ports
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END stratixii_pll;
ARCHITECTURE vital_pll of stratixii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer;
signal i_vco_max : integer;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 5) := (OTHERS => 0);
signal c_high_val : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val : int_array(0 to 5) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 5) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 5);
-- old values
signal c_high_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 5);
-- hold registers
signal c_high_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 5) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 5);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
signal sig_c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal sig_c_hi_val_tmp : int_array(0 to 5) := (OTHERS => 1);
signal c_ph_val_orig : int_array(0 to 5) := (OTHERS => 0);
--signal i_clk5_counter : string(1 to 2) := "c5";
--signal i_clk4_counter : string(1 to 2) := "c4";
--signal i_clk3_counter : string(1 to 2) := "c3";
--signal i_clk2_counter : string(1 to 2) := "c2";
--signal i_clk1_counter : string(1 to 2) := "c1";
--signal i_clk0_counter : string(1 to 2) := "c0";
signal i_clk5_counter : integer := 5;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT GPP_SCAN_CHAIN : integer := 174;
CONSTANT FAST_SCAN_CHAIN : integer := 75;
CONSTANT GATE_LOCK_CYCLES : integer := 7;
CONSTANT cntrs : str_array(5 downto 0) := (" C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (57, 16, 36, 5);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (18, 13, 8, 2);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (6, 12, 30, 36, 52, 57, 72, 77, 92, 96, 110, 114, 127, 131, 144, 148);
CONSTANT loop_filter_r_arr : str_array1(0 to 39) := (" 1.000000", " 1.500000", " 2.000000", " 2.500000", " 3.000000", " 3.500000", " 4.000000", " 4.500000", " 5.000000", " 5.500000", " 6.000000", " 6.500000", " 7.000000", " 7.500000", " 8.000000", " 8.500000", " 9.000000", " 9.500000", "10.000000", "10.500000", "11.000000", "11.500000", "12.000000", "12.500000", "13.000000", "13.500000", "14.000000", "14.500000", "15.000000", "15.500000", "16.000000", "16.500000", "17.000000", "17.500000", "18.000000", "18.500000", "19.000000", "19.500000", "20.000000", "20.500000");
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal c_clk : std_logic_array(0 to 5);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_tap : std_logic_vector(7 downto 0) := (OTHERS => '0');
signal vco_out_last_value : std_logic_vector(7 downto 0);
signal vco_tap_last_value : std_logic_vector(7 downto 0);
-- signals to assign values to counter params
signal m_val : int_array(0 to 1) := (OTHERS => 1);
signal n_val : int_array(0 to 1) := (OTHERS => 1);
signal m_ph_val : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val : str_array(0 to 1) := (OTHERS => " ");
signal lfc_val : integer := 0;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 9) := " ";
-- old values
signal m_val_old : int_array(0 to 1) := (OTHERS => 1);
signal n_val_old : int_array(0 to 1) := (OTHERS => 1);
signal m_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal n_mode_val_old : str_array(0 to 1) := (OTHERS => " ");
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 9) := " ";
signal num_output_cntrs : integer := 6;
signal scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal sclkout0_tmp : std_logic;
signal sclkout1_tmp : std_logic;
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal ena_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanread_ipd : std_logic;
signal scanwrite_ipd : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
-- registered signals
signal scanread_reg : std_logic := '0';
signal scanwrite_reg : std_logic := '0';
signal scanwrite_enabled : std_logic := '0';
signal gated_scanclk : std_logic := '1';
signal inclk_c0_dly1 : std_logic := '0';
signal inclk_c0_dly2 : std_logic := '0';
signal inclk_c0_dly3 : std_logic := '0';
signal inclk_c0_dly4 : std_logic := '0';
signal inclk_c0_dly5 : std_logic := '0';
signal inclk_c0_dly6 : std_logic := '0';
signal inclk_c1_dly1 : std_logic := '0';
signal inclk_c1_dly2 : std_logic := '0';
signal inclk_c1_dly3 : std_logic := '0';
signal inclk_c1_dly4 : std_logic := '0';
signal inclk_c1_dly5 : std_logic := '0';
signal inclk_c1_dly6 : std_logic := '0';
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal ext_fbk_cntr_high : integer := 0;
signal ext_fbk_cntr_low : integer := 0;
signal ext_fbk_cntr_ph : integer := 0;
signal ext_fbk_cntr_initial : integer := 1;
signal ext_fbk_cntr : string(1 to 2) := "c0";
signal ext_fbk_cntr_mode : string(1 to 6) := "bypass";
signal ext_fbk_cntr_index : integer := 0;
signal enable0_tmp : std_logic := '0';
signal enable1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandone_tmp : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 5);
signal inclk_m_from_vco : std_logic;
signal inclk_sclkout0_from_vco : std_logic;
signal inclk_sclkout1_from_vco : std_logic;
--signal tap0_is_active : boolean := true;
signal sig_quiet_time : time := 0 ps;
signal sig_slowest_clk_old : time := 0 ps;
signal sig_slowest_clk_new : time := 0 ps;
signal sig_m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
COMPONENT stratixii_m_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixii_n_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanread_ipd, scanread, tipd_scanread);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (scanwrite_ipd, scanwrite, tipd_scanwrite);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
end block;
inclk_m <= clkin when m_test_source = 0 else
clk0_tmp when operation_mode = "external_feedback" and feedback_source = "clk0" else
clk1_tmp when operation_mode = "external_feedback" and feedback_source = "clk1" else
clk2_tmp when operation_mode = "external_feedback" and feedback_source = "clk2" else
clk3_tmp when operation_mode = "external_feedback" and feedback_source = "clk3" else
clk4_tmp when operation_mode = "external_feedback" and feedback_source = "clk4" else
clk5_tmp when operation_mode = "external_feedback" and feedback_source = "clk5" else
inclk_m_from_vco;
ext_fbk_cntr_high <= c_high_val(ext_fbk_cntr_index);
ext_fbk_cntr_low <= c_low_val(ext_fbk_cntr_index);
ext_fbk_cntr_ph <= c_ph_val(ext_fbk_cntr_index);
ext_fbk_cntr_initial <= c_initial_val(ext_fbk_cntr_index);
ext_fbk_cntr_mode <= c_mode_val(ext_fbk_cntr_index);
areset_ena_sig <= areset_ipd or (not ena_ipd) or sig_stop_vco;
pll_in_test_mode <= true when m_test_source /= 5 or c0_test_source /= 5 or
c1_test_source /= 5 or c2_test_source /= 5 or
c3_test_source /= 5 or c4_test_source /= 5 or
c5_test_source /= 5 else
false;
m1 : stratixii_m_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val(0),
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and switch_over_on_lossclk = "on" and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if (input_value = '0') then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (switch_over_on_lossclk = "on" and primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
if (switch_over_on_lossclk = "on" and clkswitch_ipd /= '1') then
if (primary_clk_is_bad) then
-- assert clkloss
clkloss <= '1';
else
clkloss <= '0';
end if;
else
clkloss <= clkswitch_ipd;
end if;
activeclock <= active_clock;
end process;
process (inclk_sclkout0_from_vco)
begin
sclkout0_tmp <= inclk_sclkout0_from_vco;
end process;
process (inclk_sclkout1_from_vco)
begin
sclkout1_tmp <= inclk_sclkout1_from_vco;
end process;
n1 : stratixii_n_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val(0),
modulus => n_val(0));
inclk_c0 <= clkin when c0_test_source = 0 else
refclk when c0_test_source = 1 else
inclk_c_from_vco(0);
c0 : stratixii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= clkin when c1_test_source = 0 else
fbclk when c1_test_source = 2 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= clkin when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= clkin when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= '0' when (pll_type = "fast") else
clkin when (c4_test_source = 0) else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= '0' when (pll_type = "fast") else
clkin when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c0_dly1 <= inclk_c0 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c0_dly2 <= inclk_c0_dly1;
inclk_c0_dly3 <= inclk_c0_dly2;
inclk_c0_dly4 <= inclk_c0_dly3;
inclk_c0_dly5 <= inclk_c0_dly4;
inclk_c0_dly6 <= inclk_c0_dly5;
inclk_c1_dly1 <= inclk_c1 when (pll_type = "fast" or pll_type = "lvds")
else '0';
inclk_c1_dly2 <= inclk_c1_dly1;
inclk_c1_dly3 <= inclk_c1_dly2;
inclk_c1_dly4 <= inclk_c1_dly3;
inclk_c1_dly5 <= inclk_c1_dly4;
inclk_c1_dly6 <= inclk_c1_dly5;
process(inclk_c0_dly6, inclk_c1_dly6, areset_ipd, ena_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or ena_ipd = '0' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0_dly6'event and inclk_c0_dly6 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0_dly6'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0_dly6'event and inclk_c0_dly6 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1_dly6'event and inclk_c1_dly6 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1_dly6'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1_dly6'event and inclk_c1_dly6 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
if (enable0_counter = "c0") then
enable0_tmp <= c0_tmp;
elsif (enable0_counter = "c1") then
enable0_tmp <= c1_tmp;
else
enable0_tmp <= '0';
end if;
if (enable1_counter = "c0") then
enable1_tmp <= c0_tmp;
elsif (enable1_counter = "c1") then
enable1_tmp <= c1_tmp;
else
enable1_tmp <= '0';
end if;
end process;
glocked_cntr : process(clkin, ena_ipd, areset_ipd)
variable count : integer := 0;
variable output : std_logic := '0';
begin
if (areset_ipd = '1') then
count := 0;
output := '0';
elsif (clkin'event and clkin = '1') then
if (ena_ipd = '1') then
count := count + 1;
if (sim_gate_lock_device_behavior = "on") then
if (count = gate_lock_counter) then
output := '1';
end if;
elsif (count = GATE_LOCK_CYCLES) then
output := '1';
end if;
end if;
end if;
gate_locked <= output;
end process;
locked <= gate_locked and lock when gate_lock_signal = "yes" else
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT family_name & " PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val(0));
write (buf, string'(" ( "));
write (buf, n_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val(0));
write (buf, string'(" ( "));
write (buf, m_val_old(0));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
if (ss > 0) then
write (buf, string'(" M2 modulus = "));
write (buf, m_val(1));
write (buf, string'(" ( "));
write (buf, m_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" N2 modulus = "));
write (buf, n_val(1));
write (buf, string'(" ( "));
write (buf, n_val_old(1));
write (buf, string'(" )"));
writeline (output, buf);
end if;
for i in 0 to (num_output_cntrs-1) loop
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, sig_c_low_val_tmp(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
process (scanwrite_enabled, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), vco_tap, fbclk, scanclk_ipd, gated_scanclk)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable n_fast : std_logic_vector(1 downto 0);
variable c_high_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_low_val_tmp : int_array(0 to 5) := (OTHERS => 1);
variable c_ph_val_tmp : int_array(0 to 5) := (OTHERS => 0);
variable c_mode_val_tmp : str_array(0 to 5);
variable m_ph_val_tmp : integer := 0;
variable m_val_tmp : int_array(0 to 1) := (OTHERS => 1);
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_m2 : integer;
variable i_n2 : integer;
variable i_ss : integer;
variable i_c_high : int_array(0 to 5);
variable i_c_low : int_array(0 to 5);
variable i_c_initial : int_array(0 to 5);
variable i_c_ph : int_array(0 to 5);
variable i_c_mode : str_array(0 to 5);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 2) := "c0";
variable clk1_cntr : string(1 to 2) := "c1";
variable clk2_cntr : string(1 to 2) := "c2";
variable clk3_cntr : string(1 to 2) := "c3";
variable clk4_cntr : string(1 to 2) := "c4";
variable clk5_cntr : string(1 to 2) := "c5";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable tmp_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable m_lo, m_hi : std_logic_vector(4 downto 0);
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable got_first_gated_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable scanclk_period : time := 0 ps;
variable current_scan_data : std_logic_vector(173 downto 0) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable Tviol_scanread_scanclk : std_ulogic := '0';
variable Tviol_scanwrite_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanread_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_scanwrite_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
if (refclk_int > (refclk_int * max_modulus / m_mod)) then
q_period := refclk_int * 1 ps;
else
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(2) = '0') then
index := 0;
elsif (arg(2) = '1') then
index := 1;
elsif (arg(2) = '2') then
index := 2;
elsif (arg(2) = '3') then
index := 3;
elsif (arg(2) = '4') then
index := 4;
else index := 5;
end if;
return index;
end extract_cntr_index;
begin
if (init) then
if (m = 0) then
clk5_cntr := "c5";
clk4_cntr := "c4";
clk3_cntr := "c3";
clk2_cntr := "c2";
clk1_cntr := "c1";
clk0_cntr := "c0";
else
clk5_cntr := clk5_counter;
clk4_cntr := clk4_counter;
clk3_cntr := clk3_counter;
clk2_cntr := clk2_counter;
clk1_cntr := clk1_counter;
clk0_cntr := clk0_counter;
end if;
if (operation_mode = "external_feedback") then
if (feedback_source = "clk0") then
fbk_cntr := clk0_cntr;
elsif (feedback_source = "clk1") then
fbk_cntr := clk1_cntr;
elsif (feedback_source = "clk2") then
fbk_cntr := clk2_cntr;
elsif (feedback_source = "clk3") then
fbk_cntr := clk3_cntr;
elsif (feedback_source = "clk4") then
fbk_cntr := clk4_cntr;
elsif (feedback_source = "clk5") then
fbk_cntr := clk5_cntr;
else
fbk_cntr := "c0";
end if;
if (fbk_cntr = "c0") then
fbk_cntr_index := 0;
elsif (fbk_cntr = "c1") then
fbk_cntr_index := 1;
elsif (fbk_cntr = "c2") then
fbk_cntr_index := 2;
elsif (fbk_cntr = "c3") then
fbk_cntr_index := 3;
elsif (fbk_cntr = "c4") then
fbk_cntr_index := 4;
elsif (fbk_cntr = "c5") then
fbk_cntr_index := 5;
end if;
ext_fbk_cntr <= fbk_cntr;
ext_fbk_cntr_index <= fbk_cntr_index;
end if;
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
if (((pll_type = "fast") or (pll_type = "lvds")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
-- in external feedback mode, need to adjust M value to take
-- into consideration the external feedback counter value
if(operation_mode = "external_feedback") then
-- if there is a negative phase shift, m_initial can
-- only be 1
if (max_neg_abs > 0) then
i_m_initial := 1;
end if;
-- calculate the feedback counter multiplier
if (i_c_mode(fbk_cntr_index) = "bypass") then
output_count := 1;
else
output_count := i_c_high(fbk_cntr_index) + i_c_low(fbk_cntr_index);
end if;
new_divisor := gcd(i_m, output_count);
i_m := i_m / new_divisor;
i_n := output_count / new_divisor;
end if;
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val(0) <= i_n;
m_val(0) <= i_m;
m_val(1) <= m2;
n_val(1) <= n2;
if (i_m = 1) then
m_mode_val(0) <= "bypass";
else
m_mode_val(0) <= " ";
end if;
if (m2 = 1) then
m_mode_val(1) <= "bypass";
end if;
if (i_n = 1) then
n_mode_val(0) <= "bypass";
end if;
if (n2 = 1) then
n_mode_val(1) <= "bypass";
end if;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
m_val_tmp := m_val;
for i in 0 to 5 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds") then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_tmp(i) := i_c_ph(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
lfc_val <= loop_filter_c;
lfr_val <= loop_filter_r;
cp_curr_val <= charge_pump_current;
if (pll_type = "fast") then
scan_chain_length := FAST_SCAN_CHAIN;
end if;
-- initialize the scan_chain contents
-- CP/LF bits
scan_data(11 downto 0) <= "000000000000";
for i in 0 to 3 loop
if (pll_type = "fast" or pll_type = "lvds") then
if (fpll_loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
else
if (loop_filter_c_arr(i) = loop_filter_c) then
scan_data(11 downto 10) <= int2bin(i, 2);
end if;
end if;
end loop;
for i in 0 to 15 loop
if (charge_pump_curr_arr(i) = charge_pump_current) then
scan_data(3 downto 0) <= int2bin(i, 4);
end if;
end loop;
for i in 0 to 39 loop
if (loop_filter_r_arr(i) = loop_filter_r) then
if (i >= 16 and i <= 23) then
scan_data(9 downto 4) <= int2bin((i+8), 6);
elsif (i >= 24 and i <= 31) then
scan_data(9 downto 4) <= int2bin((i+16), 6);
elsif (i >= 32) then
scan_data(9 downto 4) <= int2bin((i+24), 6);
else
scan_data(9 downto 4) <= int2bin(i, 6);
end if;
end if;
end loop;
if (pll_type = "fast" or pll_type = "lvds") then
scan_data(21 downto 12) <= "0000000000"; -- M, C3-C0 ph
-- C0-C3 high
scan_data(25 downto 22) <= int2bin(i_c_high(0), 4);
scan_data(35 downto 32) <= int2bin(i_c_high(1), 4);
scan_data(45 downto 42) <= int2bin(i_c_high(2), 4);
scan_data(55 downto 52) <= int2bin(i_c_high(3), 4);
-- C0-C3 low
scan_data(30 downto 27) <= int2bin(i_c_low(0), 4);
scan_data(40 downto 37) <= int2bin(i_c_low(1), 4);
scan_data(50 downto 47) <= int2bin(i_c_low(2), 4);
scan_data(60 downto 57) <= int2bin(i_c_low(3), 4);
-- C0-C3 mode
for i in 0 to 3 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(26 + (10*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
else
scan_data(26 + (10*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(31 + (10*i)) <= '1';
else
scan_data(31 + (10*i)) <= '0';
end if;
end if;
end loop;
-- M
if (i_m = 1) then
scan_data(66) <= '1';
scan_data(71) <= '0';
scan_data(65 downto 62) <= "0000";
scan_data(70 downto 67) <= "0000";
else
scan_data(66) <= '0'; -- set BYPASS bit to 0
scan_data(70 downto 67) <= int2bin(i_m/2, 4); -- set M low
if (i_m rem 2 = 0) then
-- M is an even no. : set M high = low,
-- set odd/even bit to 0
scan_data(65 downto 62) <= int2bin(i_m/2, 4);
scan_data(71) <= '0';
else -- M is odd : M high = low + 1
scan_data(65 downto 62) <= int2bin((i_m/2) + 1, 4);
scan_data(71) <= '1';
end if;
end if;
-- N
scan_data(73 downto 72) <= int2bin(i_n, 2);
if (i_n = 1) then
scan_data(74) <= '1';
scan_data(73 downto 72) <= "00";
end if;
else -- PLL type is auto or enhanced
scan_data(25 downto 12) <= "00000000000000"; -- M, C5-C0 ph
-- C0-C5 high
scan_data(123 downto 116) <= int2bin(i_c_high(0), 8);
scan_data(105 downto 98) <= int2bin(i_c_high(1), 8);
scan_data(87 downto 80) <= int2bin(i_c_high(2), 8);
scan_data(69 downto 62) <= int2bin(i_c_high(3), 8);
scan_data(51 downto 44) <= int2bin(i_c_high(4), 8);
scan_data(33 downto 26) <= int2bin(i_c_high(5), 8);
-- C0-C5 low
scan_data(132 downto 125) <= int2bin(i_c_low(0), 8);
scan_data(114 downto 107) <= int2bin(i_c_low(1), 8);
scan_data(96 downto 89) <= int2bin(i_c_low(2), 8);
scan_data(78 downto 71) <= int2bin(i_c_low(3), 8);
scan_data(60 downto 53) <= int2bin(i_c_low(4), 8);
scan_data(42 downto 35) <= int2bin(i_c_low(5), 8);
-- C0-C5 mode
for i in 0 to 5 loop
if (i_c_mode(i) = " off" or i_c_mode(i) = "bypass") then
scan_data(124 - (18*i)) <= '1';
if (i_c_mode(i) = " off") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
else
scan_data(124 - (18*i)) <= '0';
if (i_c_mode(i) = " odd") then
scan_data(133 - (18*i)) <= '1';
else
scan_data(133 - (18*i)) <= '0';
end if;
end if;
end loop;
-- M/M2
scan_data(142 downto 134) <= int2bin(i_m, 9);
scan_data(143) <= '0';
scan_data(152 downto 144) <= int2bin(m2, 9);
scan_data(153) <= '0';
if (i_m = 1) then
scan_data(143) <= '1';
scan_data(142 downto 134) <= "000000000";
end if;
if (m2 = 1) then
scan_data(153) <= '1';
scan_data(152 downto 144) <= "000000000";
end if;
-- N/N2
scan_data(162 downto 154) <= int2bin(i_n, 9);
scan_data(172 downto 164) <= int2bin(n2, 9);
if (i_n = 1) then
scan_data(163) <= '1';
scan_data(162 downto 154) <= "000000000";
end if;
if (n2 = 1) then
scan_data(173) <= '1';
scan_data(172 downto 164) <= "000000000";
end if;
end if;
if (pll_type = "fast" or pll_type = "lvds") then
num_output_cntrs <= 4;
else
num_output_cntrs <= 6;
end if;
init := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '0') then
-- falling edge : deassert scandone
scandone_tmp <= transport '0' after (1.5 * scanclk_period);
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
elsif (scanwrite_enabled'event and scanwrite_enabled = '1') then
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
reconfig_err <= false;
-- make temporary copy of scan_data for processing
tmp_scan_data := scan_data;
-- save old values
lfc_old <= lfc_val;
lfr_old <= lfr_val;
cp_curr_old <= cp_curr_val;
-- CP
-- Bits 0-3 : all values are legal
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(scan_data(3 downto 0)));
-- LF Resistance : bits 4-9
-- values from 010000 - 010111, 100000 - 100111,
-- 110000 - 110111 are illegal
lfr_tmp := tmp_scan_data(9 downto 4);
lfr_int := alt_conv_integer(lfr_tmp);
if (((lfr_int >= 16) and (lfr_int <= 23)) or
((lfr_int >= 32) and (lfr_int <= 39)) or
((lfr_int >= 48) and (lfr_int <= 55))) then
reconfig_err <= true;
ASSERT false REPORT "Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000-001111, 011000-011111, 101000-101111 and 111000-111111. Reconfiguration may not work." severity warning;
else
if (lfr_int >= 56) then
lfr_int := lfr_int - 24;
elsif ((lfr_int >= 40) and (lfr_int <= 47)) then
lfr_int := lfr_int - 16;
elsif ((lfr_int >= 24) and (lfr_int <= 31)) then
lfr_int := lfr_int - 8;
end if;
lfr_val <= loop_filter_r_arr(lfr_int);
end if;
-- LF Capacitance : bits 10,11 : all values are legal
lfc_tmp := scan_data(11 downto 10);
if (pll_type = "fast" or pll_type = "lvds") then
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(lfc_tmp));
else
lfc_val <= loop_filter_c_arr(alt_conv_integer(lfc_tmp));
end if;
-- cntrs c0-c5
-- save old values for display info.
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
m_ph_val_old <= m_ph_val;
c_high_val_old <= c_high_val;
c_low_val_old <= c_low_val;
c_ph_val_old <= c_ph_val;
c_mode_val_old <= c_mode_val;
-- first the M counter phase : bit order same for fast and GPP
if (scan_data(12) = '0') then
-- do nothing
elsif (scan_data(12) = '1' and scan_data(13) = '1') then
m_ph_val_tmp := m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7) then
m_ph_val_tmp := 0;
end if;
elsif (scan_data(12) = '1' and scan_data(13) = '0') then
m_ph_val_tmp := m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0) then
m_ph_val_tmp := 7;
end if;
else
reconfig_err <= true;
ASSERT false REPORT "Illegal values for M counter phase tap. Reconfiguration may not work." severity warning;
end if;
-- read the fast PLL bits
if (pll_type = "fast" or pll_type = "lvds") then
-- C3-C0 phase bits
for i in 3 downto 0 loop
start_bit := 14 + ((3-i)*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
-- C0-C3 counter moduli
for i in 0 to 3 loop
start_bit := 22 + (i*10);
if (tmp_scan_data(start_bit + 4) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 9) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high_fast := tmp_scan_data(start_bit+3 downto start_bit);
low_fast := tmp_scan_data(start_bit+8 downto start_bit+5);
if (tmp_scan_data(start_bit+3 downto start_bit) = "0000") then
c_high_val_tmp(i) := 16;
else
c_high_val_tmp(i) := alt_conv_integer(high_fast);
end if;
if (tmp_scan_data(start_bit+8 downto start_bit+5) = "0000") then
c_low_val_tmp(i) := 16;
else
c_low_val_tmp(i) := alt_conv_integer(low_fast);
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- M
-- some temporary storage
if (tmp_scan_data(65 downto 62) = "0000") then
m_hi := "10000";
else
m_hi := "0" & tmp_scan_data(65 downto 62);
end if;
if (tmp_scan_data(70 downto 67) = "0000") then
m_lo := "10000";
else
m_lo := "0" & tmp_scan_data(70 downto 67);
end if;
m_val_tmp(0) := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
if (tmp_scan_data(66) = '1') then
if (tmp_scan_data(71) = '1') then
-- this will turn off the M counter : error
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work." severity warning;
else -- M counter is being bypassed
if (m_mode_val(0) /= "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(0) := 1;
m_mode_val(0) <= "bypass";
end if;
else
if (m_mode_val(0) = "bypass") then
-- mode is switched : give warning
ASSERT false REPORT "M counter switched BYPASS mode to enabled. PLL may lose lock." severity warning;
end if;
m_mode_val(0) <= " ";
if (tmp_scan_data(71) = '1') then
-- odd : check for duty cycle, if not 50% -- error
if (alt_conv_integer(m_hi) - alt_conv_integer(m_lo) /= 1) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
else -- even
if (alt_conv_integer(m_hi) /= alt_conv_integer(m_lo)) then
reconfig_err <= true;
ASSERT FALSE REPORT "The M counter of the " & family_name & " FAST PLL can be configured for 50% duty cycle only. In this case, the HIGH and LOW moduli programmed will result in a duty cycle other than 50%, which is illegal. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
-- N
is_error := false;
n_fast := tmp_scan_data(73 downto 72);
n_val(0) <= alt_conv_integer(n_fast);
if (tmp_scan_data(74) /= '1') then
if (alt_conv_integer(n_fast) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for N counter. Instead the counter should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_fast) = 0) then
n_val(0) <= 4;
ASSERT FALSE REPORT "N Modulus = " &int2str(4)& " " severity note;
end if;
if (not is_error) then
if (n_mode_val(0) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_fast))& "). PLL may lose lock." severity warning;
else
ASSERT FALSE REPORT "N modulus = " &int2str(alt_conv_integer(n_fast))& " "severity note;
end if;
n_mode_val(0) <= " ";
end if;
elsif (tmp_scan_data(74) = '1') then
if (tmp_scan_data(72) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for N counter in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(0) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(0) <= 1;
n_mode_val(0) <= "bypass";
end if;
end if;
else -- GENERAL PURPOSE PLL
for i in 0 to 5 loop
start_bit := 116 - (i*18);
if (tmp_scan_data(start_bit + 8) = '1') then
c_mode_val_tmp(i) := "bypass";
if (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " off";
ASSERT false REPORT "The specified bit settings will turn OFF the " &cntrs(i)& "counter. It cannot be turned on unless the part is re-initialized." severity warning;
end if;
elsif (tmp_scan_data(start_bit + 17) = '1') then
c_mode_val_tmp(i) := " odd";
else
c_mode_val_tmp(i) := " even";
end if;
high := tmp_scan_data(start_bit + 7 downto start_bit);
low := tmp_scan_data(start_bit+16 downto start_bit+9);
if (tmp_scan_data(start_bit+7 downto start_bit) = "00000000") then
c_high_val_tmp(i) := 256;
else
c_high_val_tmp(i) := alt_conv_integer(high);
end if;
if (tmp_scan_data(start_bit+16 downto start_bit+9) = "00000000") then
c_low_val_tmp(i) := 256;
else
c_low_val_tmp(i) := alt_conv_integer(low);
end if;
end loop;
-- the phase taps
for i in 0 to 5 loop
start_bit := 14 + (i*2);
if (tmp_scan_data(start_bit) = '0') then
-- do nothing
elsif (tmp_scan_data(start_bit) = '1') then
if (tmp_scan_data(start_bit + 1) = '1') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) + 1;
if (c_ph_val_tmp(i) > 7) then
c_ph_val_tmp(i) := 0;
end if;
elsif (tmp_scan_data(start_bit + 1) = '0') then
c_ph_val_tmp(i) := c_ph_val_tmp(i) - 1;
if (c_ph_val_tmp(i) < 0) then
c_ph_val_tmp(i) := 7;
end if;
end if;
end if;
end loop;
sig_c_ph_val_tmp <= c_ph_val_tmp;
sig_c_low_val_tmp <= c_low_val_tmp;
sig_c_hi_val_tmp <= c_high_val_tmp;
-- cntrs M/M2
for i in 0 to 1 loop
start_bit := 134 + (i*10);
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
m_tmp := tmp_scan_data(start_bit+8 downto start_bit);
m_val_tmp(i) := alt_conv_integer(m_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(m_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(i)& "counter. Instead " &ss_cntrs(i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (tmp_scan_data(start_bit+8 downto start_bit) = "000000000") then
m_val_tmp(i) := 512;
end if;
if (not is_error) then
if (m_mode_val(i) = "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from BYPASS mode to enabled (M modulus = " &int2str(alt_conv_integer(m_tmp))& "). PLL may lose lock." severity warning;
else
end if;
m_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (m_mode_val(i) /= "bypass") then
-- Mode is switched : give warning
ASSERT false REPORT "M Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
m_val_tmp(i) := 1;
m_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (m_mode_val(0) /= m_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for M/M2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
sig_m_val_tmp <= m_val_tmp;
-- cntrs N/N2
for i in 0 to 1 loop
start_bit := 154 + i*10;
if ( i = 0 or (i = 1 and ss > 0) ) then
is_error := false;
n_tmp := tmp_scan_data(start_bit+8 downto start_bit);
n_val(i) <= alt_conv_integer(n_tmp);
if (tmp_scan_data(start_bit+9) /= '1') then
if (alt_conv_integer(n_tmp) = 1) then
is_error := true;
reconfig_err <= true;
-- cntr value is illegal : give warning
ASSERT false REPORT "Illegal 1 value for " &ss_cntrs(2+i)& "counter. Instead " &ss_cntrs(2+i)& "should be BYPASSED. Reconfiguration may not work." severity warning;
elsif (alt_conv_integer(n_tmp) = 0) then
n_val(i) <= 512;
end if;
if (not is_error) then
if (n_mode_val(i) = "bypass") then
ASSERT false REPORT "N Counter switched from BYPASS mode to enabled (N modulus = " &int2str(alt_conv_integer(n_tmp))& "). PLL may lose lock." severity warning;
else
end if;
n_mode_val(i) <= " ";
end if;
elsif (tmp_scan_data(start_bit+9) = '1') then
if (tmp_scan_data(start_bit) /= '0') then
is_error := true;
reconfig_err <= true;
ASSERT false report "Illegal value for counter " &ss_cntrs(2+i)& "in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work." severity warning;
else
if (n_mode_val(i) /= "bypass") then
ASSERT false REPORT "N Counter switched from enabled to BYPASS mode. PLL may lose lock." severity warning;
end if;
n_val(i) <= 1;
n_mode_val(i) <= "bypass";
end if;
end if;
end if;
end loop;
if (ss > 0) then
if (n_mode_val(0) /= n_mode_val(1)) then
reconfig_err <= true;
is_error := true;
ASSERT false REPORT "Incompatible modes for N/N2 counters. Either both should be BYPASSED or both NON-BYPASSED. Reconfiguration may not work." severity warning;
end if;
end if;
end if;
slowest_clk_old := slowest_clk(c_high_val(0)+c_low_val(0), c_mode_val(0),
c_high_val(1)+c_low_val(1), c_mode_val(1),
c_high_val(2)+c_low_val(2), c_mode_val(2),
c_high_val(3)+c_low_val(3), c_mode_val(3),
c_high_val(4)+c_low_val(4), c_mode_val(4),
c_high_val(5)+c_low_val(5), c_mode_val(5),
sig_refclk_period, m_val(0));
slowest_clk_new := slowest_clk(c_high_val_tmp(0)+c_low_val_tmp(0), c_mode_val_tmp(0),
c_high_val_tmp(1)+c_low_val_tmp(1), c_mode_val_tmp(1),
c_high_val_tmp(2)+c_low_val_tmp(2), c_mode_val_tmp(2),
c_high_val_tmp(3)+c_low_val_tmp(3), c_mode_val_tmp(3),
c_high_val_tmp(4)+c_low_val_tmp(4), c_mode_val_tmp(4),
c_high_val_tmp(5)+c_low_val_tmp(5), c_mode_val_tmp(5),
sig_refclk_period, m_val_tmp(0));
if (slowest_clk_new > slowest_clk_old) then
quiet_time := slowest_clk_new;
else
quiet_time := slowest_clk_old;
end if;
sig_quiet_time <= quiet_time;
sig_slowest_clk_old <= slowest_clk_old;
sig_slowest_clk_new <= slowest_clk_new;
tmp_rem := (quiet_time/1 ps) rem (scanclk_period/ 1 ps);
scanclk_cycles := (quiet_time/1 ps) / (scanclk_period/1 ps);
if (tmp_rem /= 0) then
scanclk_cycles := scanclk_cycles + 1;
end if;
scandone_tmp <= transport '1' after ((scanclk_cycles+1)*scanclk_period - (scanclk_period/2));
end if;
if (scanwrite_enabled = '1') then
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (c_clk(0)'event and c_clk(0) = '1') then
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
c0_rising_edge_transfer_done := true;
end if;
if (c_clk(1)'event and c_clk(1) = '1') then
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
c1_rising_edge_transfer_done := true;
end if;
if (c_clk(2)'event and c_clk(2) = '1') then
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
c2_rising_edge_transfer_done := true;
end if;
if (c_clk(3)'event and c_clk(3) = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (c_clk(4)'event and c_clk(4) = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (c_clk(5)'event and c_clk(5) = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
end if;
if (c_clk(0)'event and c_clk(0) = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (c_clk(1)'event and c_clk(1) = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (c_clk(2)'event and c_clk(2) = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (c_clk(3)'event and c_clk(3) = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (c_clk(4)'event and c_clk(4) = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (c_clk(5)'event and c_clk(5) = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanwrite_enabled = '1') then
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x) and vco_tap(x) = '0') then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = x) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end loop;
end if;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
if (areset_ipd = '1') then
c_ph_val <= i_c_ph;
c_ph_val_tmp := i_c_ph;
m_ph_val <= i_m_ph;
m_ph_val_tmp := i_m_ph;
end if;
for x in 0 to 7 loop
if (vco_tap(x) /= vco_tap_last_value(x)) then
-- TAP X has event
for i in 0 to 5 loop
if (c_ph_val(i) = x) then
inclk_c_from_vco(i) <= vco_tap(x);
if (i = 0 and enable0_counter = "c0") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 0 and enable1_counter = "c0") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable0_counter = "c1") then
inclk_sclkout0_from_vco <= vco_tap(x);
end if;
if (i = 1 and enable1_counter = "c1") then
inclk_sclkout1_from_vco <= vco_tap(x);
end if;
end if;
end loop;
if (m_ph_val = x) then
inclk_m_from_vco <= vco_tap(x);
end if;
vco_tap_last_value(x) <= vco_tap(x);
end if;
end loop;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_posedge,
SetupLow => tsetup_scandata_scanclk_noedge_posedge,
HoldHigh => thold_scandata_scanclk_noedge_posedge,
HoldLow => thold_scandata_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanread_scanclk,
TimingData => TimingData_scanread_scanclk,
TestSignal => scanread_ipd,
TestSignalName => "scanread",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanread_scanclk_noedge_posedge,
SetupLow => tsetup_scanread_scanclk_noedge_posedge,
HoldHigh => thold_scanread_scanclk_noedge_posedge,
HoldLow => thold_scanread_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanwrite_scanclk,
TimingData => TimingData_scanwrite_scanclk,
TestSignal => scanwrite_ipd,
TestSignalName => "scanwrite",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanwrite_scanclk_noedge_posedge,
SetupLow => tsetup_scanwrite_scanclk_noedge_posedge,
HoldHigh => thold_scanwrite_scanclk_noedge_posedge,
HoldLow => thold_scanwrite_scanclk_noedge_posedge,
-- CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event and scanclk_ipd = '0') then
-- enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end if;
if (scanread_reg = '1') then
gated_scanclk <= transport scanclk_ipd and scanread_reg;
else
gated_scanclk <= transport '1';
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
-- register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk) then
scanclk_period := now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
-- reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd = '0' and scanread_reg = '1') then
got_first_scanclk := false;
got_first_gated_scanclk := false;
end if;
scanclk_last_rising_edge := now;
end if;
if (gated_scanclk'event and gated_scanclk = '1' and now > 0 ps) then
if (not got_first_gated_scanclk) then
got_first_gated_scanclk := true;
end if;
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_ipd;
end if;
end process;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-1) when (pll_type = "fast" or pll_type = "lvds") else scan_data(GPP_SCAN_CHAIN-1);
SCHEDULE : process (schedule_vco, areset_ipd, ena_ipd, pfdena_ipd, refclk, fbclk, vco_out)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable pll_about_to_lock : boolean := false;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable pll_is_disabled : boolean := false;
variable next_vco_sched_time : time := 0 ps;
variable tap0_is_active : boolean := true;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val(0) * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
pll_is_in_reset := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
if (ena_ipd = '1' and not stop_vco and next_vco_sched_time <= now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- ena was deasserted
if (ena_ipd'event and ena_ipd = '0') then
assert false report family_name & " PLL was disabled" severity note;
pll_is_disabled := true;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
if (ena_ipd'event and ena_ipd = '1') then
assert false report family_name & " PLL is enabled" severity note;
pll_is_disabled := false;
if (areset_ipd /= '1' and not stop_vco and next_vco_sched_time < now) then
schedule_vco <= not schedule_vco;
end if;
end if;
-- illegal value on areset_ipd
if (areset_ipd'event and areset_ipd = 'X') then
assert false report "Illegal value 'X' detected on ARESET input" severity warning;
end if;
if (areset_ipd = '1' or ena_ipd = '0' or stop_vco) then
-- reset lock parameters
locked_tmp := '0';
pll_is_locked := false;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
-- first_schedule := true;
-- vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
-- reset all counter phase taps to POF programmed values
end if;
if (schedule_vco'event and areset_ipd /= '1' and ena_ipd /= '0' and (not stop_vco) and now > 0 ps) then
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val(0);
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
if (operation_mode = "external_feedback") then
if (ext_fbk_cntr_mode = "bypass") then
ext_fbk_cntr_modulus := 1;
else
ext_fbk_cntr_modulus := ext_fbk_cntr_high + ext_fbk_cntr_low;
end if;
loop_xplier := m_val(0) * (ext_fbk_cntr_modulus);
loop_ph := ext_fbk_cntr_ph;
loop_initial := ext_fbk_cntr_initial - 1 + ((m_initial_val - 1) * ext_fbk_cntr_modulus);
end if;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
if (operation_mode = "external_feedback") then
pull_back_M := (m_initial_val - 1) * ext_fbk_cntr_modulus * ((refclk_period/loop_xplier)/1 ps);
while (pull_back_M > refclk_period/1 ps) loop
pull_back_M := pull_back_M - refclk_period/ 1 ps;
end loop;
else
pull_back_M := initial_delay/1 ps + fbk_phase;
end if;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
if (operation_mode = "external_feedback") then
fbk_delay := pull_back_M;
if (simulation_type = "timing") then
fbk_delay := fbk_delay + pll_compensation_delay;
end if;
else
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap0
vco_out(0) <= transport vco_val after sched_time;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule tap 0
vco_out(0) <= transport vco_val after sched_time;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
next_vco_sched_time := now + sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- now schedule the other taps with the appropriate phase-shift
if (vco_out(0)'event) then
for k in 1 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_out(0) after phase_shift(k);
end loop;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (vco_max /= 0 and vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > vco_max) or
((refclk_period/1 ps)/loop_xplier < vco_min)) ) then
if (pll_is_locked) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may lose lock" severity warning;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
inclk_out_of_range := false;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or ( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1') ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock" severity note;
end if;
pll_about_to_lock := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
tap0_is_active := false;
for x in 0 to 7 loop
vco_tap(x) <= '0';
end loop;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = valid_lock_multiplier - 1) then
pll_about_to_lock := true;
end if;
if (cycles_to_lock = valid_lock_multiplier) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = invalid_lock_multiplier) then
pll_is_locked := false;
locked_tmp := '0';
pll_about_to_lock := false;
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
if ( abs(fbclk_time - refclk_time) > 1.5 * refclk_period) then
-- input clock may have stopped : do nothing
else
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
end if;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
-- check which vco_tap has event
for x in 0 to 7 loop
if (vco_out(x) /= vco_out_last_value(x)) then
-- TAP X has event
if (x = 0 and areset_ipd = '0' and ena_ipd = '1' and sig_stop_vco = '0') then
if (vco_out(0) = '1') then
tap0_is_active := true;
end if;
if (tap0_is_active) then
vco_tap(0) <= vco_out(0);
end if;
elsif (tap0_is_active) then
vco_tap(x) <= vco_out(x);
end if;
if (sig_stop_vco = '1') then
vco_tap(x) <= '0';
end if;
vco_out_last_value(x) <= vco_out(x);
end if;
end loop;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
about_to_lock <= pll_about_to_lock after 1 ps;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
end process SCHEDULE;
clk0_tmp <= c_clk(i_clk0_counter);
clk(0) <= clk0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk(1) <= clk1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk(2) <= clk2_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk(3) <= clk3_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk(4) <= clk4_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk(5) <= clk5_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(0) <= sclkout0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
sclkout(1) <= sclkout1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable0 <= enable0_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
enable1 <= enable1_tmp when (areset_ipd = '1' or ena_ipd = '0' or pll_in_test_mode) or (about_to_lock and (not reconfig_err)) else
'X';
scandataout <= scandataout_tmp;
scandone <= scandone_tmp;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixii_mac_bit_register
--
-- Description : a single bit register. This is used for registering all
-- single bit input ports.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_bit_register IS
GENERIC (
power_up : std_logic := '0';
tipd_data : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_data_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0'
);
END stratixii_mac_bit_register;
ARCHITECTURE arch OF stratixii_mac_bit_register IS
SIGNAL data_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic := '0';
SIGNAL viol_notifier : std_logic := '0';
SIGNAL data_dly : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (data_ipd, data, tipd_data);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
clk_delay: process (data_ipd)
begin
data_dly <= data_ipd;
end process;
PROCESS (data_dly, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_reg : STD_LOGIC := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg := data_dly;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg := '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg := data_dly;
ELSE
dataout_reg := dataout_reg;
END IF;
END IF;
end if;
end if;
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_REGISTER
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_register IS
GENERIC (
data_width : integer := 18;
power_up : std_logic := '0';
tipd_data : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(143 downto 0) := (OTHERS => DefPropDelay01);
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(143 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END stratixii_mac_register;
ARCHITECTURE arch OF stratixii_mac_register IS
SIGNAL data_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '1';
SIGNAL dataout_reg : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL viol_notifier : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
PROCESS (data_ipd, clk_ipd, aclr_ipd, ena_ipd, async)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
variable Tviol_clk_ena : STD_ULOGIC := '0';
variable Tviol_data_clk : STD_ULOGIC := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena : STD_ULOGIC := '0';
variable PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
BEGIN
if(async = '1') then
dataout_reg <= data_ipd;
else
if (if_aclr = '1') then
IF (aclr_ipd = '1') THEN
dataout_reg <= (others => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
else
IF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (ena_ipd = '1') THEN
dataout_reg <= data_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
end if;
end if;
END PROCESS;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_reg(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_reg(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_RS_BLOCK
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_rs_block IS
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END stratixii_mac_rs_block;
ARCHITECTURE arch OF stratixii_mac_rs_block IS
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tbuf : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_mult : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_mac_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dly : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturated : std_logic := '0';
SIGNAL min : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL max : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL msb : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
round_ipd <= round ;
saturate_ipd <= saturate ;
addnsub_ipd <= addnsub ;
signa_ipd <= signa ;
signb_ipd <= signb ;
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
datain_ipd(71 downto 0) <= datain(71 downto 0) ;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
addnsub_ipd,
round_ipd)
VARIABLE dataout_round_tmp2 : std_logic_vector(71 DOWNTO 0);
BEGIN
IF (round_ipd = '1') THEN
dataout_round_tmp2 := datain_ipd + (2 **(conv_integer(dataoutsize - signsize - roundsize - "00000001")));
ELSE
dataout_round_tmp2 := datain_ipd;
END IF;
dataout_round <= dataout_round_tmp2;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
addnsub_ipd,
dataout_round)
VARIABLE dataout_saturate_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE saturated_tmp4 : std_logic := '0';
VARIABLE gnd : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE min_tmp5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE max_tmp6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE msb_tmp7 : std_logic := '0';
VARIABLE i : integer;
BEGIN
IF (saturate_ipd = '1') THEN
IF (block_type = "mac_mult") THEN
IF (dataout_round(dataa_width + datab_width - 1) = '0' AND dataout_round(dataa_width + datab_width - 2) = '1') THEN
dataout_saturate_tmp3 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN dataa_width + datab_width - 2 TO (72 - 1) LOOP
dataout_saturate_tmp3(i) := '0';
END LOOP;
saturated_tmp4 := '1';
ELSE
dataout_saturate_tmp3 := dataout_round;
saturated_tmp4 := '0';
END IF;
min_tmp5 := dataout_saturate_tmp3;
max_tmp6 := dataout_saturate_tmp3;
ELSE
IF ((operation(2) = '1') AND ((block_type = "ab") OR (block_type = "cd"))) THEN
saturated_tmp4 := '0';
i := datab_width - 2;
WHILE (i < (datab_width + signsize - 2)) LOOP
IF (dataout_round(datab_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
IF (saturated_tmp4 = '1') THEN
min_tmp5 := "111111111111111111111111111111111111111111111111111111111111111111111111";
max_tmp6 := "111111111111111111111111111111111111111111111111111111111111111111111111";
FOR i IN 0 TO ((datab_width - 2) - 1) LOOP
max_tmp6(i) := '0';
END LOOP;
FOR i IN datab_width - 2 TO (72 - 1) LOOP
min_tmp5(i) := '0';
END LOOP;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
msb_tmp7 := dataout_round(datab_width + 15);
ELSE
IF ((signa_ipd OR signb_ipd OR NOT addnsub_ipd) = '1') THEN
min_tmp5 := gnd + (2 **(conv_integer(dataa_width)));
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width))) - 1);
ELSE
min_tmp5 := "000000000000000000000000000000000000000000000000000000000000000000000000";
max_tmp6 := gnd + ((2 **(conv_integer(dataa_width + 1))) - 1);
END IF;
saturated_tmp4 := '0';
i := dataa_width - 2;
WHILE (i < (dataa_width + signsize - 1)) LOOP
IF (dataout_round(dataa_width - 2) /= dataout_round(i)) THEN
saturated_tmp4 := '1';
END IF;
i := i + 1;
END LOOP;
msb_tmp7 := dataout_round(i);
END IF;
IF (saturated_tmp4 = '1') THEN
IF (msb_tmp7 = '1') THEN
dataout_saturate_tmp3 := max_tmp6;
ELSE
dataout_saturate_tmp3 := min_tmp5;
END IF;
ELSE
dataout_saturate_tmp3 := dataout_round;
END IF;
END IF;
ELSE
saturated_tmp4 := '0';
dataout_saturate_tmp3 := dataout_round;
END IF;
dataout_saturate <= dataout_saturate_tmp3;
saturated <= saturated_tmp4;
min <= min_tmp5;
max <= max_tmp6;
msb <= msb_tmp7;
END PROCESS;
PROCESS (datain_ipd,
signa_ipd,
signb_ipd,
round_ipd,
saturate_ipd,
dataout_round,
dataout_saturate)
VARIABLE dataout_dly_tmp8 : std_logic_vector(71 DOWNTO 0);
VARIABLE i : integer;
VARIABLE width_tmp : integer;
BEGIN
IF (round_ipd = '1') THEN
dataout_dly_tmp8 := dataout_saturate;
width_tmp := conv_integer(dataoutsize) - conv_integer(signsize) - conv_integer(roundsize);
i := 0;
WHILE (i < width_tmp) LOOP
dataout_dly_tmp8(i) := '0';
i := i + 1;
END LOOP;
ELSE
dataout_dly_tmp8 := dataout_saturate;
END IF;
dataout_dly <= dataout_dly_tmp8;
END PROCESS;
dataout_tbuf <= datain WHEN (operation = 0) OR (operation = 7) ELSE rs_saturate ;
rs_saturate <= rs_mac_mult WHEN (saturate_ipd = '1') ELSE rs_mac_out ;
rs_mac_mult <= (dataout_dly(71 DOWNTO 3) & "00" & saturated)
WHEN ((saturate_ipd = '1') AND (saturated = '1') AND (block_type = "mac_mult")) ELSE rs_mac_out ;
rs_mac_out <= (dataout_dly(71 DOWNTO 3) & saturated & datain_ipd(1 DOWNTO 0))
WHEN ((saturate_ipd = '1') AND (block_type /= "mac_mult")) ELSE dataout_dly ;
pathDelay : BLOCK
BEGIN
g1 : for i in dataout'range generate
PROCESS (dataout_tbuf)
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tbuf(i),
Paths => (0 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
1 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END GENERATE;
END BLOCK;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_MULT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_mult_internal IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataout_width : integer := 36;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0) := (others => '0')
);
END stratixii_mac_mult_internal;
ARCHITECTURE arch OF stratixii_mac_mult_internal IS
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL neg : std_logic := '0';
SIGNAL dataout_pre_bypass : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0) := (others => '0');
SIGNAL abs_output : std_logic_vector((dataa_width+datab_width) -1 DOWNTO 0) := (others => '0');
BEGIN
neg <= (dataa_ipd(dataa_width - 1) AND signa) XOR (datab_ipd(datab_width - 1) AND signb) ;
abs_a <= (NOT dataa_ipd(dataa_width - 1 DOWNTO 0) + 1) WHEN (signa AND dataa_ipd(dataa_width - 1)) = '1' ELSE dataa_ipd(dataa_width - 1 DOWNTO 0) ;
abs_b <= (NOT datab_ipd(datab_width - 1 DOWNTO 0) + 1) WHEN (signb AND datab_ipd(datab_width - 1)) = '1' ELSE datab_ipd(datab_width - 1 DOWNTO 0) ;
abs_output((dataa_width + datab_width) - 1 DOWNTO 0) <= abs_a(dataa_width-1 downto 0) * abs_b(datab_width-1 downto 0) ;
dataout_pre_bypass((dataa_width + datab_width) - 1 DOWNTO 0) <= (NOT abs_output + 1) WHEN neg = '1' ELSE abs_output ;
dataout_tmp((dataa_width + datab_width) - 1 DOWNTO 0) <= datab(datab_width-1 downto 0) & dataa(dataa_width-1 downto 0) when ((dynamic_mode = "yes") and (bypass = '1')) else dataa(dataa_width-1 downto 0) & datab(datab_width-1 downto 0) WHEN (bypass = '1') ELSE dataout_pre_bypass ;
PathDelay : block
begin
do:for i in dataout_tmp'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
sa: for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
PROCESS(dataa_ipd)
variable scanouta_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanouta(i),
OutSignalName => "scanouta",
OutTemp => dataa_ipd(i),
Paths => (1 => (dataa_ipd'last_event, tpd_dataa_scanouta(i), TRUE)),
GlitchData => scanouta_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sa;
sb: for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
PROCESS(datab_ipd)
variable scanoutb_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => scanoutb(i),
OutSignalName => "scanoutb",
OutTemp => datab_ipd(i),
Paths => (1 => (datab_ipd'last_event, tpd_datab_scanoutb(i), TRUE)),
GlitchData => scanoutb_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate sb;
end block;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_MULT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_mac_mult_internal;
use work.stratixii_mac_bit_register;
use work.stratixii_mac_register;
use work.stratixii_mac_rs_block;
ENTITY stratixii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode : IN std_logic := '0';
zeroacc : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_mac_mult;
ARCHITECTURE arch OF stratixii_mac_mult IS
COMPONENT stratixii_mac_mult_internal
GENERIC (
dataout_width : integer := 36;
dataa_width : integer := 18;
datab_width : integer := 18;
dynamic_mode : string := "no";
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_dataa_scanouta : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
tpd_datab_scanoutb : VitalDelayArrayType01(18*18-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
bypass : IN std_logic := '0';
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(35 DOWNTO 0));
END COMPONENT;
COMPONENT stratixii_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixii_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT stratixii_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL mult_output : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL round_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL mode_out : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_rs : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_src : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_dataa : std_logic := '0';
SIGNAL clear_dataa : std_logic := '0';
SIGNAL aclr_dataa : std_logic := '0';
SIGNAL ena_dataa : std_logic := '0';
SIGNAL async_dataa : std_logic := '0';
SIGNAL clk_datab : std_logic := '0';
SIGNAL clear_datab : std_logic := '0';
SIGNAL aclr_datab : std_logic := '0';
SIGNAL ena_datab : std_logic := '0';
SIGNAL async_datab : std_logic := '0';
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_round : std_logic := '0';
SIGNAL clear_round : std_logic := '0';
SIGNAL aclr_round : std_logic := '0';
SIGNAL ena_round : std_logic := '0';
SIGNAL async_round : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode : std_logic := '0';
SIGNAL clear_mode : std_logic := '0';
SIGNAL aclr_mode : std_logic := '0';
SIGNAL ena_mode : std_logic := '0';
SIGNAL async_mode : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL signa_internal : std_logic := '0';
SIGNAL signb_internal : std_logic := '0';
SIGNAL bypass : std_logic := '0';
SIGNAL mac_mult_dataoutsize : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_60 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp62 : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL port_tmp63 : std_logic := '0';
SIGNAL port_tmp64 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp65 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL scanouta_tmp2 : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL scanoutb_tmp3 : std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
BEGIN
dataout <= dataout_tmp1(dataout'range);
scanouta <= scanouta_tmp2;
scanoutb <= scanoutb_tmp3;
dataout_tmp1 <= dataout_tmp(35 DOWNTO 0) ;
dataa_src <= scanina WHEN (sourcea = '1') ELSE dataa ;
datab_src <= scaninb WHEN (sourceb = '1') ELSE datab ;
dataa_mac_reg : stratixii_mac_register
GENERIC MAP (
data_width => dataa_width,
power_up => '0')
PORT MAP (
data => dataa_src,
clk => clk_dataa,
aclr => aclr_dataa,
if_aclr => clear_dataa,
ena => ena_dataa,
dataout => scanouta_tmp,
async => async_dataa);
async_dataa <= '1' WHEN (dataa_clock = "none") ELSE '0' ;
clear_dataa <= '1' WHEN (dataa_clear /= "none") ELSE '0' ;
clk_dataa <= '1' WHEN clk(conv_integer(dataa_clk)) = '1' ELSE '0' ;
aclr_dataa <= '1' WHEN (aclr(conv_integer(dataa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_dataa <= '1' WHEN ena(conv_integer(dataa_clk)) = '1' ELSE '0' ;
dataa_clk <= "0000" WHEN ((dataa_clock = "0") OR (dataa_clock = "none")) ELSE "0001" WHEN (dataa_clock = "1") ELSE "0010" WHEN (dataa_clock = "2") ELSE "0011" WHEN (dataa_clock = "3") ELSE "0000" ;
dataa_aclr <= "0000" WHEN ((dataa_clear = "0") OR (dataa_clear = "none")) ELSE "0001" WHEN (dataa_clear = "1") ELSE "0010" WHEN (dataa_clear = "2") ELSE "0011" WHEN (dataa_clear = "3") ELSE "0000" ;
datab_mac_reg : stratixii_mac_register
GENERIC MAP (
data_width => datab_width,
power_up => '0')
PORT MAP (
data => datab_src,
clk => clk_datab,
aclr => aclr_datab,
if_aclr => clear_datab,
ena => ena_datab,
dataout => scanoutb_tmp,
async => async_datab);
async_datab <= '1' WHEN (datab_clock = "none") ELSE '0' ;
clear_datab <= '1' WHEN (datab_clear /= "none") ELSE '0' ;
clk_datab <= '1' WHEN clk(conv_integer(datab_clk)) = '1' ELSE '0' ;
aclr_datab <= '1' WHEN (aclr(conv_integer(datab_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_datab <= '1' WHEN ena(conv_integer(datab_clk)) = '1' ELSE '0' ;
datab_clk <= "0000" WHEN ((datab_clock = "0") OR (datab_clock = "none")) ELSE "0001" WHEN (datab_clock = "1") ELSE "0010" WHEN (datab_clock = "2") ELSE "0011" WHEN (datab_clock = "3") ELSE "0000" ;
datab_aclr <= "0000" WHEN ((datab_clear = "0") OR (datab_clear = "none")) ELSE "0001" WHEN (datab_clear = "1") ELSE "0010" WHEN (datab_clear = "2") ELSE "0011" WHEN (datab_clear = "3") ELSE "0000" ;
signa_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_out,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_out,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
round_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round,
clk => clk_round,
aclr => aclr_round,
if_aclr => clear_round,
ena => ena_round,
dataout => round_out,
async => async_round);
async_round <= '1' WHEN (round_clock = "none") ELSE '0' ;
clear_round <= '1' WHEN (round_clear /= "none") ELSE '0' ;
clk_round <= '1' WHEN clk(conv_integer(round_clk)) = '1' ELSE '0' ;
aclr_round <= '1' WHEN (aclr(conv_integer(round_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round <= '1' WHEN ena(conv_integer(round_clk)) = '1' ELSE '0' ;
round_clk <= "0000" WHEN ((round_clock = "0") OR (round_clock = "none")) ELSE "0001" WHEN (round_clock = "1") ELSE "0010" WHEN (round_clock = "2") ELSE "0011" WHEN (round_clock = "3") ELSE "0000" ;
round_aclr <= "0000" WHEN ((round_clear = "0") OR (round_clear = "none")) ELSE "0001" WHEN (round_clear = "1") ELSE "0010" WHEN (round_clear = "2") ELSE "0011" WHEN (round_clear = "3") ELSE "0000" ;
saturate_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_out,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode,
clk => clk_mode,
aclr => aclr_mode,
if_aclr => clear_mode,
ena => ena_mode,
dataout => mode_out,
async => async_mode);
async_mode <= '1' WHEN (mode_clock = "none") ELSE '0' ;
clear_mode <= '1' WHEN (mode_clear /= "none") ELSE '0' ;
clk_mode <= '1' WHEN clk(conv_integer(mode_clk)) = '1' ELSE '0' ;
aclr_mode <= '1' WHEN (aclr(conv_integer(mode_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode <= '1' WHEN ena(conv_integer(mode_clk)) = '1' ELSE '0' ;
mode_clk <= "0000" WHEN ((mode_clock = "0") OR (mode_clock = "none")) ELSE "0001" WHEN (mode_clock = "1") ELSE "0010" WHEN (mode_clock = "2") ELSE "0011" WHEN (mode_clock = "3") ELSE "0000" ;
mode_aclr <= "0000" WHEN ((mode_clear = "0") OR (mode_clear = "none")) ELSE "0001" WHEN (mode_clear = "1") ELSE "0010" WHEN (mode_clear = "2") ELSE "0011" WHEN (mode_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_out,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
mac_multiply : stratixii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
dataout_width => dataa_width + datab_width,
dynamic_mode => dynamic_mode)
PORT MAP (
dataa => scanouta_tmp,
datab => scanoutb_tmp,
signa => signa_internal,
signb => signb_internal,
bypass => bypass,
scanouta => scanouta_tmp2,
scanoutb => scanoutb_tmp3,
dataout => mult_output);
signa_internal <= '0' WHEN ((signa_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signa_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signa_out ;
signb_internal <= '0' WHEN ((signb_internally_grounded = "true") AND (dynamic_mode = "no")) OR ((((signb_internally_grounded = "true") AND (dynamic_mode = "yes")) AND (zeroacc_out = '1')) AND (mode_out = '0')) ELSE signb_out ;
bypass <= '1' WHEN ((bypass_multiplier = "yes") AND (dynamic_mode = "no")) OR (((bypass_multiplier = "yes") AND (mode_out = '1')) AND (dynamic_mode = "yes")) ELSE '0' ;
tmp_60 <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & mult_output(35 DOWNTO 0);
port_tmp62 <= "1111";
port_tmp63 <= '0';
port_tmp64 <= "00000010";
port_tmp65 <= "00001111";
mac_rs_block : stratixii_mac_rs_block
GENERIC MAP (
block_type => "mac_mult",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => port_tmp62,
round => round_out,
saturate => saturate_out,
addnsub => port_tmp63,
signa => signa_out,
signb => signb_out,
signsize => port_tmp64,
roundsize => port_tmp65,
dataoutsize => mac_mult_dataoutsize,
dataa => scanouta_tmp,
datab => scanoutb_tmp,
datain => tmp_60,
dataout => dataout_rs);
mac_mult_dataoutsize <= CONV_STD_LOGIC_VECTOR(dataa_width + datab_width, 8) ;
dataout_reg <= tmp_60 when bypass = '1' else dataout_rs;
dataout_mac_reg : stratixii_mac_register
GENERIC MAP (
data_width => dataa_width + datab_width,
power_up => '0')
PORT MAP (
data => dataout_reg((dataa_width + datab_width) -1 downto 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_tmp((dataa_width + datab_width) -1 downto 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
END arch;
--////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_ADDNSUB
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_addnsub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
block_type : string := "ab");
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END stratixii_mac_addnsub;
ARCHITECTURE arch OF stratixii_mac_addnsub IS
-- REGULAR ADD/SUB
SIGNAL sa : std_logic := '0';
SIGNAL sb : std_logic := '0';
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
-- 36 BIT MULT
SIGNAL dataa_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_u : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_s : std_logic_vector(71 DOWNTO 0) := (others => '0');
--SIGNAL z36 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--SIGNAL z18 : std_logic_vector(17 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
overflow <= overflow_tmp2;
PROCESS (dataa, datab, datac, datad, signa, signb, operation, addnsub)
--VARIABLE z36_tmp3 : std_logic_vector(35 DOWNTO 0) := (others => '0');
--VARIABLE z18_tmp4 : std_logic_vector(17 DOWNTO 0) := (others => '0');
VARIABLE dataout_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE overflow_tmp_tmp13 : std_logic;
VARIABLE sa_tmp14 : std_logic;
VARIABLE sb_tmp15 : std_logic;
VARIABLE abs_a_tmp16 : std_logic_vector(71 DOWNTO 0);
VARIABLE abs_b_tmp17 : std_logic_vector(71 DOWNTO 0);
VARIABLE dataout_t : std_logic_vector(72 downto 0) := (others => '0');
VARIABLE dataa_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datab_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datac_s : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_u : std_logic_vector(71 downto 0) := (others => '0');
VARIABLE datad_s : std_logic_vector(71 downto 0) := (others => '0');
BEGIN
IF ((unsigned(operation) = 7) AND (block_type /= "sum")) THEN
dataa_u := (others => '0');
datab_u := (others => '0');
datac_u := (others => '0');
datad_u := (others => '0');
datab_s := (others => '0');
datac_s := (others => '0');
dataa_u(35 downto 0) := dataa(35 downto 0);
datab_u(71 downto 36) := datab(35 downto 0);
datab_s(71 downto 36) := datab(35 downto 0);
datac_u(53 downto 18) := datac(35 downto 0);
datac_s(71 downto 18) := sxt(datac(datac_width-1 downto 0), 54);
datad_u(53 downto 18) := datad(35 downto 0);
datad_s(71 downto 18) := sxt(datad(datad_width-1 downto 0), 54);
if((signa = '0') and (signb = '0')) then
dataout_tmp_tmp12 := unsigned(datab_u) + unsigned(datac_u)
+ unsigned(datad_u) + unsigned(dataa_u);
elsif((signa = '0') and (signb = '1')) then
dataout_t := signed(datab_s) + unsigned(datac_u)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '0')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ unsigned(datad_u) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
elsif((signa = '1') and (signb = '1')) then
dataout_t := signed(datab_s) + signed(datac_s)
+ signed(datad_s) + unsigned(dataa_u);
dataout_tmp_tmp12 := dataout_t(71 downto 0);
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF ((operation(2) = '1') AND (block_type = "ab")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datab_width+16 downto 0) :=
signed(sxt(dataa(datab_width+15 downto 0), datab_width+17)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+17));
else
dataout_tmp_tmp12(datab_width+16 downto 0) :=
unsigned(ext(dataa(datab_width+15 downto 0), datab_width+17)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16) XOR dataout_tmp_tmp12(datab_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datab_width + 16);
END IF;
ELSE
IF ((operation(2) = '1') AND (block_type = "cd")) THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
else
if ((signa or signb) = '1') then
dataout_tmp_tmp12(datad_width+16 downto 0) :=
signed(sxt(datac(datad_width+15 downto 0), datad_width+17)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+17));
else
dataout_tmp_tmp12(datad_width+16 downto 0) :=
unsigned(ext(datac(datad_width+15 downto 0), datad_width+17)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+17));
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16) XOR dataout_tmp_tmp12(datad_width + 15);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datad_width + 16);
END IF;
ELSE
IF (block_type = "sum") THEN
if ((signa = '1') and (signb = '0')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(ext(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '0') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(ext(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
elsif ((signa = '1') and (signb = '1')) then
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
signed(sxt(dataa(dataa_width downto 0), dataa_width+2)) +
signed(sxt(datab(datab_width downto 0), dataa_width+2));
else
dataout_tmp_tmp12(dataa_width+1 downto 0) :=
unsigned(ext(dataa(dataa_width downto 0), dataa_width+2)) +
unsigned(ext(datab(datab_width downto 0), dataa_width+2));
end if;
overflow_tmp_tmp13 := '0';
ELSE
IF (block_type = "cd") THEN
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) -
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) -
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
signed(sxt(datac(datac_width-1 downto 0), datac_width+1)) +
signed(sxt(datad(datad_width-1 downto 0), datad_width+1));
end if;
else
if(datac_width >= datad_width) then
dataout_tmp_tmp12(datac_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
else
dataout_tmp_tmp12(datad_width downto 0) :=
unsigned(ext(datac(datac_width-1 downto 0), datac_width+1)) +
unsigned(ext(datad(datad_width-1 downto 0), datad_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1) XOR dataout_tmp_tmp12(datac_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(datac_width + 1);
END IF;
ELSE
if(addnsub = '0') then
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) -
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) -
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
else
if ((signa or signb) = '1') then
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
signed(sxt(dataa(dataa_width-1 downto 0), dataa_width+1)) +
signed(sxt(datab(datab_width-1 downto 0), datab_width+1));
end if;
else
if(dataa_width >= datab_width) then
dataout_tmp_tmp12(dataa_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
else
dataout_tmp_tmp12(datab_width downto 0) :=
unsigned(ext(dataa(dataa_width-1 downto 0), dataa_width+1)) +
unsigned(ext(datab(datab_width-1 downto 0), datab_width+1));
end if;
end if;
end if;
IF ((signa OR signb) = '1') THEN
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1) XOR dataout_tmp_tmp12(dataa_width);
ELSE
overflow_tmp_tmp13 := dataout_tmp_tmp12(dataa_width + 1);
END IF;
END IF;
END IF;
END IF;
END IF;
END IF;
--z36 <= z36_tmp3;
--z18 <= z18_tmp4;
dataout_tmp <= dataout_tmp_tmp12;
overflow_tmp <= overflow_tmp_tmp13;
sa <= sa_tmp14;
sb <= sb_tmp15;
abs_a <= abs_a_tmp16;
abs_b <= abs_b_tmp17;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
overflow_tmp2 <= overflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_DYNAMIC_SRC
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_dynamic_src IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0'
);
END stratixii_mac_dynamic_src;
ARCHITECTURE arch OF stratixii_mac_dynamic_src IS
SIGNAL outa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp : std_logic := '0';
SIGNAL satb_tmp : std_logic := '0';
SIGNAL satc_tmp : std_logic := '0';
SIGNAL satd_tmp : std_logic := '0';
SIGNAL satab_tmp : std_logic := '0';
SIGNAL satcd_tmp : std_logic := '0';
SIGNAL i : integer;
SIGNAL j : integer;
SIGNAL outa_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outb_tmp2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outc_tmp3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL outd_tmp4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata_tmp5 : std_logic := '0';
SIGNAL satb_tmp6 : std_logic := '0';
SIGNAL satc_tmp7 : std_logic := '0';
SIGNAL satd_tmp8 : std_logic := '0';
SIGNAL satab_tmp9 : std_logic := '0';
SIGNAL satcd_tmp10 : std_logic := '0';
SIGNAL dynamic_dataa_width : integer := 36;
SIGNAL dynamic_datab_width : integer := 36;
SIGNAL dynamic_datac_width : integer := 36;
SIGNAL dynamic_datad_width : integer := 36;
BEGIN
outa <= outa_tmp1;
outb <= outb_tmp2;
outc <= outc_tmp3;
outd <= outd_tmp4;
sata <= sata_tmp5;
satb <= satb_tmp6;
satc <= satc_tmp7;
satd <= satd_tmp8;
satab <= satab_tmp9;
satcd <= satcd_tmp10;
dynamic_dataa_width <= dataa_width WHEN (dataa_width > 0) ELSE 36;
dynamic_datab_width <= datab_width WHEN (datab_width > 0) ELSE 36;
dynamic_datac_width <= datac_width WHEN (datac_width > 0) ELSE 36;
dynamic_datad_width <= datad_width WHEN (datad_width > 0) ELSE 36;
PROCESS (accuma, accumc, dataa, datab, datac, datad, multabsaturate, multcdsaturate, signa, signb, zeroacc, zeroacc1, operation)
VARIABLE outa_tmp_tmp11 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outb_tmp_tmp12 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outc_tmp_tmp13 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE outd_tmp_tmp14 : std_logic_vector(71 DOWNTO 0) := (others => '0');
VARIABLE j_tmp15 : integer;
VARIABLE temp_tmp16 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE sata_tmp_tmp17 : std_logic := '0';
VARIABLE satb_tmp_tmp18 : std_logic := '0';
VARIABLE satc_tmp_tmp19 : std_logic := '0';
VARIABLE satd_tmp_tmp20 : std_logic := '0';
VARIABLE satab_tmp_tmp21 : std_logic := '0';
VARIABLE satcd_tmp_tmp22 : std_logic := '0';
BEGIN
CASE operation IS
WHEN "0000" =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') then
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "0100" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11:= sxt(dataa(datab_width+15 downto 0), 72);
ELSE
outa_tmp_tmp11:= ext(dataa(datab_width+15 downto 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
j_tmp15 := dataa_width - 1;
FOR i IN (datab_width + 15) DOWNTO 0 LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 - 1;
END LOOP;
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1100" =>
temp_tmp16 := zeroacc1 & zeroacc;
CASE temp_tmp16 IS
WHEN "00" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "01" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "10" =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN "11" =>
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
WHEN OTHERS =>
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
WHEN "1101" =>
IF (zeroacc = '1') THEN
outa_tmp_tmp11 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (dataa(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(datab_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datab_width + 16 > dataa_width) THEN
FOR i IN datab_width + 16 - dataa_width TO (datab_width + 16 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datab_width + 16 - dataa_width - 1 LOOP
outa_tmp_tmp11(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datab_width + 15 - 1) LOOP
outa_tmp_tmp11(i) := dataa(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outa_tmp_tmp11(dataa_width + 15 DOWNTO 0) := dataa(15 DOWNTO 0) & dataa(35 DOWNTO 18) & dataa(17 downto 16) & "0000000000000000";
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (accuma(datab_width + 15) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(accuma(datab_width + 15 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(accuma(datab_width + 15 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN "1110" =>
IF (zeroacc1 = '1') THEN
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
outc_tmp_tmp13 := "000000000000000000000000000000000000000000000000000000000000000000000000";
IF (datac(datad_width + 15) = '1' AND signb = '1') THEN
outc_tmp_tmp13 := sxt(datac(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(datad_width + 15 DOWNTO 0), 72);
END IF;
j_tmp15 := 0;
IF (datad_width + 16 > datac_width) THEN
FOR i IN datad_width + 16 - datac_width TO (datad_width + 16 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
FOR i IN 0 to datad_width + 16 - datac_width - 1 LOOP
outc_tmp_tmp13(i) := '0';
END LOOP;
ELSE
FOR i IN 0 TO (datad_width + 15 - 1) LOOP
outc_tmp_tmp13(i) := datac(j_tmp15);
j_tmp15 := j_tmp15 + 1;
END LOOP;
END IF;
outc_tmp_tmp13(datac_width + 15 DOWNTO 0) := datac(15 DOWNTO 0) & datac(35 DOWNTO 18) & datac(17 downto 16) & "0000000000000000";
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signb = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (accumc(datad_width + 15) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(accumc(datad_width + 15 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(accumc(datad_width + 15 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signb = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
WHEN OTHERS =>
IF (dataa(dynamic_dataa_width - 1) = '1' AND signa = '1') THEN
outa_tmp_tmp11 := sxt(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
ELSE
outa_tmp_tmp11 := ext(dataa(dynamic_dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(dynamic_datab_width - 1) = '1' AND signa = '1') THEN
outb_tmp_tmp12 := sxt(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
ELSE
outb_tmp_tmp12 := ext(datab(dynamic_datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(dynamic_datac_width - 1) = '1' AND signa = '1') THEN
outc_tmp_tmp13 := sxt(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
ELSE
outc_tmp_tmp13 := ext(datac(dynamic_datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(dynamic_datad_width - 1) = '1' AND signa = '1') THEN
outd_tmp_tmp14 := sxt(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
ELSE
outd_tmp_tmp14 := ext(datad(dynamic_datad_width - 1 DOWNTO 0), 72);
END IF;
END CASE;
IF (multabsaturate = '1') THEN
IF ((outa_tmp_tmp11(0) AND ((zeroacc AND operation(2)) OR NOT operation(2))) = '1') THEN
sata_tmp_tmp17 := '1';
outa_tmp_tmp11(0) := '0';
ELSE
sata_tmp_tmp17 := '0';
END IF;
IF (outb_tmp_tmp12(0) = '1') THEN
satb_tmp_tmp18 := '1';
outb_tmp_tmp12(0) := '0';
ELSE
satb_tmp_tmp18 := '0';
END IF;
ELSE
sata_tmp_tmp17 := '0';
satb_tmp_tmp18 := '0';
END IF;
IF (multcdsaturate = '1') THEN
IF ((outc_tmp_tmp13(0) AND ((zeroacc1 AND operation(2)) OR NOT operation(2))) = '1') THEN
satc_tmp_tmp19 := '1';
outc_tmp_tmp13(0) := '0';
ELSE
satc_tmp_tmp19 := '0';
END IF;
IF (outd_tmp_tmp14(0) = '1') THEN
satd_tmp_tmp20 := '1';
outd_tmp_tmp14(0) := '0';
ELSE
satd_tmp_tmp20 := '0';
END IF;
ELSE
satc_tmp_tmp19 := '0';
satd_tmp_tmp20 := '0';
END IF;
IF ((sata_tmp_tmp17 OR satb_tmp_tmp18) = '1') THEN
satab_tmp_tmp21 := '1';
ELSE
satab_tmp_tmp21 := '0';
END IF;
IF ((satc_tmp_tmp19 OR satd_tmp_tmp20) = '1') THEN
satcd_tmp_tmp22 := '1';
ELSE
satcd_tmp_tmp22 := '0';
END IF;
outa_tmp <= outa_tmp_tmp11;
outb_tmp <= outb_tmp_tmp12;
outc_tmp <= outc_tmp_tmp13;
outd_tmp <= outd_tmp_tmp14;
j <= j_tmp15;
sata_tmp <= sata_tmp_tmp17;
satb_tmp <= satb_tmp_tmp18;
satc_tmp <= satc_tmp_tmp19;
satd_tmp <= satd_tmp_tmp20;
satab_tmp <= satab_tmp_tmp21;
satcd_tmp <= satcd_tmp_tmp22;
END PROCESS;
outa_tmp1 <= outa_tmp ;
outb_tmp2 <= outb_tmp ;
outc_tmp3 <= outc_tmp ;
outd_tmp4 <= outd_tmp ;
sata_tmp5 <= sata_tmp ;
satb_tmp6 <= satb_tmp ;
satc_tmp7 <= satc_tmp ;
satd_tmp8 <= satd_tmp ;
satab_tmp9 <= satab_tmp ;
satcd_tmp10 <= satcd_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_DYNAMIC_MUX
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_dynamic_mux IS
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END stratixii_mac_dynamic_mux;
ARCHITECTURE arch OF stratixii_mac_dynamic_mux IS
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataout <= dataout_tmp1;
accoverflow <= accoverflow_tmp2;
PROCESS (ab, cd, sata, satb, satc, satd, multsatab, multsatcd, outsatab, outsatcd, multabsaturate, multcdsaturate, saturateab, saturatecd, overab, overcd, sum, m36, bypass, operation)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
VARIABLE accoverflow_tmp_tmp4 : std_logic := '0';
VARIABLE temp_tmp5 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp6 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp7 : std_logic_vector(3 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp8 : std_logic_vector(1 DOWNTO 0) := (others => '0');
VARIABLE temp_tmp9 : std_logic_vector(1 DOWNTO 0) := (others => '0');
BEGIN
CASE operation IS
WHEN "0000" =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
WHEN "0100" =>
temp_tmp5 := saturateab & multabsaturate;
CASE temp_tmp5 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "0001" =>
IF (multabsaturate = '1') THEN
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 2) & satb & sata;
ELSE
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 0);
END IF;
accoverflow_tmp_tmp4 := '0';
WHEN "0010" =>
temp_tmp6 := multsatcd & multsatab;
CASE temp_tmp6 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 2) & satb & sata;
accoverflow_tmp_tmp4 := '0';
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & sum(1 DOWNTO 0);
accoverflow_tmp_tmp4 := satd;
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 3) & satc & satb & sata;
accoverflow_tmp_tmp4 := satd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & sum(71 DOWNTO 0);
accoverflow_tmp_tmp4 := '0';
END CASE;
WHEN "0111" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & m36;
accoverflow_tmp_tmp4 := '0';
WHEN "1100" =>
temp_tmp7 := saturatecd & saturateab & multsatcd & multsatab;
CASE temp_tmp7 IS
WHEN "0000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "0011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "0100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "0110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "0111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1000" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1001" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1010" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
WHEN "1011" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "1100" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN "1110" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "1111" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1101" =>
temp_tmp8 := saturateab & multabsaturate;
CASE temp_tmp8 IS
WHEN "00" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 2) & multsatab & ab(0);
WHEN "10" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & ab(1 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 3) & outsatab & multsatab & ab(0);
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass(143 DOWNTO 72) & ab(71 DOWNTO 53) & overab & ab(51 DOWNTO 36) & ab(35 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overab;
WHEN "1110" =>
temp_tmp9 := saturatecd & multcdsaturate;
CASE temp_tmp9 IS
WHEN "00" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "01" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 2) & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN "10" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & cd(1 DOWNTO 0) & bypass(71 DOWNTO 0);
WHEN "11" =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 3) & outsatcd & multsatcd & cd(0) & bypass(71 DOWNTO 0);
WHEN OTHERS =>
dataout_tmp_tmp3 := cd(71 DOWNTO 53) & overcd & cd(51 DOWNTO 0) & bypass(71 DOWNTO 0);
END CASE;
accoverflow_tmp_tmp4 := overcd;
WHEN OTHERS =>
dataout_tmp_tmp3 := bypass;
accoverflow_tmp_tmp4 := '0';
END CASE;
dataout_tmp <= dataout_tmp_tmp3;
accoverflow_tmp <= accoverflow_tmp_tmp4;
END PROCESS;
dataout_tmp1 <= dataout_tmp ;
accoverflow_tmp2 <= accoverflow_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_OUT_INTERNAL
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_mac_addnsub;
use work.stratixii_mac_dynamic_mux;
use work.stratixii_mac_dynamic_src;
use work.stratixii_mac_rs_block;
ENTITY stratixii_mac_out_internal IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width -1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0'
);
END stratixii_mac_out_internal;
ARCHITECTURE arch OF stratixii_mac_out_internal IS
COMPONENT stratixii_mac_addnsub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
block_type : string := "ab";
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
signb : IN std_logic := '0';
signa : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixii_mac_dynamic_mux
PORT (
ab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
cd : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : IN std_logic := '0';
satb : IN std_logic := '0';
satc : IN std_logic := '0';
satd : IN std_logic := '0';
multsatab : IN std_logic := '0';
multsatcd : IN std_logic := '0';
outsatab : IN std_logic := '0';
outsatcd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
saturateab : IN std_logic := '0';
saturatecd : IN std_logic := '0';
overab : IN std_logic := '0';
overcd : IN std_logic := '0';
sum : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
m36 : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
bypass : IN std_logic_vector(143 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(143 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixii_mac_dynamic_src
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36);
PORT (
accuma : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
accumc : IN std_logic_vector(51 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
outa : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outb : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outc : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
outd : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
sata : OUT std_logic := '0';
satb : OUT std_logic := '0';
satc : OUT std_logic := '0';
satd : OUT std_logic := '0';
satab : OUT std_logic := '0';
satcd : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixii_mac_rs_block
GENERIC (
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
block_type : string := "mac_mult";
dataa_width : integer := 18;
datab_width : integer := 18);
PORT (
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
addnsub : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
signsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
roundsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataoutsize : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataout_tmp : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL dataa_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_src : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sata : std_logic := '0';
SIGNAL satb : std_logic := '0';
SIGNAL satc : std_logic := '0';
SIGNAL satd : std_logic := '0';
SIGNAL satab : std_logic := '0';
SIGNAL satcd : std_logic := '0';
SIGNAL addnsub_ab_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_cd_out : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL addnsub_sum : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_ab : std_logic := '0';
SIGNAL overflow_cd : std_logic := '0';
SIGNAL overflow_sum : std_logic := '0';
SIGNAL rs_block_ab_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_ab_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL rs_block_cd_sign_size : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL dataout_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datac_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL datad_ipd : std_logic_vector(35 DOWNTO 0) := (others => '0');
SIGNAL feedback_ipd : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL saturateab_ipd : std_logic := '0';
SIGNAL saturatecd_ipd : std_logic := '0';
SIGNAL multabsaturate_ipd : std_logic := '0';
SIGNAL multcdsaturate_ipd : std_logic := '0';
SIGNAL dataout_tbuf : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tbuf : std_logic;
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signx_or_y : std_logic;
SIGNAL addnsub_signa_input : std_logic;
SIGNAL addnsub_signb_input : std_logic;
SIGNAL feedback_accuma : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL feedback_accumc : std_logic_vector(51 DOWNTO 0) := (others => '0');
SIGNAL xory_addnsub0 : std_logic := '0';
SIGNAL xory_addnsub1 : std_logic := '0';
SIGNAL tmp_4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_8 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL tmp_10 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL port_tmp38 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp43 : std_logic_vector(7 DOWNTO 0) := (others => '0');
SIGNAL port_tmp50 : std_logic := '0';
SIGNAL tmp_59 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp1 : std_logic_vector(143 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_tmp2 : std_logic := '0';
BEGIN
dataa_ipd(dataa_width -1 downto 0) <= dataa;
datab_ipd(datab_width -1 downto 0) <= datab;
datac_ipd(datac_width -1 downto 0) <= datac;
datad_ipd(datad_width -1 downto 0) <= datad;
WireDelay : block
begin
loopbits : FOR i in feedback'RANGE GENERATE
VitalWireDelay (feedback_ipd(i), feedback(i), tipd_feedback(i));
END GENERATE;
end block;
multabsaturate_ipd <= multabsaturate ;
multcdsaturate_ipd <= multcdsaturate ;
saturateab_ipd <= saturateab ;
saturatecd_ipd <= saturatecd ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '0')) AND (zeroacc1 = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0 = '1')) AND (mode1 = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE "0000" ;
addnsub_signa_input <= signx WHEN (operation_mode = "36_bit_multiply") ELSE signx WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
addnsub_signb_input <= signy WHEN (operation_mode = "36_bit_multiply") ELSE signy WHEN (((((operation_mode = "dynamic") AND (mode0 = '0')) AND (mode1 = '0')) AND (zeroacc = '1')) AND (zeroacc1 = '1')) ELSE signx_or_y;
tmp_4(dataa_ipd'range) <= dataa_ipd;
tmp_6(datab_ipd'range) <= datab_ipd;
tmp_8(datac_ipd'range) <= datac_ipd;
tmp_10(datad_ipd'range) <= datad_ipd;
dynamic_src : stratixii_mac_dynamic_src
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
accuma => feedback_accuma,
accumc => feedback_accumc,
dataa => tmp_4,
datab => tmp_6,
datac => tmp_8,
datad => tmp_10,
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
zeroacc => zeroacc,
zeroacc1 => zeroacc1,
signa => signx,
signb => signy,
operation => operation,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
satab => satab,
satcd => satcd,
outa => dataa_src,
outb => datab_src,
outc => datac_src,
outd => datad_src);
signx_or_y <= signx OR signy ;
feedback_accuma <= feedback(52 DOWNTO 37) & feedback(35 DOWNTO 0) WHEN (operation_mode = "dynamic") ELSE feedback(51 DOWNTO 0) ;
feedback_accumc <= feedback(124 DOWNTO 109) & feedback(107 DOWNTO 72) WHEN (operation_mode = "dynamic") ELSE feedback(123 DOWNTO 72) ;
addnsub_ab : stratixii_mac_addnsub
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => addnsub_signa_input,
signb => addnsub_signb_input,
operation => operation,
addnsub => addnsub0,
dataout => addnsub_ab_out,
overflow => overflow_ab);
addnsub_cd : stratixii_mac_addnsub
GENERIC MAP (
block_type => "cd",
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataa_src,
datab => datab_src,
datac => datac_src,
datad => datad_src,
signa => signx_or_y,
signb => signx_or_y,
operation => operation,
addnsub => addnsub1,
dataout => addnsub_cd_out,
overflow => overflow_cd);
port_tmp38 <= "00001111";
mac_rs_block_low : stratixii_mac_rs_block
GENERIC MAP (
block_type => "ab",
dataa_width => dataa_width,
datab_width => datab_width)
PORT MAP (
operation => operation,
round => roundab,
saturate => saturateab_ipd,
addnsub => addnsub0,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_ab_sign_size,
roundsize => port_tmp38,
dataoutsize => rs_block_ab_size,
dataa => dataa_src(dataa_width-1 downto 0),
datab => datab_src(datab_width-1 downto 0),
datain => addnsub_ab_out,
dataout => dataout_low);
rs_block_ab_size <= CONV_STD_LOGIC_VECTOR((datab_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((dataa_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_ab_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp43 <= "00001111";
mac_rs_block_high : stratixii_mac_rs_block
GENERIC MAP (
block_type => "cd",
dataa_width => datac_width,
datab_width => datad_width)
PORT MAP (
operation => operation,
round => roundcd,
saturate => saturatecd_ipd,
addnsub => addnsub1,
signa => signx_or_y,
signb => signx_or_y,
signsize => rs_block_cd_sign_size,
roundsize => port_tmp43,
dataoutsize => rs_block_cd_size,
dataa => datac_src(datac_width -1 downto 0),
datab => datad_src(datad_width -1 downto 0),
datain => addnsub_cd_out,
dataout => dataout_high);
rs_block_cd_size <= CONV_STD_LOGIC_VECTOR((datad_width + 16), 8) WHEN (operation(2) = '1') ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 1) ELSE CONV_STD_LOGIC_VECTOR((datac_width + 1), 8) WHEN (unsigned(operation) = 2) ELSE "00100100" ;
rs_block_cd_sign_size <= "00010010" WHEN (operation(2) = '1') ELSE "00000011" WHEN (unsigned(operation) = 1) OR (unsigned(operation) = 2) ELSE "00000010" ;
port_tmp50 <= '1';
addnsub_sum_abcd : stratixii_mac_addnsub
GENERIC MAP (
block_type => "sum",
dataa_width => dataa_width,
datab_width => dataa_width,
datac_width => datac_width,
datad_width => datad_width)
PORT MAP (
dataa => dataout_low,
datab => dataout_high,
datac => datac_src,
datad => datad_src,
signa => xory_addnsub0,
signb => xory_addnsub1,
operation => operation,
addnsub => port_tmp50,
dataout => addnsub_sum,
overflow => overflow_sum);
xory_addnsub0 <= signx_or_y OR NOT addnsub0 ;
xory_addnsub1 <= signx_or_y OR NOT addnsub1 ;
tmp_59 <= datad_ipd & datac_ipd & datab_ipd & dataa_ipd;
dynamic_mux : stratixii_mac_dynamic_mux
PORT MAP (
ab => dataout_low,
cd => dataout_high,
sata => sata,
satb => satb,
satc => satc,
satd => satd,
multsatab => satab,
multsatcd => satcd,
outsatab => dataout_low(2),
outsatcd => dataout_high(2),
multabsaturate => multabsaturate_ipd,
multcdsaturate => multcdsaturate_ipd,
saturateab => saturateab_ipd,
saturatecd => saturatecd_ipd,
overab => overflow_ab,
overcd => overflow_cd,
sum => addnsub_sum,
m36 => addnsub_ab_out,
bypass => tmp_59,
operation => operation,
dataout => dataout_tmp,
accoverflow => accoverflow_tmp);
PathDelay: for i in dataout'range generate
PROCESS(dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (1 => (dataa'last_event, tpd_dataa_dataout(i), TRUE),
2 => (datab'last_event, tpd_datab_dataout(i), TRUE),
3 => (datac'last_event, tpd_datac_dataout(i), TRUE),
4 => (datad'last_event, tpd_datad_dataout(i), TRUE),
5 => (signx'last_event, tpd_signx_dataout(i), TRUE),
6 => (signy'last_event, tpd_signy_dataout(i), TRUE),
7 => (addnsub0'last_event, tpd_addnsub0_dataout(i), TRUE),
8 => (addnsub1'last_event, tpd_addnsub1_dataout(i), TRUE),
9 => (zeroacc'last_event, tpd_zeroacc_dataout(i), TRUE),
10 => (zeroacc1'last_event, tpd_zeroacc1_dataout(i), TRUE),
11 => (mode0'last_event, tpd_mode0_dataout(i), TRUE),
12 => (mode1'last_event, tpd_mode1_dataout(i), TRUE),
13 => (multabsaturate'last_event, tpd_multabsaturate_dataout(i), TRUE),
14 => (multcdsaturate'last_event, tpd_multcdsaturate_dataout(i), TRUE),
15 => (feedback'last_event, tpd_feedback_dataout(i), TRUE)
),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end generate PathDelay;
acc: for i in dataa'range generate
PROCESS(accoverflow_tmp)
variable accoverflow_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => accoverflow,
OutSignalName => "accoverflow",
OutTemp => accoverflow_tmp,
Paths => (1 => (dataa'last_event, tpd_dataa_accoverflow(i), TRUE),
2 => (signx'last_event, tpd_signx_accoverflow, TRUE),
3 => (signy'last_event, tpd_signy_accoverflow, TRUE),
4 => (addnsub0'last_event, tpd_addnsub0_accoverflow, TRUE),
5 => (addnsub1'last_event, tpd_addnsub1_accoverflow, TRUE),
6 => (zeroacc'last_event, tpd_zeroacc_accoverflow, TRUE),
7 => (zeroacc1'last_event, tpd_zeroacc1_accoverflow, TRUE),
8 => (mode0'last_event, tpd_mode0_accoverflow, TRUE),
9 => (mode1'last_event, tpd_mode1_accoverflow, TRUE),
10 => (feedback'last_event, tpd_feedback_accoverflow, TRUE)
),
GlitchData => accoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END process;
END GENERATE acc;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_PIN_MAP
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_mac_pin_map IS
GENERIC (
tipd_addnsub : VitalDelayType01 := DefPropDelay01;
data_width : integer := 144;
tipd_datain : VitalDelayArrayType01(143 downto 0) := (OTHERS => (20 ps,20 ps));
operation_mode : string := "output_only";
pinmap : string := "map");
PORT (
datain : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END stratixii_mac_pin_map;
ARCHITECTURE arch OF stratixii_mac_pin_map IS
SIGNAL addnsub_ipd : std_logic := '0';
SIGNAL datain_ipd : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp2 : std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (addnsub_ipd, addnsub, tipd_addnsub);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
dataout <= dataout_tmp2(dataout'range);
PROCESS (datain_ipd, addnsub_ipd)
VARIABLE dataout_tmp_tmp3 : std_logic_vector(143 DOWNTO 0) := (others => '0');
BEGIN
IF (operation_mode = "dynamic") THEN
IF (pinmap = "map") THEN
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) &
'X' & datain_ipd(107 DOWNTO 72) &
"XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) &
'X' & datain_ipd(35 DOWNTO 0);
WHEN "1101" =>
dataout_tmp_tmp3 := datain_ipd(143 DOWNTO 72)& "XXXXXXXXXXXXXXXXXXX" & datain_ipd(51 DOWNTO 36) & 'X' & datain_ipd(35 DOWNTO 0);
WHEN "1110" =>
dataout_tmp_tmp3 := "XXXXXXXXXXXXXXXXXXX" & datain_ipd(123 DOWNTO 108) & 'X' & datain_ipd(107 DOWNTO 0);
WHEN "0111" =>
IF (addnsub_ipd = '1') THEN
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
ELSE
dataout_tmp_tmp3(17 DOWNTO 0) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(35 DOWNTO 18) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(53 DOWNTO 36) := "XXXXXXXXXXXXXXXXXX";
dataout_tmp_tmp3(71 DOWNTO 54) := "XXXXXXXXXXXXXXXXXX";
END IF;
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
ELSE
CASE operation IS
WHEN "1100" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "1101" =>
dataout_tmp_tmp3(35 DOWNTO 0) := datain_ipd(35 DOWNTO 0);
dataout_tmp_tmp3(70 DOWNTO 36) := datain_ipd(71 DOWNTO 37);
dataout_tmp_tmp3(143 DOWNTO 72) := datain_ipd(143 DOWNTO 72);
WHEN "1110" =>
dataout_tmp_tmp3(107 DOWNTO 0) := datain_ipd(107 DOWNTO 0);
dataout_tmp_tmp3(107 DOWNTO 72) := datain_ipd(107 DOWNTO 72);
dataout_tmp_tmp3(142 DOWNTO 108) := datain_ipd(143 DOWNTO 109);
WHEN "0111" =>
dataout_tmp_tmp3(17 DOWNTO 0) := datain_ipd(17 DOWNTO 0);
dataout_tmp_tmp3(53 DOWNTO 36) := datain_ipd(35 DOWNTO 18);
dataout_tmp_tmp3(35 DOWNTO 18) := datain_ipd(53 DOWNTO 36);
dataout_tmp_tmp3(71 DOWNTO 54) := datain_ipd(71 DOWNTO 54);
dataout_tmp_tmp3(143 DOWNTO 72) := "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
WHEN OTHERS =>
dataout_tmp_tmp3 := datain_ipd;
END CASE;
END IF;
ELSE
dataout_tmp_tmp3 := datain_ipd;
END IF;
dataout_tmp <= dataout_tmp_tmp3;
END PROCESS;
dataout_tmp2 <= dataout_tmp ;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- STRATIXII_MAC_OUT
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
use work.stratixii_mac_out_internal;
use work.stratixii_mac_pin_map;
use work.stratixii_mac_bit_register;
use work.stratixii_mac_register;
ENTITY stratixii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "stratixii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
saturate1 : IN std_logic := '0';
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_mac_out;
ARCHITECTURE arch OF stratixii_mac_out IS
COMPONENT stratixii_mac_out_internal
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
tmp_width : integer := 144;
dataout_width : integer := 144;
tipd_dataa : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datac : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_datad : VitalDelayArrayType01(35 downto 0):= (OTHERS => DefPropDelay01);
tipd_feedback : VitalDelayArrayType01(143 downto 0):= (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datac_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_datad_dataout : VitalDelayArrayType01(144*36-1 downto 0) := (others => DefPropDelay01);
tpd_feedback_dataout : VitalDelayArrayType01(144*144-1 downto 0) := (others => DefPropDelay01);
tpd_signx_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_signy_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_addnsub1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_zeroacc1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multabsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_multcdsaturate_dataout: VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode0_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_mode1_dataout : VitalDelayArrayType01(143 downto 0) := (others => DefPropDelay01);
tpd_dataa_accoverflow : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_feedback_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signx_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signy_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_addnsub1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_zeroacc1_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode0_accoverflow : VitalDelayType01 := DefPropDelay01;
tpd_mode1_accoverflow : VitalDelayType01 := DefPropDelay01;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
datac : IN std_logic_vector(datac_width -1 DOWNTO 0) := (others => '0');
datad : IN std_logic_vector(datad_width -1 DOWNTO 0) := (others => '0');
mode0 : IN std_logic := '0';
mode1 : IN std_logic := '0';
roundab : IN std_logic := '0';
saturateab : IN std_logic := '0';
roundcd : IN std_logic := '0';
saturatecd : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signx : IN std_logic := '0';
signy : IN std_logic := '0';
addnsub0 : IN std_logic := '0';
addnsub1 : IN std_logic := '0';
zeroacc : IN std_logic := '0';
zeroacc1 : IN std_logic := '0';
feedback : IN std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(dataout_width-1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic);
END COMPONENT;
COMPONENT stratixii_mac_pin_map
GENERIC (
pinmap : string := "map";
data_width : integer := 144;
operation_mode : string := "output_only");
PORT (
datain : IN std_logic_vector(data_width-1 DOWNTO 0) := (others => '0');
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
addnsub : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width-1 DOWNTO 0) := (others => '0'));
END COMPONENT;
COMPONENT stratixii_mac_bit_register
GENERIC (
power_up : std_logic := '0');
PORT (
data : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic := '0');
END COMPONENT;
COMPONENT stratixii_mac_register
GENERIC (
power_up : std_logic := '0';
data_width : integer := 18);
PORT (
data : IN std_logic_vector(data_width -1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
if_aclr : IN std_logic := '0';
ena : IN std_logic := '1';
async : IN std_logic := '1';
dataout : OUT std_logic_vector(data_width -1 DOWNTO 0) := (others => '0'));
END COMPONENT;
SIGNAL dataa_f : std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
SIGNAL datac_f : std_logic_vector(datac_width-1 DOWNTO 0) := (others => '0');
SIGNAL signa_pipe : std_logic := '0';
SIGNAL signb_pipe : std_logic := '0';
SIGNAL multabsaturate_pipe : std_logic := '0';
SIGNAL multcdsaturate_pipe : std_logic := '0';
SIGNAL signa_out : std_logic := '0';
SIGNAL signb_out : std_logic := '0';
SIGNAL multabsaturate_out : std_logic := '0';
SIGNAL multcdsaturate_out : std_logic := '0';
SIGNAL addnsub0_pipe : std_logic := '0';
SIGNAL addnsub1_pipe : std_logic := '0';
SIGNAL addnsub0_out : std_logic := '0';
SIGNAL addnsub1_out : std_logic := '0';
SIGNAL zeroacc_pipe : std_logic := '0';
SIGNAL zeroacc1_pipe : std_logic := '0';
SIGNAL zeroacc_out : std_logic := '0';
SIGNAL zeroacc1_out : std_logic := '0';
SIGNAL dataout_feedback : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_map : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_mapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_unmapped : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_non_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic2 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic3 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic4 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic5 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic6 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_dynamic7 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_low : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp_high : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_to_reg : std_logic_vector(tmp_width-1 DOWNTO 0) := (others => '0');
SIGNAL accoverflow_reg : std_logic := '0';
SIGNAL accoverflow_tmp : std_logic := '0';
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipe : std_logic := '0';
SIGNAL round1_pipe : std_logic := '0';
SIGNAL saturate_pipe : std_logic := '0';
SIGNAL saturate1_pipe : std_logic := '0';
SIGNAL mode0_pipe : std_logic := '0';
SIGNAL mode1_pipe : std_logic := '0';
SIGNAL round0_out : std_logic := '0';
SIGNAL round1_out : std_logic := '0';
SIGNAL saturate_out : std_logic := '0';
SIGNAL saturate1_out : std_logic := '0';
SIGNAL mode0_out : std_logic := '0';
SIGNAL mode1_out : std_logic := '0';
SIGNAL addnsub0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL addnsub1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multabsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL multcdsaturate_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output1_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output2_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output3_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output4_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output5_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output6_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL output7_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_clk : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode0_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL mode1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate1_pipeline_aclr : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL clk_signa : std_logic := '0';
SIGNAL clear_signa : std_logic := '0';
SIGNAL aclr_signa : std_logic := '0';
SIGNAL ena_signa : std_logic := '0';
SIGNAL async_signa : std_logic := '0';
SIGNAL clk_signb : std_logic := '0';
SIGNAL clear_signb : std_logic := '0';
SIGNAL aclr_signb : std_logic := '0';
SIGNAL ena_signb : std_logic := '0';
SIGNAL async_signb : std_logic := '0';
SIGNAL clk_zeroacc : std_logic := '0';
SIGNAL clear_zeroacc : std_logic := '0';
SIGNAL aclr_zeroacc : std_logic := '0';
SIGNAL ena_zeroacc : std_logic := '0';
SIGNAL async_zeroacc : std_logic := '0';
SIGNAL clk_zeroacc1 : std_logic := '0';
SIGNAL clear_zeroacc1 : std_logic := '0';
SIGNAL aclr_zeroacc1 : std_logic := '0';
SIGNAL ena_zeroacc1 : std_logic := '0';
SIGNAL async_zeroacc1 : std_logic := '0';
SIGNAL clk_addnsub0 : std_logic := '0';
SIGNAL clear_addnsub0 : std_logic := '0';
SIGNAL aclr_addnsub0 : std_logic := '0';
SIGNAL ena_addnsub0 : std_logic := '0';
SIGNAL async_addnsub0 : std_logic := '0';
SIGNAL clk_addnsub1 : std_logic := '0';
SIGNAL clear_addnsub1 : std_logic := '0';
SIGNAL aclr_addnsub1 : std_logic := '0';
SIGNAL ena_addnsub1 : std_logic := '0';
SIGNAL async_addnsub1 : std_logic := '0';
SIGNAL clk_round0 : std_logic := '0';
SIGNAL clear_round0 : std_logic := '0';
SIGNAL aclr_round0 : std_logic := '0';
SIGNAL ena_round0 : std_logic := '0';
SIGNAL async_round0 : std_logic := '0';
SIGNAL clk_saturate : std_logic := '0';
SIGNAL clear_saturate : std_logic := '0';
SIGNAL aclr_saturate : std_logic := '0';
SIGNAL ena_saturate : std_logic := '0';
SIGNAL async_saturate : std_logic := '0';
SIGNAL clk_mode0 : std_logic := '0';
SIGNAL clear_mode0 : std_logic := '0';
SIGNAL aclr_mode0 : std_logic := '0';
SIGNAL ena_mode0 : std_logic := '0';
SIGNAL async_mode0 : std_logic := '0';
SIGNAL clk_round1 : std_logic := '0';
SIGNAL clear_round1 : std_logic := '0';
SIGNAL aclr_round1 : std_logic := '0';
SIGNAL ena_round1 : std_logic := '0';
SIGNAL async_round1 : std_logic := '0';
SIGNAL clk_saturate1 : std_logic := '0';
SIGNAL clear_saturate1 : std_logic := '0';
SIGNAL aclr_saturate1 : std_logic := '0';
SIGNAL ena_saturate1 : std_logic := '0';
SIGNAL async_saturate1 : std_logic := '0';
SIGNAL clk_mode1 : std_logic := '0';
SIGNAL clear_mode1 : std_logic := '0';
SIGNAL aclr_mode1 : std_logic := '0';
SIGNAL ena_mode1 : std_logic := '0';
SIGNAL async_mode1 : std_logic := '0';
SIGNAL clk_multabsaturate : std_logic := '0';
SIGNAL clear_multabsaturate : std_logic := '0';
SIGNAL aclr_multabsaturate : std_logic := '0';
SIGNAL ena_multabsaturate : std_logic := '0';
SIGNAL async_multabsaturate : std_logic := '0';
SIGNAL clk_multcdsaturate : std_logic := '0';
SIGNAL clear_multcdsaturate : std_logic := '0';
SIGNAL aclr_multcdsaturate : std_logic := '0';
SIGNAL ena_multcdsaturate : std_logic := '0';
SIGNAL async_multcdsaturate : std_logic := '0';
SIGNAL clk_signa_pipeline : std_logic := '0';
SIGNAL clear_signa_pipeline : std_logic := '0';
SIGNAL aclr_signa_pipeline : std_logic := '0';
SIGNAL ena_signa_pipeline : std_logic := '0';
SIGNAL async_signa_pipeline : std_logic := '0';
SIGNAL clk_signb_pipeline : std_logic := '0';
SIGNAL clear_signb_pipeline : std_logic := '0';
SIGNAL aclr_signb_pipeline : std_logic := '0';
SIGNAL ena_signb_pipeline : std_logic := '0';
SIGNAL async_signb_pipeline : std_logic := '0';
SIGNAL clk_zeroacc_pipeline : std_logic := '0';
SIGNAL clear_zeroacc_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc_pipeline : std_logic := '0';
SIGNAL ena_zeroacc_pipeline : std_logic := '0';
SIGNAL async_zeroacc_pipeline : std_logic := '0';
SIGNAL clk_zeroacc1_pipeline : std_logic := '0';
SIGNAL clear_zeroacc1_pipeline : std_logic := '0';
SIGNAL aclr_zeroacc1_pipeline : std_logic := '0';
SIGNAL ena_zeroacc1_pipeline : std_logic := '0';
SIGNAL async_zeroacc1_pipeline : std_logic := '0';
SIGNAL clk_addnsub0_pipeline : std_logic := '0';
SIGNAL clear_addnsub0_pipeline : std_logic := '0';
SIGNAL aclr_addnsub0_pipeline : std_logic := '0';
SIGNAL ena_addnsub0_pipeline : std_logic := '0';
SIGNAL async_addnsub0_pipeline : std_logic := '0';
SIGNAL clk_addnsub1_pipeline : std_logic := '0';
SIGNAL clear_addnsub1_pipeline : std_logic := '0';
SIGNAL aclr_addnsub1_pipeline : std_logic := '0';
SIGNAL ena_addnsub1_pipeline : std_logic := '0';
SIGNAL async_addnsub1_pipeline : std_logic := '0';
SIGNAL clk_round0_pipeline : std_logic := '0';
SIGNAL clear_round0_pipeline : std_logic := '0';
SIGNAL aclr_round0_pipeline : std_logic := '0';
SIGNAL ena_round0_pipeline : std_logic := '0';
SIGNAL async_round0_pipeline : std_logic := '0';
SIGNAL clk_saturate_pipeline : std_logic := '0';
SIGNAL clear_saturate_pipeline : std_logic := '0';
SIGNAL aclr_saturate_pipeline : std_logic := '0';
SIGNAL ena_saturate_pipeline : std_logic := '0';
SIGNAL async_saturate_pipeline : std_logic := '0';
SIGNAL clk_mode0_pipeline : std_logic := '0';
SIGNAL clear_mode0_pipeline : std_logic := '0';
SIGNAL aclr_mode0_pipeline : std_logic := '0';
SIGNAL ena_mode0_pipeline : std_logic := '0';
SIGNAL async_mode0_pipeline : std_logic := '0';
SIGNAL clk_round1_pipeline : std_logic := '0';
SIGNAL clear_round1_pipeline : std_logic := '0';
SIGNAL aclr_round1_pipeline : std_logic := '0';
SIGNAL ena_round1_pipeline : std_logic := '0';
SIGNAL async_round1_pipeline : std_logic := '0';
SIGNAL clk_saturate1_pipeline : std_logic := '0';
SIGNAL clear_saturate1_pipeline : std_logic := '0';
SIGNAL aclr_saturate1_pipeline : std_logic := '0';
SIGNAL ena_saturate1_pipeline : std_logic := '0';
SIGNAL async_saturate1_pipeline : std_logic := '0';
SIGNAL clk_mode1_pipeline : std_logic := '0';
SIGNAL clear_mode1_pipeline : std_logic := '0';
SIGNAL aclr_mode1_pipeline : std_logic := '0';
SIGNAL ena_mode1_pipeline : std_logic := '0';
SIGNAL async_mode1_pipeline : std_logic := '0';
SIGNAL clk_multabsaturate_pipeline : std_logic := '0';
SIGNAL clear_multabsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multabsaturate_pipeline : std_logic := '0';
SIGNAL ena_multabsaturate_pipeline : std_logic := '0';
SIGNAL async_multabsaturate_pipeline : std_logic := '0';
SIGNAL clk_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clear_multcdsaturate_pipeline : std_logic := '0';
SIGNAL aclr_multcdsaturate_pipeline : std_logic := '0';
SIGNAL ena_multcdsaturate_pipeline : std_logic := '0';
SIGNAL async_multcdsaturate_pipeline : std_logic := '0';
SIGNAL clk_output : std_logic := '0';
SIGNAL clear_output : std_logic := '0';
SIGNAL aclr_output : std_logic := '0';
SIGNAL ena_output : std_logic := '0';
SIGNAL async_output : std_logic := '0';
SIGNAL clk_output1 : std_logic := '0';
SIGNAL clear_output1 : std_logic := '0';
SIGNAL aclr_output1 : std_logic := '0';
SIGNAL ena_output1 : std_logic := '0';
SIGNAL async_output1 : std_logic := '0';
SIGNAL clk_output2 : std_logic := '0';
SIGNAL clear_output2 : std_logic := '0';
SIGNAL aclr_output2 : std_logic := '0';
SIGNAL ena_output2 : std_logic := '0';
SIGNAL async_output2 : std_logic := '0';
SIGNAL clk_output3 : std_logic := '0';
SIGNAL clear_output3 : std_logic := '0';
SIGNAL aclr_output3 : std_logic := '0';
SIGNAL ena_output3 : std_logic := '0';
SIGNAL async_output3 : std_logic := '0';
SIGNAL clk_output4 : std_logic := '0';
SIGNAL clear_output4 : std_logic := '0';
SIGNAL aclr_output4 : std_logic := '0';
SIGNAL ena_output4 : std_logic := '0';
SIGNAL async_output4 : std_logic := '0';
SIGNAL clk_output5 : std_logic := '0';
SIGNAL clear_output5 : std_logic := '0';
SIGNAL aclr_output5 : std_logic := '0';
SIGNAL ena_output5 : std_logic := '0';
SIGNAL async_output5 : std_logic := '0';
SIGNAL clk_output6 : std_logic := '0';
SIGNAL clear_output6 : std_logic := '0';
SIGNAL aclr_output6 : std_logic := '0';
SIGNAL ena_output6 : std_logic := '0';
SIGNAL async_output6 : std_logic := '0';
SIGNAL clk_output7 : std_logic := '0';
SIGNAL clear_output7 : std_logic := '0';
SIGNAL aclr_output7 : std_logic := '0';
SIGNAL ena_output7 : std_logic := '0';
SIGNAL async_output7 : std_logic := '0';
SIGNAL tmp_186 : std_logic := '0';
SIGNAL tmp_189 : std_logic := '0';
SIGNAL accoverflow_tmp2 : std_logic := '0';
SIGNAL pin_map_addnsub : std_logic := '0';
BEGIN
dataout <= dataout_tmp(dataout'range);
accoverflow <= accoverflow_tmp2;
signa_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa,
clk => clk_signa,
aclr => aclr_signa,
if_aclr => clear_signa,
ena => ena_signa,
dataout => signa_pipe,
async => async_signa);
async_signa <= '1' WHEN (signa_clock = "none") ELSE '0' ;
clear_signa <= '1' WHEN (signa_clear /= "none") ELSE '0' ;
clk_signa <= '1' WHEN clk(conv_integer(signa_clk)) = '1' ELSE '0' ;
aclr_signa <= '1' WHEN (aclr(conv_integer(signa_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa <= '1' WHEN ena(conv_integer(signa_clk)) = '1' ELSE '0' ;
signa_clk <= "0000" WHEN ((signa_clock = "0") OR (signa_clock = "none")) ELSE "0001" WHEN (signa_clock = "1") ELSE "0010" WHEN (signa_clock = "2") ELSE "0011" WHEN (signa_clock = "3") ELSE "0000" ;
signa_aclr <= "0000" WHEN ((signa_clear = "0") OR (signa_clear = "none")) ELSE "0001" WHEN (signa_clear = "1") ELSE "0010" WHEN (signa_clear = "2") ELSE "0011" WHEN (signa_clear = "3") ELSE "0000" ;
signb_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb,
clk => clk_signb,
aclr => aclr_signb,
if_aclr => clear_signb,
ena => ena_signb,
dataout => signb_pipe,
async => async_signb);
async_signb <= '1' WHEN (signb_clock = "none") ELSE '0' ;
clear_signb <= '1' WHEN (signb_clear /= "none") ELSE '0' ;
clk_signb <= '1' WHEN clk(conv_integer(signb_clk)) = '1' ELSE '0' ;
aclr_signb <= '1' WHEN (aclr(conv_integer(signb_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb <= '1' WHEN ena(conv_integer(signb_clk)) = '1' ELSE '0' ;
signb_clk <= "0000" WHEN ((signb_clock = "0") OR (signb_clock = "none")) ELSE "0001" WHEN (signb_clock = "1") ELSE "0010" WHEN (signb_clock = "2") ELSE "0011" WHEN (signb_clock = "3") ELSE "0000" ;
signb_aclr <= "0000" WHEN ((signb_clear = "0") OR (signb_clear = "none")) ELSE "0001" WHEN (signb_clear = "1") ELSE "0010" WHEN (signb_clear = "2") ELSE "0011" WHEN (signb_clear = "3") ELSE "0000" ;
zeroacc_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc,
clk => clk_zeroacc,
aclr => aclr_zeroacc,
if_aclr => clear_zeroacc,
ena => ena_zeroacc,
dataout => zeroacc_pipe,
async => async_zeroacc);
async_zeroacc <= '1' WHEN (zeroacc_clock = "none") ELSE '0' ;
clear_zeroacc <= '1' WHEN (zeroacc_clear /= "none") ELSE '0' ;
clk_zeroacc <= '1' WHEN clk(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
aclr_zeroacc <= '1' WHEN (aclr(conv_integer(zeroacc_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc <= '1' WHEN ena(conv_integer(zeroacc_clk)) = '1' ELSE '0' ;
zeroacc_clk <= "0000" WHEN ((zeroacc_clock = "0") OR (zeroacc_clock = "none")) ELSE "0001" WHEN (zeroacc_clock = "1") ELSE "0010" WHEN (zeroacc_clock = "2") ELSE "0011" WHEN (zeroacc_clock = "3") ELSE "0000" ;
zeroacc_aclr <= "0000" WHEN ((zeroacc_clear = "0") OR (zeroacc_clear = "none")) ELSE "0001" WHEN (zeroacc_clear = "1") ELSE "0010" WHEN (zeroacc_clear = "2") ELSE "0011" WHEN (zeroacc_clear = "3") ELSE "0000" ;
zeroacc1_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1,
clk => clk_zeroacc1,
aclr => aclr_zeroacc1,
if_aclr => clear_zeroacc1,
ena => ena_zeroacc1,
dataout => zeroacc1_pipe,
async => async_zeroacc1);
async_zeroacc1 <= '1' WHEN (zeroacc1_clock = "none") ELSE '0' ;
clear_zeroacc1 <= '1' WHEN (zeroacc1_clear /= "none") ELSE '0' ;
clk_zeroacc1 <= '1' WHEN clk(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
aclr_zeroacc1 <= '1' WHEN (aclr(conv_integer(zeroacc1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1 <= '1' WHEN ena(conv_integer(zeroacc1_clk)) = '1' ELSE '0' ;
zeroacc1_clk <= "0000" WHEN ((zeroacc1_clock = "0") OR (zeroacc1_clock = "none")) ELSE "0001" WHEN (zeroacc1_clock = "1") ELSE "0010" WHEN (zeroacc1_clock = "2") ELSE "0011" WHEN (zeroacc1_clock = "3") ELSE "0000" ;
zeroacc1_aclr <= "0000" WHEN ((zeroacc1_clear = "0") OR (zeroacc1_clear = "none")) ELSE "0001" WHEN (zeroacc1_clear = "1") ELSE "0010" WHEN (zeroacc1_clear = "2") ELSE "0011" WHEN (zeroacc1_clear = "3") ELSE "0000" ;
addnsub0_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0,
clk => clk_addnsub0,
aclr => aclr_addnsub0,
if_aclr => clear_addnsub0,
ena => ena_addnsub0,
dataout => addnsub0_pipe,
async => async_addnsub0);
async_addnsub0 <= '1' WHEN (addnsub0_clock = "none") ELSE '0' ;
clear_addnsub0 <= '1' WHEN (addnsub0_clear /= "none") ELSE '0' ;
clk_addnsub0 <= '1' WHEN clk(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
aclr_addnsub0 <= '1' WHEN (aclr(conv_integer(addnsub0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0 <= '1' WHEN ena(conv_integer(addnsub0_clk)) = '1' ELSE '0' ;
addnsub0_clk <= "0000" WHEN ((addnsub0_clock = "0") OR (addnsub0_clock = "none")) ELSE "0001" WHEN (addnsub0_clock = "1") ELSE "0010" WHEN (addnsub0_clock = "2") ELSE "0011" WHEN (addnsub0_clock = "3") ELSE "0000" ;
addnsub0_aclr <= "0000" WHEN ((addnsub0_clear = "0") OR (addnsub0_clear = "none")) ELSE "0001" WHEN (addnsub0_clear = "1") ELSE "0010" WHEN (addnsub0_clear = "2") ELSE "0011" WHEN (addnsub0_clear = "3") ELSE "0000" ;
addnsub1_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1,
clk => clk_addnsub1,
aclr => aclr_addnsub1,
if_aclr => clear_addnsub1,
ena => ena_addnsub1,
dataout => addnsub1_pipe,
async => async_addnsub1);
async_addnsub1 <= '1' WHEN (addnsub1_clock = "none") ELSE '0' ;
clear_addnsub1 <= '1' WHEN (addnsub1_clear /= "none") ELSE '0' ;
clk_addnsub1 <= '1' WHEN clk(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
aclr_addnsub1 <= '1' WHEN (aclr(conv_integer(addnsub1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1 <= '1' WHEN ena(conv_integer(addnsub1_clk)) = '1' ELSE '0' ;
addnsub1_clk <= "0000" WHEN ((addnsub1_clock = "0") OR (addnsub1_clock = "none")) ELSE "0001" WHEN (addnsub1_clock = "1") ELSE "0010" WHEN (addnsub1_clock = "2") ELSE "0011" WHEN (addnsub1_clock = "3") ELSE "0000" ;
addnsub1_aclr <= "0000" WHEN ((addnsub1_clear = "0") OR (addnsub1_clear = "none")) ELSE "0001" WHEN (addnsub1_clear = "1") ELSE "0010" WHEN (addnsub1_clear = "2") ELSE "0011" WHEN (addnsub1_clear = "3") ELSE "0000" ;
round0_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0,
clk => clk_round0,
aclr => aclr_round0,
if_aclr => clear_round0,
ena => ena_round0,
dataout => round0_pipe,
async => async_round0);
async_round0 <= '1' WHEN (round0_clock = "none") ELSE '0' ;
clear_round0 <= '1' WHEN (round0_clear /= "none") ELSE '0' ;
clk_round0 <= '1' WHEN clk(conv_integer(round0_clk)) = '1' ELSE '0' ;
aclr_round0 <= '1' WHEN (aclr(conv_integer(round0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0 <= '1' WHEN ena(conv_integer(round0_clk)) = '1' ELSE '0' ;
round0_clk <= "0000" WHEN ((round0_clock = "0") OR (round0_clock = "none")) ELSE "0001" WHEN (round0_clock = "1") ELSE "0010" WHEN (round0_clock = "2") ELSE "0011" WHEN (round0_clock = "3") ELSE "0000" ;
round0_aclr <= "0000" WHEN ((round0_clear = "0") OR (round0_clear = "none")) ELSE "0001" WHEN (round0_clear = "1") ELSE "0010" WHEN (round0_clear = "2") ELSE "0011" WHEN (round0_clear = "3") ELSE "0000" ;
saturate_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate,
clk => clk_saturate,
aclr => aclr_saturate,
if_aclr => clear_saturate,
ena => ena_saturate,
dataout => saturate_pipe,
async => async_saturate);
async_saturate <= '1' WHEN (saturate_clock = "none") ELSE '0' ;
clear_saturate <= '1' WHEN (saturate_clear /= "none") ELSE '0' ;
clk_saturate <= '1' WHEN clk(conv_integer(saturate_clk)) = '1' ELSE '0' ;
aclr_saturate <= '1' WHEN (aclr(conv_integer(saturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate <= '1' WHEN ena(conv_integer(saturate_clk)) = '1' ELSE '0' ;
saturate_clk <= "0000" WHEN ((saturate_clock = "0") OR (saturate_clock = "none")) ELSE "0001" WHEN (saturate_clock = "1") ELSE "0010" WHEN (saturate_clock = "2") ELSE "0011" WHEN (saturate_clock = "3") ELSE "0000" ;
saturate_aclr <= "0000" WHEN ((saturate_clear = "0") OR (saturate_clear = "none")) ELSE "0001" WHEN (saturate_clear = "1") ELSE "0010" WHEN (saturate_clear = "2") ELSE "0011" WHEN (saturate_clear = "3") ELSE "0000" ;
mode0_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0,
clk => clk_mode0,
aclr => aclr_mode0,
if_aclr => clear_mode0,
ena => ena_mode0,
dataout => mode0_pipe,
async => async_mode0);
async_mode0 <= '1' WHEN (mode0_clock = "none") ELSE '0' ;
clear_mode0 <= '1' WHEN (mode0_clear /= "none") ELSE '0' ;
clk_mode0 <= '1' WHEN clk(conv_integer(mode0_clk)) = '1' ELSE '0' ;
aclr_mode0 <= '1' WHEN (aclr(conv_integer(mode0_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0 <= '1' WHEN ena(conv_integer(mode0_clk)) = '1' ELSE '0' ;
mode0_clk <= "0000" WHEN ((mode0_clock = "0") OR (mode0_clock = "none")) ELSE "0001" WHEN (mode0_clock = "1") ELSE "0010" WHEN (mode0_clock = "2") ELSE "0011" WHEN (mode0_clock = "3") ELSE "0000" ;
mode0_aclr <= "0000" WHEN ((mode0_clear = "0") OR (mode0_clear = "none")) ELSE "0001" WHEN (mode0_clear = "1") ELSE "0010" WHEN (mode0_clear = "2") ELSE "0011" WHEN (mode0_clear = "3") ELSE "0000" ;
round1_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1,
clk => clk_round1,
aclr => aclr_round1,
if_aclr => clear_round1,
ena => ena_round1,
dataout => round1_pipe,
async => async_round1);
async_round1 <= '1' WHEN (round1_clock = "none") ELSE '0' ;
clear_round1 <= '1' WHEN (round1_clear /= "none") ELSE '0' ;
clk_round1 <= '1' WHEN clk(conv_integer(round1_clk)) = '1' ELSE '0' ;
aclr_round1 <= '1' WHEN (aclr(conv_integer(round1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1 <= '1' WHEN ena(conv_integer(round1_clk)) = '1' ELSE '0' ;
round1_clk <= "0000" WHEN ((round1_clock = "0") OR (round1_clock = "none")) ELSE "0001" WHEN (round1_clock = "1") ELSE "0010" WHEN (round1_clock = "2") ELSE "0011" WHEN (round1_clock = "3") ELSE "0000" ;
round1_aclr <= "0000" WHEN ((round1_clear = "0") OR (round1_clear = "none")) ELSE "0001" WHEN (round1_clear = "1") ELSE "0010" WHEN (round1_clear = "2") ELSE "0011" WHEN (round1_clear = "3") ELSE "0000" ;
saturate1_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1,
clk => clk_saturate1,
aclr => aclr_saturate1,
if_aclr => clear_saturate1,
ena => ena_saturate1,
dataout => saturate1_pipe,
async => async_saturate1);
async_saturate1 <= '1' WHEN (saturate1_clock = "none") ELSE '0' ;
clear_saturate1 <= '1' WHEN (saturate1_clear /= "none") ELSE '0' ;
clk_saturate1 <= '1' WHEN clk(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
aclr_saturate1 <= '1' WHEN (aclr(conv_integer(saturate1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1 <= '1' WHEN ena(conv_integer(saturate1_clk)) = '1' ELSE '0' ;
saturate1_clk <= "0000" WHEN ((saturate1_clock = "0") OR (saturate1_clock = "none")) ELSE "0001" WHEN (saturate1_clock = "1") ELSE "0010" WHEN (saturate1_clock = "2") ELSE "0011" WHEN (saturate1_clock = "3") ELSE "0000" ;
saturate1_aclr <= "0000" WHEN ((saturate1_clear = "0") OR (saturate1_clear = "none")) ELSE "0001" WHEN (saturate1_clear = "1") ELSE "0010" WHEN (saturate1_clear = "2") ELSE "0011" WHEN (saturate1_clear = "3") ELSE "0000" ;
mode1_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1,
clk => clk_mode1,
aclr => aclr_mode1,
if_aclr => clear_mode1,
ena => ena_mode1,
dataout => mode1_pipe,
async => async_mode1);
async_mode1 <= '1' WHEN (mode1_clock = "none") ELSE '0' ;
clear_mode1 <= '1' WHEN (mode1_clear /= "none") ELSE '0' ;
clk_mode1 <= '1' WHEN clk(conv_integer(mode1_clk)) = '1' ELSE '0' ;
aclr_mode1 <= '1' WHEN (aclr(conv_integer(mode1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1 <= '1' WHEN ena(conv_integer(mode1_clk)) = '1' ELSE '0' ;
mode1_clk <= "0000" WHEN ((mode1_clock = "0") OR (mode1_clock = "none")) ELSE "0001" WHEN (mode1_clock = "1") ELSE "0010" WHEN (mode1_clock = "2") ELSE "0011" WHEN (mode1_clock = "3") ELSE "0000" ;
mode1_aclr <= "0000" WHEN ((mode1_clear = "0") OR (mode1_clear = "none")) ELSE "0001" WHEN (mode1_clear = "1") ELSE "0010" WHEN (mode1_clear = "2") ELSE "0011" WHEN (mode1_clear = "3") ELSE "0000" ;
multabsaturate_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate,
clk => clk_multabsaturate,
aclr => aclr_multabsaturate,
if_aclr => clear_multabsaturate,
ena => ena_multabsaturate,
dataout => multabsaturate_pipe,
async => async_multabsaturate);
async_multabsaturate <= '1' WHEN (multabsaturate_clock = "none") ELSE '0' ;
clear_multabsaturate <= '1' WHEN (multabsaturate_clear /= "none") ELSE '0' ;
clk_multabsaturate <= '1' WHEN clk(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
aclr_multabsaturate <= '1' WHEN (aclr(conv_integer(multabsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate <= '1' WHEN ena(conv_integer(multabsaturate_clk)) = '1' ELSE '0' ;
multabsaturate_clk <= "0000" WHEN ((multabsaturate_clock = "0") OR (multabsaturate_clock = "none")) ELSE "0001" WHEN (multabsaturate_clock = "1") ELSE "0010" WHEN (multabsaturate_clock = "2") ELSE "0011" WHEN (multabsaturate_clock = "3") ELSE "0000" ;
multabsaturate_aclr <= "0000" WHEN ((multabsaturate_clear = "0") OR (multabsaturate_clear = "none")) ELSE "0001" WHEN (multabsaturate_clear = "1") ELSE "0010" WHEN (multabsaturate_clear = "2") ELSE "0011" WHEN (multabsaturate_clear = "3") ELSE "0000" ;
multcdsaturate_mac_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate,
clk => clk_multcdsaturate,
aclr => aclr_multcdsaturate,
if_aclr => clear_multcdsaturate,
ena => ena_multcdsaturate,
dataout => multcdsaturate_pipe,
async => async_multcdsaturate);
async_multcdsaturate <= '1' WHEN (multcdsaturate_clock = "none") ELSE '0' ;
clear_multcdsaturate <= '1' WHEN (multcdsaturate_clear /= "none") ELSE '0' ;
clk_multcdsaturate <= '1' WHEN clk(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate <= '1' WHEN (aclr(conv_integer(multcdsaturate_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate <= '1' WHEN ena(conv_integer(multcdsaturate_clk)) = '1' ELSE '0' ;
multcdsaturate_clk <= "0000" WHEN ((multcdsaturate_clock = "0") OR (multcdsaturate_clock = "none")) ELSE "0001" WHEN (multcdsaturate_clock = "1") ELSE "0010" WHEN (multcdsaturate_clock = "2") ELSE "0011" WHEN (multcdsaturate_clock = "3") ELSE "0000" ;
multcdsaturate_aclr <= "0000" WHEN ((multcdsaturate_clear = "0") OR (multcdsaturate_clear = "none")) ELSE "0001" WHEN (multcdsaturate_clear = "1") ELSE "0010" WHEN (multcdsaturate_clear = "2") ELSE "0011" WHEN (multcdsaturate_clear = "3") ELSE "0000" ;
signa_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signa_pipe,
clk => clk_signa_pipeline,
aclr => aclr_signa_pipeline,
if_aclr => clear_signa_pipeline,
ena => ena_signa_pipeline,
dataout => signa_out,
async => async_signa_pipeline);
async_signa_pipeline <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0' ;
clear_signa_pipeline <= '1' WHEN (signa_pipeline_clear /= "none") ELSE '0' ;
clk_signa_pipeline <= '1' WHEN clk(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
aclr_signa_pipeline <= '1' WHEN (aclr(conv_integer(signa_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signa_pipeline <= '1' WHEN ena(conv_integer(signa_pipeline_clk)) = '1' ELSE '0' ;
signa_pipeline_clk <= "0000" WHEN ((signa_pipeline_clock = "0") OR (signa_pipeline_clock = "none")) ELSE "0001" WHEN (signa_pipeline_clock = "1") ELSE "0010" WHEN (signa_pipeline_clock = "2") ELSE "0011" WHEN (signa_pipeline_clock = "3") ELSE "0000" ;
signa_pipeline_aclr <= "0000" WHEN ((signa_pipeline_clear = "0") OR (signa_pipeline_clear = "none")) ELSE "0001" WHEN (signa_pipeline_clear = "1") ELSE "0010" WHEN (signa_pipeline_clear = "2") ELSE "0011" WHEN (signa_pipeline_clear = "3") ELSE "0000" ;
signb_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => signb_pipe,
clk => clk_signb_pipeline,
aclr => aclr_signb_pipeline,
if_aclr => clear_signb_pipeline,
ena => ena_signb_pipeline,
dataout => signb_out,
async => async_signb_pipeline);
async_signb_pipeline <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0' ;
clear_signb_pipeline <= '1' WHEN (signb_pipeline_clear /= "none") ELSE '0' ;
clk_signb_pipeline <= '1' WHEN clk(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
aclr_signb_pipeline <= '1' WHEN (aclr(conv_integer(signb_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_signb_pipeline <= '1' WHEN ena(conv_integer(signb_pipeline_clk)) = '1' ELSE '0' ;
signb_pipeline_clk <= "0000" WHEN ((signb_pipeline_clock = "0") OR (signb_pipeline_clock = "none")) ELSE "0001" WHEN (signb_pipeline_clock = "1") ELSE "0010" WHEN (signb_pipeline_clock = "2") ELSE "0011" WHEN (signb_pipeline_clock = "3") ELSE "0000" ;
signb_pipeline_aclr <= "0000" WHEN ((signb_pipeline_clear = "0") OR (signb_pipeline_clear = "none")) ELSE "0001" WHEN (signb_pipeline_clear = "1") ELSE "0010" WHEN (signb_pipeline_clear = "2") ELSE "0011" WHEN (signb_pipeline_clear = "3") ELSE "0000" ;
zeroacc_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc_pipe,
clk => clk_zeroacc_pipeline,
aclr => aclr_zeroacc_pipeline,
if_aclr => clear_zeroacc_pipeline,
ena => ena_zeroacc_pipeline,
dataout => zeroacc_out,
async => async_zeroacc_pipeline);
async_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc_pipeline <= '1' WHEN (zeroacc_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc_pipeline <= '1' WHEN clk(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc_pipeline <= '1' WHEN ena(conv_integer(zeroacc_pipeline_clk)) = '1' ELSE '0' ;
zeroacc_pipeline_clk <= "0000" WHEN ((zeroacc_pipeline_clock = "0") OR (zeroacc_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc_pipeline_clock = "3") ELSE "0000" ;
zeroacc_pipeline_aclr <= "0000" WHEN ((zeroacc_pipeline_clear = "0") OR (zeroacc_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc_pipeline_clear = "3") ELSE "0000" ;
zeroacc1_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => zeroacc1_pipe,
clk => clk_zeroacc1_pipeline,
aclr => aclr_zeroacc1_pipeline,
if_aclr => clear_zeroacc1_pipeline,
ena => ena_zeroacc1_pipeline,
dataout => zeroacc1_out,
async => async_zeroacc1_pipeline);
async_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clock = "none") ELSE '0' ;
clear_zeroacc1_pipeline <= '1' WHEN (zeroacc1_pipeline_clear /= "none") ELSE '0' ;
clk_zeroacc1_pipeline <= '1' WHEN clk(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
aclr_zeroacc1_pipeline <= '1' WHEN (aclr(conv_integer(zeroacc1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_zeroacc1_pipeline <= '1' WHEN ena(conv_integer(zeroacc1_pipeline_clk)) = '1' ELSE '0' ;
zeroacc1_pipeline_clk <= "0000" WHEN ((zeroacc1_pipeline_clock = "0") OR (zeroacc1_pipeline_clock = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clock = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clock = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clock = "3") ELSE "0000" ;
zeroacc1_pipeline_aclr <= "0000" WHEN ((zeroacc1_pipeline_clear = "0") OR (zeroacc1_pipeline_clear = "none")) ELSE "0001" WHEN (zeroacc1_pipeline_clear = "1") ELSE "0010" WHEN (zeroacc1_pipeline_clear = "2") ELSE "0011" WHEN (zeroacc1_pipeline_clear = "3") ELSE "0000" ;
addnsub0_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub0_pipe,
clk => clk_addnsub0_pipeline,
aclr => aclr_addnsub0_pipeline,
if_aclr => clear_addnsub0_pipeline,
ena => ena_addnsub0_pipeline,
dataout => addnsub0_out,
async => async_addnsub0_pipeline);
async_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clock = "none") ELSE '0' ;
clear_addnsub0_pipeline <= '1' WHEN (addnsub0_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub0_pipeline <= '1' WHEN clk(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub0_pipeline <= '1' WHEN (aclr(conv_integer(addnsub0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub0_pipeline <= '1' WHEN ena(conv_integer(addnsub0_pipeline_clk)) = '1' ELSE '0' ;
addnsub0_pipeline_clk <= "0000" WHEN ((addnsub0_pipeline_clock = "0") OR (addnsub0_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clock = "1") ELSE "0010" WHEN (addnsub0_pipeline_clock = "2") ELSE "0011" WHEN (addnsub0_pipeline_clock = "3") ELSE "0000" ;
addnsub0_pipeline_aclr <= "0000" WHEN ((addnsub0_pipeline_clear = "0") OR (addnsub0_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub0_pipeline_clear = "1") ELSE "0010" WHEN (addnsub0_pipeline_clear = "2") ELSE "0011" WHEN (addnsub0_pipeline_clear = "3") ELSE "0000" ;
addnsub1_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => addnsub1_pipe,
clk => clk_addnsub1_pipeline,
aclr => aclr_addnsub1_pipeline,
if_aclr => clear_addnsub1_pipeline,
ena => ena_addnsub1_pipeline,
dataout => addnsub1_out,
async => async_addnsub1_pipeline);
async_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clock = "none") ELSE '0' ;
clear_addnsub1_pipeline <= '1' WHEN (addnsub1_pipeline_clear /= "none") ELSE '0' ;
clk_addnsub1_pipeline <= '1' WHEN clk(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
aclr_addnsub1_pipeline <= '1' WHEN (aclr(conv_integer(addnsub1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_addnsub1_pipeline <= '1' WHEN ena(conv_integer(addnsub1_pipeline_clk)) = '1' ELSE '0' ;
addnsub1_pipeline_clk <= "0000" WHEN ((addnsub1_pipeline_clock = "0") OR (addnsub1_pipeline_clock = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clock = "1") ELSE "0010" WHEN (addnsub1_pipeline_clock = "2") ELSE "0011" WHEN (addnsub1_pipeline_clock = "3") ELSE "0000" ;
addnsub1_pipeline_aclr <= "0000" WHEN ((addnsub1_pipeline_clear = "0") OR (addnsub1_pipeline_clear = "none")) ELSE "0001" WHEN (addnsub1_pipeline_clear = "1") ELSE "0010" WHEN (addnsub1_pipeline_clear = "2") ELSE "0011" WHEN (addnsub1_pipeline_clear = "3") ELSE "0000" ;
round0_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round0_pipe,
clk => clk_round0_pipeline,
aclr => aclr_round0_pipeline,
if_aclr => clear_round0_pipeline,
ena => ena_round0_pipeline,
dataout => round0_out,
async => async_round0_pipeline);
async_round0_pipeline <= '1' WHEN (round0_pipeline_clock = "none") ELSE '0' ;
clear_round0_pipeline <= '1' WHEN (round0_pipeline_clear /= "none") ELSE '0' ;
clk_round0_pipeline <= '1' WHEN clk(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
aclr_round0_pipeline <= '1' WHEN (aclr(conv_integer(round0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round0_pipeline <= '1' WHEN ena(conv_integer(round0_pipeline_clk)) = '1' ELSE '0' ;
round0_pipeline_clk <= "0000" WHEN ((round0_pipeline_clock = "0") OR (round0_pipeline_clock = "none")) ELSE "0001" WHEN (round0_pipeline_clock = "1") ELSE "0010" WHEN (round0_pipeline_clock = "2") ELSE "0011" WHEN (round0_pipeline_clock = "3") ELSE "0000" ;
round0_pipeline_aclr <= "0000" WHEN ((round0_pipeline_clear = "0") OR (round0_pipeline_clear = "none")) ELSE "0001" WHEN (round0_pipeline_clear = "1") ELSE "0010" WHEN (round0_pipeline_clear = "2") ELSE "0011" WHEN (round0_pipeline_clear = "3") ELSE "0000" ;
saturate_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate_pipe,
clk => clk_saturate_pipeline,
aclr => aclr_saturate_pipeline,
if_aclr => clear_saturate_pipeline,
ena => ena_saturate_pipeline,
dataout => saturate_out,
async => async_saturate_pipeline);
async_saturate_pipeline <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0' ;
clear_saturate_pipeline <= '1' WHEN (saturate_pipeline_clear /= "none") ELSE '0' ;
clk_saturate_pipeline <= '1' WHEN clk(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate_pipeline <= '1' WHEN (aclr(conv_integer(saturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate_pipeline <= '1' WHEN ena(conv_integer(saturate_pipeline_clk)) = '1' ELSE '0' ;
saturate_pipeline_clk <= "0000" WHEN ((saturate_pipeline_clock = "0") OR (saturate_pipeline_clock = "none")) ELSE "0001" WHEN (saturate_pipeline_clock = "1") ELSE "0010" WHEN (saturate_pipeline_clock = "2") ELSE "0011" WHEN (saturate_pipeline_clock = "3") ELSE "0000" ;
saturate_pipeline_aclr <= "0000" WHEN ((saturate_pipeline_clear = "0") OR (saturate_pipeline_clear = "none")) ELSE "0001" WHEN (saturate_pipeline_clear = "1") ELSE "0010" WHEN (saturate_pipeline_clear = "2") ELSE "0011" WHEN (saturate_pipeline_clear = "3") ELSE "0000" ;
mode0_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode0_pipe,
clk => clk_mode0_pipeline,
aclr => aclr_mode0_pipeline,
if_aclr => clear_mode0_pipeline,
ena => ena_mode0_pipeline,
dataout => mode0_out,
async => async_mode0_pipeline);
async_mode0_pipeline <= '1' WHEN (mode0_pipeline_clock = "none") ELSE '0' ;
clear_mode0_pipeline <= '1' WHEN (mode0_pipeline_clear /= "none") ELSE '0' ;
clk_mode0_pipeline <= '1' WHEN clk(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode0_pipeline <= '1' WHEN (aclr(conv_integer(mode0_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode0_pipeline <= '1' WHEN ena(conv_integer(mode0_pipeline_clk)) = '1' ELSE '0' ;
mode0_pipeline_clk <= "0000" WHEN ((mode0_pipeline_clock = "0") OR (mode0_pipeline_clock = "none")) ELSE "0001" WHEN (mode0_pipeline_clock = "1") ELSE "0010" WHEN (mode0_pipeline_clock = "2") ELSE "0011" WHEN (mode0_pipeline_clock = "3") ELSE "0000" ;
mode0_pipeline_aclr <= "0000" WHEN ((mode0_pipeline_clear = "0") OR (mode0_pipeline_clear = "none")) ELSE "0001" WHEN (mode0_pipeline_clear = "1") ELSE "0010" WHEN (mode0_pipeline_clear = "2") ELSE "0011" WHEN (mode0_pipeline_clear = "3") ELSE "0000" ;
round1_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => round1_pipe,
clk => clk_round1_pipeline,
aclr => aclr_round1_pipeline,
if_aclr => clear_round1_pipeline,
ena => ena_round1_pipeline,
dataout => round1_out,
async => async_round1_pipeline);
async_round1_pipeline <= '1' WHEN (round1_pipeline_clock = "none") ELSE '0' ;
clear_round1_pipeline <= '1' WHEN (round1_pipeline_clear /= "none") ELSE '0' ;
clk_round1_pipeline <= '1' WHEN clk(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
aclr_round1_pipeline <= '1' WHEN (aclr(conv_integer(round1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_round1_pipeline <= '1' WHEN ena(conv_integer(round1_pipeline_clk)) = '1' ELSE '0' ;
round1_pipeline_clk <= "0000" WHEN ((round1_pipeline_clock = "0") OR (round1_pipeline_clock = "none")) ELSE "0001" WHEN (round1_pipeline_clock = "1") ELSE "0010" WHEN (round1_pipeline_clock = "2") ELSE "0011" WHEN (round1_pipeline_clock = "3") ELSE "0000" ;
round1_pipeline_aclr <= "0000" WHEN ((round1_pipeline_clear = "0") OR (round1_pipeline_clear = "none")) ELSE "0001" WHEN (round1_pipeline_clear = "1") ELSE "0010" WHEN (round1_pipeline_clear = "2") ELSE "0011" WHEN (round1_pipeline_clear = "3") ELSE "0000" ;
saturate1_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => saturate1_pipe,
clk => clk_saturate1_pipeline,
aclr => aclr_saturate1_pipeline,
if_aclr => clear_saturate1_pipeline,
ena => ena_saturate1_pipeline,
dataout => saturate1_out,
async => async_saturate1_pipeline);
async_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clock = "none") ELSE '0' ;
clear_saturate1_pipeline <= '1' WHEN (saturate1_pipeline_clear /= "none") ELSE '0' ;
clk_saturate1_pipeline <= '1' WHEN clk(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
aclr_saturate1_pipeline <= '1' WHEN (aclr(conv_integer(saturate1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_saturate1_pipeline <= '1' WHEN ena(conv_integer(saturate1_pipeline_clk)) = '1' ELSE '0' ;
saturate1_pipeline_clk <= "0000" WHEN ((saturate1_pipeline_clock = "0") OR (saturate1_pipeline_clock = "none")) ELSE "0001" WHEN (saturate1_pipeline_clock = "1") ELSE "0010" WHEN (saturate1_pipeline_clock = "2") ELSE "0011" WHEN (saturate1_pipeline_clock = "3") ELSE "0000" ;
saturate1_pipeline_aclr <= "0000" WHEN ((saturate1_pipeline_clear = "0") OR (saturate1_pipeline_clear = "none")) ELSE "0001" WHEN (saturate1_pipeline_clear = "1") ELSE "0010" WHEN (saturate1_pipeline_clear = "2") ELSE "0011" WHEN (saturate1_pipeline_clear = "3") ELSE "0000" ;
mode1_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => mode1_pipe,
clk => clk_mode1_pipeline,
aclr => aclr_mode1_pipeline,
if_aclr => clear_mode1_pipeline,
ena => ena_mode1_pipeline,
dataout => mode1_out,
async => async_mode1_pipeline);
async_mode1_pipeline <= '1' WHEN (mode1_pipeline_clock = "none") ELSE '0' ;
clear_mode1_pipeline <= '1' WHEN (mode1_pipeline_clear /= "none") ELSE '0' ;
clk_mode1_pipeline <= '1' WHEN clk(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
aclr_mode1_pipeline <= '1' WHEN (aclr(conv_integer(mode1_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_mode1_pipeline <= '1' WHEN ena(conv_integer(mode1_pipeline_clk)) = '1' ELSE '0' ;
mode1_pipeline_clk <= "0000" WHEN ((mode1_pipeline_clock = "0") OR (mode1_pipeline_clock = "none")) ELSE "0001" WHEN (mode1_pipeline_clock = "1") ELSE "0010" WHEN (mode1_pipeline_clock = "2") ELSE "0011" WHEN (mode1_pipeline_clock = "3") ELSE "0000" ;
mode1_pipeline_aclr <= "0000" WHEN ((mode1_pipeline_clear = "0") OR (mode1_pipeline_clear = "none")) ELSE "0001" WHEN (mode1_pipeline_clear = "1") ELSE "0010" WHEN (mode1_pipeline_clear = "2") ELSE "0011" WHEN (mode1_pipeline_clear = "3") ELSE "0000" ;
multabsaturate_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multabsaturate_pipe,
clk => clk_multabsaturate_pipeline,
aclr => aclr_multabsaturate_pipeline,
if_aclr => clear_multabsaturate_pipeline,
ena => ena_multabsaturate_pipeline,
dataout => multabsaturate_out,
async => async_multabsaturate_pipeline);
async_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multabsaturate_pipeline <= '1' WHEN (multabsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multabsaturate_pipeline <= '1' WHEN clk(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multabsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multabsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multabsaturate_pipeline <= '1' WHEN ena(conv_integer(multabsaturate_pipeline_clk)) = '1' ELSE '0' ;
multabsaturate_pipeline_clk <= "0000" WHEN ((multabsaturate_pipeline_clock = "0") OR (multabsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clock = "3") ELSE "0000" ;
multabsaturate_pipeline_aclr <= "0000" WHEN ((multabsaturate_pipeline_clear = "0") OR (multabsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multabsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multabsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multabsaturate_pipeline_clear = "3") ELSE "0000" ;
multcdsaturate_mac_pipeline_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => multcdsaturate_pipe,
clk => clk_multcdsaturate_pipeline,
aclr => aclr_multcdsaturate_pipeline,
if_aclr => clear_multcdsaturate_pipeline,
ena => ena_multcdsaturate_pipeline,
dataout => multcdsaturate_out,
async => async_multcdsaturate_pipeline);
async_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clock = "none") ELSE '0' ;
clear_multcdsaturate_pipeline <= '1' WHEN (multcdsaturate_pipeline_clear /= "none") ELSE '0' ;
clk_multcdsaturate_pipeline <= '1' WHEN clk(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
aclr_multcdsaturate_pipeline <= '1' WHEN (aclr(conv_integer(multcdsaturate_pipeline_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_multcdsaturate_pipeline <= '1' WHEN ena(conv_integer(multcdsaturate_pipeline_clk)) = '1' ELSE '0' ;
multcdsaturate_pipeline_clk <= "0000" WHEN ((multcdsaturate_pipeline_clock = "0") OR (multcdsaturate_pipeline_clock = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clock = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clock = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clock = "3") ELSE "0000" ;
multcdsaturate_pipeline_aclr <= "0000" WHEN ((multcdsaturate_pipeline_clear = "0") OR (multcdsaturate_pipeline_clear = "none")) ELSE "0001" WHEN (multcdsaturate_pipeline_clear = "1") ELSE "0010" WHEN (multcdsaturate_pipeline_clear = "2") ELSE "0011" WHEN (multcdsaturate_pipeline_clear = "3") ELSE "0000" ;
dataa_f <= (others => '0') WHEN (dataa_forced_to_zero = "yes") ELSE dataa ;
datac_f <= (others => '0') WHEN (datac_forced_to_zero = "yes") ELSE datac ;
mac_adder : stratixii_mac_out_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
dataout_width => dataout_width,
operation_mode => operation_mode)
PORT MAP (
dataa => dataa_f,
datab => datab,
datac => datac_f,
datad => datad,
mode0 => mode0_out,
mode1 => mode1_out,
zeroacc => zeroacc_out,
zeroacc1 => zeroacc1_out,
roundab => round0_out,
roundcd => round1_out,
saturateab => saturate_out,
saturatecd => saturate1_out,
multabsaturate => multabsaturate_out,
multcdsaturate => multcdsaturate_out,
signx => signa_out,
signy => signb_out,
addnsub0 => addnsub0_out,
addnsub1 => addnsub1_out,
feedback => dataout_feedback,
dataout => dataout_map(dataout_width -1 downto 0),
accoverflow => accoverflow_reg);
pin_map_addnsub <= addnsub0_out AND addnsub1_out;
mac_pin_map : stratixii_mac_pin_map
GENERIC MAP (
operation_mode => operation_mode,
data_width => tmp_width,
pinmap => "map")
PORT MAP (
datain => dataout_map,
operation => operation,
addnsub => pin_map_addnsub,
dataout => dataout_to_reg);
output0_reg : stratixii_mac_register
GENERIC MAP (
data_width => dataout_width,
power_up => '0')
PORT MAP (
data => dataout_to_reg(dataout_width -1 DOWNTO 0),
clk => clk_output,
aclr => aclr_output,
if_aclr => clear_output,
ena => ena_output,
dataout => dataout_non_dynamic(dataout_width -1 DOWNTO 0),
async => async_output);
async_output <= '1' WHEN (output_clock = "none") ELSE '0' ;
clear_output <= '1' WHEN (output_clear /= "none") ELSE '0' ;
clk_output <= '1' WHEN clk(conv_integer(output_clk)) = '1' ELSE '0' ;
aclr_output <= '1' WHEN (aclr(conv_integer(output_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output <= '1' WHEN ena(conv_integer(output_clk)) = '1' ELSE '0' ;
output_clk <= "0000" WHEN ((output_clock = "0") OR (output_clock = "none")) ELSE "0001" WHEN (output_clock = "1") ELSE "0010" WHEN (output_clock = "2") ELSE "0011" WHEN (output_clock = "3") ELSE "0000" ;
output_aclr <= "0000" WHEN ((output_clear = "0") OR (output_clear = "none")) ELSE "0001" WHEN (output_clear = "1") ELSE "0010" WHEN (output_clear = "2") ELSE "0011" WHEN (output_clear = "3") ELSE "0000" ;
output1_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(35 DOWNTO 18),
clk => clk_output1,
aclr => aclr_output1,
if_aclr => clear_output1,
ena => ena_output1,
dataout => dataout_dynamic1(17 downto 0),
async => async_output1);
async_output1 <= '1' WHEN (output1_clock = "none") ELSE '0' ;
clear_output1 <= '1' WHEN (output1_clear /= "none") ELSE '0' ;
clk_output1 <= '1' WHEN clk(conv_integer(output1_clk)) = '1' ELSE '0' ;
aclr_output1 <= '1' WHEN (aclr(conv_integer(output1_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output1 <= '1' WHEN ena(conv_integer(output1_clk)) = '1' ELSE '0' ;
output1_clk <= "0000" WHEN ((output1_clock = "0") OR (output1_clock = "none")) ELSE "0001" WHEN (output1_clock = "1") ELSE "0010" WHEN (output1_clock = "2") ELSE "0011" WHEN (output1_clock = "3") ELSE "0000" ;
output1_aclr <= "0000" WHEN ((output1_clear = "0") OR (output1_clear = "none")) ELSE "0001" WHEN (output1_clear = "1") ELSE "0010" WHEN (output1_clear = "2") ELSE "0011" WHEN (output1_clear = "3") ELSE "0000" ;
output2_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(53 DOWNTO 36),
clk => clk_output2,
aclr => aclr_output2,
if_aclr => clear_output2,
ena => ena_output2,
dataout => dataout_dynamic2(17 downto 0),
async => async_output2);
async_output2 <= '1' WHEN (output2_clock = "none") ELSE '0' ;
clear_output2 <= '1' WHEN (output2_clear /= "none") ELSE '0' ;
clk_output2 <= '1' WHEN clk(conv_integer(output2_clk)) = '1' ELSE '0' ;
aclr_output2 <= '1' WHEN (aclr(conv_integer(output2_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output2 <= '1' WHEN ena(conv_integer(output2_clk)) = '1' ELSE '0' ;
output2_clk <= "0000" WHEN ((output2_clock = "0") OR (output2_clock = "none")) ELSE "0001" WHEN (output2_clock = "1") ELSE "0010" WHEN (output2_clock = "2") ELSE "0011" WHEN (output2_clock = "3") ELSE "0000" ;
output2_aclr <= "0000" WHEN ((output2_clear = "0") OR (output2_clear = "none")) ELSE "0001" WHEN (output2_clear = "1") ELSE "0010" WHEN (output2_clear = "2") ELSE "0011" WHEN (output2_clear = "3") ELSE "0000" ;
output3_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(71 DOWNTO 54),
clk => clk_output3,
aclr => aclr_output3,
if_aclr => clear_output3,
ena => ena_output3,
dataout => dataout_dynamic3(17 downto 0),
async => async_output3);
async_output3 <= '1' WHEN (output3_clock = "none") ELSE '0' ;
clear_output3 <= '1' WHEN (output3_clear /= "none") ELSE '0' ;
clk_output3 <= '1' WHEN clk(conv_integer(output3_clk)) = '1' ELSE '0' ;
aclr_output3 <= '1' WHEN (aclr(conv_integer(output3_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output3 <= '1' WHEN ena(conv_integer(output3_clk)) = '1' ELSE '0' ;
output3_clk <= "0000" WHEN ((output3_clock = "0") OR (output3_clock = "none")) ELSE "0001" WHEN (output3_clock = "1") ELSE "0010" WHEN (output3_clock = "2") ELSE "0011" WHEN (output3_clock = "3") ELSE "0000" ;
output3_aclr <= "0000" WHEN ((output3_clear = "0") OR (output3_clear = "none")) ELSE "0001" WHEN (output3_clear = "1") ELSE "0010" WHEN (output3_clear = "2") ELSE "0011" WHEN (output3_clear = "3") ELSE "0000" ;
output4_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(89 DOWNTO 72),
clk => clk_output4,
aclr => aclr_output4,
if_aclr => clear_output4,
ena => ena_output4,
dataout => dataout_dynamic4(17 downto 0),
async => async_output4);
async_output4 <= '1' WHEN (output4_clock = "none") ELSE '0' ;
clear_output4 <= '1' WHEN (output4_clear /= "none") ELSE '0' ;
clk_output4 <= '1' WHEN clk(conv_integer(output4_clk)) = '1' ELSE '0' ;
aclr_output4 <= '1' WHEN (aclr(conv_integer(output4_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output4 <= '1' WHEN ena(conv_integer(output4_clk)) = '1' ELSE '0' ;
output4_clk <= "0000" WHEN ((output4_clock = "0") OR (output4_clock = "none")) ELSE "0001" WHEN (output4_clock = "1") ELSE "0010" WHEN (output4_clock = "2") ELSE "0011" WHEN (output4_clock = "3") ELSE "0000" ;
output4_aclr <= "0000" WHEN ((output4_clear = "0") OR (output4_clear = "none")) ELSE "0001" WHEN (output4_clear = "1") ELSE "0010" WHEN (output4_clear = "2") ELSE "0011" WHEN (output4_clear = "3") ELSE "0000" ;
output5_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(107 DOWNTO 90),
clk => clk_output5,
aclr => aclr_output5,
if_aclr => clear_output5,
ena => ena_output5,
dataout => dataout_dynamic5(17 downto 0),
async => async_output5);
async_output5 <= '1' WHEN (output5_clock = "none") ELSE '0' ;
clear_output5 <= '1' WHEN (output5_clear /= "none") ELSE '0' ;
clk_output5 <= '1' WHEN clk(conv_integer(output5_clk)) = '1' ELSE '0' ;
aclr_output5 <= '1' WHEN (aclr(conv_integer(output5_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output5 <= '1' WHEN ena(conv_integer(output5_clk)) = '1' ELSE '0' ;
output5_clk <= "0000" WHEN ((output5_clock = "0") OR (output5_clock = "none")) ELSE "0001" WHEN (output5_clock = "1") ELSE "0010" WHEN (output5_clock = "2") ELSE "0011" WHEN (output5_clock = "3") ELSE "0000" ;
output5_aclr <= "0000" WHEN ((output5_clear = "0") OR (output5_clear = "none")) ELSE "0001" WHEN (output5_clear = "1") ELSE "0010" WHEN (output5_clear = "2") ELSE "0011" WHEN (output5_clear = "3") ELSE "0000" ;
output6_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(125 DOWNTO 108),
clk => clk_output6,
aclr => aclr_output6,
if_aclr => clear_output6,
ena => ena_output6,
dataout => dataout_dynamic6(17 downto 0),
async => async_output6);
async_output6 <= '1' WHEN (output6_clock = "none") ELSE '0' ;
clear_output6 <= '1' WHEN (output6_clear /= "none") ELSE '0' ;
clk_output6 <= '1' WHEN clk(conv_integer(output6_clk)) = '1' ELSE '0' ;
aclr_output6 <= '1' WHEN (aclr(conv_integer(output6_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output6 <= '1' WHEN ena(conv_integer(output6_clk)) = '1' ELSE '0' ;
output6_clk <= "0000" WHEN ((output6_clock = "0") OR (output6_clock = "none")) ELSE "0001" WHEN (output6_clock = "1") ELSE "0010" WHEN (output6_clock = "2") ELSE "0011" WHEN (output6_clock = "3") ELSE "0000" ;
output6_aclr <= "0000" WHEN ((output6_clear = "0") OR (output6_clear = "none")) ELSE "0001" WHEN (output6_clear = "1") ELSE "0010" WHEN (output6_clear = "2") ELSE "0011" WHEN (output6_clear = "3") ELSE "0000" ;
output7_reg : stratixii_mac_register
GENERIC MAP (
data_width => 18,
power_up => '0')
PORT MAP (
data => dataout_to_reg(tmp_width-1 DOWNTO 126),
clk => clk_output7,
aclr => aclr_output7,
if_aclr => clear_output7,
ena => ena_output7,
dataout => dataout_dynamic7(17 downto 0),
async => async_output7);
async_output7 <= '1' WHEN (output7_clock = "none") ELSE '0' ;
clear_output7 <= '1' WHEN (output7_clear /= "none") ELSE '0' ;
clk_output7 <= '1' WHEN clk(conv_integer(output7_clk)) = '1' ELSE '0' ;
aclr_output7 <= '1' WHEN (aclr(conv_integer(output7_aclr)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
ena_output7 <= '1' WHEN ena(conv_integer(output7_clk)) = '1' ELSE '0' ;
output7_clk <= "0000" WHEN ((output7_clock = "0") OR (output7_clock = "none")) ELSE "0001" WHEN (output7_clock = "1") ELSE "0010" WHEN (output7_clock = "2") ELSE "0011" WHEN (output7_clock = "3") ELSE "0000" ;
output7_aclr <= "0000" WHEN ((output7_clear = "0") OR (output7_clear = "none")) ELSE "0001" WHEN (output7_clear = "1") ELSE "0010" WHEN (output7_clear = "2") ELSE "0011" WHEN (output7_clear = "3") ELSE "0000" ;
tmp_186 <= '1' when (output_clear /= "none") else '0';
tmp_189 <= '1' when (output_clock = "none") else '0';
accoverflow_out_reg : stratixii_mac_bit_register
GENERIC MAP (
power_up => '0')
PORT MAP (
data => accoverflow_reg,
clk => clk_output,
aclr => aclr_output,
if_aclr => tmp_186,
ena => ena_output,
dataout => accoverflow_tmp,
async => tmp_189);
dataout_dynamic(tmp_width-1 DOWNTO 0) <= dataout_dynamic7(17 DOWNTO 0) & dataout_dynamic6(17 DOWNTO 0) & dataout_dynamic5(17 DOWNTO 0) & dataout_dynamic4(17 DOWNTO 0) & dataout_dynamic3(17 DOWNTO 0) & dataout_dynamic2(17 DOWNTO 0) & dataout_dynamic1(17 DOWNTO 0) & dataout_non_dynamic(17 DOWNTO 0) ;
dataout_tmp <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
operation <= "0000" WHEN (operation_mode = "output_only") ELSE "0001" WHEN (operation_mode = "one_level_adder") ELSE "0010" WHEN (operation_mode = "two_level_adder") ELSE "0100" WHEN (operation_mode = "accumulator") ELSE "0111" WHEN (operation_mode = "36_bit_multiply") ELSE "0000" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '0')) AND (zeroacc1_out = '0')) ELSE "1100" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '1')) ELSE "1101" WHEN (((operation_mode = "dynamic") AND (mode0_out = '1')) AND (mode1_out = '0')) ELSE "1110" WHEN (((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '1')) ELSE "0111" WHEN (((((operation_mode = "dynamic") AND (mode0_out = '0')) AND (mode1_out = '0')) AND (zeroacc_out = '1')) AND (zeroacc1_out = '1')) ELSE "0000" ;
dataout_feedback <= dataout_dynamic WHEN (operation_mode = "dynamic") ELSE dataout_non_dynamic ;
accoverflow_tmp2 <= accoverflow_tmp;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixii_lvds_tx_reg : ENTITY is TRUE;
END stratixii_lvds_tx_reg;
ARCHITECTURE vital_stratixii_lvds_tx_reg of stratixii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_stratixii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the StratixII
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE std.textio.all;
ENTITY stratixii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE std.textio.all;
ENTITY stratixii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixii_lvds_transmitter
--
-- Description : Timing simulation model for the StratixII LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) StratixII_lvds_tx_parallel_register and
-- 3) StratixII_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE std.textio.all;
USE work.stratixii_lvds_tx_parallel_register;
USE work.stratixii_lvds_tx_out_block;
USE work.stratixii_lvds_tx_reg;
ENTITY stratixii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixii_lvds_reg;
ARCHITECTURE vital_stratixii_lvds_reg of stratixii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_lvds_rx_fifo_sync_ram;
ENTITY stratixii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_lvds_reg;
ENTITY stratixii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- Bit Slip shift register
-- process (clk0_in, bsliprst_in)
-- begin
-- if (bsliprst_in = '1') then
-- elsif (clk0_in'event and clk0_in = '1' and clk0'last_value = '0') then
-- bitslip_arr(0) <= datain_in;
-- for i in 0 to (bitslip_rollover - 1) loop
-- bitslip_arr(i + 1) <= bitslip_arr(i);
-- end loop;
--
-- if (start_corrupt_bits = '1') then
-- num_corrupt_bits <= num_corrupt_bits + 1;
-- end if;
-- if (num_corrupt_bits+1 = 3) then
-- start_corrupt_bits <= '0';
-- end if;
-- end if;
-- end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_deser
--
-- Description : Timing simulation model for the STRATIXII LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the STRATIXII LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
ENTITY stratixii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : STRATIXII_LVDS_RECEIVER
--
-- Description : Timing simulation model for the STRATIXII LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixii_lvds_rx_fifo
-- 2) stratixii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixii_lvds_rx_parallel_reg
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixii_atom_pack.all;
USE work.stratixii_lvds_rx_bitslip;
USE work.stratixii_lvds_rx_fifo;
USE work.stratixii_lvds_rx_deser;
USE work.stratixii_lvds_rx_parallel_reg;
USE work.stratixii_lvds_reg;
ENTITY stratixii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "stratixii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixii_lvds_receiver IS
COMPONENT stratixii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal first_dpa_lock : std_logic;
signal loadreg_datain : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_int : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal clk0_dly : std_logic;
signal datain_tmp : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
-- INTERNAL PARAMETERS
CONSTANT DPA_CYCLES_TO_LOCK : integer := 2;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpareg1_out WHEN (enable_dpa = "on") ELSE gnd ;
reset_int <= (NOT devpor) OR (NOT devclrn) ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpareset_ipd OR reset_fifo ;
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_dly <= clk0_ipd;
xhdl_12 <= devclrn OR devpor;
-- SUB-MODULE INSTANTIATION
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixii_lvds_reg
PORT MAP ( d => in_reg_data,
clk => clk0_dly,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
datain_reg_tmp <= datain_reg;
dpa_clk <= clk0_ipd when (enable_dpa = "on") else '0' ;
dpa_rst <= dpareset_ipd when (enable_dpa = "on") else '0' ;
process (dpa_clk, dpa_rst)
variable dpa_lock_count : integer := 0;
variable dparst_msg : boolean := false;
variable dpa_is_locked : std_logic := '0';
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
if (enable_dpa = "on") then
ASSERT false report "DPA Phase tracking is not modeled, and once locked, DPA will continue to lock until the next reset is asserted. Please refer to the StratixII device handbook for further details." severity warning;
end if;
initial := false;
end if;
if (dpa_rst = '1') then
dpa_is_locked := '0';
dpa_lock_count := 0;
if (not dparst_msg) then
ASSERT false report "DPA was reset" severity note;
dparst_msg := true;
end if;
elsif (dpa_clk'event and dpa_clk = '1') then
dparst_msg := false;
if (dpa_is_locked = '0') then
dpa_lock_count := dpa_lock_count + 1;
if (dpa_lock_count > DPA_CYCLES_TO_LOCK) then
dpa_is_locked := '1';
ASSERT false report "DPA locked" severity note;
reset_fifo <= '0';
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
-- ?????????? insert delay to mimic DPLL dataout ?????????
-- DPA registers
dpareg0 : stratixii_lvds_reg
PORT MAP ( d => in_reg_data,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
s_fifo : stratixii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => fifo_wclk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= slip_datain_tmp;
s_bitslip_clk <= clk0_dly;
s_bslip : stratixii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
--********* DESERIALISER *********//
loaden <= enable0_ipd;
-- only 1 enable signal used for StratixII
rxload_reg : stratixii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
s_deser : stratixii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
postdpaserialdataout <= dpareg1_out ;
serialdataout <= datain_ipd;
END vital_arm_lvds_receiver;
-------------------------------------------------------------------------------
--
-- Entity Name : StratixII_dll
--
-- Outputs : delayctrlout - current delay chain settings for DQS pin
-- offsetctrlout - current delay offset setting
-- dqsupdate - update enable signal for delay setting latces
-- upndnout - raw output of the phase comparator
--
-- Inputs : clk - reference clock matching in frequency to DQS clock
-- aload - asychronous load signal for delay setting counter
-- when asserted, counter is loaded with initial value
-- offset - offset added/subtracted from delayctrlout
-- upndnin - up/down input port for delay setting counter in
-- use_updndnin mode (user control mode)
-- upndninclkena - clock enable for the delaying setting counter
-- addnsub - dynamically control +/- on offsetctrlout
--
-- Formulae : delay (input_period) = sim_loop_intrinsic_delay +
-- sim_loop_delay_increment * dllcounter;
--
-- Latency : 3 (clk8 cycles) = pc + dc + dr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
USE work.stratixii_pllpack.all;
ENTITY stratixii_dll is
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "stratixii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixii_dll;
ARCHITECTURE vital_armdll of stratixii_dll is
-- tuncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal addnsub_in : std_logic := '0';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal dqsupdate_out : std_logic := '1';
signal upndn_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_offsetctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_offset : integer := 0;
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : integer := 0;
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_int : integer := 0;
signal dr_offset_in : integer := 0;
signal dr_dllcount_in : integer := 0;
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_offset : integer := 0;
signal dr_reg_dllcount : integer := 0;
signal dr_delayctrl_out_tmp : integer := 0;
-- delay chain setting counter
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_offset <= dqs_str2int(static_offset);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "offset_only" ELSE "10" WHEN delayctrlout_mode="normal_offset" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
para_offsetctrlout_mode <= "11" WHEN offsetctrlout_mode = "dynamic_addnsub" ELSE "10" WHEN offsetctrlout_mode = "dynamic_sub" ELSE "01" WHEN offsetctrlout_mode = "dynamic_add" ELSE "00";
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetctrl_out <= dr_offsetctrl_out;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_offset_in <= (64 - alt_conv_integer(offset_in)) WHEN ((offset_in /= "000000") AND ((offsetctrlout_mode = "dynamic_addnsub" AND addnsub_in = '0') or (offsetctrlout_mode = "dynamic_sub"))) ELSE
alt_conv_integer(offset_in);
dr_dllcount_in <= dc_dllcount_out;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in;
-- outputs
dr_delayctrl_out <= dll_unsigned2bin(dr_delayctrl_out_tmp);
dr_offsetctrl_out <= dll_unsigned2bin(dr_reg_offset);
dr_delayctrl_out_tmp <= dr_offset_in WHEN (delayctrlout_mode = "offset_only") ELSE
dr_reg_offset WHEN (delayctrlout_mode = "normal_offset") ELSE
dr_reg_dllcount;
dr_delayctrl_int <= para_static_delay_ctrl WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
dr_offsetctrl_int <= para_static_offset WHEN (offsetctrlout_mode = "static") ELSE
dr_offset_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= 0;
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= 0;
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (offsetctrlout_mode = "dynamic_addnsub") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
end if;
elsif (offsetctrlout_mode = "dynamic_sub") then
if (dr_delayctrl_int > dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int - dr_offset_in;
else
dr_reg_offset <= 0;
end if;
elsif (offsetctrlout_mode = "dynamic_add") then
if (dr_delayctrl_int < 63 - dr_offset_in) then
dr_reg_offset <= dr_delayctrl_int + dr_offset_in;
else
dr_reg_offset <= 63;
end if;
elsif (offsetctrlout_mode = "static") then
if (para_static_offset >= 0) then
if ((para_static_offset < 64) AND (para_static_offset < 64 - dr_delayctrl_int)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 64;
end if;
else
if ((para_static_offset > -63) AND (dr_delayctrl_int > (-1)*para_static_offset)) then
dr_reg_offset <= dr_delayctrl_int + para_static_offset;
else
dr_reg_offset <= 0;
end if;
end if;
else
dr_reg_offset <= 14; -- error
end if; -- modes
end if; -- rising clock
end process ; -- generating dr_reg_offset
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount;
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := sim_loop_intrinsic_delay + sim_loop_delay_increment * pc_dllcount_in;
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
pc_delay <= pc_var_delay;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, upndn_in, upndninclkena_in, addnsub_in,
delayctrl_out, offsetctrl_out, dqsupdate_out, upndn_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/SRRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetctrlout <= offsetctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE),
1 => (offset_in'last_event, tpd_offset_delayctrlout, TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_armdll;
--
--
-- STRATIXII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixii_atom_pack.all;
entity stratixii_rublock is
generic
(
operation_mode : string := "remote";
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_page_select : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic;
pgmout : out std_logic_vector(2 downto 0)
);
end stratixii_rublock;
architecture architecture_rublock of stratixii_rublock is
signal update_reg : std_logic_vector(20 downto 0);
signal status_reg : std_logic_vector(4 downto 0) := conv_std_logic_vector(sim_init_status, 5);
signal shift_reg : std_logic_vector(25 downto 0) := (others => '0');
signal pgmout_update : std_logic_vector(2 downto 0) := (others => '0');
begin
-- regout is output of shift-reg bit 0
-- note that in Stratix, there is an inverter to regout.
-- but in Stratix II, there is no inverter.
regout <= shift_reg(0);
-- pgmout is set when reconfig is asserted
pgmout <= pgmout_update;
process (clk)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- wd_timeout field
update_reg(20 downto 9) <= conv_std_logic_vector(sim_init_watchdog_value, 12);
-- wd enable field
if (sim_init_watchdog_value > 0) then
update_reg(8) <= '1';
else
update_reg(8) <= '0';
end if;
-- PGM[] field
update_reg(7 downto 1) <= conv_std_logic_vector(sim_init_page_select, 7);
-- AnF bit
if (sim_init_config = "factory") then
update_reg(0) <= '0';
else
update_reg(0) <= '1';
end if;
--to-do: print field values
--report "Remote Update Block: Initial configuration:";
--report " -> Field CRC, POF ID, SW ID Error Caused Reconfiguration is set to" & status_reg(0);
--report " -> Field nSTATUS Caused Reconfiguration is set to %s", status_reg[1] ? "True" : "False";
--report " -> Field Core nCONFIG Caused Reconfiguration is set to %s", status_reg[2] ? "True" : "False";
--report " -> Field Pin nCONFIG Caused Reconfiguration is set to %s", status_reg[3] ? "True" : "False";
--report " -> Field Watchdog Timeout Caused Reconfiguration is set to %s", status_reg[4] ? "True" : "False";
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1]);
--report " -> Field User Watchdog is set to %s", update_reg[8] ? "Enabled" : "Disabled";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
else
-- dont handle clk events during initialization since this will
-- destroy the register values that we just initialized
if (clk = '1') then
if (shiftnld = '1') then
-- register shifting
for i in 0 to 24 loop
shift_reg(i) <= shift_reg(i+1);
end loop;
shift_reg(25) <= regin;
elsif (shiftnld = '0') then
-- register loading
if (captnupdt = '1') then
-- capture data into shift register
shift_reg <= update_reg & status_reg;
elsif (captnupdt = '0') then
-- update data from shift into Update Register
if (sim_init_config = "factory" and
(operation_mode = "remote" or operation_mode = "active_serial_remote")) then
-- every bit in Update Reg gets updated
update_reg(20 downto 0) <= shift_reg(25 downto 5);
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Update Register updated at time " & time'image(now);
--report " -> Field PGM[] Page Select is set to %d", shift_reg[12:6];
--report " -> Field User Watchdog is set to %s", (shift_reg[13] == 1) ? "Enableds" : (shift_reg[13] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", shift_reg[25:14];
else
-- trying to do update in Application mode
--VHDL93 only: report "Remote Update Block: Attempted update of Update Register at time " & time'image(now) & " when Configuration is set to Application" severity WARNING;
end if;
else
-- invalid captnupdt
-- destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
else
-- invalid shiftnld: destroys update and shift regs
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
elsif (clk /= '0') then
-- invalid clk: destroys registers
shift_reg <= (others => 'X');
if (sim_init_config = "factory") then
update_reg(20 downto 1) <= (others => 'X');
end if;
end if;
end if;
end process;
process (rconfig)
begin
-- initialize registers/outputs
if ( now = 0 ns ) then
-- pgmout update
if (operation_mode = "local") then
pgmout_update <= "001";
elsif (operation_mode = "remote") then
pgmout_update <= conv_std_logic_vector(sim_init_page_select, 3);
-- PGM[] field
else
pgmout_update <= (others => 'X');
end if;
end if;
if (rconfig = '1') then
-- start reconfiguration
--to-do: print field values
--VHDL93 only: report "Remote Update Block: Reconfiguration initiated at time " & time'image(now);
--report " -> Field Current Configuration is set to %s", update_reg[0] ? "Application" : "Factory";
--report " -> Field PGM[] Page Select is set to %d", update_reg[7:1];
--report " -> Field User Watchdog is set to %s", (update_reg[8] == 1) ? "Enabled" : (update_reg[8] == 0) ? "Disabled" : "x";
--report " -> Field User Watchdog Timeout Value is set to %d", update_reg[20:9];
if (operation_mode = "remote") then
-- set pgm[] to page as set in Update Register
pgmout_update <= update_reg(3 downto 1);
elsif (operation_mode = "local") then
-- set pgm[] to page as 001
pgmout_update <= "001";
else
-- invalid rconfig: destroys pgmout (only if not initializing)
pgmout_update <= (others => 'X');
end if;
elsif (rconfig /= '0') then
-- invalid rconfig: destroys pgmout (only if not initializing)
if (now /= 0 ns) then
pgmout_update <= (others => 'X');
end if;
end if;
end process;
end architecture_rublock;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixii_termination
--
-- Outputs : incrup and incrdn - output of voltage comparator
-- terminationcontrol - to I/O, cannot wired to PLD
-- terminationcontrolprobe - internal testing outputs only
--
-- Descriptions : the Atom represent On Chip Termination calibration block.
-- The block has no digital outputs that can be observed in PLD.
-- Therefore we do not have simulation model other than entity
-- declaration.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_termination is
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "stratixii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END stratixii_termination;
ARCHITECTURE vital_armtermination of stratixii_termination is
begin
--------------------
-- INPUT PATH DELAYS
--------------------
------------------------
-- Timing Check Section
------------------------
----------------------
-- Path Delay Section
----------------------
end vital_armtermination;
---------------------------------------------------------------------
--
-- Entity Name : stratixii_routing_wire
--
-- Description : StratixII Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixii_atom_pack.all;
ENTITY stratixii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixii_routing_wire : entity is TRUE;
end stratixii_routing_wire;
ARCHITECTURE behave of stratixii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
| gpl-3.0 | d0462c2fb5b0d0e9ce316827337f02fa | 0.495567 | 3.884446 | false | false | false | false |
google/myelin-acorn-electron-hardware | cpu_socket_expansion/cpld/cpu_socket_expansion.vhd | 1 | 7,786 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cpu_socket_expansion is
Port (
-- Buffer chips:
-- *buf_ext_to_cpu buffers from pins A->B when 1, B->A when 0.
-- A = pins 2-9, B = pins 18-11.
-- A pins all connect to the external connector, and B pins connect to
-- the CPU socket, so setting *buf_ext_to_cpu=0 means the CPU drives the
-- external port, and setting it to 1 means the external port is driving,
-- and defaulting to 0 is the most sensible.
-- *buf_nCE enables buffers when 0, disables when 1. Defaulting to just
-- disabling all buffers.
abuf_ext_to_cpu : out std_logic := '0';
abuf_nCE : out std_logic := '1';
dbuf_ext_to_cpu : out std_logic := '0';
dbuf_nCE : out std_logic := '1';
-- For shadow RAM support, we buffer A13:A15. When shadow RAM is not being accessed,
-- these should just pass through from the CPU to the motherboard.
cpu_A13_1 : out std_logic; -- connects to motherboard
cpu_A13_2 : in std_logic; -- connects to ABUFH and socketed CPU
cpu_A14_1 : out std_logic; -- connects to motherboard
cpu_A14_2 : in std_logic; -- connects to ABUFH and socketed CPU
cpu_A15_1 : out std_logic; -- connects to motherboard
cpu_A15_2 : in std_logic; -- connects to ABUFH and socketed CPU
-- This may or may not connect to the ULA's 16MHz clock; it requires
-- an extra wire to be added.
clk_16MHz : in std_logic;
-- All the control pins from the CPU socket
cpu_PHI0_IN : in std_logic; -- input from motherboard
cpu_PHI1_OUT : inout std_logic;
cpu_PHI2_OUT : inout std_logic; -- best clock
cpu_RDY : in std_logic;
cpu_RnW : inout std_logic;
cpu_SYNC : in std_logic;
cpu_nIRQ : in std_logic;
cpu_nNMI : in std_logic;
cpu_nRESET : inout std_logic;
cpu_nSO : in std_logic;
-- General purpose pins, for passing clocks etc to the external device.
-- ext_GP1, ext_GP3, and ext_GP4 are pulled up to 3V3, so should be used
-- as active low chip enables for anything (driving the A/D bus, etc) that
-- could have undesirable results during FPGA reprogramming or if the
-- external device gets disconnected.
-- GP0 convention: (is surrounded by ground plane) CPU clock; connected to
-- cpu_PHI2_OUT.
ext_GP0 : out std_logic;
-- GP1 convention: (is surrounded by ground plane, has pullup to 3V3)
-- global chip enable: 1=disable all buffers and shadowing, 0=enable
-- buffer controls. This is used to stop anything bad from happening
-- while the external device is disconnected or tristated.
ext_GP1 : in std_logic;
-- GP2 convention: (is surrounded by ground plane) 16MHz clock; connected
-- to clk_16MHz.
ext_GP2 : out std_logic;
-- GP3 convention: (has pullup to 3V3) /OE for data buffer. When 1, the
-- data buffer is disabled. When 0, it's enabled.
ext_GP3 : in std_logic;
-- GP4 convention: (has pullup to 3V3) '0' when accessing shadow ram, '1' otherwise.
ext_GP4 : in std_logic;
-- GP5 convention: 1=onboard CPU, 0=external CPU. When 1, the address
-- bus, RnW, SYNC, PHI1, and PHI2 are buffered from the CPU socket.
-- When 0, all of these are buffered from the external connector (or
-- PHI1/PHI2 are generated by the CPLD; not sure yet).
ext_GP5 : in std_logic;
-- GP6 convention: RnW (buffered from expansion if CPU is external,
-- from motherboard if CPU is internal)
ext_GP6 : inout std_logic;
-- GP7 convention: nRESET (buffered from motherboard)
ext_GP7 : out std_logic;
-- GP8 convention: RDY
ext_GP8 : in std_logic;
-- GP9 convention: /NMI
ext_GP9 : in std_logic;
-- GP10 convention: /IRQ
ext_GP10 : in std_logic;
-- GP11 convention: data buffer direction: 1=from CPU
-- to connector, 0=from connector to CPU.
ext_GP11 : in std_logic;
-- GP12 convention:
ext_GP12 : in std_logic
);
end cpu_socket_expansion;
architecture Behavioural of cpu_socket_expansion is
-- When '0', this disables all outputs and buffers
signal global_enable : std_logic := '0';
-- When '1', this forces A15:A13 = "110" (&C000-&DFFF address range), which
-- will make the ULA think we're accessing the OS ROM. If the (socketed)
-- ROM is removed, this results in this tristating the data bus, letting the
-- CPU access something without the ULA interfering.
signal accessing_shadow_ram : std_logic := '0';
-- When '1', this means the CPU is on the external connector (i.e. probably
-- a soft-CPU implemented in an FPGA). When '0', there is a 6502 plugged in
-- to the onboard socket.
signal cpu_is_external : std_logic := '0';
-- PHI2, which may be generated by an internal CPU or by us.
signal cpu_clock : std_logic;
begin
---- Critical pins that require pullups
-- external device must pull ext_GP1 low to enable clocks and buffers.
global_enable <= not ext_GP1;
-- CPU is always internal for now
-- When ext_GP5 is pulled low, buffer directions and clock generation changes
-- to support a CPU on the external connector.
cpu_is_external <= '0'; --'1' when global_enable = '1' and ext_GP5 = '0' else '0';
-- Force A15:A13 into OS ROM area when ext_GP4 is pulled low
accessing_shadow_ram <= '1' when global_enable = '1' and ext_GP4 = '0' else '0';
---- Clocks
-- With an internal CPU, we just buffer PHI2. With an external CPU, we
-- generate PHI1 and PHI2.
cpu_clock <= cpu_PHI2_OUT when cpu_is_external = '0' else cpu_PHI0_IN;
cpu_PHI1_OUT <= not cpu_PHI0_IN when global_enable = '1' and cpu_is_external = '1' else 'Z';
cpu_PHI2_OUT <= cpu_clock when global_enable = '1' and cpu_is_external = '1' else 'Z';
-- ext_GP0 outputs the CPU clock to the external device
ext_GP0 <= cpu_clock when global_enable = '1' else 'Z';
-- ext_GP2 outputs 16MHz clock to the external device
ext_GP2 <= clk_16MHz when global_enable = '1' else 'Z';
---- Other buffers
-- enable DBUF when ext_GP3='0'.
dbuf_nCE <= ext_GP3 when global_enable = '1' else '1';
-- ext_GP11='0' when the external device is driving the bus, '1' otherwise
dbuf_ext_to_cpu <= not ext_GP11;
-- ABUF is driven by the CPU (internal or external)
abuf_nCE <= not global_enable;
abuf_ext_to_cpu <= cpu_is_external;
-- RnW is driven by the CPU (internal or external)
-- ext_GP6 buffers cpu_RnW for internal CPUs, vice versa for external.
ext_GP6 <= cpu_RnW when global_enable = '1' and cpu_is_external = '0' else 'Z';
cpu_RnW <= ext_GP6 when global_enable = '1' and cpu_is_external = '1' else 'Z';
-- ext_GP7 buffers /RESET from the motherboard
ext_GP7 <= cpu_nRESET when global_enable = '1' else 'Z';
-- Buffer A15:13 from socketed CPU (or external CPU via ABUFH) to motherboard
cpu_A15_1 <= '1' when accessing_shadow_ram = '1' else cpu_A15_2;
cpu_A14_1 <= '1' when accessing_shadow_ram = '1' else cpu_A14_2;
cpu_A13_1 <= '0' when accessing_shadow_ram = '1' else cpu_A13_2;
end Behavioural;
| apache-2.0 | a93777866f64f1a71d877e80c7904c20 | 0.656306 | 3.443609 | false | false | false | false |
google/myelin-acorn-electron-hardware | serial_sd_adapter/bbc_1mhz_bus_cpld/serial_sd_adapter.vhd | 1 | 15,214 | -- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- This implements a fast serial port with help from an AVR. It also includes
-- some code from spi_sd_card.vhd to support MMFS (bit-banged SD card interface)
-- and UPURS (bit-banged serial)
-- Addresses used:
-- &FCA0 = serial TX/RX (for HostFS)
-- &FCA1 = serial status (for HostFS)
-- &FCA2 = serial2 TX/RX
-- &FCA3 = serial2 status
-- &FC71 = Plus 1 parallel data register (for MMFS)
-- &FC72 = Plus 1 serial data register (for MMFS)
entity serial_sd_adapter is
generic (
-- Use the avr_INT pin
include_avr_int : boolean := false;
-- '1' to include the ROM at &FD00
include_rom : boolean := false;
-- Include SD pins
include_sd : boolean := true;
-- '1' to include the Plus 1 SD card interface
include_bitbang_sd : boolean := true;
-- '1' to include the pass-through SD card interface via the AVR
include_avr_sd : boolean := false;
-- '1' to include the second serial port
include_second_serial : std_logic := '0'
);
Port (
-- Pins that connect to the BBC 1MHz Bus
bbc_A : in std_logic_vector(7 downto 0);
bbc_D : inout std_logic_vector(7 downto 0);
bbc_nPGFC : in std_logic;
bbc_nPGFD : in std_logic;
bbc_1MHZE : in std_logic;
bbc_RnW : in std_logic;
bbc_nIRQ : in std_logic;
bbc_nNMI : in std_logic;
bbc_nRESET : in std_logic;
-- AVR interface: MISO, MOSI, SCK, /SS, INT.
-- The first four are a standard SPI port, with the AVR as
-- controller and CPLD as peripheral. INT is an output from the CPLD
-- that goes high when we have a byte to send to the AVR.
avr_INT : out std_logic;
avr_MISC1 : in std_logic;
avr_MISO : out std_logic;
avr_MOSI : in std_logic;
avr_SCK : in std_logic;
avr_nSD_SEL : in std_logic;
avr_nSS : in std_logic;
-- SD interface: MISO, MOSI, SCK, /SS
-- These are wired to the pins on the micro SD card socket.
sd_MISO : in std_logic;
sd_MOSI : out std_logic;
sd_SCK : out std_logic;
sd_nSS : out std_logic
);
end serial_sd_adapter;
architecture Behavioural of serial_sd_adapter is
-- 1MHz Bus helpers
signal latched_nPGFC : std_logic := '1';
signal latched_nPGFD : std_logic := '1';
---- Fast SPI port (peripheral, for AVR) ----
signal int_avr_MISO : std_logic; -- output to AVR
signal nAVR_SPI_REG_ACCESS : std_logic; -- '0' when A = &FCA0;
signal nAVR_SPI_STATUS_REG_ACCESS : std_logic; -- '0' when A = &FCA1;
signal nAVR_SPI_REG2_ACCESS : std_logic; -- '0' when A = &FCA2;
signal nAVR_SPI_STATUS_REG2_ACCESS : std_logic; -- '0' when A = &FCA3;
-- we use a toggle synchronizer to know if the buffer is full or empty.
-- RECEPTION FROM AVR TO CPLD+ELK:
-- on the avr side, it's safe to receive a byte if avr_RXD_state = elk_RXD_state_sync
-- on the elk side, it's safe to read a byte if elk_RXD_state != avr_RXD_state_sync
-- we just use a single flip flop to synchronize in each case, because there's always
-- a longish settling time.
-- TRANSMISSION FROM ELK+CPLD TO AVR:
-- it's safe to accept a byte from the elk for transmission if elk_TXD_state == avr_TXD_state_sync
-- it's safe to transmit a byte to the avr if avr_TXD_state != elk_TXD_state_sync
-- TODO could maybe save 9 registers here with a single fast clock
signal avr_RXD_state : std_logic := '0'; -- toggles whenever the CPLD receives a byte from the AVR
signal avr_RXD_state_sync : std_logic := '0'; -- avr_RXD_state synchronized to bbc_1MHZE
signal elk_RXD_state : std_logic := '0'; -- toggles when the elk reads a byte
signal elk_RXD_state_sync : std_logic := '0'; -- elk_RXD_state synchronized to avr_SCK
signal avr_RXD2_state : std_logic := '0'; -- toggles whenever the CPLD receives a byte from the AVR
signal avr_RXD2_state_sync : std_logic := '0'; -- avr_RXD_state synchronized to bbc_1MHZE
signal elk_RXD2_state : std_logic := '0'; -- toggles when the elk reads a byte
signal elk_RXD2_state_sync : std_logic := '0'; -- elk_RXD_state synchronized to avr_SCK
signal avr_TXD_state : std_logic := '0'; -- toggles whenever the CPLD sends a byte to the AVR
signal avr_TXD_state_sync : std_logic := '0'; -- avr_TXD_state synchronized to bbc_1MHZE
signal elk_TXD_state : std_logic := '0'; -- toggles when the elk writes a byte
signal elk_TXD_state_sync : std_logic := '0'; -- elk_TXD_state synchronized to avr_SCK
signal avr_RXD : std_logic_vector(7 downto 0); -- byte received from AVR
signal avr_RXD2 : std_logic_vector(7 downto 0); -- byte received from AVR
signal avr_TXD : std_logic_vector(7 downto 0); -- next byte to transmit / being transmitted to AVR
signal avr_TXD_port_sel : std_logic := '0'; -- which port the next byte is for
-- signals used during an SPI transaction
signal avr_spi_SHIFT : std_logic_vector(7 downto 0); -- SPI shift register
signal avr_spi_bit_count : std_logic_vector(3 downto 0); -- SPI bit counter for transfers
signal avr_spi_receiving : std_logic := '0'; -- copy bits into avr_RXD and toggle avr_RXD_state when done
signal avr_spi_port_sel : std_logic := '0'; -- port 0 or 1
signal avr_spi_transmitting : std_logic := '0'; -- toggle avr_TXD_state when done
---- SPI (controller, for SD card) ---
signal bitbang_MOSI : std_logic := '1';
signal bitbang_SCK : std_logic := '1';
signal bitbang_nSS : std_logic := '0';
---- Plus 1 workalike registers ----
-- chip selects
signal nDATA_REG_ACCESS : std_logic; -- '0' when A = &FC71
signal nSTATUS_REG_ACCESS : std_logic; -- '0' when A = &FC72
---- ROM ----
signal ROM_D : std_logic_vector(7 downto 0);
begin
-- Multiplex MISO between SD card and avr SPI module
avr_MISO <= 'Z' when avr_nSS = '1' else
sd_MISO when include_avr_sd and avr_nSD_SEL = '0' else
int_avr_MISO;
-- Multiplex SD card SPI port between AVR and BBC
gen_sd_pins : if include_sd generate
sd_nSS <= avr_nSS when include_avr_sd and avr_nSD_SEL = '0'
else bitbang_nSS when include_bitbang_sd
else 'Z';
sd_MOSI <= avr_MOSI when include_avr_sd and avr_nSD_SEL = '0'
else bitbang_MOSI when include_bitbang_sd
else 'Z';
sd_SCK <= avr_SCK when include_avr_sd and avr_nSD_SEL = '0'
else bitbang_SCK when include_bitbang_sd
else 'Z';
end generate;
---- Fast SPI peripheral for AVR ---
nAVR_SPI_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A0") else '1';
nAVR_SPI_STATUS_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A1") else '1';
nAVR_SPI_REG2_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A2") else '1';
nAVR_SPI_STATUS_REG2_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"A3") else '1';
gen_avr_INT : if include_avr_int generate
avr_INT <= '1' when (elk_TXD_state /= avr_TXD_state_sync) else '0';
end generate;
---- Plus 1 parallel port emulation ----
nDATA_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"71") else '1';
nSTATUS_REG_ACCESS <= '0' when (latched_nPGFC = '0' and bbc_A = x"72") else '1';
---- ROM from rom_fd00.vhd ----
gen_rom : if include_rom generate
rom_fd00 : entity RomFD00
port map (
A => bbc_A,
D => ROM_D
);
end generate;
---- Data bus ----
bbc_D <=
-- AVR SPI data
avr_RXD when (nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '1') else
avr_RXD2 when (include_second_serial = '1' and nAVR_SPI_REG2_ACCESS = '0' and bbc_RnW = '1') else
-- AVR SPI status
"000000" & (elk_TXD_state xnor avr_TXD_state_sync) & (elk_RXD_state xor avr_RXD_state_sync)
when (nAVR_SPI_STATUS_REG_ACCESS = '0' and bbc_RnW = '1') else
"000000" & (elk_TXD_state xnor avr_TXD_state_sync) & (elk_RXD2_state xor avr_RXD2_state_sync)
when (include_second_serial = '1' and nAVR_SPI_STATUS_REG2_ACCESS = '0' and bbc_RnW = '1') else
-- Plus 1 parallel port
sd_MISO & "0000000" when (include_bitbang_sd and nSTATUS_REG_ACCESS = '0' and bbc_RnW = '1') else
-- ROM on &FDxx
ROM_D when include_rom and latched_nPGFD = '0' and bbc_RnW = '1' else
-- default
"ZZZZZZZZ";
-- AVR SPI clock domain
process (avr_nSS, avr_SCK)
begin
-- RISING EDGE of avr_SCK: read avr_MOSI
if avr_nSS = '1' then
-- asynchronous reset (must not happen on an avr_SCK edge)
avr_spi_bit_count <= x"0";
elsif rising_edge(avr_SCK) then
-- increment the count each time
avr_spi_bit_count <= std_logic_vector(unsigned(avr_spi_bit_count) + 1);
-- clock in a bit, depending on avr_spi_bit_count
if avr_spi_bit_count = x"0" then
-- synchronize elk_RXD_state and elk_TXD_state
elk_RXD_state_sync <= elk_RXD_state;
elk_RXD2_state_sync <= elk_RXD2_state;
elk_TXD_state_sync <= elk_TXD_state;
elsif avr_spi_bit_count = x"5" then
avr_spi_port_sel <= avr_MOSI;
elsif avr_spi_bit_count = x"6" then
-- SPI is big-endian, so we want to ignore incoming bits 0-5.
-- bit 6 (1) tells us if the remote wants to send a byte
avr_spi_receiving <= (
avr_MOSI -- '1' if the remote has a byte for us
and (
(
-- byte sent from AVR to serial port 0
(not include_second_serial or not avr_spi_port_sel)
and (avr_RXD_state xnor elk_RXD_state_sync)
) or (
-- byte sent from AVR to serial port 1
include_second_serial and avr_spi_port_sel and
(avr_RXD2_state xnor elk_RXD2_state_sync)
)
) -- '1' if we have room in our buffer
);
elsif avr_spi_bit_count = x"7" then
-- bit 7 (0) tells us if the remote is capable of receiving a byte
avr_spi_transmitting <= (
avr_MOSI -- '1' if the remote has buffer space
and (avr_TXD_state xor elk_TXD_state_sync) -- '1' if we have a byte to transmit
);
-- copy avr_TXD into the shift register if it's safe
if avr_TXD_state /= elk_TXD_state_sync then
avr_spi_SHIFT <= avr_TXD;
end if;
elsif avr_spi_bit_count(3) = '1' then
-- clock in a bit if we have buffer space
avr_spi_SHIFT <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
if avr_spi_bit_count = x"F" then
if avr_spi_receiving = '1' then
avr_RXD_state <= not avr_RXD_state;
if avr_spi_port_sel = '0' then
avr_RXD <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
else
avr_RXD2 <= avr_spi_SHIFT(6 downto 0) & avr_MOSI;
end if;
end if;
if avr_spi_transmitting = '1' then
avr_TXD_state <= not avr_TXD_state;
end if;
end if;
end if;
end if;
-- FALLING EDGE of avr_SCK: write int_avr_MISO
if avr_nSS = '1' then
elsif falling_edge(avr_SCK) then
-- We always update MISO on an avr_SCK falling edge.
if avr_spi_bit_count = x"5" then
-- '0' or '1' depending which port our outgoing byte is for
int_avr_MISO <= avr_TXD_port_sel;
elsif avr_spi_bit_count = x"6" then
-- '1' if we have a byte to send to the AVR
int_avr_MISO <= avr_TXD_state xor elk_TXD_state_sync;
elsif avr_spi_bit_count = x"7" then
-- '1' if we can accept a byte from the AVR
int_avr_MISO <= avr_RXD_state xnor elk_RXD_state_sync;
elsif avr_spi_bit_count(3) = '1' then
int_avr_MISO <= avr_spi_SHIFT(7);
end if;
end if;
end process;
-- Electron clock domain
process (bbc_1MHZE)
begin
-- The 1MHz Bus is glitchy, so we need to latch chip enables
if rising_edge(bbc_1MHZE) then
latched_nPGFC <= bbc_nPGFC;
latched_nPGFD <= bbc_nPGFD;
end if;
if falling_edge(bbc_1MHZE) then
-- AVR SPI registers
avr_RXD_state_sync <= avr_RXD_state;
avr_TXD_state_sync <= avr_TXD_state;
if nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '0' and elk_TXD_state = avr_TXD_state_sync then
-- we're writing to the TXD register (first serial port)
avr_TXD <= bbc_D;
avr_TXD_port_sel <= '0';
elk_TXD_state <= not elk_TXD_state;
end if;
if include_second_serial = '1' and nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '0' and elk_TXD_state = avr_TXD_state_sync then
-- we're writing to the TXD register (second serial port)
avr_TXD <= bbc_D;
avr_TXD_port_sel <= '1';
elk_TXD_state <= not elk_TXD_state;
end if;
if nAVR_SPI_REG_ACCESS = '0' and bbc_RnW = '1' and elk_RXD_state /= avr_RXD_state_sync then
-- the electron just read avr_RXD
elk_RXD_state <= not elk_RXD_state;
end if;
if include_second_serial = '1' and nAVR_SPI_REG2_ACCESS = '0' and bbc_RnW = '1' and elk_RXD2_state /= avr_RXD2_state_sync then
-- the electron just read avr_RXD
elk_RXD2_state <= not elk_RXD2_state;
end if;
if nAVR_SPI_STATUS_REG_ACCESS = '0' and bbc_RnW = '0' then
-- we never write to the status register
end if;
-- Bit-banged SPI
if include_bitbang_sd and nDATA_REG_ACCESS = '0' and bbc_RnW = '0' then
-- handle write to &FC71
bitbang_MOSI <= bbc_D(0);
bitbang_SCK <= bbc_D(1);
end if;
end if;
end process;
end Behavioural;
| apache-2.0 | 8175bf0616a555c4755c29471c0faf21 | 0.568029 | 3.470347 | false | false | false | false |
alvieboy/xtc-base | internalram.vhd | 1 | 79,373 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity internalram is
port (
CLK: in std_logic;
EN: in std_logic;
ADDR: in std_logic_vector(12 downto 2);
DO: out std_logic_vector(31 downto 0)
);
end entity internalram;
architecture behave of internalram is
begin
process(CLK)
variable iaddr: natural;
begin
if rising_edge(CLK) then
if EN='1' then
iaddr := to_integer(unsigned(ADDR));
case iaddr is
when 0 => DO <= x"80007020";
when 1 => DO <= x"70427331";
when 2 => DO <= x"10121860";
when 3 => DO <= x"1000f001";
when 4 => DO <= x"4010a5a5";
when 5 => DO <= x"704b7a52";
when 6 => DO <= x"10211830";
when 7 => DO <= x"0723c1c0";
when 8 => DO <= x"42003800";
when 9 => DO <= x"80006080";
when 10 => DO <= x"6001c060";
when 11 => DO <= x"42003800";
when 12 => DO <= x"4e600011";
when 13 => DO <= x"cfad4000";
when 14 => DO <= x"74514fe0";
when 15 => DO <= x"38001060";
when 16 => DO <= x"0c1a801f";
when 17 => DO <= x"40fc3c11";
when 18 => DO <= x"38008511";
when 19 => DO <= x"40023e11";
when 20 => DO <= x"3800c16d";
when 21 => DO <= x"40013800";
when 22 => DO <= x"70112401";
when 23 => DO <= x"38003800";
when 24 => DO <= x"38003800";
when 25 => DO <= x"80096080";
when 26 => DO <= x"7f31c9cd";
when 27 => DO <= x"40003800";
when 28 => DO <= x"46ed0ca1";
when 29 => DO <= x"800a6080";
when 30 => DO <= x"7331c8cd";
when 31 => DO <= x"40003800";
when 32 => DO <= x"8aa14002";
when 33 => DO <= x"7002cc2d";
when 34 => DO <= x"40033800";
when 35 => DO <= x"4fe03800";
when 36 => DO <= x"0cdc0c1b";
when 37 => DO <= x"80096080";
when 38 => DO <= x"7d8146ed";
when 39 => DO <= x"38000c41";
when 40 => DO <= x"43ed3800";
when 41 => DO <= x"80096080";
when 42 => DO <= x"7f1145ed";
when 43 => DO <= x"38000c41";
when 44 => DO <= x"42ed3800";
when 45 => DO <= x"42603800";
when 46 => DO <= x"0c1b0c27";
when 47 => DO <= x"80096080";
when 48 => DO <= x"7d81446d";
when 49 => DO <= x"38000c71";
when 50 => DO <= x"416d3800";
when 51 => DO <= x"80096080";
when 52 => DO <= x"7f11436d";
when 53 => DO <= x"38000c51";
when 54 => DO <= x"406d3800";
when 55 => DO <= x"4fe03800";
when 56 => DO <= x"0cd50c14";
when 57 => DO <= x"70778941";
when 58 => DO <= x"401c8844";
when 59 => DO <= x"40048411";
when 60 => DO <= x"400f5301";
when 61 => DO <= x"6391d081";
when 62 => DO <= x"4700436d";
when 63 => DO <= x"38006007";
when 64 => DO <= x"ce2041ff";
when 65 => DO <= x"5ff73050";
when 66 => DO <= x"38000c18";
when 67 => DO <= x"1a186001";
when 68 => DO <= x"c0e04200";
when 69 => DO <= x"50180cd6";
when 70 => DO <= x"418d3800";
when 71 => DO <= x"0c6d4ec0";
when 72 => DO <= x"380030d0";
when 73 => DO <= x"38000000";
when 74 => DO <= x"00000000";
when 75 => DO <= x"00000000";
when 76 => DO <= x"00008000";
when 77 => DO <= x"70207002";
when 78 => DO <= x"98324004";
when 79 => DO <= x"84334002";
when 80 => DO <= x"6003cf20";
when 81 => DO <= x"41ff3800";
when 82 => DO <= x"101230d0";
when 83 => DO <= x"38007021";
when 84 => DO <= x"24013800";
when 85 => DO <= x"38003800";
when 86 => DO <= x"20013800";
when 87 => DO <= x"84124002";
when 88 => DO <= x"6002cf20";
when 89 => DO <= x"41ff3800";
when 90 => DO <= x"30d03800";
when 91 => DO <= x"70112401";
when 92 => DO <= x"38003800";
when 93 => DO <= x"38003800";
when 94 => DO <= x"30d03800";
when 95 => DO <= x"30103800";
when 96 => DO <= x"00000000";
when 97 => DO <= x"00000000";
when 98 => DO <= x"00008004";
when 99 => DO <= x"608074cd";
when 100 => DO <= x"30d07001";
when 101 => DO <= x"4fe03800";
when 102 => DO <= x"4fe03800";
when 103 => DO <= x"3e5f3800";
when 104 => DO <= x"ffff6000";
when 105 => DO <= x"7fcf180f";
when 106 => DO <= x"101f902f";
when 107 => DO <= x"40fc903f";
when 108 => DO <= x"40f8904f";
when 109 => DO <= x"40f4905f";
when 110 => DO <= x"40f0906f";
when 111 => DO <= x"40ec907f";
when 112 => DO <= x"40e8908f";
when 113 => DO <= x"40e4909f";
when 114 => DO <= x"40e090af";
when 115 => DO <= x"40dc90bf";
when 116 => DO <= x"40d890cf";
when 117 => DO <= x"40d490df";
when 118 => DO <= x"40d090ef";
when 119 => DO <= x"40cc3c51";
when 120 => DO <= x"3800901f";
when 121 => DO <= x"40c83c21";
when 122 => DO <= x"3800901f";
when 123 => DO <= x"40c43c41";
when 124 => DO <= x"3800901f";
when 125 => DO <= x"40c080f1";
when 126 => DO <= x"40c05bcf";
when 127 => DO <= x"cdcd4002";
when 128 => DO <= x"3800544f";
when 129 => DO <= x"981f40c0";
when 130 => DO <= x"3e413800";
when 131 => DO <= x"981f40c4";
when 132 => DO <= x"3e213800";
when 133 => DO <= x"981f40c8";
when 134 => DO <= x"3e513800";
when 135 => DO <= x"98ef40cc";
when 136 => DO <= x"98df40d0";
when 137 => DO <= x"98cf40d4";
when 138 => DO <= x"98bf40d8";
when 139 => DO <= x"98af40dc";
when 140 => DO <= x"989f40e0";
when 141 => DO <= x"988f40e4";
when 142 => DO <= x"987f40e8";
when 143 => DO <= x"986f40ec";
when 144 => DO <= x"985f40f0";
when 145 => DO <= x"984f40f4";
when 146 => DO <= x"983f40f8";
when 147 => DO <= x"982f40fc";
when 148 => DO <= x"181f3c5f";
when 149 => DO <= x"38003400";
when 150 => DO <= x"38000c01";
when 151 => DO <= x"0c020c03";
when 152 => DO <= x"0c040c05";
when 153 => DO <= x"0c060c07";
when 154 => DO <= x"0c080c09";
when 155 => DO <= x"0c0a0c0b";
when 156 => DO <= x"30d00c0c";
when 157 => DO <= x"3c113800";
when 158 => DO <= x"30d03800";
when 159 => DO <= x"30d03800";
when 160 => DO <= x"20813800";
when 161 => DO <= x"30d03800";
when 162 => DO <= x"20513800";
when 163 => DO <= x"30d03800";
when 164 => DO <= x"24813800";
when 165 => DO <= x"30d03800";
when 166 => DO <= x"24513800";
when 167 => DO <= x"30d03800";
when 168 => DO <= x"20913800";
when 169 => DO <= x"30d03800";
when 170 => DO <= x"20a13800";
when 171 => DO <= x"30d03800";
when 172 => DO <= x"20b13800";
when 173 => DO <= x"30d03800";
when 174 => DO <= x"20c13800";
when 175 => DO <= x"30d03800";
when 176 => DO <= x"20d13800";
when 177 => DO <= x"30d03800";
when 178 => DO <= x"20e13800";
when 179 => DO <= x"30d03800";
when 180 => DO <= x"24e13800";
when 181 => DO <= x"30d03800";
when 182 => DO <= x"20f13800";
when 183 => DO <= x"30d03800";
when 184 => DO <= x"24613800";
when 185 => DO <= x"30d02071";
when 186 => DO <= x"380030d0";
when 187 => DO <= x"38002061";
when 188 => DO <= x"380030d0";
when 189 => DO <= x"38000000";
when 190 => DO <= x"5f0f10df";
when 191 => DO <= x"905f400c";
when 192 => DO <= x"0c157011";
when 193 => DO <= x"906f4008";
when 194 => DO <= x"907f4004";
when 195 => DO <= x"90154008";
when 196 => DO <= x"70b19005";
when 197 => DO <= x"40089015";
when 198 => DO <= x"40049815";
when 199 => DO <= x"40049700";
when 200 => DO <= x"60007001";
when 201 => DO <= x"90154024";
when 202 => DO <= x"98154024";
when 203 => DO <= x"90054004";
when 204 => DO <= x"98154004";
when 205 => DO <= x"90054034";
when 206 => DO <= x"98654034";
when 207 => DO <= x"90054014";
when 208 => DO <= x"800a6080";
when 209 => DO <= x"75819875";
when 210 => DO <= x"4014c22d";
when 211 => DO <= x"40043800";
when 212 => DO <= x"0c61c52d";
when 213 => DO <= x"40043800";
when 214 => DO <= x"800a6080";
when 215 => DO <= x"7691c0ed";
when 216 => DO <= x"40043800";
when 217 => DO <= x"80ff6000";
when 218 => DO <= x"7ff10471";
when 219 => DO <= x"c9cd4005";
when 220 => DO <= x"3800800a";
when 221 => DO <= x"60807c81";
when 222 => DO <= x"cf4d4003";
when 223 => DO <= x"38009005";
when 224 => DO <= x"4034800a";
when 225 => DO <= x"60807721";
when 226 => DO <= x"98754034";
when 227 => DO <= x"ce0d4003";
when 228 => DO <= x"38000c71";
when 229 => DO <= x"c10d4004";
when 230 => DO <= x"38008afa";
when 231 => DO <= x"60626d57";
when 232 => DO <= x"c0804200";
when 233 => DO <= x"3800c900";
when 234 => DO <= x"40003800";
when 235 => DO <= x"90054034";
when 236 => DO <= x"800a6080";
when 237 => DO <= x"78d19875";
when 238 => DO <= x"4034cb2d";
when 239 => DO <= x"40033800";
when 240 => DO <= x"0c71ce2d";
when 241 => DO <= x"40033800";
when 242 => DO <= x"800a6080";
when 243 => DO <= x"7a01c9ed";
when 244 => DO <= x"40033800";
when 245 => DO <= x"c76d40fd";
when 246 => DO <= x"38006006";
when 247 => DO <= x"c1a04200";
when 248 => DO <= x"38007001";
when 249 => DO <= x"90054034";
when 250 => DO <= x"5ff69825";
when 251 => DO <= x"40341021";
when 252 => DO <= x"50416006";
when 253 => DO <= x"cec041ff";
when 254 => DO <= x"3800800a";
when 255 => DO <= x"60807ab1";
when 256 => DO <= x"c6cd4003";
when 257 => DO <= x"3800c44d";
when 258 => DO <= x"40fd3800";
when 259 => DO <= x"c5cd40fd";
when 260 => DO <= x"3800800a";
when 261 => DO <= x"60807b31";
when 262 => DO <= x"c54d4003";
when 263 => DO <= x"38007001";
when 264 => DO <= x"c58d40fd";
when 265 => DO <= x"3800987f";
when 266 => DO <= x"4004986f";
when 267 => DO <= x"4008985f";
when 268 => DO <= x"400c18df";
when 269 => DO <= x"510f30d0";
when 270 => DO <= x"3800800a";
when 271 => DO <= x"60807801";
when 272 => DO <= x"c2cd4003";
when 273 => DO <= x"38004fe0";
when 274 => DO <= x"38000000";
when 275 => DO <= x"5f8f800a";
when 276 => DO <= x"60807cb1";
when 277 => DO <= x"10df905f";
when 278 => DO <= x"4004c12d";
when 279 => DO <= x"40033800";
when 280 => DO <= x"ff114000";
when 281 => DO <= x"8000703e";
when 282 => DO <= x"70028000";
when 283 => DO <= x"70409010";
when 284 => DO <= x"40007011";
when 285 => DO <= x"80007040";
when 286 => DO <= x"90004008";
when 287 => DO <= x"80007040";
when 288 => DO <= x"90104008";
when 289 => DO <= x"80007040";
when 290 => DO <= x"90004008";
when 291 => DO <= x"80007040";
when 292 => DO <= x"90204034";
when 293 => DO <= x"80007040";
when 294 => DO <= x"98504034";
when 295 => DO <= x"80007040";
when 296 => DO <= x"90104008";
when 297 => DO <= x"800a6080";
when 298 => DO <= x"7e51cc2d";
when 299 => DO <= x"40023800";
when 300 => DO <= x"ffff6001";
when 301 => DO <= x"7ff10451";
when 302 => DO <= x"cecd4002";
when 303 => DO <= x"3800800a";
when 304 => DO <= x"60807c81";
when 305 => DO <= x"ca8d4002";
when 306 => DO <= x"38008000";
when 307 => DO <= x"70407001";
when 308 => DO <= x"c24d40fe";
when 309 => DO <= x"38004fe0";
when 310 => DO <= x"38000000";
when 311 => DO <= x"5f8f10df";
when 312 => DO <= x"905f4004";
when 313 => DO <= x"0c15800b";
when 314 => DO <= x"60807021";
when 315 => DO <= x"c80d4002";
when 316 => DO <= x"38001815";
when 317 => DO <= x"cb0d4002";
when 318 => DO <= x"3800800a";
when 319 => DO <= x"60807c81";
when 320 => DO <= x"c6cd4002";
when 321 => DO <= x"3800800b";
when 322 => DO <= x"60807231";
when 323 => DO <= x"c60d4002";
when 324 => DO <= x"38009815";
when 325 => DO <= x"4004c8ed";
when 326 => DO <= x"40023800";
when 327 => DO <= x"800b6080";
when 328 => DO <= x"72e1c4ad";
when 329 => DO <= x"40023800";
when 330 => DO <= x"800a6080";
when 331 => DO <= x"7c81c3ed";
when 332 => DO <= x"40023800";
when 333 => DO <= x"800b6080";
when 334 => DO <= x"72a1c32d";
when 335 => DO <= x"40023800";
when 336 => DO <= x"98154040";
when 337 => DO <= x"c60d4002";
when 338 => DO <= x"3800800b";
when 339 => DO <= x"608072e1";
when 340 => DO <= x"c1cd4002";
when 341 => DO <= x"3800800b";
when 342 => DO <= x"60807301";
when 343 => DO <= x"c10d4002";
when 344 => DO <= x"38009815";
when 345 => DO <= x"403cc3ed";
when 346 => DO <= x"40023800";
when 347 => DO <= x"800b6080";
when 348 => DO <= x"72e1cfad";
when 349 => DO <= x"40013800";
when 350 => DO <= x"800b6080";
when 351 => DO <= x"7361ceed";
when 352 => DO <= x"40013800";
when 353 => DO <= x"98154038";
when 354 => DO <= x"c1cd4002";
when 355 => DO <= x"3800800b";
when 356 => DO <= x"608072e1";
when 357 => DO <= x"cd8d4001";
when 358 => DO <= x"3800800b";
when 359 => DO <= x"608073c1";
when 360 => DO <= x"cccd4001";
when 361 => DO <= x"38009815";
when 362 => DO <= x"4034cfad";
when 363 => DO <= x"40013800";
when 364 => DO <= x"800b6080";
when 365 => DO <= x"72e1cb6d";
when 366 => DO <= x"40013800";
when 367 => DO <= x"800a6080";
when 368 => DO <= x"7c81caad";
when 369 => DO <= x"40013800";
when 370 => DO <= x"800b6080";
when 371 => DO <= x"7421c9ed";
when 372 => DO <= x"40013800";
when 373 => DO <= x"98154030";
when 374 => DO <= x"cccd4001";
when 375 => DO <= x"3800800b";
when 376 => DO <= x"608072e1";
when 377 => DO <= x"c88d4001";
when 378 => DO <= x"3800800b";
when 379 => DO <= x"60807481";
when 380 => DO <= x"c7cd4001";
when 381 => DO <= x"38009815";
when 382 => DO <= x"402ccaad";
when 383 => DO <= x"40013800";
when 384 => DO <= x"800b6080";
when 385 => DO <= x"72e1c66d";
when 386 => DO <= x"40013800";
when 387 => DO <= x"800b6080";
when 388 => DO <= x"74e1c5ad";
when 389 => DO <= x"40013800";
when 390 => DO <= x"98154028";
when 391 => DO <= x"c88d4001";
when 392 => DO <= x"3800800b";
when 393 => DO <= x"608072e1";
when 394 => DO <= x"c44d4001";
when 395 => DO <= x"3800800b";
when 396 => DO <= x"60807541";
when 397 => DO <= x"c38d4001";
when 398 => DO <= x"38009815";
when 399 => DO <= x"4024c66d";
when 400 => DO <= x"40013800";
when 401 => DO <= x"800b6080";
when 402 => DO <= x"72e1c22d";
when 403 => DO <= x"40013800";
when 404 => DO <= x"800a6080";
when 405 => DO <= x"7c81c16d";
when 406 => DO <= x"40013800";
when 407 => DO <= x"800b6080";
when 408 => DO <= x"75a1c0ad";
when 409 => DO <= x"40013800";
when 410 => DO <= x"98154020";
when 411 => DO <= x"c38d4001";
when 412 => DO <= x"3800800b";
when 413 => DO <= x"608072e1";
when 414 => DO <= x"cf4d4000";
when 415 => DO <= x"3800800b";
when 416 => DO <= x"60807601";
when 417 => DO <= x"ce8d4000";
when 418 => DO <= x"38009815";
when 419 => DO <= x"401cc16d";
when 420 => DO <= x"40013800";
when 421 => DO <= x"800b6080";
when 422 => DO <= x"72e1cd2d";
when 423 => DO <= x"40003800";
when 424 => DO <= x"800b6080";
when 425 => DO <= x"7661cc6d";
when 426 => DO <= x"40003800";
when 427 => DO <= x"98154018";
when 428 => DO <= x"cf4d4000";
when 429 => DO <= x"3800800b";
when 430 => DO <= x"608072e1";
when 431 => DO <= x"cb0d4000";
when 432 => DO <= x"3800800b";
when 433 => DO <= x"608076c1";
when 434 => DO <= x"ca4d4000";
when 435 => DO <= x"38009815";
when 436 => DO <= x"4014cd2d";
when 437 => DO <= x"40003800";
when 438 => DO <= x"800b6080";
when 439 => DO <= x"72e1c8ed";
when 440 => DO <= x"40003800";
when 441 => DO <= x"800a6080";
when 442 => DO <= x"7c81c82d";
when 443 => DO <= x"40003800";
when 444 => DO <= x"800b6080";
when 445 => DO <= x"7721478d";
when 446 => DO <= x"38009815";
when 447 => DO <= x"4010ca6d";
when 448 => DO <= x"40003800";
when 449 => DO <= x"800b6080";
when 450 => DO <= x"72e1464d";
when 451 => DO <= x"3800800b";
when 452 => DO <= x"60807781";
when 453 => DO <= x"45ad3800";
when 454 => DO <= x"9815400c";
when 455 => DO <= x"c88d4000";
when 456 => DO <= x"3800800b";
when 457 => DO <= x"608072e1";
when 458 => DO <= x"446d3800";
when 459 => DO <= x"800b6080";
when 460 => DO <= x"77e143cd";
when 461 => DO <= x"38009815";
when 462 => DO <= x"400846cd";
when 463 => DO <= x"3800800b";
when 464 => DO <= x"608072e1";
when 465 => DO <= x"42ad3800";
when 466 => DO <= x"800a6080";
when 467 => DO <= x"7c81420d";
when 468 => DO <= x"3800c1ed";
when 469 => DO <= x"40fb3800";
when 470 => DO <= x"ff024000";
when 471 => DO <= x"04216201";
when 472 => DO <= x"c0804100";
when 473 => DO <= x"38001815";
when 474 => DO <= x"50211015";
when 475 => DO <= x"4fe03800";
when 476 => DO <= x"5f8f10df";
when 477 => DO <= x"905f4004";
when 478 => DO <= x"0c151a15";
when 479 => DO <= x"6001c180";
when 480 => DO <= x"42003800";
when 481 => DO <= x"3811ca8d";
when 482 => DO <= x"40f93800";
when 483 => DO <= x"9a154001";
when 484 => DO <= x"50156001";
when 485 => DO <= x"cec041ff";
when 486 => DO <= x"3800985f";
when 487 => DO <= x"400418df";
when 488 => DO <= x"508f30d0";
when 489 => DO <= x"38000000";
when 490 => DO <= x"5f0f10df";
when 491 => DO <= x"905f400c";
when 492 => DO <= x"0c15906f";
when 493 => DO <= x"40087306";
when 494 => DO <= x"907f4004";
when 495 => DO <= x"ffff703f";
when 496 => DO <= x"6ff58951";
when 497 => DO <= x"401cc060";
when 498 => DO <= x"4a003800";
when 499 => DO <= x"40803800";
when 500 => DO <= x"05614040";
when 501 => DO <= x"38005371";
when 502 => DO <= x"c56d40f9";
when 503 => DO <= x"38008951";
when 504 => DO <= x"401870f7";
when 505 => DO <= x"88524004";
when 506 => DO <= x"ffff703f";
when 507 => DO <= x"6ff20471";
when 508 => DO <= x"c0604a00";
when 509 => DO <= x"38004080";
when 510 => DO <= x"38000561";
when 511 => DO <= x"40403800";
when 512 => DO <= x"5371c2cd";
when 513 => DO <= x"40f93800";
when 514 => DO <= x"89514014";
when 515 => DO <= x"88524008";
when 516 => DO <= x"ffff703f";
when 517 => DO <= x"6ff20471";
when 518 => DO <= x"c0604a00";
when 519 => DO <= x"38004080";
when 520 => DO <= x"38000561";
when 521 => DO <= x"40403800";
when 522 => DO <= x"5371c04d";
when 523 => DO <= x"40f93800";
when 524 => DO <= x"89514010";
when 525 => DO <= x"8852400c";
when 526 => DO <= x"ffff703f";
when 527 => DO <= x"6ff20471";
when 528 => DO <= x"c0604a00";
when 529 => DO <= x"38004080";
when 530 => DO <= x"38000561";
when 531 => DO <= x"40403800";
when 532 => DO <= x"5371cdcd";
when 533 => DO <= x"40f83800";
when 534 => DO <= x"8951400c";
when 535 => DO <= x"88524010";
when 536 => DO <= x"ffff703f";
when 537 => DO <= x"6ff20471";
when 538 => DO <= x"c0604a00";
when 539 => DO <= x"38004080";
when 540 => DO <= x"38000561";
when 541 => DO <= x"40403800";
when 542 => DO <= x"5371cb4d";
when 543 => DO <= x"40f83800";
when 544 => DO <= x"89514008";
when 545 => DO <= x"88524014";
when 546 => DO <= x"ffff703f";
when 547 => DO <= x"6ff20471";
when 548 => DO <= x"c0604a00";
when 549 => DO <= x"38004080";
when 550 => DO <= x"38000561";
when 551 => DO <= x"40403800";
when 552 => DO <= x"5371c8cd";
when 553 => DO <= x"40f83800";
when 554 => DO <= x"89514004";
when 555 => DO <= x"88524018";
when 556 => DO <= x"ffff703f";
when 557 => DO <= x"6ff20471";
when 558 => DO <= x"c0604a00";
when 559 => DO <= x"38004080";
when 560 => DO <= x"38000561";
when 561 => DO <= x"40403800";
when 562 => DO <= x"5371c64d";
when 563 => DO <= x"40f83800";
when 564 => DO <= x"84752001";
when 565 => DO <= x"8852401c";
when 566 => DO <= x"ffff703f";
when 567 => DO <= x"6ff2c060";
when 568 => DO <= x"4a003800";
when 569 => DO <= x"40803800";
when 570 => DO <= x"05614040";
when 571 => DO <= x"38005371";
when 572 => DO <= x"c3ed40f8";
when 573 => DO <= x"3800987f";
when 574 => DO <= x"4004986f";
when 575 => DO <= x"4008985f";
when 576 => DO <= x"400c18df";
when 577 => DO <= x"510f30d0";
when 578 => DO <= x"38000000";
when 579 => DO <= x"5f4f10df";
when 580 => DO <= x"905f4008";
when 581 => DO <= x"0c15906f";
when 582 => DO <= x"40047306";
when 583 => DO <= x"809f6000";
when 584 => DO <= x"6ff58951";
when 585 => DO <= x"400cc060";
when 586 => DO <= x"4a003800";
when 587 => DO <= x"40803800";
when 588 => DO <= x"05614040";
when 589 => DO <= x"38005371";
when 590 => DO <= x"cf6d40f7";
when 591 => DO <= x"38008851";
when 592 => DO <= x"400480ff";
when 593 => DO <= x"60007f02";
when 594 => DO <= x"0412809f";
when 595 => DO <= x"60006ff2";
when 596 => DO <= x"8921400c";
when 597 => DO <= x"c0604a00";
when 598 => DO <= x"38004080";
when 599 => DO <= x"38000561";
when 600 => DO <= x"40403800";
when 601 => DO <= x"5371cc8d";
when 602 => DO <= x"40f73800";
when 603 => DO <= x"88514008";
when 604 => DO <= x"80ff6000";
when 605 => DO <= x"70020412";
when 606 => DO <= x"809f6000";
when 607 => DO <= x"6ff28921";
when 608 => DO <= x"400cc060";
when 609 => DO <= x"4a003800";
when 610 => DO <= x"40803800";
when 611 => DO <= x"05614040";
when 612 => DO <= x"38005371";
when 613 => DO <= x"c9ad40f7";
when 614 => DO <= x"38008851";
when 615 => DO <= x"400c80f0";
when 616 => DO <= x"60007002";
when 617 => DO <= x"0412809f";
when 618 => DO <= x"60006ff2";
when 619 => DO <= x"8921400c";
when 620 => DO <= x"c0604a00";
when 621 => DO <= x"38004080";
when 622 => DO <= x"38000561";
when 623 => DO <= x"40403800";
when 624 => DO <= x"5371c6cd";
when 625 => DO <= x"40f73800";
when 626 => DO <= x"986f4004";
when 627 => DO <= x"985f4008";
when 628 => DO <= x"18df50cf";
when 629 => DO <= x"30d03800";
when 630 => DO <= x"4d656d6f";
when 631 => DO <= x"72792065";
when 632 => DO <= x"72726f72";
when 633 => DO <= x"20617420";
when 634 => DO <= x"61646472";
when 635 => DO <= x"65737320";
when 636 => DO <= x"00200058";
when 637 => DO <= x"5468756e";
when 638 => DO <= x"64657243";
when 639 => DO <= x"6f726520";
when 640 => DO <= x"426f6f74";
when 641 => DO <= x"204c6f61";
when 642 => DO <= x"64657220";
when 643 => DO <= x"76302e31";
when 644 => DO <= x"20284329";
when 645 => DO <= x"20323031";
when 646 => DO <= x"3420416c";
when 647 => DO <= x"7661726f";
when 648 => DO <= x"204c6f70";
when 649 => DO <= x"65730d0a";
when 650 => DO <= x"54657374";
when 651 => DO <= x"696e6720";
when 652 => DO <= x"30780020";
when 653 => DO <= x"62797465";
when 654 => DO <= x"73206f66";
when 655 => DO <= x"206d656d";
when 656 => DO <= x"6f72793a";
when 657 => DO <= x"20004661";
when 658 => DO <= x"696c6564";
when 659 => DO <= x"0d0a0070";
when 660 => DO <= x"61737365";
when 661 => DO <= x"640d0a00";
when 662 => DO <= x"50726f67";
when 663 => DO <= x"72616d20";
when 664 => DO <= x"73697a65";
when 665 => DO <= x"3a203078";
when 666 => DO <= x"002c2043";
when 667 => DO <= x"52432030";
when 668 => DO <= x"78005369";
when 669 => DO <= x"676e6174";
when 670 => DO <= x"7572653a";
when 671 => DO <= x"20307800";
when 672 => DO <= x"202d2049";
when 673 => DO <= x"4e56414c";
when 674 => DO <= x"49440d0a";
when 675 => DO <= x"000d0a54";
when 676 => DO <= x"61726765";
when 677 => DO <= x"7420626f";
when 678 => DO <= x"6172643a";
when 679 => DO <= x"20307800";
when 680 => DO <= x"0d0a4c6f";
when 681 => DO <= x"6164696e";
when 682 => DO <= x"673a0020";
when 683 => DO <= x"646f6e65";
when 684 => DO <= x"0d0a0053";
when 685 => DO <= x"74617274";
when 686 => DO <= x"696e6720";
when 687 => DO <= x"6170706c";
when 688 => DO <= x"69636174";
when 689 => DO <= x"696f6e2e";
when 690 => DO <= x"0d0a0043";
when 691 => DO <= x"6f6e6e65";
when 692 => DO <= x"6374696e";
when 693 => DO <= x"6720746f";
when 694 => DO <= x"20535049";
when 695 => DO <= x"20666c61";
when 696 => DO <= x"73680d0a";
when 697 => DO <= x"00535049";
when 698 => DO <= x"20466c61";
when 699 => DO <= x"73682049";
when 700 => DO <= x"64656e74";
when 701 => DO <= x"69666963";
when 702 => DO <= x"6174696f";
when 703 => DO <= x"6e3a2030";
when 704 => DO <= x"78000d0a";
when 705 => DO <= x"45786365";
when 706 => DO <= x"7074696f";
when 707 => DO <= x"6e206361";
when 708 => DO <= x"75676874";
when 709 => DO <= x"20617420";
when 710 => DO <= x"61646472";
when 711 => DO <= x"65737320";
when 712 => DO <= x"30780053";
when 713 => DO <= x"5053523a";
when 714 => DO <= x"20005231";
when 715 => DO <= x"203a2000";
when 716 => DO <= x"5232203a";
when 717 => DO <= x"20005233";
when 718 => DO <= x"203a2000";
when 719 => DO <= x"5234203a";
when 720 => DO <= x"20005235";
when 721 => DO <= x"203a2000";
when 722 => DO <= x"5236203a";
when 723 => DO <= x"20005237";
when 724 => DO <= x"203a2000";
when 725 => DO <= x"5238203a";
when 726 => DO <= x"20005239";
when 727 => DO <= x"203a2000";
when 728 => DO <= x"5231303a";
when 729 => DO <= x"20005231";
when 730 => DO <= x"313a2000";
when 731 => DO <= x"5231323a";
when 732 => DO <= x"20005231";
when 733 => DO <= x"333a2000";
when 734 => DO <= x"5231343a";
when 735 => DO <= x"20005231";
when 736 => DO <= x"353a2000";
when 737 => DO <= x"00000000";
when 738 => DO <= x"00000000";
when 739 => DO <= x"00000000";
when 740 => DO <= x"00000000";
when 741 => DO <= x"00000000";
when 742 => DO <= x"00000000";
when 743 => DO <= x"00000000";
when 744 => DO <= x"00000000";
when 745 => DO <= x"00000000";
when 746 => DO <= x"00000000";
when 747 => DO <= x"00000000";
when 748 => DO <= x"00000000";
when 749 => DO <= x"00000000";
when 750 => DO <= x"00000000";
when 751 => DO <= x"00000000";
when 752 => DO <= x"00000000";
when 753 => DO <= x"00000000";
when 754 => DO <= x"00000000";
when 755 => DO <= x"00000000";
when 756 => DO <= x"00000000";
when 757 => DO <= x"00000000";
when 758 => DO <= x"00000000";
when 759 => DO <= x"00000000";
when 760 => DO <= x"00000000";
when 761 => DO <= x"00000000";
when 762 => DO <= x"00000000";
when 763 => DO <= x"00000000";
when 764 => DO <= x"00000000";
when 765 => DO <= x"00000000";
when 766 => DO <= x"00000000";
when 767 => DO <= x"00000000";
when 768 => DO <= x"00000000";
when 769 => DO <= x"00000000";
when 770 => DO <= x"00000000";
when 771 => DO <= x"00000000";
when 772 => DO <= x"00000000";
when 773 => DO <= x"00000000";
when 774 => DO <= x"00000000";
when 775 => DO <= x"00000000";
when 776 => DO <= x"00000000";
when 777 => DO <= x"00000000";
when 778 => DO <= x"00000000";
when 779 => DO <= x"00000000";
when 780 => DO <= x"00000000";
when 781 => DO <= x"00000000";
when 782 => DO <= x"00000000";
when 783 => DO <= x"00000000";
when 784 => DO <= x"00000000";
when 785 => DO <= x"00000000";
when 786 => DO <= x"00000000";
when 787 => DO <= x"00000000";
when 788 => DO <= x"00000000";
when 789 => DO <= x"00000000";
when 790 => DO <= x"00000000";
when 791 => DO <= x"00000000";
when 792 => DO <= x"00000000";
when 793 => DO <= x"00000000";
when 794 => DO <= x"00000000";
when 795 => DO <= x"00000000";
when 796 => DO <= x"00000000";
when 797 => DO <= x"00000000";
when 798 => DO <= x"00000000";
when 799 => DO <= x"00000000";
when 800 => DO <= x"00000000";
when 801 => DO <= x"00000000";
when 802 => DO <= x"00000000";
when 803 => DO <= x"00000000";
when 804 => DO <= x"00000000";
when 805 => DO <= x"00000000";
when 806 => DO <= x"00000000";
when 807 => DO <= x"00000000";
when 808 => DO <= x"00000000";
when 809 => DO <= x"00000000";
when 810 => DO <= x"00000000";
when 811 => DO <= x"00000000";
when 812 => DO <= x"00000000";
when 813 => DO <= x"00000000";
when 814 => DO <= x"00000000";
when 815 => DO <= x"00000000";
when 816 => DO <= x"00000000";
when 817 => DO <= x"00000000";
when 818 => DO <= x"00000000";
when 819 => DO <= x"00000000";
when 820 => DO <= x"00000000";
when 821 => DO <= x"00000000";
when 822 => DO <= x"00000000";
when 823 => DO <= x"00000000";
when 824 => DO <= x"00000000";
when 825 => DO <= x"00000000";
when 826 => DO <= x"00000000";
when 827 => DO <= x"00000000";
when 828 => DO <= x"00000000";
when 829 => DO <= x"00000000";
when 830 => DO <= x"00000000";
when 831 => DO <= x"00000000";
when 832 => DO <= x"00000000";
when 833 => DO <= x"00000000";
when 834 => DO <= x"00000000";
when 835 => DO <= x"00000000";
when 836 => DO <= x"00000000";
when 837 => DO <= x"00000000";
when 838 => DO <= x"00000000";
when 839 => DO <= x"00000000";
when 840 => DO <= x"00000000";
when 841 => DO <= x"00000000";
when 842 => DO <= x"00000000";
when 843 => DO <= x"00000000";
when 844 => DO <= x"00000000";
when 845 => DO <= x"00000000";
when 846 => DO <= x"00000000";
when 847 => DO <= x"00000000";
when 848 => DO <= x"00000000";
when 849 => DO <= x"00000000";
when 850 => DO <= x"00000000";
when 851 => DO <= x"00000000";
when 852 => DO <= x"00000000";
when 853 => DO <= x"00000000";
when 854 => DO <= x"00000000";
when 855 => DO <= x"00000000";
when 856 => DO <= x"00000000";
when 857 => DO <= x"00000000";
when 858 => DO <= x"00000000";
when 859 => DO <= x"00000000";
when 860 => DO <= x"00000000";
when 861 => DO <= x"00000000";
when 862 => DO <= x"00000000";
when 863 => DO <= x"00000000";
when 864 => DO <= x"00000000";
when 865 => DO <= x"00000000";
when 866 => DO <= x"00000000";
when 867 => DO <= x"00000000";
when 868 => DO <= x"00000000";
when 869 => DO <= x"00000000";
when 870 => DO <= x"00000000";
when 871 => DO <= x"00000000";
when 872 => DO <= x"00000000";
when 873 => DO <= x"00000000";
when 874 => DO <= x"00000000";
when 875 => DO <= x"00000000";
when 876 => DO <= x"00000000";
when 877 => DO <= x"00000000";
when 878 => DO <= x"00000000";
when 879 => DO <= x"00000000";
when 880 => DO <= x"00000000";
when 881 => DO <= x"00000000";
when 882 => DO <= x"00000000";
when 883 => DO <= x"00000000";
when 884 => DO <= x"00000000";
when 885 => DO <= x"00000000";
when 886 => DO <= x"00000000";
when 887 => DO <= x"00000000";
when 888 => DO <= x"00000000";
when 889 => DO <= x"00000000";
when 890 => DO <= x"00000000";
when 891 => DO <= x"00000000";
when 892 => DO <= x"00000000";
when 893 => DO <= x"00000000";
when 894 => DO <= x"00000000";
when 895 => DO <= x"00000000";
when 896 => DO <= x"00000000";
when 897 => DO <= x"00000000";
when 898 => DO <= x"00000000";
when 899 => DO <= x"00000000";
when 900 => DO <= x"00000000";
when 901 => DO <= x"00000000";
when 902 => DO <= x"00000000";
when 903 => DO <= x"00000000";
when 904 => DO <= x"00000000";
when 905 => DO <= x"00000000";
when 906 => DO <= x"00000000";
when 907 => DO <= x"00000000";
when 908 => DO <= x"00000000";
when 909 => DO <= x"00000000";
when 910 => DO <= x"00000000";
when 911 => DO <= x"00000000";
when 912 => DO <= x"00000000";
when 913 => DO <= x"00000000";
when 914 => DO <= x"00000000";
when 915 => DO <= x"00000000";
when 916 => DO <= x"00000000";
when 917 => DO <= x"00000000";
when 918 => DO <= x"00000000";
when 919 => DO <= x"00000000";
when 920 => DO <= x"00000000";
when 921 => DO <= x"00000000";
when 922 => DO <= x"00000000";
when 923 => DO <= x"00000000";
when 924 => DO <= x"00000000";
when 925 => DO <= x"00000000";
when 926 => DO <= x"00000000";
when 927 => DO <= x"00000000";
when 928 => DO <= x"00000000";
when 929 => DO <= x"00000000";
when 930 => DO <= x"00000000";
when 931 => DO <= x"00000000";
when 932 => DO <= x"00000000";
when 933 => DO <= x"00000000";
when 934 => DO <= x"00000000";
when 935 => DO <= x"00000000";
when 936 => DO <= x"00000000";
when 937 => DO <= x"00000000";
when 938 => DO <= x"00000000";
when 939 => DO <= x"00000000";
when 940 => DO <= x"00000000";
when 941 => DO <= x"00000000";
when 942 => DO <= x"00000000";
when 943 => DO <= x"00000000";
when 944 => DO <= x"00000000";
when 945 => DO <= x"00000000";
when 946 => DO <= x"00000000";
when 947 => DO <= x"00000000";
when 948 => DO <= x"00000000";
when 949 => DO <= x"00000000";
when 950 => DO <= x"00000000";
when 951 => DO <= x"00000000";
when 952 => DO <= x"00000000";
when 953 => DO <= x"00000000";
when 954 => DO <= x"00000000";
when 955 => DO <= x"00000000";
when 956 => DO <= x"00000000";
when 957 => DO <= x"00000000";
when 958 => DO <= x"00000000";
when 959 => DO <= x"00000000";
when 960 => DO <= x"00000000";
when 961 => DO <= x"00000000";
when 962 => DO <= x"00000000";
when 963 => DO <= x"00000000";
when 964 => DO <= x"00000000";
when 965 => DO <= x"00000000";
when 966 => DO <= x"00000000";
when 967 => DO <= x"00000000";
when 968 => DO <= x"00000000";
when 969 => DO <= x"00000000";
when 970 => DO <= x"00000000";
when 971 => DO <= x"00000000";
when 972 => DO <= x"00000000";
when 973 => DO <= x"00000000";
when 974 => DO <= x"00000000";
when 975 => DO <= x"00000000";
when 976 => DO <= x"00000000";
when 977 => DO <= x"00000000";
when 978 => DO <= x"00000000";
when 979 => DO <= x"00000000";
when 980 => DO <= x"00000000";
when 981 => DO <= x"00000000";
when 982 => DO <= x"00000000";
when 983 => DO <= x"00000000";
when 984 => DO <= x"00000000";
when 985 => DO <= x"00000000";
when 986 => DO <= x"00000000";
when 987 => DO <= x"00000000";
when 988 => DO <= x"00000000";
when 989 => DO <= x"00000000";
when 990 => DO <= x"00000000";
when 991 => DO <= x"00000000";
when 992 => DO <= x"00000000";
when 993 => DO <= x"00000000";
when 994 => DO <= x"00000000";
when 995 => DO <= x"00000000";
when 996 => DO <= x"00000000";
when 997 => DO <= x"00000000";
when 998 => DO <= x"00000000";
when 999 => DO <= x"00000000";
when 1000 => DO <= x"00000000";
when 1001 => DO <= x"00000000";
when 1002 => DO <= x"00000000";
when 1003 => DO <= x"00000000";
when 1004 => DO <= x"00000000";
when 1005 => DO <= x"00000000";
when 1006 => DO <= x"00000000";
when 1007 => DO <= x"00000000";
when 1008 => DO <= x"00000000";
when 1009 => DO <= x"00000000";
when 1010 => DO <= x"00000000";
when 1011 => DO <= x"00000000";
when 1012 => DO <= x"00000000";
when 1013 => DO <= x"00000000";
when 1014 => DO <= x"00000000";
when 1015 => DO <= x"00000000";
when 1016 => DO <= x"00000000";
when 1017 => DO <= x"00000000";
when 1018 => DO <= x"00000000";
when 1019 => DO <= x"00000000";
when 1020 => DO <= x"00000000";
when 1021 => DO <= x"00000000";
when 1022 => DO <= x"00000000";
when 1023 => DO <= x"00000000";
when 1024 => DO <= x"00000000";
when 1025 => DO <= x"00000000";
when 1026 => DO <= x"00000000";
when 1027 => DO <= x"00000000";
when 1028 => DO <= x"00000000";
when 1029 => DO <= x"00000000";
when 1030 => DO <= x"00000000";
when 1031 => DO <= x"00000000";
when 1032 => DO <= x"00000000";
when 1033 => DO <= x"00000000";
when 1034 => DO <= x"00000000";
when 1035 => DO <= x"00000000";
when 1036 => DO <= x"00000000";
when 1037 => DO <= x"00000000";
when 1038 => DO <= x"00000000";
when 1039 => DO <= x"00000000";
when 1040 => DO <= x"00000000";
when 1041 => DO <= x"00000000";
when 1042 => DO <= x"00000000";
when 1043 => DO <= x"00000000";
when 1044 => DO <= x"00000000";
when 1045 => DO <= x"00000000";
when 1046 => DO <= x"00000000";
when 1047 => DO <= x"00000000";
when 1048 => DO <= x"00000000";
when 1049 => DO <= x"00000000";
when 1050 => DO <= x"00000000";
when 1051 => DO <= x"00000000";
when 1052 => DO <= x"00000000";
when 1053 => DO <= x"00000000";
when 1054 => DO <= x"00000000";
when 1055 => DO <= x"00000000";
when 1056 => DO <= x"00000000";
when 1057 => DO <= x"00000000";
when 1058 => DO <= x"00000000";
when 1059 => DO <= x"00000000";
when 1060 => DO <= x"00000000";
when 1061 => DO <= x"00000000";
when 1062 => DO <= x"00000000";
when 1063 => DO <= x"00000000";
when 1064 => DO <= x"00000000";
when 1065 => DO <= x"00000000";
when 1066 => DO <= x"00000000";
when 1067 => DO <= x"00000000";
when 1068 => DO <= x"00000000";
when 1069 => DO <= x"00000000";
when 1070 => DO <= x"00000000";
when 1071 => DO <= x"00000000";
when 1072 => DO <= x"00000000";
when 1073 => DO <= x"00000000";
when 1074 => DO <= x"00000000";
when 1075 => DO <= x"00000000";
when 1076 => DO <= x"00000000";
when 1077 => DO <= x"00000000";
when 1078 => DO <= x"00000000";
when 1079 => DO <= x"00000000";
when 1080 => DO <= x"00000000";
when 1081 => DO <= x"00000000";
when 1082 => DO <= x"00000000";
when 1083 => DO <= x"00000000";
when 1084 => DO <= x"00000000";
when 1085 => DO <= x"00000000";
when 1086 => DO <= x"00000000";
when 1087 => DO <= x"00000000";
when 1088 => DO <= x"00000000";
when 1089 => DO <= x"00000000";
when 1090 => DO <= x"00000000";
when 1091 => DO <= x"00000000";
when 1092 => DO <= x"00000000";
when 1093 => DO <= x"00000000";
when 1094 => DO <= x"00000000";
when 1095 => DO <= x"00000000";
when 1096 => DO <= x"00000000";
when 1097 => DO <= x"00000000";
when 1098 => DO <= x"00000000";
when 1099 => DO <= x"00000000";
when 1100 => DO <= x"00000000";
when 1101 => DO <= x"00000000";
when 1102 => DO <= x"00000000";
when 1103 => DO <= x"00000000";
when 1104 => DO <= x"00000000";
when 1105 => DO <= x"00000000";
when 1106 => DO <= x"00000000";
when 1107 => DO <= x"00000000";
when 1108 => DO <= x"00000000";
when 1109 => DO <= x"00000000";
when 1110 => DO <= x"00000000";
when 1111 => DO <= x"00000000";
when 1112 => DO <= x"00000000";
when 1113 => DO <= x"00000000";
when 1114 => DO <= x"00000000";
when 1115 => DO <= x"00000000";
when 1116 => DO <= x"00000000";
when 1117 => DO <= x"00000000";
when 1118 => DO <= x"00000000";
when 1119 => DO <= x"00000000";
when 1120 => DO <= x"00000000";
when 1121 => DO <= x"00000000";
when 1122 => DO <= x"00000000";
when 1123 => DO <= x"00000000";
when 1124 => DO <= x"00000000";
when 1125 => DO <= x"00000000";
when 1126 => DO <= x"00000000";
when 1127 => DO <= x"00000000";
when 1128 => DO <= x"00000000";
when 1129 => DO <= x"00000000";
when 1130 => DO <= x"00000000";
when 1131 => DO <= x"00000000";
when 1132 => DO <= x"00000000";
when 1133 => DO <= x"00000000";
when 1134 => DO <= x"00000000";
when 1135 => DO <= x"00000000";
when 1136 => DO <= x"00000000";
when 1137 => DO <= x"00000000";
when 1138 => DO <= x"00000000";
when 1139 => DO <= x"00000000";
when 1140 => DO <= x"00000000";
when 1141 => DO <= x"00000000";
when 1142 => DO <= x"00000000";
when 1143 => DO <= x"00000000";
when 1144 => DO <= x"00000000";
when 1145 => DO <= x"00000000";
when 1146 => DO <= x"00000000";
when 1147 => DO <= x"00000000";
when 1148 => DO <= x"00000000";
when 1149 => DO <= x"00000000";
when 1150 => DO <= x"00000000";
when 1151 => DO <= x"00000000";
when 1152 => DO <= x"00000000";
when 1153 => DO <= x"00000000";
when 1154 => DO <= x"00000000";
when 1155 => DO <= x"00000000";
when 1156 => DO <= x"00000000";
when 1157 => DO <= x"00000000";
when 1158 => DO <= x"00000000";
when 1159 => DO <= x"00000000";
when 1160 => DO <= x"00000000";
when 1161 => DO <= x"00000000";
when 1162 => DO <= x"00000000";
when 1163 => DO <= x"00000000";
when 1164 => DO <= x"00000000";
when 1165 => DO <= x"00000000";
when 1166 => DO <= x"00000000";
when 1167 => DO <= x"00000000";
when 1168 => DO <= x"00000000";
when 1169 => DO <= x"00000000";
when 1170 => DO <= x"00000000";
when 1171 => DO <= x"00000000";
when 1172 => DO <= x"00000000";
when 1173 => DO <= x"00000000";
when 1174 => DO <= x"00000000";
when 1175 => DO <= x"00000000";
when 1176 => DO <= x"00000000";
when 1177 => DO <= x"00000000";
when 1178 => DO <= x"00000000";
when 1179 => DO <= x"00000000";
when 1180 => DO <= x"00000000";
when 1181 => DO <= x"00000000";
when 1182 => DO <= x"00000000";
when 1183 => DO <= x"00000000";
when 1184 => DO <= x"00000000";
when 1185 => DO <= x"00000000";
when 1186 => DO <= x"00000000";
when 1187 => DO <= x"00000000";
when 1188 => DO <= x"00000000";
when 1189 => DO <= x"00000000";
when 1190 => DO <= x"00000000";
when 1191 => DO <= x"00000000";
when 1192 => DO <= x"00000000";
when 1193 => DO <= x"00000000";
when 1194 => DO <= x"00000000";
when 1195 => DO <= x"00000000";
when 1196 => DO <= x"00000000";
when 1197 => DO <= x"00000000";
when 1198 => DO <= x"00000000";
when 1199 => DO <= x"00000000";
when 1200 => DO <= x"00000000";
when 1201 => DO <= x"00000000";
when 1202 => DO <= x"00000000";
when 1203 => DO <= x"00000000";
when 1204 => DO <= x"00000000";
when 1205 => DO <= x"00000000";
when 1206 => DO <= x"00000000";
when 1207 => DO <= x"00000000";
when 1208 => DO <= x"00000000";
when 1209 => DO <= x"00000000";
when 1210 => DO <= x"00000000";
when 1211 => DO <= x"00000000";
when 1212 => DO <= x"00000000";
when 1213 => DO <= x"00000000";
when 1214 => DO <= x"00000000";
when 1215 => DO <= x"00000000";
when 1216 => DO <= x"00000000";
when 1217 => DO <= x"00000000";
when 1218 => DO <= x"00000000";
when 1219 => DO <= x"00000000";
when 1220 => DO <= x"00000000";
when 1221 => DO <= x"00000000";
when 1222 => DO <= x"00000000";
when 1223 => DO <= x"00000000";
when 1224 => DO <= x"00000000";
when 1225 => DO <= x"00000000";
when 1226 => DO <= x"00000000";
when 1227 => DO <= x"00000000";
when 1228 => DO <= x"00000000";
when 1229 => DO <= x"00000000";
when 1230 => DO <= x"00000000";
when 1231 => DO <= x"00000000";
when 1232 => DO <= x"00000000";
when 1233 => DO <= x"00000000";
when 1234 => DO <= x"00000000";
when 1235 => DO <= x"00000000";
when 1236 => DO <= x"00000000";
when 1237 => DO <= x"00000000";
when 1238 => DO <= x"00000000";
when 1239 => DO <= x"00000000";
when 1240 => DO <= x"00000000";
when 1241 => DO <= x"00000000";
when 1242 => DO <= x"00000000";
when 1243 => DO <= x"00000000";
when 1244 => DO <= x"00000000";
when 1245 => DO <= x"00000000";
when 1246 => DO <= x"00000000";
when 1247 => DO <= x"00000000";
when 1248 => DO <= x"00000000";
when 1249 => DO <= x"00000000";
when 1250 => DO <= x"00000000";
when 1251 => DO <= x"00000000";
when 1252 => DO <= x"00000000";
when 1253 => DO <= x"00000000";
when 1254 => DO <= x"00000000";
when 1255 => DO <= x"00000000";
when 1256 => DO <= x"00000000";
when 1257 => DO <= x"00000000";
when 1258 => DO <= x"00000000";
when 1259 => DO <= x"00000000";
when 1260 => DO <= x"00000000";
when 1261 => DO <= x"00000000";
when 1262 => DO <= x"00000000";
when 1263 => DO <= x"00000000";
when 1264 => DO <= x"00000000";
when 1265 => DO <= x"00000000";
when 1266 => DO <= x"00000000";
when 1267 => DO <= x"00000000";
when 1268 => DO <= x"00000000";
when 1269 => DO <= x"00000000";
when 1270 => DO <= x"00000000";
when 1271 => DO <= x"00000000";
when 1272 => DO <= x"00000000";
when 1273 => DO <= x"00000000";
when 1274 => DO <= x"00000000";
when 1275 => DO <= x"00000000";
when 1276 => DO <= x"00000000";
when 1277 => DO <= x"00000000";
when 1278 => DO <= x"00000000";
when 1279 => DO <= x"00000000";
when 1280 => DO <= x"00000000";
when 1281 => DO <= x"00000000";
when 1282 => DO <= x"00000000";
when 1283 => DO <= x"00000000";
when 1284 => DO <= x"00000000";
when 1285 => DO <= x"00000000";
when 1286 => DO <= x"00000000";
when 1287 => DO <= x"00000000";
when 1288 => DO <= x"00000000";
when 1289 => DO <= x"00000000";
when 1290 => DO <= x"00000000";
when 1291 => DO <= x"00000000";
when 1292 => DO <= x"00000000";
when 1293 => DO <= x"00000000";
when 1294 => DO <= x"00000000";
when 1295 => DO <= x"00000000";
when 1296 => DO <= x"00000000";
when 1297 => DO <= x"00000000";
when 1298 => DO <= x"00000000";
when 1299 => DO <= x"00000000";
when 1300 => DO <= x"00000000";
when 1301 => DO <= x"00000000";
when 1302 => DO <= x"00000000";
when 1303 => DO <= x"00000000";
when 1304 => DO <= x"00000000";
when 1305 => DO <= x"00000000";
when 1306 => DO <= x"00000000";
when 1307 => DO <= x"00000000";
when 1308 => DO <= x"00000000";
when 1309 => DO <= x"00000000";
when 1310 => DO <= x"00000000";
when 1311 => DO <= x"00000000";
when 1312 => DO <= x"00000000";
when 1313 => DO <= x"00000000";
when 1314 => DO <= x"00000000";
when 1315 => DO <= x"00000000";
when 1316 => DO <= x"00000000";
when 1317 => DO <= x"00000000";
when 1318 => DO <= x"00000000";
when 1319 => DO <= x"00000000";
when 1320 => DO <= x"00000000";
when 1321 => DO <= x"00000000";
when 1322 => DO <= x"00000000";
when 1323 => DO <= x"00000000";
when 1324 => DO <= x"00000000";
when 1325 => DO <= x"00000000";
when 1326 => DO <= x"00000000";
when 1327 => DO <= x"00000000";
when 1328 => DO <= x"00000000";
when 1329 => DO <= x"00000000";
when 1330 => DO <= x"00000000";
when 1331 => DO <= x"00000000";
when 1332 => DO <= x"00000000";
when 1333 => DO <= x"00000000";
when 1334 => DO <= x"00000000";
when 1335 => DO <= x"00000000";
when 1336 => DO <= x"00000000";
when 1337 => DO <= x"00000000";
when 1338 => DO <= x"00000000";
when 1339 => DO <= x"00000000";
when 1340 => DO <= x"00000000";
when 1341 => DO <= x"00000000";
when 1342 => DO <= x"00000000";
when 1343 => DO <= x"00000000";
when 1344 => DO <= x"00000000";
when 1345 => DO <= x"00000000";
when 1346 => DO <= x"00000000";
when 1347 => DO <= x"00000000";
when 1348 => DO <= x"00000000";
when 1349 => DO <= x"00000000";
when 1350 => DO <= x"00000000";
when 1351 => DO <= x"00000000";
when 1352 => DO <= x"00000000";
when 1353 => DO <= x"00000000";
when 1354 => DO <= x"00000000";
when 1355 => DO <= x"00000000";
when 1356 => DO <= x"00000000";
when 1357 => DO <= x"00000000";
when 1358 => DO <= x"00000000";
when 1359 => DO <= x"00000000";
when 1360 => DO <= x"00000000";
when 1361 => DO <= x"00000000";
when 1362 => DO <= x"00000000";
when 1363 => DO <= x"00000000";
when 1364 => DO <= x"00000000";
when 1365 => DO <= x"00000000";
when 1366 => DO <= x"00000000";
when 1367 => DO <= x"00000000";
when 1368 => DO <= x"00000000";
when 1369 => DO <= x"00000000";
when 1370 => DO <= x"00000000";
when 1371 => DO <= x"00000000";
when 1372 => DO <= x"00000000";
when 1373 => DO <= x"00000000";
when 1374 => DO <= x"00000000";
when 1375 => DO <= x"00000000";
when 1376 => DO <= x"00000000";
when 1377 => DO <= x"00000000";
when 1378 => DO <= x"00000000";
when 1379 => DO <= x"00000000";
when 1380 => DO <= x"00000000";
when 1381 => DO <= x"00000000";
when 1382 => DO <= x"00000000";
when 1383 => DO <= x"00000000";
when 1384 => DO <= x"00000000";
when 1385 => DO <= x"00000000";
when 1386 => DO <= x"00000000";
when 1387 => DO <= x"00000000";
when 1388 => DO <= x"00000000";
when 1389 => DO <= x"00000000";
when 1390 => DO <= x"00000000";
when 1391 => DO <= x"00000000";
when 1392 => DO <= x"00000000";
when 1393 => DO <= x"00000000";
when 1394 => DO <= x"00000000";
when 1395 => DO <= x"00000000";
when 1396 => DO <= x"00000000";
when 1397 => DO <= x"00000000";
when 1398 => DO <= x"00000000";
when 1399 => DO <= x"00000000";
when 1400 => DO <= x"00000000";
when 1401 => DO <= x"00000000";
when 1402 => DO <= x"00000000";
when 1403 => DO <= x"00000000";
when 1404 => DO <= x"00000000";
when 1405 => DO <= x"00000000";
when 1406 => DO <= x"00000000";
when 1407 => DO <= x"00000000";
when 1408 => DO <= x"00000000";
when 1409 => DO <= x"00000000";
when 1410 => DO <= x"00000000";
when 1411 => DO <= x"00000000";
when 1412 => DO <= x"00000000";
when 1413 => DO <= x"00000000";
when 1414 => DO <= x"00000000";
when 1415 => DO <= x"00000000";
when 1416 => DO <= x"00000000";
when 1417 => DO <= x"00000000";
when 1418 => DO <= x"00000000";
when 1419 => DO <= x"00000000";
when 1420 => DO <= x"00000000";
when 1421 => DO <= x"00000000";
when 1422 => DO <= x"00000000";
when 1423 => DO <= x"00000000";
when 1424 => DO <= x"00000000";
when 1425 => DO <= x"00000000";
when 1426 => DO <= x"00000000";
when 1427 => DO <= x"00000000";
when 1428 => DO <= x"00000000";
when 1429 => DO <= x"00000000";
when 1430 => DO <= x"00000000";
when 1431 => DO <= x"00000000";
when 1432 => DO <= x"00000000";
when 1433 => DO <= x"00000000";
when 1434 => DO <= x"00000000";
when 1435 => DO <= x"00000000";
when 1436 => DO <= x"00000000";
when 1437 => DO <= x"00000000";
when 1438 => DO <= x"00000000";
when 1439 => DO <= x"00000000";
when 1440 => DO <= x"00000000";
when 1441 => DO <= x"00000000";
when 1442 => DO <= x"00000000";
when 1443 => DO <= x"00000000";
when 1444 => DO <= x"00000000";
when 1445 => DO <= x"00000000";
when 1446 => DO <= x"00000000";
when 1447 => DO <= x"00000000";
when 1448 => DO <= x"00000000";
when 1449 => DO <= x"00000000";
when 1450 => DO <= x"00000000";
when 1451 => DO <= x"00000000";
when 1452 => DO <= x"00000000";
when 1453 => DO <= x"00000000";
when 1454 => DO <= x"00000000";
when 1455 => DO <= x"00000000";
when 1456 => DO <= x"00000000";
when 1457 => DO <= x"00000000";
when 1458 => DO <= x"00000000";
when 1459 => DO <= x"00000000";
when 1460 => DO <= x"00000000";
when 1461 => DO <= x"00000000";
when 1462 => DO <= x"00000000";
when 1463 => DO <= x"00000000";
when 1464 => DO <= x"00000000";
when 1465 => DO <= x"00000000";
when 1466 => DO <= x"00000000";
when 1467 => DO <= x"00000000";
when 1468 => DO <= x"00000000";
when 1469 => DO <= x"00000000";
when 1470 => DO <= x"00000000";
when 1471 => DO <= x"00000000";
when 1472 => DO <= x"00000000";
when 1473 => DO <= x"00000000";
when 1474 => DO <= x"00000000";
when 1475 => DO <= x"00000000";
when 1476 => DO <= x"00000000";
when 1477 => DO <= x"00000000";
when 1478 => DO <= x"00000000";
when 1479 => DO <= x"00000000";
when 1480 => DO <= x"00000000";
when 1481 => DO <= x"00000000";
when 1482 => DO <= x"00000000";
when 1483 => DO <= x"00000000";
when 1484 => DO <= x"00000000";
when 1485 => DO <= x"00000000";
when 1486 => DO <= x"00000000";
when 1487 => DO <= x"00000000";
when 1488 => DO <= x"00000000";
when 1489 => DO <= x"00000000";
when 1490 => DO <= x"00000000";
when 1491 => DO <= x"00000000";
when 1492 => DO <= x"00000000";
when 1493 => DO <= x"00000000";
when 1494 => DO <= x"00000000";
when 1495 => DO <= x"00000000";
when 1496 => DO <= x"00000000";
when 1497 => DO <= x"00000000";
when 1498 => DO <= x"00000000";
when 1499 => DO <= x"00000000";
when 1500 => DO <= x"00000000";
when 1501 => DO <= x"00000000";
when 1502 => DO <= x"00000000";
when 1503 => DO <= x"00000000";
when 1504 => DO <= x"00000000";
when 1505 => DO <= x"00000000";
when 1506 => DO <= x"00000000";
when 1507 => DO <= x"00000000";
when 1508 => DO <= x"00000000";
when 1509 => DO <= x"00000000";
when 1510 => DO <= x"00000000";
when 1511 => DO <= x"00000000";
when 1512 => DO <= x"00000000";
when 1513 => DO <= x"00000000";
when 1514 => DO <= x"00000000";
when 1515 => DO <= x"00000000";
when 1516 => DO <= x"00000000";
when 1517 => DO <= x"00000000";
when 1518 => DO <= x"00000000";
when 1519 => DO <= x"00000000";
when 1520 => DO <= x"00000000";
when 1521 => DO <= x"00000000";
when 1522 => DO <= x"00000000";
when 1523 => DO <= x"00000000";
when 1524 => DO <= x"00000000";
when 1525 => DO <= x"00000000";
when 1526 => DO <= x"00000000";
when 1527 => DO <= x"00000000";
when 1528 => DO <= x"00000000";
when 1529 => DO <= x"00000000";
when 1530 => DO <= x"00000000";
when 1531 => DO <= x"00000000";
when 1532 => DO <= x"00000000";
when 1533 => DO <= x"00000000";
when 1534 => DO <= x"00000000";
when 1535 => DO <= x"00000000";
when 1536 => DO <= x"00000000";
when 1537 => DO <= x"00000000";
when 1538 => DO <= x"00000000";
when 1539 => DO <= x"00000000";
when 1540 => DO <= x"00000000";
when 1541 => DO <= x"00000000";
when 1542 => DO <= x"00000000";
when 1543 => DO <= x"00000000";
when 1544 => DO <= x"00000000";
when 1545 => DO <= x"00000000";
when 1546 => DO <= x"00000000";
when 1547 => DO <= x"00000000";
when 1548 => DO <= x"00000000";
when 1549 => DO <= x"00000000";
when 1550 => DO <= x"00000000";
when 1551 => DO <= x"00000000";
when 1552 => DO <= x"00000000";
when 1553 => DO <= x"00000000";
when 1554 => DO <= x"00000000";
when 1555 => DO <= x"00000000";
when 1556 => DO <= x"00000000";
when 1557 => DO <= x"00000000";
when 1558 => DO <= x"00000000";
when 1559 => DO <= x"00000000";
when 1560 => DO <= x"00000000";
when 1561 => DO <= x"00000000";
when 1562 => DO <= x"00000000";
when 1563 => DO <= x"00000000";
when 1564 => DO <= x"00000000";
when 1565 => DO <= x"00000000";
when 1566 => DO <= x"00000000";
when 1567 => DO <= x"00000000";
when 1568 => DO <= x"00000000";
when 1569 => DO <= x"00000000";
when 1570 => DO <= x"00000000";
when 1571 => DO <= x"00000000";
when 1572 => DO <= x"00000000";
when 1573 => DO <= x"00000000";
when 1574 => DO <= x"00000000";
when 1575 => DO <= x"00000000";
when 1576 => DO <= x"00000000";
when 1577 => DO <= x"00000000";
when 1578 => DO <= x"00000000";
when 1579 => DO <= x"00000000";
when 1580 => DO <= x"00000000";
when 1581 => DO <= x"00000000";
when 1582 => DO <= x"00000000";
when 1583 => DO <= x"00000000";
when 1584 => DO <= x"00000000";
when 1585 => DO <= x"00000000";
when 1586 => DO <= x"00000000";
when 1587 => DO <= x"00000000";
when 1588 => DO <= x"00000000";
when 1589 => DO <= x"00000000";
when 1590 => DO <= x"00000000";
when 1591 => DO <= x"00000000";
when 1592 => DO <= x"00000000";
when 1593 => DO <= x"00000000";
when 1594 => DO <= x"00000000";
when 1595 => DO <= x"00000000";
when 1596 => DO <= x"00000000";
when 1597 => DO <= x"00000000";
when 1598 => DO <= x"00000000";
when 1599 => DO <= x"00000000";
when 1600 => DO <= x"00000000";
when 1601 => DO <= x"00000000";
when 1602 => DO <= x"00000000";
when 1603 => DO <= x"00000000";
when 1604 => DO <= x"00000000";
when 1605 => DO <= x"00000000";
when 1606 => DO <= x"00000000";
when 1607 => DO <= x"00000000";
when 1608 => DO <= x"00000000";
when 1609 => DO <= x"00000000";
when 1610 => DO <= x"00000000";
when 1611 => DO <= x"00000000";
when 1612 => DO <= x"00000000";
when 1613 => DO <= x"00000000";
when 1614 => DO <= x"00000000";
when 1615 => DO <= x"00000000";
when 1616 => DO <= x"00000000";
when 1617 => DO <= x"00000000";
when 1618 => DO <= x"00000000";
when 1619 => DO <= x"00000000";
when 1620 => DO <= x"00000000";
when 1621 => DO <= x"00000000";
when 1622 => DO <= x"00000000";
when 1623 => DO <= x"00000000";
when 1624 => DO <= x"00000000";
when 1625 => DO <= x"00000000";
when 1626 => DO <= x"00000000";
when 1627 => DO <= x"00000000";
when 1628 => DO <= x"00000000";
when 1629 => DO <= x"00000000";
when 1630 => DO <= x"00000000";
when 1631 => DO <= x"00000000";
when 1632 => DO <= x"00000000";
when 1633 => DO <= x"00000000";
when 1634 => DO <= x"00000000";
when 1635 => DO <= x"00000000";
when 1636 => DO <= x"00000000";
when 1637 => DO <= x"00000000";
when 1638 => DO <= x"00000000";
when 1639 => DO <= x"00000000";
when 1640 => DO <= x"00000000";
when 1641 => DO <= x"00000000";
when 1642 => DO <= x"00000000";
when 1643 => DO <= x"00000000";
when 1644 => DO <= x"00000000";
when 1645 => DO <= x"00000000";
when 1646 => DO <= x"00000000";
when 1647 => DO <= x"00000000";
when 1648 => DO <= x"00000000";
when 1649 => DO <= x"00000000";
when 1650 => DO <= x"00000000";
when 1651 => DO <= x"00000000";
when 1652 => DO <= x"00000000";
when 1653 => DO <= x"00000000";
when 1654 => DO <= x"00000000";
when 1655 => DO <= x"00000000";
when 1656 => DO <= x"00000000";
when 1657 => DO <= x"00000000";
when 1658 => DO <= x"00000000";
when 1659 => DO <= x"00000000";
when 1660 => DO <= x"00000000";
when 1661 => DO <= x"00000000";
when 1662 => DO <= x"00000000";
when 1663 => DO <= x"00000000";
when 1664 => DO <= x"00000000";
when 1665 => DO <= x"00000000";
when 1666 => DO <= x"00000000";
when 1667 => DO <= x"00000000";
when 1668 => DO <= x"00000000";
when 1669 => DO <= x"00000000";
when 1670 => DO <= x"00000000";
when 1671 => DO <= x"00000000";
when 1672 => DO <= x"00000000";
when 1673 => DO <= x"00000000";
when 1674 => DO <= x"00000000";
when 1675 => DO <= x"00000000";
when 1676 => DO <= x"00000000";
when 1677 => DO <= x"00000000";
when 1678 => DO <= x"00000000";
when 1679 => DO <= x"00000000";
when 1680 => DO <= x"00000000";
when 1681 => DO <= x"00000000";
when 1682 => DO <= x"00000000";
when 1683 => DO <= x"00000000";
when 1684 => DO <= x"00000000";
when 1685 => DO <= x"00000000";
when 1686 => DO <= x"00000000";
when 1687 => DO <= x"00000000";
when 1688 => DO <= x"00000000";
when 1689 => DO <= x"00000000";
when 1690 => DO <= x"00000000";
when 1691 => DO <= x"00000000";
when 1692 => DO <= x"00000000";
when 1693 => DO <= x"00000000";
when 1694 => DO <= x"00000000";
when 1695 => DO <= x"00000000";
when 1696 => DO <= x"00000000";
when 1697 => DO <= x"00000000";
when 1698 => DO <= x"00000000";
when 1699 => DO <= x"00000000";
when 1700 => DO <= x"00000000";
when 1701 => DO <= x"00000000";
when 1702 => DO <= x"00000000";
when 1703 => DO <= x"00000000";
when 1704 => DO <= x"00000000";
when 1705 => DO <= x"00000000";
when 1706 => DO <= x"00000000";
when 1707 => DO <= x"00000000";
when 1708 => DO <= x"00000000";
when 1709 => DO <= x"00000000";
when 1710 => DO <= x"00000000";
when 1711 => DO <= x"00000000";
when 1712 => DO <= x"00000000";
when 1713 => DO <= x"00000000";
when 1714 => DO <= x"00000000";
when 1715 => DO <= x"00000000";
when 1716 => DO <= x"00000000";
when 1717 => DO <= x"00000000";
when 1718 => DO <= x"00000000";
when 1719 => DO <= x"00000000";
when 1720 => DO <= x"00000000";
when 1721 => DO <= x"00000000";
when 1722 => DO <= x"00000000";
when 1723 => DO <= x"00000000";
when 1724 => DO <= x"00000000";
when 1725 => DO <= x"00000000";
when 1726 => DO <= x"00000000";
when 1727 => DO <= x"00000000";
when 1728 => DO <= x"00000000";
when 1729 => DO <= x"00000000";
when 1730 => DO <= x"00000000";
when 1731 => DO <= x"00000000";
when 1732 => DO <= x"00000000";
when 1733 => DO <= x"00000000";
when 1734 => DO <= x"00000000";
when 1735 => DO <= x"00000000";
when 1736 => DO <= x"00000000";
when 1737 => DO <= x"00000000";
when 1738 => DO <= x"00000000";
when 1739 => DO <= x"00000000";
when 1740 => DO <= x"00000000";
when 1741 => DO <= x"00000000";
when 1742 => DO <= x"00000000";
when 1743 => DO <= x"00000000";
when 1744 => DO <= x"00000000";
when 1745 => DO <= x"00000000";
when 1746 => DO <= x"00000000";
when 1747 => DO <= x"00000000";
when 1748 => DO <= x"00000000";
when 1749 => DO <= x"00000000";
when 1750 => DO <= x"00000000";
when 1751 => DO <= x"00000000";
when 1752 => DO <= x"00000000";
when 1753 => DO <= x"00000000";
when 1754 => DO <= x"00000000";
when 1755 => DO <= x"00000000";
when 1756 => DO <= x"00000000";
when 1757 => DO <= x"00000000";
when 1758 => DO <= x"00000000";
when 1759 => DO <= x"00000000";
when 1760 => DO <= x"00000000";
when 1761 => DO <= x"00000000";
when 1762 => DO <= x"00000000";
when 1763 => DO <= x"00000000";
when 1764 => DO <= x"00000000";
when 1765 => DO <= x"00000000";
when 1766 => DO <= x"00000000";
when 1767 => DO <= x"00000000";
when 1768 => DO <= x"00000000";
when 1769 => DO <= x"00000000";
when 1770 => DO <= x"00000000";
when 1771 => DO <= x"00000000";
when 1772 => DO <= x"00000000";
when 1773 => DO <= x"00000000";
when 1774 => DO <= x"00000000";
when 1775 => DO <= x"00000000";
when 1776 => DO <= x"00000000";
when 1777 => DO <= x"00000000";
when 1778 => DO <= x"00000000";
when 1779 => DO <= x"00000000";
when 1780 => DO <= x"00000000";
when 1781 => DO <= x"00000000";
when 1782 => DO <= x"00000000";
when 1783 => DO <= x"00000000";
when 1784 => DO <= x"00000000";
when 1785 => DO <= x"00000000";
when 1786 => DO <= x"00000000";
when 1787 => DO <= x"00000000";
when 1788 => DO <= x"00000000";
when 1789 => DO <= x"00000000";
when 1790 => DO <= x"00000000";
when 1791 => DO <= x"00000000";
when 1792 => DO <= x"00000000";
when 1793 => DO <= x"00000000";
when 1794 => DO <= x"00000000";
when 1795 => DO <= x"00000000";
when 1796 => DO <= x"00000000";
when 1797 => DO <= x"00000000";
when 1798 => DO <= x"00000000";
when 1799 => DO <= x"00000000";
when 1800 => DO <= x"00000000";
when 1801 => DO <= x"00000000";
when 1802 => DO <= x"00000000";
when 1803 => DO <= x"00000000";
when 1804 => DO <= x"00000000";
when 1805 => DO <= x"00000000";
when 1806 => DO <= x"00000000";
when 1807 => DO <= x"00000000";
when 1808 => DO <= x"00000000";
when 1809 => DO <= x"00000000";
when 1810 => DO <= x"00000000";
when 1811 => DO <= x"00000000";
when 1812 => DO <= x"00000000";
when 1813 => DO <= x"00000000";
when 1814 => DO <= x"00000000";
when 1815 => DO <= x"00000000";
when 1816 => DO <= x"00000000";
when 1817 => DO <= x"00000000";
when 1818 => DO <= x"00000000";
when 1819 => DO <= x"00000000";
when 1820 => DO <= x"00000000";
when 1821 => DO <= x"00000000";
when 1822 => DO <= x"00000000";
when 1823 => DO <= x"00000000";
when 1824 => DO <= x"00000000";
when 1825 => DO <= x"00000000";
when 1826 => DO <= x"00000000";
when 1827 => DO <= x"00000000";
when 1828 => DO <= x"00000000";
when 1829 => DO <= x"00000000";
when 1830 => DO <= x"00000000";
when 1831 => DO <= x"00000000";
when 1832 => DO <= x"00000000";
when 1833 => DO <= x"00000000";
when 1834 => DO <= x"00000000";
when 1835 => DO <= x"00000000";
when 1836 => DO <= x"00000000";
when 1837 => DO <= x"00000000";
when 1838 => DO <= x"00000000";
when 1839 => DO <= x"00000000";
when 1840 => DO <= x"00000000";
when 1841 => DO <= x"00000000";
when 1842 => DO <= x"00000000";
when 1843 => DO <= x"00000000";
when 1844 => DO <= x"00000000";
when 1845 => DO <= x"00000000";
when 1846 => DO <= x"00000000";
when 1847 => DO <= x"00000000";
when 1848 => DO <= x"00000000";
when 1849 => DO <= x"00000000";
when 1850 => DO <= x"00000000";
when 1851 => DO <= x"00000000";
when 1852 => DO <= x"00000000";
when 1853 => DO <= x"00000000";
when 1854 => DO <= x"00000000";
when 1855 => DO <= x"00000000";
when 1856 => DO <= x"00000000";
when 1857 => DO <= x"00000000";
when 1858 => DO <= x"00000000";
when 1859 => DO <= x"00000000";
when 1860 => DO <= x"00000000";
when 1861 => DO <= x"00000000";
when 1862 => DO <= x"00000000";
when 1863 => DO <= x"00000000";
when 1864 => DO <= x"00000000";
when 1865 => DO <= x"00000000";
when 1866 => DO <= x"00000000";
when 1867 => DO <= x"00000000";
when 1868 => DO <= x"00000000";
when 1869 => DO <= x"00000000";
when 1870 => DO <= x"00000000";
when 1871 => DO <= x"00000000";
when 1872 => DO <= x"00000000";
when 1873 => DO <= x"00000000";
when 1874 => DO <= x"00000000";
when 1875 => DO <= x"00000000";
when 1876 => DO <= x"00000000";
when 1877 => DO <= x"00000000";
when 1878 => DO <= x"00000000";
when 1879 => DO <= x"00000000";
when 1880 => DO <= x"00000000";
when 1881 => DO <= x"00000000";
when 1882 => DO <= x"00000000";
when 1883 => DO <= x"00000000";
when 1884 => DO <= x"00000000";
when 1885 => DO <= x"00000000";
when 1886 => DO <= x"00000000";
when 1887 => DO <= x"00000000";
when 1888 => DO <= x"00000000";
when 1889 => DO <= x"00000000";
when 1890 => DO <= x"00000000";
when 1891 => DO <= x"00000000";
when 1892 => DO <= x"00000000";
when 1893 => DO <= x"00000000";
when 1894 => DO <= x"00000000";
when 1895 => DO <= x"00000000";
when 1896 => DO <= x"00000000";
when 1897 => DO <= x"00000000";
when 1898 => DO <= x"00000000";
when 1899 => DO <= x"00000000";
when 1900 => DO <= x"00000000";
when 1901 => DO <= x"00000000";
when 1902 => DO <= x"00000000";
when 1903 => DO <= x"00000000";
when 1904 => DO <= x"00000000";
when 1905 => DO <= x"00000000";
when 1906 => DO <= x"00000000";
when 1907 => DO <= x"00000000";
when 1908 => DO <= x"00000000";
when 1909 => DO <= x"00000000";
when 1910 => DO <= x"00000000";
when 1911 => DO <= x"00000000";
when 1912 => DO <= x"00000000";
when 1913 => DO <= x"00000000";
when 1914 => DO <= x"00000000";
when 1915 => DO <= x"00000000";
when 1916 => DO <= x"00000000";
when 1917 => DO <= x"00000000";
when 1918 => DO <= x"00000000";
when 1919 => DO <= x"00000000";
when 1920 => DO <= x"00000000";
when 1921 => DO <= x"00000000";
when 1922 => DO <= x"00000000";
when 1923 => DO <= x"00000000";
when 1924 => DO <= x"00000000";
when 1925 => DO <= x"00000000";
when 1926 => DO <= x"00000000";
when 1927 => DO <= x"00000000";
when 1928 => DO <= x"00000000";
when 1929 => DO <= x"00000000";
when 1930 => DO <= x"00000000";
when 1931 => DO <= x"00000000";
when 1932 => DO <= x"00000000";
when 1933 => DO <= x"00000000";
when 1934 => DO <= x"00000000";
when 1935 => DO <= x"00000000";
when 1936 => DO <= x"00000000";
when 1937 => DO <= x"00000000";
when 1938 => DO <= x"00000000";
when 1939 => DO <= x"00000000";
when 1940 => DO <= x"00000000";
when 1941 => DO <= x"00000000";
when 1942 => DO <= x"00000000";
when 1943 => DO <= x"00000000";
when 1944 => DO <= x"00000000";
when 1945 => DO <= x"00000000";
when 1946 => DO <= x"00000000";
when 1947 => DO <= x"00000000";
when 1948 => DO <= x"00000000";
when 1949 => DO <= x"00000000";
when 1950 => DO <= x"00000000";
when 1951 => DO <= x"00000000";
when 1952 => DO <= x"00000000";
when 1953 => DO <= x"00000000";
when 1954 => DO <= x"00000000";
when 1955 => DO <= x"00000000";
when 1956 => DO <= x"00000000";
when 1957 => DO <= x"00000000";
when 1958 => DO <= x"00000000";
when 1959 => DO <= x"00000000";
when 1960 => DO <= x"00000000";
when 1961 => DO <= x"00000000";
when 1962 => DO <= x"00000000";
when 1963 => DO <= x"00000000";
when 1964 => DO <= x"00000000";
when 1965 => DO <= x"00000000";
when 1966 => DO <= x"00000000";
when 1967 => DO <= x"00000000";
when 1968 => DO <= x"00000000";
when 1969 => DO <= x"00000000";
when 1970 => DO <= x"00000000";
when 1971 => DO <= x"00000000";
when 1972 => DO <= x"00000000";
when 1973 => DO <= x"00000000";
when 1974 => DO <= x"00000000";
when 1975 => DO <= x"00000000";
when 1976 => DO <= x"00000000";
when 1977 => DO <= x"00000000";
when 1978 => DO <= x"00000000";
when 1979 => DO <= x"00000000";
when 1980 => DO <= x"00000000";
when 1981 => DO <= x"00000000";
when 1982 => DO <= x"00000000";
when 1983 => DO <= x"00000000";
when 1984 => DO <= x"00000000";
when 1985 => DO <= x"00000000";
when 1986 => DO <= x"00000000";
when 1987 => DO <= x"00000000";
when 1988 => DO <= x"00000000";
when 1989 => DO <= x"00000000";
when 1990 => DO <= x"00000000";
when 1991 => DO <= x"00000000";
when 1992 => DO <= x"00000000";
when 1993 => DO <= x"00000000";
when 1994 => DO <= x"00000000";
when 1995 => DO <= x"00000000";
when 1996 => DO <= x"00000000";
when 1997 => DO <= x"00000000";
when 1998 => DO <= x"00000000";
when 1999 => DO <= x"00000000";
when 2000 => DO <= x"00000000";
when 2001 => DO <= x"00000000";
when 2002 => DO <= x"00000000";
when 2003 => DO <= x"00000000";
when 2004 => DO <= x"00000000";
when 2005 => DO <= x"00000000";
when 2006 => DO <= x"00000000";
when 2007 => DO <= x"00000000";
when 2008 => DO <= x"00000000";
when 2009 => DO <= x"00000000";
when 2010 => DO <= x"00000000";
when 2011 => DO <= x"00000000";
when 2012 => DO <= x"00000000";
when 2013 => DO <= x"00000000";
when 2014 => DO <= x"00000000";
when 2015 => DO <= x"00000000";
when 2016 => DO <= x"00000000";
when 2017 => DO <= x"00000000";
when 2018 => DO <= x"00000000";
when 2019 => DO <= x"00000000";
when 2020 => DO <= x"00000000";
when 2021 => DO <= x"00000000";
when 2022 => DO <= x"00000000";
when 2023 => DO <= x"00000000";
when 2024 => DO <= x"00000000";
when 2025 => DO <= x"00000000";
when 2026 => DO <= x"00000000";
when 2027 => DO <= x"00000000";
when 2028 => DO <= x"00000000";
when 2029 => DO <= x"00000000";
when 2030 => DO <= x"00000000";
when 2031 => DO <= x"00000000";
when 2032 => DO <= x"00000000";
when 2033 => DO <= x"00000000";
when 2034 => DO <= x"00000000";
when 2035 => DO <= x"00000000";
when 2036 => DO <= x"00000000";
when 2037 => DO <= x"00000000";
when 2038 => DO <= x"00000000";
when 2039 => DO <= x"00000000";
when 2040 => DO <= x"00000000";
when 2041 => DO <= x"00000000";
when 2042 => DO <= x"00000000";
when 2043 => DO <= x"00000000";
when 2044 => DO <= x"00000000";
when 2045 => DO <= x"00000000";
when 2046 => DO <= x"00000000";
when 2047 => DO <= x"00000000";
when others =>
end case;
end if;
end if;
end process;
end behave;
| bsd-3-clause | fe1896fe215d7d9672c99b312f5981eb | 0.481146 | 3.413305 | false | false | false | false |
alvieboy/xtc-base | clkgen.vhd | 1 | 4,479 | --
-- System Clock generator for ZPUINO (papilio one)
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
entity clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout1: out std_logic;
clkout2: out std_logic;
vgaclk: out std_logic;
rstout: out std_logic
);
end entity clkgen;
architecture behave of clkgen is
signal dcmlocked: std_ulogic;
signal dcmclock: std_ulogic;
signal rst1_q: std_logic := '1';
signal rst2_q: std_logic := '1';
signal clkout_i: std_ulogic;
signal clkin_i: std_ulogic;
signal clkfb: std_ulogic;
signal clk0: std_ulogic;
signal clk1: std_ulogic;
signal clk2: std_ulogic;
signal clk2x: std_ulogic;
signal clkin_i_2: std_logic;
begin
clkout <= clkout_i;
rstout <= rst1_q;
process(dcmlocked, clkout_i, rstin)
begin
if dcmlocked='0' or rstin='1' then
rst1_q <= '1';
rst2_q <= '1';
else
if rising_edge(clkout_i) then
rst1_q <= rst2_q;
rst2_q <= '0';
end if;
end if;
end process;
-- Clock buffers
clkfx_inst: BUFG
port map (
I => clk0,
O => clkout_i
);
clkin_inst: IBUFG
port map (
I => clkin,
O => clkin_i
);
clkfb_inst: BUFG
port map (
I=> dcmclock,
O=> clkfb
);
clk1_inst: BUFG port map ( I => clk1, O => clkout1 );
clk2_inst: BUFG port map ( I => clk2, O => clkout2 );
clk3_inst: BUFG port map ( I => clk2x, O => vgaclk );
pll_base_inst : PLL_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 30,--30 -- 20,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,--10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 10,
CLKOUT1_PHASE => 250.0,--300.0,--155.52,--103.700,--343.125,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 10,
CLKOUT2_PHASE => 0.0,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 38, --31,--38,
CLKOUT3_PHASE => 0.0,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 31.250,
REF_JITTER => 0.010,
SIM_DEVICE => "SPARTAN6")
port map
-- Output clocks
(CLKFBOUT => dcmclock,
CLKOUT0 => clk0,
CLKOUT1 => clk1,
CLKOUT2 => clk2,
CLKOUT3 => clk2x,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => dcmlocked,
RST => '0',
-- Input clock control
CLKFBIN => clkfb,
CLKIN1 => clkin_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0'
);
end behave;
| bsd-3-clause | 5eb29673823aeb86bc3e65ce90c73dd1 | 0.589194 | 3.515699 | false | false | false | false |
EPiCS/reconos | demos/sort_demo/hw/hwt_sort_demo_v1_00_c/hdl/vhdl/hwt_sort_demo.vhd | 2 | 8,222 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_sort_demo is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(5 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end entity hwt_sort_demo;
architecture implementation of hwt_sort_demo is
-- just for simpler use
signal clk : std_logic;
signal rst : std_logic;
type STATE_TYPE is (
STATE_GET_ADDR,STATE_READ,STATE_SORTING,
STATE_WRITE,STATE_ACK,STATE_THREAD_EXIT);
component bubble_sorter is
generic (
G_LEN : integer := 512; -- number of words to sort
G_AWIDTH : integer := 9; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- local ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- The sorting application reads 'C_LOCAL_RAM_SIZE' 32-bit words into the local RAM,
-- from a given address (send in a message box), sorts them and writes them back into main memory.
-- IMPORTANT: define size of local RAM here!!!!
constant C_LOCAL_RAM_SIZE : integer := 2048;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal addr : std_logic_vector(31 downto 0);
signal len : std_logic_vector(23 downto 0);
signal state : STATE_TYPE;
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
signal o_RAMAddr_sorter : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_sorter : std_logic_vector(0 to 31);
signal o_RAMWE_sorter : std_logic;
signal i_RAMData_sorter : std_logic_vector(0 to 31);
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal ignore : std_logic_vector(31 downto 0);
signal sort_start : std_logic := '0';
signal sort_done : std_logic := '0';
begin
DEBUG_DATA(5) <= '1' when state = STATE_GET_ADDR else '0';
DEBUG_DATA(4) <= '1' when state = STATE_READ else '0';
DEBUG_DATA(3) <= '1' when state = STATE_SORTING else '0';
DEBUG_DATA(2) <= '1' when state = STATE_WRITE else '0';
DEBUG_DATA(1) <= '1' when state = STATE_ACK else '0';
DEBUG_DATA(0) <= '1' when state = STATE_THREAD_EXIT else '0';
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local dual-port RAM
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(conv_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(conv_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_sorter = '1') then
local_ram(conv_integer(unsigned(o_RAMAddr_sorter))) := o_RAMData_sorter;
else
i_RAMData_sorter <= local_ram(conv_integer(unsigned(o_RAMAddr_sorter)));
end if;
end if;
end process;
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => C_LOCAL_RAM_SIZE,
G_AWIDTH => C_LOCAL_RAM_ADDRESS_WIDTH,
G_DWIDTH => 32
)
port map (
clk => clk,
reset => rst,
o_RAMAddr => o_RAMAddr_sorter,
o_RAMData => o_RAMData_sorter,
i_RAMData => i_RAMData_sorter,
o_RAMWE => o_RAMWE_sorter,
start => sort_start,
done => sort_done
);
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- os and memory synchronisation state machine
reconos_fsm: process (clk,rst,o_osif,o_memif,o_ram) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_GET_ADDR;
done := False;
addr <= (others => '0');
len <= (others => '0');
sort_start <= '0';
elsif rising_edge(clk) then
case state is
-- get address via mbox: the data will be copied from this address to the local ram in the next states
when STATE_GET_ADDR =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, addr, done);
if done then
if (addr = X"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
len <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES,24);
addr <= addr(31 downto 2) & "00";
state <= STATE_READ;
end if;
end if;
-- copy data from main memory to local memory
when STATE_READ =>
memif_read(i_ram,o_ram,i_memif,o_memif,addr,X"00000000",len,done);
if done then
sort_start <= '1';
state <= STATE_SORTING;
end if;
-- sort the words in local RAM
when STATE_SORTING =>
sort_start <= '0';
--o_ram.addr <= (others => '0');
if sort_done = '1' then
len <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES,24);
--state <= STATE_WRITE_REQ;
state <= STATE_WRITE;
end if;
-- copy data from local memory to main memory
when STATE_WRITE =>
memif_write(i_ram,o_ram,i_memif,o_memif,X"00000000",addr,len,done);
if done then
state <= STATE_ACK;
end if;
-- send mbox that signals that the sorting is finished
when STATE_ACK =>
osif_mbox_put(i_osif, o_osif, MBOX_SEND, addr, ignore, done);
if done then state <= STATE_GET_ADDR; end if;
-- thread exit
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end architecture;
| gpl-2.0 | 1d9c45ea9ffd1494ac264cfb4b75949d | 0.639139 | 2.759987 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/sgate.vhd | 1 | 32,227 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
ENTITY oper_add IS
GENERIC
(
sgate_representation : NATURAL :=1;
width_a : NATURAL:=8;
width_b : NATURAL:=8;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
cin : IN STD_LOGIC;
cout : OUT STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_add;
ARCHITECTURE sim_arch OF oper_add IS
SIGNAL a_ext : STD_LOGIC_VECTOR(width_a+1 DOWNTO 0);
SIGNAL b_ext : STD_LOGIC_VECTOR(width_a+1 DOWNTO 0);
SIGNAL o_ext : STD_LOGIC_VECTOR(width_a+1 DOWNTO 0);
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_o <= 0) then
ASSERT FALSE
REPORT "Value of width_o parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a /= width_b) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to value of width_b parameter!"
SEVERITY ERROR;
end if;
if (width_a /= width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to value of width_o parameter!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1(SIGNED) or 0(UNSIGNED)!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
g1: IF (width_a=width_b) AND (width_b=width_o) GENERATE
a_ext(width_a-1 DOWNTO 0) <= a(width_a-1 DOWNTO 0);
b_ext(width_a-1 DOWNTO 0) <= b(width_a-1 DOWNTO 0);
g2: IF (sgate_representation>0) GENERATE
a_ext(width_a) <= a_ext(width_a-1);
a_ext(width_a+1) <= a_ext(width_a-1);
b_ext(width_a) <= b_ext(width_a-1);
b_ext(width_a+1) <= b_ext(width_a-1);
END GENERATE g2;
g3: IF (sgate_representation=0) GENERATE
a_ext(width_a) <= '0';
a_ext(width_a+1) <= '0';
b_ext(width_a) <= '0';
b_ext(width_a+1) <= '0';
END GENERATE g3;
o_ext <= cin+a_ext+b_ext;
cout <= o_ext(width_a);
o(width_o-1 DOWNTO 0) <= o_ext(width_a-1 DOWNTO 0);
END GENERATE g1;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
ENTITY oper_addsub IS
GENERIC
(
sgate_representation : NATURAL :=1;
width_a : NATURAL :=8;
width_b : NATURAL :=8;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
addnsub : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_addsub;
ARCHITECTURE sim_arch OF oper_addsub IS
SIGNAL a_ext : STD_LOGIC_VECTOR(width_a DOWNTO 0);
SIGNAL b_ext : STD_LOGIC_VECTOR(width_a DOWNTO 0);
SIGNAL o_ext : STD_LOGIC_VECTOR(width_a DOWNTO 0);
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_o <= 0) then
ASSERT FALSE
REPORT "Value of width_o parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a /= width_b) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to value of width_b parameter!"
SEVERITY ERROR;
end if;
if (width_a /= width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to value of width_o parameter!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
g1: IF (width_a=width_b) AND (width_b=width_o) GENERATE
a_ext(width_a-1 DOWNTO 0) <= a(width_a-1 DOWNTO 0);
b_ext(width_a-1 DOWNTO 0) <= b(width_a-1 DOWNTO 0);
g2: IF (sgate_representation>0) GENERATE
a_ext(width_a) <= a_ext(width_a-1);
b_ext(width_a) <= b_ext(width_a-1);
END GENERATE g2;
g3: IF (sgate_representation=0) GENERATE
a_ext(width_a) <= '0';
b_ext(width_a) <= '0';
END GENERATE g3;
o_ext <= a_ext+b_ext when (addnsub='1') ELSE a_ext-b_ext;
o(width_o-1 DOWNTO 0) <= o_ext(width_a-1 DOWNTO 0);
END GENERATE g1;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY mux21 IS
PORT
(
dataa : IN STD_LOGIC;
datab : IN STD_LOGIC;
dataout : OUT STD_LOGIC;
outputselect : IN STD_LOGIC
);
END mux21;
ARCHITECTURE sim_arch OF mux21 IS
BEGIN
dataout <= dataa WHEN outputselect='0' ELSE datab;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY io_buf_tri IS
PORT
(
datain : IN STD_LOGIC;
dataout : OUT STD_LOGIC;
oe : IN STD_LOGIC
);
END io_buf_tri;
ARCHITECTURE sim_arch OF io_buf_tri IS
BEGIN
dataout <= datain WHEN oe='1' ELSE 'Z';
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY io_buf_opdrn IS
PORT
(
datain : IN STD_LOGIC;
dataout : OUT STD_LOGIC
);
END io_buf_opdrn;
ARCHITECTURE sim_arch OF io_buf_opdrn IS
BEGIN
dataout <= '0' when datain='0' else 'Z';
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY tri_bus IS
GENERIC
(
width_datain : NATURAL:=2;
width_dataout : NATURAL:=1
);
PORT
(
datain : IN STD_LOGIC_VECTOR(width_datain-1 downto 0);
dataout : OUT STD_LOGIC_VECTOR(width_dataout-1 downto 0)
);
END tri_bus;
ARCHITECTURE sim_arch OF tri_bus IS
BEGIN
MSG: process
begin
if (width_datain <= 0) then
ASSERT FALSE
REPORT "Value of width_datain parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_dataout /= 1) then
ASSERT FALSE
REPORT "Value of width_dataout parameter must be equal to 1!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
g:for i in 0 to width_datain-1 generate
dataout(0) <= '1' when (datain(i)='1' or datain(i)='H') ELSE '0' when (datain(i)='0' or datain(i)='L') ELSE 'Z';
end generate g;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
ENTITY oper_mult IS
GENERIC
(
sgate_representation : NATURAL :=1;
width_a : NATURAL :=8;
width_b : NATURAL :=6;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_mult;
ARCHITECTURE sim_arch OF oper_mult IS
SIGNAL a_ext : STD_LOGIC_VECTOR(width_a downto 0);
SIGNAL b_ext : STD_LOGIC_VECTOR(width_b downto 0);
SIGNAL o_ext : STD_LOGIC_VECTOR(width_a+width_b+1 downto 0);
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_o <= 0) then
ASSERT FALSE
REPORT "Value of width_o parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
g1: IF (sgate_representation>0) GENERATE
a_ext(width_a) <= a_ext(width_a-1);
b_ext(width_b) <= b_ext(width_b-1);
END GENERATE g1;
g2: IF (sgate_representation=0) GENERATE
a_ext(width_a) <= '0';
b_ext(width_b) <= '0';
END GENERATE g2;
a_ext(width_a-1 DOWNTO 0) <= a(width_a-1 DOWNTO 0);
b_ext(width_b-1 DOWNTO 0) <= b(width_b-1 DOWNTO 0);
o_ext <= a_ext*b_ext;
o(width_o-1 DOWNTO 0) <= o_ext(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
ENTITY oper_div IS
GENERIC
(
sgate_representation : NATURAL :=1;
width_a : NATURAL :=8;
width_b : NATURAL :=8;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_div;
ARCHITECTURE sim_arch OF oper_div IS
FUNCTION STR_REPRESENTATION( i : NATURAL ) RETURN STRING IS
BEGIN
IF (i>0) THEN
RETURN "SIGNED";
ELSE
RETURN "UNSIGNED";
END IF;
END;
SIGNAL quotient : STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_o <= 0) then
ASSERT FALSE
REPORT "Value of width_o parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
u0 : lpm_divide GENERIC MAP (
lpm_widthn => width_a,
lpm_widthd => width_b,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => STR_REPRESENTATION(sgate_representation),
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => STR_REPRESENTATION(sgate_representation)
)
PORT MAP (
denom => b,
numer => a,
quotient => quotient,
remain => open
);
o(width_o-1 DOWNTO 0) <= quotient(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.all;
ENTITY oper_mod IS
GENERIC
(
sgate_representation : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_mod;
ARCHITECTURE sim_arch OF oper_mod IS
FUNCTION STR_REPRESENTATION( i : NATURAL ) RETURN STRING IS
BEGIN
IF (i>0) THEN
RETURN "SIGNED";
ELSE
RETURN "UNSIGNED";
END IF;
END;
SIGNAL remain : STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_o <= 0) then
ASSERT FALSE
REPORT "Value of width_o parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
u0 : lpm_divide GENERIC MAP (
lpm_widthn => width_a,
lpm_widthd => width_b,
lpm_type => "LPM_DIVIDE",
lpm_nrepresentation => STR_REPRESENTATION(sgate_representation),
lpm_hint => "LPM_REMAINDERPOSITIVE=FALSE",
lpm_drepresentation => STR_REPRESENTATION(sgate_representation)
)
PORT MAP (
denom => b,
numer => a,
quotient => open ,
remain => remain
);
o(width_o-1 DOWNTO 0) <= remain(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY oper_left_shift IS
GENERIC
(
sgate_representation : NATURAL := 0;
width_a : NATURAL :=8;
width_amount : NATURAL :=2;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_left_shift;
ARCHITECTURE sim_arch OF oper_left_shift IS
SIGNAL res : STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
SIGNAL resx : STD_LOGIC_VECTOR(width_a-1 DOWNTO 0); --need to add cin xor functionality
SIGNAL wire_gnd : STD_LOGIC;
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_amount <= 0) then
ASSERT FALSE
REPORT "Value of width_amount parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a < width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than or equal to width_o!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
PROCESS (a, amount, cin)
variable tmpdata : std_logic_vector(width_a-1 downto 0);
variable tmpdist : integer;
BEGIN
tmpdata := conv_std_logic_vector(unsigned(a), width_a);
tmpdist := conv_integer(unsigned(amount));
for i in width_a-1 downto 0 loop
if (i >= tmpdist) then
res(i) <= tmpdata(i-tmpdist);
else
res(i) <= cin;
end if;
end loop;
END PROCESS;
o(width_o-1 DOWNTO 0) <= res(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY oper_right_shift IS
GENERIC
(
sgate_representation : NATURAL :=1;
width_a : NATURAL :=8;
width_amount : NATURAL :=3;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_right_shift;
ARCHITECTURE sim_arch OF oper_right_shift IS
FUNCTION STR_REPRESENTATION( i : NATURAL ) RETURN STRING IS
BEGIN
IF (i>0) THEN
RETURN "ARITHMETIC";
ELSE
RETURN "LOGICAL";
END IF;
END;
SIGNAL res : STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_amount <= 0) then
ASSERT FALSE
REPORT "Value of width_amount parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a < width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than or equal to width_o!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
PROCESS (a, amount, cin)
variable tmpdata : std_logic_vector(width_a-1 downto 0);
variable tmpdist : integer;
BEGIN
tmpdata := conv_std_logic_vector(unsigned(a), width_a);
tmpdist := conv_integer(unsigned(amount));
for i in width_a-1 downto 0 loop
if ((i+tmpdist) < width_a) then
res(i) <= tmpdata(i+tmpdist);
else
res(i) <= cin;
end if;
end loop;
END PROCESS;
o(width_o-1 DOWNTO 0) <= res(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.all;
ENTITY oper_rotate_left IS
GENERIC
(
sgate_representation : NATURAL := 0;
width_a : NATURAL;
width_amount : NATURAL;
width_o : NATURAL
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_rotate_left;
ARCHITECTURE sim_arch OF oper_rotate_left IS
SIGNAL res : STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_amount <= 0) then
ASSERT FALSE
REPORT "Value of width_amount parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a /= width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to width_o!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
wire_gnd <= '0';
U0 : lpm_clshift
GENERIC MAP (
lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ROTATE",
lpm_width => width_a,
lpm_widthdist => width_amount
)
PORT MAP (
distance => amount,
direction => wire_gnd,
data => a,
result => res
);
o(width_o-1 DOWNTO 0) <= res(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.all;
ENTITY oper_rotate_right IS
GENERIC
(
sgate_representation : NATURAL := 0;
width_a : NATURAL :=8;
width_amount : NATURAL :=4;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
amount : IN STD_LOGIC_VECTOR(width_amount-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_rotate_right;
ARCHITECTURE sim_arch OF oper_rotate_right IS
SIGNAL res : STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_amount <= 0) then
ASSERT FALSE
REPORT "Value of width_amount parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a /= width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to width_o!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
wire_vcc <= '1';
U0 : lpm_clshift
GENERIC MAP (
lpm_type => "LPM_CLSHIFT",
lpm_shifttype => "ROTATE",
lpm_width => width_a,
lpm_widthdist => width_amount
)
PORT MAP (
distance => amount,
direction => wire_vcc,
data => a,
result => res
);
o(width_o-1 DOWNTO 0) <= res(width_o-1 DOWNTO 0);
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
ENTITY oper_less_than IS
GENERIC
(
sgate_representation : NATURAL :=0;
width_a : NATURAL :=8;
width_b : NATURAL :=5
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END oper_less_than;
ARCHITECTURE sim_arch OF oper_less_than IS
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (sgate_representation /= 1 AND sgate_representation /= 0) then
ASSERT FALSE
REPORT "Value of sgate_representation parameter must be equal to 1 or 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
g1:IF sgate_representation>0 GENERATE
PROCESS(a,b,cin)
VARIABLE va : SIGNED(width_a-1 DOWNTO 0);
VARIABLE vb : SIGNED(width_b-1 DOWNTO 0);
BEGIN
va := SIGNED(a);
vb := SIGNED(b);
IF (va<vb) THEN
o <= '1';
ELSIF (va=vb) AND (cin='1') THEN
o <= '1';
ELSE
o <= '0';
END IF;
END PROCESS;
END GENERATE g1;
g2:IF sgate_representation=0 GENERATE
PROCESS(a,b,cin)
VARIABLE va : UNSIGNED(width_a-1 DOWNTO 0);
VARIABLE vb : UNSIGNED(width_b-1 DOWNTO 0);
BEGIN
va := UNSIGNED(a);
vb := UNSIGNED(b);
IF (va<vb) THEN
o <= '1';
ELSIF (va=vb) AND (cin='1') THEN
o <= '1';
ELSE
o <= '0';
END IF;
END PROCESS;
END GENERATE g2;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library sgate;
use sgate.sgate_pack.all;
ENTITY oper_mux IS
GENERIC
(
width_sel : NATURAL :=3;
width_data : NATURAL :=8
);
PORT
(
sel : IN STD_LOGIC_VECTOR(width_sel-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(width_data-1 DOWNTO 0);
o : OUT STD_LOGIC
);
END oper_mux;
ARCHITECTURE sim_arch OF oper_mux IS
BEGIN
MSG: process
begin
if (width_data <= 0) then
ASSERT FALSE
REPORT "Value of width_data parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_sel <= 0) then
ASSERT FALSE
REPORT "Value of width_sel parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
o <= data(sgate_conv_integer(sel));
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY oper_selector IS
GENERIC
(
width_sel : NATURAL :=8;
width_data : NATURAL :=8
);
PORT
(
sel : IN STD_LOGIC_VECTOR(width_sel-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(width_data-1 DOWNTO 0);
o : OUT STD_LOGIC
);
END oper_selector;
ARCHITECTURE sim_arch OF oper_selector IS
BEGIN
MSG: process
begin
if (width_data <= 0) then
ASSERT FALSE
REPORT "Value of width_data parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_sel /= width_data) then
ASSERT FALSE
REPORT "Value of width_sel parameter must be equal to width_data!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
PROCESS (data, sel)
variable temp_result : STD_LOGIC := '0';
BEGIN
FOR k IN 0 TO width_data-1 LOOP
IF (sel(k) = '1') THEN
temp_result := data(k);
END IF;
END LOOP;
o <= temp_result;
END PROCESS;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
ENTITY oper_prio_selector IS
GENERIC
(
width_sel : NATURAL;
width_data : NATURAL
);
PORT
(
sel : IN STD_LOGIC_VECTOR(width_sel-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(width_data-1 DOWNTO 0);
cin : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END oper_prio_selector;
ARCHITECTURE sim_arch OF oper_prio_selector IS
BEGIN
g1:FOR k IN 0 TO width_sel-1 GENERATE
o <= data(k) WHEN (sel(k)='1') ELSE 'Z';
END GENERATE;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
ENTITY oper_decoder IS
GENERIC
(
width_i : NATURAL :=1;
width_o : NATURAL :=2
);
PORT
(
i : IN STD_LOGIC_VECTOR(width_i-1 DOWNTO 0);
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_decoder;
ARCHITECTURE sim_arch OF oper_decoder IS
FUNCTION int2ustd(value : integer; width : integer) RETURN std_logic_vector IS
-- convert integer to unsigned std_logicvector
BEGIN
RETURN conv_std_logic_vector(CONV_UNSIGNED(value, width ), width);
END int2ustd;
BEGIN
MSG: process
begin
if (width_i <= 0) then
ASSERT FALSE
REPORT "Value of width_i parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_o <= 0) then
ASSERT FALSE
REPORT "Value of width_o parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
G1:FOR k IN 0 TO width_o-1 GENERATE
o(k) <= '1' WHEN (i=int2ustd(k,width_i)) ELSE '0';
END GENERATE;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY oper_bus_mux IS
GENERIC
(
width_a : NATURAL :=8;
width_b : NATURAL :=8;
width_o : NATURAL :=8
);
PORT
(
a : IN STD_LOGIC_VECTOR(width_a-1 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(width_b-1 DOWNTO 0);
sel : IN STD_LOGIC;
o : OUT STD_LOGIC_VECTOR(width_o-1 DOWNTO 0)
);
END oper_bus_mux;
ARCHITECTURE sim_arch OF oper_bus_mux IS
BEGIN
MSG: process
begin
if (width_a <= 0) then
ASSERT FALSE
REPORT "Value of width_a parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_b <= 0) then
ASSERT FALSE
REPORT "Value of width_b parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (width_a /= width_b) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to width_b!"
SEVERITY ERROR;
end if;
if (width_a /= width_o) then
ASSERT FALSE
REPORT "Value of width_a parameter must be equal to width_o!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
o <= a WHEN sel='0' ELSE b;
END sim_arch;
--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
ENTITY oper_latch IS
PORT
(
datain : IN STD_LOGIC;
aclr : IN STD_LOGIC;
preset : IN STD_LOGIC;
dataout : OUT STD_LOGIC;
latch_enable : IN STD_LOGIC
);
END oper_latch;
ARCHITECTURE sim_arch OF oper_latch IS
BEGIN
PROCESS(datain, latch_enable, aclr, preset)
BEGIN
if (aclr = '1') then
dataout <= '0';
elsif (preset = '1') then
dataout <= '1';
elsif (latch_enable = '1') then
dataout <= datain;
end if;
END PROCESS;
END sim_arch;
| gpl-3.0 | 947fafc7e98618f5fe9bc24462acc25a | 0.530208 | 3.557849 | false | false | false | false |
asicguy/gplgpu | hdl/sim_lib/stratixiii_components.vhd | 1 | 104,407 | -- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
package stratixiii_components is
--
-- stratixiii_jtag
--
COMPONENT stratixiii_jtag
generic (
lpm_type : string := "stratixiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- stratixiii_crcblock
--
COMPONENT stratixiii_crcblock
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiii_lcell_comb
--
COMPONENT stratixiii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- stratixiii_routing_wire
--
COMPONENT stratixiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- stratixiii_lvds_transmitter
--
COMPONENT stratixiii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- stratixiii_rublock
--
COMPONENT stratixiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
END COMPONENT;
--
-- stratixiii_ram_block
--
COMPONENT stratixiii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiii_ff
--
COMPONENT stratixiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
END COMPONENT;
--
-- stratixiii_clkselect
--
COMPONENT stratixiii_clkselect
generic (
lpm_type : STRING := "stratixiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiii_clkena
--
COMPONENT stratixiii_clkena
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
END COMPONENT;
--
-- stratixiii_mlab_cell
--
COMPONENT stratixiii_mlab_cell
GENERIC (
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiii_io_ibuf
--
COMPONENT stratixiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_io_obuf
--
COMPONENT stratixiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_ddio_in
--
COMPONENT stratixiii_ddio_in
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_ddio_oe
--
COMPONENT stratixiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_ddio_out
--
COMPONENT stratixiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_termination
--
COMPONENT stratixiii_termination
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END COMPONENT;
--
-- stratixiii_termination_logic
--
COMPONENT stratixiii_termination_logic
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END COMPONENT;
--
-- stratixiii_dll
--
COMPONENT stratixiii_dll
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dll_offset_ctrl
--
COMPONENT stratixiii_dll_offset_ctrl
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiii_dqs_delay_chain
--
COMPONENT stratixiii_dqs_delay_chain
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
test_enable : string := "false";
test_select : integer := 0;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dqs_enable
--
COMPONENT stratixiii_dqs_enable
GENERIC (
lpm_type : string := "stratixiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dqs_enable_ctrl
--
COMPONENT stratixiii_dqs_enable_ctrl
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_delay_chain
--
COMPONENT stratixiii_delay_chain
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_io_clock_divider
--
COMPONENT stratixiii_io_clock_divider
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_output_phase_alignment
--
COMPONENT stratixiii_output_phase_alignment
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_input_phase_alignment
--
COMPONENT stratixiii_input_phase_alignment
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_half_rate_input
--
COMPONENT stratixiii_half_rate_input
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_io_config
--
COMPONENT stratixiii_io_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_dqs_config
--
COMPONENT stratixiii_dqs_config
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_mac_mult
--
COMPONENT stratixiii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_mac_out
--
COMPONENT stratixiii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_io_pad
--
COMPONENT stratixiii_io_pad
GENERIC (
lpm_type : string := "stratixiii_io_pad");
PORT (
padin : IN std_logic := '0'; -- Input Pad
padout : OUT std_logic); -- Output Pad
END COMPONENT;
--
-- stratixiii_pll
--
COMPONENT stratixiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
family_name : string := "StratixIII";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- stratixiii_asmiblock
--
COMPONENT stratixiii_asmiblock
generic (
lpm_type : string := "stratixiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
END COMPONENT;
--
-- stratixiii_lvds_receiver
--
COMPONENT stratixiii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- stratixiii_pseudo_diff_out
--
COMPONENT stratixiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- stratixiii_bias_block
--
COMPONENT stratixiii_bias_block
GENERIC (
lpm_type : string := "stratixiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
END COMPONENT;
--
-- stratixiii_tsdblock
--
COMPONENT stratixiii_tsdblock
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
END COMPONENT;
end stratixiii_components;
| gpl-3.0 | 266e681711c98b9072e71c5f2de285bb | 0.479958 | 4.390354 | false | false | false | false |
freecores/t400 | bench/vhdl/tb_t420.vhd | 1 | 4,606 | -------------------------------------------------------------------------------
--
-- Testbench for the T420 system toplevel.
--
-- $Id: tb_t420.vhd,v 1.5 2006-06-05 18:50:45 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t420 is
end tb_t420;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t420;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t420 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal io_in_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t420_b : t420
generic map (
opt_ck_div_g => t400_opt_ck_div_4_c,
opt_cko_g => t400_opt_cko_gpi_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
cko_i => io_in_s(2),
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s,
io_in_i => io_in_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
io_in_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => io_in_s,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2006/05/27 19:10:20 arniml
-- explicitly select clock divider 4
--
-- Revision 1.3 2006/05/24 00:48:49 arniml
-- connect cko_i to bit 2 of IN bus
--
-- Revision 1.2 2006/05/23 01:18:10 arniml
-- consider CKO and IN port
--
-- Revision 1.1 2006/05/15 22:21:59 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 4e54cc3c109b95f29191615a5e6ad200 | 0.54277 | 3.638231 | false | false | false | false |
alvieboy/xtc-base | uart.vhd | 1 | 7,925 | --
-- UART for Newcpu
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity uart is
generic (
bits: integer := 11
);
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
tx: out std_logic;
rx: in std_logic
);
end entity uart;
architecture behave of uart is
component uart_rx is
port (
clk: in std_logic;
rst: in std_logic;
rx: in std_logic;
rxclk: in std_logic;
read: in std_logic;
data: out std_logic_vector(7 downto 0);
data_av: out std_logic
);
end component uart_rx;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
intx_o : out std_logic; -- Tx in progress
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
component fifo is
generic (
bits: integer := 11
);
port (
clk: in std_logic;
rst: in std_logic;
wr: in std_logic;
rd: in std_logic;
write: in std_logic_vector(7 downto 0);
read : out std_logic_vector(7 downto 0);
full: out std_logic;
empty: out std_logic
);
end component fifo;
signal uart_read: std_logic;
signal uart_write: std_logic;
signal divider_tx: std_logic_vector(15 downto 0) := x"000f";
signal divider_rx_q: std_logic_vector(15 downto 0);
signal data_ready: std_logic;
signal received_data: std_logic_vector(7 downto 0);
signal fifo_data: std_logic_vector(7 downto 0);
signal uart_busy: std_logic;
signal uart_intx: std_logic;
signal fifo_empty: std_logic;
signal rx_br: std_logic;
signal tx_br: std_logic;
signal rx_en: std_logic;
signal dready_q: std_logic;
signal data_ready_dly_q: std_logic;
signal fifo_rd: std_logic;
signal enabled_q: std_logic;
signal do_interrupt: std_logic;
signal int_enabled: std_logic;
signal ack: std_logic;
signal tsc: unsigned(31 downto 0);
signal millis: unsigned(31 downto 0);
constant FREQKHZ: integer := 96000; -- TODO
signal milliscount: integer range 0 to FREQKHZ-1;
begin
--enabled <= enabled_q;
wbo.int<= do_interrupt;
wbo.ack <= ack;
wbo.err <= '0';
rx_inst: uart_rx
port map(
clk => syscon.clk,
rst => syscon.rst,
rxclk => rx_br,
read => uart_read,
rx => rx,
data_av => data_ready,
data => received_data
);
uart_read <= dready_q;
tx_core: TxUnit
port map(
clk_i => syscon.clk,
reset_i => syscon.rst,
enable_i => tx_br,
load_i => uart_write,
txd_o => tx,
busy_o => uart_busy,
intx_o => uart_intx,
datai_i => wbi.dat(7 downto 0)
);
-- TODO: check multiple writes
-- Rx timing
rx_timer: uart_brgen
port map(
clk => syscon.clk,
rst => syscon.rst,
en => '1',
clkout => rx_br,
count => divider_rx_q
);
-- Tx timing
tx_timer: uart_brgen
port map(
clk => syscon.clk,
rst => syscon.rst,
en => rx_br,
clkout => tx_br,
count => divider_tx
);
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
dready_q<='0';
data_ready_dly_q<='0';
else
data_ready_dly_q<=data_ready;
if data_ready='1' and data_ready_dly_q='0' then
dready_q<='1';
else
dready_q<='0';
end if;
end if;
end if;
end process;
fifo_instance: fifo
generic map (
bits => bits
)
port map (
clk => syscon.clk,
rst => syscon.rst,
wr => dready_q,
rd => fifo_rd,
write => received_data,
read => fifo_data,
full => open,
empty => fifo_empty
);
fifo_rd<='1' when wbi.adr(3 downto 2)="00" and (wbi.cyc='1' and wbi.stb='1' and wbi.we='0') else '0';
process(syscon.clk)--wb_adr_i, received_data, uart_busy, data_ready, fifo_empty, fifo_data,uart_intx, int_enabled)
begin
if rising_edge(syscon.clk) then
case wbi.adr(3 downto 2) is
when "01" =>
wbo.dat <= (others => '0');
wbo.dat(0) <= not fifo_empty;
wbo.dat(1) <= uart_busy;
wbo.dat(2) <= uart_intx;
wbo.dat(3) <= int_enabled;
when "00" =>
wbo.dat <= (others => '0');
wbo.dat(7 downto 0) <= fifo_data;
when "11" =>
wbo.dat <= std_logic_vector(tsc);
when "10" =>
wbo.dat <= std_logic_vector(millis);
when others =>
wbo.dat <= (others => 'X');
end case;
end if;
end process;
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
tsc <= (others => '0');
milliscount<=FREQKHZ-1;
else
if milliscount=0 then
milliscount<=FREQKHZ-1;
tsc<=tsc+1;
else
milliscount<=milliscount-1;
end if;
end if;
end if;
end process;
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
enabled_q<='0';
int_enabled <= '0';
do_interrupt<='0';
ack<='0';
else
ack <='0';
uart_write<='0';
if wbi.cyc='1' and wbi.stb='1' and ack='0' then
ack <= '1';
if wbi.we='1' then
case wbi.adr(3 downto 2) is
when "00" =>
uart_write <= '1';
when "01" =>
divider_rx_q <= wbi.dat(15 downto 0);
enabled_q <= wbi.dat(16);
when "10" =>
int_enabled <= wbi.dat(0);
do_interrupt <= '0';
when others =>
null;
end case;
end if;
else
if int_enabled='1' and fifo_empty='0' then
do_interrupt <= '1';
int_enabled <= '0';
end if;
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | 20fafb0e1bf435f3522c833929dc8cd7 | 0.56694 | 3.411537 | false | false | false | false |
sittner/lcnc-mdsio | vhdl/source/pci32lite/pci32tlite.vhd | 1 | 15,738 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pci32tLite.vhd |
--| |
--| Components: pcidec.vhd |
--| pciwbsequ.vhd |
--| pcidmux.vhd |
--| pciregs.vhd |
--| pcipargen.vhd |
--| ona.vhd |
--| |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Revision history : |
--| Date Version Author Description |
--| 2005-05-13 R00A00 PAU First alfa revision |
--| |
--| 2006-11-27 R01 PAU * BUG fast back-to-back transactions |
--| * TIMEOUT: Target termination with RETRY |
--| 2007-09-19 R02 PAU * "intb" and "serr" signals not defined as TRI. They have to be |
--| defined Opendrain in the FPGA (externally to the IP Core). |
--| * Small changes due to onalib.vhd improvement. |
--| * Removed TIMEOUT. Added wb_rty_i for Target termination with |
--| RETRY. |
--| * Support Burst Cicles. |
--| * Add Whisbone data bus configuration generics: WBSIZE and |
--| WBENDIAN. |
--| * Add wb_adr_o(1..0) signals. |
--| * wb_dat_i,wb_dat_o,wb_sel_o size depends on WBSIZE. |
--| * Advice: Change WB <-> PCI databus routing for "BIG"/16 WB |
--| configuration and DWORD PCI transactions (DWORD is not |
--| recomended when WB 16 configuration). |
--| 2008-06-16 R03 PAU * Add "1BARIO" configuration option for BARS generic. |
--| * fix bug with WBENDIAN generic in pciwbsequ. |
--| * Change PCI Burts to WB traslation behavior. |
--| * Add "classcode" generic. |
--| * Change BAR0 reset state to "0". |
--| * Fix pcidmux bug for LITTLE/8 configuration. |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005-2008 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pci32tLite is
generic (
vendorID : std_logic_vector(15 downto 0) := x"4150";
deviceID : std_logic_vector(15 downto 0) := x"0001";
revisionID : std_logic_vector(7 downto 0) := x"90";
subsystemID : std_logic_vector(15 downto 0) := x"0000";
subsystemvID : std_logic_vector(15 downto 0) := x"1172";
classcodeID : std_logic_vector(23 downto 0) := x"068000";
-- BAR&WB_CFG (dont delete)
BARS : string := "1BARMEM";
WBSIZE : integer := 16;
WBENDIAN : string := "BIG"
);
port (
-- General
clk33 : in std_logic;
rst : in std_logic;
-- PCI target 32bits
ad_in : in std_logic_vector(31 downto 0);
ad_out : out std_logic_vector(31 downto 0);
ad_oe : out std_logic;
cbe : in std_logic_vector(3 downto 0);
par_in : in std_logic;
par_out : out std_logic;
par_oe : out std_logic;
frame : in std_logic;
irdy : in std_logic;
trdy_out : out std_logic;
devsel_out : out std_logic;
stop_out : out std_logic;
targ_oe : out std_logic;
idsel : in std_logic;
perr_drv : out std_logic;
serr_drv : out std_logic;
inta_drv : out std_logic;
req_drv : out std_logic;
gnt : in std_logic;
-- Master whisbone
wb_adr_o : out std_logic_vector(24 downto 0);
wb_dat_i : in std_logic_vector(WBSIZE-1 downto 0);
wb_dat_o : out std_logic_vector(WBSIZE-1 downto 0);
wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_rty_i : in std_logic;
wb_err_i : in std_logic;
wb_int_i : in std_logic
);
end pci32tLite;
--+-----------------------------------------------------------------------------+
--| ARCHITECTURE |
--+-----------------------------------------------------------------------------+
architecture rtl of pci32tLite is
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal bar0 : std_logic_vector(31 downto 9);
signal memEN : std_logic;
signal ioEN : std_logic;
signal pciadrLD : std_logic;
signal adrcfg : std_logic;
signal adrmem : std_logic;
signal adr : std_logic_vector(24 downto 0);
signal cmd : std_logic_vector(3 downto 0);
signal pcidOE : std_logic;
signal wbdatLD : std_logic;
signal wrcfg : std_logic;
signal rdcfg : std_logic;
signal pcidatread : std_logic_vector(31 downto 0);
signal pcidatwrite : std_logic_vector(31 downto 0);
signal pcidatout : std_logic_vector(31 downto 0);
signal parerr : std_logic;
signal syserr : std_logic;
signal tabort : std_logic;
signal perrEN : std_logic;
signal serrEN : std_logic;
begin
-- ASSERT
assert (BARS = "1BARMEM" or BARS = "1BARIO")
report "ERROR : Bad BAR configuration"
severity Failure;
assert ((WBSIZE = 32 and WBENDIAN = "LITTLE") or (WBSIZE = 16) or (WBSIZE = 8 and WBENDIAN = "LITTLE"))
report "ERROR : Bad WBSIZE/WBENDIAN configuration"
severity Failure;
--+-------------------------------------------------------------------------+
--| Component instances |
--+-------------------------------------------------------------------------+
--+-----------------------------------------+
--| PCI decoder |
--+-----------------------------------------+
u1: entity work.pcidec
generic map (
BARS => BARS
)
port map (
clk_i => clk33,
rst_i => rst,
--
ad_i => ad_in,
cbe_i => cbe,
idsel_i => idsel,
bar0_i => bar0,
memEN_i => memEN,
ioEN_i => ioEN,
pciadrLD_i => pciadrLD,
adrcfg_o => adrcfg,
adrmem_o => adrmem,
adr_o => adr,
cmd_o => cmd
);
--+-----------------------------------------+
--| PCI-WB Sequencer |
--+-----------------------------------------+
u2: entity work.pciwbsequ
generic map (
BARS => BARS,
WBSIZE => WBSIZE,
WBENDIAN => WBENDIAN
)
port map (
-- General
clk_i => clk33,
rst_i => rst,
-- pci
cmd_i => cmd,
cbe_i => cbe,
frame_i => frame,
irdy_i => irdy,
devsel_o => devsel_out,
trdy_o => trdy_out,
stop_o => stop_out,
targ_oe => targ_oe,
-- control
adrcfg_i => adrcfg,
adrmem_i => adrmem,
pciadrLD_o => pciadrLD,
pcidOE_o => pcidOE,
parOE_o => par_oe,
wbdatLD_o => wbdatLD,
wrcfg_o => wrcfg,
rdcfg_o => rdcfg,
-- whisbone
wb_sel_o => wb_sel_o(((WBSIZE/8)-1) downto 0),
wb_we_o => wb_we_o,
wb_stb_o => wb_stb_o,
wb_cyc_o => wb_cyc_o,
wb_ack_i => wb_ack_i,
wb_rty_i => wb_rty_i,
wb_err_i => wb_err_i
);
--+-----------------------------------------+
--| PCI-wb datamultiplexer |
--+-----------------------------------------+
u3: entity work.pcidmux
generic map (
BARS => BARS,
WBSIZE => WBSIZE,
WBENDIAN => WBENDIAN
)
port map (
clk_i => clk33,
rst_i => rst,
--
d_in => ad_in,
d_out => pcidatout,
wbdatLD_i => wbdatLD,
rdcfg_i => rdcfg,
cbe_i => cbe,
wb_dat_i => wb_dat_i((WBSIZE-1) downto 0),
wb_dat_o => wb_dat_o((WBSIZE-1) downto 0),
rg_dat_i => pcidatread,
rg_dat_o => pcidatwrite
);
ad_out <= pcidatout;
ad_oe <= pcidOE;
--+-----------------------------------------+
--| PCI registers |
--+-----------------------------------------+
u4: entity work.pciregs
generic map (
vendorID => vendorID,
deviceID => deviceID,
revisionID => revisionID,
subsystemID => subsystemID,
subsystemvID => subsystemvID,
classcodeID => classcodeID,
BARS => BARS
)
port map (
clk_i => clk33,
rst_i => rst,
--
adr_i => adr(7 downto 2),
cbe_i => cbe,
dat_i => pcidatwrite,
dat_o => pcidatread,
wrcfg_i => wrcfg,
rdcfg_i => rdcfg,
perr_i => parerr,
serr_i => syserr,
tabort_i => tabort,
bar0_o => bar0,
perrEN_o => perrEN,
serrEN_o => serrEN,
memEN_o => memEN,
ioEN_o => ioEN
);
--+-----------------------------------------+
--| PCI Parity Gnerator |
--+-----------------------------------------+
u5: entity work.pcipargen
port map (
clk_i => clk33,
pcidatout_i => pcidatout,
cbe_i => cbe,
par_o => par_out
);
--+-----------------------------------------+
--| Whisbone Address bus |
--+-----------------------------------------+
wb_adr_o <= adr;
--+-----------------------------------------+
--| unimplemented |
--+-----------------------------------------+
parerr <= '0';
syserr <= '0';
tabort <= '0';
--+-----------------------------------------+
--| unused outputs |
--+-----------------------------------------+
perr_drv <= '0';
serr_drv <= '0';
req_drv <= '0';
--+-----------------------------------------+
--| Interrupt |
--+-----------------------------------------+
inta_drv <= wb_int_i;
end rtl;
| gpl-3.0 | b78f23e4af7f504f732f9cfa1124299e | 0.312873 | 5.080052 | false | false | false | false |
alvieboy/xtc-base | xtc_ioctrl.vhd | 1 | 2,197 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
use work.xtcpkg.all;
entity xtc_ioctrl is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
-- Slaves
swbi: in slot_wbi;
swbo: out slot_wbo;
sids: in slot_ids
);
end entity xtc_ioctrl;
architecture behave of xtc_ioctrl is
signal selector: std_logic_vector(15 downto 0);
signal selnum: integer range 0 to 15;
signal ackint: std_logic := '0';
signal trans_valid: std_logic := '1';
signal tagi: std_logic_vector(31 downto 0);
begin
process(wbi.adr)
variable num: integer range 0 to 15;
begin
num := to_integer(unsigned(wbi.adr(30 downto 28)));
selector<=(others => '0');
selector(num)<='1';
selnum<=num;
end process;
direct: if not IO_REGISTER_INPUTS generate
wbo.dat <= swbi(selnum).dat;
ackint <= swbi(selnum).ack;
wbo.err <= swbi(selnum).err;
wbo.tag <= tagi;
end generate;
indirect: if IO_REGISTER_INPUTS generate
trans_valid<='1' when ackint='0' else '0';
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
wbo.dat <= (others => 'X');
ackint <= '0';
wbo.err <= '0';
wbo.tag <= (others => 'X');
else
wbo.dat <= swbi(selnum).dat;
ackint <= swbi(selnum).ack;
wbo.err <= swbi(selnum).err;
wbo.tag <= tagi;
end if;
end if;
end process;
end generate;
wbo.stall <= '0';
wbo.ack <= ackint;
-- Simple tag generator. Also resynchronizer
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
--if syscon.rst='1' then
-- wbo.tag <= (others => '0');
--else
tagi <= wbi.tag;
--end if;
end if;
end process;
slavegen: for i in 0 to 15 generate
swbo(i).adr <= wbi.adr;
swbo(i).dat <= wbi.dat;
swbo(i).we <= wbi.we;
--swbo(i).tag <= wbi.tag;
swbo(i).cyc <= wbi.cyc and selector(i) and trans_valid;
swbo(i).stb <= wbi.stb and selector(i) and trans_valid;
end generate;
end behave;
| bsd-3-clause | c7acd299969b46be63e935646a6f08ea | 0.577606 | 3.120739 | false | false | false | false |
lerwys/hdl-make2 | test/top_module.vhd | 1 | 1,925 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
entity top_module is
port(
clk_i : in std_logic;
locked_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
-- Constant declaration
constant c_blink_num_pins : natural := 8;
constant c_counter_width : natural := 4;
-- Global clock and reset signals
--signal s_locked : std_logic;
signal clk_sys_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- Global Clock Single ended
signal clk_sys : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
constant s_counter_full : integer := 4;
signal s_blink : std_logic_vector(c_blink_num_pins-1 downto 0);
begin
-- Reset synchronization
cmp_reset : gc_reset
generic map(
g_logdelay => 1,
g_syncdepth => 2
)
port map(
free_clk_i => clk_sys,
locked_i => locked_i,
clks_i => reset_clks,
rstn_o => reset_rstn
);
-- Simulation only
clk_sys <= clk_i;
-- End of simulation only!
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0);
p_counter : process (clk_sys)
begin
if rising_edge(clk_sys) then
if clk_sys_rstn = '0' then
s_counter <= (others => '0');
s_blink <= x"01";
else
if (s_counter = s_counter_full-1) then
s_counter <= (others => '0');
s_blink <= s_blink(c_blink_num_pins-2 downto 0) & s_blink(c_blink_num_pins-1);
else
s_counter <= s_counter + 1;
end if;
end if;
end if;
end process;
blink_o <= s_blink;
end rtl;
| gpl-2.0 | f16900e83fbe575a51fc54e129e9bbe5 | 0.564156 | 2.934451 | false | false | false | false |
alvieboy/xtc-base | mmu.vhd | 1 | 4,020 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity mmu is
generic (
TLB_ENTRY_BITS: natural := 3;
CONTEXT_SIZE_BITS: natural := 1;
SIMPLIFIED: boolean := true
);
port (
clk: in std_logic;
rst: in std_logic;
addr: in std_logic_vector(31 downto 0);
ctx: in std_logic_vector(CONTEXT_SIZE_BITS-1 downto 0);
en: in std_logic;
tlbw: in std_logic;
tlba: in std_logic_vector(TLB_ENTRY_BITS-1 downto 0);
tlbv: in tlb_entry_type;
paddr: out std_logic_vector(31 downto 0);
valid: out std_logic;
pw: out std_logic; -- Write permission
pr: out std_logic; -- Read permission
px: out std_logic; -- eXecute permission
ps: out std_logic -- Supervisor/User
);
end entity mmu;
architecture behave of mmu is
constant TLB_ENTRIES: integer := 2**TLB_ENTRY_BITS;
constant PAGE_4K: std_logic_vector(1 downto 0) := "00";
constant PAGE_256K: std_logic_vector(1 downto 0) := "01";
constant PAGE_1M: std_logic_vector(1 downto 0) := "10";
constant PAGE_16M: std_logic_vector(1 downto 0) := "11";
signal tlbmatch: std_logic_vector(TLB_ENTRIES-1 downto 0);
type tlb_array_type is array(TLB_ENTRIES-1 downto 0) of tlb_entry_type;
signal tlb: tlb_array_type;
subtype physaddr_t is std_logic_vector(31 downto 0);
type physaddr_a is array(TLB_ENTRIES-1 downto 0) of physaddr_t;
signal physaddr: physaddr_a;
begin
-- Match signals
tlbe: for n in 0 to TLB_ENTRIES-1 generate
process(tlb(n), addr, ctx)
variable match_4k, match_256k, match_1m, match_16m, match_ctx: std_logic;
variable e: tlb_entry_type;
begin
e:=tlb(n);
match_4k :='0';
match_256k :='0';
match_16m :='0';
match_1m :='0';
match_ctx :='0';
physaddr(n) <= (others => 'X');
if (e.ctx=ctx) then
match_ctx:='1';
end if;
if (e.vaddr(17 downto 12) = addr(17 downto 12)) then
match_4k := '1';
end if;
if SIMPLIFIED then
match_1m := '1';
match_16m := '1';
match_256k := '1';
else
if (e.vaddr(19 downto 18) = addr(19 downto 18)) then
match_256k := '1';
end if;
if (e.vaddr(23 downto 20) = addr(23 downto 20)) then
match_1m := '1';
end if;
if (e.vaddr(31 downto 24) = addr(31 downto 24)) then
match_16m := '1';
end if;
end if;
if SIMPLIFIED then
tlbmatch(n) <= match_ctx and match_16m and match_1m and match_256k and match_4k;
physaddr(n) <= e.paddr(31 downto 12) & addr(11 downto 0);
else
case (e.pagesize) is
when PAGE_4K =>
tlbmatch(n) <= match_ctx and match_16m and match_1m and match_256k and match_4k;
physaddr(n) <= e.paddr(31 downto 12) & addr(11 downto 0);
when PAGE_256K =>
tlbmatch(n) <= match_ctx and match_16m and match_1m and match_256k;
physaddr(n) <= e.paddr(31 downto 18) & addr(17 downto 0);
when PAGE_1M =>
tlbmatch(n) <= match_ctx and match_16m and match_1m;
physaddr(n) <= e.paddr(31 downto 20) & addr(19 downto 0);
when PAGE_16M =>
tlbmatch(n) <= match_ctx and match_16m;
physaddr(n) <= e.paddr(31 downto 24) & addr(23 downto 0);
when others =>
tlbmatch(n) <= '0';
end case;
end if;
end process;
end generate;
process(clk)
variable valid_i: std_logic;
begin
if rising_edge(clk) then
valid_i:='0';
if en='1' then
for i in 0 to TLB_ENTRIES-1 loop
if tlbmatch(i)='1' then
paddr <= physaddr(i);
valid_i:='1';
end if;
end loop;
valid<=valid_i;
end if;
if tlbw='1' then
tlb(to_integer(unsigned(tlba)))<=tlbv;
end if;
end if;
end process;
end behave;
| bsd-3-clause | c2df0e0b832d49b4a71c5876b951099c | 0.559204 | 3.177866 | false | false | false | false |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/main.vhd | 1 | 9,121 | -- Copyright 2018 Google LLC
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpu_socket_fpga is
port (
c1_1 : inout std_logic;
c1_2 : inout std_logic;
c1_3 : inout std_logic;
c1_5 : inout std_logic;
c1_6 : inout std_logic;
c1_7 : inout std_logic;
c1_9 : inout std_logic;
c1_10 : inout std_logic;
c1_11 : inout std_logic;
c1_12 : inout std_logic;
c1_13 : inout std_logic;
c1_14 : inout std_logic;
c1_16 : inout std_logic;
c1_17 : inout std_logic;
c1_18 : in std_logic; -- ext_GP6
c1_19 : inout std_logic; -- BAD
c1_20 : in std_logic; -- ext_GP0
c1_22 : in std_logic; -- ext_GP8
c1_23 : in std_logic; -- ext_GP2
c1_24 : out std_logic; -- ext_GP1
c1_25 : in std_logic; -- ext_GP10
c1_26 : in std_logic; -- ext_GP7
c1_27 : out std_logic; -- ext_GP4
c1_28 : out std_logic; -- ext_GP3
c1_29 : out std_logic; -- ext_GP11
c1_30 : in std_logic; -- ext_GP9
c1_31 : out std_logic; -- ext_GP5
c1_33 : inout std_logic; -- ext_D2
c1_34 : inout std_logic; -- ext_D0
c1_36 : in std_logic; -- ext_GP12
c1_37 : inout std_logic; -- ext_D3
c1_38 : inout std_logic; -- ext_D1
c2_1 : inout std_logic;
c2_3 : inout std_logic;
c2_4 : inout std_logic;
c2_5 : inout std_logic;
c2_8 : inout std_logic;
c2_12 : inout std_logic;
c3_1 : inout std_logic; -- ext_D4
c3_2_CLK3n : inout std_logic; -- ext_D5
c3_3 : inout std_logic; -- ext_D6
c3_4 : inout std_logic; -- ext_D7
c3_5_CLK3p : in std_logic; -- ext_A0
c3_6 : in std_logic; -- ext_A1
c3_7 : in std_logic; -- ext_A2
c3_8 : in std_logic; -- ext_A3
c3_9 : in std_logic; -- ext_A4
c3_10 : in std_logic; -- ext_A5
c3_11 : in std_logic; -- ext_A6
c3_12 : in std_logic; -- ext_A7
c4_3_VREFB2N0 : inout std_logic;
c4_4 : inout std_logic;
c4_6 : inout std_logic;
c4_7 : inout std_logic;
c4_8 : inout std_logic;
c4_10 : inout std_logic;
c4_11 : inout std_logic;
c4_12 : inout std_logic;
c4_13 : inout std_logic;
c4_14 : inout std_logic;
c4_15_DPCLK1 : inout std_logic;
c4_16_DPCLK0 : inout std_logic;
c4_17 : inout std_logic;
c4_18 : inout std_logic;
c4_19 : inout std_logic;
c4_20 : inout std_logic;
c4_21 : inout std_logic;
c4_22 : inout std_logic;
c4_23 : inout std_logic;
c4_24 : inout std_logic;
c4_25 : inout std_logic;
c4_26 : inout std_logic;
c4_27 : inout std_logic;
c4_28 : out std_logic; -- ext_uart_txd (plug in white cable from Adafruit adapter)
c4_30 : inout std_logic;
c4_31 : inout std_logic; -- ext_A11 on first try board, which has bad c4_39
c4_32 : in std_logic; -- ext_uart_rxd (plug in green cable from Adafruit adapter)
c4_33 : in std_logic; -- ext_A14
c4_34 : in std_logic; -- ext_A12
c4_35 : in std_logic; -- ext_A10
c4_36 : in std_logic; -- ext_A8
c4_37 : in std_logic; -- ext_A15
c4_38 : in std_logic; -- ext_A13
c4_39 : in std_logic; -- ext_A11, bad on first try board
c4_40 : in std_logic -- ext_A9
);
end cpu_socket_fpga;
architecture rtl of cpu_socket_fpga is
component main_to_elk is
port (
debug_uart_txd : out std_logic;
debug_a : out std_logic;
debug_b : out std_logic;
ext_uart_rxd : in std_logic;
ext_uart_txd : out std_logic;
fast_clock : in std_logic; -- pass through for FPGA's internal flash
-- connections to the cpu_socket_expansion board
ext_A : in std_logic_vector(15 downto 0);
ext_D : inout std_logic_vector(7 downto 0);
ext_GP0 : in std_logic; -- PHI2
ext_GP1 : out std_logic; -- n_global_enable
ext_GP2 : in std_logic; -- 16MHz
ext_GP3 : out std_logic; -- dbuf_nOE
ext_GP4 : out std_logic; -- n_accessing_shadow_ram
ext_GP5 : out std_logic; -- n_cpu_is_external
ext_GP6 : in std_logic; -- RnW
ext_GP7 : in std_logic; -- nRESET
ext_GP8 : in std_logic; -- READY
ext_GP9 : in std_logic; -- /NMI
ext_GP10 : in std_logic; -- /IRQ
ext_GP11 : out std_logic; -- dbuf_driven_by_cpu
ext_GP12 : in std_logic
);
end component;
component internal_osc is
port (
clkout : out std_logic; -- clkout.clk
oscena : in std_logic := '0' -- oscena.oscena
);
end component;
signal clk : std_logic; -- 55-115MHz clock from internal oscillator
signal clk_div_count : std_logic_vector(26 downto 0) := (others => '0');
signal slow_clk : std_logic; -- clk/(128*1024*1024), 0.4-0.85 Hz
begin
elk0: component main_to_elk port map (
debug_uart_txd => c2_1,
debug_a => c2_3,
debug_b => c2_5,
ext_uart_txd => c4_28,
ext_uart_rxd => c4_32,
fast_clock => clk,
-- fast_clock => clk_div_count(0),
ext_A(0) => c3_5_CLK3p,
ext_A(1) => c3_6,
ext_A(2) => c3_7,
ext_A(3) => c3_8,
ext_A(4) => c3_9,
ext_A(5) => c3_10,
ext_A(6) => c3_11,
ext_A(7) => c3_12,
ext_A(8) => c4_36,
ext_A(9) => c4_40,
ext_A(10) => c4_35,
ext_A(11) => c4_39, -- c4_31 on first try board, c4_39 on second
ext_A(12) => c4_34,
ext_A(13) => c4_38,
ext_A(14) => c4_33,
ext_A(15) => c4_37,
ext_D(0) => c1_34,
ext_D(1) => c1_38,
ext_D(2) => c1_33,
ext_D(3) => c1_37,
ext_D(4) => c3_1,
ext_D(5) => c3_2_CLK3n,
ext_D(6) => c3_3,
ext_D(7) => c3_4,
ext_GP0 => c1_20,
ext_GP1 => c1_24,
ext_GP2 => c1_23,
ext_GP3 => c1_28,
ext_GP4 => c1_27,
ext_GP5 => c1_31,
ext_GP6 => c1_18,
ext_GP7 => c1_26,
ext_GP8 => c1_22,
ext_GP9 => c1_30,
ext_GP10 => c1_25,
ext_GP11 => c1_29,
ext_GP12 => c1_36
);
-- Max 10 internal oscillator
int_osc_0 : component internal_osc port map (
oscena => '1',
clkout => clk
);
-- Divide clock down to ~1Hz
process (clk)
begin
if rising_edge(clk) then
clk_div_count <= std_logic_vector(unsigned(clk_div_count) + 1);
if unsigned(clk_div_count) = 0 then
slow_clk <= not slow_clk;
end if;
end if;
end process;
-- Output 1Hz clock on all unused pins
c1_1 <= slow_clk;
c1_2 <= 'Z'; -- poor solder connection, tristate so we can patch
c1_3 <= slow_clk;
c1_5 <= slow_clk;
c1_6 <= slow_clk;
c1_7 <= slow_clk;
c1_9 <= slow_clk;
c1_10 <= slow_clk;
c1_11 <= slow_clk;
c1_12 <= slow_clk;
c1_13 <= slow_clk;
c1_14 <= slow_clk;
c1_16 <= slow_clk;
c1_17 <= slow_clk;
-- c1_18 <= slow_clk;
c1_19 <= 'Z'; -- poor solder connection, tristate so we can patch
-- c1_20 <= slow_clk;
-- c1_22 <= slow_clk;
-- c1_23 <= slow_clk;
-- c1_24 <= slow_clk;
-- c1_25 <= slow_clk;
-- c1_26 <= slow_clk;
-- c1_27 <= slow_clk;
-- c1_28 <= slow_clk;
-- c1_29 <= slow_clk;
-- c1_30 <= slow_clk;
-- c1_31 <= slow_clk;
-- c1_33 <= slow_clk;
-- c1_34 <= slow_clk;
-- c1_36 <= slow_clk;
-- c1_37 <= slow_clk;
-- c1_38 <= slow_clk;
-- c2_1 <= slow_clk; -- debug uart tx
-- c2_3 <= slow_clk; -- debug a
c2_4 <= slow_clk;
-- c2_5 <= slow_clk; -- debug b
c2_8 <= slow_clk;
c2_12 <= slow_clk;
-- c3_1 <= slow_clk;
-- c3_2_CLK3n <= slow_clk;
-- c3_3 <= slow_clk;
-- c3_4 <= slow_clk;
-- c3_5_CLK3p <= slow_clk;
-- c3_6 <= slow_clk;
-- c3_7 <= slow_clk;
-- c3_8 <= slow_clk;
-- c3_9 <= slow_clk;
-- c3_10 <= slow_clk;
-- c3_11 <= slow_clk;
-- c3_12 <= slow_clk;
c4_3_VREFB2N0 <= slow_clk;
c4_4 <= slow_clk;
c4_6 <= slow_clk;
c4_7 <= slow_clk;
c4_8 <= slow_clk;
c4_10 <= slow_clk;
c4_11 <= slow_clk;
c4_12 <= slow_clk;
c4_13 <= slow_clk;
c4_14 <= slow_clk;
c4_15_DPCLK1 <= slow_clk;
c4_16_DPCLK0 <= slow_clk;
c4_17 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_18 <= slow_clk;
c4_19 <= slow_clk;
c4_20 <= slow_clk;
c4_21 <= slow_clk;
c4_22 <= slow_clk;
c4_23 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_24 <= slow_clk;
c4_25 <= slow_clk;
c4_26 <= slow_clk;
c4_27 <= slow_clk;
-- c4_28 <= 'Z'; -- poor solder connection, tristate so we can patch
c4_30 <= slow_clk;
c4_31 <= 'Z'; -- patched over c4_39 on first try board; leaving Z in case i program the old board by mistake
-- c4_32 <= slow_clk;
-- c4_33 <= slow_clk;
-- c4_34 <= slow_clk;
-- c4_35 <= slow_clk;
-- c4_36 <= slow_clk;
-- c4_37 <= slow_clk;
-- c4_38 <= slow_clk;
-- c4_39 <= 'Z'; -- poor solder connection on try 1 board, tristated so we can patch
-- c4_40 <= slow_clk;
end rtl;
| apache-2.0 | 2114f276220ba74ae88a100ca16d86e9 | 0.563535 | 2.509216 | false | false | false | false |
alvieboy/xtc-base | nodev.vhd | 1 | 739 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity nodev is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type
);
end entity nodev;
architecture behave of nodev is
signal ack,err: std_logic := '0';
begin
wbo.ack<=ack;
wbo.err<=err;
wbo.dat<=(others => 'X');
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
ack<='0';
err<='0';
else
ack<='0';
err<='0';
if err='0' and wbi.stb='1' and wbi.cyc='1' then
--ack<='1';
err<='1';
end if;
end if;
end if;
end process;
end behave;
| bsd-3-clause | 1c8df85e9e7402baa336daccbbd49a71 | 0.548038 | 3.118143 | false | false | false | false |
alvieboy/xtc-base | romram.vhd | 1 | 3,913 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_tag_o: out std_logic_vector(31 downto 0);
ram_wb_tag_i: in std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
ram_wb_sel_i: in std_logic_vector(3 downto 0);
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_tag_i: in std_logic_vector(31 downto 0);
rom_wb_tag_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity romram;
architecture behave of romram is
component internalram is
port (
CLKA: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(BITS-1 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
CLKB: in std_logic;
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(BITS-1 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end component;
signal rom_enable: std_logic;
signal ram_enable: std_logic;
signal romack, ramack: std_logic;
constant nothing: std_logic_vector(31 downto 0) := (others => '0');
signal rom_data: std_logic_vector(31 downto 0);
begin
rom_enable <= rom_wb_stb_i and rom_wb_cyc_i;
ram_enable <= ram_wb_stb_i and ram_wb_cyc_i;
rom_wb_stall_o <= '0';
ram_wb_stall_o <= '0';
rom_wb_ack_o <= romack;
ram_wb_ack_o <= ramack;
-- ACK processing (pipelined)
cache: if INSTRUCTION_CACHE generate
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
romack <= '0';
else
--if rom_enable='1' then
romack <= rom_enable;
if rom_enable='1' then
rom_wb_tag_o <= rom_wb_tag_i;
end if;
--end if;
end if;
end if;
end process;
end generate;
nocache: if not INSTRUCTION_CACHE generate
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
romack <= '0';
else
romack <= '1';
rom_wb_tag_o <= rom_wb_tag_i;
end if;
end if;
end process;
end generate;
-- ACK processing (pipelined)
process(ram_wb_clk_i)
begin
if rising_edge(ram_wb_clk_i) then
if ram_wb_rst_i='1' then
ramack <= '0';
else
ramack <= ram_enable;
if ram_enable='1' then
ram_wb_tag_o <= ram_wb_tag_i;
end if;
end if;
end if;
end process;
rom_wb_dat_o <= rom_data;
ram: internalram
port map (
CLKA => rom_wb_clk_i,
CLKB => ram_wb_clk_i,
WEA => '0',
ENA => rom_enable,
MASKA => "1111",
ADDRA => rom_wb_adr_i(BITS-1 downto 2),
DIA => nothing,
DOA => rom_data,
WEB => ram_wb_we_i,
ENB => ram_enable,
ADDRB => ram_wb_adr_i(BITS-1 downto 2),
DIB => ram_wb_dat_i,
MASKB => ram_wb_sel_i,
DOB => ram_wb_dat_o
);
end behave;
| bsd-3-clause | dd09d84de00d7d711f1d745432a4c9c2 | 0.559162 | 2.875092 | false | false | false | false |
EPiCS/reconos | pcores/reconos_hwt_idle_v1_00_a/hdl/vhdl/reconos_hwt_idle.vhd | 2 | 1,657 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity reconos_hwt_idle is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end entity reconos_hwt_idle;
architecture implementation of reconos_hwt_idle is
begin
OSIF_FIFO_Sw2Hw_RE <= '0';
OSIF_FIFO_Hw2Sw_WE <= '0';
OSIF_FIFO_Hw2Sw_Data <= (others => '0');
MEMIF_FIFO_Mem2Hwt_RE <= '0';
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
end architecture;
| gpl-2.0 | f977a8614f98c2b35f121c317b90421f | 0.658419 | 2.585023 | false | false | false | false |
keith-epidev/md2x | build/code/n_add_sub.vhdl | 1 | 859 | library ieee;
use ieee.std_logic_1164.all;
entity N_add_sub is
generic(
size:integer := 8
);
port (
A,B : in std_logic_vector(size-1 downto 0);
Cin : in std_logic;
mode : in std_logic;
sum : out std_logic_vector(size-1 downto 0);
Cout : out std_logic
);
end N_add_sub;
architecture arch of N_add_sub is
signal C : std_logic_vector (size downto 0);
signal A_val, B_val: std_logic_vector (size-1 downto 0);
component FULL_ADDER
port (
A,B,Cin : in std_logic;
sum,CARRY : out std_logic
);
end component;
begin
-- mode
-- 0 add
-- 1 sub
C(0) <= Cin when mode = '0' else
'1' when Cin = '0' else
'0';
A_val <= A;
B_val <= B when mode='0' else
not B;
Cout <= C(size);
GEN_REG: for I in 0 to size-1 generate
UX : FULL_ADDER port map (A_val(I), B_val(I), C(I), sum(I), C(I+1));
end generate GEN_REG;
end arch;
| gpl-2.0 | e0025ffae9b7067fdfd08a3d10c1c339 | 0.61234 | 2.447293 | false | false | false | false |
alvieboy/xtc-base | spirom.vhd | 1 | 5,157 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbonepkg.all;
entity spirom is
port (
syscon: in wb_syscon_type;
wbi: in wb_mosi_type;
wbo: out wb_miso_type;
mosi: out std_logic;
miso: in std_logic;
sck: out std_logic;
ncs: out std_logic
);
end entity spirom;
architecture behave of spirom is
type state_type is (
idle,
chipsel,
reselect,
clock,
transfer,
read,
chipdesel
);
constant CSDLYMAX: integer := 8;
constant BASEADDR: unsigned(23 downto 0) := x"000000";
constant PRESCALEVAL: unsigned(3 downto 0) := "0001";
type regs_type is record
state: state_type;
ack: std_logic;
sel: std_logic;
nextaddr: unsigned(21 downto 0);
csdly: integer range 0 to CSDLYMAX;
end record;
signal r: regs_type;
signal shreg: std_logic_vector(31 downto 0);
signal shbusy: std_logic;
signal size: std_logic_vector(1 downto 0);
signal loaden: std_logic;
signal load: std_logic_vector(31 downto 0);
begin
ncs<=r.sel;
wbo.ack<=r.ack;
wbo.dat<=shreg;
process(r,wbi,syscon)
variable w: regs_type;
variable laddr: unsigned(21 downto 0);
begin
w:=r;
w.ack:='0';
loaden<='0';
load<=(others => 'X');
size<=(others => 'X');
case r.state is
when idle =>
if wbi.cyc='1' and wbi.stb='1' and r.ack='0' then
if wbi.we='1' then
-- Ignore writes;
w.ack:='1';
else
if r.sel='0' then
if r.nextaddr=unsigned(wbi.adr(23 downto 2)) then
-- dly must be zero
w.state := transfer;
w.sel:='0'; -- already
else
-- Need deselect.
w.sel:='1';
w.state := reselect;
w.csdly := CSDLYMAX;
end if;
else
w.state := chipsel;
w.sel :='0';
w.csdly := CSDLYMAX;
end if;
end if;
end if;
when reselect =>
if r.csdly=0 then
w.state := chipsel;
w.csdly := CSDLYMAX;
w.sel:='0';
else
w.csdly:=w.csdly-1;
end if;
when chipsel =>
if r.csdly=0 then
if shbusy='0' then
w.state := clock;
end if;
loaden <='1';
load(31 downto 24) <= x"0b"; -- READ_FAST
load(23 downto 2) <= wbi.adr(23 downto 2);
load(1 downto 0)<="00";
size <="11";
else
w.csdly:=w.csdly-1;
end if;
when clock =>
if shbusy='0' then
w.state := transfer;
end if;
loaden<='1';
size<="00";
when transfer =>
if shbusy='0' then
w.state := read;
end if;
laddr:=unsigned(wbi.adr(23 downto 2));
w.nextaddr := laddr+1;
loaden<='1';
size<="11";
when read =>
if shbusy='0' then
-- We got data.
w.ack:='1';
w.state:=idle;
end if;
when others =>
end case;
if syscon.rst='1' then
w.ack := '0';
w.sel := '1';
w.state:=idle;
end if;
if rising_edge(syscon.clk) then
r<=w;
end if;
end process;
shifter: block
signal cnt: integer range 0 to 31;
signal prescale: unsigned(3 downto 0);
type shstate_type is (idle, clock0, clock1);
signal state: shstate_type;
begin
process(syscon.clk)
begin
if rising_edge(syscon.clk) then
if syscon.rst='1' then
state <= idle;
sck <= '1';
shbusy<='0';
else
case state is
when idle =>
if loaden='1' then
shreg<=load;
shbusy<='1';
prescale <= PRESCALEVAL;
state <= clock0;
case size is
when "00" => cnt<=7;
when "01" => cnt<=15;
when "10" => cnt<=23;
when "11" => cnt<=31;
when others =>
end case;
sck <= '1';
end if;
when clock0 =>
if prescale=0 then
prescale <= PRESCALEVAL;
sck<='0';
state <=clock1;
mosi<=shreg(31);
-- Sample ?
else
prescale<=prescale-1;
end if;
when clock1 =>
if prescale=0 then
prescale <= PRESCALEVAL;
sck<='1';
shreg(31 downto 0)<=shreg(30 downto 0) & miso;
if cnt=0 then
-- If load is present, do it.
shbusy<='0';
state <=idle;
else
cnt<=cnt-1;
state <= clock0;
end if;
else
prescale<=prescale-1;
end if;
end case;
end if;
end if;
end process;
end block;
end behave;
| bsd-3-clause | 64e6bd32783073bc6bcaffda9edd0eb1 | 0.452395 | 3.86003 | false | false | false | false |
alvieboy/xtc-base | uart_pty_tx.vhd | 1 | 2,061 | library IEEE;
use IEEE.std_logic_1164.all;
use work.pty.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
entity uart_pty_tx is
port(
clk: in std_logic;
rst: in std_logic;
tx: out std_logic
);
end entity uart_pty_tx;
architecture sim of uart_pty_tx is
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component uart_brgen is
port (
clk: in std_logic;
rst: in std_logic;
en: in std_logic;
count: in std_logic_vector(15 downto 0);
clkout: out std_logic
);
end component uart_brgen;
signal rxclk,txclk: std_logic;
signal load_data: std_logic;
signal busy: std_logic;
signal data: std_logic_vector(7 downto 0);
begin
rxclkgen: uart_brgen
port map (
clk => clk,
rst => rst,
en => '1',
count => x"0005", -- 1Mbps
clkout => rxclk
);
txclkgen: uart_brgen
port map (
clk => clk,
rst => rst,
en => rxclk,
count => x"000f",
clkout => txclk
);
txu: TxUnit
port map (
clk_i => clk,
reset_i => rst,
enable_i => txclk,
load_i => load_data,
txd_o => tx,
busy_o => busy,
datai_i => data
);
process(clk)
begin
if rising_edge(clk) then
if rst='1' then
load_data<='1';
else
load_data<='0';
if busy='0' then
if pty_available > 0 then
data <= conv_std_logic_vector(pty_receive,8);
load_data<='1';
end if;
end if;
end if;
end if;
end process;
process
variable c: integer;
begin
c := pty_initialize;
wait;
end process;
end sim;
| bsd-3-clause | 7d34c46fff378998f2a981aebf107162 | 0.536148 | 3.235479 | false | false | false | false |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/bd/base_zynq_design/hdl/base_zynq_design_wrapper.vhd | 1 | 3,914 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Wed Aug 26 21:30:37 2015
--Host : localhost.localdomain running 64-bit CentOS release 6.7 (Final)
--Command : generate_target base_zynq_design_wrapper.bd
--Design : base_zynq_design_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity base_zynq_design_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end base_zynq_design_wrapper;
architecture STRUCTURE of base_zynq_design_wrapper is
component base_zynq_design is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
leds_8bits_tri_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end component base_zynq_design;
begin
base_zynq_design_i: component base_zynq_design
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
btns_5bits_tri_i(4 downto 0) => btns_5bits_tri_i(4 downto 0),
leds_8bits_tri_o(7 downto 0) => leds_8bits_tri_o(7 downto 0)
);
end STRUCTURE;
| gpl-3.0 | d5132c049e2902bdad931e0bdfe2f536 | 0.59862 | 3.031758 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.