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EPiCS/soundgates | hardware/hwt/pcores/hwt_nco_v1_00_a/hdl/vhdl/hwt_nco.vhd | 1 | 13,602 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_nco
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Hardware thread for a numeric controlled oscillator
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_nco is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NCO_TPYE : integer := 0
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_nco;
architecture Behavioral of hwt_nco is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component nco is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SIN
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end component nco;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 1024;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 10;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_nco : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_nco : std_logic_vector(0 to 31); -- nco to local ram
signal i_RAMData_nco : std_logic_vector(0 to 31); -- local ram to nco
signal o_RAMWE_nco : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal nco_ce : std_logic; -- nco clock enable (like a start/stop signal)
signal phase_offset_addr : std_logic_vector(31 downto 0);
signal phase_incr_addr : std_logic_vector(31 downto 0);
signal phase_offset : std_logic_vector(31 downto 0);
signal phase_incr : std_logic_vector(31 downto 0);
signal nco_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant NCO_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NCO_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_nco <= std_logic_vector(nco_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
nco_inst : nco
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ,
WAVEFORM => WAVEFORM_TYPE'val(SND_COMP_NCO_TPYE)
)
port map(
clk => clk,
rst => rst,
ce => nco_ce,
phase_offset => signed(phase_offset),
phase_incr => signed(phase_incr),
data => nco_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_nco = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco))) := o_RAMData_nco;
--else -- else not needed, because nco is not consuming any samples
-- i_RAMData_nco <= local_ram(conv_integer(unsigned(o_RAMAddr_nco)));
end if;
end if;
end process;
NCO_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
nco_ce <= '0';
o_RAMWE_nco <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
nco_ce <= '0';
o_RAMWE_nco <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
phase_offset_addr <= snd_comp_header.opt_arg_addr;
phase_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = NCO_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = NCO_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, phase_offset_addr, phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_PHASE_INCR =>
memif_read_word(i_memif, o_memif, phase_incr_addr, phase_incr, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_nco <= '1';
nco_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_nco <= std_logic_vector(unsigned(o_RAMAddr_nco) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_nco <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 575442a70880f3377659c92fd9477996 | 0.488861 | 3.705995 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Decode_Buffer.vhd | 1 | 3,233 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Decode_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
R1_in: in std_logic_vector(15 downto 0 ); --addres of reg1
R2_in: in std_logic_vector(15 downto 0 ); --addres of reg2
Rout_in: in std_logic_vector(2 downto 0 ); --for write back
R1_out: out std_logic_vector(15 downto 0 ); --addres of reg1
R2_out: out std_logic_vector(15 downto 0 ); --addres of reg2
Rout_out: out std_logic_vector(2 downto 0 ); --for write back
R_shift_in:in std_logic_vector(3 downto 0 );
R_shift_out:out std_logic_vector(3 downto 0 );
OPcode_in: in std_logic_vector(4 downto 0 );
OPcode_out: out std_logic_vector(4 downto 0 );
R1_address_in,R2_address_in: in std_logic_vector(2 downto 0 );
R1_address_out,R2_address_out: out std_logic_vector(2 downto 0 );
pc_mux_input : in std_logic_vector(1 downto 0);
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
int_flags_en_input : in std_logic; -- int to take flags from meomry to alu
alu_control_input : in std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
mem_mux_input : in std_logic;
pc_mux_output : out std_logic_vector(1 downto 0);
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
-- to know if make shift or not
write_back_mux_output : out std_logic_vector(1 downto 0);
int_flags_en_output : out std_logic; -- int to take flags from meomry to alu
alu_control_output : out std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
mem_mux_output : out std_logic;
Stack_WriteEnable_input, StackPushPop_signal_input : in std_logic;
Stack_WriteEnable_output, StackPushPop_output : out std_logic
);
end Decode_Buffer;
architecture Decode_Buffer_arch of Decode_Buffer is
begin
--call control unit
process(clk) is
begin
if (rising_edge(clk)) then
R1_out<=R1_in;
R2_out<=R2_in;
OPcode_out<=OPcode_in;
Rout_out<=Rout_in;
R_shift_out<=R_shift_in;
R1_address_out<=R1_address_in;
R2_address_out<=R2_address_in;
pc_mux_output <= pc_mux_input;
outport_en_output <=outport_en_input;
reg_write_output <=reg_write_input;
mem_write_output <= mem_write_input;
write_data_reg_mux_output <= write_data_reg_mux_input;
write_back_mux_output <= write_back_mux_input;
int_flags_en_output <= int_flags_en_input; -- int to take flags from meomry to alu
alu_control_output <= alu_control_input; --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
mem_mux_output <= mem_mux_input;
end if;
end process;
end Decode_Buffer_arch;
| mit | daffe6af27b0b644769a0c66be28b0ed | 0.610888 | 3.018674 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_package.vhd | 1 | 11,379 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver component package. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.8 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.7 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.6 2004/06/23 18:10:17 gedra
-- Added Wishbone bus cycle decoder.
--
-- Revision 1.5 2004/06/16 19:03:45 gedra
-- Changed status reg. declaration
--
-- Revision 1.4 2004/06/13 18:08:09 gedra
-- Added frame decoder and sample extractor
--
-- Revision 1.3 2004/06/10 18:57:36 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2 2004/06/09 19:24:50 gedra
-- Added dual port ram.
--
-- Revision 1.1 2004/06/07 18:06:00 gedra
-- Receiver component declarations.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
package rx_package is
-- type declarations
type bus_array is array (0 to 7) of std_logic_vector(31 downto 0);
-- components
component rx_ver_reg
generic (DATA_WIDTH: integer := 32;
ADDR_WIDTH: integer := 8;
CH_ST_CAPTURE: integer := 1);
port (
ver_rd: in std_logic; -- version register read
ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data
end component;
component gen_control_reg
generic (DATA_WIDTH: integer;
-- note that this vector is (0 to xx), reverse order
ACTIVE_BIT_MASK: std_logic_vector);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
ctrl_wr: in std_logic; -- control register write
ctrl_rd: in std_logic; -- control register read
ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0);
ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
component rx_status_reg
generic (DATA_WIDTH: integer := 32);
port (
up_clk: in std_logic; -- clock
status_rd: in std_logic; -- status register read
lock: in std_logic; -- signal lock status
chas: in std_logic; -- channel A or B select
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
component gen_event_reg
generic (DATA_WIDTH: integer := 32);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
evt_wr: in std_logic; -- event register write
evt_rd: in std_logic; -- event register read
evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
evt_en: in std_logic; -- irq enable
evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
evt_irq: out std_logic); -- interrupt request
end component;
component rx_cap_reg
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
--cap_ctrl_wr: in std_logic; -- control register write
--cap_ctrl_rd: in std_logic; -- control register read
--cap_data_rd: in std_logic; -- data register read
cap_reg: in std_logic_vector(31 downto 0);
cap_din: in std_logic_vector(31 downto 0); -- write data
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
ud_a_en: in std_logic; -- user data ch. A enable
ud_b_en: in std_logic; -- user data ch. B enable
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
cap_dout: out std_logic_vector(31 downto 0); -- read data
cap_evt: out std_logic); -- capture event (interrupt)
end component;
component rx_phase_det
generic (AXI_FREQ: natural := 33); -- WishBone frequency in MHz
port (
up_clk: in std_logic;
rxen: in std_logic;
spdif: in std_logic;
lock: out std_logic;
lock_evt: out std_logic; -- lock status change event
rx_data: out std_logic;
rx_data_en: out std_logic;
rx_block_start: out std_logic;
rx_frame_start: out std_logic;
rx_channel_a: out std_logic;
rx_error: out std_logic;
ud_a_en: out std_logic; -- user data ch. A enable
ud_b_en: out std_logic; -- user data ch. B enable
cs_a_en: out std_logic; -- channel status ch. A enable
cs_b_en: out std_logic); -- channel status ch. B enable);
end component;
component dpram
generic (DATA_WIDTH: positive := 32;
RAM_WIDTH: positive := 8);
port (
clk: in std_logic;
rst: in std_logic; -- reset is optional, not used here
din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
component rx_decode
generic (DATA_WIDTH: integer range 16 to 32 := 32;
ADDR_WIDTH: integer range 8 to 64 := 8);
port (
up_clk: in std_logic;
conf_rxen: in std_logic;
conf_sample: in std_logic;
conf_valid: in std_logic;
conf_mode: in std_logic_vector(3 downto 0);
conf_blken: in std_logic;
conf_valen: in std_logic;
conf_useren: in std_logic;
conf_staten: in std_logic;
conf_paren: in std_logic;
lock: in std_logic;
rx_data: in std_logic;
rx_data_en: in std_logic;
rx_block_start: in std_logic;
rx_frame_start: in std_logic;
rx_channel_a: in std_logic;
wr_en: out std_logic;
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
stat_paritya: out std_logic;
stat_parityb: out std_logic;
stat_lsbf: out std_logic;
stat_hsbf: out std_logic);
end component;
component rx_wb_decoder
generic (DATA_WIDTH: integer := 32;
ADDR_WIDTH: integer := 8);
port (
up_clk: in std_logic; -- wishbone clock
wb_rst_i: in std_logic; -- reset signal
wb_sel_i: in std_logic; -- select input
wb_stb_i: in std_logic; -- strobe input
wb_we_i: in std_logic; -- write enable
wb_cyc_i: in std_logic; -- cycle input
wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier
data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
wb_ack_o: out std_logic; -- acknowledge
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
version_rd: out std_logic; -- Version register read
config_rd: out std_logic; -- Config register read
config_wr: out std_logic; -- Config register write
status_rd: out std_logic; -- Status register read
intmask_rd: out std_logic; -- Interrupt mask register read
intmask_wr: out std_logic; -- Interrupt mask register write
intstat_rd: out std_logic; -- Interrupt status register read
intstat_wr: out std_logic; -- Interrupt status register read
mem_rd: out std_logic; -- Sample memory read
mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr.
ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read
ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
end component;
end rx_package;
| mit | 2a809d028a0f680a2bfa1e7316d32074 | 0.511468 | 4.032247 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/vhdl/axi_upif.vhd | 1 | 6,926 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_upif is
generic (
C_S_AXI_MIN_SIZE : std_logic_vector := x"0000ffff";
C_BASEADDR : std_logic_vector := x"ffffffff";
C_HIGHADDR : std_logic_vector := x"00000000");
port (
up_rstn : out std_logic;
up_clk : out std_logic;
upif_sel : out std_logic;
upif_rwn : out std_logic;
upif_addr : out std_logic_vector(31 downto 0);
upif_wdata : out std_logic_vector(31 downto 0);
upif_wack : in std_logic;
upif_rdata : in std_logic_vector(31 downto 0);
upif_rack : in std_logic;
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awvalid : in std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arvalid : in std_logic;
s_axi_rready : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_awready : out std_logic);
end entity axi_upif;
architecture rtl of axi_upif is
constant ZERO_32 : std_logic_vector(31 downto 0) := (others => '0');
constant C_TIMEOUT : integer := 16;
constant C_NUM_CE : INTEGER_ARRAY_TYPE := (0 => (32));
constant C_ADDR_RANGE : SLV64_ARRAY_TYPE := (ZERO_32 & C_BASEADDR, ZERO_32 & C_HIGHADDR);
signal gnd : std_logic;
signal upif_sel_s : std_logic_vector(0 downto 0);
begin
gnd <= '0';
upif_sel <= upif_sel_s(0);
i_axi_lite_ipif: entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map (
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_DPHASE_TIMEOUT => C_TIMEOUT,
C_ARD_NUM_CE_ARRAY => C_NUM_CE,
C_ARD_ADDR_RANGE_ARRAY => C_ADDR_RANGE)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_RREADY => s_axi_rready,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_AWREADY => s_axi_awready,
Bus2IP_Clk => up_clk,
Bus2IP_Resetn => up_rstn,
Bus2IP_Addr => upif_addr,
Bus2IP_RNW => upif_rwn,
Bus2IP_BE => open,
Bus2IP_CS => upif_sel_s,
Bus2IP_RdCE => open,
Bus2IP_WrCE => open,
Bus2IP_Data => upif_wdata,
IP2Bus_WrAck => upif_wack,
IP2Bus_RdAck => upif_rack,
IP2Bus_Error => gnd,
IP2Bus_Data => upif_rdata);
end rtl;
-- ***************************************************************************
-- ***************************************************************************
| mit | d2817784b2dd53cd44fc269cc06ba6df | 0.513716 | 3.906373 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_32.vhd | 1 | 1,286 | -- File: gray_counter_32.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:42 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_32 is
port (
gray_count: out unsigned(31 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_32;
architecture MyHDL of gray_counter_32 is
signal even: std_logic;
signal gray: unsigned(31 downto 0);
begin
GRAY_COUNTER_32_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(31 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((32 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 32-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_32_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | 7fd613d824cf62f63ffc99eaca87677e | 0.561431 | 3.402116 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_8.vhd | 1 | 1,275 | -- File: gray_counter_8.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_8 is
port (
gray_count: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_8;
architecture MyHDL of gray_counter_8 is
signal even: std_logic;
signal gray: unsigned(7 downto 0);
begin
GRAY_COUNTER_8_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(7 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((8 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 8-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_8_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | 56ce0c0715338093fa155f0320c5d9d2 | 0.557647 | 3.373016 | false | false | false | false |
EPiCS/soundgates | hardware/basic/mul/mul.vhd | 1 | 1,548 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - mul.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: multiplies two samples
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity mul is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end mul;
architecture Behavioral of mul is
signal output64 : signed (63 downto 0);
begin
output <= output64(31 downto 0);
adder : process (clk, rst, ce)
begin
if rising_edge(clk) then
if ce = '1' then
output64 <= wave1 * wave2;
end if;
end if;
end process;
end Behavioral;
| mit | adbdb9c707ccc2bd1b53c5f245d9511f | 0.363695 | 3.748184 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_square_v1_00_a/hdl/vhdl/hwt_square.vhd | 1 | 14,449 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_square
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for a square wave
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_square is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_square;
architecture Behavioral of hwt_square is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component square is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
duty_on : in signed(31 downto 0);
duty_off: in signed(31 downto 0);
sq : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_DUTY_ON,STATE_REFRESH_DUTY_OFF, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--10;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_sq : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_sq : std_logic_vector(0 to 31); -- sq to local ram
signal i_RAMData_sq : std_logic_vector(0 to 31); -- local ram to sq
signal o_RAMWE_sq : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal sq_ce : std_logic; -- sq clock enable (like a start/stop signal)
signal phase_offset_addr : std_logic_vector(31 downto 0);
signal phase_incr_addr : std_logic_vector(31 downto 0);
signal duty_on_addr : std_logic_vector(31 downto 0);
signal duty_off_addr : std_logic_vector(31 downto 0);
signal phase_offset : std_logic_vector(31 downto 0);
signal phase_incr : std_logic_vector(31 downto 0);
signal duty_on : std_logic_vector(31 downto 0);
signal duty_off : std_logic_vector(31 downto 0);
signal sq_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant sq_START : std_logic_vector(31 downto 0) := x"0000000F";
constant sq_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_sq <= std_logic_vector(sq_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
sq_inst : square
port map(
clk => clk,
rst => rst,
ce => sq_ce,
incr => signed(phase_incr),
offset => signed(phase_offset),
duty_on => signed(duty_on),
duty_off => signed(duty_off),
sq => sq_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_sq = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_sq))) := o_RAMData_sq;
--else -- else not needed, because sq is not consuming any samples
-- i_RAMData_sq <= local_ram(conv_integer(unsigned(o_RAMAddr_sq)));
end if;
end if;
end process;
sq_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
sq_ce <= '0';
o_RAMWE_sq <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
sq_ce <= '0';
o_RAMWE_sq <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
phase_offset_addr <= snd_comp_header.opt_arg_addr;
phase_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
duty_on <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 8);
duty_off <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 12);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = sq_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = sq_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, phase_offset_addr, phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_PHASE_INCR =>
memif_read_word(i_memif, o_memif, phase_incr_addr, phase_incr, done);
if done then
state <= STATE_REFRESH_DUTY_ON;
end if;
when STATE_REFRESH_DUTY_ON =>
memif_read_word(i_memif, o_memif, duty_on_addr, duty_on, done);
if done then
state <= STATE_REFRESH_DUTY_OFF;
end if;
when STATE_REFRESH_DUTY_OFF =>
memif_read_word(i_memif, o_memif, duty_off_addr, duty_off, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_sq <= '1';
sq_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_sq <= std_logic_vector(unsigned(o_RAMAddr_sq) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_sq <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 31ce93db812dfa4ea6b9dea793b83fcd | 0.488511 | 3.709371 | false | false | false | false |
EPiCS/soundgates | hardware/basic/triangle/triangle.vhd | 1 | 2,380 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - triangle.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Triangle wave generator
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity triangle is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
tri : out signed(31 downto 0)
);
end triangle;
architecture Behavioral of triangle is
signal direction : std_logic := '0';
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant upper : signed (31 downto 0) := to_signed(integer(real( 1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant lower : signed (31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
begin
tri <= x;
CALC_TRI : process (clk, rst)
begin
if rst = '1' then
x <= offset;
else
if rising_edge(clk) then
if ce = '1' then
if direction = '0' then
x <= x + incr;
if x > upper then
direction <= '1';
end if;
elsif direction = '1' then
x <= x - incr;
if x < lower then
direction <= '0';
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 3ce2ee4404ff9a4147da8a7ab90e7b54 | 0.371429 | 4 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_noise_v1_00_a/hdl/vhdl/hwt_noise.vhd | 1 | 12,074 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_noise
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating noise
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_noise is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NOISE_TPYE : integer := 0
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_noise;
architecture Behavioral of hwt_noise is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component PRBS is
generic(
FPGA_FREQUENCY : integer := 100_000_000
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end component PRBS;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_noise : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_noise : std_logic_vector(0 to 31); -- noise to local ram
signal i_RAMData_noise : std_logic_vector(0 to 31); -- local ram to noise
signal o_RAMWE_noise : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal state_inner_process : std_logic;
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal noise_ce : std_logic; -- noise clock enable (like a start/stop signal)
signal noise_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant NOISE_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NOISE_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_noise <= std_logic_vector(noise_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
NOISE_INST : PRBS
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ
)
port map(
clk => clk,
rst => rst,
ce => noise_ce,
signed(rand) => noise_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_noise = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_noise))) := o_RAMData_noise;
--else -- else not needed, because noise is not consuming any samples
-- i_RAMData_noise <= local_ram(conv_integer(unsigned(o_RAMAddr_noise)));
end if;
end if;
end process;
NOISE_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
noise_ce <= '0';
o_RAMWE_noise <= '0';
done := False;
elsif rising_edge(clk) then
noise_ce <= '0';
o_RAMWE_noise <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
when STATE_INIT =>
-- Init not used
state <= STATE_WAITING;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = NOISE_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_PROCESS;
elsif osif_ctrl_signal = NOISE_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_noise <= '1';
noise_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_noise <= std_logic_vector(unsigned(o_RAMAddr_noise) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_noise <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | bfef21c4c13de3d4860a24914f9da8a1 | 0.487037 | 3.669605 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Main_Processor.vhd | 1 | 24,086 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.STD_LOGIC;
use ieee.numeric_std.all;
entity Main_Processor is
port(
CLK : in std_logic;
RESET,enable : in std_logic;
INPORT : in std_logic_vector(15 downto 0) --
);
end Main_Processor;
architecture Main_Processor_arch of Main_Processor is
--------------------------------------------------------------------------------------------------------
component control_entity is
port (
op_code: in std_logic_vector(4 downto 0);
nop_enable:in std_logic; --nop operation enable for load & store
pc_mux : out std_logic_vector(1 downto 0);
inport_en : out std_logic;
outport_en : out std_logic;
reg_write : out std_logic;
mem_write : out std_logic;
write_data_reg_mux : out std_logic;
Shift_Mux : out std_logic; -- to know if make shift or not
write_back_mux : out std_logic_vector(1 downto 0);
int_flags_en : out std_logic; -- int to take flags from meomry to alu
alu_control : out std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)علي حسب شغلك 'musgi'
mem_mux : out std_logic;
Stack_WriteEnable_control, StackPushPop_control : out std_logic
);
end component;
-------------------------------------------------------------------------------------------------------
component MUX_Fetch is
port(
Sel: in std_logic_vector (1 downto 0);--input from control unit
PC2: in std_logic_vector(15 downto 0 ); --address to jump to from BRANCH
PC3: in std_logic_vector(15 downto 0 ); --address from memory[0]
PC4: in std_logic_vector(15 downto 0 ); --address from memory[1]
CLK: in std_logic;
Out_instruction: out std_logic_vector(15 downto 0 );
InPort: in std_logic_vector(15 downto 0);
OutPort: out std_logic_vector(15 downto 0);
RESET: in std_logic
);
end component;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
component fetch_Buffer is
Generic ( n : integer := 16);
port(
Clk : in std_logic;
Rst : in std_logic;
inport_en_input : in std_logic_vector(15 downto 0); --
instruction_input :in std_logic_vector(15 downto 0);
inport_en_output : out std_logic_vector(15 downto 0); --
instruction_output :out std_logic_vector(15 downto 0);
OPcode: out std_logic_vector(4 downto 0 );
R1: out std_logic_vector(2 downto 0 ); --addres of reg1
R2: out std_logic_vector(2 downto 0 ); --addres of reg2
Rout: out std_logic_vector(2 downto 0 ); --for write back
R_shift: out std_logic_vector(3 downto 0 );
LDD_Memory: out std_logic_vector(9 downto 0 ); --load value from memory to register
LDM_immediate: out std_logic_vector(15 downto 0 ) --load immediate value from user to register
--pc_mux_input : in std_logic_vector(1 downto 0);
--outport_en_input : in std_logic;
--reg_write_input : in std_logic;
--mem_write_input : in std_logic;
--write_data_reg_mux_input : in std_logic;
--Shift_Mux_input : in std_logic; -- to know if make shift or not
--write_back_mux_input : in std_logic_vector(1 downto 0);
--int_flags_en_input : in std_logic; -- int to take flags from meomry to alu
--alu_control_input : in std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
--mem_mux_input : in std_logic;
--pc_mux_output : out std_logic_vector(1 downto 0);
--outport_en_output : out std_logic;
--reg_write_output : out std_logic;
--mem_write_output : out std_logic;
--write_data_reg_mux_output : out std_logic;
--Shift_Mux_output : out std_logic; -- to know if make shift or not
--write_back_mux_output : out std_logic_vector(1 downto 0);
--int_flags_en_output : out std_logic; -- int to take flags from meomry to alu
--alu_control_output : out std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
--mem_mux_output : out std_logic
);
end component;
------------------------------------------------------------------------------------------------------------------------------------
component Decode_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
R1_in: in std_logic_vector(15 downto 0 ); --addres of reg1
R2_in: in std_logic_vector(15 downto 0 ); --addres of reg2
Rout_in: in std_logic_vector(2 downto 0 ); --for write back
R1_out: out std_logic_vector(15 downto 0 ); --addres of reg1
R2_out: out std_logic_vector(15 downto 0 ); --addres of reg2
Rout_out: out std_logic_vector(2 downto 0 ); --for write back
R_shift_in:in std_logic_vector(3 downto 0 );
R_shift_out:out std_logic_vector(3 downto 0 );
OPcode_in: in std_logic_vector(4 downto 0 );
OPcode_out: out std_logic_vector(4 downto 0 );
R1_address_in,R2_address_in: in std_logic_vector(2 downto 0 );
R1_address_out,R2_address_out: out std_logic_vector(2 downto 0 );
pc_mux_input : in std_logic_vector(1 downto 0);
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
int_flags_en_input : in std_logic; -- int to take flags from meomry to alu
alu_control_input : in std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
mem_mux_input : in std_logic;
pc_mux_output : out std_logic_vector(1 downto 0);
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
-- to know if make shift or not
write_back_mux_output : out std_logic_vector(1 downto 0);
int_flags_en_output : out std_logic; -- int to take flags from meomry to alu
alu_control_output : out std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
mem_mux_output : out std_logic;
Stack_WriteEnable_input, StackPushPop_signal_input : in std_logic;
Stack_WriteEnable_output, StackPushPop_output : out std_logic
);
end component;
----------------------------------------------------------------------------------------------------------
component Ext_Mem_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
op_code_input: in std_logic_vector(4 downto 0);
mem_mux_input : in std_logic; --mickey mux
R1_regfile_input: in std_logic_vector(15 downto 0);
--ALU_address_input : in std_logic_vector(9 downto 0);
--stack_address_input : in std_logic_vector(9 downto 0);
--ALU_address_input,stack_address_input : in std_logic_vector(9 downto 0);
ALU_out_input : in std_logic_vector(15 downto 0);
Z_input: in std_logic;
NF_input: in std_logic;
V_input: in std_logic;
C_input: in std_logic;
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
LDM_immediate_input : in std_logic_vector(15 downto 0);
load_store_address_input : in std_logic_vector(9 downto 0); --LDD
--------------------------------------------------------------------------------------------------------------------
pc_mux_output : out std_logic_vector(1 downto 0);
op_code_output: out std_logic_vector(4 downto 0);
mem_mux_output : out std_logic; --mickey mux
R1_regfile_output: out std_logic_vector(15 downto 0);
--ALU_address_output,stack_address_output : out std_logic_vector(9 downto 0);
ALU_out_output : out std_logic_vector(15 downto 0);
Z_output: out std_logic;
NF_output: out std_logic;
V_output: out std_logic;
C_output: out std_logic;
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
LDM_immediate_output : out std_logic_vector(15 downto 0);
load_store_address_output : out std_logic_vector(9 downto 0);
Stack_WriteEnable_input1, StackPushPop_signal_input1 : in std_logic;
Stack_WriteEnable_output1, StackPushPop_output1 : out std_logic;
R1_address_in2,R2_address_in2: in std_logic_vector(2 downto 0 );
R1_address_out2,R2_address_out2: out std_logic_vector(2 downto 0 );
Rout_in1: out std_logic_vector(2 downto 0 );
Rout_out1: out std_logic_vector(2 downto 0 )
);
end component;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
component Mem_WB_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
outport_en_input : in std_logic;
reg_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
LDM_immediate_input : in std_logic_vector(15 downto 0);
--------------------------------------------------------------------------------------------------------------------
pc_mux_output : out std_logic_vector(1 downto 0);
outport_en_output : out std_logic;
reg_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
LDM_immediate_output : out std_logic_vector(15 downto 0);
--R1_address_in3,R2_address_in3: in std_logic_vector(2 downto 0 );
--R1_address_out3,R2_address_out3: out std_logic_vector(2 downto 0 );
Rout_in2: out std_logic_vector(2 downto 0 );
Rout_out2: out std_logic_vector(2 downto 0 )
);
end component;
-------------------------------------------------------------------------------------------------------------------------------------------
component Execution IS
port(
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1_Reg1,R2_Reg1,ROut_Alu1,ROut_Mem1: in std_logic_vector(2 downto 0);
R1_dec: in std_logic_vector(15 downto 0);
R2_dec: in std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Alu_Output_exe , Meomry_Output_exe: in std_logic_vector(15 downto 0);
Execution_Output: out std_logic_vector(15 downto 0);
Z_F: out std_logic;
NF_F: out std_logic;
V_F: out std_logic;
C_F: out std_logic
);
end component;
--------------------------------------------------------------------------------------------------------------------------------------------------
component ALU is
port (
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1: in std_logic_vector(15 downto 0);
R2: in std_logic_vector(15 downto 0);
Output: out std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Z: out std_logic;
NF: out std_logic;
v: out std_logic;
C: out std_logic
);
end component;
---------------------------------------------------------------------------------------------------------------------------
component Forwarding IS
port(
R1_Reg,R2_Reg,ROut_Alu,ROut_Mem: in std_logic_vector(2 downto 0);
R1,R2: out std_logic_vector(15 downto 0);
R1_Mux,R2_Mux : out std_logic;
Alu_Output , Meomry_Output: in std_logic_vector(15 downto 0)
);
END component;
--------------------------------------------------------------------------------------------------------------------------------
component REG is
Generic ( n : integer := 16);
port(
Clock,Reset : in std_logic;
d : in std_logic_vector(n-1 downto 0);
R1_Out, R2_Out : out std_logic_vector(15 downto 0);
w_en : in std_logic ;--write enable
Rout,R1,R2 : in std_logic_vector(2 downto 0);--
input_port : in std_logic_vector(15 downto 0);
wrt_data_reg_mux : in std_logic;
--------------------------------------------------------
Shift_Mux : in std_logic;
OPcode_in: in std_logic_vector(4 downto 0 );
OPcode_out: out std_logic_vector(4 downto 0 )
);
end component;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
component syncram is
Generic ( n : integer := 8);
port ( clk : in std_logic;
we : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end component;
-------------------------------------------------------------------------------------------------------------------
component syncram2 is
Generic ( n : integer := 8);
port ( clk,rst : in std_logic;
we, weStack, stackPushPop : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end component;
------------------------------------------------------------------------------------------------------------------------
component Memory is
PORT ( Clk, rst, Mux_Selector, Memory_WriteEnable, Stack_WriteEnable, StackPushPop : in std_logic; --StackPushPop 0: psuh, 1: pop
--FlagEnable : in std_logic;
InputAddress, LoadAdress : in std_logic_vector(9 downto 0);
DataIn : in std_logic_vector(15 downto 0);
DataOut, M0, M1 : out std_logic_vector (15 downto 0);
Flags_Z_In, Flags_NF_In, Flags_V_In, Flags_C_In : in std_logic;
Flags_Z_Out, Flags_NF_Out, Flags_V_Out, Flags_C_Out : out std_logic;
BranchOpCode_In : in std_logic_vector (4 downto 0);
BranchR1_In : in std_logic_vector (15 downto 0);
Branch_Out : out std_logic_vector (15 downto 0)
);
END component;
---------------------------------------------------------------------------------------------------------------------------------------
component WriteBack is
PORT ( Clk, rst : in std_logic;
DataIn1, DataIn2, DataIn3 : in std_logic_vector(15 downto 0);
ControlIn : in std_logic_vector (1 downto 0);
DataOut : out std_logic_vector (15 downto 0)
);
END component;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--control signals
signal nop_enable_signal : std_logic;
signal pc_mux_signal : std_logic_vector(1 downto 0);
signal inport_en_signal : std_logic;
signal outport_en_signal : std_logic;
signal reg_write_signal : std_logic;
signal mem_write_signal : std_logic;
signal write_data_reg_mux_signal : std_logic;
signal Shift_Mux_signal : std_logic;
signal write_back_mux_signal : std_logic_vector(1 downto 0);
signal int_flags_en_signal : std_logic;
signal alu_control_signal : std_logic_vector(4 downto 0);
signal mem_mux_signal : std_logic;
signal nop_enable_signal1 : std_logic;
signal pc_mux_signal1 : std_logic_vector(1 downto 0);
signal inport_en_signal1 : std_logic;
signal outport_en_signal1 : std_logic;
signal reg_write_signal1 : std_logic;
signal mem_write_signal1 : std_logic;
signal write_data_reg_mux_signal1 : std_logic;
signal Shift_Mux_signal1 : std_logic;
signal write_back_mux_signal1 : std_logic_vector(1 downto 0);
signal int_flags_en_signal1 : std_logic;
signal alu_control_signal1 : std_logic_vector(4 downto 0);
signal mem_mux_signal1 : std_logic;
signal Stack_WriteEnable_signal, StackPushPop_signal : std_logic ;
--Fetch signals
signal Sel_signal: std_logic_vector (1 downto 0);
signal PC2_signal: std_logic_vector(15 downto 0 );
signal PC3_signal: std_logic_vector(15 downto 0 );
signal PC4_signal: std_logic_vector(15 downto 0 );
signal Out_instruction_signal: std_logic_vector(15 downto 0 );
signal OutPort_signal: std_logic_vector(15 downto 0);
--fetch_Buffer signals
signal instruction_output_signal: std_logic_vector(15 downto 0 );
signal inport_en_output_signal:std_logic_vector(15 downto 0 );
signal OPcode_signal: std_logic_vector(4 downto 0 );
signal R1_signal: std_logic_vector(2 downto 0 ); --addres of reg1
signal R2_signal: std_logic_vector(2 downto 0 ); --addres of reg2
signal Rout_signal: std_logic_vector(2 downto 0 ); --for write back
signal R_shift_signal: std_logic_vector(3 downto 0 );
signal LDD_Memory_signal: std_logic_vector(9 downto 0 ); --load value from memory to register
signal LDM_immediate_signal: std_logic_vector(15 downto 0 );
--Decoder signals
signal R1_Out_signal, R2_Out_signal : std_logic_vector(15 downto 0);
signal write_enable : std_logic;
signal datavsinport : std_logic;
signal Shift_Mux : std_logic;
signal OPcode_signal1: std_logic_vector(4 downto 0 );
--decode Buffer signals
signal R1_out_signal1 : std_logic_vector(15 downto 0 );
signal R2_out_signal1 : std_logic_vector(15 downto 0 );
signal Rout_out_signal1 : std_logic_vector(2 downto 0 );
signal R_shift_out_signal: std_logic_vector(3 downto 0 );
signal OPcode_signal2: std_logic_vector(4 downto 0 );
signal R1_signal2: std_logic_vector(2 downto 0 );
signal R2_signal2: std_logic_vector(2 downto 0 );
signal ROut_Alu_signal: std_logic_vector(2 downto 0 ); --R_out_ALu address
signal ROut_Mem_signal: std_logic_vector(2 downto 0 ); --R_out_Mem addres
signal Alu_dataout_signal: std_logic_vector(15 downto 0 ); --R_out_ALu address
--signal Mem_dataout_signal: std_logic_vector(15 downto 0 ); --R_out_Mem addres
signal Stack_WriteEnable_signal1 : std_logic;
signal StackPushPop_signal1 : std_logic;
--Execution signals
signal Output_signal: std_logic_vector(15 downto 0);
signal Z_signal: std_logic;
signal NF_signal: std_logic;
signal v_signal: std_logic;
signal C_signal: std_logic;
signal Execution_Output_signal : std_logic_vector(15 downto 0);
signal Meomrey_Output_signal : std_logic_vector(15 downto 0);
signal OPcode_signal3: std_logic_vector(4 downto 0 );
signal pc_mux_signal2 : std_logic_vector(1 downto 0);
signal outport_en_signal2 : std_logic;
signal reg_write_signal2 : std_logic;
signal mem_write_signal2 : std_logic;
signal write_data_reg_mux_signal2 : std_logic;
signal write_back_mux_signal2 : std_logic_vector(1 downto 0);
signal R1_out_signal3,R2_out_signal3: std_logic_vector(2 downto 0 );
signal R1_out_signal4,R2_out_signal4: std_logic_vector(2 downto 0 );
signal mem_mux_signal2 : std_logic;
signal LDD_Memory_signal1: std_logic_vector(9 downto 0 ); --load value from memory to register
signal LDM_immediate_signal1: std_logic_vector(15 downto 0 );
signal Z_signal1: std_logic;
signal NF_signal1: std_logic;
signal v_signal1: std_logic;
signal C_signal1: std_logic;
signal Execution_Output_signal1 : std_logic_vector(15 downto 0);
signal Stack_WriteEnable_signal2, StackPushPop_signal2 : std_logic;
signal R1_out_signal2 : std_logic_vector(15 downto 0 );
signal R2_out_signal2 : std_logic_vector(15 downto 0 );
--Memory
signal Mem_dataout_signal,M0_signal,M1_signal : std_logic_vector(15 downto 0);
signal Z_signal2: std_logic;
signal NF_signal2: std_logic;
signal v_signal2: std_logic;
signal C_signal2: std_logic;
signal Branch_out_signal : std_logic_vector (15 downto 0);
--MEM_WB signals
signal pc_mux_signal3 : std_logic_vector(1 downto 0);
signal outport_en_signal3 : std_logic;
signal reg_write_signal3 : std_logic;
signal write_data_reg_mux_signal3 : std_logic;
signal write_back_mux_signal3 : std_logic_vector(1 downto 0);
signal LDM_immediate_signal2: std_logic_vector(15 downto 0 );
------
signal Rout_signal1,Rout_signal2,Rout_signal3: std_logic_vector(2 downto 0 );
------
begin
--Comments :1)sel should be entered by control unit
--2)what reset do ?
FETCH : MUX_Fetch generic map (n=>16)port map(pc_mux_signal3,Branch_out_signal,M0_signal,M1_signal,CLK,Out_instruction_signal,INPORT,OutPort_signal,RESET);
BUFFER1: fetch_Buffer generic map (n =>16) port map (CLK,RESET,OutPort_signal,Out_instruction_signal,inport_en_output_signal,instruction_output_signal,OPcode_signal,R1_signal,R2_signal,Rout_signal,R_shift_signal,LDD_Memory_signal,LDM_immediate_signal);
Decoder: REG generic map (n=>16)port map(CLK,RESET,"1111000011110000",R1_Out_signal,R2_Out_signal,write_enable,Rout_signal,R1_signal,R2_signal,inport_en_output_signal,datavsinport,Shift_Mux,OPcode_signal,OPcode_signal1);
control_map : control_entity port map(OPcode_signal1,nop_enable_signal,pc_mux_signal,inport_en_signal,outport_en_signal,reg_write_signal,mem_write_signal,write_data_reg_mux_signal,Shift_Mux_signal,write_back_mux_signal,int_flags_en_signal,alu_control_signal,mem_mux_signal,Stack_WriteEnable_signal, StackPushPop_signal);
Buffer2 : Decode_Buffer port map(CLK,RESET,R1_Out_signal,R2_Out_signal,Rout_signal,R1_out_signal1,R2_out_signal1,Rout_out_signal1,R_shift_signal,R_shift_out_signal,OPcode_signal1,OPcode_signal2,R1_signal,R2_signal,R1_signal2,R2_signal2,pc_mux_signal,outport_en_signal,reg_write_signal,mem_write_signal,write_data_reg_mux_signal,write_back_mux_signal,int_flags_en_signal,alu_control_signal,mem_mux_signal,pc_mux_signal1,outport_en_signal1,reg_write_signal1,mem_write_signal1,write_data_reg_mux_signal1,write_back_mux_signal1,int_flags_en_signal1,alu_control_signal1,mem_mux_signal1,Stack_WriteEnable_signal, StackPushPop_signal,Stack_WriteEnable_signal1, StackPushPop_signal1);
Execute_map : Execution port map(CLK,RESET,enable,OPcode_signal2,R1_signal2,R2_signal2,ROut_Alu_signal,ROut_Mem_signal,R1_out_signal1,R2_Out_signal,R_shift_out_signal,Execution_Output_signal1,Mem_dataout_signal,Execution_Output_signal,Z_signal,NF_signal,v_signal,C_signal);
Buffer3 : Ext_Mem_Buffer port map(CLK,RESET,enable,pc_mux_signal1,OPcode_signal2,mem_mux_signal1,R1_out_signal1,Execution_Output_signal,Z_signal,NF_signal,v_signal,C_signal,outport_en_signal1,reg_write_signal1,mem_write_signal1,write_data_reg_mux_signal1,write_back_mux_signal1,LDM_immediate_signal,LDD_Memory_signal,pc_mux_signal2,OPcode_signal3,mem_mux_signal2,R1_out_signal2,Execution_Output_signal1,Z_signal1,NF_signal1,v_signal1,C_signal1,outport_en_signal2,reg_write_signal2,mem_write_signal2,write_data_reg_mux_signal2,write_back_mux_signal2,LDM_immediate_signal1,LDD_Memory_signal1,Stack_WriteEnable_signal1, StackPushPop_signal1,Stack_WriteEnable_signal2, StackPushPop_signal2,R1_signal2,R2_signal2,R1_out_signal3,R2_out_signal3,Rout_signal,ROut_Alu_signal);
--Memory_map : Memory port map(CLK,RESET,mem_mux_signal2,mem_write_signal2,Stack_WriteEnable_signa2, StackPushPop_signa2,stackaddress"mickey"!!,LDD_Memory_signal1,Execution_Output_signal1,Mem_dataout_signal,M0_signal,M1_signal,Z_signal1,NF_signal1,v_signal1,C_signal1,Z_signal2,NF_signal2,v_signal2,C_signal2,OPcode_signal3,R1_out_signal2,Branch_out_signal)
Buffer4 : Mem_WB_Buffer port map(Clk,RESET,enable,pc_mux_signal2,outport_en_signal2,reg_write_signal2,write_data_reg_mux_signal2,write_back_mux_signal2,LDM_immediate_signal1,pc_mux_signal3,outport_en_signal3,reg_write_signal3,write_data_reg_mux_signal3,write_back_mux_signal3,LDM_immediate_signal2,Rout_signal1,ROut_Mem_signal);
-- Buffer3:
-- Memory:
-- Buffer4:
-- WB:
end Main_Processor_arch;
| mit | 18bde064fa204365bd124b43be3b6751 | 0.61987 | 3.167061 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_f_v1_00_a/hdl/vhdl/axi_dac_1c_2p_f.vhd | 1 | 11,874 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_dac_1c_2p_f is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
rst : in std_logic;
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_a_p : out std_logic_vector(13 downto 0);
dac_data_out_a_n : out std_logic_vector(13 downto 0);
dac_data_out_b_p : out std_logic_vector(13 downto 0);
dac_data_out_b_n : out std_logic_vector(13 downto 0);
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sd_o : out std_logic;
spi_sd_i : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_clk : out std_logic;
debug_data : out std_logic_vector(79 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
vdma_clk : in std_logic;
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dac_1c_2p_f;
architecture IMP of axi_dac_1c_2p_f is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
rst : in std_logic;
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_a_p : out std_logic_vector(13 downto 0);
dac_data_out_a_n : out std_logic_vector(13 downto 0);
dac_data_out_b_p : out std_logic_vector(13 downto 0);
dac_data_out_b_n : out std_logic_vector(13 downto 0);
vdma_clk : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_ready : out std_logic;
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sd_o : out std_logic;
spi_sd_i : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_clk : out std_logic;
debug_data : out std_logic_vector(79 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
rst => rst,
dac_clk_in_p => dac_clk_in_p,
dac_clk_in_n => dac_clk_in_n,
dac_clk_out_p => dac_clk_out_p,
dac_clk_out_n => dac_clk_out_n,
dac_frame_out_p => dac_frame_out_p,
dac_frame_out_n => dac_frame_out_n,
dac_data_out_a_p => dac_data_out_a_p,
dac_data_out_a_n => dac_data_out_a_n,
dac_data_out_b_p => dac_data_out_b_p,
dac_data_out_b_n => dac_data_out_b_n,
vdma_clk => vdma_clk,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_ready => M_AXIS_MM2S_TREADY,
spi_cs0n => spi_cs0n,
spi_cs1n => spi_cs1n,
spi_clk => spi_clk,
spi_sd_o => spi_sd_o,
spi_sd_i => spi_sd_i,
up_status => up_status,
debug_clk => debug_clk,
debug_data => debug_data,
debug_trigger => debug_trigger,
delay_clk => delay_clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 8253ccc9196833f4b75902e0da33900c | 0.544467 | 2.983417 | false | false | false | false |
aylons/sp601_spi_test | hdl/top/spi_single_test.vhd | 1 | 8,170 | -------------------------------------------------------------------------------
-- Title : Testbench for one SPI frequency
-- Project :
-------------------------------------------------------------------------------
-- File : spi_single_test.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-11-01
-- Last update: 2014-11-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This module tests one SPI channel
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-11-01 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spi_single_test is
generic(
g_width : positive := 16
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
--master
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_ssel_o : out std_logic;
--slave
spi_sck_i : in std_logic;
spi_mosi_i : in std_logic;
spi_miso_o : out std_logic;
spi_ssel_i : in std_logic;
chipscope_control : inout std_logic_vector(35 downto 0)
);
end entity spi_single_test;
architecture structural of spi_single_test is
constant c_cpol : std_logic := '0';
constant c_cpha : std_logic := '0';
constant c_prefetch : positive := 1;
constant c_spi_clk_div : positive := 1;
-- service signals
signal clock : std_logic;
signal enable : std_logic := '1';
-- master signals
signal master_req, master_wren : std_logic;
signal master_di : std_logic_vector(g_width-1 downto 0);
signal count_up : std_logic;
--slave signals
signal slave_valid : std_logic;
signal slave_do : std_logic_vector(g_width-1 downto 0);
signal slave_ok, slave_nok : std_logic;
-- output signals
signal ok_count, nok_count : std_logic_vector(g_width-1 downto 0);
component spi_master is
generic (
N : positive; -- width
CPOL : std_logic;
CPHA : std_logic;
PREFETCH : positive;
SPI_2X_CLK_DIV : positive);
port (
sclk_i : in std_logic := 'X';
pclk_i : in std_logic := 'X';
rst_i : in std_logic := 'X';
spi_ssel_o : out std_logic;
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic := 'X';
di_req_o : out std_logic;
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X');
wren_i : in std_logic := 'X';
wr_ack_o : out std_logic;
do_valid_o : out std_logic;
do_o : out std_logic_vector (N-1 downto 0));
end component spi_master;
component spi_slave is
generic (
N : positive;
CPOL : std_logic;
CPHA : std_logic;
PREFETCH : positive);
port (
clk_i : in std_logic := 'X';
spi_ssel_i : in std_logic := 'X';
spi_sck_i : in std_logic := 'X';
spi_mosi_i : in std_logic := 'X';
spi_miso_o : out std_logic := 'X';
di_req_o : out std_logic;
di_i : in std_logic_vector (N-1 downto 0) := (others => 'X');
wren_i : in std_logic := 'X';
wr_ack_o : out std_logic;
do_valid_o : out std_logic;
do_o : out std_logic_vector (N-1 downto 0));
end component spi_slave;
component simple_counter is
generic (
g_width : natural);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0));
end component simple_counter;
component slave_checker is
generic (
g_width : natural);
port (
clk_i : in std_logic;
rst_i : in std_logic;
spi_valid_i : in std_logic;
data_i : in std_logic_vector(g_width-1 downto 0);
ok_o : out std_logic;
nok_o : out std_logic);
end component slave_checker;
component master_controller is
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
spi_req_i : in std_logic;
spi_wen_o : out std_logic;
count_up_o : out std_logic);
end component master_controller;
component chipscope_ila is
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
DATA : in std_logic_vector(63 downto 0);
TRIG0 : in std_logic_vector(7 downto 0));
end component chipscope_ila;
begin
cmp_master_controller : master_controller
port map (
clk_i => clk_i,
en_i => enable,
rst_i => rst_i,
spi_req_i => master_req,
spi_wen_o => master_wren,
count_up_o => count_up);
cmp_count_gen : simple_counter
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => count_up,
data_o => master_di);
cmp_master : spi_master
generic map (
N => g_width,
CPOL => c_cpol,
CPHA => c_cpha,
PREFETCH => c_prefetch,
SPI_2X_CLK_DIV => c_spi_clk_div)
port map (
sclk_i => clk_i,
pclk_i => clk_i,
rst_i => rst_i,
spi_ssel_o => spi_ssel_o,
spi_sck_o => spi_sck_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
di_req_o => master_req,
di_i => master_di,
wren_i => master_wren,
wr_ack_o => open,
do_valid_o => open,
do_o => open);
-----------------------------------------------------------------------------
-- slave section
cmp_spi_slave : spi_slave
generic map (
N => g_width,
CPOL => c_cpol,
CPHA => c_cpha,
PREFETCH => c_prefetch)
port map (
clk_i => clk_i,
spi_ssel_i => spi_ssel_i,
spi_sck_i => spi_sck_i,
spi_mosi_i => spi_mosi_i,
spi_miso_o => spi_miso_o,
di_req_o => open,
di_i => (others => '0'),
wren_i => '0',
wr_ack_o => open,
do_valid_o => slave_valid,
do_o => slave_do);
cmp_slave_checker : slave_checker
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
spi_valid_i => slave_valid,
data_i => slave_do,
ok_o => slave_ok,
nok_o => slave_nok);
cmp_ok_counter : simple_counter
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => slave_ok,
data_o => ok_count);
cmp_nok_counter : simple_counter
generic map (
g_width => g_width)
port map (
clk_i => clk_i,
rst_i => rst_i,
ce_i => slave_nok,
data_o => nok_count);
cmp_ila : chipscope_ila
port map (
CONTROL => chipscope_control,
CLK => clk_i,
DATA(63 downto 48) => master_di(15 downto 0),
DATA(47 downto 32) => ok_count(15 downto 0),
DATA(31 downto 16) => nok_count(15 downto 0),
DATA(15) => slave_valid,
DATA(14) => slave_ok,
DATA(13) => slave_nok,
DATA(12 downto 0) => slave_do(12 downto 0),
TRIG0(7) => slave_valid,
TRIG0(6 downto 2) => (others => '0'),
TRIG0(1) => slave_ok,
TRIG0(0) => master_req);
end architecture structural;
| gpl-3.0 | 24ba30ff46c6ba8ec5b4354ee7dbe78c | 0.464137 | 3.427013 | false | false | false | false |
spiersad/ECGR4146-FIFO | FIFO_LOGIC_MODIFIED.vhd | 1 | 2,662 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_LOGIC is
generic (N: integer := 8);
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
BUFF: buffer std_logic_vector(3 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic);
end entity FIFO_LOGIC;
architecture RTL of FIFO_LOGIC is
signal WPTR, RPTR: std_logic_vector(N-1 downto 0);
signal LASTOP: std_logic;
begin
SYNC: process (CLK) begin
if (CLK'event and CLK = '1') then
if (INIT = '1') then -- initialization --
WPTR <= (others => '0');
RPTR <= (others => '0');
LASTOP <= '0';
BUFF <= "0000";
elsif (POP = '1' and empty = '0') then -- pop --
RPTR <= RPTR + 1;
if (RPTR(5) = '1') then
RPTR(5) <= '0';
end if;
LASTOP <= '0';
BUFF <= BUFF - "0001";
elsif (PUSH = '1' and FULL = '0') then -- push --
WPTR <= WPTR + 1;
if (WPTR(5) = '1') then
WPTR(5) <= '0';
end if;
LASTOP <= '1';
BUFF <= BUFF + "0001";
end if; -- otherwise all Fs hold their value --
end if;
end process SYNC;
COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY)
begin
-- full and empty flags --
if (RPTR = WPTR) then
if (LASTOP = '1') then
FULL <= '1';
empty <= '0';
else
FULL <= '0';
empty <= '1';
end if;
else
FULL <= '0';
empty <= '0';
end if;
-- address, write enable and nopush/nopop logic --
if (POP = '0' and PUSH = '0') then -- no operation --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '0';
NOPOP <= '0';
elsif (POP = '0' and PUSH = '1') then -- push only --
ADD <= WPTR;
NOPOP <= '0';
if (FULL = '0') then -- valid write condition --
WE <= '1';
NOPUSH <= '0';
else -- no write condition --
WE <= '0';
NOPUSH <= '1';
end if;
elsif (POP = '1' and PUSH = '0') then -- pop only --
ADD <= RPTR;
NOPUSH <= '0';
WE <= '0';
if (empty = '0') then
-- valid read condition --
NOPOP <= '0';
else
NOPOP <= '1'; -- no red condition --
end if;
else -- push and pop at same time \u2013
if (empty = '0') then -- valid pop --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '1';
NOPOP <= '0';
else
ADD <= wptr;
WE <= '1';
NOPUSH <= '0';
NOPOP <= '1';
end if;
end if;
end process COMB;
end architecture RTL; | gpl-2.0 | a1ca091e9ed5e734dd4c3ccc4e9647b6 | 0.462059 | 3.319202 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/nco/nco_tb.vhd | 1 | 3,179 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use STD.textio.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY nco_tb IS
END nco_tb;
ARCHITECTURE behavior OF nco_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT nco
PORT(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '0';
signal phase_offset : signed(31 downto 0) := (others => '0');
signal phase_incr : signed(31 downto 0) := (others => '0');
constant C_MAX_SAMPLE_COUNT : integer := 1024;
constant FPGA_FREQUENCY : integer := 100000000;
--Outputs
signal data : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 10;
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
shared variable local_ram : LOCAL_MEMORY_T;-- := ( others => (others => '0'));
signal o_RAMAddr_nco : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others => '0');
signal o_RAMData_nco : std_logic_vector(0 to 31); -- nco to local ram
signal o_RAMWE_nco : std_logic := '0';
BEGIN
phase_incr <= Get_Cordic_Phase_Increment(FPGA_FREQUENCY, 1999);
-- Instantiate the Unit Under Test (UUT)
uut: nco PORT MAP (
clk => clk,
rst => rst,
ce => ce,
phase_offset => phase_offset,
phase_incr => phase_incr,
data => data
);
o_RAMData_nco <= std_logic_vector(data);
local_ram_ctrl_2 : process (clk) is
begin
if rising_edge(clk) then
if (o_RAMWE_nco = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco))) := o_RAMData_nco;
end if;
end if;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
wait;
end process;
process(clk)
begin
if(rising_edge(clk) )then
ce <= '1';
o_RAMWE_nco <= '1';
o_RAMAddr_nco <= std_logic_vector(unsigned(o_RAMAddr_nco) + 1);
end if;
end process;
write_data_proc : process
file sine_file : TEXT open WRITE_MODE is "sine.out";
variable wline : line;
begin
write(wline, to_integer(data));
writeline(sine_file, wline);
wait for clk_period;
end process;
END;
| mit | 62e7f75729a566e6dab8c0913e4fb515 | 0.571249 | 3.425647 | false | false | false | false |
qynvi/rtl-lcdfsm | lcdfsm.vhd | 1 | 5,512 | -- William Fan
-- 02/11/2011
-- LCD Display Driver RTL
-- vector table
-- direction of horizontal display --->
-- _ 012345
-- _ ABCDEF |
-- 0 > |
-- 1 >> |
-- 2 > |
-- 3 >> |
-- 4 > |
-- 5 >> |
-- 6 > |
-- 7 >> |
-- 8 > |
-- 9 >> |
-- 10 > |
-- 11 > > |
library ieee;
use ieee.std_logic_1164.all;
entity fsmlcd is
generic (clkdiv: positive := 500_000; -- divide down to 1ms clock cycles
sclk: natural := 3_000_000; -- slow clock toggles singular ">" prints to 60ms
fclk: natural := 1_500_000; -- fast clock toggles shadowed ">>" prints to 30ms
char: std_logic_vector(7 downto 0) := "00111110"; -- this is the code for ">"
blank: std_logic_vector(7 downto 0) := "00100000"); -- this is the code for a blank space
port(clk: in std_logic;
RS, RW, LCD_ON, BKL_ON: out std_logic;
E: buffer std_logic;
DB: out std_logic_vector(7 downto 0));
end fsmlcd;
architecture lcd of fsmlcd is
type state is (f1,f2,f3,f4,CD,DC,EM,
-- define all possible states from the vector table
a_0_1,
ab_1_2,
ab_2_0,
b_3_1,
b_4_2,
bc_5_3,
bc_6_1,
c_7_2,
c_8_3,
cd_9_4,
cd_10_2,
d_11_3,
d_12_4,
de_13_5,
de_14_3,
e_15_4,
e_16_5,
ef_17_6,
ef_18_4,
f_19_5,
f_20_0,
fa_21_1,
fa_22_5,
a_23_6,
a_24_1);
signal pr_state, nx_state: state;
shared variable cv: positive := clkdiv;
begin
lcd_on <= '1'; bkl_on <= '1';
process (clk)
variable count: integer range 0 to sclk := 0;
begin
if (clk'event and clk='1') then
count := count + 1;
if (count=cv) then
E <= NOT E;
count := 0;
end if;
end if;
end process;
process (E)
begin
if (E'EVENT AND E='1') then
pr_state <= nx_state;
end if;
end process;
process (pr_state)
-- state names arrangement motif
-- <a/b/c/d/e/f>_<time step>_<coordinate of the cursor>
begin
case pr_state is
-- initialization elements
when f1 =>
RS<='0'; RW<='0';
DB <= "0011XX00";
nx_state <= f2;
when f2 =>
RS<='0'; RW<='0';
DB <= "0011XX00";
nx_state <= f3;
when f3 =>
RS<='0'; RW<='0';
DB <= "0011XX00";
nx_state <= f4;
when f4 =>
RS<='0'; RW<='0';
DB <= "00111000";
nx_state <= cd;
when CD => -- clear display
RS<='0'; RW<='0';
DB <= "00000001";
nx_state <= dc;
when DC => -- display control vector
RS<='0'; RW<='0';
DB <= "00001100";
nx_state <= em;
when EM => -- entry mode
RS<='0'; RW<='0';
DB <= "00000110";
nx_state <= a_0_1;
-- loop elements
-- from <null> character, time = -1, cursor at 0
when a_0_1 =>
RS<='1'; RW<='0';
DB <= char;
cv := sclk;
nx_state <= ab_1_2;
when ab_1_2 =>
RS<='1'; RW<='0';
DB <= char;
cv := fclk;
nx_state <= ab_2_0;
when ab_2_0 =>
RS<='0'; RW<='0';
DB <= "10000000";
cv := clkdiv;
nx_state <= b_3_1;
when b_3_1 =>
RS<='1'; RW<='0';
DB <= blank;
cv := sclk;
nx_state <= b_4_2;
when b_4_2 =>
RS<='0'; RW<='0';
DB <= "10000010";
cv := clkdiv;
nx_state <= bc_5_3;
when bc_5_3 =>
RS<='1'; RW<='0';
DB <= char;
cv := fclk;
nx_state <= bc_6_1;
when bc_6_1 =>
RS<='0'; RW<='0';
DB <= "10000001";
cv := clkdiv;
nx_state <= c_7_2;
when c_7_2 =>
RS<='1'; RW<='0';
DB <= blank;
cv := sclk;
nx_state <= c_8_3;
when c_8_3 =>
RS<='0'; RW<='0';
DB <= "10000011";
cv := clkdiv;
nx_state <= cd_9_4;
when cd_9_4 =>
RS<='1'; RW<='0';
DB <= char;
cv := fclk;
nx_state <= cd_10_2;
when cd_10_2 =>
RS<='0'; RW<='0';
DB <= "10000010";
cv := clkdiv;
nx_state <= d_11_3;
when d_11_3 =>
RS<='1'; RW<='0';
DB <= blank;
cv := sclk;
nx_state <= d_12_4;
when d_12_4 =>
RS<='0'; RW<='0';
DB <= "10000101";
cv := clkdiv;
nx_state <= de_13_5;
when de_13_5 =>
RS<='1'; RW<='0';
DB <= char;
cv := fclk;
nx_state <= de_14_3;
when de_14_3 =>
RS<='0'; RW<='0';
DB <= "10000011";
cv := clkdiv;
nx_state <= e_15_4;
when e_15_4 =>
RS<='1'; RW<='0';
DB <= blank;
cv := sclk;
nx_state <= e_16_5;
when e_16_5 =>
RS<='0'; RW<='0';
DB <= "10000101";
cv := clkdiv;
nx_state <= ef_17_6;
when ef_17_6 =>
RS<='1'; RW<='0';
DB <= char;
cv := fclk;
nx_state <= ef_18_4;
when ef_18_4 =>
RS<='0'; RW<='0';
DB <= "10000100";
cv := clkdiv;
nx_state <= f_19_5;
when f_19_5 =>
RS<='1'; RW<='0';
DB <= blank;
cv := sclk;
nx_state <= f_20_0;
when f_20_0 =>
RS<='0'; RW<='0';
DB <= "10000000";
cv := clkdiv;
nx_state <= fa_21_1;
when fa_21_1 =>
RS<='1'; RW<='0';
DB <= char;
cv := fclk;
nx_state <= fa_22_5;
when fa_22_5 =>
RS<='0'; RW<='0';
DB <= "10000101";
cv := clkdiv;
nx_state <= a_23_6;
when a_23_6 =>
RS<='1'; RW<='0';
DB <= blank;
cv := sclk;
nx_state <= a_24_1;
when a_24_1 =>
RS<='0'; RW<='0';
DB <= "10000001";
cv := clkdiv;
nx_state <= ab_1_2;
end case;
end process;
end architecture;
| mit | b3c11cda21f736592efe830b4c19c0a0 | 0.439042 | 2.6 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/axi_i2s_adi.vhd | 1 | 12,135 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.i2s_controller;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_streaming_dma_rx_fifo;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
use adi_common_v1_00_a.axi_ctrlif;
entity axi_i2s_adi is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_SLOT_WIDTH : integer := 24;
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_DMA_TYPE : integer := 0;
C_NUM_CH : integer := 1;
C_HAS_TX : integer := 1;
C_HAS_RX : integer := 1
);
port
(
-- Serial Data interface
DATA_CLK_I : in std_logic;
BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0);
SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0);
-- AXI Streaming DMA TX interface
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
-- AXI Streaming DMA RX interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
--PL330 DMA TX interface
DMA_REQ_TX_ACLK : in std_logic;
DMA_REQ_TX_RSTN : in std_logic;
DMA_REQ_TX_DAVALID : in std_logic;
DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_TX_DAREADY : out std_logic;
DMA_REQ_TX_DRVALID : out std_logic;
DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_TX_DRLAST : out std_logic;
DMA_REQ_TX_DRREADY : in std_logic;
-- PL330 DMA RX interface
DMA_REQ_RX_ACLK : in std_logic;
DMA_REQ_RX_RSTN : in std_logic;
DMA_REQ_RX_DAVALID : in std_logic;
DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_RX_DAREADY : out std_logic;
DMA_REQ_RX_DRVALID : out std_logic;
DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_RX_DRLAST : out std_logic;
DMA_REQ_RX_DRREADY : in std_logic;
-- AXI bus interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : inout std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : inout std_logic;
S_AXI_AWREADY : inout std_logic
);
end entity axi_i2s_adi;
architecture Behavioral of axi_i2s_adi is
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal i2s_reset : std_logic;
signal tx_fifo_reset : std_logic;
signal tx_enable : Boolean;
signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal tx_ack : std_logic;
signal tx_stb : std_logic;
signal rx_enable : Boolean;
signal rx_fifo_reset : std_logic;
signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
signal rx_ack : std_logic;
signal rx_stb : std_logic;
signal bclk_div_rate : natural range 0 to 255;
signal lrclk_div_rate : natural range 0 to 255;
signal period_len : integer range 0 to 65535;
signal I2S_RESET_REG : std_logic_vector(31 downto 0);
signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8))));
-- Audio samples FIFO
constant RAM_ADDR_WIDTH : integer := 7;
type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
-- RX FIFO signals
signal audio_fifo_rx : RAM_TYPE;
signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
signal tvalid : std_logic := '0';
signal rx_tlast : std_logic;
signal drain_tx_dma : std_logic;
signal rx_sample : std_logic_vector(23 downto 0);
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 11;
signal rd_addr : integer range 0 to 11;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
signal tx_fifo_stb : std_logic;
signal rx_fifo_ack : std_logic;
signal cnt : integer range 0 to 2**16-1;
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
cnt <= 0;
else
cnt <= (cnt + 1) mod 2**16;
end if;
end if;
end process;
streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate
tx_fifo : entity axi_streaming_dma_tx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8),
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
out_stb => tx_stb,
out_ack => tx_ack,
out_data => tx_data
);
end generate;
streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate
rx_fifo : entity axi_streaming_dma_rx_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24
)
port map(
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
period_len => period_len,
in_stb => rx_stb,
in_ack => rx_ack,
in_data => rx_data,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8),
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
M_AXIS_TDATA(7 downto 0) <= (others => '0');
end generate;
pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
tx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 0
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => tx_fifo_reset,
enable => tx_enable,
in_data => wr_data(31 downto 8),
in_stb => tx_fifo_stb,
out_ack => tx_ack,
out_stb => tx_stb,
out_data => tx_data,
dclk => DMA_REQ_TX_ACLK,
dresetn => DMA_REQ_TX_RSTN,
davalid => DMA_REQ_TX_DAVALID,
daready => DMA_REQ_TX_DAREADY,
datype => DMA_REQ_TX_DATYPE,
drvalid => DMA_REQ_TX_DRVALID,
drready => DMA_REQ_TX_DRREADY,
drtype => DMA_REQ_TX_DRTYPE,
drlast => DMA_REQ_TX_DRLAST
);
end generate;
pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
rx_fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => FIFO_AWIDTH,
FIFO_DWIDTH => 24,
FIFO_DIRECTION => 1
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => rx_fifo_reset,
enable => rx_enable,
in_ack => rx_ack,
in_stb => rx_stb,
in_data => rx_data,
out_data => rx_sample,
out_ack => rx_fifo_ack,
dclk => DMA_REQ_RX_ACLK,
dresetn => DMA_REQ_RX_RSTN,
davalid => DMA_REQ_RX_DAVALID,
daready => DMA_REQ_RX_DAREADY,
datype => DMA_REQ_RX_DATYPE,
drvalid => DMA_REQ_RX_DRVALID,
drready => DMA_REQ_RX_DRREADY,
drtype => DMA_REQ_RX_DRTYPE,
drlast => DMA_REQ_RX_DRLAST
);
end generate;
ctrl : entity i2s_controller
generic map (
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_BCLK_POL => C_BCLK_POL,
C_LRCLK_POL => C_LRCLK_POL,
C_NUM_CH => C_NUM_CH,
C_HAS_TX => C_HAS_TX,
C_HAS_RX => C_HAS_RX
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
data_clk => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
tx_enable => tx_enable,
tx_ack => tx_ack,
tx_stb => tx_stb,
tx_data => tx_data,
rx_enable => rx_enable,
rx_ack => rx_ack,
rx_stb => rx_stb,
rx_data => rx_data,
bclk_div_rate => bclk_div_rate,
lrclk_div_rate => lrclk_div_rate
);
i2s_reset <= I2S_RESET_REG(0);
tx_fifo_reset <= I2S_RESET_REG(1);
rx_fifo_reset <= I2S_RESET_REG(2);
tx_enable <= I2S_CONTROL_REG(0) = '1';
rx_enable <= I2S_CONTROL_REG(1) = '1';
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_REG => 12
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
rd_stb => '1',
wr_addr => wr_addr,
wr_data => wr_data,
wr_ack => '1',
wr_stb => wr_stb
);
process(rd_addr)
begin
case rd_addr is
when 1 => rd_data <= I2S_CONTROL_REG and x"3";
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
when 6 => rd_data <= PERIOD_LEN_REG and x"ffff";
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
when others => rd_data <= (others => '0');
end case;
end process;
process(S_AXI_ACLK) is
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
I2S_RESET_REG <= (others => '0');
I2S_CONTROL_REG <= (others => '0');
I2S_CLK_CONTROL_REG <= (others => '0');
PERIOD_LEN_REG <= (others => '0');
else
-- Auto-clear the Reset Register bits
I2S_RESET_REG(0) <= '0';
I2S_RESET_REG(1) <= '0';
I2S_RESET_REG(2) <= '0';
if wr_stb = '1' then
case wr_addr is
when 0 => I2S_RESET_REG <= wr_data;
when 1 => I2S_CONTROL_REG <= wr_data;
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
when 6 => PERIOD_LEN_REG <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 1821688311f265c5fafebe3074fd9459 | 0.609806 | 2.497427 | false | false | false | false |
aylons/sp601_spi_test | hdl/modules/dcm/dcm_reset.vhd | 1 | 768 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity reset_dcm is
generic(cycles : positive := 100);
port (clk : in std_logic;
locked_i : in std_logic;
reset_o : out std_logic
); --reset ='1' enable ,i.e. reset dcm
end reset_dcm;
architecture Behavioral of reset_dcm is
begin
process(clk)
variable count : positive := cycles;
begin
if rising_edge(clk) then
if locked_i = '1' then
count := count - 1;
else
count := cycles;
reset_o <= '1';
end if;
if count = 0 then
reset_o <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 9fad10cbeca944f1b22ec34776f716f1 | 0.542969 | 3.588785 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/F_D_test.vhd | 1 | 3,803 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Ext_Mem_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
op_code_input: in std_logic_vector(4 downto 0);
mem_mux_input : in std_logic; --mickey mux
R1_regfile_input: in std_logic_vector(15 downto 0);
ALU_address_input,stack_address_input : in std_logic_vector(9 downto 0);
ALU_out_input : in std_logic_vector(15 downto 0);
Z_input: in std_logic;
NF_input: in std_logic;
V_input: in std_logic;
C_input: in std_logic;
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
load_store_address_input : in std_logic_vector(15 downto 0); --LDM
--------------------------------------------------------------------------------------------------------------------
pc_mux_output : out std_logic_vector(1 downto 0);
op_code_output: out std_logic_vector(4 downto 0);
mem_mux_output : out std_logic; --mickey mux
R1_regfile_output: out std_logic_vector(15 downto 0);
ALU_address_output,stack_address_output : out std_logic_vector(9 downto 0);
ALU_out_output : out std_logic_vector(15 downto 0);
Z_output: out std_logic;
NF_output: out std_logic;
V_output: out std_logic;
C_output: out std_logic;
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
load_store_address_output : out std_logic_vector(15 downto 0)
);
end Ext_Mem_Buffer;
architecture arch_Ext_Mem_Buffer of Ext_Mem_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
begin
pc_mux_map : nreg generic map (n=>2)port map(Clk,Rst,enable,pc_mux_input,pc_mux_output);
op_code_map : nreg generic map (n=>5)port map(Clk,Rst,enable,op_code_input,op_code_output);
mem_mux_map : Regis port map(Clk,Rst,enable,mem_mux_input,mem_mux_output);
R1_regfile_map : nreg generic map (n=>16)port map(Clk,Rst,enable,R1_regfile_input,R1_regfile_output);
ALU_address_map : nreg generic map (n=>10)port map(Clk,Rst,enable,ALU_address_input,ALU_address_output);
ALU_out_map : nreg generic map (n=>16)port map(Clk,Rst,enable,ALU_out_input,ALU_out_output);
Z_map : Regis port map(Clk,Rst,enable,Z_input,Z_output);
NF_map : Regis port map(Clk,Rst,enable,NF_input,NF_output);
V_map : Regis port map(Clk,Rst,enable,V_input,V_output);
C_map : Regis port map(Clk,Rst,enable,C_input,C_output);
outport_en_map : Regis port map(Clk,Rst,enable,outport_en_input,outport_en_output);
reg_write_map : Regis port map(Clk,Rst,enable,reg_write_input,reg_write_output);
mem_write_map : Regis port map(Clk,Rst,enable,mem_write_input,mem_write_output);
write_data_reg_mux_map : Regis port map(Clk,Rst,enable,write_data_reg_mux_input,write_data_reg_mux_output);
write_back_mux_map : nreg generic map (n=>16)port map(Clk,Rst,enable,write_back_mux_input,write_back_mux_output);
load_store_address_map : nreg generic map (n=>16)port map(Clk,Rst,enable,load_store_address_input,load_store_address_output);
end arch_Ext_Mem_Buffer;
| mit | 3a4d7994f45662ad2310a21fe7eeb5e5 | 0.641862 | 2.81287 | false | false | false | false |
EPiCS/soundgates | hardware/basic/sawtooth/sawtooth.vhd | 1 | 2,047 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - sawtooth.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Sawtooth wave generator
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity sawtooth is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end sawtooth;
architecture Behavioral of sawtooth is
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant upper : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant lower : signed (31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
begin
saw <= x;
CALC_SAW : process (clk, rst)
begin
if rst = '1' then
x <= offset;
else
if rising_edge(clk) then
if ce = '1' then
x <= x + incr;
if x > upper then
x <= lower;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | d62acab8d93826f1b88626dfaf30ce84 | 0.382511 | 3.776753 | false | false | false | false |
jandecaluwe/myhdl-examples | crusty_UK101/UK101AddressDecode/vhdl/pck_myhdl_08.vhd | 1 | 3,359 | -- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Mar 8 21:33:13 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
| mit | e1cce79e792be5208ed35f8ae54f55c4 | 0.600774 | 4.017943 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Decode_Ext_Buffer.vhd | 1 | 5,078 | library ieee;
use ieee.std_logic_1164.all;
entity D_E_Buffer is
Generic ( n : integer := 16);
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
--pc_mux : in std_logic_vector(1 downto 0);
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_read_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
--r1_load_mux : in std_logic; --deleted from desgin
r2_shift_mux_input : in std_logic;
r1_forward_mux_input : in std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
r2_forward_mux_input : in std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
write_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
flags_en_input : in std_logic;
flags_rti_en_input : in std_logic;
alu_control_input : in std_logic; --change it according to alu control (3 bit ****)علي حسب شغلك 'musgi'
mem_mux_input : in std_logic;
--stack_plus : in std_logic;
--stack_minus : in std_logic;
--stack_en : in std_logic_vector(1 downto 0);
--load_value_15_0 : in std_logic_vector(15 downto 0); --jump from fetch to ext (without decode)
load_store_address_input : in std_logic_vector(15 downto 0);
port1_data_input, port2_data_input : in std_logic_vector(16 downto 0);
--n : in std_logic
--pc_mux : out std_logic_vector(1 downto 0);
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_read_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
--r1_load_mux : out std_logic; --deleted from desgin
r2_shift_mux_output : out std_logic;
r1_forward_mux_output : out std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
r2_forward_mux_output : out std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
write_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
flags_en_output : out std_logic;
flags_rti_en_output : out std_logic;
alu_control_output : out std_logic; --change it according to alu control (3 bit ****)علي حسب شغلك 'musgi'
mem_mux_output : out std_logic;
--stack_plus : out std_logic;
--stack_minus : out std_logic;
--stack_en : out std_logic_vector(1 downto 0);
--load_value_15_0 : in std_logic_vector(15 downto 0); --jump from fetch to ext (without decode)
--load_store_address_output : out std_logic_vector(15 downto 0)
port1_data_output, port2_data_output : out std_logic_vector(16 downto 0)
--n : in std_logic
);
end D_E_Buffer;
architecture arch_D_E_Buffer of D_E_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
begin
outport_en_map : Regis port map(Clk,Rst,enable,outport_en_input,outport_en_output);
reg_write_map : Regis port map(Clk,Rst,enable,reg_write_input,reg_write_output);
mem_read_map : Regis port map(Clk,Rst,enable,mem_read_input,mem_read_output);
mem_write_map : Regis port map(Clk,Rst,enable,mem_write_input,mem_write_output);
write_data_reg_mux_map : Regis port map(Clk,Rst,enable,write_data_reg_mux_input,write_data_reg_mux_output);
r2_shift_mux_map : Regis port map(Clk,Rst,enable,r2_shift_mux_input,r2_shift_mux_output);
r1_forward_mux_map : Regis port map(Clk,Rst,enable,r1_forward_mux_input,r1_forward_mux_output);
r2_forward_mux_map : Regis port map(Clk,Rst,enable,r2_forward_mux_input,r2_forward_mux_output);
write_reg_mux_map : Regis port map(Clk,Rst,enable,write_reg_mux_input,write_reg_mux_output);
write_back_mux_map : nreg generic map (n=>16)port map(Clk,Rst,enable,write_back_mux_input,write_back_mux_output);
flags_en_map : Regis port map(Clk,Rst,enable,flags_en_input,flags_en_output);
flags_rti_en_map : Regis port map(Clk,Rst,enable,flags_rti_en_input,flags_rti_en_output);
alu_control_map : Regis port map(Clk,Rst,enable,alu_control_input,alu_control_output);
mem_mux_map : Regis port map(Clk,Rst,enable,mem_mux_input,mem_mux_output);
--load_store_address_map : nreg generic map (n=>16)port map(Clk,Rst,enable,load_store_address_input,load_store_address_output);
port1_data_map : nreg generic map (n=>16)port map(Clk,Rst,enable,port1_data_input,port1_data_output);
port2_data_map : nreg generic map (n=>16)port map(Clk,Rst,enable,port2_data_input,port2_data_output);
end arch_D_E_Buffer;
| mit | 6e416c1be1007b1dd1508e7c56284e2d | 0.657177 | 2.785242 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Dec_Ext_Buffer.vhd | 1 | 4,188 | library ieee;
use ieee.std_logic_1164.all;
entity D_E_Buffer is
Generic ( n : integer := 16);
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_read_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
r2_shift_mux_input : in std_logic;
r1_forward_mux_input : in std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
r2_forward_mux_input : in std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
write_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
flags_en_input : in std_logic;
flags_rti_en_input : in std_logic;
alu_control_input : in std_logic; --change it according to alu control (3 bit ****)علي حسب شغلك 'musgi'
mem_mux_input : in std_logic;
load_store_address_input : in std_logic_vector(15 downto 0);
port1_data_input, port2_data_input : in std_logic_vector(15 downto 0);
op_code_input: in std_logic_vector(4 downto 0);
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_read_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
r2_shift_mux_output : out std_logic;
r1_forward_mux_output : out std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
r2_forward_mux_output : out std_logic; --always 0 be 1 if only make forward so take signal from forward to mux to make it 1
write_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
flags_en_output : out std_logic;
flags_rti_en_output : out std_logic;
alu_control_output : out std_logic; --change it according to alu control (3 bit ****)علي حسب شغلك 'musgi'
mem_mux_output : out std_logic;
port1_data_output, port2_data_output : out std_logic_vector(15 downto 0)
);
end D_E_Buffer;
architecture arch_D_E_Buffer of D_E_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
begin
outport_en_map : Regis port map(Clk,Rst,'1',outport_en_input,outport_en_output);
reg_write_map : Regis port map(Clk,Rst,'1',reg_write_input,reg_write_output);
mem_read_map : Regis port map(Clk,Rst,'1',mem_read_input,mem_read_output);
mem_write_map : Regis port map(Clk,Rst,'1',mem_write_input,mem_write_output);
write_data_reg_mux_map : Regis port map(Clk,Rst,'1',write_data_reg_mux_input,write_data_reg_mux_output);
r2_shift_mux_map : Regis port map(Clk,Rst,'1',r2_shift_mux_input,r2_shift_mux_output);
r1_forward_mux_map : Regis port map(Clk,Rst,'1',r1_forward_mux_input,r1_forward_mux_output);
r2_forward_mux_map : Regis port map(Clk,Rst,'1',r2_forward_mux_input,r2_forward_mux_output);
write_reg_mux_map : Regis port map(Clk,Rst,'1',write_reg_mux_input,write_reg_mux_output);
write_back_mux_map : nreg generic map (n=>2)port map(Clk,Rst,'1',write_back_mux_input,write_back_mux_output);
flags_en_map : Regis port map(Clk,Rst,'1',flags_en_input,flags_en_output);
flags_rti_en_map : Regis port map(Clk,Rst,'1',flags_rti_en_input,flags_rti_en_output);
alu_control_map : Regis port map(Clk,Rst,'1',alu_control_input,alu_control_output);
mem_mux_map : Regis port map(Clk,Rst,'1',mem_mux_input,mem_mux_output);
port1_data_map : nreg generic map (n=>16)port map(Clk,Rst,'1',port1_data_input,port1_data_output);
port2_data_map : nreg generic map (n=>16)port map(Clk,Rst,'1',port2_data_input,port2_data_output);
end arch_D_E_Buffer;
| mit | 1bedcd38de0b20cbbdd2c88506c0406c | 0.647553 | 2.727749 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_sample_mul_v1_00_a/hdl/vhdl/hwt_sample_mul.vhd | 1 | 13,034 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sample_mul
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating mul envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sample_mul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sample_mul;
architecture Behavioral of hwt_sample_mul is
----------------------------------------------------------------
-- mulcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_mul : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_mul2: std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_mul : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_mul : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_mul2: std_logic_vector(0 to 31);
signal o_RAMWE_mul : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal mul_data : signed(63 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_mul <= std_logic_vector(mul_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_mul = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_mul))) := o_RAMData_mul;
else -- else needed, because add is consuming samples
i_RAMData_mul <= local_ram(to_integer(unsigned(o_RAMAddr_mul)));
i_RAMData_mul2<= local_ram(to_integer(unsigned(o_RAMAddr_mul2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_mul<= '0';
o_RAMAddr_mul <= (others => '0');
o_RAMAddr_mul2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_mul2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
mul_data <= signed(i_RAMData_mul) * signed(i_RAMData_mul2);
process_state <= 1;
when 1 =>
o_RAMData_mul <= std_logic_vector(resize(mul_data(31 downto 0), 32));
o_RAMWE_mul <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_mul <= '0';
o_RAMAddr_mul <= std_logic_vector(unsigned(o_RAMAddr_mul) + 1);
o_RAMAddr_mul2 <= std_logic_vector(unsigned(o_RAMAddr_mul2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_mul <= (others => '0');
o_RAMAddr_mul2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 41e51b04981777a122a65b7ffa59da6e | 0.488722 | 3.673619 | false | false | false | false |
aylons/sp601_spi_test | hdl/modules/master_controller/master_controller.vhd | 1 | 1,972 | -------------------------------------------------------------------------------
-- Title : Master controller
-- Project :
-------------------------------------------------------------------------------
-- File : master_controller.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-23
-- Last update: 2014-10-30
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple controller for master SPI
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-23 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity master_controller is
port (
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
spi_req_i : in std_logic;
spi_wen_o : out std_logic;
count_up_o : out std_logic
);
end entity master_controller;
architecture str of master_controller is
signal wen : std_logic := '1';
begin -- architecture str
send : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
wen <= '1';
else
if spi_req_i = '1' and en_i = '1' then
wen <= '1';
if wen = '0' then
count_up_o <= '1';
else
count_up_o <= '0';
end if;
else
wen <= '0';
count_up_o <= '0';
end if;
end if;
end if;
end process;
spi_wen_o <= wen;
end architecture str;
-------------------------------------------------------------------------------
| gpl-3.0 | 44044ae87a6e9bc0c73efd612be940a8 | 0.391481 | 4.277657 | false | false | false | false |
EPiCS/soundgates | hardware/basic/cordic/cordic_tb.vhd | 1 | 3,493 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:23:57 09/05/2013
-- Design Name:
-- Module Name: /home/soundgates/wave_generators/cordic/cordic_tb.vhd
-- Project Name: cordic
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: cordic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
use STD.textio.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY cordic_tb IS
END cordic_tb;
ARCHITECTURE behavior OF cordic_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT cordic
generic (
pipeline_stages : integer
);
PORT(
phi : in signed(31 downto 0); -- 0 <= phi <= pi/2
sin : out signed(31 downto 0);
cos : out signed(31 downto 0);
clk : in std_logic;
rst : in std_logic;
ce : in std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic;
signal ce : std_logic;
constant phi_init : signed(31 downto 0) := to_signed(0, 32);
signal phi : signed(31 downto 0) := to_signed(0, 32);--phi_init;
--Outputs
signal sin : signed(31 downto 0);
signal cos : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
constant cordic_p_stages : integer := 16;
constant standard_cordic_offset : integer := integer(real(MATH_PI * 2.0 * 2 ** SOUNDGATE_FIX_PT_SCALING));
constant f_sin : integer := 2000; -- in Hz
constant f_fpga : integer := 100000000; -- in Hz;
constant phase_incr : signed(31 downto 0) := Get_Cordic_Phase_Increment(f_fpga, f_sin);
-- simulation related signals
signal init_done : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: cordic
generic map (
pipeline_stages => cordic_p_stages
)
PORT MAP (
clk => clk,
rst => rst,
ce => ce,
phi => phi,
sin => sin,
cos => cos
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
rst <= '1';
wait for cordic_p_stages * clk_period;
rst <= '0';
ce <= '1';
init_done <= '1';
loop
if phi >= standard_cordic_offset then
phi <= phase_incr;
else
phi <= phi + phase_incr;
end if;
wait for clk_period;
end loop;
end process;
END;
| mit | 9982be238e72c71a4d64151fd3c8ee8d | 0.564558 | 3.881111 | false | false | false | false |
EPiCS/soundgates | hardware/basic/add/add.vhd | 1 | 1,479 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - add.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: adds up two samples or control units
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity add is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end add;
architecture Behavioral of add is
begin
adder : process (clk, rst, ce)
begin
if rising_edge(clk) then
if ce = '1' then
output <= wave1 + wave2;
end if;
end if;
end process;
end Behavioral;
| mit | 7bc1c4d54fce9500d1b437ca19f2e720 | 0.350913 | 3.763359 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_36b_v1_00_a/hdl/vhdl/axi_hdmi_tx_36b.vhd | 1 | 11,608 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_hdmi_tx_36b is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(35 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hdmi_tx_36b;
architecture IMP of axi_hdmi_tx_36b is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(35 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_be : in std_logic_vector(7 downto 0);
vdma_last : in std_logic;
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
hdmi_ref_clk => hdmi_ref_clk,
hdmi_clk => hdmi_clk,
hdmi_vsync => hdmi_vsync,
hdmi_hsync => hdmi_hsync,
hdmi_data_e => hdmi_data_e,
hdmi_data => hdmi_data,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_fs_ret => vdma_fs_ret,
vdma_empty => vdma_empty,
vdma_almost_empty => vdma_almost_empty,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_be => M_AXIS_MM2S_TKEEP,
vdma_last => M_AXIS_MM2S_TLAST,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
debug_trigger => debug_trigger,
debug_data => debug_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | a845057fddd135e577648f81330fd0e6 | 0.518091 | 3.245178 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_decode.vhd | 1 | 10,173 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Sample decoder. Extract sample words and write to sample ----
---- buffer. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
-- Revision 1.3 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.2 2004/06/16 19:04:09 gedra
-- Fixed a few bugs.
--
-- Revision 1.1 2004/06/13 18:07:47 gedra
-- Frame decoder and sample extractor
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx_decode is
generic (DATA_WIDTH: integer range 16 to 32;
ADDR_WIDTH: integer range 8 to 64);
port (
up_clk: in std_logic;
conf_rxen: in std_logic;
conf_sample: in std_logic;
conf_valid: in std_logic;
conf_mode: in std_logic_vector(3 downto 0);
conf_blken: in std_logic;
conf_valen: in std_logic;
conf_useren: in std_logic;
conf_staten: in std_logic;
conf_paren: in std_logic;
lock: in std_logic;
rx_data: in std_logic;
rx_data_en: in std_logic;
rx_block_start: in std_logic;
rx_frame_start: in std_logic;
rx_channel_a: in std_logic;
wr_en: out std_logic;
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
stat_paritya: out std_logic;
stat_parityb: out std_logic;
stat_lsbf: out std_logic;
stat_hsbf: out std_logic);
end rx_decode;
architecture rtl of rx_decode is
signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK);
signal sampst : samp_states;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal samp_start : integer range 0 to 15;
signal tmp_data : std_logic_vector(31 downto 0);
signal tmp_stat : std_logic_vector(4 downto 0);
signal valid, next_is_a, blk_start : std_logic;
begin
-- output data
OD32: if DATA_WIDTH = 32 generate
--wr_data(31 downto 27) <= tmp_stat;
wr_data(31 downto 0) <= tmp_data(31 downto 0);
end generate OD32;
OD16: if DATA_WIDTH = 16 generate
wr_data(15 downto 0) <= tmp_data(15 downto 0);
end generate OD16;
-- State machine extracting audio samples
SAEX: process (up_clk, conf_rxen)
begin -- process SAEX
if conf_rxen = '0' then
adr_cnt <= 0;
next_is_a <= '1';
wr_en <= '0';
wr_addr <= (others => '0');
tmp_data <= (others => '0');
par_cnt <= 0;
blk_start <= '0';
stat_paritya <= '0';
stat_parityb <= '0';
stat_lsbf <= '0';
stat_hsbf <= '0';
valid <= '0';
bit_cnt <= 0;
sampst <= IDLE;
tmp_stat <= (others => '0');
elsif rising_edge(up_clk) then
--extract and store samples
case sampst is
when IDLE =>
next_is_a <= '1';
if lock = '1' and conf_sample = '1' then
sampst <= CHA_SYNC;
end if;
when CHA_SYNC =>
wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1));
wr_en <= '0';
bit_cnt <= 0;
valid <= '0';
par_cnt <= 0;
stat_paritya <= '0';
stat_parityb <= '0';
stat_lsbf <= '0';
stat_hsbf <= '0';
--tmp_data(31 downto 0) <= (others => '0');
if rx_block_start = '1' and conf_blken = '1' then
blk_start <= '1';
end if;
if rx_frame_start = '1' then --and rx_channel_a = '1' then --next_is_a then
next_is_a <= rx_channel_a;
if(rx_channel_a = '1') then
tmp_data(31 downto 0) <= (others => '0');
end if;
sampst <= GET_SAMP;
end if;
when GET_SAMP =>
tmp_stat(0) <= blk_start;
if rx_data_en = '1' then
bit_cnt <= bit_cnt + 1;
-- audio part
if bit_cnt >= samp_start and bit_cnt <= 23 then
if(next_is_a = '1') then
tmp_data(bit_cnt - samp_start) <= rx_data;
else
tmp_data(bit_cnt + 16 - samp_start) <= rx_data;
end if;
end if;
-- status bits
case bit_cnt is
when 24 => -- validity bit
valid <= rx_data;
if conf_valen = '1' then
tmp_stat(1) <= rx_data;
else
tmp_stat(1) <= '0';
end if;
when 25 => -- user data
if conf_useren = '1' then
tmp_stat(2) <= rx_data;
else
tmp_stat(2) <= '0';
end if;
when 26 => -- channel status
if conf_staten = '1' then
tmp_stat(3) <= rx_data;
else
tmp_stat(3) <= '0';
end if;
when 27 => -- parity bit
if conf_paren = '1' then
tmp_stat(4) <= rx_data;
else
tmp_stat(4) <= '0';
end if;
when others =>
null;
end case;
-- parity: count number of 1's
if rx_data = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
if bit_cnt = 28 then
sampst <= PAR_CHK;
end if;
when PAR_CHK =>
blk_start <= '0';
if (((valid = '0' and conf_valid = '1') or conf_valid = '0') and (next_is_a = '0')) then
wr_en <= '1';
end if;
-- parity check
if par_cnt mod 2 /= 0 then
if rx_channel_a = '1' then
stat_paritya <= '1';
else
stat_parityb <= '1';
end if;
end if;
-- address counter
if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then
adr_cnt <= adr_cnt + 1;
else
adr_cnt <= 0;
stat_hsbf <= '1'; -- signal high buffer full
end if;
if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then
stat_lsbf <= '1'; -- signal low buffer full
end if;
sampst <= CHA_SYNC;
when others =>
sampst <= IDLE;
end case;
end if;
end process SAEX;
-- determine sample resolution from mode bits in 32bit mode
M32: if DATA_WIDTH = 32 generate
samp_start <= 8 when conf_mode = "0000" else
7 when conf_mode = "0001" else
6 when conf_mode = "0010" else
5 when conf_mode = "0011" else
4 when conf_mode = "0100" else
3 when conf_mode = "0101" else
2 when conf_mode = "0110" else
1 when conf_mode = "0111" else
0 when conf_mode = "1000" else
8;
end generate M32;
-- in 16bit mode only 16bit of audio is supported
M16: if DATA_WIDTH = 16 generate
samp_start <= 8;
end generate M16;
end rtl;
| mit | 6f3e75c43d119db4cde006338a1d6b06 | 0.423179 | 4.215914 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_phase_det.vhd | 1 | 15,071 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Oversampling phase detector. Decodes bi-phase mark encoded ----
---- signal. Clock must be at least 8 times higher than bit rate. ----
---- The SPDIF bitrate must be minimum 100kHz. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2004/07/19 16:58:37 gedra
-- Fixed bug.
--
-- Revision 1.4 2004/07/12 17:06:41 gedra
-- Fixed bug with lock event generation.
--
-- Revision 1.3 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
-- Revision 1.2 2004/06/13 18:08:50 gedra
-- Renamed generic and cleaned some lint's
--
-- Revision 1.1 2004/06/06 15:43:02 gedra
-- Early version of the bi-phase mark decoder.
--
--
library ieee;
use ieee.std_logic_1164.all;
entity rx_phase_det is
generic (AXI_FREQ: natural := 100); -- WishBone frequency in MHz
port (
up_clk: in std_logic; -- wishbone clock
rxen: in std_logic; -- phase detector enable
spdif: in std_logic; -- SPDIF input signal
lock: out std_logic; -- true if locked to spdif input
lock_evt: out std_logic; -- lock status change event
rx_data: out std_logic; -- recevied data
rx_data_en: out std_logic; -- received data enable
rx_block_start: out std_logic; -- start-of-block pulse
rx_frame_start: out std_logic; -- start-of-frame pulse
rx_channel_a: out std_logic; -- 1 if channel A frame is recevied
rx_error: out std_logic; -- signal error was detected
ud_a_en: out std_logic; -- user data ch. A enable
ud_b_en: out std_logic; -- user data ch. B enable
cs_a_en: out std_logic; -- channel status ch. A enable
cs_b_en: out std_logic); -- channel status ch. B enable);
end rx_phase_det;
architecture rtl of rx_phase_det is
constant TRANSITIONS : integer := 70;
constant FRAMES_FOR_LOCK : integer := 3;
signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * AXI_FREQ;
signal last_cnt, max_thres : integer range 0 to 16 * AXI_FREQ;
signal minpulse, minp, min_thres: integer range 0 to 8 * AXI_FREQ;
signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
signal trans_cnt : integer range 0 to TRANSITIONS;
signal valid, p_long, p_short: std_logic;
type pulse_type is (ZERO, SHORT, MED, LONG);
type pulse_array is array (0 to 3) of pulse_type;
signal preamble: pulse_array;
signal new_pulse, short_idx, ilock: std_logic;
type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX);
signal framerx : frame_state;
signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK;
signal bit_cnt : integer range 0 to 63;
signal pre_cnt : integer range 0 to 7;
type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z);
signal new_preamble, last_preamble : preamble_types;
signal irx_channel_a, zilock : std_logic;
begin
-- Pulse width analyzer
PHDET: process (up_clk, rxen)
begin
if rxen = '0' then -- reset by configuration register bit
maxpulse <= 0;
maxp <= 0;
mp_cnt <= 0;
zspdif <= '0';
zspdif_in <= '0';
spdif_in <= '0';
trans_cnt <= 0;
minpulse <= 0;
minp <= 8 * AXI_FREQ;
last_cnt <= 0;
trans <= '0';
valid <= '0';
preamble <= (ZERO, ZERO, ZERO, ZERO);
max_thres <= 0;
min_thres <= 0;
new_preamble <= NONE;
ztrans <= '0';
new_pulse <= '0';
else
if rising_edge(up_clk) then
-- sync spdif signal to wishbone clock
zspdif <= spdif;
spdif_in <= zspdif;
-- find the longest pulse, which is the bi-phase violation
-- also find the shortest pulse
zspdif_in <= spdif_in;
if zspdif_in /= spdif_in then -- input transition
mp_cnt <= 0;
trans <= '1';
last_cnt <= mp_cnt;
if trans_cnt > 0 then
if mp_cnt > maxp then
maxp <= mp_cnt;
end if;
if mp_cnt < minp then
minp <= mp_cnt;
end if;
end if;
else
trans <= '0';
if mp_cnt < 16 * AXI_FREQ then
mp_cnt <= mp_cnt + 1;
end if;
end if;
-- transition counting
if trans = '1' then
if trans_cnt < TRANSITIONS then
trans_cnt <= trans_cnt + 1;
else
-- the max/min pulse length is updated after given # of transitions
trans_cnt <= 0;
maxpulse <= maxp;
maxp <= 0;
minpulse <= minp;
minp <= 8 * AXI_FREQ;
min_thres <= maxp / 2;
if maxp < 11 then
max_thres <= maxp - 1;
else
max_thres <= maxp - 3;
end if;
end if;
end if;
-- detection of valid SPDIF signal
if maxpulse > 6 then
valid <= '1';
else
valid <= '0';
end if;
-- bit decoding
if trans = '1' then
if (last_cnt < min_thres) and (last_cnt > 0) then
p_short <= '1';
preamble(0) <= SHORT;
else
p_short <= '0';
end if;
if last_cnt >= max_thres then
p_long <= '1';
preamble(0) <= LONG;
else
p_long <= '0';
end if;
if last_cnt = 0 then
preamble(0) <= ZERO;
end if;
if (last_cnt < max_thres) and (last_cnt >= min_thres) then
preamble(0) <= MED;
end if;
preamble(3) <= preamble(2);
preamble(2) <= preamble(1);
preamble(1) <= preamble(0);
end if;
-- preamble detection
if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT
and preamble(0) = SHORT then
new_preamble <= PRE_X;
elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT
and preamble(0) = MED then
new_preamble <= PRE_Y;
elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT
and preamble(0) = LONG then
new_preamble <= PRE_Z;
else
new_preamble <= NONE;
end if;
-- delayed transition pulse for the state machine
ztrans <= trans;
new_pulse <= ztrans;
end if;
end if;
end process;
lock <= ilock;
rx_channel_a <= irx_channel_a;
-- State machine that hunt for and lock onto sub-frames
FRX: process (up_clk, rxen)
begin
if rxen = '0' then
framerx <= IDLE;
ilock <= '0';
zilock <= '0';
rx_data <= '0';
rx_data_en <= '0';
rx_block_start <= '0';
rx_frame_start <= '0';
irx_channel_a <= '0';
ud_a_en <= '0';
ud_b_en <= '0';
cs_a_en <= '0';
cs_b_en <= '0';
rx_error <= '0';
lock_evt <= '0';
bit_cnt <= 0;
pre_cnt <= 0;
short_idx <= '0';
frame_cnt <= 0;
last_preamble <= NONE;
elsif rising_edge(up_clk) then
zilock <= ilock;
if zilock /= ilock then -- generate event for event reg.
lock_evt <= '1';
else
lock_evt <= '0';
end if;
case framerx is
when IDLE => -- wait for recevier to be enabled
if valid = '1' then
framerx <= HUNT;
end if;
when HUNT => -- wait for preamble detection
frame_cnt <= 0;
ilock <= '0';
rx_error <= '0';
if new_pulse = '1' then
if new_preamble /= NONE then
framerx <= FRAMESTART;
end if;
end if;
when FRAMESTART => -- reset sub-frame bit counter
bit_cnt <= 0;
pre_cnt <= 0;
if frame_cnt < FRAMES_FOR_LOCK then
frame_cnt <= frame_cnt + 1;
else
ilock <= '1';
end if;
last_preamble <= new_preamble;
short_idx <= '0';
rx_frame_start <= '1';
rx_block_start <= '0';
framerx <= FRAME_RX;
when FRAME_RX => -- receive complete sub-frame
if new_pulse = '1' then
if bit_cnt < 28 then
case preamble(0) is
when ZERO =>
short_idx <= '0';
when SHORT =>
if short_idx = '0' then
short_idx <= '1';
else
-- two short pulses is a logical '1'
bit_cnt <= bit_cnt + 1;
short_idx <= '0';
rx_data <= '1';
rx_data_en <= ilock;
-- user data enable for the capture register
if bit_cnt = 25 and ilock = '1' then
ud_a_en <= irx_channel_a;
ud_b_en <= not irx_channel_a;
end if;
-- channel status enable for the capture register
if bit_cnt = 26 and ilock = '1' then
cs_a_en <= irx_channel_a;
cs_b_en <= not irx_channel_a;
end if;
end if;
when MED =>
-- medium pulse is logical '0'
bit_cnt <= bit_cnt + 1;
rx_data <= '0';
rx_data_en <= ilock;
short_idx <= '0';
-- user data enable for the capture register
if bit_cnt = 25 and ilock = '1' then
ud_a_en <= irx_channel_a;
ud_b_en <= not irx_channel_a;
end if;
-- channel status enable for the capture register
if bit_cnt = 26 and ilock = '1' then
cs_a_en <= irx_channel_a;
cs_b_en <= not irx_channel_a;
end if;
when LONG =>
short_idx <= '0';
when others =>
framerx <= HUNT;
end case;
else
-- there should be 4 pulses in preamble
if pre_cnt < 7 then
pre_cnt <= pre_cnt + 1;
else
rx_error <= '1';
framerx <= HUNT;
end if;
-- check for correct preamble here
if pre_cnt = 3 then
case last_preamble is
when PRE_X =>
if new_preamble = PRE_Y then
framerx <= FRAMESTART;
irx_channel_a <= '0';
else
rx_error <= '1';
framerx <= HUNT;
end if;
when PRE_Y =>
if new_preamble = PRE_X or new_preamble = PRE_Z then
irx_channel_a <= '1';
-- start of new block?
if new_preamble = PRE_Z then
rx_block_start <= '1';
end if;
framerx <= FRAMESTART;
else
rx_error <= '1';
framerx <= HUNT;
end if;
when PRE_Z =>
if new_preamble = PRE_Y then
irx_channel_a <= '0';
framerx <= FRAMESTART;
else
rx_error <= '1';
framerx <= HUNT;
end if;
when others =>
rx_error <= '1';
framerx <= HUNT;
end case;
end if;
end if;
else
rx_data_en <= '0';
rx_block_start <= '0';
rx_frame_start <= '0';
ud_a_en <= '0';
ud_b_en <= '0';
cs_a_en <= '0';
cs_b_en <= '0';
end if;
when others =>
framerx <= IDLE;
end case;
end if;
end process FRX;
end rtl;
| mit | 65409ba55ff280c810f1e07e6a79f73f | 0.426714 | 4.340726 | false | false | false | false |
EPiCS/soundgates | hardware/basic/white_noise/PRBS.vhd | 1 | 1,870 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - PRBS.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Generates pseudo random bit sequences, as needed for
-- white noise, implementing "Fibonacci-LFSR"
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity PRBS is
Generic ( constant levels : integer := 32);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ce : in STD_LOGIC;
rand : out STD_LOGIC_VECTOR (levels - 1 downto 0));
end PRBS;
architecture Behavioral of PRBS is
signal seed : std_logic_vector (levels-1 downto 0) := (0 => '1', others => '0');
signal feedback : std_logic := '1';
constant polynome : std_logic_vector (0 to levels-1) := "10110100000000001011010000000000";
begin
rand <= seed;
process (clk, rst, seed, ce)
begin
if ce = '1' then
if (rst = '1') then
seed <= (0 => '1', others => '0');
end if;
if (rising_edge(clk)) then
feedback <= feedback xor (seed(5) xor (seed(3) xor (seed(2) xor seed(0))));
seed <= feedback & seed (levels - 1 downto 1);
end if;
end if;
end process;
end Behavioral;
| mit | c240650c1c96200c54664a850fb99512 | 0.432086 | 3.456562 | false | false | false | false |
aylons/sp601_spi_test | hdl/modules/dcm/clk_wiz_v3_3.vhd | 1 | 6,775 | -- file: clk_wiz_v3_3.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___200.000______0.000______50.0______132.912____233.106
-- CLK_OUT2____80.000______0.000______50.0______159.282____233.106
-- CLK_OUT3____50.000______0.000______50.0______174.921____233.106
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_wiz_v3_3 is
port
(-- Clock in ports
CLK_IN_P : in std_logic;
CLK_IN_N : in std_logic;
-- Clock out ports
clk_200M : out std_logic;
clk_80M : out std_logic;
clk_50M : out std_logic;
-- Status and control signals
reset_i : in std_logic;
locked_o : out std_logic
);
end clk_wiz_v3_3;
architecture xilinx of clk_wiz_v3_3 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v3_3,clk_wiz_v3_3,{component_name=clk_wiz_v3_3,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=5.0,clkin2_period=5.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFGDS
port map
(O => clkin1,
I => CLK_IN_P,
IB => CLK_IN_N);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 2,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 5.0,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => locked_o,
RST => reset_i,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => clk_200M,
I => clkout0);
clkout2_buf : BUFG
port map
(O => clk_80M,
I => clkout1);
clkout3_buf : BUFG
port map
(O => clk_50M,
I => clkout2);
end xilinx;
| gpl-3.0 | 6c9f1006f3f61d3bab37aeae8fbdc1f0 | 0.585387 | 3.975939 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/vhdl/axi_hdmi_tx_16b.vhd | 1 | 11,608 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_hdmi_tx_16b is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hdmi_tx_16b;
architecture IMP of axi_hdmi_tx_16b is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
hdmi_ref_clk : in std_logic;
hdmi_clk : out std_logic;
hdmi_vsync : out std_logic;
hdmi_hsync : out std_logic;
hdmi_data_e : out std_logic;
hdmi_data : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_fs_ret : in std_logic;
vdma_empty : in std_logic;
vdma_almost_empty : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_be : in std_logic_vector(7 downto 0);
vdma_last : in std_logic;
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
hdmi_ref_clk => hdmi_ref_clk,
hdmi_clk => hdmi_clk,
hdmi_vsync => hdmi_vsync,
hdmi_hsync => hdmi_hsync,
hdmi_data_e => hdmi_data_e,
hdmi_data => hdmi_data,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_fs_ret => vdma_fs_ret,
vdma_empty => vdma_empty,
vdma_almost_empty => vdma_almost_empty,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_be => M_AXIS_MM2S_TKEEP,
vdma_last => M_AXIS_MM2S_TLAST,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
debug_trigger => debug_trigger,
debug_data => debug_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 2971cba76c90d2b12f76f77069a8ab03 | 0.518091 | 3.245178 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/MemoryStage.vhd | 1 | 2,490 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity Memory is
PORT ( Clk, rst, Mux_Selector, Memory_WriteEnable, Stack_WriteEnable, StackPushPop : in std_logic; --StackPushPop 0: psuh, 1: pop
--FlagEnable : in std_logic;
InputAddress, LoadAdress : in std_logic_vector(9 downto 0);
DataIn : in std_logic_vector(15 downto 0);
DataOut, M0, M1 : out std_logic_vector (15 downto 0);
Flags_Z_In, Flags_NF_In, Flags_V_In, Flags_C_In : in std_logic;
Flags_Z_Out, Flags_NF_Out, Flags_V_Out, Flags_C_Out : out std_logic;
BranchOpCode_In : in std_logic_vector (4 downto 0);
BranchR1_In : in std_logic_vector (15 downto 0);
Branch_Out : out std_logic_vector (15 downto 0)
);
END Memory;
architecture arch_Memory of Memory is
Component syncram2 is
Generic ( n : integer := 8);
port ( clk,rst : in std_logic;
we, weStack, stackPushPop : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end component;
signal Address : std_logic_vector(9 downto 0);
signal DO,DO0,DO1 : std_logic_vector(15 downto 0);
signal dontCare1, dontCare2 : std_logic_vector (15 downto 0);
begin
Mem : syncram2 generic map(n=>10) port map(Clk, rst, Memory_WriteEnable, Stack_WriteEnable, StackPushPop, Address, datain,DO,DO0,DO1);
process (clk,rst)
begin
if rising_edge(clk) then
if Mux_Selector = '0' then
Address <= InputAddress;
else
Address <= LoadAdress;
end if;
DataOut <= DO;
M0 <= DO0;
M1 <= DO1;
if BranchOpCode_In = "10100" and Flags_Z_In = '1' then --JZ Rdst
Branch_Out <= BranchR1_In;
Flags_Z_Out <= '0';
elsif BranchOpCode_In = "10101" and Flags_NF_In = '1' then --JN Rdst
Branch_Out <= BranchR1_In;
Flags_NF_Out <= '0';
elsif BranchOpCode_In = "10110" and Flags_C_In = '1' then --JC Rdst
Branch_Out <= BranchR1_In;
Flags_C_Out <= '0';
elsif BranchOpCode_In = "10111" then --JMP Rdst
Branch_Out <= BranchR1_In;
elsif BranchOpCode_In = "11001" then --RET
Branch_Out <= DO;
elsif BranchOpCode_In = "11010" then --RTI --FLAGS RESTORED
Branch_Out <= DO;
Flags_Z_Out <= '0';
Flags_NF_Out <= '0';
Flags_C_Out <= '0';
Flags_V_Out <= '0';
else
Flags_Z_Out <= Flags_Z_In;
Flags_NF_Out <= Flags_NF_In;
Flags_C_Out <= Flags_C_In;
Flags_V_Out <= Flags_V_In;
end if;
end if;
end process;
end architecture arch_Memory; | mit | ec68f28f0bacec0cde4f0687b62bb059 | 0.6751 | 2.703583 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_4.vhd | 1 | 1,275 | -- File: gray_counter_4.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_4 is
port (
gray_count: out unsigned(3 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_4;
architecture MyHDL of gray_counter_4 is
signal even: std_logic;
signal gray: unsigned(3 downto 0);
begin
GRAY_COUNTER_4_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(3 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((4 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 4-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_4_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | 4703042e40e99b5ba7fc9f6421595b8b | 0.557647 | 3.373016 | false | false | false | false |
EPiCS/soundgates | hardware/basic/iir/iir.vhdl | 1 | 5,136 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - iir.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: IIR filter with order IIR_ORDER and
-- feedback order IIR_FEEDBACK_ORDER
-- Direct-Form 2
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity iir is
generic(
IIR_ORDER : integer := 9 --> 10 coefficients
);
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
input_wave : in signed(31 downto 0);
config_valid : in std_logic;
config_index : in signed(31 downto 0);
config_data : in signed(31 downto 0);
config_feedback_valid: in std_logic;
config_feedback_index: in signed(31 downto 0);
config_feedback_data : in signed(31 downto 0);
wave : out signed(31 downto 0)
);
end iir;
architecture Behavioral of iir is
type mem32 is array (natural range <>) of signed(31 downto 0);
type mem64 is array (natural range <>) of signed(63 downto 0);
type mem96 is array (natural range <>) of signed(95 downto 0);
signal sum_mem64 : mem64(IIR_ORDER downto 0);
signal coeffs_mem32 : mem32(IIR_ORDER downto 0);
signal coeffs_feedback_mem32 : mem32(IIR_ORDER downto 0);
signal coeff_index : signed(31 downto 0);
signal coeff_feedback_index : signed(31 downto 0);
signal feedback_mem96 : mem96(IIR_ORDER downto 0);
signal inputs_mem32 : mem32(IIR_ORDER downto 0);
signal mult_mem64 : mem64(IIR_ORDER downto 0);
signal s_zero : signed (31 downto 0 ) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_zero64 : signed (63 downto 0 ) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 64);
type calc_states is (s_read, s_calc, s_shift);
signal state : calc_states;
signal i_coeff_index : integer := to_integer(config_index);
signal i_coeff_feedback_index : integer := to_integer(config_feedback_index);
signal output : signed(63 downto 0);
begin
output <= sum_mem64(IIR_ORDER) - feedback_mem96(IIR_ORDER)(63 downto 0);
wave <= output(31 downto 0);
CALCULATE : process (clk, rst, ce)
begin
if rst = '1' then
inputs_mem32 <= (others => (others => '0'));
mult_mem64 <= (others => (others => '0'));
state <= s_read;
sum_mem64 <= (others => s_zero64);
else
if rising_edge(clk) then
case state is
when s_read =>
inputs_mem32(0) <= input_wave;
state <= s_calc;
sum_mem64 <= (others => s_zero64);-- TODO: das wäre für ein clock cycle output von 0 :-(
when s_calc =>
for i in 0 to IIR_ORDER loop
mult_mem64(i) <= coeffs_mem32(i) * inputs_mem32(i);
sum_mem64(i) <= sum_mem64(i) + mult_mem64(i);
feedback_mem96(i) <= coeffs_feedback_mem32(i) * sum_mem64(i);
end loop;
state <= s_shift;
when s_shift =>
for i in 1 to IIR_ORDER loop
inputs_mem32(i) <= inputs_mem32(i - 1);
sum_mem64(i) <= sum_mem64(i - 1);
feedback_mem96(i) <= feedback_mem96(i - 1);
end loop;
state <= s_read;
end case;
end if;
end if;
end process;
CONFIGURE_COEFFICIENTS : process (clk, rst)
begin
if rst = '1' then
coeffs_mem32 <= (others => (others => '0'));
else
if rising_edge(clk) then
if config_valid = '1' then
if coeff_index >= s_zero then
i_coeff_index <= to_integer(config_index);
coeffs_mem32(i_coeff_index) <= config_data;
end if;
end if;
end if;
end if;
end process;
CONFIGURE_FEEDBACK_COEFFICIENTS : process (clk, rst)
begin
if rst = '1' then
coeffs_feedback_mem32 <= (others => (others => '0'));
else
if rising_edge(clk) then
if config_feedback_valid = '1' then
if coeff_feedback_index >= s_zero then
i_coeff_feedback_index <= to_integer(config_feedback_index);
coeffs_feedback_mem32(i_coeff_feedback_index) <= config_feedback_data;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | 1b5438fba0ef73c4b06f233030d817b7 | 0.500584 | 3.597758 | false | true | false | false |
IslamKhaledH/ArchitecturePorject | Project/ALU.vhd | 1 | 6,579 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
--Mux bet B and Nbits(shifting kam bit)
--
entity ALU is
port (
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1: in std_logic_vector(15 downto 0);
R2: in std_logic_vector(15 downto 0);
Output: out std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Z: out std_logic;
NF: out std_logic;
v: out std_logic;
C: out std_logic
);
end ALU;
Architecture archi of ALU is
Component AddSubIncDec is
port(
R1,R2: in std_logic_vector(15 downto 0);
OutPut : out std_logic_vector(15 downto 0);
OpCode :in std_logic_vector(4 downto 0);
--Z: out std_logic;
--V: out std_logic;
C: out std_logic
--N: out std_logic
);
end component;
component Regis is
port( Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic);
end component;
signal TempOut : std_logic_vector(15 downto 0);
signal TempZ,TempC,TempC_Add,TempV,TempN,TempZ2,TempC2,TempV2,TempN2 : std_logic;
signal Output_signal: std_logic_vector(15 downto 0);
Begin
--F1: AddSubIncDec port map(R1,R2,TempOut,OpCode,TempZ,TempV,TempC,TempN);
F1: AddSubIncDec port map(R1,R2,TempOut,OpCode,TempC_Add);
F2: Regis port map(Clk,Rst,enable,TempZ,TempZ2);
F3: Regis port map(Clk,Rst,enable,TempC,TempC2);
F4: Regis port map(Clk,Rst,enable,TempV,TempV2);
F5: Regis port map(Clk,Rst,enable,TempN,TempN2);
-----------------------------------------------------------
TempC <= '0' when OpCode = "01010" else
'1' when OpCode = "01011" else
--TempC2 when OpCode = "00010" or OpCode = "00011" or OpCode = "10010" or OpCode = "10011" else
R1(0) when OpCode = "00111" else
TempC_Add when OpCode = "00010" or OpCode = "00011" or OpCode = "10010" or OpCode = "10011" else
R1(15) when OpCode = "00110";
TempV <= '1' when Output_signal(15) = '1' and R1(15) = '0' and R2(15) = '0' and OpCode = "00010" else
'1' when Output_signal(15) = '0' and R1(15) = '1' and R2(15) = '1' and OpCode = "00010" else
'1' when Output_signal(15) = '0' and R1(15) = '1' and R2(15) = '0' and OpCode = "00011" else
'1' when Output_signal(15) = '1' and R1(15) = '0' and R2(15) = '1' and OpCode = "00011" else
'1' when Output_signal(15) = '1' and R1(15) = '0' and OpCode = "10010" else
'1' when Output_signal(15) = '0' and R1(15) = '1' and OpCode = "10011" else
'0';
TempZ <= '1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "00010" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "00011" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "00100" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "00101" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "10000" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "10001" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "10010" else
'1' when Output_signal(15 downto 0) = "0000000000000000" and OpCode = "10011" else
'0';
TempN <= '1' when Output_signal(15) = '1' and OpCode = "00010" else
'1' when Output_signal(15) = '1' and OpCode = "00011" else
'1' when Output_signal(15) = '1' and OpCode = "00100" else
'1' when Output_signal(15) = '1' and OpCode = "00101" else
'1' when Output_signal(15) = '1' and OpCode = "10000" else
'1' when Output_signal(15) = '1' and OpCode = "10001" else
'1' when Output_signal(15) = '1' and OpCode = "10010" else
'1' when Output_signal(15) = '1' and OpCode = "10011" else
'0';
--------------------------------------
Output_signal <= R1(15 downto 0) when n = "0000" else
'0' & R1(15 downto 1) when n = "0001" and OpCode = "01001" else
"00" & R1(15 downto 2) when n = "0010" and OpCode = "01001" else
"000" & R1(15 downto 3) when n = "0011" and OpCode = "01001" else
"0000" & R1(15 downto 4) when n = "0100" and OpCode = "01001" else
"00000" & R1(15 downto 5) when n = "0101" and OpCode = "01001" else
"000000" & R1(15 downto 6) when n = "0110" and OpCode = "01001" else
"0000000" & R1(15 downto 7) when n = "0111" and OpCode = "01001" else
"00000000" & R1(15 downto 8) when n = "1000" and OpCode = "01001" else
"000000000" & R1(15 downto 9) when n = "1001" and OpCode = "01001" else
"0000000000" & R1(15 downto 10) when n = "1010" and OpCode = "01001" else
"00000000000" & R1(15 downto 11) when n = "1011" and OpCode = "01001" else
"000000000000" & R1(15 downto 12) when n = "1100" and OpCode = "01001" else
"0000000000000" & R1(15 downto 13) when n = "1101" and OpCode = "01001" else
"00000000000000" & R1(15 downto 14) when n = "1110" and OpCode = "01001" else
"000000000000000" & R1(15) when n = "1111" and OpCode = "01001" else
R1(15 downto 0) when n = "0000" and OpCode = "01000" else
R1(14 downto 0) & '0' when n = "0001" and OpCode = "01000" else
R1(13 downto 0) & "00" when n = "0010" and OpCode = "01000" else
R1(12 downto 0) & "000" when n = "0011" and OpCode = "01000" else
R1(11 downto 0) & "0000" when n = "0100" and OpCode = "01000" else
R1(10 downto 0) & "00000" when n = "0101" and OpCode = "01000" else
R1(9 downto 0) & "000000" when n = "0110" and OpCode = "01000" else
R1(8 downto 0) & "0000000" when n = "0111" and OpCode = "01000" else
R1(7 downto 0) & "00000000" when n = "1000" and OpCode = "01000" else
R1(6 downto 0) & "000000000" when n = "1001" and OpCode = "01000" else
R1(5 downto 0) & "0000000000" when n = "1010" and OpCode = "01000" else
R1(4 downto 0) & "00000000000" when n = "1011" and OpCode = "01000" else
R1(3 downto 0) & "000000000000" when n = "1100" and OpCode = "01000" else
R1(2 downto 0) & "0000000000000" when n = "1101" and OpCode = "01000" else
R1(1 downto 0) & "00000000000000" when n = "1110" and OpCode = "01000" else
R1(0)& "000000000000000" when n = "1111" and OpCode = "01000" else
R1 and R2 when OpCode ="00100" else
R1 or R2 when OpCode ="00101" else
not R1 when OpCode ="10000" else
TempC2 & R1(15 downto 1) when OpCode = "00111"else
R1(14 downto 0) & TempC2 when OpCode = "00110" else
(-R1) when OpCode = "10001" else
R1 when OpCode = "00001";
OutPut <= TempOut when OpCode = "00010" or OpCode = "00011" or OpCode = "10010" or OpCode = "10011" else
Output_signal;
c <= TempC;
z <= TempZ;
v <= TempV;
NF <= TempN;
end archi; | mit | 63d19578893f00f1310b1df9aa8bae78 | 0.617115 | 2.885526 | false | false | false | false |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/soc_system_inst.vhd | 1 | 17,357 | component soc_system is
port (
cart_io_ad_in : in std_logic_vector(15 downto 0) := (others => 'X'); -- ad_in
cart_io_ad_out : out std_logic_vector(15 downto 0); -- ad_out
cart_io_ad_outen : out std_logic; -- ad_outen
cart_io_ale_h : out std_logic; -- ale_h
cart_io_ale_l : out std_logic; -- ale_l
cart_io_read_n : out std_logic; -- read_n
cart_io_write_n : out std_logic; -- write_n
cart_led_out_led_read : out std_logic; -- led_read
cart_led_out_led_write : out std_logic; -- led_write
clk_clk : in std_logic := 'X'; -- clk
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_system;
u0 : component soc_system
port map (
cart_io_ad_in => CONNECTED_TO_cart_io_ad_in, -- cart_io.ad_in
cart_io_ad_out => CONNECTED_TO_cart_io_ad_out, -- .ad_out
cart_io_ad_outen => CONNECTED_TO_cart_io_ad_outen, -- .ad_outen
cart_io_ale_h => CONNECTED_TO_cart_io_ale_h, -- .ale_h
cart_io_ale_l => CONNECTED_TO_cart_io_ale_l, -- .ale_l
cart_io_read_n => CONNECTED_TO_cart_io_read_n, -- .read_n
cart_io_write_n => CONNECTED_TO_cart_io_write_n, -- .write_n
cart_led_out_led_read => CONNECTED_TO_cart_led_out_led_read, -- cart_led_out.led_read
cart_led_out_led_write => CONNECTED_TO_cart_led_out_led_write, -- .led_write
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| mit | 1549ac56be905514be0d3c673d525edd | 0.462983 | 2.910295 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_28.vhd | 1 | 1,286 | -- File: gray_counter_28.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_28 is
port (
gray_count: out unsigned(27 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_28;
architecture MyHDL of gray_counter_28 is
signal even: std_logic;
signal gray: unsigned(27 downto 0);
begin
GRAY_COUNTER_28_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(27 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((28 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 28-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_28_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | ff1d7b1989fdcbee1ec5bbe1b03c8f20 | 0.561431 | 3.402116 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/nco_sync/nco_sync.vhd | 1 | 3,818 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - nco_sync.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Synchronization of two oscillators
-- Whenever the master's phase ends, reset slave's phase.
-- Slave's frequency usually higher and not dividable by
-- master's frequency
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity nco_sync is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SAW
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
master_phase_offset : in signed(31 downto 0);
master_phase_incr : in signed(31 downto 0);
slave_phase_offset : in signed(31 downto 0);
slave_phase_incr : in signed(31 downto 0);
soundout : out signed(31 downto 0)
);
end nco_sync;
architecture Behavioral of nco_sync is
component sawtooth
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end component sawtooth;
component nco
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM_SLAVE : WAVEFORM_TYPE := WAVEFORM
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end component nco;
constant master_threshold : signed (31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal master_data : signed(31 downto 0);
signal slave_data : signed(31 downto 0);
signal slave_rst : std_logic := '0';
signal state : integer := 0;
begin
soundout <= slave_data;
SAWTOOTH_MASTER_INSTA : sawtooth
port map(
clk => clk,
ce => ce,
rst => rst,
incr => master_phase_incr,
offset => master_phase_offset,
saw => master_data );
NCO_INSTA : nco
Port map(
clk => clk,
rst => slave_rst,
ce => ce,
phase_offset => slave_phase_offset,
phase_incr => slave_phase_incr,
data => slave_data
);
SYNC_PROCESS : process (clk)
begin
if rising_edge(clk) then
if master_data = master_threshold then
case state is
when 0 =>
slave_rst <= '1';
state <= 1;
when 1 =>
slave_rst <= '0';
state <= 0;
when others =>
state <= 0;
end case;
elsif slave_rst = '1' then
slave_rst <= '0';
end if;
end if;
end process;
end Behavioral;
| mit | 4120e81e0ad9f4526ef2eb72c9e7b4c3 | 0.435568 | 3.944215 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/nreg.vhd | 1 | 451 | Library ieee;
Use ieee.std_logic_1164.all;
Entity nreg is
Generic ( n : integer := 16);
port( Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0));
end nreg;
Architecture arch_nreg of nreg is
begin
Process (Clk,Rst)
begin
if Rst = '1' then
q <= (others=>'0');
elsif clk'event and clk = '1' then
if (enable = '1') then
q <= d;
end if;
end if;
end process;
end arch_nreg;
| mit | 680e4b8e1e5425c9119a813a38ecd260 | 0.636364 | 2.700599 | false | false | false | false |
spiersad/ECGR4146-FIFO | FIFO_LOGIC.vhd | 1 | 2,359 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_LOGIC is
generic (N: integer := 8);
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic);
end entity FIFO_LOGIC;
architecture RTL of FIFO_LOGIC is
signal WPTR, RPTR: std_logic_vector(N-1 downto 0);
signal LASTOP: std_logic;
begin
SYNC: process (CLK) begin
if (CLK'event and CLK = '1') then
if (INIT = '1') then -- initialization --
WPTR <= (others => '0');
RPTR <= (others => '0');
LASTOP <= '0';
elsif (POP = '1' and empty = '0') then -- pop --
RPTR <= RPTR + 1;
LASTOP <= '0';
elsif (PUSH = '1' and FULL = '0') then -- push --
WPTR <= WPTR + 1;
LASTOP <= '1';
end if; -- otherwise all Fs hold their value --
end if;
end process SYNC;
COMB: process (PUSH, POP, WPTR, RPTR, LASTOP, FULL, EMPTY)
begin
-- full and empty flags --
if (RPTR = WPTR) then
if (LASTOP = '1') then
FULL <= '1';
empty <= '0';
else
FULL <= '0';
empty <= '1';
end if;
else
FULL <= '0';
empty <= '0';
end if;
-- address, write enable and nopush/nopop logic --
if (POP = '0' and PUSH = '0') then -- no operation --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '0';
NOPOP <= '0';
elsif (POP = '0' and PUSH = '1') then -- push only --
ADD <= WPTR;
NOPOP <= '0';
if (FULL = '0') then -- valid write condition --
WE <= '1';
NOPUSH <= '0';
else -- no write condition --
WE <= '0';
NOPUSH <= '1';
end if;
elsif (POP = '1' and PUSH = '0') then -- pop only --
ADD <= RPTR;
NOPUSH <= '0';
WE <= '0';
if (empty = '0') then
-- valid read condition --
NOPOP <= '0';
else
NOPOP <= '1'; -- no red condition --
end if;
else -- push and pop at same time \u2013
if (empty = '0') then -- valid pop --
ADD <= RPTR;
WE <= '0';
NOPUSH <= '1';
NOPOP <= '0';
else
ADD <= wptr;
WE <= '1';
NOPUSH <= '0';
NOPOP <= '1';
end if;
end if;
end process COMB;
end architecture RTL; | gpl-2.0 | 3bc82d6dfba81ea748d00ca1446e2da7 | 0.474777 | 3.313202 | false | false | false | false |
jandecaluwe/myhdl-examples | ChessPlayingFPGA/stack/vhdl/Stack.vhd | 1 | 3,091 | -- File: Stack.vhd
-- Generated by MyHDL 0.8
-- Date: Fri May 17 10:15:39 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity Stack is
port (
ToSPieceOut: out unsigned(5 downto 0);
ToSMaskOut: out unsigned(15 downto 0);
PieceIn: in unsigned(5 downto 0);
MaskIn: in unsigned(15 downto 0);
MaskReset: in unsigned(15 downto 0);
Enable: in std_logic;
PushPop: in std_logic;
Reset: in std_logic;
Clk: in std_logic
);
end entity Stack;
-- Stack module in MyHDL
--
-- This the MyHDL RTL code for the Stack module. It
-- can be converted to Verilog/VHDL and synthesized.
architecture MyHDL of Stack is
constant DEPTH: integer := 6;
signal StackWrite: std_logic;
signal WritePointer: unsigned(2 downto 0);
signal Pointer: unsigned(2 downto 0);
signal StackWriteData: unsigned(21 downto 0);
signal StackReadData: unsigned(21 downto 0);
signal NrItems: unsigned(2 downto 0);
signal ToSPiece: unsigned(5 downto 0);
signal ToSMask: unsigned(15 downto 0);
type t_array_Stack is array(0 to 5-1) of unsigned(21 downto 0);
signal Stack: t_array_Stack;
begin
STACK_CONTROL: process (Clk) is
begin
if rising_edge(Clk) then
if (Reset = '1') then
StackWrite <= '0';
WritePointer <= to_unsigned(0, 3);
StackWriteData <= to_unsigned(0, 22);
NrItems <= to_unsigned(0, 3);
ToSPiece <= to_unsigned(0, 6);
Pointer <= to_unsigned(0, 3);
ToSMask <= to_unsigned(65535, 16);
else
StackWrite <= '0';
if (MaskReset /= 0) then
ToSMask <= (ToSMask and (not MaskReset));
elsif (bool(PushPop) and bool(Enable)) then
ToSPiece <= PieceIn;
ToSMask <= MaskIn;
NrItems <= (NrItems + 1);
if (NrItems > 0) then
StackWriteData <= unsigned'(ToSPiece & ToSMask);
StackWrite <= '1';
Pointer <= WritePointer;
if (signed(resize(WritePointer, 4)) < (DEPTH - 2)) then
WritePointer <= (WritePointer + 1);
end if;
end if;
elsif ((not bool(PushPop)) and bool(Enable)) then
ToSPiece <= StackReadData(22-1 downto 16);
ToSMask <= StackReadData(16-1 downto 0);
NrItems <= (NrItems - 1);
WritePointer <= Pointer;
if (Pointer > 0) then
Pointer <= (Pointer - 1);
end if;
end if;
end if;
end if;
end process STACK_CONTROL;
STACK_WRITE_STACK: process (Clk) is
begin
if rising_edge(Clk) then
if bool(StackWrite) then
Stack(to_integer(Pointer)) <= StackWriteData;
end if;
end if;
end process STACK_WRITE_STACK;
StackReadData <= Stack(to_integer(Pointer));
ToSPieceOut <= ToSPiece;
ToSMaskOut <= ToSMask;
end architecture MyHDL;
| mit | 151f39cf838266ed04bfc99b27b1cea7 | 0.570366 | 3.760341 | false | false | false | false |
jandecaluwe/myhdl-examples | crusty_UK101/UK101AddressDecode/vhdl/UK101AddressDecode.vhd | 1 | 997 | -- File: UK101AddressDecode.vhd
-- Generated by MyHDL 0.8dev
-- Date: Fri Mar 8 21:33:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity UK101AddressDecode is
port (
AL: in unsigned(15 downto 0);
MonitorRom: out std_logic;
ACIA: out std_logic;
KeyBoardPort: out std_logic;
VideoMem: out std_logic;
BasicRom: out std_logic;
Ram: out std_logic
);
end entity UK101AddressDecode;
-- UK101 address map decoder.
--
-- Source: http://www.gifford.co.uk/~coredump/ukarch.htm
architecture MyHDL of UK101AddressDecode is
begin
MonitorRom <= stdl((63488 <= AL) and (AL <= 65535));
ACIA <= stdl((61440 <= AL) and (AL <= 63487));
KeyBoardPort <= stdl((56320 <= AL) and (AL <= 57343));
VideoMem <= stdl((53248 <= AL) and (AL <= 54271));
BasicRom <= stdl((40960 <= AL) and (AL <= 49151));
Ram <= stdl((0 <= AL) and (AL <= 8191));
end architecture MyHDL;
| mit | 8c8fdb4820d79d36e5a9811ed5e42703 | 0.638917 | 3.07716 | false | false | false | false |
jandecaluwe/myhdl-examples | crusty_UK101/FourToSeven/vhdl/pck_myhdl_08.vhd | 1 | 3,359 | -- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Mon Mar 25 09:12:03 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
| mit | cb6befe076c336ad267726b55f1c7dfe | 0.601072 | 4.022754 | false | false | false | false |
EPiCS/soundgates | hardware/basic/cordic/cordic_stage.vhd | 1 | 3,260 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - cordic_stage.vhd
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Part of the cordic implementation
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity cordic_stage is
Generic( stage : integer := 1;
alpha : real := 0.5
);
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ce : in STD_LOGIC;
x : in SIGNED (31 downto 0);
y : in SIGNED (31 downto 0);
z : in SIGNED (31 downto 0);
x_n : out SIGNED (31 downto 0);
y_n : out SIGNED (31 downto 0);
z_n : out SIGNED (31 downto 0)
);
end cordic_stage;
architecture Behavioral of cordic_stage is
-- registers
signal x_next : signed(31 downto 0) := (others => '0');
signal y_next : signed(31 downto 0) := (others => '0');
signal z_next : signed(31 downto 0) := (others => '0');
-- intermediate signals
signal x_next_i : signed(31 downto 0);
signal y_next_i : signed(31 downto 0);
signal z_next_i : signed(31 downto 0);
constant arctan_init : real := ARCTAN(alpha) * 2**SOUNDGATE_FIX_PT_SCALING;
constant scaled_arctan : signed(31 downto 0) := to_signed(integer(arctan_init), 32);
signal y_shift : signed(31 downto 0);
signal x_shift : signed(31 downto 0);
begin
SHIFT_PROCESS : process(x, y)
begin
y_shift <= shift_right(y, stage); -- x 2^-stage
x_shift <= shift_right(x, stage);
end process;
ARTIHM_PROCESS : process(x, y, z, x_shift, y_shift)
variable x_next : signed(31 downto 0);
variable y_next : signed(31 downto 0);
variable z_next : signed(31 downto 0);
begin
if z(31) = '0' then -- sgn = + 1
x_next := x + (-y_shift);
y_next := x_shift + y;
z_next := z + (-scaled_arctan);
else -- sgn = -1
x_next := x + y_shift;
y_next := (-x_shift) + y;
z_next := z + scaled_arctan;
end if;
x_next_i <= x_next;
y_next_i <= y_next;
z_next_i <= z_next;
end process;
REG_PROCESS : process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
x_next <= (others => '0');
y_next <= (others => '0');
z_next <= (others => '0');
elsif ce = '1' then
x_next <= x_next_i;
y_next <= y_next_i;
z_next <= z_next_i;
end if;
end if;
end process;
x_n <= x_next;
y_n <= y_next;
z_n <= z_next;
end Behavioral;
| mit | f3850807cc7bf0de231c466de7bbe359 | 0.445706 | 3.276382 | false | false | false | false |
EPiCS/soundgates | hardware/basic/amplifier/amplifier_tb.vhd | 1 | 1,677 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY amplifier_tb IS
END amplifier_tb;
ARCHITECTURE behavior OF amplifier_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT amplifier
PORT(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave : in signed(31 downto 0);
percentage: in signed(31 downto 0);
amp : out signed(31 downto 0)
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
signal incr : signed(31 downto 0) := to_signed(integer(real( 0.1 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr2 : signed(31 downto 0) := to_signed(integer(real( 0.2 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--Outputs
signal rmp : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: amplifier PORT MAP (
clk => clk,
rst => rst,
ce => ce,
incr => incr,
incr2 => incr2,
rmp => rmp
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 5bf7b799e03340d8d3fc80c52b2b8885 | 0.581395 | 3.47205 | false | false | false | false |
spiersad/ECGR4146-FIFO | FIFO_TB.vhd | 1 | 1,826 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity FIFO_TB is
end FIFO_TB;
architecture behavior of FIFO_TB is
constant N: integer := 8;
constant M: integer := 64;
constant clk_period : time := 1 ns;
component FIFO
port(CLK, PUSH, POP, INIT: in std_logic;
DIN: in std_logic_vector(M-1 downto 0);
DOUT: out std_logic_vector(M-1 downto 0);
FULL, EMPTY, NOPUSH, NOPOP: out std_logic);
end component;
signal CLK, PUSH, POP, INIT: std_logic := '0';
signal DIN: std_logic_vector(M-1 downto 0) := std_logic_vector(to_unsigned(5, M));
signal DOUT: std_logic_vector(M-1 downto 0);
signal FULL, EMPTY, NOPUSH, NOPOP: std_logic;
begin
uut: FIFO port map(CLK => CLK, PUSH => PUSH, POP => POP,
INIT => INIT, DIN => DIN, DOUT => DOUT,
FULL => FULL, EMPTY => EMPTY,
NOPUSH => NOPUSH, NOPOP => NOPOP);
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
process
begin
init <= '1';
wait for 1 ns;
init <= '0';
wait for 1 ns;
din <= std_logic_vector(to_unsigned(5, M));
push <= '1';
wait for 1 ns;
push <= '0';
wait for 1 ns;
din <= std_logic_vector(to_unsigned(30, M));
push <= '1';
wait for 1 ns;
push <= '0';
wait for 1 ns;
din <= std_logic_vector(to_unsigned(255, M));
push <= '1';
wait for 1 ns;
push <= '0';
wait for 1 ns;
pop <= '1';
wait for 1 ns;
pop <= '0';
wait for 1 ns;
pop <= '1';
wait for 1 ns;
pop <= '0';
wait;
end process;
end behavior; | gpl-2.0 | bbeb9eb5ff050ddd2e6b63b7f552c2fd | 0.508762 | 3.451796 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/axi_spdif_rx.vhd | 1 | 17,240 | ------------------------------------------------------------------------------
-- axi_spdif_rx.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_spdif_rx.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Dec 15 12:04:13 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_spdif_rx_v1_00_a;
use axi_spdif_rx_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH --
-- C_S_AXI_ADDR_WIDTH --
-- C_S_AXI_MIN_SIZE --
-- C_USE_WSTRB --
-- C_DPHASE_TIMEOUT --
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY --
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK --
-- S_AXI_ARESETN --
-- S_AXI_AWADDR --
-- S_AXI_AWVALID --
-- S_AXI_WDATA --
-- S_AXI_WSTRB --
-- S_AXI_WVALID --
-- S_AXI_BREADY --
-- S_AXI_ARADDR --
-- S_AXI_ARVALID --
-- S_AXI_RREADY --
-- S_AXI_ARREADY --
-- S_AXI_RDATA --
-- S_AXI_RRESP --
-- S_AXI_RVALID --
-- S_AXI_WREADY --
-- S_AXI_BRESP --
-- S_AXI_BVALID --
-- S_AXI_AWREADY --
------------------------------------------------------------------------------
entity axi_spdif_rx is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 8;
CH_ST_CAPTURE : integer := 1;
AXI_FREQ : natural := 100;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
rx_int_o: out std_logic;
spdif_rx_i: in std_logic;
spdif_rx_i_osc: out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
--ACLK : in std_logic;
--ARESETN : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_spdif_rx;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_spdif_rx is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 8;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_spdif_rx_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
CH_ST_CAPTURE => CH_ST_CAPTURE,
AXI_FREQ => AXI_FREQ,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
rx_int_o => rx_int_o,
spdif_rx_i => spdif_rx_i,
spdif_rx_i_osc => spdif_rx_i_osc,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 702f2113541d23b89ceb00f3de4485d0 | 0.436195 | 4.097932 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_sinus_v1_00_a/hdl/vhdl/hwt_sinus.vhd | 1 | 12,187 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sinus
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Hardware thread for a sine wave
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sinus is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sinus;
architecture Behavioral of hwt_sinus is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component nco is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SIN
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end component nco;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_IDLE, STATE_REFRESH_HWT_ARGS, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := clog2(C_LOCAL_RAM_SIZE); -- 6
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_nco : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_nco : std_logic_vector(0 to 31); -- nco to local ram
signal i_RAMData_nco : std_logic_vector(0 to 31); -- local ram to nco
signal o_RAMWE_nco : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
----------------------------------------------------------------
-- Hardware arguements
----------------------------------------------------------------
signal hwtio : hwtio_t;
-- arg[0] = destination address
-- arg[1] = phase offset
-- arg[2] = phase increment
-- argc = 3
constant hwt_argc : integer := 3;
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal nco_ce : std_logic; -- nco clock enable (like a start/stop signal)
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
signal nco_data : signed(31 downto 0);
signal destaddr : std_logic_vector(DWORD_WIDTH - 1 downto 0);
signal phaseoffset : std_logic_vector(31 downto 0);
signal phaseincr : std_logic_vector(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant NCO_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NCO_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Component related wiring
-----------------------------------
destaddr <= hwtio.argv(0);
phaseoffset <= hwtio.argv(1);
phaseincr <= hwtio.argv(2);
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_nco <= std_logic_vector(nco_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
nco_inst : nco
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ,
WAVEFORM => SIN
)
port map(
clk => clk,
rst => rst,
ce => nco_ce,
phase_offset => signed(phaseoffset),
phase_incr => signed(phaseincr),
data => nco_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_nco = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco))) := o_RAMData_nco;
--else -- else not needed, because nco is not consuming any samples
-- i_RAMData_nco <= local_ram(conv_integer(unsigned(o_RAMAddr_nco)));
end if;
end if;
end process;
NCO_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
osif_ctrl_signal <= (others => '0');
state <= STATE_IDLE;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
nco_ce <= '0';
o_RAMWE_nco <= '0';
state_inner_process <= '0';
-- Initialize hwt args
hwtio.f_step <= 0;
hwtio.base_addr <= (others => '0');
done := False;
elsif rising_edge(clk) then
nco_ce <= '0';
o_RAMWE_nco <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
when STATE_IDLE =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = NCO_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_HWT_ARGS;
elsif osif_ctrl_signal = NCO_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_HWT_ARGS =>
get_hwt_args(i_osif, o_osif, i_memif, o_memif, hwtio, hwt_argc, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_nco <= '1';
nco_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_nco <= std_logic_vector(unsigned(o_RAMAddr_nco) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_nco <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", destaddr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, destaddr, ignore, done);
if done then
state <= STATE_IDLE;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
| mit | a35d3f5b950ee3a8ee3bf2ab7f822876 | 0.468488 | 3.778605 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/nco/nco.vhd | 1 | 6,446 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - nco.vhd
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Numeric controlled oscillator top level entity
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity nco is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SIN
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
phase_offset : in signed(31 downto 0);
phase_incr : in signed(31 downto 0);
data : out signed(31 downto 0)
);
end nco;
architecture Behavioral of nco is
--------------------------------------------------------------------------------
-- Cordic related components and signals
--------------------------------------------------------------------------------
component cordic
generic ( pipeline_stages : integer := 24 );
port (
phi : in signed(31 downto 0); -- 0 < phi < 2 * pi
sin : out signed(31 downto 0);
cos : out signed(31 downto 0);
clk : in std_logic; -- clock
rst : in std_logic; -- reset
ce : in std_logic -- enable
);
end component cordic;
component sawtooth
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end component sawtooth;
component square
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
duty_on : in signed(31 downto 0);
duty_off: in signed(31 downto 0);
sq : out signed(31 downto 0)
);
end component square;
component triangle
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
tri : out signed(31 downto 0)
);
end component triangle;
constant cordic_pipeline_stages : integer := 16;
constant standard_cordic_offset : integer := integer(real(MATH_PI * 2.0 * 2 ** SOUNDGATE_FIX_PT_SCALING));
signal cordic_phi_offset : signed(31 downto 0) := (others => '0');
signal cordic_phi_incr : signed(31 downto 0) := (others => '0');
signal cordic_phi_acc : signed(31 downto 0) := (others => '0');
signal cordic_threshold : signed(31 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- FOO related components and signals
--------------------------------------------------------------------------------
begin
SIN_GENERATOR : if WAVEFORM = SIN generate
CORDIC_INSTA : cordic
generic map(
pipeline_stages => cordic_pipeline_stages
)
port map(
clk => clk,
rst => rst,
ce => ce,
phi => cordic_phi_acc,
sin => data,
cos => open );
PHASE_STIMULIS_PROCESS : process(clk, rst)
begin
if rst = '1' then
cordic_phi_acc <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if (cordic_phi_acc + phase_incr) > standard_cordic_offset then
cordic_phi_acc <= phase_incr - (standard_cordic_offset - cordic_phi_acc);
else
cordic_phi_acc <= cordic_phi_acc + phase_incr;
end if;
end if;
end if;
end process;
end generate SIN_GENERATOR;
--------------------------------------------------------------------------------
-- SQUARE_GENERATOR : if WAVEFORM = SQU generate
--
-- SQUARE_INSTA : square
-- port map(
-- clk => clk,
-- ce => ce,
-- rst => rst,
-- incr => phase_incr,
-- offset => phase_offset,
-- duty_on => duty_on,
-- duty_off=> duty_off,
-- sq => data );
--
-- end generate SQUARE_GENERATOR;
--------------------------------------------------------------------------------
TRIANGLE_GENERATOR : if WAVEFORM = TRI generate
TRIANGLE_INSTA : triangle
port map(
clk => clk,
ce => ce,
rst => rst,
incr => phase_incr,
offset => phase_offset,
tri => data );
end generate TRIANGLE_GENERATOR;
--------------------------------------------------------------------------------
SAWTOOTH_GENERATOR : if WAVEFORM = SAW generate
SAWTOOTH_INSTA : sawtooth
port map(
clk => clk,
ce => ce,
rst => rst,
incr => phase_incr,
offset => phase_offset,
saw => data );
end generate SAWTOOTH_GENERATOR;
--------------------------------------------------------------------------------
end Behavioral; | mit | 90559fb30aa5417c2b8c1edbbc73ee1c | 0.370773 | 4.578125 | false | false | false | false |
EPiCS/soundgates | hardware/basic/ramp/ramp_tb.vhd | 1 | 1,634 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY ramp_tb IS
END ramp_tb;
ARCHITECTURE behavior OF ramp_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ramp
PORT(
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
incr : IN signed(31 downto 0);
incr2 : IN signed(31 downto 0);
rmp : OUT signed(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
signal incr : signed(31 downto 0) := to_signed(integer(real( 0.1 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr2 : signed(31 downto 0) := to_signed(integer(real( 0.2 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--Outputs
signal rmp : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ramp PORT MAP (
clk => clk,
rst => rst,
ce => ce,
incr => incr,
incr2 => incr2,
rmp => rmp
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | afbf4a83c9cb1d688bdaed1c1f529f32 | 0.578335 | 3.44 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/gen_event_reg.vhd | 1 | 5,357 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Generic event register. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
-- Revision 1.3 2004/06/06 15:42:20 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2 2004/06/04 15:55:07 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1 2004/06/03 17:49:26 gedra
-- Generic event register. Used in both receiver and transmitter.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
entity gen_event_reg is
generic (DATA_WIDTH: integer:=32);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
evt_wr: in std_logic; -- event register write
evt_rd: in std_logic; -- event register read
evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
evt_en: in std_logic; -- irq enable
evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
evt_irq: out std_logic); -- interrupt request
end gen_event_reg;
architecture rtl of gen_event_reg is
signal evt_internal, zero: std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
evt_dout <= evt_internal when evt_rd = '1' else (others => '0');
zero <= (others => '0');
-- IRQ generation:
-- IRQ signal will pulse low when writing to the event register. This will
-- capture situations when not all active events are cleared or an event happens
-- at the same time as it is cleared.
IR: process (clk)
begin
if rising_edge(clk) then
if ((evt_internal and evt_mask) /= zero) and evt_wr = '0'
and evt_en = '1' then
evt_irq <= '1';
else
evt_irq <= '0';
end if;
end if;
end process IR;
-- event register generation
EVTREG: for k in evt_din'range generate
EBIT: process (clk, rst)
begin
if rst = '1' then
evt_internal(k) <= '0';
else
if rising_edge(clk) then
if event(k)= '1' then -- set event
evt_internal(k) <= '1';
elsif evt_wr = '1' and evt_din(k) = '1' then -- clear event
evt_internal(k) <= '0';
end if;
end if;
end if;
end process EBIT;
end generate EVTREG;
end rtl;
| mit | c07c1d9815e02db3cecd01d4f8e36a71 | 0.428971 | 4.813118 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/noise/noise_tb.vhd | 1 | 1,467 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY noise_tb IS
END noise_tb;
ARCHITECTURE behavior OF noise_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT noise
GENERIC(
NOISE : NOISE_TYPE := WHITE
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
data : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
--Outputs
signal data : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: noise PORT MAP (
clk => clk,
rst => rst,
ce => ce,
data => data
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 068040b33e06793ad5b5725158b1b7e5 | 0.591002 | 3.6675 | false | false | false | false |
jandecaluwe/myhdl-examples | ChessPlayingFPGA/stack/vhdl/pck_myhdl_08.vhd | 1 | 3,356 | -- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8
-- Date: Fri May 17 10:15:39 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
| mit | e4eb2d3fd01513429cc967c858037950 | 0.600715 | 4.023981 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_nco_sync_v1_00_a/hdl/vhdl/hwt_nco_sync.vhd | 1 | 15,485 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_nco_sync_sync
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for a synchronized numeric controlled
-- oscillator
--
-- Synchronization of two oscillators
-- Whenever the master's phase ends, reset slave's phase.
-- Slave's frequency usually higher and not dividable by
-- master's frequency
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_nco_sync is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NCO_SYNC_TPYE : integer := 2
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_nco_sync;
architecture Behavioral of hwt_nco_sync is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component nco_sync is
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SAW -- sync nco eignet sich eigentlich nur für square oder saw
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
master_phase_offset : in signed(31 downto 0);
master_phase_incr : in signed(31 downto 0);
slave_phase_offset : in signed(31 downto 0);
slave_phase_incr : in signed(31 downto 0);
soundout : out signed(31 downto 0)
);
end component nco_sync;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 1024;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 10;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_nco_sync : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_nco_sync : std_logic_vector(0 to 31); -- nco_sync to local ram
signal i_RAMData_nco_sync : std_logic_vector(0 to 31); -- local ram to nco_sync
signal o_RAMWE_nco_sync : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal nco_sync_ce : std_logic; -- nco_sync clock enable (like a start/stop signal)
signal master_offset_addr : std_logic_vector(31 downto 0);
signal master_incr_addr : std_logic_vector(31 downto 0);
signal slave_offset_addr : std_logic_vector(31 downto 0);
signal slave_incr_addr : std_logic_vector(31 downto 0);
signal master_phase_offset : std_logic_vector(31 downto 0);
signal master_phase_incr : std_logic_vector(31 downto 0);
signal slave_phase_offset : std_logic_vector(31 downto 0);
signal slave_phase_incr : std_logic_vector(31 downto 0);
signal nco_sync_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant nco_sync_START : std_logic_vector(31 downto 0) := x"0000000F";
constant nco_sync_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_nco_sync <= std_logic_vector(nco_sync_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stufff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
nco_sync_inst : nco_sync
generic map(
FPGA_FREQUENCY => SND_COMP_CLK_FREQ,
WAVEFORM => WAVEFORM_TYPE'val(SND_COMP_NCO_TPYE)
)
port map(
clk => clk,
rst => rst,
ce => nco_sync_ce,
master_phase_offset => signed(master_phase_offset),
master_phase_incr => signed(master_phase_incr),
slave_phase_offset => signed(slave_phase_offset),
slave_phase_incr => signed(slave_phase_incr),
soundout => nco_sync_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_nco_sync = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_nco_sync))) := o_RAMData_nco_sync;
--else -- else not needed, because nco_sync is not consuming any samples
-- i_RAMData_nco_sync <= local_ram(conv_integer(unsigned(o_RAMAddr_nco_sync)));
end if;
end if;
end process;
NCO_SYNC_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
nco_sync_ce <= '0';
o_RAMWE_nco_sync <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
nco_sync_ce <= '0';
o_RAMWE_nco_sync <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
master_offset_addr <= snd_comp_header.opt_arg_addr;
master_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
master_offset_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 8);
slave_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 12);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = nco_sync_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = nco_sync_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_MASTER_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, master_offset_addr, master_phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_MASTER_PHASE_INCR =>
memif_read_word(i_memif, o_memif, master_incr_addr, master_phase_incr, done);
if done then
state <= STATE_REFRESH_MASTER_INPUT_PHASE_OFFSET;
end if;
when STATE_REFRESH_MASTER_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, slave_offset_addr, slave_phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_SLAVE_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_SLAVE_PHASE_INCR =>
memif_read_word(i_memif, o_memif, slave_incr_addr, slave_phase_incr, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_nco_sync <= '1';
nco_sync_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_nco_sync <= std_logic_vector(unsigned(o_RAMAddr_nco_sync) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_nco_sync <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | ec20579f697c883c5c7924b61c4ca4df | 0.50281 | 3.724561 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_1c_v1_00_a/hdl/vhdl/axi_adc_1c.vhd | 1 | 12,167 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_adc_1c is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(7 downto 0);
adc_data_in_n : in std_logic_vector(7 downto 0);
adc_data_or_p : in std_logic;
adc_data_or_n : in std_logic;
delay_clk : in std_logic;
up_status : out std_logic_vector(7 downto 0);
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(15 downto 0);
up_dbg_trigger : out std_logic;
up_dbg_data : out std_logic_vector(163 downto 0);
S_AXIS_S2MM_CLK : in std_logic;
S_AXIS_S2MM_TVALID : out std_logic;
S_AXIS_S2MM_TDATA : out std_logic_vector(63 downto 0);
S_AXIS_S2MM_TKEEP : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TLAST : out std_logic;
S_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_adc_1c;
architecture IMP of axi_adc_1c is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(7 downto 0);
adc_data_in_n : in std_logic_vector(7 downto 0);
adc_data_or_p : in std_logic;
adc_data_or_n : in std_logic;
dma_clk : in std_logic;
dma_valid : out std_logic;
dma_data : out std_logic_vector(63 downto 0);
dma_be : out std_logic_vector(7 downto 0);
dma_last : out std_logic;
dma_ready : in std_logic;
delay_clk : in std_logic;
up_status : out std_logic_vector(7 downto 0);
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(15 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
up_dbg_trigger <= ipif_Bus2IP_CS(0);
up_dbg_data(163) <= ipif_Bus2IP_RNW;
up_dbg_data(162 downto 162) <= ipif_Bus2IP_CS;
up_dbg_data(161) <= ipif_IP2Bus_WrAck;
up_dbg_data(160) <= ipif_IP2Bus_RdAck;
up_dbg_data(159 downto 128) <= ipif_Bus2IP_Addr;
up_dbg_data(127 downto 96) <= ipif_Bus2IP_RdCE;
up_dbg_data( 95 downto 64) <= ipif_Bus2IP_WrCE;
up_dbg_data( 63 downto 32) <= ipif_Bus2IP_Data;
up_dbg_data( 31 downto 0) <= ipif_IP2Bus_Data;
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_CF_BUFTYPE => C_CF_BUFTYPE
)
port map
(
adc_clk_in_p => adc_clk_in_p,
adc_clk_in_n => adc_clk_in_n,
adc_data_in_p => adc_data_in_p,
adc_data_in_n => adc_data_in_n,
adc_data_or_p => adc_data_or_p,
adc_data_or_n => adc_data_or_n,
dma_clk => S_AXIS_S2MM_CLK,
dma_valid => S_AXIS_S2MM_TVALID,
dma_data => S_AXIS_S2MM_TDATA,
dma_be => S_AXIS_S2MM_TKEEP,
dma_last => S_AXIS_S2MM_TLAST,
dma_ready => S_AXIS_S2MM_TREADY,
delay_clk => delay_clk,
up_status => up_status,
dma_dbg_data => dma_dbg_data,
dma_dbg_trigger => dma_dbg_trigger,
adc_clk => adc_clk,
adc_dbg_data => adc_dbg_data,
adc_dbg_trigger => adc_dbg_trigger,
adc_mon_valid => adc_mon_valid,
adc_mon_data => adc_mon_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | a3025ccba52453bfb2b7ad1a033306a3 | 0.549437 | 2.998275 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_fir_v1_00_a/hdl/vhdl/hwt_fir.vhd | 1 | 20,494 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_fir
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
-- Lukas Funke, University of Paderborn
--
-- description: Hardware thread for FIR Filter
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_fir is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_fir;
architecture Behavioral of hwt_fir is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
COMPONENT fir
generic(
FIR_ORDER : integer
);
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
coefficients : in mem16(FIR_ORDER downto 0);
x_in : in signed(23 downto 0);
y_out : out signed(23 downto 0)
);
END COMPONENT;
----------------------------------------------------------------
-- Signal declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_IDLE, STATE_REFRESH_HWT_ARGS, STATE_READ_MEM, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_fir : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_fir : std_logic_vector(0 to 31); -- fir to local ram
signal i_RAMData_fir : std_logic_vector(0 to 31); -- local ram to fir
signal o_RAMWE_fir : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
constant FIR_ORDER : integer := 28;
----------------------------------------------------------------
-- Memory management
----------------------------------------------------------------
signal ptr : natural range 0 to C_MAX_SAMPLE_COUNT-1;
----------------------------------------------------------------
-- Hardware arguements
----------------------------------------------------------------
signal hwtio : hwtio_t;
-- arg[0] = source address
-- arg[1] = destination address
-- arg[2] = 1. coefficient
-- arg[3] = 2. coefficient
-- ...
-- arg[30] = 29. coefficient
-- argc = # 2 + number of coefficients
constant hwt_argc : integer := 2 + FIR_ORDER + 1;
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
signal fir_ce : std_logic; -- fir clock enable (like a start/stop signal)
signal sourceaddr : std_logic_vector(31 downto 0);
signal destaddr : std_logic_vector(31 downto 0);
signal process_state : integer range 0 to 7;
signal x_i : signed(23 downto 0); -- 24 bit internal input sample
signal y_i : signed(23 downto 0); -- 24 bit internal output sample
signal sample_in : std_logic_vector(SAMPLE_WIDTH - 1 downto 0) := (others =>'0');
signal sample_out : std_logic_vector(SAMPLE_WIDTH - 1 downto 0);
signal coefficients_i16 : mem16(FIR_ORDER downto 0);
signal coefficients_i_0 : std_logic_vector(31 downto 0);
signal coefficients_i_1 : std_logic_vector(31 downto 0);
signal coefficients_i_2 : std_logic_vector(31 downto 0);
signal coefficients_i_3 : std_logic_vector(31 downto 0);
signal coefficients_i_4 : std_logic_vector(31 downto 0);
signal coefficients_i_5 : std_logic_vector(31 downto 0);
signal coefficients_i_6 : std_logic_vector(31 downto 0);
signal coefficients_i_7 : std_logic_vector(31 downto 0);
signal coefficients_i_8 : std_logic_vector(31 downto 0);
signal coefficients_i_9 : std_logic_vector(31 downto 0);
signal coefficients_i_10 : std_logic_vector(31 downto 0);
signal coefficients_i_11 : std_logic_vector(31 downto 0);
signal coefficients_i_12 : std_logic_vector(31 downto 0);
signal coefficients_i_13 : std_logic_vector(31 downto 0);
signal coefficients_i_14 : std_logic_vector(31 downto 0);
signal coefficients_i_15 : std_logic_vector(31 downto 0);
signal coefficients_i_16 : std_logic_vector(31 downto 0);
signal coefficients_i_17 : std_logic_vector(31 downto 0);
signal coefficients_i_18 : std_logic_vector(31 downto 0);
signal coefficients_i_19 : std_logic_vector(31 downto 0);
signal coefficients_i_20 : std_logic_vector(31 downto 0);
signal coefficients_i_21 : std_logic_vector(31 downto 0);
signal coefficients_i_22 : std_logic_vector(31 downto 0);
signal coefficients_i_23 : std_logic_vector(31 downto 0);
signal coefficients_i_24 : std_logic_vector(31 downto 0);
signal coefficients_i_25 : std_logic_vector(31 downto 0);
signal coefficients_i_26 : std_logic_vector(31 downto 0);
signal coefficients_i_27 : std_logic_vector(31 downto 0);
signal coefficients_i_28 : std_logic_vector(31 downto 0);
signal coefficients_i_29 : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant FIR_START : std_logic_vector(31 downto 0) := x"0000000F";
constant FIR_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Component related wiring
-----------------------------------
x_i <= signed(sample_in(31 downto 8));
sample_out <= std_logic_vector(y_i) & X"11" when y_i(23) = '1' else
std_logic_vector(y_i) & X"00";
sourceaddr <= hwtio.argv(0);
destaddr <= hwtio.argv(1);
coefficients_i_0 <= hwtio.argv(2);
coefficients_i_1 <= hwtio.argv(3);
coefficients_i_2 <= hwtio.argv(4);
coefficients_i_3 <= hwtio.argv(5);
coefficients_i_4 <= hwtio.argv(6);
coefficients_i_5 <= hwtio.argv(7);
coefficients_i_6 <= hwtio.argv(8);
coefficients_i_7 <= hwtio.argv(9);
coefficients_i_8 <= hwtio.argv(10);
coefficients_i_9 <= hwtio.argv(11);
coefficients_i_10 <= hwtio.argv(12);
coefficients_i_11 <= hwtio.argv(13);
coefficients_i_12 <= hwtio.argv(14);
coefficients_i_13 <= hwtio.argv(15);
coefficients_i_14 <= hwtio.argv(16);
coefficients_i_15 <= hwtio.argv(17);
coefficients_i_16 <= hwtio.argv(18);
coefficients_i_17 <= hwtio.argv(19);
coefficients_i_18 <= hwtio.argv(20);
coefficients_i_19 <= hwtio.argv(21);
coefficients_i_20 <= hwtio.argv(22);
coefficients_i_21 <= hwtio.argv(23);
coefficients_i_22 <= hwtio.argv(24);
coefficients_i_23 <= hwtio.argv(25);
coefficients_i_24 <= hwtio.argv(26);
coefficients_i_25 <= hwtio.argv(27);
coefficients_i_26 <= hwtio.argv(28);
coefficients_i_27 <= hwtio.argv(29);
coefficients_i_28 <= hwtio.argv(30);
coefficients_i16(0) <= signed(coefficients_i_0(31) & coefficients_i_0(14 downto 0));
coefficients_i16(1) <= signed(coefficients_i_1(31) & coefficients_i_1(14 downto 0));
coefficients_i16(2) <= signed(coefficients_i_2(31) & coefficients_i_2(14 downto 0));
coefficients_i16(3) <= signed(coefficients_i_3(31) & coefficients_i_3(14 downto 0));
coefficients_i16(4) <= signed(coefficients_i_4(31) & coefficients_i_4(14 downto 0));
coefficients_i16(5) <= signed(coefficients_i_5(31) & coefficients_i_5(14 downto 0));
coefficients_i16(6) <= signed(coefficients_i_6(31) & coefficients_i_6(14 downto 0));
coefficients_i16(7) <= signed(coefficients_i_7(31) & coefficients_i_7(14 downto 0));
coefficients_i16(8) <= signed(coefficients_i_8(31) & coefficients_i_8(14 downto 0));
coefficients_i16(9) <= signed(coefficients_i_9(31) & coefficients_i_9(14 downto 0));
coefficients_i16(10) <= signed(coefficients_i_10(31) & coefficients_i_10(14 downto 0));
coefficients_i16(11) <= signed(coefficients_i_11(31) & coefficients_i_11(14 downto 0));
coefficients_i16(12) <= signed(coefficients_i_12(31) & coefficients_i_12(14 downto 0));
coefficients_i16(13) <= signed(coefficients_i_13(31) & coefficients_i_13(14 downto 0));
coefficients_i16(14) <= signed(coefficients_i_14(31) & coefficients_i_14(14 downto 0));
coefficients_i16(15) <= signed(coefficients_i_15(31) & coefficients_i_15(14 downto 0));
coefficients_i16(16) <= signed(coefficients_i_16(31) & coefficients_i_16(14 downto 0));
coefficients_i16(17) <= signed(coefficients_i_17(31) & coefficients_i_17(14 downto 0));
coefficients_i16(18) <= signed(coefficients_i_18(31) & coefficients_i_18(14 downto 0));
coefficients_i16(19) <= signed(coefficients_i_19(31) & coefficients_i_19(14 downto 0));
coefficients_i16(20) <= signed(coefficients_i_20(31) & coefficients_i_20(14 downto 0));
coefficients_i16(21) <= signed(coefficients_i_21(31) & coefficients_i_21(14 downto 0));
coefficients_i16(22) <= signed(coefficients_i_22(31) & coefficients_i_22(14 downto 0));
coefficients_i16(23) <= signed(coefficients_i_23(31) & coefficients_i_23(14 downto 0));
coefficients_i16(24) <= signed(coefficients_i_24(31) & coefficients_i_24(14 downto 0));
coefficients_i16(25) <= signed(coefficients_i_25(31) & coefficients_i_25(14 downto 0));
coefficients_i16(26) <= signed(coefficients_i_26(31) & coefficients_i_26(14 downto 0));
coefficients_i16(27) <= signed(coefficients_i_27(31) & coefficients_i_27(14 downto 0));
coefficients_i16(28) <= signed(coefficients_i_28(31) & coefficients_i_28(14 downto 0));
-----------------------------------------------------------------
-- Memory Management
-----------------------------------------------------------------
o_RAMAddr_fir <= std_logic_vector(TO_UNSIGNED(ptr, C_LOCAL_RAM_ADDRESS_WIDTH));
o_RAMData_fir <= sample_out;
uut: fir
generic map (
FIR_ORDER => FIR_ORDER
)
PORT MAP(
clk => clk,
rst => rst,
ce => fir_ce,
coefficients => coefficients_i16,
x_in => x_i,
y_out => y_i
);
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_fir = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_fir))) := o_RAMData_fir;
else
i_RAMData_fir <= local_ram(to_integer(unsigned(o_RAMAddr_fir)));
end if;
end if;
end process;
FIR_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
hwtio_init(hwtio);
osif_ctrl_signal <= (others => '0');
state <= STATE_IDLE;
o_RAMWE_fir <= '0';
ptr <= 0;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16); -- number of samples processed
done := False;
elsif rising_edge(clk) then
fir_ce <= '0';
o_RAMWE_fir <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
when STATE_IDLE =>
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = FIR_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_HWT_ARGS;
elsif osif_ctrl_signal = FIR_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_HWT_ARGS =>
get_hwt_args(i_osif, o_osif, i_memif, o_memif, hwtio, hwt_argc, done);
if done then
state <= STATE_READ_MEM;
end if;
when STATE_READ_MEM =>
-- store input samples in local ram
memif_read(i_ram, o_ram, i_memif, o_memif, sourceaddr, X"00000000",
std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case process_state is
-- Read one sample from local memory
when 0 =>
sample_in <= i_RAMData_fir; -- not sure here
process_state <= 2;
when 2 =>
fir_ce <= '1';
o_RAMWE_fir <= '1';
process_state <= 3;
when 3 =>
sample_count <= sample_count - 1;
process_state <= 4;
-- Write sample back to local memory
when 4 =>
ptr <= ptr + 1;
process_state <= 5;
when 5 =>
process_state <= 6;
when others =>
process_state <= 0;
end case;
else
-- Samples have been generated
ptr <= 0;
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", destaddr,
std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, destaddr, ignore, done);
if done then
state <= STATE_IDLE;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | e1e86a70f40698306fa0d1f06717ed04 | 0.518932 | 3.616376 | false | false | false | false |
EPiCS/soundgates | hardware/basic/square/square_tb.vhd | 1 | 1,568 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY square_tb IS
END square_tb;
ARCHITECTURE behavior OF square_tb IS
COMPONENT square
PORT(
clk : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
sq : out signed(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal calc : std_logic := '1';
signal offset : signed(31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr : signed(31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr2 : signed(31 downto 0) := to_signed(integer(real(0.05 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--Outputs
signal sq : signed(31 downto 0);
signal sq1 : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
uut: square PORT MAP (
clk => clk,
ce => '1',
offset => offset,
incr => incr,
sq => sq
);
uut2: square PORT MAP (
clk => clk,
ce => '1',
offset => offset,
incr => incr2,
sq => sq1
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| mit | 944e9cad18ed4c87c2599b8e6d0d85fd | 0.544005 | 3.350427 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_adsr_v1_00_a/hdl/vhdl/hwt_adsr.vhd | 1 | 18,702 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_adsr
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating adsr
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_adsr is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_adsr;
architecture Behavioral of hwt_adsr is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
-- ?? Was macht das hier?!
-- memif_read_word(i_memif, o_memif, rlse_amp_addr, rlse_amp, done);
-- if done then
-- refresh_state <= "0";
-- state <= STATE_PROCESS;
component adsr is
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
input_wave : in signed(31 downto 0);
start : in std_logic_vector;
stop : in std_logic_vector;
attack : in signed(31 downto 0);
decay : in signed(31 downto 0);
sustain : in signed(31 downto 0);
release : in signed(31 downto 0);
wave : out signed(31 downto 0)
);
end component adsr;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_REFRESH, STATE_READ,STATE_CHECK_BANG, STATE_WAITING, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_adsr : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_adsr : std_logic_vector(0 to 31); -- adsr to local ram
signal i_RAMData_adsr : std_logic_vector(0 to 31); -- local ram to adsr
signal o_RAMWE_adsr : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal adsr_ce : std_logic; -- adsr clock enable (like a start/stop signal)
signal input_data : signed(31 downto 0);
signal adsr_data : signed(31 downto 0);
signal refresh_state : integer range 0 to 3;
signal process_state : integer range 0 to 2;
signal bang_state : integer range 0 to 1;
signal bang_addr : std_logic_vector(31 downto 0);
signal stop_addr : std_logic_vector(31 downto 0);
signal start : std_logic_vector(31 downto 0);
signal stop : std_logic_vector(31 downto 0);
signal atck_dura_addr : std_logic_vector(31 downto 0);
signal dcay_dura_addr : std_logic_vector(31 downto 0);
signal rlse_dura_addr : std_logic_vector(31 downto 0);
signal sust_amp_addr : std_logic_vector(31 downto 0);
signal bang : std_logic_vector(31 downto 0);
signal bang_stop : std_logic_vector(31 downto 0);
signal atck_dura : std_logic_vector(31 downto 0);
signal dcay_dura : std_logic_vector(31 downto 0);
signal rlse_dura : std_logic_vector(31 downto 0);
signal sust_amp : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant ADSR_START : std_logic_vector(31 downto 0) := x"0000000F";
constant ADSR_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
constant C_START_BANG : std_logic_vector(31 downto 0) := x"00000001";
constant C_STOP_BANG : std_logic_vector(31 downto 0) := x"FFFFFFFF";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
-- o_RAMData_adsr <= std_logic_vector(adsr_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
adsr_INST : adsr
port map(
clk => clk,
rst => rst,
ce => adsr_ce,
input_wave => signed(input_data),
start => start,
stop => stop,
attack => signed(atck_dura),
decay => signed(dcay_dura),
sustain => signed(sust_amp),
release => signed(rlse_dura),
wave => adsr_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_adsr = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_adsr))) := o_RAMData_adsr;
else -- else needed, because adsr is consuming samples
i_RAMData_adsr <= local_ram(to_integer(unsigned(o_RAMAddr_adsr)));
end if;
end if;
end process;
ADSR_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
adsr_ce <= '0';
start <= (others => '0');
stop <= (others => '0');
o_RAMWE_adsr<= '0';
refresh_state <= 0;
process_state <= 0;
bang_state <= 0;
bang <= (others => '0');
done := False;
elsif rising_edge(clk) then
adsr_ce <= '0';
o_RAMWE_adsr <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
bang_addr <= snd_comp_header.opt_arg_addr;
stop_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
atck_dura_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 8);
dcay_dura_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 12);
sust_amp_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 16);
rlse_dura_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 20);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = ADSR_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_CHECK_BANG;
elsif osif_ctrl_signal = ADSR_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_CHECK_BANG =>
case bang_state is
when 0 =>
memif_read_word(i_memif, o_memif, bang_addr, bang, done);
if done then
if bang = C_START_BANG then
bang_state <= 1;
start <= (others => '1');
state <= STATE_REFRESH;
else
state <= STATE_WAITING;
end if;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, stop_addr, bang_stop, done);
if done then
if (bang_stop = C_STOP_BANG) then
bang_state <= 0;
stop <= (others => '1');
state <= STATE_PROCESS;
else
state <= STATE_REFRESH;
end if;
end if;
end case;
when STATE_REFRESH =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, atck_dura_addr, atck_dura, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, dcay_dura_addr, dcay_dura, done);
if done then
refresh_state <= 2;
end if;
when 2 =>
memif_read_word(i_memif, o_memif, sust_amp_addr, sust_amp, done);
if done then
refresh_state <= 3;
end if;
when 3 =>
memif_read_word(i_memif, o_memif, dcay_dura_addr, dcay_dura, done);
if done then
refresh_state <= 0;
state <= STATE_READ;
end if;
end case;
-- when STATE_REFRESH_RELEASE =>
-- state <= STATE_PROCESS;
-- folgendes nicht mehr anpassbar:
-- case refresh_state is
-- when 0 =>
-- memif_read_word(i_memif, o_memif, rlse_amp_addr, rlse_amp, done);
-- if done then
-- refresh_state <= 1;
-- end if;
-- when 1 =>
-- memif_read_word(i_memif, o_memif, rlse_dura_addr, rlse_dura, done);
-- if done then
-- refresh_state <= 0;
-- state <= STATE_PROCESS;
-- end if;
-- when others =>
-- refresh_state <= 0;
-- end case;
when STATE_READ =>
-- store input samples in local ram
memif_read(i_ram,o_ram,i_memif,o_memif,snd_comp_header.source_addr,X"00000000",std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)),done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
adsr_ce <= '1';
process_state <= 1;
when 1 =>
start <= (others => '0');
stop <= (others => '0');
o_RAMData_adsr <= std_logic_vector(resize(adsr_data * signed(i_RAMData_adsr), 32));
o_RAMWE_adsr <= '1';
adsr_ce <= '0';
process_state <= 2;
when 2 =>
o_RAMWE_adsr <= '0';
o_RAMAddr_adsr <= std_logic_vector(unsigned(o_RAMAddr_adsr) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_adsr <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | bd3ca6e689a16a7f30f67dc95204ff68 | 0.463373 | 3.829238 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/memory.vhd | 1 | 811 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity syncram is
Generic ( n : integer := 8);
port ( clk : in std_logic;
we : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end entity syncram;
architecture syncrama of syncram is
type ram_type is array (0 to (2**n)-1) of std_logic_vector(15 downto 0);
signal ram : ram_type;
begin
process(clk) is
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
end if;
end process;
dataout <= ram(to_integer(unsigned(address)));
dataout0 <= ram(0);
dataout1 <= ram(1);
end architecture syncrama; | mit | 403a2f2a0132eeb4d840a240da3291da | 0.706535 | 2.981618 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/control.vhd | 1 | 4,901 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity control_entity is
port (
op_code: in std_logic_vector(4 downto 0);
nop_enable:in std_logic; --nop operation enable for load & store
pc_mux : out std_logic_vector(1 downto 0);
inport_en : out std_logic;
outport_en : out std_logic;
reg_write : out std_logic;
mem_write : out std_logic;
write_data_reg_mux : out std_logic;
Shift_Mux : out std_logic; -- to know if make shift or not
write_back_mux : out std_logic_vector(1 downto 0);
int_flags_en : out std_logic; -- int to take flags from meomry to alu
alu_control : out std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)علي حسب شغلك 'musgi'
mem_mux : out std_logic;
Stack_WriteEnable_control, StackPushPop_control: out std_logic
-- FlagEnable : in std_logic;
);
end control_entity;
Architecture arch_control_entity of control_entity is
signal op_code_signal : std_logic_vector(4 downto 0);
Begin
op_code_signal<="00000" when nop_enable='1' else
op_code;
pc_mux <= "01" when op_code_signal="10100" or op_code_signal="10101" or op_code_signal="10110" or op_code_signal="11000" or op_code_signal="11001" or op_code_signal="11010" or op_code_signal="01100" or op_code_signal="01101" else
"10" when op_code_signal="11110" else
"11" when op_code_signal="11111" else
"00";
inport_en <= '1' when op_code_signal="01111" else
'0';
outport_en <= '1' when op_code_signal="01110" else
'0';
reg_write <= '1' when (op_code_signal>="00001" and op_code_signal<="01001") or (op_code_signal>="10000" and op_code_signal<="10011") or op_code_signal="01101" or op_code_signal="01111" or op_code_signal="11011" or op_code_signal="11100" else
'0';
mem_write <= '1' when op_code_signal="01100" or op_code_signal="11000" or op_code_signal="11101" or op_code_signal="11111" else
'0';
write_data_reg_mux <= '1' when op_code_signal="01111" else
'0';
Shift_Mux <='1' when op_code_signal="01000" or op_code_signal="01001" else '0';
write_back_mux <= "01" when (op_code_signal>="01100" and op_code_signal<="01110") or op_code_signal="11100" else
"10" when op_code_signal="11011" else
"00";
int_flags_en <= '1' when (op_code_signal>="00010" and op_code_signal<="00111") or (op_code_signal>="10000" and op_code_signal<="10011") or op_code_signal="01010" or op_code_signal="01011" or (op_code_signal>="10100" and op_code_signal<="10110") or op_code_signal="11001" or op_code_signal="11010" or op_code_signal="11110" else
'0';
alu_control <= "00000" when op_code="00000" else
"00001" when op_code="00001" else
"00010" when op_code="00010" else
"00011" when op_code="00011"else
"00100" when op_code="00100"else
"00101" when op_code="00101"else
"00111" when op_code="00111"else
"01000" when op_code="01000"else
"01001" when op_code="01001"else
"01010" when op_code="01010"else
"01011" when op_code="01011"else
"01100" when op_code="01100"else
"01101" when op_code="01101"else
"01110" when op_code="01110"else
"01111" when op_code="01111"else
"10000" when op_code="10000"else
"10001" when op_code="10001"else
"10010" when op_code="10010"else
"10011" when op_code="10011"else
"10100" when op_code="10100"else
"10101" when op_code="10101"else
"10110" when op_code="10110"else
"10111" when op_code="10111"else
"11000" when op_code="11000"else
"11001" when op_code="11001"else
"11010" when op_code="11010"else
"11011" when op_code="11011"else
"11100" when op_code="11100"else
"11101" when op_code="11101"else
"11110" when op_code="11110"else
"11111" when op_code="11111";
mem_mux <= '1' when (op_code_signal>="01100" and op_code_signal<="01110") or (op_code_signal>="11000" and op_code_signal<="11010") or op_code_signal="11111" else
'0';
Stack_WriteEnable_control <= '1' when op_code_signal="01100" or op_code_signal="01101" or op_code_signal="11000" or op_code_signal="11001" or op_code_signal="11010" else
'0';
StackPushPop_control <= '1' when op_code_signal="01101" or op_code_signal="11001" or op_code_signal="11010" else
'0';
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--enable_LoadStore<='1' when op_code_signal="11011" or op_code_signal= "11100" or op_code_signal="11101";--el mafrood trgo zero b3d one cycle
end arch_control_entity; | mit | 1f0d5d2ef81ee7c2268cb3d1ce0b1449 | 0.597015 | 3.058787 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_iir_v1_00_a/hdl/vhdl/hwt_iir.vhd | 1 | 17,253 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_iir
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for iir Filter
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_iir is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
IIR_ORDER : integer := 3 -- 4 coefficients
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_iir;
architecture Behavioral of hwt_iir is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
-- ?? Was macht das hier?
-- memif_read_word(i_memif, o_memif, rlse_amp_addr, rlse_amp, done);
-- if done then
-- refresh_state <= "0";
-- state <= STATE_PROCESS;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_INIT_ADDRESSES, STATE_READ_COEFFICIENTS_ADRESSES, STATE_READ, STATE_WAITING, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_iir : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_iir : std_logic_vector(0 to 31); -- iir to local ram
signal i_RAMData_iir : std_logic_vector(0 to 31); -- local ram to iir
signal o_RAMWE_iir : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal iir_ce : std_logic; -- iir clock enable (like a start/stop signal)
signal input_data : signed(31 downto 0);
signal iir_data : signed(31 downto 0);
signal count : signed (31 downto 0);
signal process_state : integer range 0 to 3;
type mem32 is array (natural range <>) of std_logic_vector(31 downto 0);
type smem32 is array (natural range <>) of signed(31 downto 0);
type mem64 is array (natural range <>) of signed(63 downto 0);
signal coeffs_mem32 : mem32(IIR_ORDER downto 0);
signal coeff_index : signed(31 downto 0);
signal inputs_mem32 : mem32(IIR_ORDER downto 0);
signal mult_mem64 : mem64(IIR_ORDER downto 0);
signal init_state : integer range 0 to 1;
signal coefficients_addr : mem32(2 * IIR_ORDER downto 0);
signal coefficients : mem32(2 * IIR_ORDER downto 0);
signal buffer_states_addr : mem32(IIR_ORDER downto 0);
signal buffer_states : mem32(IIR_ORDER downto 0);
signal opt_arg : std_logic_vector(31 downto 0);
signal coefficient_count_addr : std_logic_vector(31 downto 0);
signal coefficient_count : std_logic_vector(31 downto 0);
signal addr_counter : integer range 0 to IIR_ORDER + 1;
signal input_mem32 : smem32(IIR_ORDER downto 0);
signal output_mem64 : mem64(IIR_ORDER downto 0);
signal iir_data64 : signed(63 downto 0);
signal iir : signed(63 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant iir_START : std_logic_vector(31 downto 0) := x"0000000F";
constant iir_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
constant C_START_BANG : std_logic_vector(31 downto 0) := x"00000001";
constant C_STOP_BANG : std_logic_vector(31 downto 0) := x"FFFFFFFF";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
-- o_RAMData_iir <= std_logic_vector(iir_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_iir = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_iir))) := o_RAMData_iir;
else -- else needed, because iir is consuming samples
i_RAMData_iir <= local_ram(to_integer(unsigned(o_RAMAddr_iir)));
end if;
end if;
end process;
iir_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
addr_counter <= 0;
state <= STATE_INIT;
osif_ctrl_signal <= (others => '0');
o_RAMWE_iir<= '0';
count <= (others => '0');
done := False;
init_state <= 0;
sample_count <= to_unsigned(0, 16);
elsif rising_edge(clk) then
iir_ce <= '0';
o_RAMWE_iir <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
opt_arg <= snd_comp_header.opt_arg_addr;
coefficient_count_addr <= opt_arg; -- address to number of coefficients
state <= STATE_INIT_ADDRESSES;
end if;
when STATE_INIT_ADDRESSES =>
case init_state is
when 0 =>
-- get number of coefficients
memif_read_word(i_memif, o_memif, coefficient_count_addr, coefficient_count, done);
if done then
init_state <= 1;
end if;
when 1 =>
coefficients_addr(addr_counter) <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4*(addr_counter+1));
addr_counter <= addr_counter + 1;
if addr_counter >= 2*to_integer(signed(coefficient_count)) then
init_state <= 0;
state <= STATE_WAITING;
else
init_state <= 1;
end if;
-- for i in 0 to to_integer(signed(coefficient_count)) - 1 loop
-- coefficients_addr(i) <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4*(i+1));
-- --address to actual coefficients
-- end loop;
-- init_state <= 0;
-- state <= STATE_WAITING;
-- when "2" =>
--
-- buffer_state_count_addr <= std_logic_vector(unsigned(opt_arg + 4*(to_integer(signed(coefficient_count)) + 2)));
-- -- address to number of buffer states
--
-- for i in 0 to to_integer(signed(buffer_state_count_addr)) - 1 loop
-- buffer_states_addr(i) <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + unsigned(4*(i+1)));
-- --address to actual buffer states
-- end loop;
end case;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = iir_START then
state <= STATE_READ_COEFFICIENTS_ADRESSES;
elsif osif_ctrl_signal = iir_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_READ_COEFFICIENTS_ADRESSES =>
-- read adresses to the iir coefficients values
memif_read_word(i_memif, o_memif, coefficients_addr(to_integer(count)), coefficients(to_integer(count)), done);
if done then
-- write values to iir component
count <= count + 1;
if count >= 2*signed(coefficient_count) then
state <= STATE_READ;
count <= (others => '0');
else
state <= STATE_READ_COEFFICIENTS_ADRESSES;
end if;
end if;
-- when STATE_READ_BUFFER_STATE_ADRESSES =>
-- -- read adresses to the iir buffer state values
-- memif_read_word(i_memif, o_memif, buffer_states_addr(to_integer(count)), buffer_states(to_integer(count)), done);
-- if done then
-- -- write values to the iir component
-- count <= count + 1;
--
-- config_buffer_state_valid <= '1';
-- config_buffer_state_index <= count;
-- config_buffer_state_data <= buffer_states(to_integer(count));
--
-- if count > signed(buffer_states) then
-- state <= STATE_READ;
-- count <= (others => '0');
-- else
-- state <= STATE_READ_BUFFER_STATE_ADRESSES;
-- end if;
-- end if;
when STATE_READ =>
-- store input samples in local ram
memif_read(i_ram,o_ram,i_memif,o_memif,snd_comp_header.source_addr,X"00000000",std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)),done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
for i in 0 to IIR_ORDER - 1 loop
input_mem32(i + 1) <= input_mem32(i);
end loop;
input_mem32(0) <= signed(i_RAMData_iir);
for i in 0 to IIR_ORDER loop
output_mem64(i) <= signed(coefficients(i)) * input_mem32(IIR_ORDER - i);
iir_data64 <= iir_data64 + output_mem64(i);
end loop;
process_state <= 1;
when 1 =>
for i in 0 to IIR_ORDER - 1 loop
output_mem64(i) <= signed(coefficients(IIR_ORDER + 1 + i)) * input_mem32(2*IIR_ORDER - (IIR_ORDER + 1 + i));
iir <= iir_data64 - output_mem64(i);
end loop;
process_state <= 2;
when 2 =>
iir_data <= iir(31 downto 0);
o_RAMData_iir <= std_logic_vector(iir_data);
o_RAMWE_iir <= '1';
count <= count + 1;
process_state <= 3;
when 3 =>
o_RAMWE_iir <= '0';
iir_data64 <= (others => '0');
o_RAMAddr_iir <= std_logic_vector(unsigned(o_RAMAddr_iir) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_iir <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 4e303a543ea7a3ee6a810294ce16a2a3 | 0.520779 | 3.572789 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Forwarding.vhd | 1 | 819 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
ENTITY AddSubIncDec IS
port(
R1_Reg,R2_Reg,ROut_Alu,ROut_Mem: in std_logic_vector(2 downto 0);
R1,R2: out std_logic_vector(15 downto 0);
R1_Mux,R2_Mux : out std_logic;
Alu_Output , Meomry_Output: in std_logic_vector(15 downto 0)
--Alu_Output1 , Meomry_Output1: out std_logic_vector(15 downto 0);
--WriteBackSignal : in std_logic
);
END AddSubIncDec;
Architecture archi of AddSubIncDec is
begin
R1 <= Alu_Output when R1_Reg = ROut_Alu else
Meomry_Output when R1_Reg = ROut_Mem;
R2 <= Alu_Output when R2_Reg = ROut_Alu else
Meomry_Output when R2_Reg = ROut_Mem;
R1_Mux <= '1' when R1_Reg = ROut_Alu or R1_Reg = ROut_Mem else
'0';
R2_Mux <= '1' when R2_Reg = ROut_Alu or R2_Reg = ROut_Mem else
'0';
end archi; | mit | 6158b29b7ed93efbac13b9fc885eb5c0 | 0.684982 | 2.423077 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_status_reg.vhd | 1 | 6,540 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver status register ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.3 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.2 2004/06/16 19:03:10 gedra
-- Added channel status decoding.
--
-- Revision 1.1 2004/06/05 17:17:12 gedra
-- Recevier status register
--
--
library ieee;
use ieee.std_logic_1164.all;
entity rx_status_reg is
generic (DATA_WIDTH: integer);
port (
up_clk: in std_logic; -- clock
status_rd: in std_logic; -- status register read
lock: in std_logic; -- signal lock status
chas: in std_logic; -- channel A or B select
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end rx_status_reg;
architecture rtl of rx_status_reg is
signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal cur_pos : integer range 0 to 255;
signal pro_mode : std_logic;
begin
status_dout <= status_vector when status_rd = '1' else (others => '0');
D32: if DATA_WIDTH = 32 generate
status_vector(31 downto 16) <= (others => '0');
end generate D32;
status_vector(0) <= lock;
status_vector(15 downto 7) <= (others => '0');
-- extract channel status bits to be used
CDAT: process (up_clk, lock)
begin
if lock = '0' then
cur_pos <= 0;
pro_mode <= '0';
status_vector(6 downto 1) <= (others => '0');
else
if rising_edge(up_clk) then
-- bit counter, 0 to 191
if rx_block_start = '1' then
cur_pos <= 0;
elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
cur_pos <= cur_pos + 1;
end if;
-- extract status bits used in status register
if (chas = '0' and cs_b_en = '1') or
(chas = '1' and cs_a_en = '1') then
case cur_pos is
when 0 => -- PRO bit
status_vector(1) <= ch_data;
pro_mode <= ch_data;
when 1 => -- AUDIO bit
status_vector(2) <= not ch_data;
when 2 => -- emphasis/copy bit
if pro_mode = '1' then
status_vector(5) <= ch_data;
else
status_vector(6) <= ch_data;
end if;
when 3 => -- emphasis
if pro_mode = '1' then
status_vector(4) <= ch_data;
else
status_vector(5) <= ch_data;
end if;
when 4 => -- emphasis
if pro_mode = '1' then
status_vector(3) <= ch_data;
else
status_vector(4) <= ch_data;
end if;
when 5 => -- emphasis
if pro_mode = '0' then
status_vector(3) <= ch_data;
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process CDAT;
end rtl;
| mit | ea53829b37116929c09143c501a6ef4c | 0.400612 | 4.876957 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/MUX_FETCH.vhd | 1 | 3,905 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity MUX_Fetch is
port (
Sel: in std_logic_vector (1 downto 0);--input from control unit
--at reset control unit send zeroes to pcs
--PC1: in std_logic_vector(15 downto 0 ); --
PC2: in std_logic_vector(15 downto 0 ); --address to jump to from BRANCH
PC3: in std_logic_vector(15 downto 0 ); --address from memory[0]
PC4: in std_logic_vector(15 downto 0 ); --address from memory[1]
CLK: in std_logic;
Out_instruction: out std_logic_vector(15 downto 0 );
InPort: in std_logic_vector(15 downto 0);
OutPort: out std_logic_vector(15 downto 0);
RESET: in std_logic
);
end entity MUX_Fetch;
architecture MUX_Fetch_Arch of MUX_Fetch is
Component syncram is
generic ( n : integer := 16);
port (
clk : in std_logic;
we : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0)
);
end component;
--***********************************************************************************
Component PC is
port (
counter: in std_logic_vector(15 downto 0 );
new_counter: out std_logic_vector(15 downto 0 );
CLK: in std_logic;
RESET: in std_logic
);
end component;
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Component Ext_Mem_Buffer is
Generic ( n : integer := 16);
port (
Clk : in std_logic;
Rst : in std_logic;
--enable : in std_logic;
inport_en_input : in std_logic_vector(15 downto 0); --??????????????
instruction_input :in std_logic_vector(15 downto 0);
inport_en_output : out std_logic_vector(15 downto 0); --??????????????
instruction_output :out std_logic_vector(15 downto 0);
OPcode: out std_logic_vector(4 downto 0 );
R1: out std_logic_vector(2 downto 0 ); --addres of reg1
R2: out std_logic_vector(2 downto 0 ); --addres of reg2
Rout: out std_logic_vector(2 downto 0 ) --for write back
--LDD_Memory: out std_logic_vector(9 downto 0 ); --load value from memory to register
--LDM_immediate: out std_logic_vector(15 downto 0 ); --load immediate value from user to register
--input_port : in std_logic_vector(15 downto 0 )
);
end component;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal MY_PC_SIGNAL: std_logic_vector(15 downto 0);
--signal new_count: std_logic_vector(15 downto 0);
signal PC1: std_logic_vector(15 downto 0);
signal copied_data: std_logic_vector(15 downto 0);
-----------------------BUFFER SIGNALS--------------------------
signal inport_en_output_signal: std_logic_vector(15 downto 0); --??????????????
signal instruction_output_signal : std_logic_vector(15 downto 0);
signal OPcode_signal: std_logic_vector(4 downto 0 );
signal R1_signal: std_logic_vector(2 downto 0 ); --addres of reg1
signal R2_signal: std_logic_vector(2 downto 0 ); --addres of reg2
signal Rout_signal: std_logic_vector(2 downto 0 ); --for write back
---------------------------------------------
begin
--inport data
--regesiter to store data of inport
OutPort<=InPort;
--send zero to pc when reset
MY_PC_SIGNAL <= PC1 when Sel = "00" and RESET='0' else
PC2 when Sel = "01" and RESET='0' else
PC3 when Sel = "10" and RESET='0' else
PC4 when Sel = "11" and RESET='0'else
(others => '0') when RESET='1' else
(others => '0');
--------------------------------------
set0: syncram generic map (n =>16) port map (CLK,'0',MY_PC_SIGNAL,"0000000000000000",copied_data); --clk,enable,(address to WRITE in),data to write, outputdata from selected address
My_PC: PC port map (MY_PC_SIGNAL,PC1,CLK,RESET);
--PC1<=MY_PC_SIGNAL;
Out_instruction<=copied_data;
--Out_PC<=MY_PC_SIGNAL;
end architecture MUX_Fetch_Arch; | mit | e46c341f2b67ed779a31aca932c806da | 0.595134 | 3.351931 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/PC_FETCH.vhd | 1 | 831 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity PC is
port (
counter: in std_logic_vector(15 downto 0 );
new_counter: out std_logic_vector(15 downto 0 );
CLK: in std_logic;
RESET: in std_logic
);
end entity PC;
architecture PC_Arch of PC is
begin
--------------------------------------
--set0: syncram generic map (n =>16) port map (CLK,'0',new_count,"0000000000000000",copied_data); --clk,enable,(address to WRITE in),data to write, outputdata from selected address
process(CLK,RESET)
begin
if RESET='1' then new_counter<="0000000000000000" ; --RESET PC
end if;
if RESET='0' and CLK='1' then
new_counter <= std_logic_vector(unsigned(counter)+1);
end if;
------------------------------------------------
end process;
end architecture PC_Arch; | mit | 4d0817753d0d04ed8e1e3db3ac2ad803 | 0.632972 | 3.284585 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_control_add_v1_00_a/hdl/vhdl/hwt_control_add.vhd | 1 | 14,024 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_control_add
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for adding control units
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_control_add is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_control_add;
architecture Behavioral of hwt_control_add is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component add is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_add : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_add : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_add : std_logic_vector(0 to 31); -- local ram to add
signal o_RAMWE_add : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal add_ce : std_logic; -- add clock enable (like a start/stop signal)
signal refresh_state : integer;
signal process_state : integer;
signal input1 : std_logic_vector(31 downto 0);
signal input2 : std_logic_vector(31 downto 0);
signal input1_addr : std_logic_vector(31 downto 0);
signal input2_addr : std_logic_vector(31 downto 0);
signal add_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_add <= std_logic_vector(add_data);
--add_wave <= signed(i_RAMData_add);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
add_INST : add
port map(
clk => clk,
rst => rst,
ce => add_ce,
wave1 => signed(input1),
wave2 => signed(input2),
output => add_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_add = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_add))) := o_RAMData_add;
else -- else needed, because add is consuming samples
i_RAMData_add <= local_ram(to_integer(unsigned(o_RAMAddr_add)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
add_ce <= '0';
o_RAMWE_add<= '0';
o_RAMAddr_add <= (others => '0');
refresh_state <= 0;
process_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
input2_addr <= snd_comp_header.opt_arg_addr;
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, snd_comp_header.source_addr , input1, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, input2_addr , input2, done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= 0;
end case;
-- memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
-- if done then
-- refresh_state <= 0;
-- state <= STATE_PROCESS;
-- end if;
-- when others =>
-- refresh_state <= 0;
-- end case;
when STATE_PROCESS =>
--if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
add_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_add <= std_logic_vector(add_data);
o_RAMWE_add <= '1';
add_ce <= '0';
process_state <= 2;
when 2 =>
o_RAMWE_add <= '0';
-- o_RAMAddr_add <= std_logic_vector(unsigned(o_RAMAddr_add) + 1);
-- sample_count <= sample_count + 1;
process_state <= 3;
when 3 =>
--o_RAMAddr_add <= (others => '0');
state <= STATE_WRITE_MEM;
when others =>
process_state <= 0;
end case;
-- else
-- -- Samples have been generated
-- o_RAMAddr_add <= (others => '0');
-- sample_count <= to_unsigned(0, 16);
-- state <= STATE_WRITE_MEM;
-- end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 5110b3b2aec8535e595dbd52af23f645 | 0.469837 | 3.786177 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_sample_and_hold_v1_00_a/hdl/vhdl/hwt_sample_and_hold.vhd | 1 | 12,555 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sample_and_hold
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating sample_and_hold
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sample_and_hold is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sample_and_hold;
architecture Behavioral of hwt_sample_and_hold is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
-- ?? Was macht das hier?!
-- memif_read_word(i_memif, o_memif, rlse_amp_addr, rlse_amp, done);
-- if done then
-- refresh_state <= "0";
-- state <= STATE_PROCESS;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_READ,STATE_CHECK_TRIGGER, STATE_WAITING, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_sample_and_hold : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_sample_and_hold : std_logic_vector(0 to 31); -- sample_and_hold to local ram
signal i_RAMData_sample_and_hold : std_logic_vector(0 to 31); -- local ram to sample_and_hold
signal o_RAMWE_sample_and_hold : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal sample_and_hold_ce : std_logic; -- sample_and_hold clock enable (like a start/stop signal)
signal input_data : signed(31 downto 0);
signal sample_and_hold_data : signed(31 downto 0);
signal refresh_state : integer range 0 to 3;
signal process_state : integer range 0 to 2;
signal bang_state : integer range 0 to 1;
signal trigger : std_logic_vector(31 downto 0);
signal trigger_addr : std_logic_vector(31 downto 0);
signal hold_length : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant SAMPLE_AND_HOLD_START : std_logic_vector(31 downto 0) := x"0000000F";
constant SAMPLE_AND_HOLD_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
constant C_START_TRIGGER : std_logic_vector(31 downto 0) := x"FFFFFFFF";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
-- o_RAMData_sample_and_hold <= std_logic_vector(sample_and_hold_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_sample_and_hold = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_sample_and_hold))) := o_RAMData_sample_and_hold;
else -- else needed, because sample_and_hold is consuming samples
i_RAMData_sample_and_hold <= local_ram(to_integer(unsigned(o_RAMAddr_sample_and_hold)));
end if;
end if;
end process;
SAMPLE_AND_HOLD_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
sample_and_hold_ce <= '0';
o_RAMWE_sample_and_hold<= '0';
refresh_state <= 0;
process_state <= 0;
bang_state <= 0;
done := False;
elsif rising_edge(clk) then
sample_and_hold_ce <= '0';
o_RAMWE_sample_and_hold <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
trigger_addr <= snd_comp_header.opt_arg_addr;
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = SAMPLE_AND_HOLD_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_READ;
elsif osif_ctrl_signal = SAMPLE_AND_HOLD_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_CHECK_TRIGGER =>
memif_read_word(i_memif, o_memif, trigger_addr, trigger, done);
if done then
if trigger = C_START_TRIGGER then
state <= STATE_WRITE_MEM;
else
state <= STATE_WAITING;
end if;
end if;
when STATE_READ =>
-- store input samples in local ram
memif_read(i_ram,o_ram,i_memif,o_memif,snd_comp_header.source_addr,X"00000000",std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)),done);
if done then
state <= STATE_CHECK_TRIGGER;
hold_length <= std_logic_vector(to_unsigned(hold_length) + (to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)));
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr,std_logic_vector(to_unsigned(hold_length,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | adf316ce84baa075c532c417bd5dbe17 | 0.516049 | 3.54661 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_control_mul_v1_00_a/hdl/vhdl/hwt_control_mul.vhd | 1 | 14,029 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_control_mul
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for multracting control units
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_control_mul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_control_mul;
architecture Behavioral of hwt_control_mul is
----------------------------------------------------------------
-- mulcomponent declarations
----------------------------------------------------------------
component mul is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMaddr_mul : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_mul : std_logic_vector(0 to 31); -- mul to local ram
signal i_RAMData_mul : std_logic_vector(0 to 31); -- local ram to mul
signal o_RAMWE_mul : std_logic;
signal o_RAMaddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMaddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMaddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal mul_ce : std_logic; -- mul clock enable (like a start/stop signal)
signal refresh_state : integer;
signal process_state : integer;
signal input1 : std_logic_vector(31 downto 0);
signal input2 : std_logic_vector(31 downto 0);
signal input1_addr : std_logic_vector(31 downto 0);
signal input2_addr : std_logic_vector(31 downto 0);
signal mul_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant mul_START : std_logic_vector(31 downto 0) := x"0000000F";
constant mul_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_mul <= std_logic_vector(mul_data);
--mul_wave <= signed(i_RAMData_mul);
o_RAMaddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMaddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMaddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
mul_INST : mul
port map(
clk => clk,
rst => rst,
ce => mul_ce,
wave1 => signed(input1),
wave2 => signed(input2),
output => mul_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMaddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMaddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_mul = '1') then
local_ram(to_integer(unsigned(o_RAMaddr_mul))) := o_RAMData_mul;
else -- else needed, because mul is consuming samples
i_RAMData_mul <= local_ram(to_integer(unsigned(o_RAMaddr_mul)));
end if;
end if;
end process;
mul_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
mul_ce <= '0';
o_RAMWE_mul<= '0';
o_RAMaddr_mul <= (others => '0');
refresh_state <= 0;
process_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
input2_addr <= snd_comp_header.opt_arg_addr;
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = mul_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = mul_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, snd_comp_header.source_addr , input1, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, input2_addr , input2, done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= 0;
end case;
-- memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
-- if done then
-- refresh_state <= 0;
-- state <= STATE_PROCESS;
-- end if;
-- when others =>
-- refresh_state <= 0;
-- end case;
when STATE_PROCESS =>
--if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
mul_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_mul <= std_logic_vector(mul_data);
o_RAMWE_mul <= '1';
mul_ce <= '0';
process_state <= 2;
when 2 =>
o_RAMWE_mul <= '0';
-- o_RAMaddr_mul <= std_logic_vector(unsigned(o_RAMaddr_mul) + 1);
-- sample_count <= sample_count + 1;
process_state <= 3;
when 3 =>
--o_RAMaddr_mul <= (others => '0');
state <= STATE_WRITE_MEM;
when others =>
process_state <= 0;
end case;
-- else
-- -- Samples have been generated
-- o_RAMaddr_mul <= (others => '0');
-- sample_count <= to_unsigned(0, 16);
-- state <= STATE_WRITE_MEM;
-- end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 3902c040f290358e46b46b0101774f49 | 0.470026 | 3.763144 | false | false | false | false |
EPiCS/soundgates | hardware/basic/adsr/adsr.vhd | 1 | 3,771 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - adsr.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: ADSR Envelope
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity adsr is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
input_wave : in signed(31 downto 0);
start : in std_logic_vector(31 downto 0);
stop : in std_logic_vector(31 downto 0);
attack : in signed(31 downto 0);
decay : in signed(31 downto 0);
sustain : in signed(31 downto 0);
release : in signed(31 downto 0);
wave : out signed(31 downto 0)
);
end adsr;
architecture Behavioral of adsr is
type adsr_states is (s_idle, s_attack, s_decay, s_sustain, s_release, s_exit);
signal state : adsr_states;
signal i_wave : signed (31 downto 0);
signal b_stop : std_logic;
signal s_one : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_zero : signed (31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal wave64 : signed (63 downto 0);
begin
wave64 <= i_wave * input_wave;
wave <= wave64(31 downto 0);
ADSR_PROC : process (clk, rst)
begin
if rst = '1' then
i_wave <= s_zero;
state <= s_idle;
b_stop <= '0';
else
if rising_edge(clk) then
if stop(0) = '1' then
b_stop <= '1';
end if;
if ce = '1' then
if start(0) = '1' then
state <= s_attack;
end if;
case state is
when s_attack =>
i_wave <= i_wave + attack;
if i_wave >= s_one then
state <= s_decay;
end if;
when s_decay =>
i_wave <= i_wave - decay;
if i_wave <= sustain then
state <= s_sustain;
end if;
when s_sustain =>
i_wave <= sustain;
if b_stop = '1' then
state <= s_release;
b_stop <= '0';
end if;
when s_release =>
i_wave <= i_wave - release;
if i_wave <= s_zero then
state <= s_exit;
end if;
when s_exit =>
state <= s_idle;
when others =>
state <= s_idle;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | aa0a1994caadf14e7c1a290ad24b4bd6 | 0.356404 | 4.166851 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_encoder.vhd | 1 | 19,836 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio : std_logic;
signal tick_counter : std_logic;
signal tick_counter_d1 : std_logic;
signal tick_counter_d2 : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
tick_counter <= not tick_counter;
end if;
end process DCLK;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
tick_counter_d1 <= '0';
tick_counter_d2 <= '0';
spdif_clk_en <= '0';
else
tick_counter_d1 <= tick_counter;
tick_counter_d2 <= tick_counter_d1;
spdif_clk_en <= '0';
if (tick_counter_d1 xor tick_counter_d2) = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
sample_data_ack <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
sample_data_ack <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
sample_data_ack <='1';
end if;
when READ_CHA =>
channel <= '0';
sample_data_ack <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
sample_data_ack <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
if resetn = '0' then
spdif_tx_o <= '0';
else
spdif_tx_o <= spdif_out;
end if;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= def_user_data;
end rtl;
| mit | 0a3f09cb3834c792901ea429dd891af2 | 0.44263 | 4.35956 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/vhdl/axi_dac_1c_2p.vhd | 1 | 11,303 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_dac_1c_2p is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_data_out_a_p : out std_logic_vector(13 downto 0);
dac_data_out_a_n : out std_logic_vector(13 downto 0);
dac_data_out_b_p : out std_logic_vector(13 downto 0);
dac_data_out_b_n : out std_logic_vector(13 downto 0);
up_status : out std_logic_vector(7 downto 0);
vdma_dbg_data : out std_logic_vector(198 downto 0);
vdma_dbg_trigger : out std_logic_vector(7 downto 0);
dac_div3_clk : out std_logic;
dac_dbg_data : out std_logic_vector(292 downto 0);
dac_dbg_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
vdma_clk : in std_logic;
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dac_1c_2p;
architecture IMP of axi_dac_1c_2p is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_data_out_a_p : out std_logic_vector(13 downto 0);
dac_data_out_a_n : out std_logic_vector(13 downto 0);
dac_data_out_b_p : out std_logic_vector(13 downto 0);
dac_data_out_b_n : out std_logic_vector(13 downto 0);
vdma_clk : in std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
vdma_dbg_data : out std_logic_vector(198 downto 0);
vdma_dbg_trigger : out std_logic_vector(7 downto 0);
dac_div3_clk : out std_logic;
dac_dbg_data : out std_logic_vector(292 downto 0);
dac_dbg_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
dac_clk_in_p => dac_clk_in_p,
dac_clk_in_n => dac_clk_in_n,
dac_clk_out_p => dac_clk_out_p,
dac_clk_out_n => dac_clk_out_n,
dac_data_out_a_p => dac_data_out_a_p,
dac_data_out_a_n => dac_data_out_a_n,
dac_data_out_b_p => dac_data_out_b_p,
dac_data_out_b_n => dac_data_out_b_n,
vdma_clk => vdma_clk,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
vdma_dbg_data => vdma_dbg_data,
vdma_dbg_trigger => vdma_dbg_trigger,
dac_div3_clk => dac_div3_clk,
dac_dbg_data => dac_dbg_data,
dac_dbg_trigger => dac_dbg_trigger,
delay_clk => delay_clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | ebb708a9ec4f1abcdeb88d9b701210f5 | 0.555251 | 2.977608 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_cap_reg.vhd | 1 | 7,626 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver channel status capture module ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.4 2004/07/19 16:58:37 gedra
-- Fixed bug.
--
-- Revision 1.3 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.2 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.1 2004/06/05 17:16:46 gedra
-- Channel status/user data capture register
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rx_package.all;
entity rx_cap_reg is
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
--cap_ctrl_wr: in std_logic; -- control register write
--cap_ctrl_rd: in std_logic; -- control register read
--cap_data_rd: in std_logic; -- data register read
cap_reg: in std_logic_vector(31 downto 0);
cap_din: in std_logic_vector(31 downto 0); -- write data
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
ud_a_en: in std_logic; -- user data ch. A enable
ud_b_en: in std_logic; -- user data ch. B enable
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
cap_dout: out std_logic_vector(31 downto 0); -- read data
cap_evt: out std_logic); -- capture event (interrupt)
end rx_cap_reg;
architecture rtl of rx_cap_reg is
signal cap_ctrl_bits, cap_ctrl_dout: std_logic_vector(31 downto 0);
signal cap_reg_1, cap_new : std_logic_vector(31 downto 0);
signal bitlen, cap_len : integer range 0 to 63;
signal bitpos, cur_pos : integer range 0 to 255;
signal chid, cdata, compared : std_logic;
signal d_enable : std_logic_vector(3 downto 0);
begin
-- Data bus or'ing
cap_dout <= cap_reg_1;-- when cap_data_rd = '1' else cap_ctrl_dout;
chid <= cap_reg(6);
cdata <= cap_reg(7);
-- capture data register
CDAT: process (clk, rst)
begin
if rst = '1' then
cap_reg_1 <= (others => '0'); --
cap_new <= (others => '0');
cur_pos <= 0;
cap_len <= 0;
cap_evt <= '0';
compared <= '0';
bitpos <= 0;
bitlen <= 0;
else
if rising_edge(clk) then
bitlen <= to_integer(unsigned(cap_reg(5 downto 0)));
bitpos <= to_integer(unsigned(cap_reg(15 downto 8)));
if bitlen > 0 then -- bitlen = 0 disables the capture function
-- bit counter, 0 to 191
if rx_block_start = '1' then
cur_pos <= 0;
cap_len <= 0;
cap_new <= (others => '0');
compared <= '0';
elsif cs_b_en = '1' then -- ch. status #2 comes last, count then
cur_pos <= cur_pos + 1;
end if;
-- capture bits
if cur_pos >= bitpos and cap_len < bitlen then
case d_enable is
when "0001" => -- user data channel A
if cdata = '0' and chid = '0' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "0010" => -- user data channel B
if cdata = '0' and chid = '1' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "0100" => -- channel status ch. A
if cdata = '1' and chid = '0' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when "1000" => -- channel status ch. B
if cdata = '1' and chid = '1' then
cap_new(cap_len) <= ch_data;
cap_len <= cap_len + 1;
end if;
when others => null;
end case;
end if;
-- if all bits captured, check with previous data
if cap_len = bitlen and compared = '0' then
compared <= '1';
-- event generated if captured bits differ
if cap_reg_1 /= cap_new then
cap_evt <= '1';
end if;
cap_reg_1 <= cap_new;
else
cap_evt <= '0';
end if;
end if;
end if;
end if;
end process CDAT;
d_enable(0) <= ud_a_en;
d_enable(1) <= ud_b_en;
d_enable(2) <= cs_a_en;
d_enable(3) <= cs_b_en;
end rtl;
| mit | fd31f5e1aa94fce635093d002a781202 | 0.420666 | 4.462259 | false | false | false | false |
EPiCS/soundgates | hardware/basic/sawtooth/sawtooth_tb.vhd | 1 | 1,653 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY sawtooth_tb IS
END sawtooth_tb;
ARCHITECTURE behavior OF sawtooth_tb IS
COMPONENT sawtooth
PORT(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
signal offset : signed(31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr : signed(31 downto 0) := to_signed(integer(real(0.1 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr2 : signed(31 downto 0) := to_signed(integer(real(0.05 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--Outputs
signal saw : signed(31 downto 0);
signal saw1 : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
uut: sawtooth PORT MAP (
clk => clk,
rst => rst,
ce => ce,
incr => incr,
offset => offset,
saw => saw
);
uut2: sawtooth PORT MAP (
clk => clk,
rst => rst,
ce => ce,
incr => incr2,
offset => offset,
saw => saw1
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| mit | b67446cf6f3bb0a8bb87b8ece29cfddf | 0.553539 | 3.312625 | false | false | false | false |
theapi/nand2tetris_fpga | hack/ip/qsys/qsys/qsys_inst.vhd | 1 | 7,177 | component qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_clock_areset_conduit_export : in std_logic := 'X'; -- export
sdram_clock_c0_clk : out std_logic; -- clk
sdram_read_control_fixed_location : in std_logic := 'X'; -- fixed_location
sdram_read_control_read_base : in std_logic_vector(31 downto 0) := (others => 'X'); -- read_base
sdram_read_control_read_length : in std_logic_vector(31 downto 0) := (others => 'X'); -- read_length
sdram_read_control_go : in std_logic := 'X'; -- go
sdram_read_control_done : out std_logic; -- done
sdram_read_control_early_done : out std_logic; -- early_done
sdram_read_user_read_buffer : in std_logic := 'X'; -- read_buffer
sdram_read_user_buffer_output_data : out std_logic_vector(63 downto 0); -- buffer_output_data
sdram_read_user_data_available : out std_logic; -- data_available
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
sdram_write_control_fixed_location : in std_logic := 'X'; -- fixed_location
sdram_write_control_write_base : in std_logic_vector(31 downto 0) := (others => 'X'); -- write_base
sdram_write_control_write_length : in std_logic_vector(31 downto 0) := (others => 'X'); -- write_length
sdram_write_control_go : in std_logic := 'X'; -- go
sdram_write_control_done : out std_logic; -- done
sdram_write_user_write_buffer : in std_logic := 'X'; -- write_buffer
sdram_write_user_buffer_input_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- buffer_input_data
sdram_write_user_buffer_full : out std_logic -- buffer_full
);
end component qsys;
u0 : component qsys
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_clock_areset_conduit_export => CONNECTED_TO_sdram_clock_areset_conduit_export, -- sdram_clock_areset_conduit.export
sdram_clock_c0_clk => CONNECTED_TO_sdram_clock_c0_clk, -- sdram_clock_c0.clk
sdram_read_control_fixed_location => CONNECTED_TO_sdram_read_control_fixed_location, -- sdram_read_control.fixed_location
sdram_read_control_read_base => CONNECTED_TO_sdram_read_control_read_base, -- .read_base
sdram_read_control_read_length => CONNECTED_TO_sdram_read_control_read_length, -- .read_length
sdram_read_control_go => CONNECTED_TO_sdram_read_control_go, -- .go
sdram_read_control_done => CONNECTED_TO_sdram_read_control_done, -- .done
sdram_read_control_early_done => CONNECTED_TO_sdram_read_control_early_done, -- .early_done
sdram_read_user_read_buffer => CONNECTED_TO_sdram_read_user_read_buffer, -- sdram_read_user.read_buffer
sdram_read_user_buffer_output_data => CONNECTED_TO_sdram_read_user_buffer_output_data, -- .buffer_output_data
sdram_read_user_data_available => CONNECTED_TO_sdram_read_user_data_available, -- .data_available
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
sdram_write_control_fixed_location => CONNECTED_TO_sdram_write_control_fixed_location, -- sdram_write_control.fixed_location
sdram_write_control_write_base => CONNECTED_TO_sdram_write_control_write_base, -- .write_base
sdram_write_control_write_length => CONNECTED_TO_sdram_write_control_write_length, -- .write_length
sdram_write_control_go => CONNECTED_TO_sdram_write_control_go, -- .go
sdram_write_control_done => CONNECTED_TO_sdram_write_control_done, -- .done
sdram_write_user_write_buffer => CONNECTED_TO_sdram_write_user_write_buffer, -- sdram_write_user.write_buffer
sdram_write_user_buffer_input_data => CONNECTED_TO_sdram_write_user_buffer_input_data, -- .buffer_input_data
sdram_write_user_buffer_full => CONNECTED_TO_sdram_write_user_buffer_full -- .buffer_full
);
| mit | f77200e1c96b3d69f701453c25ccbf85 | 0.446426 | 4.068594 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/axi_spdif_tx.vhd | 1 | 10,466 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Copyright 2011-2013(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- [email protected] (c) Analog Devices Inc.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_spdif_tx_v1_00_a;
use axi_spdif_tx_v1_00_a.tx_package.all;
library adi_common_v1_00_a;
use adi_common_v1_00_a.axi_ctrlif;
use adi_common_v1_00_a.axi_streaming_dma_tx_fifo;
use adi_common_v1_00_a.pl330_dma_fifo;
entity axi_spdif_tx is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_DMA_TYPE : integer := 0
);
port (
--SPDIF ports
spdif_data_clk : in std_logic;
spdif_tx_o : out std_logic;
--AXI Lite interface
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic;
--AXI streaming interface
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
--PL330 DMA interface
DMA_REQ_ACLK : in std_logic;
DMA_REQ_RSTN : in std_logic;
DMA_REQ_DAVALID : in std_logic;
DMA_REQ_DATYPE : in std_logic_vector(1 downto 0);
DMA_REQ_DAREADY : out std_logic;
DMA_REQ_DRVALID : out std_logic;
DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0);
DMA_REQ_DRLAST : out std_logic;
DMA_REQ_DRREADY : in std_logic
);
end entity axi_spdif_tx;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_spdif_tx is
------------------------------------------
-- SPDIF signals
------------------------------------------
signal config_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal chstat_freq : std_logic_vector(1 downto 0);
signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic;
signal sample_data_ack : std_logic;
signal sample_data: std_logic_vector(15 downto 0);
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_ratio : std_logic_vector(7 downto 0);
signal conf_tinten, conf_txdata, conf_txen : std_logic;
signal channel : std_logic;
signal fifo_data_out : std_logic_vector(31 downto 0);
signal fifo_reset : std_logic;
signal tx_fifo_stb : std_logic;
-- Register access
signal wr_data : std_logic_vector(31 downto 0);
signal rd_data : std_logic_vector(31 downto 0);
signal wr_addr : integer range 0 to 3;
signal rd_addr : integer range 0 to 3;
signal wr_stb : std_logic;
signal rd_ack : std_logic;
begin
fifo_reset <= not conf_txdata;
streaming_dma_gen: if C_DMA_TYPE = 0 generate
fifo: entity axi_streaming_dma_tx_fifo
generic map (
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => fifo_reset,
enable => conf_txdata = '1',
S_AXIS_ACLK => S_AXIS_ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TVALID => S_AXIS_TLAST,
S_AXIS_TLAST => S_AXIS_TVALID,
out_ack => channel and sample_data_ack,
out_data => fifo_data_out
);
end generate;
pl330_dma_gen: if C_DMA_TYPE = 1 generate
tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0';
fifo: entity pl330_dma_fifo
generic map(
RAM_ADDR_WIDTH => 3,
FIFO_DWIDTH => 32,
FIFO_DIRECTION => 0
)
port map (
clk => S_AXI_ACLK,
resetn => S_AXI_ARESETN,
fifo_reset => fifo_reset,
enable => conf_txdata = '1',
in_data => wr_data,
in_stb => tx_fifo_stb,
out_ack => channel and sample_data_ack,
out_data => fifo_data_out,
dclk => DMA_REQ_ACLK,
dresetn => DMA_REQ_RSTN,
davalid => DMA_REQ_DAVALID,
daready => DMA_REQ_DAREADY,
datype => DMA_REQ_DATYPE,
drvalid => DMA_REQ_DRVALID,
drready => DMA_REQ_DRREADY,
drtype => DMA_REQ_DRTYPE,
drlast => DMA_REQ_DRLAST
);
end generate;
sample_data_mux: process (fifo_data_out, channel) is
begin
if channel = '0' then
sample_data <= fifo_data_out(15 downto 0);
else
sample_data <= fifo_data_out(31 downto 16);
end if;
end process;
-- Configuration signals update
conf_mode(3 downto 0) <= config_reg(23 downto 20);
conf_ratio(7 downto 0) <= config_reg(15 downto 8);
conf_tinten <= config_reg(2);
conf_txdata <= config_reg(1);
conf_txen <= config_reg(0);
-- Channel status signals update
chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6);
chstat_gstat <= chstatus_reg(3);
chstat_preem <= chstatus_reg(2);
chstat_copy <= chstatus_reg(1);
chstat_audio <= chstatus_reg(0);
-- Transmit encoder
TENC: tx_encoder
generic map (
DATA_WIDTH => 16
)
port map (
up_clk => S_AXI_ACLK,
data_clk => spdif_data_clk, -- data clock
resetn => S_AXI_ARESETN, -- resetn
conf_mode => conf_mode, -- sample format
conf_ratio => conf_ratio, -- clock divider
conf_txdata => conf_txdata, -- sample data enable
conf_txen => conf_txen, -- spdif signal enable
chstat_freq => chstat_freq, -- sample freq.
chstat_gstat => chstat_gstat, -- generation status
chstat_preem => chstat_preem, -- preemphasis status
chstat_copy => chstat_copy, -- copyright bit
chstat_audio => chstat_audio, -- data format
sample_data => sample_data, -- audio data
sample_data_ack => sample_data_ack, -- sample buffer read
channel => channel, -- which channel should be read
spdif_tx_o => spdif_tx_o -- SPDIF output signal
);
ctrlif: entity axi_ctrlif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_REG => 4
)
port map(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
rd_addr => rd_addr,
rd_data => rd_data,
rd_ack => rd_ack,
rd_stb => '1',
wr_addr => wr_addr,
wr_data => wr_data,
wr_ack => '1',
wr_stb => wr_stb
);
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
config_reg <= (others => '0');
chstatus_reg <= (others => '0');
else
if wr_stb = '1' then
case wr_addr is
when 0 => config_reg <= wr_data;
when 1 => chstatus_reg <= wr_data;
when others => null;
end case;
end if;
end if;
end if;
end process;
process (rd_addr)
begin
case rd_addr is
when 0 => rd_data <= config_reg;
when 1 => rd_data <= chstatus_reg;
when others => rd_data <= (others => '0');
end case;
end process;
end IMP;
| mit | 0588a1850a6dd2fcc0d636c7874d5872 | 0.609497 | 2.999713 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/util_i2c_mixer_v1_00_a/hdl/vhdl/util_i2c_mixer.vhd | 2 | 1,540 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.all;
entity util_i2c_mixer is
generic (
C_WIDTH: integer := 2
);
port (
upstream_scl_T : in std_logic;
upstream_scl_I : in std_logic;
upstream_scl_O : out std_logic;
upstream_sda_T : in std_logic;
upstream_sda_I : in std_logic;
upstream_sda_O : out std_logic;
downstream_scl_T : out std_logic;
downstream_scl_I : in std_logic_vector(C_WIDTH - 1 downto 0);
downstream_scl_O : out std_logic_vector(C_WIDTH - 1 downto 0);
downstream_sda_T : out std_logic;
downstream_sda_I : in std_logic_vector(C_WIDTH - 1 downto 0);
downstream_sda_O : out std_logic_vector(C_WIDTH - 1 downto 0)
);
end util_i2c_mixer;
architecture IMP of util_i2c_mixer is
begin
upstream_scl_O <= '1' when (downstream_scl_I = (downstream_scl_I'range => '1')) else '0';
upstream_sda_O <= '1' when (downstream_sda_I = (downstream_sda_I'range => '1')) else '0';
downstream_scl_T <= upstream_scl_T;
downstream_sda_T <= upstream_sda_T;
GEN: for i in 0 to C_WIDTH - 1 generate
downstream_scl_O(i) <= upstream_scl_I;
downstream_sda_O(i) <= upstream_sda_I;
end generate GEN;
end IMP;
| mit | 9c8ae216365c2bebeca05759f2bde64e | 0.538961 | 3.136456 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_wb_decoder.vhd | 1 | 10,684 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver: Wishbone bus cycle decoder. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/24 19:25:03 gedra
-- Added data output.
--
-- Revision 1.1 2004/06/23 18:09:57 gedra
-- Wishbone bus cycle decoder.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx_wb_decoder is
generic (DATA_WIDTH: integer;
ADDR_WIDTH: integer);
port (
wb_clk_i: in std_logic; -- wishbone clock
wb_rst_i: in std_logic; -- reset signal
wb_sel_i: in std_logic; -- select input
wb_stb_i: in std_logic; -- strobe input
wb_we_i: in std_logic; -- write enable
wb_cyc_i: in std_logic; -- cycle input
wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension
wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
wb_ack_o: out std_logic; -- acknowledge
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
version_rd: out std_logic; -- Version register read
config_rd: out std_logic; -- Config register read
config_wr: out std_logic; -- Config register write
status_rd: out std_logic; -- Status register read
intmask_rd: out std_logic; -- Interrupt mask register read
intmask_wr: out std_logic; -- Interrupt mask register write
intstat_rd: out std_logic; -- Interrupt status register read
intstat_wr: out std_logic; -- Interrupt status register read
mem_rd: out std_logic; -- Sample memory read
mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr.
ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read
ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
end rx_wb_decoder;
architecture rtl of rx_wb_decoder is
constant REG_RXVERSION : std_logic_vector(6 downto 0) := "0000000";
constant REG_RXCONFIG : std_logic_vector(6 downto 0) := "0000001";
constant REG_RXSTATUS : std_logic_vector(6 downto 0) := "0000010";
constant REG_RXINTMASK : std_logic_vector(6 downto 0) := "0000011";
constant REG_RXINTSTAT : std_logic_vector(6 downto 0) := "0000100";
signal iack, iwr, ird : std_logic;
signal acnt: integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal rdout : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
wb_ack_o <= iack;
-- acknowledge generation
ACK: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
iack <= '0';
elsif rising_edge(wb_clk_i) then
if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then
case wb_cti_i is
when "010" => -- incrementing burst
case wb_bte_i is -- burst extension
when "00" => -- linear burst
iack <= '1';
when others => -- all other treated assert classic cycle
iack <= not iack;
end case;
when "111" => -- end of burst
iack <= not iack;
when others => -- all other treated assert classic cycle
iack <= not iack;
end case;
else
iack <= '0';
end if;
end if;
end process ACK;
-- write generation
WR: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
iwr <= '0';
elsif rising_edge(wb_clk_i) then
if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
wb_we_i = '1' then
case wb_cti_i is
when "010" => -- incrementing burst
case wb_bte_i is -- burst extension
when "00" => -- linear burst
iwr <= '1';
when others => -- all other treated assert classic cycle
iwr <= not iwr;
end case;
when "111" => -- end of burst
iwr <= not iwr;
when others => -- all other treated assert classic cycle
iwr <= not iwr;
end case;
else
iwr <= '0';
end if;
end if;
end process WR;
-- read generation
ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
wb_we_i = '0' else '0';
wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout;
DREG: process (wb_clk_i) -- clock data from registers
begin
if rising_edge(wb_clk_i) then
rdout <= data_out;
end if;
end process DREG;
-- sample memory read address. This needs special attention due to read latency
mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when
wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1');
SMA: process (wb_clk_i, wb_rst_i)
begin
if wb_rst_i = '1' then
acnt <= 0;
elsif rising_edge(wb_clk_i) then
if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then
if iack = '0' then
if wb_adr_i = all_ones then
acnt <= 0;
else
acnt <= to_integer(unsigned(wb_adr_i)) + 1;
end if;
else
if acnt < 2**(ADDR_WIDTH - 1) - 1 then
acnt <= acnt + 1;
else
acnt <= 0;
end if;
end if;
end if;
end if;
end process SMA;
-- read and write strobe generation
version_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXVERSION and ird = '1'
else '0';
config_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and ird = '1'
else '0';
config_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and iwr = '1'
else '0';
status_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXSTATUS and ird = '1'
else '0';
intmask_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and ird = '1'
else '0';
intmask_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and iwr = '1'
else '0';
intstat_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and ird = '1'
else '0';
intstat_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and iwr = '1'
else '0';
mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
-- capture register strobes
CR32: if DATA_WIDTH = 32 generate
CRST: for k in 0 to 7 generate
ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
else '0';
ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k,4))
else '0';
ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1,4))
else '0';
end generate CRST;
end generate CR32;
CR16: if DATA_WIDTH = 16 generate
ch_st_cap_rd(7 downto 0) <= (others => '0');
ch_st_cap_wr(7 downto 0) <= (others => '0');
ch_st_data_rd(7 downto 0) <= (others => '0');
end generate CR16;
end rtl;
| mit | f2e4e04e560aac2691cd7d460b1e7fcb | 0.470704 | 3.872418 | false | false | false | false |
aylons/sp601_spi_test | hdl/modules/slave_checker/slave_checker.vhd | 1 | 2,470 | -------------------------------------------------------------------------------
-- Title : Slave checker
-- Project :
-------------------------------------------------------------------------------
-- File : slave_checker.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-23
-- Last update: 2014-10-30
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Checks if slave is receiving incremental data and output the result
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-23 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity slave_checker is
generic (
g_width : natural := 16
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
spi_valid_i : in std_logic;
data_i : in std_logic_vector(g_width-1 downto 0);
ok_o : out std_logic;
nok_o : out std_logic
);
end entity slave_checker;
-------------------------------------------------------------------------------
architecture str of slave_checker is
signal valid_d : std_logic;
begin -- architecture str
getdata : process(clk_i)
variable cur_data : unsigned(g_width-1 downto 0);
variable prev_data : unsigned(g_width-1 downto 0);
begin
if rising_edge(clk_i) then
if rst_i = '1' then
prev_data := (others => '0');
valid_d <= '0';
else
cur_data := unsigned(data_i);
-- valid from spi slave is active for 2 cycles, get only the first
if(spi_valid_i = '1' and valid_d = '0') then
if cur_data = prev_data then
ok_o <= '1';
else
nok_o <= '1';
end if;
prev_data := cur_data + 1;
else
ok_o <= '0';
nok_o <= '0';
end if; -- newdata
valid_d <= spi_valid_i;
end if; --rst
end if; -- clk_i
end process;
end architecture str;
| gpl-3.0 | 2928a4d04465a4d1adb7c2eb3064aeb2 | 0.41336 | 4.251291 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_nco_v1_00_a/hdl/vhdl/hwt_nco_tb.vhd | 1 | 6,429 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
Library unimacro;
use unimacro.vcomponents.all;
ENTITY hwt_nco_tb IS
END hwt_nco_tb;
ARCHITECTURE behavior OF hwt_nco_tb IS
COMPONENT hwt_nco
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000;
SND_COMP_NCO_TPYE : integer := 0
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
END COMPONENT;
-- OSIF FIFO ports
signal OSIF_FIFO_Sw2Hw_Data : std_logic_vector(31 downto 0);-- := (others => '0');
signal OSIF_FIFO_Sw2Hw_Fill : std_logic_vector(8 downto 0);-- := (others => '0');
signal OSIF_FIFO_Sw2Hw_Empty : std_logic;-- := '1';
signal OSIF_FIFO_Sw2Hw_RE : std_logic;
signal osif_fifo_sw2hw_din : std_logic_vector(31 downto 0) := (others => '0');
signal osif_fifo_sw2hw_wren : std_logic := '0';
signal osif_fifo_sw2hw_rdcount : std_logic_vector(8 downto 0);
signal OSIF_FIFO_Hw2Sw_Data : std_logic_vector(31 downto 0);
signal OSIF_FIFO_Hw2Sw_Rem : std_logic_vector(15 downto 0);
signal OSIF_FIFO_Hw2Sw_Full : std_logic := '0';
signal OSIF_FIFO_Hw2Sw_WE : std_logic;
-- MEMIF FIFO ports
signal MEMIF_FIFO_Hwt2Mem_Data : std_logic_vector(31 downto 0);
signal MEMIF_FIFO_Hwt2Mem_Rem : std_logic_vector(15 downto 0);
signal MEMIF_FIFO_Hwt2Mem_Full : std_logic;
signal MEMIF_FIFO_Hwt2Mem_WE : std_logic;
signal MEMIF_FIFO_Mem2Hwt_Data : std_logic_vector(31 downto 0);
signal MEMIF_FIFO_Mem2Hwt_Fill : std_logic_vector(15 downto 0);
signal MEMIF_FIFO_Mem2Hwt_Empty : std_logic;
signal MEMIF_FIFO_Mem2Hwt_RE : std_logic;
signal HWT_Clk : std_logic;
signal HWT_Rst : std_logic;
signal clk : std_logic;
signal rst : std_logic;
constant clk_period : time := 10 ns;
constant NCO_START : std_logic_vector(31 downto 0) := x"0000000F";
constant NCO_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
signal OSIF_FIFO_Sw2Hw_Fill_extend : std_logic_vector(15 downto 0);
BEGIN
HWT_Clk <= clk;
HWT_Rst <= rst;
OSIF_FIFO_Sw2Hw_Fill_extend <= "0000000" & OSIF_FIFO_Sw2Hw_Fill;
-- Component Instantiation
uut: hwt_nco PORT MAP(
OSIF_FIFO_Sw2Hw_Data => OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill => OSIF_FIFO_Sw2Hw_Fill_extend,
OSIF_FIFO_Sw2Hw_Empty => OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Sw2Hw_RE => OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data => OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_Rem => OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full => OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Hw2Sw_WE => OSIF_FIFO_Hw2Sw_WE,
MEMIF_FIFO_Hwt2Mem_Data => MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_Rem => MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full => MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Hwt2Mem_WE => MEMIF_FIFO_Hwt2Mem_WE,
MEMIF_FIFO_Mem2Hwt_Data => MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill => MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty => MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Mem2Hwt_RE => MEMIF_FIFO_Mem2Hwt_RE,
HWT_Clk => HWT_Clk,
HWT_Rst => HWT_Rst
);
OSIF_SW2HW_FIFO_INST : FIFO_SYNC_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5, "VIRTEX6", "7SERIES"
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DATA_WIDTH => 32,-- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb") -- Target BRAM, "18Kb" or "36Kb"
port map ( ALMOSTEMPTY => open, -- 1-bit output almost empty
ALMOSTFULL => open, -- 1-bit output almost full
DO => OSIF_FIFO_Sw2Hw_Data, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => OSIF_FIFO_Sw2Hw_Empty, -- 1-bit output empty
FULL => open, -- 1-bit output full
RDCOUNT => osif_fifo_sw2hw_rdcount,-- Output read count, width determined by FIFO depth
RDERR => open, -- 1-bit output read error
WRCOUNT => OSIF_FIFO_Sw2Hw_Fill, -- Output write count, width determined by FIFO depth
WRERR => open, -- 1-bit output write error
CLK => clk, -- 1-bit input clock
DI => osif_fifo_sw2hw_din, -- Input data, width defined by DATA_WIDTH parameter
RDEN => OSIF_FIFO_Sw2Hw_RE, -- 1-bit input read enable
RST => rst, -- 1-bit input reset
WREN => osif_fifo_sw2hw_wren-- 1-bit input write enable
);
-- End of FIFO_SYNC_MACRO_inst instantiation
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stimulus_process :process
begin
rst <= '0';
wait for clk_period*10;
--rst <= '0';
osif_fifo_sw2hw_din <= NCO_START;
wait for clk_period;
osif_fifo_sw2hw_wren <= '1';
--OSIF_FIFO_Sw2Hw_Data <= NCO_START;
--OSIF_FIFO_Sw2Hw_Fill <= std_logic_vector(to_unsigned(1, 16));
end process;
END;
| mit | d73c5901eadfcaf29a14effd7a138e51 | 0.600871 | 3.105797 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_sample_add_v1_00_a/hdl/vhdl/hwt_sample_add.vhd | 1 | 13,021 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sample_add
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating add envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sample_add is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sample_add;
architecture Behavioral of hwt_sample_add is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_add : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_add2: std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_add : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_add : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_add2: std_logic_vector(0 to 31);
signal o_RAMWE_add : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal add_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_add <= std_logic_vector(add_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_add = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_add))) := o_RAMData_add;
else -- else needed, because add is consuming samples
i_RAMData_add <= local_ram(to_integer(unsigned(o_RAMAddr_add)));
i_RAMData_add2<= local_ram(to_integer(unsigned(o_RAMAddr_add2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_add<= '0';
o_RAMAddr_add <= (others => '0');
o_RAMAddr_add2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_add2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
add_data <= signed(i_RAMData_add) + signed(i_RAMData_add2);
process_state <= 1;
when 1 =>
o_RAMData_add <= std_logic_vector(resize(add_data, 32));
o_RAMWE_add <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_add <= '0';
o_RAMAddr_add <= std_logic_vector(unsigned(o_RAMAddr_add) + 1);
o_RAMAddr_add2 <= std_logic_vector(unsigned(o_RAMAddr_add2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_add <= (others => '0');
o_RAMAddr_add2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | c18cf1fca6578f22406847c2da5a36cb | 0.488519 | 3.681368 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_triangle_v1_00_a/hdl/vhdl/hwt_triangle.vhd | 1 | 13,328 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_triangle
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for a triangle wave
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_triangle is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_triangle;
architecture Behavioral of hwt_triangle is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component triangle is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
tri : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_tri : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_tri : std_logic_vector(0 to 31); -- tri to local ram
signal i_RAMData_tri : std_logic_vector(0 to 31); -- local ram to tri
signal o_RAMWE_tri : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal tri_ce : std_logic; -- tri clock enable (like a start/stop signal)
signal phase_offset_addr : std_logic_vector(31 downto 0);
signal phase_incr_addr : std_logic_vector(31 downto 0);
signal phase_offset : std_logic_vector(31 downto 0);
signal phase_incr : std_logic_vector(31 downto 0);
signal tri_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant tri_START : std_logic_vector(31 downto 0) := x"0000000F";
constant tri_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_tri <= std_logic_vector(tri_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
tri_inst : triangle
port map(
clk => clk,
rst => rst,
ce => tri_ce,
incr => signed(phase_incr),
offset => signed(phase_offset),
tri => tri_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_tri = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_tri))) := o_RAMData_tri;
--else -- else not needed, because tri is not consuming any samples
-- i_RAMData_tri <= local_ram(conv_integer(unsigned(o_RAMAddr_tri)));
end if;
end if;
end process;
tri_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
tri_ce <= '0';
o_RAMWE_tri <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
tri_ce <= '0';
o_RAMWE_tri <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
phase_offset_addr <= snd_comp_header.opt_arg_addr;
phase_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = tri_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = tri_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, phase_offset_addr, phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_PHASE_INCR =>
memif_read_word(i_memif, o_memif, phase_incr_addr, phase_incr, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_tri <= '1';
tri_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_tri <= std_logic_vector(unsigned(o_RAMAddr_tri) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_tri <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | b442baee554afef34fcb5c538a82d87d | 0.488782 | 3.716397 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_16b_es_v1_00_a/hdl/vhdl/axi_hdmi_16b_es.vhd | 1 | 11,776 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_hdmi_16b_es is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
h2v_hdmi_clk : in std_logic;
h2v_hdmi_data : in std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
h2v_vdma_fs : out std_logic;
h2v_vdma_fs_ret : in std_logic;
h2v_vdma_full : in std_logic;
h2v_vdma_almost_full : in std_logic;
up_status : out std_logic_vector(7 downto 0);
vdma_dbg_data : out std_logic_vector(75 downto 0);
vdma_dbg_trigger : out std_logic_vector(15 downto 0);
h2v_dbg_data : out std_logic_vector(61 downto 0);
h2v_dbg_trigger : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TVALID : out std_logic;
S_AXIS_S2MM_TKEEP : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TDATA : out std_logic_vector(63 downto 0);
S_AXIS_S2MM_TLAST : out std_logic;
S_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_hdmi_16b_es;
architecture IMP of axi_hdmi_16b_es is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
h2v_hdmi_clk : in std_logic;
h2v_hdmi_data : in std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
h2v_vdma_fs : out std_logic;
h2v_vdma_fs_ret : in std_logic;
h2v_vdma_valid : out std_logic;
h2v_vdma_be : out std_logic_vector(7 downto 0);
h2v_vdma_data : out std_logic_vector(63 downto 0);
h2v_vdma_last : out std_logic;
h2v_vdma_ready : in std_logic;
h2v_vdma_full : in std_logic;
h2v_vdma_almost_full : in std_logic;
up_status : out std_logic_vector(7 downto 0);
vdma_dbg_data : out std_logic_vector(75 downto 0);
vdma_dbg_trigger : out std_logic_vector(15 downto 0);
h2v_dbg_data : out std_logic_vector(61 downto 0);
h2v_dbg_trigger : out std_logic_vector(7 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
h2v_hdmi_clk => h2v_hdmi_clk,
h2v_hdmi_data => h2v_hdmi_data,
vdma_clk => vdma_clk,
h2v_vdma_fs => h2v_vdma_fs,
h2v_vdma_fs_ret => h2v_vdma_fs_ret,
h2v_vdma_valid => S_AXIS_S2MM_TVALID,
h2v_vdma_be => S_AXIS_S2MM_TKEEP,
h2v_vdma_data => S_AXIS_S2MM_TDATA,
h2v_vdma_last => S_AXIS_S2MM_TLAST,
h2v_vdma_ready => S_AXIS_S2MM_TREADY,
h2v_vdma_full => h2v_vdma_full,
h2v_vdma_almost_full => h2v_vdma_almost_full,
up_status => up_status,
vdma_dbg_data => vdma_dbg_data,
vdma_dbg_trigger => vdma_dbg_trigger,
h2v_dbg_data => h2v_dbg_data,
h2v_dbg_trigger => h2v_dbg_trigger,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | d5ae74ef900a3c59389554f2959a7afe | 0.516984 | 3.189599 | false | false | false | false |
spiersad/ECGR4146-FIFO | RAM.vhd | 1 | 1,230 | --N x K RAM is 2-dimensional array of N K-bit words
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAM is
generic (K: integer:=64; --number of bits per word
W: integer:=8); --number of address bits; N = 2^W
port(
WR: in std_logic; --active high write enable
ADDR: in std_logic_vector(W-1 downto 0); --RAM address
DIN : in std_logic_vector(K-1 downto 0); --write data
DOUT: out std_logic_vector(K-1 downto 0)); --read data
end entity RAM;
architecture RAMBEHAVIOR of RAM is
subtype WORD is std_logic_vector( K-1 downto 0) ; --define size of WORD
type MEMORY is array (0 to 2**W-1) of WORD;--define size of MEMORY
signal RAM256: MEMORY := ((others=> (others=>'0')));--define RAM256 as signal of type MEMORY
begin
process (WR, DIN, ADDR)
variable RAM_ADDR_IN: natural range 0 to 2**W-1;--translate address to integer
begin
RAM_ADDR_IN := TO_INTEGER(UNSIGNED(ADDR));--convert address to integer
if (WR='1') then--write operation to RAM
RAM256 (RAM_ADDR_IN) <= DIN ;
end if;
DOUT <= RAM256 (RAM_ADDR_IN);--always does read operation
end process;
end architecture RAMBEHAVIOR; | gpl-2.0 | 7f2c8b1581020f431ac85d4d4a4051cd | 0.643089 | 3.494318 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_pwm_v1_00_a/hdl/vhdl/hwt_pwm.vhd | 1 | 13,333 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_pwm
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating add envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_pwm is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_pwm;
architecture Behavioral of hwt_pwm is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_pwm : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_pwm2: std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_pwm : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_pwm : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_pwm2: std_logic_vector(0 to 31);
signal o_RAMWE_pwm : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
signal s_zero : signed(31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_one : signed(31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal add_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_pwm <= std_logic_vector(add_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_pwm = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_pwm))) := o_RAMData_pwm;
else -- else needed, because add is consuming samples
i_RAMData_pwm <= local_ram(to_integer(unsigned(o_RAMAddr_pwm)));
i_RAMData_pwm2<= local_ram(to_integer(unsigned(o_RAMAddr_pwm2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_pwm<= '0';
o_RAMAddr_pwm <= (others => '0');
o_RAMAddr_pwm2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_pwm2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
if signed(i_RAMData_pwm) > signed(i_RAMData_pwm2) then
add_data <= s_one ;
else
add_data <= s_zero;
end if;
process_state <= 1;
when 1 =>
o_RAMData_pwm <= std_logic_vector(resize(add_data, 32));
o_RAMWE_pwm <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_pwm <= '0';
o_RAMAddr_pwm <= std_logic_vector(unsigned(o_RAMAddr_pwm) + 1);
o_RAMAddr_pwm2 <= std_logic_vector(unsigned(o_RAMAddr_pwm2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_pwm <= (others => '0');
o_RAMAddr_pwm2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 596a9419724f5a4d6b1f0fbe3aa2f245 | 0.489537 | 3.650876 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_amplifier_v1_00_a/hdl/vhdl/hwt_amplifier.vhd | 1 | 13,882 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_amplifier
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for amplifying samples
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_amplifier is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_amplifier;
architecture Behavioral of hwt_amplifier is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component amplifier is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave : in signed(31 downto 0);
percentage: in signed(31 downto 0);
amp : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_amplifier : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_amplifier : std_logic_vector(0 to 31); -- amplifier to local ram
signal i_RAMData_amplifier : std_logic_vector(0 to 31); -- local ram to amplifier
signal o_RAMWE_amplifier : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal amplifier_ce : std_logic; -- amplifier clock enable (like a start/stop signal)
signal input_data : signed(31 downto 0);
signal amplifier_data : signed(31 downto 0);
signal amplifier_wave : signed(31 downto 0);
signal amplifier_value : signed(31 downto 0);
signal start : std_logic;
signal stop : std_logic;
signal refresh_state : integer;
signal process_state : integer;
signal factor : std_logic_vector(31 downto 0);
signal amp_addr : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant amplifier_START : std_logic_vector(31 downto 0) := x"0000000F";
constant amplifier_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_amplifier <= std_logic_vector(amplifier_data);
amplifier_wave <= signed(i_RAMData_amplifier);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
amplifier_INST : amplifier
port map(
clk => clk,
rst => rst,
ce => amplifier_ce,
wave => amplifier_wave,
percentage => signed(factor),
amp => amplifier_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_amplifier = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_amplifier))) := o_RAMData_amplifier;
else -- else needed, because amplifier is consuming samples
i_RAMData_amplifier <= local_ram(to_integer(unsigned(o_RAMAddr_amplifier)));
end if;
end if;
end process;
amplifier_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
amplifier_ce <= '0';
o_RAMWE_amplifier<= '0';
o_RAMAddr_amplifier <= (others => '0');
refresh_state <= 0;
process_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
amp_addr <= snd_comp_header.opt_arg_addr;
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = amplifier_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = amplifier_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, amp_addr , factor, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= 0;
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
amplifier_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_amplifier <= std_logic_vector(amplifier_data);
o_RAMWE_amplifier <= '1';
amplifier_ce <= '0';
process_state <= 2;
when 2 =>
o_RAMWE_amplifier <= '0';
o_RAMAddr_amplifier <= std_logic_vector(unsigned(o_RAMAddr_amplifier) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
when others =>
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_amplifier <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 76056c1cfa6aebe286f312ba83e078bd | 0.483504 | 3.851831 | false | false | false | false |
EPiCS/soundgates | hardware/basic/triangle/triangle_tb.vhd | 1 | 1,587 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY triangle_tb IS
END triangle_tb;
ARCHITECTURE behavior OF triangle_tb IS
COMPONENT triangle
PORT(
clk : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
tri : out signed(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal calc : std_logic := '1';
signal offset : signed(31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr : signed(31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal incr2 : signed(31 downto 0) := to_signed(integer(real(0.05 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--Outputs
signal tri : signed(31 downto 0);
signal tri1 : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
uut: triangle PORT MAP (
clk => clk,
ce => '1',
offset => offset,
incr => incr,
tri => tri
);
uut2: triangle PORT MAP (
clk => clk,
ce => '1',
offset => offset,
incr => incr2,
tri => tri1
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
END;
| mit | 853eff72324ed60591159beb867df78f | 0.549464 | 3.391026 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/fetch_Buffer.vhd | 1 | 4,481 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fetch_Buffer is
Generic ( n : integer := 16);
port(
Clk : in std_logic;
Rst : in std_logic;
inport_en_input : in std_logic_vector(15 downto 0); --
instruction_input :in std_logic_vector(15 downto 0);
inport_en_output : out std_logic_vector(15 downto 0); --
instruction_output :out std_logic_vector(15 downto 0);
OPcode: out std_logic_vector(4 downto 0 );
R1: out std_logic_vector(2 downto 0 ); --addres of reg1
R2: out std_logic_vector(2 downto 0 ); --addres of reg2
Rout: out std_logic_vector(2 downto 0 ); --for write back
R_shift: out std_logic_vector(3 downto 0 );
LDD_Memory: out std_logic_vector(9 downto 0 ); --load value from memory to register
LDM_immediate: out std_logic_vector(15 downto 0 ) ;--load immediate value from user to register
pc_mux_input : in std_logic_vector(1 downto 0);
--outport_en_input : in std_logic;
--reg_write_input : in std_logic;
--mem_write_input : in std_logic;
--write_data_reg_mux_input : in std_logic;
--Shift_Mux_input : in std_logic; -- to know if make shift or not
--write_back_mux_input : in std_logic_vector(1 downto 0);
--int_flags_en_input : in std_logic; -- int to take flags from meomry to alu
--alu_control_input : in std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
--mem_mux_input : in std_logic;
pc_mux_output : out std_logic_vector(1 downto 0)
--outport_en_output : out std_logic;
--reg_write_output : out std_logic;
--mem_write_output : out std_logic;
--write_data_reg_mux_output : out std_logic;
--Shift_Mux_output : out std_logic; -- to know if make shift or not
--write_back_mux_output : out std_logic_vector(1 downto 0);
--int_flags_en_output : out std_logic; -- int to take flags from meomry to alu
--alu_control_output : out std_logic_vector(4 downto 0); --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
--mem_mux_output : out std_logic
);
end fetch_Buffer;
architecture fetch_Buffer_arch of fetch_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
signal LDD_Memory_signal : std_logic_vector(9 downto 0 ); --load value from memory to register
signal LDM_immediate_signal : std_logic_vector(15 downto 0 ); --load value from memory to register
signal OPcode_nop: std_logic_vector(4 downto 0 );
signal en_signal_nop: std_logic;
begin
inport_en_output<=inport_en_input;
--call control unit
process(clk) is
begin
if (rising_edge(clk)) and instruction_input(15 downto 11)="11011" then
OPcode_nop <= "00000";
en_signal_nop <='1';
LDM_immediate<=instruction_input(15 downto 0);
elsif (rising_edge(clk) ) and ((instruction_input(15 downto 11))="11100" or instruction_input(15 downto 11)="11101") then
OPcode_nop <= "00000";
en_signal_nop <='1';--send to control unit
LDD_Memory<=instruction_input(15 downto 6);
elsif (rising_edge(clk)) then
en_signal_nop <='0';
instruction_output<=instruction_input;
OPcode<=instruction_input(15 downto 11);
R1<=instruction_input(10 downto 8);
R2<=instruction_input(7 downto 5);
R_shift<=instruction_input(7 downto 4);
Rout<=instruction_input(4 downto 2);
pc_mux_output <= pc_mux_input;
--outport_en_output <=outport_en_input;
--reg_write_output <=reg_write_input;
--mem_write_output <= mem_write_input;
--write_data_reg_mux_output <= write_data_reg_mux_input;
--Shift_Mux_output <= Shift_Mux_input;
--write_back_mux_output <= write_back_mux_input;
--int_flags_en_output <= int_flags_en_input; -- int to take flags from meomry to alu
--alu_control_output <= alu_control_input; --change it according to alu control (3 bit ****)??? ??? ???? 'musgi'
--mem_mux_output <= mem_mux_input;
end if;
end process;
end fetch_Buffer_arch;
| mit | 8720db738ee044e6ca30d742bd150164 | 0.619728 | 3.162315 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/soundgates_v1_00_a/hdl/vhdl/soundgates_common_pkg.vhd | 1 | 3,997 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL Package - soundgates_common_pkg
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Common functions, declaration, constants for sound
-- processing components
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
package soundgates_common_pkg is
-- Constant declarations
constant SOUNDGATE_FIX_PT_SCALING : real := 28.0;
constant MAX_NCO_FREQUNCY : integer := 16000;
constant SAMPLE_WIDTH : integer := 32;
-- Type declarations
type Phase_Increment_Array is array(0 to MAX_NCO_FREQUNCY) of signed(31 downto 0);
type WAVEFORM_TYPE is ( SIN, SQU, SAW, TRI);
type NOISE_TYPE is ( WHITE, PINK, GREY );
type ARITHMETIC_TYPE is ( ADD, SUB, MUL );
type mem16 is array (natural range <>) of signed(15 downto 0);
type mem24 is array (natural range <>) of signed(23 downto 0);
type mem32 is array (natural range <>) of signed(31 downto 0);
type mem64 is array (natural range <>) of signed(63 downto 0);
------------------------------------------------------------
-- Functions and Procedure declarations
------------------------------------------------------------
------------------------------------------------------------
function Precalculate_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array;
function Precalculate_Cordic_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array;
function Get_Cordic_Phase_Increment (FPGA_FREQUENCY, SIN_FREQUENCY : integer) return signed;
------------------------------------------------------------
end package soundgates_common_pkg;
package body soundgates_common_pkg is
function Get_Cordic_Phase_Increment (FPGA_FREQUENCY, SIN_FREQUENCY : integer) return signed is
variable stepsize : integer;
variable phi_incr_real : real;
variable phi_incr_signed : signed(31 downto 0);
begin
if SIN_FREQUENCY > 0 then
--stepsize := FPGA_FREQUENCY / SIN_FREQUENCY;
--phi_incr_real := MATH_PI * 2.0 / real(stepsize);
--phi_incr_signed := to_signed(integer(real(phi_incr_real) * 2**SOUNDGATE_FIX_PT_SCALING), 32);
phi_incr_real := (MATH_PI * 2.0 * real(SIN_FREQUENCY) / 44100.0) * 2**SOUNDGATE_FIX_PT_SCALING;
phi_incr_signed := to_signed(integer(phi_incr_real), 32);
else
phi_incr_signed := to_signed(0, 32);
end if;
return phi_incr_signed;
end Get_Cordic_Phase_Increment;
function Precalculate_Cordic_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array is
variable tmp : phase_increment_array;
variable stepsize : integer;
variable phi_offset : real;
begin
for i in 0 to MAX_NCO_FREQUNCY loop
if i > 0 then
stepsize := FPGA_FREQUENCY / i;
phi_offset := MATH_PI * 2.0 / real(stepsize);
tmp(i) := to_signed(integer(real(phi_offset) * 2**SOUNDGATE_FIX_PT_SCALING), 32);
else
tmp(i) := to_signed(0, 32);
end if;
end loop;
return tmp;
end Precalculate_Cordic_Phase_Increments;
function Precalculate_Phase_Increments (FPGA_FREQUENCY : integer) return Phase_Increment_Array is
variable tmp : phase_increment_array;
begin
for i in 0 to MAX_NCO_FREQUNCY loop
if i > 0 then
tmp(i) := to_signed(FPGA_FREQUENCY / i, 32);
else
tmp(i) := to_signed(0, 32);
end if;
end loop;
return tmp;
end Precalculate_Phase_Increments;
end package body soundgates_common_pkg;
| mit | 3d20fb0b71d4c7dbd8a1ec781af810d4 | 0.557418 | 3.562389 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/util_outclk_lvds_v1_00_a/hdl/vhdl/util_outclk_lvds.vhd | 1 | 4,153 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
-- this module simply generates an fpga output clock from an input clock net
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.all;
entity util_outclk_lvds is
port (
ref_clk : in std_logic; -- clock input
clk_out_p : out std_logic; -- output clock (lvds)
clk_out_n : out std_logic
);
end util_outclk_lvds;
architecture IMP of util_outclk_lvds is
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
R : in std_ulogic;
S : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
C : in std_ulogic;
Q : out std_ulogic
);
end component;
component OBUFDS
generic (
IOSTANDARD : string := "LVDS_25";
CAPACITANCE : string := "DONT_CARE";
DRIVE : integer := 12
);
port (
I : in std_ulogic;
O : out std_ulogic;
OB : out std_ulogic
);
end component;
signal clk_s : std_ulogic;
begin
-- oddr is used to drive output (this reduces skew to IOB->PAD)
i_ddr : ODDR
generic map (
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC"
)
port map (
R => '0',
S => '0',
CE => '1',
D1 => '1',
D2 => '0',
C => ref_clk,
Q => clk_s
);
i_obuf : OBUFDS
generic map (
IOSTANDARD => "LVDS_25"
)
port map (
I => clk_s,
O => clk_out_p,
OB => clk_out_n
);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 08ced180db809f68b94c4291d7ad2a00 | 0.565374 | 4.339603 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/WriteBack.vhd | 1 | 526 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity WriteBack is
PORT ( Clk, rst : in std_logic;
DataIn1, DataIn2, DataIn3 : in std_logic_vector(15 downto 0);
ControlIn : in std_logic_vector (1 downto 0);
DataOut : out std_logic_vector (15 downto 0)
);
END WriteBack;
architecture arch_WriteBack of WriteBack is
begin
DataOut <= DataIn1 when ControlIn = "00" else
DataIn2 when ControlIn = "01" else
DataIn3 when ControlIn = "10" else
(others => '0');
end architecture arch_WriteBack; | mit | 4aa4b324fa8b279fb62f5066fc7f0ced | 0.71673 | 3.094118 | false | false | false | false |
spiersad/ECGR4146-FIFO | FIFO.vhd | 1 | 1,671 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO is
generic (N: integer := 8; -- number of address bits for 2**N address locations
M: integer := 64); -- number of data bits to/from FIFO
port (CLK, PUSH, POP, INIT: in std_logic;
DIN: in std_logic_vector(M-1 downto 0);
DOUT: out std_logic_vector(M-1 downto 0);
FULL, EMPTY, NOPUSH, NOPOP: out std_logic);
end entity FIFO;
architecture TOP_HIER of FIFO is
signal WE: std_logic;
signal A: std_logic_vector(N-1 downto 0);
component FIFO_LOGIC is
generic (N: integer); -- number of address bits
port (CLK, PUSH, POP, INIT: in std_logic;
ADD: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: buffer std_logic);
end component FIFO_LOGIC;
component RAM is
generic (K, W: integer); -- number of address and data bits
port (WR: in std_logic; -- active high write enable
ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
DIN: in std_logic_vector (K-1 downto 0); -- write data
DOUT: out std_logic_vector (K-1 downto 0)); -- read data
end component RAM;
begin
-- example of component instantiation using positional notation
FL: FIFO_LOGIC generic map (N => N)
port map (CLK => CLK, PUSH => PUSH, POP => POP, INIT => INIT,
ADD => A, FULL => FULL, EMPTY => EMPTY, WE =>WE,
NOPUSH => NOPUSH, NOPOP => NOPOP);
-- example of component instantiation using keyword notation
R: RAM generic map (W => N, K => M)
port map (DIN => DIN, ADDR => A, WR => WE, DOUT => DOUT);
end architecture TOP_HIER; | gpl-2.0 | 429733a59ca80557748746cadba346f6 | 0.623579 | 3.570513 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/util_spi_3w_v1_00_a/hdl/vhdl/util_spi_3w.vhd | 1 | 5,638 | -- ***************************************************************************
-- ***************************************************************************
-- Copyright 2011(c) Analog Devices, Inc.
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
-- this module converts 3 wire spi (physical) to 4 wire spi (internal)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.all;
entity util_spi_3w is
port (
m_clk : in std_logic; -- master clock
x_csn : in std_logic_vector(1 downto 0); -- 4 wire csn
x_clk : in std_logic; -- 4 wire clock
x_mosi : in std_logic; -- 4 wire mosi
x_miso : out std_logic; -- 4 wire miso
spi_cs0n : out std_logic; -- 3 wire csn (split)
spi_cs1n : out std_logic;
spi_clk : out std_logic; -- 3 wire clock
spi_sdio_T : out std_logic; -- 3 wire sdio (bi-dir)
spi_sdio_O : out std_logic;
spi_sdio_I : in std_logic;
debug_trigger : out std_logic_vector(7 downto 0);
debug_data : out std_logic_vector(63 downto 0)
);
end util_spi_3w;
architecture IMP of util_spi_3w is
signal x_clk_d : std_logic := '0';
signal x_csn_d : std_logic := '0';
signal m_enable : std_logic := '0';
signal m_rdwr : std_logic := '0';
signal m_bitcnt : std_logic_vector(5 downto 0) := (others => '0');
signal m_clkcnt : std_logic_vector(5 downto 0) := (others => '0');
signal x_csn_s : std_logic;
begin
-- pass most of the 4 wire stuff as it is (we only need the tristate controls)
x_csn_s <= not(x_csn(0) and x_csn(1));
x_miso <= spi_sdio_I;
spi_cs0n <= x_csn(0);
spi_cs1n <= x_csn(1);
spi_clk <= x_clk;
spi_sdio_T <= x_csn_s and m_enable;
spi_sdio_O <= x_mosi;
-- debug ports
debug_trigger <= "0000000" & x_csn_s;
debug_data(63 downto 23) <= (others => '0');
debug_data(22) <= m_rdwr;
debug_data(21) <= x_csn(1);
debug_data(20) <= x_csn(0);
debug_data(19) <= x_clk;
debug_data(18) <= x_mosi;
debug_data(17) <= x_clk_d;
debug_data(16) <= x_csn_d;
debug_data(15) <= x_csn_s;
debug_data(14) <= x_csn_s and m_enable;
debug_data(13) <= spi_sdio_I;
debug_data(12) <= m_enable;
debug_data(11 downto 6) <= m_bitcnt;
debug_data( 5 downto 0) <= m_clkcnt;
-- adc uses 16bit address phase, so count and change direction if read
p_cnts: process(m_clk) begin
if (m_clk'event and m_clk = '1') then
x_clk_d <= x_clk;
x_csn_d <= x_csn_s;
if ((m_bitcnt = 16) and (m_clkcnt = 10)) then
m_enable <= m_rdwr;
elsif ((x_csn_s = '0') and (x_csn_d = '1')) then
m_enable <= '0';
end if;
if ((x_csn_s = '1') and (x_csn_d = '0')) then
m_rdwr <= '0';
m_bitcnt <= (others => '0');
elsif ((x_clk = '1') and (x_clk_d = '0')) then
if (m_bitcnt = 0) then
m_rdwr <= x_mosi;
end if;
m_bitcnt <= m_bitcnt + 1;
end if;
if ((x_clk = '1') and (x_clk_d = '0')) then
m_clkcnt <= (others => '0');
else
m_clkcnt <= m_clkcnt + 1;
end if;
end if;
end process;
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 2a0dbe2b945a36a9ec0787bcd9abf191 | 0.548599 | 3.680157 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_004_test_input.fixed.vhd | 1 | 337 |
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
-- Violation below
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
end architecture RTL;
| gpl-3.0 | b2da25c6efa7fc227a456e7eadf928dd | 0.48368 | 3.179245 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_007_test_input.vhd | 1 | 818 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- case statement override
if a = '1' then
case x is
end case;
elsif c = '1' then
end if;
-- loop statement override
if a = '1' then
loop
end loop;
elsif c = '1' then
end if;
end process;
end architecture RTL;
| gpl-3.0 | 7a1d8188a81cc631e5e6471b02c65e77 | 0.403423 | 3.394191 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rdmux.vhd | 1 | 69,827 | -------------------------------------------------------------------------------
-- axi_datamover_rdmux.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rdmux.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Multiplexer.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_rdmux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_rdmux is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the select control bus
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 Data Channel
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32
-- Indicates the width of the AXI Stream Data Channel
);
port (
-- AXI MMap Data Channel Input -----------------------------------------------
--
mmap_read_data_in : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
-------------------------------------------------------------------------------
-- AXI Master Stream ---------------------------------------------------------
--
mux_data_out : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
--Mux data output --
-------------------------------------------------------------------------------
-- Command Calculator Interface -----------------------------------------------
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is less than the MMap Data --
-- Width). --
-------------------------------------------------------------------------------
);
end entity axi_datamover_rdmux;
architecture implementation of axi_datamover_rdmux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Decalarations -------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_mux_sel_width
--
-- Function Description:
-- Calculates the number of needed bits for the Mux Select control
-- based on the number of input channels to the mux.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_mux_sel_width (num_channels : integer) return integer is
Variable var_sel_width : integer := 0;
begin
case num_channels is
when 2 =>
var_sel_width := 1;
when 4 =>
var_sel_width := 2;
when 8 =>
var_sel_width := 3;
when 16 =>
var_sel_width := 4;
when 32 =>
var_sel_width := 5;
when 64 =>
var_sel_width := 6;
when 128 =>
var_sel_width := 7;
when others =>
var_sel_width := 0;
end case;
Return (var_sel_width);
end function func_mux_sel_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_sel_ls_index
--
-- Function Description:
-- Calculates the LS index of the select field to rip from the
-- input select bus.
--
-- Note that the number of input mux channels are always a
-- power of 2.
--
-------------------------------------------------------------------
function func_sel_ls_index (channel_width : integer) return integer is
Variable var_sel_ls_index : integer := 0;
begin
case channel_width is
when 8 =>
var_sel_ls_index := 0;
when 16 =>
var_sel_ls_index := 1;
when 32 =>
var_sel_ls_index := 2;
when 64 =>
var_sel_ls_index := 3;
when 128 =>
var_sel_ls_index := 4;
when 256 =>
var_sel_ls_index := 5;
when 512 =>
var_sel_ls_index := 6;
when others => -- 1024-bit channel case
var_sel_ls_index := 7;
end case;
Return (var_sel_ls_index);
end function func_sel_ls_index;
-- Constant Decalarations -------------------------------------------------
Constant CHANNEL_DWIDTH : integer := C_STREAM_DWIDTH;
Constant NUM_MUX_CHANNELS : integer := C_MMAP_DWIDTH/CHANNEL_DWIDTH;
Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS);
Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(CHANNEL_DWIDTH);
-- Signal Declarations --------------------------------------------
signal sig_rdmux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the Output data port
mux_data_out <= sig_rdmux_dout;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STRM_EQ_MMAP
--
-- If Generate Description:
-- This IfGen implements the case where the Stream Data Width is
-- the same as the Memory Map read Data width.
--
--
------------------------------------------------------------
GEN_STRM_EQ_MMAP : if (NUM_MUX_CHANNELS = 1) generate
begin
sig_rdmux_dout <= mmap_read_data_in;
end generate GEN_STRM_EQ_MMAP;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2XN
--
-- If Generate Description:
-- 2 channel input mux case
--
--
------------------------------------------------------------
GEN_2XN : if (NUM_MUX_CHANNELS = 2) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_2XN_NUX
--
-- Process Description:
-- Implement the 2XN Mux
--
-------------------------------------------------------------
DO_2XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when others => -- 1 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
end case;
end process DO_2XN_NUX;
end generate GEN_2XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4XN
--
-- If Generate Description:
-- 4 channel input mux case
--
--
------------------------------------------------------------
GEN_4XN : if (NUM_MUX_CHANNELS = 4) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_4XN_NUX
--
-- Process Description:
-- Implement the 4XN Mux
--
-------------------------------------------------------------
DO_4XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when others => -- 3 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
end case;
end process DO_4XN_NUX;
end generate GEN_4XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8XN
--
-- If Generate Description:
-- 8 channel input mux case
--
--
------------------------------------------------------------
GEN_8XN : if (NUM_MUX_CHANNELS = 8) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_8XN_NUX
--
-- Process Description:
-- Implement the 8XN Mux
--
-------------------------------------------------------------
DO_8XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when others => -- 7 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
end case;
end process DO_8XN_NUX;
end generate GEN_8XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16XN
--
-- If Generate Description:
-- 16 channel input mux case
--
--
------------------------------------------------------------
GEN_16XN : if (NUM_MUX_CHANNELS = 16) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_16XN_NUX
--
-- Process Description:
-- Implement the 16XN Mux
--
-------------------------------------------------------------
DO_16XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when others => -- 15 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
end case;
end process DO_16XN_NUX;
end generate GEN_16XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32XN
--
-- If Generate Description:
-- 32 channel input mux case
--
--
------------------------------------------------------------
GEN_32XN : if (NUM_MUX_CHANNELS = 32) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_32XN_NUX
--
-- Process Description:
-- Implement the 32XN Mux
--
-------------------------------------------------------------
DO_32XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0);
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1);
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2);
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3);
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4);
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5);
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6);
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7);
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8);
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9);
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when others => -- 31 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
end case;
end process DO_32XN_NUX;
end generate GEN_32XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64XN
--
-- If Generate Description:
-- 64 channel input mux case
--
--
------------------------------------------------------------
GEN_64XN : if (NUM_MUX_CHANNELS = 64) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_64XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_64XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when others => -- 63 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
end case;
end process DO_64XN_NUX;
end generate GEN_64XN;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128XN
--
-- If Generate Description:
-- 128 channel input mux case
--
--
------------------------------------------------------------
GEN_128XN : if (NUM_MUX_CHANNELS = 128) generate
-- local signals
signal sig_mux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0');
signal sig_mux_sel_int : integer := 0;
signal sig_mux_sel_int_local : integer := 0;
signal sig_mux_dout : std_logic_vector(CHANNEL_DWIDTH-1 downto 0) := (others => '0');
begin
-- Rip the Mux Select bits needed for the Mux case from the input select bus
sig_mux_sel_slice <= mstr2data_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX);
sig_mux_sel_unsgnd <= UNSIGNED(sig_mux_sel_slice); -- convert to unsigned
sig_mux_sel_int <= TO_INTEGER(sig_mux_sel_unsgnd); -- convert to integer for MTI compile issue
-- with locally static subtype error in each of the
-- Mux IfGens
sig_mux_sel_int_local <= sig_mux_sel_int;
sig_rdmux_dout <= sig_mux_dout;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_128XN_NUX
--
-- Process Description:
-- Implement the 64XN Mux
--
-------------------------------------------------------------
DO_128XN_NUX : process (sig_mux_sel_int_local,
mmap_read_data_in)
begin
case sig_mux_sel_int_local is
when 0 =>
sig_mux_dout <= mmap_read_data_in(CHANNEL_DWIDTH-1 downto 0) ;
when 1 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*2)-1 downto CHANNEL_DWIDTH*1) ;
when 2 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*3)-1 downto CHANNEL_DWIDTH*2) ;
when 3 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*4)-1 downto CHANNEL_DWIDTH*3) ;
when 4 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*5)-1 downto CHANNEL_DWIDTH*4) ;
when 5 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*6)-1 downto CHANNEL_DWIDTH*5) ;
when 6 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*7)-1 downto CHANNEL_DWIDTH*6) ;
when 7 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*8)-1 downto CHANNEL_DWIDTH*7) ;
when 8 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*9)-1 downto CHANNEL_DWIDTH*8) ;
when 9 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*10)-1 downto CHANNEL_DWIDTH*9) ;
when 10 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*11)-1 downto CHANNEL_DWIDTH*10);
when 11 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*12)-1 downto CHANNEL_DWIDTH*11);
when 12 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*13)-1 downto CHANNEL_DWIDTH*12);
when 13 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*14)-1 downto CHANNEL_DWIDTH*13);
when 14 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*15)-1 downto CHANNEL_DWIDTH*14);
when 15 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*16)-1 downto CHANNEL_DWIDTH*15);
when 16 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*17)-1 downto CHANNEL_DWIDTH*16);
when 17 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*18)-1 downto CHANNEL_DWIDTH*17);
when 18 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*19)-1 downto CHANNEL_DWIDTH*18);
when 19 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*20)-1 downto CHANNEL_DWIDTH*19);
when 20 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*21)-1 downto CHANNEL_DWIDTH*20);
when 21 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*22)-1 downto CHANNEL_DWIDTH*21);
when 22 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*23)-1 downto CHANNEL_DWIDTH*22);
when 23 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*24)-1 downto CHANNEL_DWIDTH*23);
when 24 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*25)-1 downto CHANNEL_DWIDTH*24);
when 25 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*26)-1 downto CHANNEL_DWIDTH*25);
when 26 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*27)-1 downto CHANNEL_DWIDTH*26);
when 27 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*28)-1 downto CHANNEL_DWIDTH*27);
when 28 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*29)-1 downto CHANNEL_DWIDTH*28);
when 29 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*30)-1 downto CHANNEL_DWIDTH*29);
when 30 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*31)-1 downto CHANNEL_DWIDTH*30);
when 31 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*32)-1 downto CHANNEL_DWIDTH*31);
when 32 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*33)-1 downto CHANNEL_DWIDTH*32);
when 33 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*34)-1 downto CHANNEL_DWIDTH*33);
when 34 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*35)-1 downto CHANNEL_DWIDTH*34);
when 35 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*36)-1 downto CHANNEL_DWIDTH*35);
when 36 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*37)-1 downto CHANNEL_DWIDTH*36);
when 37 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*38)-1 downto CHANNEL_DWIDTH*37);
when 38 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*39)-1 downto CHANNEL_DWIDTH*38);
when 39 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*40)-1 downto CHANNEL_DWIDTH*39);
when 40 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*41)-1 downto CHANNEL_DWIDTH*40);
when 41 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*42)-1 downto CHANNEL_DWIDTH*41);
when 42 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*43)-1 downto CHANNEL_DWIDTH*42);
when 43 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*44)-1 downto CHANNEL_DWIDTH*43);
when 44 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*45)-1 downto CHANNEL_DWIDTH*44);
when 45 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*46)-1 downto CHANNEL_DWIDTH*45);
when 46 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*47)-1 downto CHANNEL_DWIDTH*46);
when 47 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*48)-1 downto CHANNEL_DWIDTH*47);
when 48 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*49)-1 downto CHANNEL_DWIDTH*48);
when 49 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*50)-1 downto CHANNEL_DWIDTH*49);
when 50 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*51)-1 downto CHANNEL_DWIDTH*50);
when 51 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*52)-1 downto CHANNEL_DWIDTH*51);
when 52 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*53)-1 downto CHANNEL_DWIDTH*52);
when 53 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*54)-1 downto CHANNEL_DWIDTH*53);
when 54 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*55)-1 downto CHANNEL_DWIDTH*54);
when 55 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*56)-1 downto CHANNEL_DWIDTH*55);
when 56 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*57)-1 downto CHANNEL_DWIDTH*56);
when 57 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*58)-1 downto CHANNEL_DWIDTH*57);
when 58 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*59)-1 downto CHANNEL_DWIDTH*58);
when 59 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*60)-1 downto CHANNEL_DWIDTH*59);
when 60 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*61)-1 downto CHANNEL_DWIDTH*60);
when 61 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*62)-1 downto CHANNEL_DWIDTH*61);
when 62 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*63)-1 downto CHANNEL_DWIDTH*62);
when 63 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*64)-1 downto CHANNEL_DWIDTH*63);
when 64 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*65)-1 downto CHANNEL_DWIDTH*64) ;
when 65 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*66)-1 downto CHANNEL_DWIDTH*65) ;
when 66 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*67)-1 downto CHANNEL_DWIDTH*66) ;
when 67 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*68)-1 downto CHANNEL_DWIDTH*67) ;
when 68 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*69)-1 downto CHANNEL_DWIDTH*68) ;
when 69 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*70)-1 downto CHANNEL_DWIDTH*69) ;
when 70 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*71)-1 downto CHANNEL_DWIDTH*70) ;
when 71 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*72)-1 downto CHANNEL_DWIDTH*71) ;
when 72 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*73)-1 downto CHANNEL_DWIDTH*72) ;
when 73 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*74)-1 downto CHANNEL_DWIDTH*73) ;
when 74 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*75)-1 downto CHANNEL_DWIDTH*74) ;
when 75 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*76)-1 downto CHANNEL_DWIDTH*75) ;
when 76 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*77)-1 downto CHANNEL_DWIDTH*76) ;
when 77 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*78)-1 downto CHANNEL_DWIDTH*77) ;
when 78 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*79)-1 downto CHANNEL_DWIDTH*78) ;
when 79 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*80)-1 downto CHANNEL_DWIDTH*79) ;
when 80 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*81)-1 downto CHANNEL_DWIDTH*80) ;
when 81 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*82)-1 downto CHANNEL_DWIDTH*81) ;
when 82 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*83)-1 downto CHANNEL_DWIDTH*82) ;
when 83 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*84)-1 downto CHANNEL_DWIDTH*83) ;
when 84 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*85)-1 downto CHANNEL_DWIDTH*84) ;
when 85 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*86)-1 downto CHANNEL_DWIDTH*85) ;
when 86 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*87)-1 downto CHANNEL_DWIDTH*86) ;
when 87 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*88)-1 downto CHANNEL_DWIDTH*87) ;
when 88 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*89)-1 downto CHANNEL_DWIDTH*88) ;
when 89 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*90)-1 downto CHANNEL_DWIDTH*89) ;
when 90 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*91)-1 downto CHANNEL_DWIDTH*90) ;
when 91 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*92)-1 downto CHANNEL_DWIDTH*91) ;
when 92 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*93)-1 downto CHANNEL_DWIDTH*92) ;
when 93 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*94)-1 downto CHANNEL_DWIDTH*93) ;
when 94 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*95)-1 downto CHANNEL_DWIDTH*94) ;
when 95 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*96)-1 downto CHANNEL_DWIDTH*95) ;
when 96 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*97 )-1 downto CHANNEL_DWIDTH*96 ) ;
when 97 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*98 )-1 downto CHANNEL_DWIDTH*97 ) ;
when 98 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*99 )-1 downto CHANNEL_DWIDTH*98 ) ;
when 99 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*100)-1 downto CHANNEL_DWIDTH*99 ) ;
when 100 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*101)-1 downto CHANNEL_DWIDTH*100) ;
when 101 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*102)-1 downto CHANNEL_DWIDTH*101) ;
when 102 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*103)-1 downto CHANNEL_DWIDTH*102) ;
when 103 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*104)-1 downto CHANNEL_DWIDTH*103) ;
when 104 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*105)-1 downto CHANNEL_DWIDTH*104) ;
when 105 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*106)-1 downto CHANNEL_DWIDTH*105) ;
when 106 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*107)-1 downto CHANNEL_DWIDTH*106) ;
when 107 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*108)-1 downto CHANNEL_DWIDTH*107) ;
when 108 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*109)-1 downto CHANNEL_DWIDTH*108) ;
when 109 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*110)-1 downto CHANNEL_DWIDTH*109) ;
when 110 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*111)-1 downto CHANNEL_DWIDTH*110) ;
when 111 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*112)-1 downto CHANNEL_DWIDTH*111) ;
when 112 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*113)-1 downto CHANNEL_DWIDTH*112) ;
when 113 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*114)-1 downto CHANNEL_DWIDTH*113) ;
when 114 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*115)-1 downto CHANNEL_DWIDTH*114) ;
when 115 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*116)-1 downto CHANNEL_DWIDTH*115) ;
when 116 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*117)-1 downto CHANNEL_DWIDTH*116) ;
when 117 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*118)-1 downto CHANNEL_DWIDTH*117) ;
when 118 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*119)-1 downto CHANNEL_DWIDTH*118) ;
when 119 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*120)-1 downto CHANNEL_DWIDTH*119) ;
when 120 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*121)-1 downto CHANNEL_DWIDTH*120) ;
when 121 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*122)-1 downto CHANNEL_DWIDTH*121) ;
when 122 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*123)-1 downto CHANNEL_DWIDTH*122) ;
when 123 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*124)-1 downto CHANNEL_DWIDTH*123) ;
when 124 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*125)-1 downto CHANNEL_DWIDTH*124) ;
when 125 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*126)-1 downto CHANNEL_DWIDTH*125) ;
when 126 =>
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*127)-1 downto CHANNEL_DWIDTH*126) ;
when others => -- 127 case
sig_mux_dout <= mmap_read_data_in((CHANNEL_DWIDTH*128)-1 downto CHANNEL_DWIDTH*127) ;
end case;
end process DO_128XN_NUX;
end generate GEN_128XN;
end implementation;
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kT2TVSMI0kzznv/ipDb3qSfrNe3Ti7VegIFfE18esL7A8BuS6a1smkYBNenYXzYHXKSAU3gYxyXx
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K++gekzy3mfAwDgx4nP3/bSHnYVzZMP9uGpWgzNjJV0SEmSYOord7+DwFQiUPM/curLd0O4D4khB
jVyMWq8lHJgyW04UPECunjWbxxx+qkzuPDaYT/5UJQEiiEx+r5sS8on5FsoGimtQV7jt6g2zGcs2
DzagAFAn76pnlSnXBguRXtwx0I5NN1tRHSoZBSMsNgS+Nfw6xRhkWXGPWI53sTmzkgcU8sKLm+js
GXS1DpAkeIA66gZpazHpsqB7pRgAOReKaLvyfuv3Sn/dk0irJAOh2nmAjVFxwpm/iHH9qISm
`protect end_protected
| bsd-2-clause | b13e4c4eeb80cacc6b6110e6b06fe401 | 0.955716 | 1.80636 | false | false | false | false |
rjarzmik/mips_processor | Caches/memory_cacheline_internal.vhd | 1 | 2,582 | -------------------------------------------------------------------------------
-- Title : Tags memory with arrays implementation
-- Project : MIPS processor implementation, compatible MIPS-1
-------------------------------------------------------------------------------
-- File : memory_cacheline_internal.vhd
-- Author : Robert Jarzmik (Intel) <[email protected]>
-- Company :
-- Created : 2016-12-15
-- Last update: 2016-12-28
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-15 1.0 rjarzmik Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cache_defs.cache_line_t;
use work.cache_defs.cache_line_selector_t;
use work.cache_defs.data_t;
-------------------------------------------------------------------------------
entity memory_cacheline_internal is
generic
(
ADDR_WIDTH : integer := 7;
DEBUG_IDX : natural := 0;
DEBUG : boolean := false
);
port
(
clock : in std_logic := '1';
raddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
waddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
data : in data_t;
rren : in std_logic;
wren : in std_logic;
q : out data_t
);
end entity memory_cacheline_internal;
architecture infer of memory_cacheline_internal is
type mem_block_t is array(0 to 2**ADDR_WIDTH - 1) of data_t;
signal memory : mem_block_t := (others => (others => '0'));
signal raddr_reg : std_logic_vector (ADDR_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture str
process(clock, memory, raddr_reg)
begin
if rising_edge(clock) then
if rren = '1' then
raddr_reg <= raddr;
end if;
if wren = '1' then
memory(to_integer(unsigned(waddr))) <= data;
-- pragma translate_off
if DEBUG then
report "Cmem(" & integer'image(DEBUG_IDX) & "): [" &
to_hstring(waddr) & "] <= " & to_hstring(data);
end if;
-- pragma translate_on
end if;
end if;
q <= memory(to_integer(unsigned(raddr_reg)));
end process;
end architecture infer;
| gpl-3.0 | 2c7ba9cdffa4b150c3f840b89d718161 | 0.466692 | 4.164516 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable_assignment/rule_001_test_input.vhd | 1 | 913 |
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
-- Violations below
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
SIMPLE_LABEL : x := z;
a := b;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
| gpl-3.0 | 15153ebda4cbca57fd1aae2a8cf1d93a | 0.599124 | 3.344322 | false | false | false | false |
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