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tgingold/ghdl | testsuite/gna/bug078/half_adder.vhdl | 1 | 2,799 | -- IEEE Std 1076-1993 5.2.1 Ginding Indication (example)
package global_signals is -- THIS PACKAGE MISSING IN THE EXAMPLE
signal Tied_High: bit := '1';
end package;
entity AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end entity AND_GATE;
architecture Behavior of AND_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 and In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
entity XOR_GATE is
generic (I1toO, I2toO : DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end entity XOR_GATE;
architecture Behavior of XOR_GATE is -- ADDED
signal In1, In2: BIT;
begin
In1 <= I1 after I1toO;
In2 <= I2 after I2toO;
O <= In1 xor In2;
process
begin
report
LF & HT & "I1to0 = " & time'image(I1toO) &
LF & HT & "I2to0 = " & time'image(I2toO);
wait;
end process;
end architecture Behavior;
package MY_GATES is
component AND_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O: out BIT);
end component AND_GATE;
component XOR_GATE is
generic (I1toO, I2toO: DELAY_LENGTH := 4 ns);
port (I1, I2: in BIT; O : out BIT);
end component XOR_GATE;
end package MY_GATES;
entity Half_Adder is
port (X, Y: in BIT;
Sum, Carry: out BIT);
end entity Half_Adder;
use WORK.MY_GATES.all;
architecture Structure of Half_Adder is
signal O: bit; -- Added
for L1: XOR_GATE use
entity WORK.XOR_GATE(Behavior) -- The primary binding indication
generic map (3 ns, 3 ns) -- for instance L1.
port map (I1 => I1, I2 => I2, O => O);
for L2: AND_GATE use
entity WORK.AND_GATE(Behavior) -- The primary binding indication
-- generic map (3 ns, 4 ns) -- for instance L2.
port map (I1, open, O);
begin
L1: XOR_GATE port map (X, Y, Sum);
L2: AND_GATE port map (X, Y, Carry);
end architecture Structure;
use WORK.GLOBAL_SIGNALS.all;
configuration Different of Half_Adder is
for Structure
for L1: XOR_GATE
generic map (2.9 ns, 3.6 ns); -- The incremental binding
end for; -- indication of L1; rebinds its generics.
for L2: AND_GATE
-- generic map (2.8 ns, 3.25 ns) -- The incremental binding
port map (I2 => Tied_High); -- indication L2; rebinds its generics
end for; -- and binds its open port.
end for;
end configuration Different;
| gpl-2.0 | 8fe642e14bc88dad7a1c7a8d0caaa3be | 0.580564 | 3.224654 | false | false | false | false |
tgingold/ghdl | libraries/ieee2008/std_logic_1164.vhdl | 2 | 14,971 | -- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1228 $
-- $Date: 2008-04-30 10:04:53 +0930 (Wed, 30 Apr 2008) $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package std_logic_1164 is
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-- and for use in declaring signal arrays of unresolved elements
-------------------------------------------------------------------
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- logic state system (resolved)
-------------------------------------------------------------------
subtype STD_LOGIC is resolved STD_ULOGIC;
-------------------------------------------------------------------
-- unconstrained array of resolved std_ulogic for use in declaring
-- signal arrays of resolved elements
-------------------------------------------------------------------
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "not" (l : STD_ULOGIC) return UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
function To_StdULogic (b : BIT) return STD_ULOGIC;
function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
alias To_Bit_Vector is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_BV is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (s : STD_ULOGIC) return X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (b : BIT) return X01;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (s : STD_ULOGIC) return X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (b : BIT) return X01Z;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (s : STD_ULOGIC) return UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (b : BIT) return UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
function Is_X (s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- matching relational operators
-------------------------------------------------------------------
-- the following operations are predefined
-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
-- the following operations are predefined
-- function TO_STRING (value : STD_ULOGIC) return STRING;
-- function TO_STRING (value : STD_ULOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
end package std_logic_1164;
| gpl-2.0 | a3e04d107038ac885ec2a93cf55628fe | 0.551199 | 4.23388 | false | false | false | false |
nickg/nvc | test/regress/wait22.vhd | 1 | 1,294 | -- Test case from Brian Padalino
--
entity wait22 is end entity ;
architecture arch of wait22 is
procedure generate_clock(signal ena : in boolean ; signal clock : inout bit) is
begin
-- Inspired by UVVM clock_generator procedure
loop
if not ena then
if now /= 0 ps then
report "Stopping clock" ;
end if ;
clock <= '0' ;
wait until ena ;
end if ;
clock <= '1' ;
wait for 5 ns ;
clock <= '0' ;
wait for 5 ns ;
end loop ;
end procedure ;
signal clock_enable : boolean := false ;
signal clock : bit := '0' ;
signal reset : bit := '1' ;
begin
gen_clock_p: generate_clock(clock_enable, clock) ;
tick_p: process(clock, reset)
begin
if reset = '1' then
else
if clock'event and clock = '1' then
report "Clock tick" ;
end if ;
end if ;
end process ;
tb : process
begin
report "About to begin" ;
wait for 10 ns ;
reset <= '0' ;
wait for 10 ns ;
clock_enable <= true ;
wait for 100 ns ;
std.env.stop;
end process ;
end architecture ;
| gpl-3.0 | 1b1f1a4f80f04c29495fa075bacecdfc | 0.486862 | 4.228758 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/sub_157.vhd | 2 | 1,735 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_157 is
port (
ge : out std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
sign : in std_logic
);
end sub_157;
architecture augh of sub_157 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
ge <= tmp_ge;
end architecture;
| gpl-2.0 | 6f04a76a8be96553003d5cdbd92fe0e8 | 0.626513 | 2.597305 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/sim/vhdl/doHist.vhd | 1 | 18,242 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2016.1
-- Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity doHist is
generic (
C_S_AXI_CTRL_BUS_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CTRL_BUS_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
inStream_TDATA : IN STD_LOGIC_VECTOR (7 downto 0);
inStream_TVALID : IN STD_LOGIC;
inStream_TREADY : OUT STD_LOGIC;
inStream_TKEEP : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TSTRB : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TUSER : IN STD_LOGIC_VECTOR (1 downto 0);
inStream_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
inStream_TID : IN STD_LOGIC_VECTOR (4 downto 0);
inStream_TDEST : IN STD_LOGIC_VECTOR (5 downto 0);
histo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
histo_EN_A : OUT STD_LOGIC;
histo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
histo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
histo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
histo_Clk_A : OUT STD_LOGIC;
histo_Rst_A : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_AWREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CTRL_BUS_WVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_WREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CTRL_BUS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH/8-1 downto 0);
s_axi_CTRL_BUS_ARVALID : IN STD_LOGIC;
s_axi_CTRL_BUS_ARREADY : OUT STD_LOGIC;
s_axi_CTRL_BUS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_ADDR_WIDTH-1 downto 0);
s_axi_CTRL_BUS_RVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_RREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CTRL_BUS_DATA_WIDTH-1 downto 0);
s_axi_CTRL_BUS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_CTRL_BUS_BVALID : OUT STD_LOGIC;
s_axi_CTRL_BUS_BREADY : IN STD_LOGIC;
s_axi_CTRL_BUS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of doHist is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"doHist,hls_ip_2016_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.860000,HLS_SYN_LAT=153858,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=91,HLS_SYN_LUT=205}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (3 downto 0) := "0001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (3 downto 0) := "0010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (3 downto 0) := "1000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv17_0 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv9_100 : STD_LOGIC_VECTOR (8 downto 0) := "100000000";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv17_12C00 : STD_LOGIC_VECTOR (16 downto 0) := "10010110000000000";
constant ap_const_lv17_1 : STD_LOGIC_VECTOR (16 downto 0) := "00000000000000001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (3 downto 0) := "0001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_21 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal inStream_TDATA_blk_n : STD_LOGIC;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_53 : BOOLEAN;
signal exitcond_fu_148_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal idxHist_1_fu_137_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_102 : BOOLEAN;
signal idxPixel_1_fu_154_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal idxPixel_1_reg_187 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_108 : BOOLEAN;
signal histo_addr_1_reg_192 : STD_LOGIC_VECTOR (7 downto 0);
signal idxHist_reg_109 : STD_LOGIC_VECTOR (8 downto 0);
signal exitcond2_fu_131_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal idxPixel_reg_120 : STD_LOGIC_VECTOR (16 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_130 : BOOLEAN;
signal tmp_fu_143_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_3_fu_164_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal histo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_fu_169_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (3 downto 0);
component doHist_CTRL_BUS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
doHist_CTRL_BUS_s_axi_U : component doHist_CTRL_BUS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CTRL_BUS_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CTRL_BUS_DATA_WIDTH)
port map (
AWVALID => s_axi_CTRL_BUS_AWVALID,
AWREADY => s_axi_CTRL_BUS_AWREADY,
AWADDR => s_axi_CTRL_BUS_AWADDR,
WVALID => s_axi_CTRL_BUS_WVALID,
WREADY => s_axi_CTRL_BUS_WREADY,
WDATA => s_axi_CTRL_BUS_WDATA,
WSTRB => s_axi_CTRL_BUS_WSTRB,
ARVALID => s_axi_CTRL_BUS_ARVALID,
ARREADY => s_axi_CTRL_BUS_ARREADY,
ARADDR => s_axi_CTRL_BUS_ARADDR,
RVALID => s_axi_CTRL_BUS_RVALID,
RREADY => s_axi_CTRL_BUS_RREADY,
RDATA => s_axi_CTRL_BUS_RDATA,
RRESP => s_axi_CTRL_BUS_RRESP,
BVALID => s_axi_CTRL_BUS_BVALID,
BREADY => s_axi_CTRL_BUS_BREADY,
BRESP => s_axi_CTRL_BUS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
idxHist_reg_109_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_131_p2))) then
idxHist_reg_109 <= idxHist_1_fu_137_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
idxHist_reg_109 <= ap_const_lv9_0;
end if;
end if;
end process;
idxPixel_reg_120_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = exitcond2_fu_131_p2)))) then
idxPixel_reg_120 <= ap_const_lv17_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
idxPixel_reg_120 <= idxPixel_1_reg_187;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (exitcond_fu_148_p2 = ap_const_lv1_0) and not(ap_sig_108))) then
histo_addr_1_reg_192 <= tmp_3_fu_164_p1(8 - 1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108))) then
idxPixel_1_reg_187 <= idxPixel_1_fu_154_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond_fu_148_p2, ap_sig_108, exitcond2_fu_131_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((ap_const_lv1_0 = exitcond2_fu_131_p2)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
if ((not(ap_sig_108) and not((exitcond_fu_148_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
elsif (((exitcond_fu_148_p2 = ap_const_lv1_0) and not(ap_sig_108))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when others =>
ap_NS_fsm <= "XXXX";
end case;
end process;
ap_done_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2, ap_sig_108)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108) and not((exitcond_fu_148_p2 = ap_const_lv1_0)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2, ap_sig_108)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108) and not((exitcond_fu_148_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_102_assign_proc : process(ap_CS_fsm)
begin
ap_sig_102 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
ap_sig_108_assign_proc : process(inStream_TVALID, exitcond_fu_148_p2)
begin
ap_sig_108 <= ((exitcond_fu_148_p2 = ap_const_lv1_0) and (inStream_TVALID = ap_const_logic_0));
end process;
ap_sig_130_assign_proc : process(ap_CS_fsm)
begin
ap_sig_130 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
ap_sig_21_assign_proc : process(ap_CS_fsm)
begin
ap_sig_21 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
ap_sig_53_assign_proc : process(ap_CS_fsm)
begin
ap_sig_53 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_21)
begin
if (ap_sig_21) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_102)
begin
if (ap_sig_102) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_53)
begin
if (ap_sig_53) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_130)
begin
if (ap_sig_130) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
exitcond2_fu_131_p2 <= "1" when (idxHist_reg_109 = ap_const_lv9_100) else "0";
exitcond_fu_148_p2 <= "1" when (idxPixel_reg_120 = ap_const_lv17_12C00) else "0";
histo_Addr_A <= std_logic_vector(shift_left(unsigned(histo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
histo_Addr_A_orig_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st2_fsm_1, histo_addr_1_reg_192, ap_sig_cseq_ST_st4_fsm_3, tmp_fu_143_p1, tmp_3_fu_164_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
histo_Addr_A_orig <= std_logic_vector(resize(unsigned(histo_addr_1_reg_192),32));
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
histo_Addr_A_orig <= tmp_fu_143_p1(32 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
histo_Addr_A_orig <= tmp_3_fu_164_p1(32 - 1 downto 0);
else
histo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
histo_Clk_A <= ap_clk;
histo_Din_A_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st4_fsm_3, tmp_4_fu_169_p2)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
histo_Din_A <= tmp_4_fu_169_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
histo_Din_A <= ap_const_lv32_0;
else
histo_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
histo_EN_A_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_108, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and not(ap_sig_108)) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
histo_EN_A <= ap_const_logic_1;
else
histo_EN_A <= ap_const_logic_0;
end if;
end process;
histo_Rst_A_assign_proc : process(ap_rst_n)
begin
histo_Rst_A <= not(ap_rst_n);
end process;
histo_WEN_A_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, exitcond2_fu_131_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_131_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3))) then
histo_WEN_A <= ap_const_lv4_F;
else
histo_WEN_A <= ap_const_lv4_0;
end if;
end process;
idxHist_1_fu_137_p2 <= std_logic_vector(unsigned(idxHist_reg_109) + unsigned(ap_const_lv9_1));
idxPixel_1_fu_154_p2 <= std_logic_vector(unsigned(idxPixel_reg_120) + unsigned(ap_const_lv17_1));
inStream_TDATA_blk_n_assign_proc : process(inStream_TVALID, ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (exitcond_fu_148_p2 = ap_const_lv1_0))) then
inStream_TDATA_blk_n <= inStream_TVALID;
else
inStream_TDATA_blk_n <= ap_const_logic_1;
end if;
end process;
inStream_TREADY_assign_proc : process(ap_sig_cseq_ST_st3_fsm_2, exitcond_fu_148_p2, ap_sig_108)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (exitcond_fu_148_p2 = ap_const_lv1_0) and not(ap_sig_108)))) then
inStream_TREADY <= ap_const_logic_1;
else
inStream_TREADY <= ap_const_logic_0;
end if;
end process;
tmp_3_fu_164_p1 <= std_logic_vector(resize(unsigned(inStream_TDATA),64));
tmp_4_fu_169_p2 <= std_logic_vector(unsigned(histo_Dout_A) + unsigned(ap_const_lv32_1));
tmp_fu_143_p1 <= std_logic_vector(resize(unsigned(idxHist_reg_109),64));
end behav;
| gpl-3.0 | d67e42e405c9df3261550f92e815c20b | 0.584804 | 2.902928 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/lib_fifo_v1_0/hdl/src/vhdl/async_fifo_fg.vhd | 3 | 124,921 | -- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- - Update to use fifo_generator_v13_0_2 (New parameter C_EN_SAFETY_CKT is added with default value as 0 or disabled)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
USE IEEE.std_logic_misc.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.ALL;
library fifo_generator_v13_1_0;
use fifo_generator_v13_1_0.all;
--library lib_fifo_v1_0_4;
--use lib_fifo_v1_0_4.lib_fifo_pkg.all;
--use lib_fifo_v1_0_4.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_EN_SAFETY_CKT : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0 ;
C_SYNCHRONIZER_STAGE : integer := 2 -- valid values are 0 to 8
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-- Constant Declarations ----------------------------------------------
-- C_FAMILY is directly passed. No need to have family_support function
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- Proc_common supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true; --not(FAMILY_NOT_SUPPORTED);
Constant C_DEFAULT_VALUE : String := "BlankString"; -- new for FIFO Gen
Constant C_PRIM_FIFO_TYPE : String := "512x36"; -- new for FIFO Gen
Constant RST_VAL : String := "0"; -- new for FIFO Gen
-- Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
-- Changing this to true
Constant FAM_IS_NOT_S3_V4_V5 : boolean := true;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
Constant C_HAS_RST_INT : integer := 1;--if_then_else(C_EN_SAFETY_CKT = 1,0,1);
Constant C_HAS_SRST_INT : integer := 0;--if_then_else(C_EN_SAFETY_CKT = 1,1,0);
--Constant C_HAS_SRST_INT : integer := 0 when (C_EN_SAFETY_CKT = 1) else 1;
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising wr clock edge to issue assertion
-- Wait until Wr_clk = '1';
-- wait until Wr_clk = '0';
-- Wait until Wr_clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait; -- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Almost_full <= '0' ; -- : out std_logic;
-- Almost_empty <= '0' ; -- : out std_logic;
-- Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
-- Rd_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_0.fifo_generator_v13_1_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => RST_VAL,--"0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0',
backup_marker => '0',
clk => '0',
rst => Ainit,
srst => '0',
wr_clk => Wr_clk,
wr_rst => Ainit,
rd_clk => Rd_clk,
rd_rst => Ainit,
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => Full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => Almost_empty,
valid => Rd_ack,
underflow => Rd_err,
data_count => DATA_COUNT,
rd_data_count => sig_full_fifo_rdcnt,
wr_data_count => sig_full_fifo_wrcnt,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal DATA_COUNT : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : entity fifo_generator_v13_1_0.fifo_generator_v13_1_0
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,--"BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => C_HAS_RST_INT,
C_HAS_SRST => C_HAS_SRST_INT,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => C_DEFAULT_VALUE,
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,--"512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => C_EN_SAFETY_CKT,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
backup => '0', -- : IN std_logic := '0';
backup_marker => '0', -- : IN std_logic := '0';
clk => '0', -- : IN std_logic := '0';
rst => Ainit, -- : IN std_logic := '0';
srst => '0', -- : IN std_logic := '0';
wr_clk => Wr_clk, -- : IN std_logic := '0';
wr_rst => Ainit, -- : IN std_logic := '0';
rd_clk => Rd_clk, -- : IN std_logic := '0';
rd_rst => Ainit, -- : IN std_logic := '0';
din => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
wr_en => Wr_en, -- : IN std_logic := '0';
rd_en => Rd_en, -- : IN std_logic := '0';
prog_empty_thresh => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
int_clk => '0', -- : IN std_logic := '0';
injectdbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
injectsbiterr => '0', -- new FG 5.1 -- : IN std_logic := '0';
sleep => '0', -- : IN std_logic := '0';
dout => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
full => Full, -- : OUT std_logic;
almost_full => Almost_full, -- : OUT std_logic;
wr_ack => Wr_ack, -- : OUT std_logic;
overflow => Rd_err, -- : OUT std_logic;
empty => Empty, -- : OUT std_logic;
almost_empty => Almost_empty, -- : OUT std_logic;
valid => Rd_ack, -- : OUT std_logic;
underflow => Wr_err, -- : OUT std_logic;
data_count => DATA_COUNT, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
rd_data_count => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
wr_data_count => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
prog_full => PROG_FULL, -- : OUT std_logic;
prog_empty => PROG_EMPTY, -- : OUT std_logic;
sbiterr => SBITERR, -- : OUT std_logic;
dbiterr => DBITERR, -- : OUT std_logic
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
| gpl-3.0 | 9c692fc00bee9f51853dfb7fb14bcb07 | 0.402574 | 3.927098 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS4_RF_IC/v_BPF.vhd | 4 | 1,744 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.math_real.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity v_BPF is
generic ( k : real := 1.0; -- filter gain
fo : real := 100.0e3; -- center frequency [Hz]
q : real := 0.707 ); -- quality factor
port ( terminal input : electrical;
terminal output : electrical );
end entity v_BPF;
----------------------------------------------------------------
architecture behavioral of v_BPF is
quantity vin across input;
quantity vout across iout through output;
constant wo : real := math_2_pi * fo; -- frequency in radians
constant num : real_vector := (0.0, wo); -- numerator array
constant den : real_vector := (wo * wo, wo / q, 1.0); -- denominator array
begin
vout == k * vin'ltf(num, den); -- Laplace transform of output
end architecture behavioral;
| gpl-2.0 | 06f222809924dea18cb74ce16739f0cc | 0.635894 | 4.22276 | false | false | false | false |
nickg/nvc | test/jit/array1.vhd | 1 | 1,201 | package array1 is
type iv is array (natural range <>) of integer;
procedure assign (a : out iv; b : in iv);
function get_ints (n, start : integer) return iv;
function issue94 (dataw : integer; shiftw : integer) return bit_vector;
procedure test2 (value : string);
end package;
package body array1 is
procedure assign (a : out iv; b : in iv) is
begin
a := b;
end procedure;
function get_ints (n, start : integer) return iv is
variable v : iv(1 to n);
begin
for i in 1 to n loop
v(i) := start + i - 1;
end loop;
return v;
end function;
function issue94 (dataw : integer; shiftw : integer) return bit_vector is
constant max_shift : integer := shiftw;
type bit_vector_array is array (natural range <>) of bit_vector(dataw-1 downto 0);
variable y_temp : bit_vector_array (0 to max_shift);
begin
y_temp(0):=(others=>'1');
y_temp(1):=(others => '0');
return y_temp(0);
end function;
procedure test2 (value : string) is
variable x : string(1 to value'length) := value;
begin
report x;
end procedure;
end package body;
| gpl-3.0 | ce1056a3e5b58782f2db8f5f1c2dcb27 | 0.592007 | 3.729814 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_mngr.vhd | 7 | 19,061 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_mngr.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
s2mm_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_cmnd_wr : std_logic := '0';
signal updt_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH
+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal updt_done : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal updt_interr : std_logic := '0';
signal updt_slverr : std_logic := '0';
signal updt_decerr : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_UPDT_SG : entity axi_sg_v4_1_2.axi_sg_updt_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ftch_error => ftch_error ,
-- Channel 1 Control and Status
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set ,
ch1_dma_slverr_set => ch1_dma_slverr_set ,
ch1_dma_decerr_set => ch1_dma_decerr_set ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set ,
ch2_dma_slverr_set => ch2_dma_slverr_set ,
ch2_dma_decerr_set => ch2_dma_decerr_set ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- DataMover Command
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- DataMover Status
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_UPDT_CMDSTS_IF : entity axi_sg_v4_1_2.axi_sg_updt_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
-- Scatter Gather Fetch Status
s2mm_err => s2mm_err ,
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr
);
end implementation;
| gpl-3.0 | 28b6f40e1dd4d2f3a1983ca723f05292 | 0.362468 | 5.095162 | false | false | false | false |
tgingold/ghdl | testsuite/synth/block01/tb_block02.vhdl | 1 | 730 | entity tb_block02 is
end tb_block02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_block02 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.block02
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 | 1842e2319f2757594de61c9b4c0d641a | 0.572603 | 3.42723 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/tb_bit_to_analog.vhd | 4 | 1,838 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_bit_to_analog is
end tb_bit_to_analog;
architecture TB_bit2analog of tb_bit_to_analog is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
signal ina : bit;
signal ina_tmp : std_logic;
begin
-- Signal assignments
ina <= To_bit(ina_tmp); -- convert std_logic to bit
-- Component instances
d2a1 : entity work.bit_to_analog(ideal)
port map(
d => ina, -- bit type pin
a => ana_out
);
clk1 : entity work.clock_duty(ideal)
generic map(
off_time => 2 ms,
on_time => 1 ms
)
port map(
CLOCK_OUT => ina_tmp -- std_logic type pin
);
R1 : entity work.resistor(ideal)
generic map(
res => 10.0e3
)
port map(
p1 => ana_out,
p2 => electrical_ref
);
end TB_bit2analog;
| gpl-2.0 | b0e4d0783b372e732cd2aa989d8c5223 | 0.645811 | 3.781893 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/composite-data/computer.vhd | 4 | 2,943 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
entity computer is
end entity computer;
-- end not in book
architecture system_level of computer is
type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
-- not in book:
nop);
-- end not in book
type reg_number is range 0 to 31;
constant r0 : reg_number := 0; constant r1 : reg_number := 1; -- . . .
-- not in book:
constant r2 : reg_number := 2;
-- end not in book
type instruction is record
opcode : opcodes;
source_reg1, source_reg2, dest_reg : reg_number;
displacement : integer;
end record instruction;
type word is record
instr : instruction;
data : bit_vector(31 downto 0);
end record word;
signal address : natural;
signal read_word, write_word : word;
signal mem_read, mem_write : bit := '0';
signal mem_ready : bit := '0';
begin
cpu : process is
variable instr_reg : instruction;
variable PC : natural;
-- . . . -- other declarations for register file, etc.
begin
address <= PC;
mem_read <= '1';
wait until mem_ready = '1';
instr_reg := read_word.instr;
mem_read <= '0';
-- not in book:
wait until mem_ready = '0';
-- end not in book
PC := PC + 4;
case instr_reg.opcode is -- execute the instruction
-- . . .
-- not in book:
when others => null;
-- end not in book
end case;
end process cpu;
memory : process is
subtype address_range is natural range 0 to 2**14 - 1;
type memory_array is array (address_range) of word;
variable store : memory_array :=
( 0 => ( ( ld, r0, r0, r2, 40 ), X"00000000" ),
1 => ( ( breq, r2, r0, r0, 5 ), X"00000000" ),
-- . . .
40 => ( ( nop, r0, r0, r0, 0 ), X"FFFFFFFE"),
others => ( ( nop, r0, r0, r0, 0 ), X"00000000") );
begin
-- . . .
-- not in book:
wait until mem_read = '1';
read_word <= store(address);
mem_ready <= '1';
wait until mem_read = '0';
mem_ready <= '0';
-- end not in book
end process memory;
end architecture system_level;
| gpl-2.0 | 464df9b52a08b90bbe689e9cb7a1695d | 0.601767 | 3.628853 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_tb_03_01.vhd | 4 | 3,453 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_tb_03_01.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity test_bench_03_01 is
end entity test_bench_03_01;
architecture test_thermostat_example of test_bench_03_01 is
signal desired_temp, actual_temp : integer := 25;
signal heater_on : boolean := false;
begin
dut : entity work.thermostat(example)
port map ( desired_temp => desired_temp, actual_temp => actual_temp,
heater_on => heater_on );
stimulus : process is
begin
wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 21; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 29; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 21; wait for 5 sec;
actual_temp <= 22; wait for 5 sec;
actual_temp <= 23; wait for 5 sec;
actual_temp <= 24; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 29; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
desired_temp <= 30; wait for 5 sec;
actual_temp <= 25; wait for 5 sec;
actual_temp <= 26; wait for 5 sec;
actual_temp <= 27; wait for 5 sec;
actual_temp <= 28; wait for 5 sec;
actual_temp <= 29; wait for 5 sec;
actual_temp <= 30; wait for 5 sec;
actual_temp <= 31; wait for 5 sec;
actual_temp <= 32; wait for 5 sec;
actual_temp <= 33; wait for 5 sec;
actual_temp <= 34; wait for 5 sec;
actual_temp <= 35; wait for 5 sec;
actual_temp <= 34; wait for 5 sec;
actual_temp <= 33; wait for 5 sec;
actual_temp <= 32; wait for 5 sec;
actual_temp <= 31; wait for 5 sec;
actual_temp <= 30; wait for 5 sec;
wait;
end process stimulus;
end architecture test_thermostat_example;
| gpl-2.0 | 1a2a4066177f78d114fcd65382b29e65 | 0.605271 | 3.288571 | false | true | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2378.vhd | 4 | 1,862 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2378.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p03n01i02378ent IS
END c07s03b02x00p03n01i02378ent;
ARCHITECTURE c07s03b02x00p03n01i02378arch OF c07s03b02x00p03n01i02378ent IS
BEGIN
TESTING: PROCESS
type x1 is array (1 to 2) of integer;
constant v1: x1 := (1 => 0, 2 => 0); -- Success_here
BEGIN
assert NOT(v1(1)=0 and v1(2)=0)
report "***PASSED TEST: c07s03b02x00p03n01i02378"
severity NOTE;
assert (v1(1)=0 and v1(2)=0)
report "***FAILED TEST: c07s03b02x00p03n01i02378 - The element association consists of (optionally) choices followed by an arrow operator (=>) and an expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p03n01i02378arch;
| gpl-2.0 | 8e21e9e57dd4952168972db1d20658da | 0.668636 | 3.546667 | false | true | false | false |
tgingold/ghdl | testsuite/gna/issue635/ram.vhdl | 1 | 988 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Ram is
generic
(
addressWidth : in positive;
busWidth : in positive;
size : in positive
);
port
(
clk : in std_logic;
address : in unsigned(addressWidth - 1 downto 0);
writeEnable : in std_logic;
dataIn : in std_logic_vector(busWidth - 1 downto 0);
dataOut : out std_logic_vector(busWidth - 1 downto 0)
);
end Ram;
architecture Behavioral of Ram is
constant alignment : positive := busWidth / 8;
constant ramSize : positive := size / alignment;
type RamType is array(natural range <>) of std_logic_vector(busWidth - 1 downto 0);
subtype RamRange is natural range 0 to ramSize;
signal ram : RamType(RamRange);
begin
process(clk)
variable index : RamRange;
begin
if (rising_edge(clk))
then
index := to_integer(address) / alignment;
if (writeEnable = '1')
then
ram(index) <= dataIn;
end if;
dataOut <= ram(index);
end if;
end process;
end Behavioral;
| gpl-2.0 | 4f8414ccd6d373217fe9e6382a60e120 | 0.686235 | 3.207792 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc745.vhd | 4 | 9,196 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc745.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p05n02i00745pkg is
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c: character;
d: severity_level;
e: integer;
f: real;
g: time;
h: natural;
i: positive;
j: string(1 to 7);
k: bit_vector(0 to 3);
end record;
type array_rec_std is array (integer range <>) of record_std_package;
function F1(inp : boolean_vector) return boolean ;
function F2(inp : bit_vector) return bit ;
function F3(inp : string) return character ;
function F4(inp : severity_level_vector) return severity_level ;
function F5(inp : integer_vector) return integer ;
function F6(inp : real_vector) return real ;
function F7(inp : time_vector) return time ;
function F8(inp : natural_vector) return natural ;
function F9(inp : positive_vector) return positive ;
function F10(inp : array_rec_std) return record_std_package ;
end c01s01b01x01p05n02i00745pkg;
package body c01s01b01x01p05n02i00745pkg is
function F1(inp : boolean_vector) return boolean is
begin
for i in 0 to 15 loop
assert(inp(i) = true) report"wrong initialization of S1" severity error;
end loop;
return false;
end F1;
function F2(inp : bit_vector) return bit is
begin
for i in 0 to 3 loop
assert(inp(i) = '0') report"wrong initialization of S2" severity error;
end loop;
return '0';
end F2;
function F3(inp : string) return character is
begin
for i in 1 to 7 loop
assert(inp(i) = 's') report"wrong initialization of S3" severity error;
end loop;
return 'h';
end F3;
function F4(inp : severity_level_vector) return severity_level is
begin
for i in 0 to 15 loop
assert(inp(i) = note) report"wrong initialization of S4" severity error;
end loop;
return error;
end F4;
function F5(inp : integer_vector) return integer is
begin
for i in 0 to 15 loop
assert(inp(i) = 3) report"wrong initialization of S5" severity error;
end loop;
return 6;
end F5;
function F6(inp : real_vector) return real is
begin
for i in 0 to 15 loop
assert(inp(i) = 3.0) report"wrong initialization of S6" severity error;
end loop;
return 6.0;
end F6;
function F7(inp : time_vector) return time is
begin
for i in 0 to 15 loop
assert(inp(i) = 3 ns) report"wrong initialization of S7" severity error;
end loop;
return 6 ns;
end F7;
function F8(inp : natural_vector) return natural is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S8" severity error;
end loop;
return 6;
end F8;
function F9(inp : positive_vector) return positive is
begin
for i in 0 to 15 loop
assert(inp(i) = 1) report"wrong initialization of S9" severity error;
end loop;
return 6;
end F9;
function F10(inp : array_rec_std) return record_std_package is
begin
for i in 0 to 7 loop
assert(inp(i) = (true,'1','s',note,3,3.0,3 ns, 1,1,"sssssss","0000")) report"wrong initialization of S10" severity error;
end loop;
return (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100");
end F10;
end c01s01b01x01p05n02i00745pkg;
use work.c01s01b01x01p05n02i00745pkg.all;
ENTITY c01s01b01x01p05n02i00745ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level:= note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "sssssss";
C11 : bit_vector := B"0000";
C48 : record_std_package := (true,'1','s',note,3,3.0,3 ns,1,1,"sssssss","0000")
);
port(
S1 : boolean_vector(zero to fifteen) := (others => C1);
S2 : severity_level_vector(zero to fifteen) := (others => C4);
S3 : integer_vector(zero to fifteen) := (others => C5);
S4 : real_vector(zero to fifteen) := (others => C6);
S5 : time_vector (zero to fifteen) := (others => C7);
S6 : natural_vector(zero to fifteen) := (others => C8);
S7 : positive_vector(zero to fifteen) := (others => C9);
S8 : string(one to seven) := C10;
S9 : bit_vector(zero to three) := C11;
S48: array_rec_std(zero to seven) := (others => C48)
);
END c01s01b01x01p05n02i00745ent;
ARCHITECTURE c01s01b01x01p05n02i00745arch OF c01s01b01x01p05n02i00745ent IS
BEGIN
TESTING: PROCESS
variable var1 : boolean;
variable var4 : severity_level;
variable var5 : integer;
variable var6 : real;
variable var7 : time;
variable var8 : natural;
variable var9 : positive;
variable var2 : bit;
variable var3 : character;
variable var48: record_std_package;
BEGIN
var1 := F1(S1);
var2 := F2(S9);
var3 := F3(S8);
var4 := F4(S2);
var5 := F5(S3);
var6 := F6(S4);
var7 := F7(S5);
var8 := F8(S6);
var9 := F9(S7);
var48 := F10(S48);
wait for 1 ns;
assert(var1 = false) report "wrong assignment in the function F1" severity error;
assert(var2 = '0') report "wrong assignment in the function F2" severity error;
assert(var3 = 'h') report "wrong assignment in the function F3" severity error;
assert(var4 = error) report "wrong assignment in the function F4" severity error;
assert(var5 = 6) report "wrong assignment in the function F5" severity error;
assert(var6 = 6.0) report "wrong assignment in the function F6" severity error;
assert(var7 = 6 ns) report "wrong assignment in the function F7" severity error;
assert(var8 = 6) report "wrong assignment in the function F8" severity error;
assert(var9 = 6) report "wrong assignment in the function F9" severity error;
assert(var48 = (false,'0','s',error,5,5.0,5 ns,5,5,"metrics","1100")) report "wrong assignment in the function F10" severity error;
assert NOT( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***PASSED TEST: c01s01b01x01p05n02i00745"
severity NOTE;
assert ( var1 = F1(S1) and
var2 = F2(S9) and
var3 = F3(S8) and
var4 = F4(S2) and
var5 = F5(S3) and
var6 = F6(S4) and
var7 = F7(S5) and
var8 = F8(S6) and
var9 = F9(S7) and
var48 = F10(S48) )
report "***FAILED TEST: c01s01b01x01p05n02i00745 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00745arch;
| gpl-2.0 | 862d1ba75e01eea1fb2a91c05c1343ea | 0.587212 | 3.445485 | false | false | false | false |
tgingold/ghdl | testsuite/gna/issue50/idct.d/fsm_23.vhd | 2 | 115,488 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_23 is
port (
clock : in std_logic;
reset : in std_logic;
in0 : in std_logic;
out181 : out std_logic;
out182 : out std_logic;
out183 : out std_logic;
out184 : out std_logic;
out185 : out std_logic;
out8 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out16 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
in2 : in std_logic;
out23 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out31 : out std_logic;
out33 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out38 : out std_logic;
out40 : out std_logic;
out42 : out std_logic;
in3 : in std_logic;
out44 : out std_logic;
out46 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out52 : out std_logic;
out54 : out std_logic;
out56 : out std_logic;
out57 : out std_logic;
out58 : out std_logic;
in4 : in std_logic;
out60 : out std_logic;
in5 : in std_logic;
out164 : out std_logic;
out165 : out std_logic;
out167 : out std_logic;
out168 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out174 : out std_logic;
out176 : out std_logic;
out178 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
in1 : in std_logic;
out4 : out std_logic;
out90 : out std_logic;
out91 : out std_logic;
out97 : out std_logic;
out99 : out std_logic;
out101 : out std_logic;
in6 : in std_logic;
out103 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out135 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
out138 : out std_logic;
in11 : in std_logic;
out140 : out std_logic;
out141 : out std_logic;
out142 : out std_logic;
out143 : out std_logic;
out145 : out std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out153 : out std_logic;
out154 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out157 : out std_logic;
out158 : out std_logic;
out159 : out std_logic;
out160 : out std_logic;
out161 : out std_logic;
out162 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out120 : out std_logic;
out121 : out std_logic;
out122 : out std_logic;
out123 : out std_logic;
out124 : out std_logic;
out125 : out std_logic;
out126 : out std_logic;
in7 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
in8 : in std_logic;
out131 : out std_logic;
in9 : in std_logic;
out132 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
in10 : in std_logic;
out186 : out std_logic;
out187 : out std_logic;
out190 : out std_logic;
out195 : out std_logic;
out197 : out std_logic;
out198 : out std_logic;
out199 : out std_logic;
out200 : out std_logic;
out201 : out std_logic;
out203 : out std_logic;
out204 : out std_logic;
out206 : out std_logic;
out207 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out215 : out std_logic;
out217 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out222 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out231 : out std_logic;
out232 : out std_logic;
out234 : out std_logic;
out235 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out243 : out std_logic;
out245 : out std_logic;
out248 : out std_logic;
out249 : out std_logic;
out250 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out254 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out257 : out std_logic;
out259 : out std_logic;
out260 : out std_logic;
out262 : out std_logic;
out263 : out std_logic;
out265 : out std_logic;
out266 : out std_logic;
out268 : out std_logic;
out269 : out std_logic;
out271 : out std_logic;
out273 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out278 : out std_logic;
out279 : out std_logic;
out280 : out std_logic;
out281 : out std_logic;
out282 : out std_logic;
out283 : out std_logic;
out284 : out std_logic;
out285 : out std_logic;
out286 : out std_logic;
out287 : out std_logic;
out288 : out std_logic;
out289 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out292 : out std_logic;
out293 : out std_logic;
out294 : out std_logic;
out295 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out298 : out std_logic;
out311 : out std_logic;
out312 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
out315 : out std_logic;
out316 : out std_logic;
out318 : out std_logic;
out321 : out std_logic;
out322 : out std_logic;
out323 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out327 : out std_logic;
out328 : out std_logic;
out329 : out std_logic;
out333 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out343 : out std_logic;
out344 : out std_logic;
out345 : out std_logic;
out346 : out std_logic;
out349 : out std_logic;
out350 : out std_logic;
out351 : out std_logic;
out352 : out std_logic;
out353 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out357 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out366 : out std_logic;
out367 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out382 : out std_logic;
out383 : out std_logic;
out385 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out398 : out std_logic;
out400 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out404 : out std_logic;
out406 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out411 : out std_logic;
out412 : out std_logic;
out413 : out std_logic;
out414 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out422 : out std_logic;
out423 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
out428 : out std_logic;
out429 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out435 : out std_logic;
out436 : out std_logic;
out437 : out std_logic;
out438 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out455 : out std_logic;
out457 : out std_logic;
out458 : out std_logic;
out459 : out std_logic;
out460 : out std_logic;
out461 : out std_logic;
out462 : out std_logic;
out463 : out std_logic;
out464 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out469 : out std_logic;
out472 : out std_logic;
out475 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out483 : out std_logic;
out484 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
out491 : out std_logic;
out495 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out499 : out std_logic;
out500 : out std_logic;
out501 : out std_logic;
out512 : out std_logic;
out513 : out std_logic;
out517 : out std_logic;
out518 : out std_logic;
out519 : out std_logic;
out521 : out std_logic;
out522 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out531 : out std_logic;
out540 : out std_logic;
out542 : out std_logic;
out544 : out std_logic;
out545 : out std_logic;
out554 : out std_logic;
out555 : out std_logic;
out559 : out std_logic;
out560 : out std_logic;
out561 : out std_logic;
out562 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out567 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
out578 : out std_logic;
out580 : out std_logic;
out581 : out std_logic
);
end fsm_23;
architecture augh of fsm_23 is
signal state_cur : std_logic_vector(0 to 240) := (7 => '1', others => '0');
signal state_next : std_logic_vector(0 to 240) := (7 => '1', others => '0');
-- Buffers for outputs
signal out122_buf : std_logic := '0';
signal out122_bufn : std_logic;
signal out36_buf : std_logic := '0';
signal out36_bufn : std_logic;
signal out49_buf : std_logic := '0';
signal out49_bufn : std_logic;
signal out35_buf : std_logic := '0';
signal out35_bufn : std_logic;
signal out27_buf : std_logic := '0';
signal out27_bufn : std_logic;
signal out16_buf : std_logic := '0';
signal out16_bufn : std_logic;
signal out25_buf : std_logic := '0';
signal out25_bufn : std_logic;
signal out20_buf : std_logic := '0';
signal out20_bufn : std_logic;
signal out57_buf : std_logic := '0';
signal out57_bufn : std_logic;
signal out23_buf : std_logic := '0';
signal out23_bufn : std_logic;
signal out136_buf : std_logic := '0';
signal out136_bufn : std_logic;
signal out0_buf : std_logic := '0';
signal out0_bufn : std_logic;
signal out134_buf : std_logic := '0';
signal out134_bufn : std_logic;
signal out13_buf : std_logic := '0';
signal out13_bufn : std_logic;
signal out131_buf : std_logic := '0';
signal out131_bufn : std_logic;
signal out129_buf : std_logic := '0';
signal out129_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out31_buf : std_logic := '0';
signal out31_bufn : std_logic;
signal out126_buf : std_logic := '0';
signal out126_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out124_buf : std_logic := '0';
signal out124_bufn : std_logic;
signal out138_buf : std_logic := '0';
signal out138_bufn : std_logic;
signal out141_buf : std_logic := '0';
signal out141_bufn : std_logic;
signal out143_buf : std_logic := '0';
signal out143_bufn : std_logic;
signal out146_buf : std_logic := '0';
signal out146_bufn : std_logic;
signal out150_buf : std_logic := '0';
signal out150_bufn : std_logic;
signal out153_buf : std_logic := '0';
signal out153_bufn : std_logic;
signal out155_buf : std_logic := '0';
signal out155_bufn : std_logic;
signal out158_buf : std_logic := '0';
signal out158_bufn : std_logic;
signal out162_buf : std_logic := '0';
signal out162_bufn : std_logic;
signal out165_buf : std_logic := '0';
signal out165_bufn : std_logic;
signal out168_buf : std_logic := '0';
signal out168_bufn : std_logic;
signal out171_buf : std_logic := '0';
signal out171_bufn : std_logic;
signal out174_buf : std_logic := '0';
signal out174_bufn : std_logic;
signal out178_buf : std_logic := '0';
signal out178_bufn : std_logic;
signal out181_buf : std_logic := '0';
signal out181_bufn : std_logic;
signal out183_buf : std_logic := '0';
signal out183_bufn : std_logic;
signal out197_buf : std_logic := '0';
signal out197_bufn : std_logic;
signal out201_buf : std_logic := '0';
signal out201_bufn : std_logic;
signal out204_buf : std_logic := '0';
signal out204_bufn : std_logic;
signal out207_buf : std_logic := '0';
signal out207_bufn : std_logic;
signal out210_buf : std_logic := '0';
signal out210_bufn : std_logic;
signal out213_buf : std_logic := '0';
signal out213_bufn : std_logic;
signal out217_buf : std_logic := '0';
signal out217_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out222_buf : std_logic := '0';
signal out222_bufn : std_logic;
signal out225_buf : std_logic := '0';
signal out225_bufn : std_logic;
signal out229_buf : std_logic := '0';
signal out229_bufn : std_logic;
signal out232_buf : std_logic := '0';
signal out232_bufn : std_logic;
signal out235_buf : std_logic := '0';
signal out235_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out241_buf : std_logic := '0';
signal out241_bufn : std_logic;
signal out245_buf : std_logic := '0';
signal out245_bufn : std_logic;
signal out248_buf : std_logic := '0';
signal out248_bufn : std_logic;
signal out250_buf : std_logic := '0';
signal out250_bufn : std_logic;
signal out253_buf : std_logic := '0';
signal out253_bufn : std_logic;
signal out257_buf : std_logic := '0';
signal out257_bufn : std_logic;
signal out260_buf : std_logic := '0';
signal out260_bufn : std_logic;
signal out263_buf : std_logic := '0';
signal out263_bufn : std_logic;
signal out266_buf : std_logic := '0';
signal out266_bufn : std_logic;
signal out269_buf : std_logic := '0';
signal out269_bufn : std_logic;
signal out273_buf : std_logic := '0';
signal out273_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out278_buf : std_logic := '0';
signal out278_bufn : std_logic;
signal out280_buf : std_logic := '0';
signal out280_bufn : std_logic;
signal out281_buf : std_logic := '0';
signal out281_bufn : std_logic;
signal out282_buf : std_logic := '0';
signal out282_bufn : std_logic;
signal out284_buf : std_logic := '0';
signal out284_bufn : std_logic;
signal out285_buf : std_logic := '0';
signal out285_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out288_buf : std_logic := '0';
signal out288_bufn : std_logic;
signal out289_buf : std_logic := '0';
signal out289_bufn : std_logic;
signal out290_buf : std_logic := '0';
signal out290_bufn : std_logic;
signal out291_buf : std_logic := '0';
signal out291_bufn : std_logic;
signal out292_buf : std_logic := '0';
signal out292_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out294_buf : std_logic := '0';
signal out294_bufn : std_logic;
signal out295_buf : std_logic := '0';
signal out295_bufn : std_logic;
signal out296_buf : std_logic := '0';
signal out296_bufn : std_logic;
signal out312_buf : std_logic := '0';
signal out312_bufn : std_logic;
signal out313_buf : std_logic := '0';
signal out313_bufn : std_logic;
signal out314_buf : std_logic := '0';
signal out314_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out318_buf : std_logic := '0';
signal out318_bufn : std_logic;
signal out322_buf : std_logic := '0';
signal out322_bufn : std_logic;
signal out323_buf : std_logic := '0';
signal out323_bufn : std_logic;
signal out324_buf : std_logic := '0';
signal out324_bufn : std_logic;
signal out325_buf : std_logic := '0';
signal out325_bufn : std_logic;
signal out326_buf : std_logic := '0';
signal out326_bufn : std_logic;
signal out327_buf : std_logic := '0';
signal out327_bufn : std_logic;
signal out328_buf : std_logic := '0';
signal out328_bufn : std_logic;
signal out333_buf : std_logic := '0';
signal out333_bufn : std_logic;
signal out341_buf : std_logic := '0';
signal out341_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out343_buf : std_logic := '0';
signal out343_bufn : std_logic;
signal out344_buf : std_logic := '0';
signal out344_bufn : std_logic;
signal out346_buf : std_logic := '0';
signal out346_bufn : std_logic;
signal out349_buf : std_logic := '0';
signal out349_bufn : std_logic;
signal out351_buf : std_logic := '0';
signal out351_bufn : std_logic;
signal out352_buf : std_logic := '0';
signal out352_bufn : std_logic;
signal out353_buf : std_logic := '0';
signal out353_bufn : std_logic;
signal out354_buf : std_logic := '0';
signal out354_bufn : std_logic;
signal out357_buf : std_logic := '0';
signal out357_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out364_buf : std_logic := '0';
signal out364_bufn : std_logic;
signal out366_buf : std_logic := '0';
signal out366_bufn : std_logic;
signal out371_buf : std_logic := '0';
signal out371_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out395_buf : std_logic := '0';
signal out395_bufn : std_logic;
signal out400_buf : std_logic := '0';
signal out400_bufn : std_logic;
signal out401_buf : std_logic := '0';
signal out401_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out407_buf : std_logic := '0';
signal out407_bufn : std_logic;
signal out408_buf : std_logic := '0';
signal out408_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out413_buf : std_logic := '0';
signal out413_bufn : std_logic;
signal out414_buf : std_logic := '0';
signal out414_bufn : std_logic;
signal out417_buf : std_logic := '0';
signal out417_bufn : std_logic;
signal out418_buf : std_logic := '0';
signal out418_bufn : std_logic;
signal out422_buf : std_logic := '0';
signal out422_bufn : std_logic;
signal out426_buf : std_logic := '0';
signal out426_bufn : std_logic;
signal out428_buf : std_logic := '0';
signal out428_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out433_buf : std_logic := '0';
signal out433_bufn : std_logic;
signal out434_buf : std_logic := '0';
signal out434_bufn : std_logic;
signal out435_buf : std_logic := '0';
signal out435_bufn : std_logic;
signal out436_buf : std_logic := '0';
signal out436_bufn : std_logic;
signal out437_buf : std_logic := '0';
signal out437_bufn : std_logic;
signal out438_buf : std_logic := '0';
signal out438_bufn : std_logic;
signal out440_buf : std_logic := '0';
signal out440_bufn : std_logic;
signal out444_buf : std_logic := '0';
signal out444_bufn : std_logic;
signal out446_buf : std_logic := '0';
signal out446_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out458_buf : std_logic := '0';
signal out458_bufn : std_logic;
signal out459_buf : std_logic := '0';
signal out459_bufn : std_logic;
signal out460_buf : std_logic := '0';
signal out460_bufn : std_logic;
signal out461_buf : std_logic := '0';
signal out461_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out464_buf : std_logic := '0';
signal out464_bufn : std_logic;
signal out466_buf : std_logic := '0';
signal out466_bufn : std_logic;
signal out468_buf : std_logic := '0';
signal out468_bufn : std_logic;
signal out472_buf : std_logic := '0';
signal out472_bufn : std_logic;
signal out475_buf : std_logic := '0';
signal out475_bufn : std_logic;
signal out481_buf : std_logic := '0';
signal out481_bufn : std_logic;
signal out482_buf : std_logic := '0';
signal out482_bufn : std_logic;
signal out483_buf : std_logic := '0';
signal out483_bufn : std_logic;
signal out487_buf : std_logic := '0';
signal out487_bufn : std_logic;
signal out495_buf : std_logic := '0';
signal out495_bufn : std_logic;
signal out496_buf : std_logic := '0';
signal out496_bufn : std_logic;
signal out497_buf : std_logic := '0';
signal out497_bufn : std_logic;
signal out499_buf : std_logic := '0';
signal out499_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out512_buf : std_logic := '0';
signal out512_bufn : std_logic;
signal out517_buf : std_logic := '0';
signal out517_bufn : std_logic;
signal out518_buf : std_logic := '0';
signal out518_bufn : std_logic;
signal out521_buf : std_logic := '0';
signal out521_bufn : std_logic;
signal out524_buf : std_logic := '0';
signal out524_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out526_buf : std_logic := '0';
signal out526_bufn : std_logic;
signal out531_buf : std_logic := '0';
signal out531_bufn : std_logic;
signal out554_buf : std_logic := '0';
signal out554_bufn : std_logic;
signal out562_buf : std_logic := '0';
signal out562_bufn : std_logic;
signal out566_buf : std_logic := '0';
signal out566_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp90 : std_logic;
signal rtmcmp95 : std_logic;
signal rtmcmp98 : std_logic;
signal rtmcmp104 : std_logic;
signal rtmcmp148 : std_logic;
signal rtmcmp167 : std_logic;
signal rtmcmp174 : std_logic;
signal rtmcmp181 : std_logic;
signal rtmcmp183 : std_logic;
signal rtmcmp194 : std_logic;
signal rtmcmp197 : std_logic;
signal rtmcmp203 : std_logic;
signal rtmcmp205 : std_logic;
signal rtmcmp215 : std_logic;
-- Function calls: return IDs
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out122_buf <= out122_bufn;
out36_buf <= out36_bufn;
out49_buf <= out49_bufn;
out35_buf <= out35_bufn;
out27_buf <= out27_bufn;
out16_buf <= out16_bufn;
out25_buf <= out25_bufn;
out20_buf <= out20_bufn;
out57_buf <= out57_bufn;
out23_buf <= out23_bufn;
out136_buf <= out136_bufn;
out0_buf <= out0_bufn;
out134_buf <= out134_bufn;
out13_buf <= out13_bufn;
out131_buf <= out131_bufn;
out129_buf <= out129_bufn;
out111_buf <= out111_bufn;
out31_buf <= out31_bufn;
out126_buf <= out126_bufn;
out106_buf <= out106_bufn;
out124_buf <= out124_bufn;
out138_buf <= out138_bufn;
out141_buf <= out141_bufn;
out143_buf <= out143_bufn;
out146_buf <= out146_bufn;
out150_buf <= out150_bufn;
out153_buf <= out153_bufn;
out155_buf <= out155_bufn;
out158_buf <= out158_bufn;
out162_buf <= out162_bufn;
out165_buf <= out165_bufn;
out168_buf <= out168_bufn;
out171_buf <= out171_bufn;
out174_buf <= out174_bufn;
out178_buf <= out178_bufn;
out181_buf <= out181_bufn;
out183_buf <= out183_bufn;
out197_buf <= out197_bufn;
out201_buf <= out201_bufn;
out204_buf <= out204_bufn;
out207_buf <= out207_bufn;
out210_buf <= out210_bufn;
out213_buf <= out213_bufn;
out217_buf <= out217_bufn;
out220_buf <= out220_bufn;
out222_buf <= out222_bufn;
out225_buf <= out225_bufn;
out229_buf <= out229_bufn;
out232_buf <= out232_bufn;
out235_buf <= out235_bufn;
out238_buf <= out238_bufn;
out241_buf <= out241_bufn;
out245_buf <= out245_bufn;
out248_buf <= out248_bufn;
out250_buf <= out250_bufn;
out253_buf <= out253_bufn;
out257_buf <= out257_bufn;
out260_buf <= out260_bufn;
out263_buf <= out263_bufn;
out266_buf <= out266_bufn;
out269_buf <= out269_bufn;
out273_buf <= out273_bufn;
out276_buf <= out276_bufn;
out278_buf <= out278_bufn;
out280_buf <= out280_bufn;
out281_buf <= out281_bufn;
out282_buf <= out282_bufn;
out284_buf <= out284_bufn;
out285_buf <= out285_bufn;
out287_buf <= out287_bufn;
out288_buf <= out288_bufn;
out289_buf <= out289_bufn;
out290_buf <= out290_bufn;
out291_buf <= out291_bufn;
out292_buf <= out292_bufn;
out293_buf <= out293_bufn;
out294_buf <= out294_bufn;
out295_buf <= out295_bufn;
out296_buf <= out296_bufn;
out312_buf <= out312_bufn;
out313_buf <= out313_bufn;
out314_buf <= out314_bufn;
out315_buf <= out315_bufn;
out318_buf <= out318_bufn;
out322_buf <= out322_bufn;
out323_buf <= out323_bufn;
out324_buf <= out324_bufn;
out325_buf <= out325_bufn;
out326_buf <= out326_bufn;
out327_buf <= out327_bufn;
out328_buf <= out328_bufn;
out333_buf <= out333_bufn;
out341_buf <= out341_bufn;
out342_buf <= out342_bufn;
out343_buf <= out343_bufn;
out344_buf <= out344_bufn;
out346_buf <= out346_bufn;
out349_buf <= out349_bufn;
out351_buf <= out351_bufn;
out352_buf <= out352_bufn;
out353_buf <= out353_bufn;
out354_buf <= out354_bufn;
out357_buf <= out357_bufn;
out361_buf <= out361_bufn;
out364_buf <= out364_bufn;
out366_buf <= out366_bufn;
out371_buf <= out371_bufn;
out393_buf <= out393_bufn;
out394_buf <= out394_bufn;
out395_buf <= out395_bufn;
out400_buf <= out400_bufn;
out401_buf <= out401_bufn;
out404_buf <= out404_bufn;
out407_buf <= out407_bufn;
out408_buf <= out408_bufn;
out409_buf <= out409_bufn;
out410_buf <= out410_bufn;
out413_buf <= out413_bufn;
out414_buf <= out414_bufn;
out417_buf <= out417_bufn;
out418_buf <= out418_bufn;
out422_buf <= out422_bufn;
out426_buf <= out426_bufn;
out428_buf <= out428_bufn;
out431_buf <= out431_bufn;
out433_buf <= out433_bufn;
out434_buf <= out434_bufn;
out435_buf <= out435_bufn;
out436_buf <= out436_bufn;
out437_buf <= out437_bufn;
out438_buf <= out438_bufn;
out440_buf <= out440_bufn;
out444_buf <= out444_bufn;
out446_buf <= out446_bufn;
out451_buf <= out451_bufn;
out457_buf <= out457_bufn;
out458_buf <= out458_bufn;
out459_buf <= out459_bufn;
out460_buf <= out460_bufn;
out461_buf <= out461_bufn;
out463_buf <= out463_bufn;
out464_buf <= out464_bufn;
out466_buf <= out466_bufn;
out468_buf <= out468_bufn;
out472_buf <= out472_bufn;
out475_buf <= out475_bufn;
out481_buf <= out481_bufn;
out482_buf <= out482_bufn;
out483_buf <= out483_bufn;
out487_buf <= out487_bufn;
out495_buf <= out495_bufn;
out496_buf <= out496_bufn;
out497_buf <= out497_bufn;
out499_buf <= out499_bufn;
out500_buf <= out500_bufn;
out512_buf <= out512_bufn;
out517_buf <= out517_bufn;
out518_buf <= out518_bufn;
out521_buf <= out521_bufn;
out524_buf <= out524_bufn;
out525_buf <= out525_bufn;
out526_buf <= out526_bufn;
out531_buf <= out531_bufn;
out554_buf <= out554_bufn;
out562_buf <= out562_bufn;
out566_buf <= out566_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
-- Function calls: return IDs
end if;
end process;
-- Combinatorial process
-- Compute the next state
-- Compute the outputs
process (
-- Inputs of the FSM
reset, in0, in2, in3, in4, in5, in1, in6, in11, in7, in8, in9, in10,
-- Retiming: outputs of the comparators
rtmcmp90, rtmcmp95, rtmcmp98, rtmcmp104, rtmcmp148, rtmcmp167, rtmcmp174, rtmcmp181, rtmcmp183, rtmcmp194, rtmcmp197, rtmcmp203, rtmcmp205, rtmcmp215,
-- Retiming: the counters
rtmcounter0,
-- Function calls: return IDs
-- Current state
state_cur
)
begin
-- Reset the next state value
state_next <= (others => '0');
-- Default value to the outputs or output buffers
out22 <= '0';
out4 <= '0';
out122_bufn <= '0';
out50 <= '0';
out121 <= '0';
out36_bufn <= '0';
out49_bufn <= '0';
out35_bufn <= '0';
out99 <= '0';
out52 <= '0';
out18 <= '0';
out33 <= '0';
out123 <= '0';
out101 <= '0';
out90 <= '0';
out91 <= '0';
out27_bufn <= '0';
out16_bufn <= '0';
out26 <= '0';
out21 <= '0';
out24 <= '0';
out54 <= '0';
out25_bufn <= '0';
out20_bufn <= '0';
out58 <= '0';
out30 <= '0';
out8 <= '0';
out57_bufn <= '0';
out48 <= '0';
out56 <= '0';
out23_bufn <= '0';
out29 <= '0';
out19 <= '0';
out136_bufn <= '0';
out2 <= '0';
out1 <= '0';
out46 <= '0';
out0_bufn <= '0';
out135 <= '0';
out118 <= '0';
out116 <= '0';
out14 <= '0';
out134_bufn <= '0';
out28 <= '0';
out13_bufn <= '0';
out133 <= '0';
out131_bufn <= '0';
out132 <= '0';
out114 <= '0';
out130 <= '0';
out112 <= '0';
out38 <= '0';
out44 <= '0';
out97 <= '0';
out129_bufn <= '0';
out111_bufn <= '0';
out31_bufn <= '0';
out126_bufn <= '0';
out107 <= '0';
out108 <= '0';
out105 <= '0';
out106_bufn <= '0';
out125 <= '0';
out120 <= '0';
out124_bufn <= '0';
out103 <= '0';
out42 <= '0';
out40 <= '0';
out60 <= '0';
out137 <= '0';
out138_bufn <= '0';
out140 <= '0';
out141_bufn <= '0';
out142 <= '0';
out143_bufn <= '0';
out145 <= '0';
out146_bufn <= '0';
out148 <= '0';
out150_bufn <= '0';
out153_bufn <= '0';
out154 <= '0';
out155_bufn <= '0';
out156 <= '0';
out157 <= '0';
out158_bufn <= '0';
out159 <= '0';
out160 <= '0';
out161 <= '0';
out162_bufn <= '0';
out164 <= '0';
out165_bufn <= '0';
out167 <= '0';
out168_bufn <= '0';
out170 <= '0';
out171_bufn <= '0';
out173 <= '0';
out174_bufn <= '0';
out176 <= '0';
out178_bufn <= '0';
out181_bufn <= '0';
out182 <= '0';
out183_bufn <= '0';
out184 <= '0';
out185 <= '0';
out186 <= '0';
out187 <= '0';
out190 <= '0';
out195 <= '0';
out197_bufn <= '0';
out198 <= '0';
out199 <= '0';
out200 <= '0';
out201_bufn <= '0';
out203 <= '0';
out204_bufn <= '0';
out206 <= '0';
out207_bufn <= '0';
out209 <= '0';
out210_bufn <= '0';
out212 <= '0';
out213_bufn <= '0';
out215 <= '0';
out217_bufn <= '0';
out220_bufn <= '0';
out221 <= '0';
out222_bufn <= '0';
out223 <= '0';
out224 <= '0';
out225_bufn <= '0';
out226 <= '0';
out227 <= '0';
out228 <= '0';
out229_bufn <= '0';
out231 <= '0';
out232_bufn <= '0';
out234 <= '0';
out235_bufn <= '0';
out237 <= '0';
out238_bufn <= '0';
out240 <= '0';
out241_bufn <= '0';
out243 <= '0';
out245_bufn <= '0';
out248_bufn <= '0';
out249 <= '0';
out250_bufn <= '0';
out251 <= '0';
out252 <= '0';
out253_bufn <= '0';
out254 <= '0';
out255 <= '0';
out256 <= '0';
out257_bufn <= '0';
out259 <= '0';
out260_bufn <= '0';
out262 <= '0';
out263_bufn <= '0';
out265 <= '0';
out266_bufn <= '0';
out268 <= '0';
out269_bufn <= '0';
out271 <= '0';
out273_bufn <= '0';
out276_bufn <= '0';
out277 <= '0';
out278_bufn <= '0';
out279 <= '0';
out280_bufn <= '0';
out281_bufn <= '0';
out282_bufn <= '0';
out283 <= '0';
out284_bufn <= '0';
out285_bufn <= '0';
out286 <= '0';
out287_bufn <= '0';
out288_bufn <= '0';
out289_bufn <= '0';
out290_bufn <= '0';
out291_bufn <= '0';
out292_bufn <= '0';
out293_bufn <= '0';
out294_bufn <= '0';
out295_bufn <= '0';
out296_bufn <= '0';
out297 <= '0';
out298 <= '0';
out311 <= '0';
out312_bufn <= '0';
out313_bufn <= '0';
out314_bufn <= '0';
out315_bufn <= '0';
out316 <= '0';
out318_bufn <= '0';
out321 <= '0';
out322_bufn <= '0';
out323_bufn <= '0';
out324_bufn <= '0';
out325_bufn <= '0';
out326_bufn <= '0';
out327_bufn <= '0';
out328_bufn <= '0';
out329 <= '0';
out333_bufn <= '0';
out341_bufn <= '0';
out342_bufn <= '0';
out343_bufn <= '0';
out344_bufn <= '0';
out345 <= '0';
out346_bufn <= '0';
out349_bufn <= '0';
out350 <= '0';
out351_bufn <= '0';
out352_bufn <= '0';
out353_bufn <= '0';
out354_bufn <= '0';
out355 <= '0';
out357_bufn <= '0';
out361_bufn <= '0';
out362 <= '0';
out363 <= '0';
out364_bufn <= '0';
out366_bufn <= '0';
out367 <= '0';
out371_bufn <= '0';
out372 <= '0';
out373 <= '0';
out382 <= '0';
out383 <= '0';
out385 <= '0';
out393_bufn <= '0';
out394_bufn <= '0';
out395_bufn <= '0';
out396 <= '0';
out398 <= '0';
out400_bufn <= '0';
out401_bufn <= '0';
out402 <= '0';
out404_bufn <= '0';
out406 <= '0';
out407_bufn <= '0';
out408_bufn <= '0';
out409_bufn <= '0';
out410_bufn <= '0';
out411 <= '0';
out412 <= '0';
out413_bufn <= '0';
out414_bufn <= '0';
out416 <= '0';
out417_bufn <= '0';
out418_bufn <= '0';
out419 <= '0';
out422_bufn <= '0';
out423 <= '0';
out425 <= '0';
out426_bufn <= '0';
out428_bufn <= '0';
out429 <= '0';
out430 <= '0';
out431_bufn <= '0';
out433_bufn <= '0';
out434_bufn <= '0';
out435_bufn <= '0';
out436_bufn <= '0';
out437_bufn <= '0';
out438_bufn <= '0';
out440_bufn <= '0';
out441 <= '0';
out443 <= '0';
out444_bufn <= '0';
out445 <= '0';
out446_bufn <= '0';
out447 <= '0';
out450 <= '0';
out451_bufn <= '0';
out454 <= '0';
out455 <= '0';
out457_bufn <= '0';
out458_bufn <= '0';
out459_bufn <= '0';
out460_bufn <= '0';
out461_bufn <= '0';
out462 <= '0';
out463_bufn <= '0';
out464_bufn <= '0';
out465 <= '0';
out466_bufn <= '0';
out467 <= '0';
out468_bufn <= '0';
out469 <= '0';
out472_bufn <= '0';
out475_bufn <= '0';
out481_bufn <= '0';
out482_bufn <= '0';
out483_bufn <= '0';
out484 <= '0';
out487_bufn <= '0';
out488 <= '0';
out491 <= '0';
out495_bufn <= '0';
out496_bufn <= '0';
out497_bufn <= '0';
out498 <= '0';
out499_bufn <= '0';
out500_bufn <= '0';
out501 <= '0';
out512_bufn <= '0';
out513 <= '0';
out517_bufn <= '0';
out518_bufn <= '0';
out519 <= '0';
out521_bufn <= '0';
out522 <= '0';
out524_bufn <= '0';
out525_bufn <= '0';
out526_bufn <= '0';
out527 <= '0';
out528 <= '0';
out531_bufn <= '0';
out540 <= '0';
out542 <= '0';
out544 <= '0';
out545 <= '0';
out554_bufn <= '0';
out555 <= '0';
out559 <= '0';
out560 <= '0';
out561 <= '0';
out562_bufn <= '0';
out563 <= '0';
out566_bufn <= '0';
out567 <= '0';
out570 <= '0';
out572 <= '0';
out575 <= '0';
out577 <= '0';
out578 <= '0';
out580 <= '0';
out581 <= '0';
-- Retiming: default value for counters
rtmcounter0_next <= (others => '0');
-- Function calls: default values (no change)
-- For all states, compute the next state bits
-- And the outputs, and the next value for buffered outputs
if state_cur(0) = '1' then
-- Next state
state_next(109) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out1 <= '1';
out2 <= '1';
end if;
if state_cur(1) = '1' then
-- Next state
if (in0) = '1' then
state_next(1) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
else
-- Return from function: memextrct_0
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out8 <= '1';
out4 <= '1';
end if;
if state_cur(2) = '1' then
-- Next state
state_next(1) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(3) = '1' then
-- Next state
state_next(0) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out19 <= '1';
end if;
if state_cur(4) = '1' then
-- Next state
state_next(3) <= '1';
-- Next values for buffered outputs
out20_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out22 <= '1';
end if;
if state_cur(5) = '1' then
-- Next state
state_next(4) <= '1';
-- Next values for buffered outputs
out23_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out24 <= '1';
end if;
if state_cur(6) = '1' then
-- Next state
state_next(5) <= '1';
-- Next values for buffered outputs
out25_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out26 <= '1';
end if;
-- Info: This is the init/reset state
if state_cur(7) = '1' then
-- Next state
if (not (in2)) = '1' then
state_next(7) <= '1';
-- Next values for buffered outputs
else
if (in1) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
state_next(154) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out28 <= '1';
out29 <= '1';
end if;
if state_cur(8) = '1' then
-- Next state
state_next(6) <= '1';
-- Next values for buffered outputs
out27_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out30 <= '1';
end if;
if state_cur(9) = '1' then
-- Next state
state_next(9) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
end if;
if state_cur(10) = '1' then
-- Next state
state_next(8) <= '1';
-- Next values for buffered outputs
out31_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out33 <= '1';
out2 <= '1';
end if;
if state_cur(11) = '1' then
-- Next state
state_next(10) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
end if;
if state_cur(12) = '1' then
-- Next state
state_next(11) <= '1';
-- Next values for buffered outputs
out35_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
end if;
if state_cur(13) = '1' then
-- Next state
state_next(12) <= '1';
-- Next values for buffered outputs
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out50 <= '1';
out48 <= '1';
out46 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(14) = '1' then
-- Next state
state_next(13) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(15) = '1' then
-- Next state
if (in3) = '1' then
state_next(15) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
else
-- Return from function: memextrct_1
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out91 <= '1';
out90 <= '1';
end if;
if state_cur(16) = '1' then
-- Next state
if (in5) = '1' then
-- Function call: memextrct_1
state_next(19) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
else
if (in4) = '1' then
-- Function call: memextrct_0
state_next(2) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
else
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out97 <= '1';
end if;
if state_cur(17) = '1' then
-- Next state
state_next(14) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(18) = '1' then
-- Next state
state_next(17) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out108 <= '1';
out107 <= '1';
end if;
if state_cur(19) = '1' then
-- Next state
state_next(15) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(20) = '1' then
-- Next state
state_next(18) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out108 <= '1';
out121 <= '1';
end if;
if state_cur(21) = '1' then
-- Next state
state_next(20) <= '1';
-- Next values for buffered outputs
out126_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out132 <= '1';
out50 <= '1';
out21 <= '1';
out130 <= '1';
out108 <= '1';
end if;
if state_cur(22) = '1' then
-- Next state
state_next(21) <= '1';
-- Next values for buffered outputs
out131_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out108 <= '1';
out133 <= '1';
end if;
if state_cur(23) = '1' then
-- Next state
state_next(22) <= '1';
-- Next values for buffered outputs
out138_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out140 <= '1';
out108 <= '1';
end if;
if state_cur(24) = '1' then
-- Next state
state_next(23) <= '1';
-- Next values for buffered outputs
out143_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out145 <= '1';
out108 <= '1';
end if;
if state_cur(25) = '1' then
-- Next state
state_next(24) <= '1';
-- Next values for buffered outputs
out146_bufn <= '1';
out31_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out148 <= '1';
out108 <= '1';
end if;
if state_cur(26) = '1' then
-- Next state
state_next(25) <= '1';
-- Next values for buffered outputs
out150_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out154 <= '1';
out40 <= '1';
out21 <= '1';
out108 <= '1';
end if;
if state_cur(27) = '1' then
-- Next state
state_next(26) <= '1';
-- Next values for buffered outputs
out153_bufn <= '1';
out35_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out156 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(28) = '1' then
-- Next state
state_next(27) <= '1';
-- Next values for buffered outputs
out155_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(29) = '1' then
-- Next state
state_next(28) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out157 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(30) = '1' then
-- Next state
state_next(29) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(31) = '1' then
-- Next state
state_next(30) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out160 <= '1';
out159 <= '1';
end if;
if state_cur(32) = '1' then
-- Next state
state_next(31) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out161 <= '1';
out160 <= '1';
end if;
if state_cur(33) = '1' then
-- Next state
state_next(32) <= '1';
-- Next values for buffered outputs
out162_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out164 <= '1';
out160 <= '1';
end if;
if state_cur(34) = '1' then
-- Next state
state_next(33) <= '1';
-- Next values for buffered outputs
out165_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out167 <= '1';
out160 <= '1';
end if;
if state_cur(35) = '1' then
-- Next state
state_next(34) <= '1';
-- Next values for buffered outputs
out168_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out170 <= '1';
out160 <= '1';
end if;
if state_cur(36) = '1' then
-- Next state
state_next(35) <= '1';
-- Next values for buffered outputs
out171_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out173 <= '1';
out160 <= '1';
end if;
if state_cur(37) = '1' then
-- Next state
state_next(36) <= '1';
-- Next values for buffered outputs
out174_bufn <= '1';
out31_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out176 <= '1';
out160 <= '1';
end if;
if state_cur(38) = '1' then
-- Next state
state_next(37) <= '1';
-- Next values for buffered outputs
out178_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out182 <= '1';
out40 <= '1';
out21 <= '1';
out160 <= '1';
end if;
if state_cur(39) = '1' then
-- Next state
state_next(38) <= '1';
-- Next values for buffered outputs
out181_bufn <= '1';
out35_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out184 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(40) = '1' then
-- Next state
state_next(39) <= '1';
-- Next values for buffered outputs
out183_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(41) = '1' then
-- Next state
state_next(40) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out185 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(42) = '1' then
-- Next state
state_next(41) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(43) = '1' then
-- Next state
if (in7) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
if (not (in6)) = '1' then
state_next(43) <= '1';
-- Next values for buffered outputs
else
state_next(108) <= '1';
-- Next values for buffered outputs
out371_bufn <= '1';
end if;
end if;
-- Assignment of non-buffered outputs
out190 <= '1';
out187 <= '1';
out186 <= '1';
end if;
if state_cur(44) = '1' then
-- Next state
if (in7) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
if (not (in8)) = '1' then
state_next(44) <= '1';
-- Next values for buffered outputs
else
state_next(110) <= '1';
-- Next values for buffered outputs
out371_bufn <= '1';
end if;
end if;
-- Assignment of non-buffered outputs
out195 <= '1';
out187 <= '1';
end if;
if state_cur(45) = '1' then
-- Next state
state_next(42) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out199 <= '1';
out198 <= '1';
end if;
if state_cur(46) = '1' then
-- Next state
state_next(45) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out200 <= '1';
out199 <= '1';
end if;
if state_cur(47) = '1' then
-- Next state
state_next(46) <= '1';
-- Next values for buffered outputs
out201_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out203 <= '1';
out199 <= '1';
end if;
if state_cur(48) = '1' then
-- Next state
state_next(47) <= '1';
-- Next values for buffered outputs
out204_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out206 <= '1';
out199 <= '1';
end if;
if state_cur(49) = '1' then
-- Next state
state_next(48) <= '1';
-- Next values for buffered outputs
out207_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out209 <= '1';
out199 <= '1';
end if;
if state_cur(50) = '1' then
-- Next state
state_next(49) <= '1';
-- Next values for buffered outputs
out210_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out212 <= '1';
out199 <= '1';
end if;
if state_cur(51) = '1' then
-- Next state
state_next(50) <= '1';
-- Next values for buffered outputs
out213_bufn <= '1';
out31_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out215 <= '1';
out199 <= '1';
end if;
if state_cur(52) = '1' then
-- Next state
state_next(51) <= '1';
-- Next values for buffered outputs
out217_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out221 <= '1';
out40 <= '1';
out21 <= '1';
out199 <= '1';
end if;
if state_cur(53) = '1' then
-- Next state
state_next(52) <= '1';
-- Next values for buffered outputs
out220_bufn <= '1';
out35_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out223 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(54) = '1' then
-- Next state
state_next(53) <= '1';
-- Next values for buffered outputs
out222_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(55) = '1' then
-- Next state
state_next(54) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out224 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(56) = '1' then
-- Next state
state_next(55) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(57) = '1' then
-- Next state
state_next(56) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out227 <= '1';
out226 <= '1';
end if;
if state_cur(58) = '1' then
-- Next state
state_next(57) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out228 <= '1';
out227 <= '1';
end if;
if state_cur(59) = '1' then
-- Next state
state_next(58) <= '1';
-- Next values for buffered outputs
out229_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out231 <= '1';
out227 <= '1';
end if;
if state_cur(60) = '1' then
-- Next state
state_next(87) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(61) = '1' then
-- Next state
state_next(59) <= '1';
-- Next values for buffered outputs
out232_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out234 <= '1';
out227 <= '1';
end if;
if state_cur(62) = '1' then
-- Next state
state_next(61) <= '1';
-- Next values for buffered outputs
out235_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out237 <= '1';
out227 <= '1';
end if;
if state_cur(63) = '1' then
-- Next state
state_next(62) <= '1';
-- Next values for buffered outputs
out238_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out240 <= '1';
out227 <= '1';
end if;
if state_cur(64) = '1' then
-- Next state
state_next(63) <= '1';
-- Next values for buffered outputs
out241_bufn <= '1';
out31_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out243 <= '1';
out227 <= '1';
end if;
if state_cur(65) = '1' then
-- Next state
state_next(64) <= '1';
-- Next values for buffered outputs
out245_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out249 <= '1';
out40 <= '1';
out21 <= '1';
out227 <= '1';
end if;
if state_cur(66) = '1' then
-- Next state
state_next(65) <= '1';
-- Next values for buffered outputs
out248_bufn <= '1';
out35_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out251 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(67) = '1' then
-- Next state
state_next(66) <= '1';
-- Next values for buffered outputs
out250_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(68) = '1' then
-- Next state
state_next(67) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out252 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(69) = '1' then
-- Next state
state_next(68) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(70) = '1' then
-- Next state
state_next(69) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out255 <= '1';
out254 <= '1';
end if;
if state_cur(71) = '1' then
-- Next state
state_next(70) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out256 <= '1';
out255 <= '1';
end if;
if state_cur(72) = '1' then
-- Next state
state_next(71) <= '1';
-- Next values for buffered outputs
out257_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out259 <= '1';
out255 <= '1';
end if;
if state_cur(73) = '1' then
-- Next state
state_next(72) <= '1';
-- Next values for buffered outputs
out260_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out262 <= '1';
out255 <= '1';
end if;
if state_cur(74) = '1' then
-- Next state
state_next(73) <= '1';
-- Next values for buffered outputs
out263_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out265 <= '1';
out255 <= '1';
end if;
if state_cur(75) = '1' then
-- Next state
state_next(74) <= '1';
-- Next values for buffered outputs
out266_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out268 <= '1';
out255 <= '1';
end if;
if state_cur(76) = '1' then
-- Next state
state_next(75) <= '1';
-- Next values for buffered outputs
out269_bufn <= '1';
out31_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out271 <= '1';
out255 <= '1';
end if;
if state_cur(77) = '1' then
-- Next state
state_next(76) <= '1';
-- Next values for buffered outputs
out273_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out277 <= '1';
out40 <= '1';
out21 <= '1';
out255 <= '1';
end if;
if state_cur(78) = '1' then
-- Next state
state_next(77) <= '1';
-- Next values for buffered outputs
out276_bufn <= '1';
out35_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out279 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(79) = '1' then
-- Next state
state_next(80) <= '1';
-- Next values for buffered outputs
out285_bufn <= '1';
out284_bufn <= '1';
out269_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(80) = '1' then
-- Next state
state_next(113) <= '1';
-- Next values for buffered outputs
out395_bufn <= '1';
out284_bufn <= '1';
out146_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(81) = '1' then
-- Next state
state_next(82) <= '1';
-- Next values for buffered outputs
out290_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(82) = '1' then
-- Next state
state_next(83) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out292_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(83) = '1' then
-- Next state
state_next(85) <= '1';
-- Next values for buffered outputs
out295_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out286 <= '1';
end if;
if state_cur(84) = '1' then
-- Next state
state_next(89) <= '1';
-- Next values for buffered outputs
out313_bufn <= '1';
out281_bufn <= '1';
out312_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(85) = '1' then
-- Next state
state_next(86) <= '1';
-- Next values for buffered outputs
out296_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(86) = '1' then
-- Next state
state_next(90) <= '1';
-- Next values for buffered outputs
out318_bufn <= '1';
out280_bufn <= '1';
out315_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(87) = '1' then
-- Next state
if (in9) = '1' then
state_next(87) <= '1';
-- Next values for buffered outputs
else
state_next(16) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out298 <= '1';
out297 <= '1';
end if;
if state_cur(88) = '1' then
-- Next state
if (in1) = '1' then
if (in5) = '1' then
state_next(43) <= '1';
-- Next values for buffered outputs
else
state_next(44) <= '1';
-- Next values for buffered outputs
end if;
else
state_next(9) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out311 <= '1';
end if;
if state_cur(89) = '1' then
-- Next state
state_next(112) <= '1';
-- Next values for buffered outputs
out394_bufn <= '1';
out284_bufn <= '1';
out393_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(90) = '1' then
if rtmcmp90 = '1' then
-- Next state
state_next(93) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out325_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out56 <= '1';
out137 <= '1';
out125 <= '1';
out116 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(90) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out318_bufn <= '1';
out280_bufn <= '1';
out315_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out316 <= '1';
end if;
if state_cur(91) = '1' then
-- Next state
state_next(170) <= '1';
-- Next values for buffered outputs
out487_bufn <= '1';
out284_bufn <= '1';
out266_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
out321 <= '1';
end if;
if state_cur(92) = '1' then
-- Next state
state_next(240) <= '1';
-- Next values for buffered outputs
out217_bufn <= '1';
out295_bufn <= '1';
out281_bufn <= '1';
out562_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(93) = '1' then
-- Next state
state_next(101) <= '1';
-- Next values for buffered outputs
out323_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out58 <= '1';
out286 <= '1';
end if;
if state_cur(94) = '1' then
-- Next state
state_next(96) <= '1';
-- Next values for buffered outputs
out341_bufn <= '1';
out281_bufn <= '1';
out241_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(95) = '1' then
if rtmcmp95 = '1' then
-- Next state
state_next(210) <= '1';
-- Next values for buffered outputs
out418_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out142 <= '1';
out112 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(95) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out333_bufn <= '1';
out245_bufn <= '1';
out318_bufn <= '1';
out328_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out329 <= '1';
end if;
if state_cur(96) = '1' then
-- Next state
state_next(91) <= '1';
-- Next values for buffered outputs
out322_bufn <= '1';
out281_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(97) = '1' then
-- Next state
state_next(95) <= '1';
-- Next values for buffered outputs
out333_bufn <= '1';
out245_bufn <= '1';
out318_bufn <= '1';
out328_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(98) = '1' then
if rtmcmp98 = '1' then
-- Next state
state_next(97) <= '1';
-- Next values for buffered outputs
out342_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(98) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out343_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out345 <= '1';
end if;
if state_cur(99) = '1' then
-- Next state
state_next(119) <= '1';
-- Next values for buffered outputs
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(100) = '1' then
-- Next state
state_next(233) <= '1';
-- Next values for buffered outputs
out566_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out125 <= '1';
out286 <= '1';
end if;
if state_cur(101) = '1' then
-- Next state
state_next(98) <= '1';
-- Next values for buffered outputs
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out343_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(102) = '1' then
-- Next state
state_next(239) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out350 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(103) = '1' then
-- Next state
state_next(146) <= '1';
-- Next values for buffered outputs
out401_bufn <= '1';
out444_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out283 <= '1';
end if;
if state_cur(104) = '1' then
if rtmcmp104 = '1' then
-- Next state
state_next(103) <= '1';
-- Next values for buffered outputs
out352_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out142 <= '1';
out99 <= '1';
out130 <= '1';
out101 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(104) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out129_bufn <= '1';
out357_bufn <= '1';
out354_bufn <= '1';
out353_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out355 <= '1';
end if;
if state_cur(105) = '1' then
-- Next state
state_next(133) <= '1';
-- Next values for buffered outputs
out431_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out363 <= '1';
out362 <= '1';
end if;
if state_cur(106) = '1' then
-- Next state
state_next(186) <= '1';
-- Next values for buffered outputs
out518_bufn <= '1';
out284_bufn <= '1';
out153_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(107) = '1' then
-- Next state
state_next(148) <= '1';
-- Next values for buffered outputs
out446_bufn <= '1';
out413_bufn <= '1';
out281_bufn <= '1';
out250_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out367 <= '1';
out283 <= '1';
end if;
if state_cur(108) = '1' then
-- Next state
if (in10) = '1' then
state_next(109) <= '1';
-- Next values for buffered outputs
else
state_next(154) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out372 <= '1';
end if;
if state_cur(109) = '1' then
-- Next state
state_next(43) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out382 <= '1';
out373 <= '1';
end if;
if state_cur(110) = '1' then
-- Next state
if (in11) = '1' then
state_next(44) <= '1';
-- Next values for buffered outputs
else
state_next(111) <= '1';
-- Next values for buffered outputs
out284_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out372 <= '1';
out385 <= '1';
out383 <= '1';
end if;
if state_cur(111) = '1' then
-- Next state
state_next(153) <= '1';
-- Next values for buffered outputs
out422_bufn <= '1';
out284_bufn <= '1';
out278_bufn <= '1';
-- Assignment of non-buffered outputs
out372 <= '1';
out286 <= '1';
end if;
if state_cur(112) = '1' then
-- Next state
state_next(94) <= '1';
-- Next values for buffered outputs
out326_bufn <= '1';
out284_bufn <= '1';
out210_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(113) = '1' then
-- Next state
state_next(160) <= '1';
-- Next values for buffered outputs
out461_bufn <= '1';
out281_bufn <= '1';
out178_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(114) = '1' then
-- Next state
state_next(196) <= '1';
-- Next values for buffered outputs
out328_bufn <= '1';
out284_bufn <= '1';
out155_bufn <= '1';
-- Assignment of non-buffered outputs
out142 <= '1';
out396 <= '1';
out286 <= '1';
end if;
if state_cur(115) = '1' then
-- Next state
state_next(105) <= '1';
-- Next values for buffered outputs
out364_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out398 <= '1';
out363 <= '1';
end if;
if state_cur(116) = '1' then
-- Next state
state_next(120) <= '1';
-- Next values for buffered outputs
out407_bufn <= '1';
out281_bufn <= '1';
out168_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(117) = '1' then
-- Next state
state_next(211) <= '1';
-- Next values for buffered outputs
out458_bufn <= '1';
out475_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(118) = '1' then
-- Next state
state_next(151) <= '1';
-- Next values for buffered outputs
out333_bufn <= '1';
out31_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out402 <= '1';
out363 <= '1';
end if;
if state_cur(119) = '1' then
-- Next state
state_next(150) <= '1';
-- Next values for buffered outputs
out366_bufn <= '1';
out35_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out406 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(120) = '1' then
-- Next state
state_next(121) <= '1';
-- Next values for buffered outputs
out409_bufn <= '1';
out281_bufn <= '1';
out408_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(121) = '1' then
-- Next state
state_next(139) <= '1';
-- Next values for buffered outputs
out438_bufn <= '1';
out284_bufn <= '1';
out431_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(122) = '1' then
-- Next state
state_next(123) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out412 <= '1';
out411 <= '1';
end if;
if state_cur(123) = '1' then
-- Next state
state_next(212) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(124) = '1' then
-- Next state
state_next(81) <= '1';
-- Next values for buffered outputs
out288_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out283 <= '1';
end if;
if state_cur(125) = '1' then
-- Next state
state_next(128) <= '1';
-- Next values for buffered outputs
out422_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(126) = '1' then
-- Next state
state_next(125) <= '1';
-- Next values for buffered outputs
out414_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out416 <= '1';
out38 <= '1';
out286 <= '1';
end if;
if state_cur(127) = '1' then
-- Next state
state_next(169) <= '1';
-- Next values for buffered outputs
out417_bufn <= '1';
out483_bufn <= '1';
out482_bufn <= '1';
out318_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out419 <= '1';
out283 <= '1';
end if;
if state_cur(128) = '1' then
-- Next state
state_next(124) <= '1';
-- Next values for buffered outputs
out413_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(129) = '1' then
-- Next state
state_next(130) <= '1';
-- Next values for buffered outputs
out426_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out423 <= '1';
out412 <= '1';
end if;
if state_cur(130) = '1' then
-- Next state
state_next(143) <= '1';
-- Next values for buffered outputs
out435_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out425 <= '1';
out412 <= '1';
end if;
if state_cur(131) = '1' then
-- Next state
state_next(102) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(132) = '1' then
-- Next state
state_next(144) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
-- Assignment of non-buffered outputs
out114 <= '1';
out429 <= '1';
out52 <= '1';
out286 <= '1';
end if;
if state_cur(133) = '1' then
-- Next state
state_next(237) <= '1';
-- Next values for buffered outputs
out475_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out430 <= '1';
out363 <= '1';
end if;
if state_cur(134) = '1' then
-- Next state
state_next(227) <= '1';
-- Next values for buffered outputs
out496_bufn <= '1';
out284_bufn <= '1';
out263_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(135) = '1' then
-- Next state
state_next(117) <= '1';
-- Next values for buffered outputs
out352_bufn <= '1';
out281_bufn <= '1';
out401_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(136) = '1' then
-- Next state
state_next(135) <= '1';
-- Next values for buffered outputs
out434_bufn <= '1';
out281_bufn <= '1';
out165_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(137) = '1' then
-- Next state
state_next(228) <= '1';
-- Next values for buffered outputs
out463_bufn <= '1';
out284_bufn <= '1';
out260_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(138) = '1' then
-- Next state
state_next(137) <= '1';
-- Next values for buffered outputs
out436_bufn <= '1';
out281_bufn <= '1';
out435_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(139) = '1' then
-- Next state
state_next(229) <= '1';
-- Next values for buffered outputs
out495_bufn <= '1';
out284_bufn <= '1';
out204_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(140) = '1' then
-- Next state
state_next(126) <= '1';
-- Next values for buffered outputs
out324_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(141) = '1' then
-- Next state
state_next(142) <= '1';
-- Next values for buffered outputs
out122_bufn <= '1';
out134_bufn <= '1';
out400_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out116 <= '1';
out283 <= '1';
end if;
if state_cur(142) = '1' then
-- Next state
state_next(168) <= '1';
-- Next values for buffered outputs
out481_bufn <= '1';
out351_bufn <= '1';
-- Assignment of non-buffered outputs
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
end if;
if state_cur(143) = '1' then
-- Next state
state_next(149) <= '1';
-- Next values for buffered outputs
out451_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out441 <= '1';
out412 <= '1';
end if;
if state_cur(144) = '1' then
-- Next state
state_next(178) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out112 <= '1';
end if;
if state_cur(145) = '1' then
-- Next state
state_next(99) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out443 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(146) = '1' then
-- Next state
state_next(100) <= '1';
-- Next values for buffered outputs
out124_bufn <= '1';
out349_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out445 <= '1';
out50 <= '1';
out283 <= '1';
end if;
if state_cur(147) = '1' then
-- Next state
state_next(78) <= '1';
-- Next values for buffered outputs
out278_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(148) = '1' then
if rtmcmp148 = '1' then
-- Next state
state_next(172) <= '1';
-- Next values for buffered outputs
out296_bufn <= '1';
out284_bufn <= '1';
out220_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out103 <= '1';
out125 <= '1';
out99 <= '1';
out123 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(148) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out446_bufn <= '1';
out413_bufn <= '1';
out281_bufn <= '1';
out250_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out447 <= '1';
end if;
if state_cur(149) = '1' then
-- Next state
state_next(226) <= '1';
-- Next values for buffered outputs
out354_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out450 <= '1';
out412 <= '1';
end if;
if state_cur(150) = '1' then
-- Next state
state_next(118) <= '1';
-- Next values for buffered outputs
out404_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out454 <= '1';
out40 <= '1';
out21 <= '1';
out363 <= '1';
end if;
if state_cur(151) = '1' then
-- Next state
state_next(115) <= '1';
-- Next values for buffered outputs
out393_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out455 <= '1';
out363 <= '1';
end if;
if state_cur(152) = '1' then
-- Next state
state_next(230) <= '1';
-- Next values for buffered outputs
out512_bufn <= '1';
out281_bufn <= '1';
out171_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(153) = '1' then
-- Next state
state_next(114) <= '1';
-- Next values for buffered outputs
out292_bufn <= '1';
out284_bufn <= '1';
out222_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(154) = '1' then
-- Next state
state_next(44) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out372 <= '1';
end if;
if state_cur(155) = '1' then
-- Next state
state_next(232) <= '1';
-- Next values for buffered outputs
out517_bufn <= '1';
out284_bufn <= '1';
out207_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(156) = '1' then
-- Next state
state_next(104) <= '1';
-- Next values for buffered outputs
out129_bufn <= '1';
out357_bufn <= '1';
out354_bufn <= '1';
out353_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(157) = '1' then
-- Next state
state_next(156) <= '1';
-- Next values for buffered outputs
out458_bufn <= '1';
out324_bufn <= '1';
-- Assignment of non-buffered outputs
out56 <= '1';
out137 <= '1';
out116 <= '1';
out283 <= '1';
end if;
if state_cur(158) = '1' then
-- Next state
state_next(157) <= '1';
-- Next values for buffered outputs
out136_bufn <= '1';
out434_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(159) = '1' then
-- Next state
state_next(158) <= '1';
-- Next values for buffered outputs
out459_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(160) = '1' then
-- Next state
state_next(189) <= '1';
-- Next values for buffered outputs
out525_bufn <= '1';
out281_bufn <= '1';
out245_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(161) = '1' then
-- Next state
state_next(106) <= '1';
-- Next values for buffered outputs
out288_bufn <= '1';
out284_bufn <= '1';
out276_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
out462 <= '1';
out283 <= '1';
end if;
if state_cur(162) = '1' then
-- Next state
state_next(159) <= '1';
-- Next values for buffered outputs
out460_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(163) = '1' then
-- Next state
state_next(162) <= '1';
-- Next values for buffered outputs
out463_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out58 <= '1';
out465 <= '1';
out48 <= '1';
out283 <= '1';
end if;
if state_cur(164) = '1' then
-- Next state
state_next(163) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out408_bufn <= '1';
out464_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(165) = '1' then
-- Next state
state_next(166) <= '1';
-- Next values for buffered outputs
out273_bufn <= '1';
out343_bufn <= '1';
out281_bufn <= '1';
out181_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(166) = '1' then
-- Next state
state_next(215) <= '1';
-- Next values for buffered outputs
out562_bufn <= '1';
out342_bufn <= '1';
out284_bufn <= '1';
out404_bufn <= '1';
-- Assignment of non-buffered outputs
out467 <= '1';
out142 <= '1';
out283 <= '1';
end if;
if state_cur(167) = '1' then
if rtmcmp167 = '1' then
-- Next state
state_next(164) <= '1';
-- Next values for buffered outputs
out409_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(167) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out475_bufn <= '1';
out257_bufn <= '1';
out472_bufn <= '1';
out451_bufn <= '1';
out468_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out469 <= '1';
end if;
if state_cur(168) = '1' then
-- Next state
state_next(132) <= '1';
-- Next values for buffered outputs
out357_bufn <= '1';
out428_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out283 <= '1';
end if;
if state_cur(169) = '1' then
-- Next state
state_next(225) <= '1';
-- Next values for buffered outputs
out554_bufn <= '1';
out284_bufn <= '1';
out333_bufn <= '1';
-- Assignment of non-buffered outputs
out137 <= '1';
out135 <= '1';
out484 <= '1';
out283 <= '1';
end if;
if state_cur(170) = '1' then
-- Next state
state_next(152) <= '1';
-- Next values for buffered outputs
out353_bufn <= '1';
out284_bufn <= '1';
out138_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(171) = '1' then
-- Next state
state_next(167) <= '1';
-- Next values for buffered outputs
out475_bufn <= '1';
out257_bufn <= '1';
out472_bufn <= '1';
out451_bufn <= '1';
out468_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(172) = '1' then
-- Next state
state_next(187) <= '1';
-- Next values for buffered outputs
out521_bufn <= '1';
out284_bufn <= '1';
out150_bufn <= '1';
-- Assignment of non-buffered outputs
out137 <= '1';
out135 <= '1';
out488 <= '1';
out286 <= '1';
end if;
if state_cur(173) = '1' then
-- Next state
state_next(84) <= '1';
-- Next values for buffered outputs
out293_bufn <= '1';
out281_bufn <= '1';
out174_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(174) = '1' then
if rtmcmp174 = '1' then
-- Next state
state_next(171) <= '1';
-- Next values for buffered outputs
out438_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(174) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out229_bufn <= '1';
out357_bufn <= '1';
out407_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out491 <= '1';
end if;
if state_cur(175) = '1' then
-- Next state
state_next(174) <= '1';
-- Next values for buffered outputs
out229_bufn <= '1';
out357_bufn <= '1';
out407_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(176) = '1' then
-- Next state
state_next(175) <= '1';
-- Next values for buffered outputs
out495_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(177) = '1' then
-- Next state
state_next(176) <= '1';
-- Next values for buffered outputs
out437_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(178) = '1' then
-- Next state
state_next(145) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(179) = '1' then
-- Next state
state_next(177) <= '1';
-- Next values for buffered outputs
out496_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out498 <= '1';
out46 <= '1';
out283 <= '1';
end if;
if state_cur(180) = '1' then
-- Next state
state_next(179) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out497_bufn <= '1';
out436_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(181) = '1' then
if rtmcmp181 = '1' then
-- Next state
state_next(180) <= '1';
-- Next values for buffered outputs
out499_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(181) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out260_bufn <= '1';
out500_bufn <= '1';
out435_bufn <= '1';
out395_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out501 <= '1';
end if;
if state_cur(182) = '1' then
-- Next state
state_next(181) <= '1';
-- Next values for buffered outputs
out260_bufn <= '1';
out500_bufn <= '1';
out435_bufn <= '1';
out395_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(183) = '1' then
if rtmcmp183 = '1' then
-- Next state
state_next(182) <= '1';
-- Next values for buffered outputs
out457_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(183) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out472_bufn <= '1';
out401_bufn <= '1';
out512_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out513 <= '1';
end if;
if state_cur(184) = '1' then
-- Next state
state_next(183) <= '1';
-- Next values for buffered outputs
out472_bufn <= '1';
out401_bufn <= '1';
out512_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(185) = '1' then
-- Next state
state_next(92) <= '1';
-- Next values for buffered outputs
out323_bufn <= '1';
out284_bufn <= '1';
out217_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out101 <= '1';
out283 <= '1';
end if;
if state_cur(186) = '1' then
-- Next state
state_next(107) <= '1';
-- Next values for buffered outputs
out366_bufn <= '1';
out315_bufn <= '1';
out281_bufn <= '1';
out183_bufn <= '1';
-- Assignment of non-buffered outputs
out142 <= '1';
out519 <= '1';
out286 <= '1';
end if;
if state_cur(187) = '1' then
-- Next state
state_next(185) <= '1';
-- Next values for buffered outputs
out290_bufn <= '1';
out281_bufn <= '1';
out248_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out130 <= '1';
out522 <= '1';
out286 <= '1';
end if;
if state_cur(188) = '1' then
-- Next state
state_next(184) <= '1';
-- Next values for buffered outputs
out517_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(189) = '1' then
-- Next state
state_next(190) <= '1';
-- Next values for buffered outputs
out526_bufn <= '1';
out284_bufn <= '1';
out213_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(190) = '1' then
-- Next state
state_next(173) <= '1';
-- Next values for buffered outputs
out468_bufn <= '1';
out284_bufn <= '1';
out143_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(191) = '1' then
-- Next state
state_next(188) <= '1';
-- Next values for buffered outputs
out524_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(192) = '1' then
-- Next state
state_next(191) <= '1';
-- Next values for buffered outputs
out487_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out527 <= '1';
out44 <= '1';
out283 <= '1';
end if;
if state_cur(193) = '1' then
-- Next state
state_next(192) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out312_bufn <= '1';
out433_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(194) = '1' then
if rtmcmp194 = '1' then
-- Next state
state_next(193) <= '1';
-- Next values for buffered outputs
out351_bufn <= '1';
out313_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(194) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out263_bufn <= '1';
out531_bufn <= '1';
out497_bufn <= '1';
out521_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out528 <= '1';
end if;
if state_cur(195) = '1' then
-- Next state
state_next(194) <= '1';
-- Next values for buffered outputs
out263_bufn <= '1';
out531_bufn <= '1';
out497_bufn <= '1';
out521_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(196) = '1' then
-- Next state
state_next(221) <= '1';
-- Next values for buffered outputs
out281_bufn <= '1';
-- Assignment of non-buffered outputs
out130 <= '1';
out540 <= '1';
out286 <= '1';
end if;
if state_cur(197) = '1' then
if rtmcmp197 = '1' then
-- Next state
state_next(195) <= '1';
-- Next values for buffered outputs
out394_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out137 <= '1';
out125 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(197) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out500_bufn <= '1';
out435_bufn <= '1';
out314_bufn <= '1';
out293_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out542 <= '1';
end if;
if state_cur(198) = '1' then
-- Next state
state_next(197) <= '1';
-- Next values for buffered outputs
out500_bufn <= '1';
out435_bufn <= '1';
out314_bufn <= '1';
out293_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(199) = '1' then
-- Next state
state_next(198) <= '1';
-- Next values for buffered outputs
out326_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(200) = '1' then
-- Next state
state_next(199) <= '1';
-- Next values for buffered outputs
out341_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(201) = '1' then
-- Next state
state_next(200) <= '1';
-- Next values for buffered outputs
out287_bufn <= '1';
out285_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out544 <= '1';
out42 <= '1';
out283 <= '1';
end if;
if state_cur(202) = '1' then
-- Next state
state_next(201) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out318_bufn <= '1';
out322_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(203) = '1' then
if rtmcmp203 = '1' then
-- Next state
state_next(202) <= '1';
-- Next values for buffered outputs
out483_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out142 <= '1';
out112 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(203) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out393_bufn <= '1';
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out518_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out545 <= '1';
end if;
if state_cur(204) = '1' then
-- Next state
state_next(203) <= '1';
-- Next values for buffered outputs
out393_bufn <= '1';
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out518_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(205) = '1' then
if rtmcmp205 = '1' then
-- Next state
state_next(204) <= '1';
-- Next values for buffered outputs
out554_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out137 <= '1';
out125 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(205) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out531_bufn <= '1';
out426_bufn <= '1';
out461_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out555 <= '1';
end if;
if state_cur(206) = '1' then
-- Next state
state_next(205) <= '1';
-- Next values for buffered outputs
out531_bufn <= '1';
out426_bufn <= '1';
out461_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(207) = '1' then
-- Next state
state_next(206) <= '1';
-- Next values for buffered outputs
out526_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(208) = '1' then
-- Next state
state_next(207) <= '1';
-- Next values for buffered outputs
out525_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(209) = '1' then
-- Next state
state_next(208) <= '1';
-- Next values for buffered outputs
out466_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out559 <= '1';
out40 <= '1';
out283 <= '1';
end if;
if state_cur(210) = '1' then
-- Next state
state_next(209) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out417_bufn <= '1';
out294_bufn <= '1';
out282_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(211) = '1' then
-- Next state
state_next(224) <= '1';
-- Next values for buffered outputs
out459_bufn <= '1';
out284_bufn <= '1';
out201_bufn <= '1';
-- Assignment of non-buffered outputs
out560 <= '1';
out286 <= '1';
end if;
if state_cur(212) = '1' then
-- Next state
state_next(147) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out561 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(213) = '1' then
-- Next state
state_next(134) <= '1';
-- Next values for buffered outputs
out433_bufn <= '1';
out281_bufn <= '1';
out426_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(214) = '1' then
-- Next state
state_next(140) <= '1';
-- Next values for buffered outputs
out351_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(215) = '1' then
if rtmcmp215 = '1' then
-- Next state
state_next(127) <= '1';
-- Next values for buffered outputs
out404_bufn <= '1';
out418_bufn <= '1';
out281_bufn <= '1';
out417_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out123 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(215) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out562_bufn <= '1';
out342_bufn <= '1';
out284_bufn <= '1';
out404_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out563 <= '1';
end if;
if state_cur(216) = '1' then
-- Next state
state_next(214) <= '1';
-- Next values for buffered outputs
out482_bufn <= '1';
out481_bufn <= '1';
out357_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(217) = '1' then
-- Next state
state_next(216) <= '1';
-- Next values for buffered outputs
out444_bufn <= '1';
out281_bufn <= '1';
out354_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(218) = '1' then
-- Next state
state_next(217) <= '1';
-- Next values for buffered outputs
out566_bufn <= '1';
out281_bufn <= '1';
out229_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(219) = '1' then
-- Next state
state_next(218) <= '1';
-- Next values for buffered outputs
out440_bufn <= '1';
out281_bufn <= '1';
out162_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(220) = '1' then
-- Next state
state_next(219) <= '1';
-- Next values for buffered outputs
out349_bufn <= '1';
out284_bufn <= '1';
out257_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(221) = '1' then
-- Next state
state_next(223) <= '1';
-- Next values for buffered outputs
out325_bufn <= '1';
out284_bufn <= '1';
out366_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out567 <= '1';
out283 <= '1';
end if;
if state_cur(222) = '1' then
-- Next state
state_next(220) <= '1';
-- Next values for buffered outputs
out464_bufn <= '1';
out281_bufn <= '1';
out451_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(223) = '1' then
-- Next state
state_next(161) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out414_bufn <= '1';
out446_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
out286 <= '1';
end if;
if state_cur(224) = '1' then
-- Next state
state_next(222) <= '1';
-- Next values for buffered outputs
out460_bufn <= '1';
out281_bufn <= '1';
out232_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(225) = '1' then
-- Next state
state_next(79) <= '1';
-- Next values for buffered outputs
out282_bufn <= '1';
out281_bufn <= '1';
out280_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(226) = '1' then
-- Next state
state_next(122) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out570 <= '1';
out412 <= '1';
end if;
if state_cur(227) = '1' then
-- Next state
state_next(116) <= '1';
-- Next values for buffered outputs
out400_bufn <= '1';
out284_bufn <= '1';
out131_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(228) = '1' then
-- Next state
state_next(136) <= '1';
-- Next values for buffered outputs
out428_bufn <= '1';
out284_bufn <= '1';
out126_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(229) = '1' then
-- Next state
state_next(138) <= '1';
-- Next values for buffered outputs
out437_bufn <= '1';
out281_bufn <= '1';
out235_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(230) = '1' then
-- Next state
state_next(231) <= '1';
-- Next values for buffered outputs
out499_bufn <= '1';
out281_bufn <= '1';
out497_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(231) = '1' then
-- Next state
state_next(155) <= '1';
-- Next values for buffered outputs
out457_bufn <= '1';
out284_bufn <= '1';
out364_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(232) = '1' then
-- Next state
state_next(213) <= '1';
-- Next values for buffered outputs
out524_bufn <= '1';
out281_bufn <= '1';
out238_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(233) = '1' then
-- Next state
state_next(141) <= '1';
-- Next values for buffered outputs
out440_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out283 <= '1';
end if;
if state_cur(234) = '1' then
-- Next state
state_next(129) <= '1';
-- Next values for buffered outputs
out346_bufn <= '1';
out31_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out572 <= '1';
out412 <= '1';
end if;
if state_cur(235) = '1' then
-- Next state
state_next(131) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out575 <= '1';
out363 <= '1';
end if;
if state_cur(236) = '1' then
-- Next state
state_next(234) <= '1';
-- Next values for buffered outputs
out280_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out577 <= '1';
out40 <= '1';
out21 <= '1';
out412 <= '1';
end if;
if state_cur(237) = '1' then
-- Next state
state_next(235) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out578 <= '1';
out363 <= '1';
end if;
if state_cur(238) = '1' then
-- Next state
state_next(236) <= '1';
-- Next values for buffered outputs
out562_bufn <= '1';
out35_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out580 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(239) = '1' then
-- Next state
state_next(238) <= '1';
-- Next values for buffered outputs
out446_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(240) = '1' then
-- Next state
state_next(165) <= '1';
-- Next values for buffered outputs
out466_bufn <= '1';
out284_bufn <= '1';
out273_bufn <= '1';
-- Assignment of non-buffered outputs
out581 <= '1';
out130 <= '1';
out283 <= '1';
end if;
-- Reset input
if reset = '1' then
-- Set the reset state
state_next <= (7 => '1', others => '0');
-- Note: Resetting all buffers for outputs here is not necessary.
-- It would cost hardware. They will be reset at the next clock front.
-- Retiming: counters
rtmcounter0_next <= (others => '0');
-- Reset state: set the buffered outputs
end if;
end process;
-- Assignment of buffered outputs
out122 <= out122_buf;
out36 <= out36_buf;
out49 <= out49_buf;
out35 <= out35_buf;
out27 <= out27_buf;
out16 <= out16_buf;
out25 <= out25_buf;
out20 <= out20_buf;
out57 <= out57_buf;
out23 <= out23_buf;
out136 <= out136_buf;
out0 <= out0_buf;
out134 <= out134_buf;
out13 <= out13_buf;
out131 <= out131_buf;
out129 <= out129_buf;
out111 <= out111_buf;
out31 <= out31_buf;
out126 <= out126_buf;
out106 <= out106_buf;
out124 <= out124_buf;
out138 <= out138_buf;
out141 <= out141_buf;
out143 <= out143_buf;
out146 <= out146_buf;
out150 <= out150_buf;
out153 <= out153_buf;
out155 <= out155_buf;
out158 <= out158_buf;
out162 <= out162_buf;
out165 <= out165_buf;
out168 <= out168_buf;
out171 <= out171_buf;
out174 <= out174_buf;
out178 <= out178_buf;
out181 <= out181_buf;
out183 <= out183_buf;
out197 <= out197_buf;
out201 <= out201_buf;
out204 <= out204_buf;
out207 <= out207_buf;
out210 <= out210_buf;
out213 <= out213_buf;
out217 <= out217_buf;
out220 <= out220_buf;
out222 <= out222_buf;
out225 <= out225_buf;
out229 <= out229_buf;
out232 <= out232_buf;
out235 <= out235_buf;
out238 <= out238_buf;
out241 <= out241_buf;
out245 <= out245_buf;
out248 <= out248_buf;
out250 <= out250_buf;
out253 <= out253_buf;
out257 <= out257_buf;
out260 <= out260_buf;
out263 <= out263_buf;
out266 <= out266_buf;
out269 <= out269_buf;
out273 <= out273_buf;
out276 <= out276_buf;
out278 <= out278_buf;
out280 <= out280_buf;
out281 <= out281_buf;
out282 <= out282_buf;
out284 <= out284_buf;
out285 <= out285_buf;
out287 <= out287_buf;
out288 <= out288_buf;
out289 <= out289_buf;
out290 <= out290_buf;
out291 <= out291_buf;
out292 <= out292_buf;
out293 <= out293_buf;
out294 <= out294_buf;
out295 <= out295_buf;
out296 <= out296_buf;
out312 <= out312_buf;
out313 <= out313_buf;
out314 <= out314_buf;
out315 <= out315_buf;
out318 <= out318_buf;
out322 <= out322_buf;
out323 <= out323_buf;
out324 <= out324_buf;
out325 <= out325_buf;
out326 <= out326_buf;
out327 <= out327_buf;
out328 <= out328_buf;
out333 <= out333_buf;
out341 <= out341_buf;
out342 <= out342_buf;
out343 <= out343_buf;
out344 <= out344_buf;
out346 <= out346_buf;
out349 <= out349_buf;
out351 <= out351_buf;
out352 <= out352_buf;
out353 <= out353_buf;
out354 <= out354_buf;
out357 <= out357_buf;
out361 <= out361_buf;
out364 <= out364_buf;
out366 <= out366_buf;
out371 <= out371_buf;
out393 <= out393_buf;
out394 <= out394_buf;
out395 <= out395_buf;
out400 <= out400_buf;
out401 <= out401_buf;
out404 <= out404_buf;
out407 <= out407_buf;
out408 <= out408_buf;
out409 <= out409_buf;
out410 <= out410_buf;
out413 <= out413_buf;
out414 <= out414_buf;
out417 <= out417_buf;
out418 <= out418_buf;
out422 <= out422_buf;
out426 <= out426_buf;
out428 <= out428_buf;
out431 <= out431_buf;
out433 <= out433_buf;
out434 <= out434_buf;
out435 <= out435_buf;
out436 <= out436_buf;
out437 <= out437_buf;
out438 <= out438_buf;
out440 <= out440_buf;
out444 <= out444_buf;
out446 <= out446_buf;
out451 <= out451_buf;
out457 <= out457_buf;
out458 <= out458_buf;
out459 <= out459_buf;
out460 <= out460_buf;
out461 <= out461_buf;
out463 <= out463_buf;
out464 <= out464_buf;
out466 <= out466_buf;
out468 <= out468_buf;
out472 <= out472_buf;
out475 <= out475_buf;
out481 <= out481_buf;
out482 <= out482_buf;
out483 <= out483_buf;
out487 <= out487_buf;
out495 <= out495_buf;
out496 <= out496_buf;
out497 <= out497_buf;
out499 <= out499_buf;
out500 <= out500_buf;
out512 <= out512_buf;
out517 <= out517_buf;
out518 <= out518_buf;
out521 <= out521_buf;
out524 <= out524_buf;
out525 <= out525_buf;
out526 <= out526_buf;
out531 <= out531_buf;
out554 <= out554_buf;
out562 <= out562_buf;
out566 <= out566_buf;
-- Retiming: the comparators
rtmcmp90 <= '1' when state_cur(90) = '1' and rtmcounter0 = 1 else '0';
rtmcmp95 <= '1' when state_cur(95) = '1' and rtmcounter0 = 1 else '0';
rtmcmp98 <= '1' when state_cur(98) = '1' and rtmcounter0 = 1 else '0';
rtmcmp104 <= '1' when state_cur(104) = '1' and rtmcounter0 = 1 else '0';
rtmcmp148 <= '1' when state_cur(148) = '1' and rtmcounter0 = 1 else '0';
rtmcmp167 <= '1' when state_cur(167) = '1' and rtmcounter0 = 1 else '0';
rtmcmp174 <= '1' when state_cur(174) = '1' and rtmcounter0 = 1 else '0';
rtmcmp181 <= '1' when state_cur(181) = '1' and rtmcounter0 = 1 else '0';
rtmcmp183 <= '1' when state_cur(183) = '1' and rtmcounter0 = 1 else '0';
rtmcmp194 <= '1' when state_cur(194) = '1' and rtmcounter0 = 1 else '0';
rtmcmp197 <= '1' when state_cur(197) = '1' and rtmcounter0 = 1 else '0';
rtmcmp203 <= '1' when state_cur(203) = '1' and rtmcounter0 = 1 else '0';
rtmcmp205 <= '1' when state_cur(205) = '1' and rtmcounter0 = 1 else '0';
rtmcmp215 <= '1' when state_cur(215) = '1' and rtmcounter0 = 1 else '0';
end architecture;
| gpl-2.0 | d02335c1dcb37b475406ef35e60e822c | 0.567782 | 2.636953 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_basic_wrap.vhd | 3 | 50,383 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_10;
use axi_datamover_v5_1_10.axi_datamover_reset;
use axi_datamover_v5_1_10.axi_datamover_cmd_status;
use axi_datamover_v5_1_10.axi_datamover_scc;
use axi_datamover_v5_1_10.axi_datamover_addr_cntl;
use axi_datamover_v5_1_10.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_10.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_10.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_10.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_10.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_10.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_10.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_10.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_10.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_10.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_10.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
| gpl-3.0 | 221035ae8f71b3189d959eb0d262810c | 0.443205 | 4.13382 | false | false | false | false |
DE5Amigos/SylvesterTheDE2Bot | DE2Botv3Fall16Main/acc_clk_gen.vhd | 1 | 2,974 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- This is an improved version of the ACC_CLK_GEN provided for Lab 8.
ENTITY ACC_CLK_GEN IS
PORT
(
clock_25Mhz : IN STD_LOGIC;
clock_12500KHz : OUT STD_LOGIC;
clock_400KHz : OUT STD_LOGIC;
clock_170KHz : OUT STD_LOGIC;
clock_10KHz : OUT STD_LOGIC;
clock_100Hz : OUT STD_LOGIC;
clock_32Hz : OUT STD_LOGIC;
clock_10Hz : OUT STD_LOGIC;
clock_4Hz : OUT STD_LOGIC
);
END ACC_CLK_GEN;
ARCHITECTURE a OF ACC_CLK_GEN IS
SIGNAL count_400Khz : INTEGER RANGE 0 TO 12500000/400000;
SIGNAL count_170Khz : INTEGER RANGE 0 TO 12500000/170000;
SIGNAL count_10Khz : INTEGER RANGE 0 TO 12500000/10000;
SIGNAL count_100hz : INTEGER RANGE 0 TO 12500000/100;
SIGNAL count_32hz : INTEGER RANGE 0 TO 12500000/32;
SIGNAL count_10hz : INTEGER RANGE 0 TO 12500000/10;
SIGNAL count_4hz : INTEGER RANGE 0 TO 12500000/4;
SIGNAL clock_12500KHz_int : STD_LOGIC;
SIGNAL clock_400Khz_int : STD_LOGIC;
SIGNAL clock_170Khz_int : STD_LOGIC;
SIGNAL clock_10Khz_int : STD_LOGIC;
SIGNAL clock_100hz_int : STD_LOGIC;
SIGNAL clock_32hz_int : STD_LOGIC;
SIGNAL clock_10hz_int : STD_LOGIC;
SIGNAL clock_4hz_int : STD_LOGIC;
BEGIN
PROCESS
BEGIN
WAIT UNTIL RISING_EDGE(clock_25Mhz);
clock_12500KHz <= clock_12500KHz_int;
clock_400Khz <= clock_400Khz_int;
clock_170Khz <= clock_170Khz_int;
clock_10Khz <= clock_10Khz_int;
clock_100hz <= clock_100hz_int;
clock_32hz <= clock_32hz_int;
clock_10hz <= clock_10hz_int;
clock_4hz <= clock_4hz_int;
clock_12500KHz_int <= NOT(clock_12500KHz_int);
--
IF count_400Khz < (12500000/400000-1) THEN
count_400Khz <= count_400Khz + 1;
ELSE
count_400Khz <= 0;
clock_400Khz_int <= NOT(clock_400Khz_int);
END IF;
--
IF count_170Khz < (12500000/170000-1) THEN
count_170Khz <= count_170Khz + 1;
ELSE
count_170Khz <= 0;
clock_170Khz_int <= NOT(clock_170Khz_int);
END IF;
--
IF count_10Khz < (12500000/10000-1) THEN
count_10Khz <= count_10Khz + 1;
ELSE
count_10Khz <= 0;
clock_10Khz_int <= NOT(clock_10Khz_int);
END IF;
--
IF count_100hz < (12500000/100-1) THEN
count_100hz <= count_100hz + 1;
ELSE
count_100hz <= 0;
clock_100hz_int <= NOT(clock_100hz_int);
END IF;
--
IF count_32hz < (12500000/32-1) THEN
count_32hz <= count_32hz + 1;
ELSE
count_32hz <= 0;
clock_32hz_int <= NOT(clock_32hz_int);
END IF;
--
IF count_10hz < (12500000/10-1) THEN
count_10hz <= count_10hz + 1;
ELSE
count_10hz <= 0;
clock_10hz_int <= NOT(clock_10hz_int);
END IF;
--
IF count_4hz < (12500000/4-1) THEN
count_4hz <= count_4hz + 1;
ELSE
count_4hz <= 0;
clock_4hz_int <= NOT(clock_4hz_int);
END IF;
--
END PROCESS;
END a;
| mit | a1edaa82e9dfc256e8ba6d5c97dc8849 | 0.623403 | 2.67446 | false | false | false | false |
nickg/nvc | test/sem/real.vhd | 1 | 1,114 | entity e is
end entity;
architecture a of e is
signal x : real := 1.234; -- OK
type my_real is range 0.0 to 1.0; -- OK
begin
process is
variable v : my_real;
begin
x <= x + 6.1215; -- OK
x <= v; -- Error
end process;
process is
variable i : integer;
begin
i := integer(x); -- OK
x <= real(i); -- OK
x <= real(5); -- OK
x <= real(bit'('1')); -- Error
end process;
process is
variable x : real;
begin
x := real'left; -- OK
x := real'right; -- OK
end process;
process is
constant i : integer := 5;
constant r : real := 252.4;
type t is range r to i; -- Error
type t2 is range i to r; -- Error
begin
end process;
process is
variable t : time;
variable r : real;
begin
r := (t / 1 ps) * 1.0; -- OK
end process;
end architecture;
| gpl-3.0 | 955a535097a402d33b95f75cb10f87a0 | 0.40754 | 4.080586 | false | false | false | false |
tgingold/ghdl | testsuite/synth/arr01/tb_arr04.vhdl | 1 | 981 | entity tb_arr04 is
end tb_arr04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr04 is
signal clk : std_logic;
signal rst : std_logic;
signal sel_i : std_logic;
signal sel_o : std_logic;
signal v : std_logic;
signal r : std_logic;
begin
dut: entity work.arr04
port map (clk => clk, rst => rst, sel_i => sel_i, sel_o => sel_o,
v => v, res => r);
process
constant siv : std_logic_vector := b"0010";
constant sov : std_logic_vector := b"0101";
constant v_v : std_logic_vector := b"0011";
constant r_v : std_logic_vector := b"0001";
begin
clk <= '0';
rst <= '1';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
rst <= '0';
for i in siv'range loop
sel_i <= siv (i);
sel_o <= sov (i);
v <= v_v (i);
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert r = r_v(i) severity failure;
end loop;
wait;
end process;
end behav;
| gpl-2.0 | 4c5bb799b59c9dd473458b3b34aac1a8 | 0.546381 | 2.954819 | false | false | false | false |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_dc_dhuff_tbl_ml.vhd | 2 | 1,405 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_dhuff_tbl_ml is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic;
clk : in std_logic;
ra0_addr : in std_logic;
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_dhuff_tbl_ml;
architecture augh of p_jinfo_dc_dhuff_tbl_ml is
-- Embedded RAM
type ram_type is array (0 to 1) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 | 749c5560a9ff056109e099d3b3953824 | 0.671174 | 2.832661 | false | false | false | false |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/ip/tmp.srcs/sources_1/ip/doHistStretch_ap_fmul_2_max_dsp_32/synth/doHistStretch_ap_fmul_2_max_dsp_32.vhd | 3 | 12,806 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
| gpl-3.0 | 2a5b906da936252bbb4e344771a4c8a3 | 0.65196 | 3.025278 | false | false | false | false |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_03.vhd | 4 | 1,649 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_tb_05_03.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity tb_05_03 is
end entity tb_05_03;
architecture test of tb_05_03 is
signal D, clk, clr, Q : bit := '0';
begin
dut : entity work.edge_triggered_Dff(behavioral)
port map ( D => D, clk => clk, clr => clr,
Q => Q );
stimulus : process is
begin
D <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
D <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
D <= '1'; wait for 10 ns;
clr <= '1'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
clr <= '0'; wait for 10 ns;
clk <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 | 6805d8a5c024fb676f8b344986be2a95 | 0.591267 | 3.600437 | false | true | false | false |
tgingold/ghdl | testsuite/synth/issue1273/assert6.vhdl | 1 | 493 | library ieee;
use ieee.std_logic_1164.all;
entity assert6 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
clk : std_logic;
rst : std_logic;
res : out std_logic);
end;
architecture behav of assert6 is
begin
process (clk, rst)
begin
if rst = '1' then
res <= '0';
elsif rising_edge(clk) and en = '1' then
assert v /= x"05";
res <= v(0) xor v(1);
else
assert v = x"00";
end if;
end process;
end behav;
| gpl-2.0 | 3211f68658d598da630e8f4039ee975c | 0.555781 | 3.100629 | false | false | false | false |
lfmunoz/vhdl | clock_domain_crossing/sync_block.vhd | 1 | 4,842 | --////////////////////////////////////////////////////////////////////////////////
--// ____ ____
--// / /\/ /
--// /___/ \ / Vendor: Xilinx
--// \ \ \/ Version : 2.6
--// \ \ Application : 7 Series FPGAs Transceivers Wizard
--// / / Filename :v7_adc16dx370_sync_block.vhd
--// /___/ /\
--// \ \ / \
--// \___\/\___\
--//
--//
--
-- Description: Used on signals crossing from one clock domain to
-- another, this is a flip-flop pair, with both flops
-- placed together with RLOCs into the same slice. Thus
-- the routing delay between the two is minimum to safe-
-- guard against metastability issues.
--
--
-- Module v7_adc16dx370_sync_block
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity sync_block is
generic (
INITIALISE : bit_vector(1 downto 0) := "00"
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end sync_block;
architecture structural of sync_block is
-- Internal Signals
signal data_sync1 : std_logic;
-- These attributes will stop Vivado translating the desired flip-flops into an
-- SRL based shift register.
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync : label is "TRUE";
attribute ASYNC_REG of data_sync_reg : label is "TRUE";
-- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
attribute MSGON : string;
attribute MSGON of data_sync : label is "FALSE";
attribute MSGON of data_sync_reg : label is "FALSE";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
attribute shreg_extract of data_sync : label is "no";
attribute shreg_extract of data_sync_reg : label is "no";
begin
data_sync : FD
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
D => data_in,
Q => data_sync1
);
data_sync_reg : FD
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
D => data_sync1,
Q => data_out
);
end structural;
| mit | e855ed556d34d0fcedb9eefeb13f623b | 0.638166 | 4.206777 | false | false | false | false |
dtysky/Led_Array | VHDL_TEST/PLL.vhd | 1 | 15,103 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: PLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY PLL IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END PLL;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=PLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| gpl-2.0 | d1d2952736eb42f53ee50d588a1d33a7 | 0.698471 | 3.354731 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/components.vhd | 1 | 9,893 | -------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
-- Copyright 2011 - 2012
--
-- Email: [email protected]
--
-- License: LGPL
--
-- If you would like a version with a different license for use
-- in commercial projects please contact the above email address
-- for more details.
-------------------------------------------------------------------
--
-- Copyright (C) 2011 - 2012 Ultra-Embedded.com
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package peripherals is
-------------------------------------------------------------------
-- Components:
-------------------------------------------------------------------
component mpx
generic
(
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
);
port
(
-- General
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
intr_i : in std_logic;
step_done_o : out std_logic;
fault_o : out std_logic;
-- Data Memory
mem_addr_o : out std_logic_vector(31 downto 0);
mem_data_out_o : out std_logic_vector(31 downto 0);
mem_data_in_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic_vector(3 downto 0);
mem_rd_o : out std_logic;
mem_pause_i : in std_logic;
-- Debug Register Access
dbg_reg_addr_i : in std_logic_vector(8 downto 0);
dbg_reg_out_o : out std_logic_vector(31 downto 0);
dbg_pc_o : out std_logic_vector(31 downto 0)
);
end component;
component mpx_soc
generic
(
CLK_KHZ : integer := 12288;
UART_BAUD : integer := 115200;
EXTERNAL_INTERRUPTS : integer := 1;
CORE_ID : std_logic_vector := X"00000000";
BOOT_VECTOR : std_logic_vector := X"00000000";
ISR_VECTOR : std_logic_vector := X"0000003C"
);
port
(
-- General - clocking & rst_i
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
ext_intr_i : in std_logic_vector(EXTERNAL_INTERRUPTS-1 downto 0);
fault_o : out std_logic;
-- UART
uart_tx_o : out std_logic;
uart_rx_i : in std_logic;
-- BootRAM
int_mem_addr_o : out std_logic_vector(32-1 downto 0);
int_mem_data_o : out std_logic_vector(32-1 downto 0);
int_mem_data_i : in std_logic_vector(32-1 downto 0);
int_mem_wr_o : out std_logic_vector(3 downto 0);
int_mem_rd_o : out std_logic;
-- External Memory
ext_mem_addr_o : out std_logic_vector(32-1 downto 0);
ext_mem_data_o : out std_logic_vector(32-1 downto 0);
ext_mem_data_i : in std_logic_vector(32-1 downto 0);
ext_mem_wr_o : out std_logic_vector(3 downto 0);
ext_mem_rd_o : out std_logic;
ext_mem_pause_i : in std_logic;
-- External IO
ext_io_addr_o : out std_logic_vector(32-1 downto 0);
ext_io_data_o : out std_logic_vector(32-1 downto 0);
ext_io_data_i : in std_logic_vector(32-1 downto 0);
ext_io_wr_o : out std_logic_vector(3 downto 0);
ext_io_rd_o : out std_logic;
ext_io_pause_i : in std_logic;
-- External Shared / DP-RAM
ext_dpram_addr_o : out std_logic_vector(32-1 downto 0);
ext_dpram_data_o : out std_logic_vector(32-1 downto 0);
ext_dpram_data_i : in std_logic_vector(32-1 downto 0);
ext_dpram_wr_o : out std_logic_vector(3 downto 0);
ext_dpram_rd_o : out std_logic;
ext_dpram_pause_i : in std_logic;
-- SPI Flash
flash_cs_o : out std_logic;
flash_si_o : out std_logic;
flash_so_i : in std_logic;
flash_sck_o : out std_logic;
-- Debug Register Access
dbg_reg_addr_i : in std_logic_vector(8 downto 0);
dbg_reg_out_o : out std_logic_vector(31 downto 0);
dbg_pc_o : out std_logic_vector(31 downto 0);
-- Debug UART Output
dbg_uart_data_o : out std_logic_vector(7 downto 0);
dbg_uart_wr_o : out std_logic
);
end component;
component asram16_if
generic
(
EXT_ADDR_WIDTH : integer := 17
);
port
(
-- General
clk_i: in std_logic;
rst_i: in std_logic;
timing_ctrl_i : in std_logic_vector(32-1 downto 0);
-- Asynchronous SRAM interface
sram_address_o: out std_logic_vector(EXT_ADDR_WIDTH-1 downto 0);
sram_data_o : out std_logic_vector(16-1 downto 0);
sram_data_i : in std_logic_vector(16-1 downto 0);
sram_oe_o : out std_logic;
sram_cs_o : out std_logic;
sram_be_o : out std_logic_vector(2-1 downto 0);
sram_we_o : out std_logic;
sram_dir_out_o: out std_logic;
-- Internal access
address_i : in std_logic_vector(32-1 downto 0);
data_i : in std_logic_vector(32-1 downto 0);
data_o : out std_logic_vector(32-1 downto 0);
rd_i : in std_logic;
wr_i : in std_logic_vector(4-1 downto 0);
ack_o : out std_logic;
busy_o : out std_logic
);
end component;
component uart
generic
(
DIVISOR : integer := 278
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
--
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
tx_avail_o : out std_logic;
tx_busy_o : out std_logic;
rx_avail_o : out std_logic;
rx_full_o : out std_logic;
rx_error_o : out std_logic;
--
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic
);
end component;
component spi_master
generic
(
-- Clock Divider
CLK_DIV : integer := 32;
-- Transfer Width
TRANSFER_WIDTH : integer := 8
);
port
(
-- Clocking / Reset
clk_i : in std_logic;
rst_i : in std_logic;
-- Control & Status
start_i : in std_logic;
done_o : out std_logic;
busy_o : out std_logic;
-- Data
data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
-- SPI interface
spi_clk_o : out std_logic;
spi_ss_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component;
component spi_ctrl
generic
(
MEM_ADDR_WIDTH : natural := 18;
XFER_COUNT_WIDTH : natural := 32;
TRANSFER_WIDTH : natural := 8
);
port
(
-- General
clk_i: in std_logic;
rst_i: in std_logic;
-- Memory interface
mem_address_o: out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
mem_data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_rd_o : out std_logic;
mem_wr_o : out std_logic;
-- SPI Access
spi_start_o : out std_logic;
spi_done_i : in std_logic;
spi_busy_i : in std_logic;
spi_data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
spi_data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
-- Control
xfer_count_i : in std_logic_vector(XFER_COUNT_WIDTH-1 downto 0);
xfer_address_i: in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
xfer_start_i : in std_logic;
xfer_rx_only_i: in std_logic;
xfer_done_o : out std_logic;
xfer_busy_o : out std_logic
);
end component;
component spi_dma_ext
generic
(
MEM_ADDR_WIDTH : natural := 18;
XFER_COUNT_WIDTH : natural := 32;
SPI_CLK_DIV : natural := 4;
TRANSFER_WIDTH : natural := 8
);
port
(
-- General
clk_i: in std_logic;
rst_i: in std_logic;
-- SPI Interface
spi_clk_o : out std_logic;
spi_ss_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-- Memory interface
mem_address_o: out std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
mem_data_o : out std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_data_i : in std_logic_vector(TRANSFER_WIDTH-1 downto 0);
mem_rd_o : out std_logic;
mem_wr_o : out std_logic;
-- Control
xfer_count_i : in std_logic_vector(XFER_COUNT_WIDTH-1 downto 0);
xfer_address_i: in std_logic_vector(MEM_ADDR_WIDTH-1 downto 0);
xfer_start_i : in std_logic;
xfer_rx_only_i: in std_logic;
xfer_done_o : out std_logic;
xfer_busy_o : out std_logic
);
end component;
component i2s
generic
(
CLK_DIVISOR : integer := 6
);
port (
-- General
clk_i : in std_logic;
rst_i : in std_logic;
-- Audio PCM input (2x16-bit LE signed data)
pcm_data_i : in std_logic_vector(32-1 downto 0);
pcm_fifo_empty_i: in std_logic;
pcm_fifo_rd_o : out std_logic;
pcm_fifo_ur_o : out std_logic;
-- I2S output
bclk_o : out std_logic;
ws_o : out std_logic;
data_o : out std_logic
);
end component;
end peripherals;
package body peripherals is
end; --package body
| mit | 2b0b5b50ed077c0aa92632fabf9b8eec | 0.596179 | 2.75571 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/register16.vhd | 1 | 2,605 | ----------------------------------------------------------------------------------
-- Company: Nibble Knowledge
-- Engineer: Colton Schmidt
--
-- Create Date: 10:22:00 10/18/2015
-- Design Name:
-- Module Name: register16 - Behavioral
-- Project Name:
-- Target Devices: CPU
-- Tool versions:
-- Description: Loads 16 bit register 1 nibble at a time every clock edge
-- while the load signal is high. The the most significant nibble must be
-- sent first and the least significant nibble las as shown below:
--
-- MSB LSB
-- 16 bits to be stored: 1111 1111 1111 1111
-- Sending Order: Nibble3 Nibble2 Nibble1 Nibble0
-- Dependencies:
--
-- Revision: 0.1
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity register16 is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC);
end register16;
architecture Behavioral of register16 is
-- Intermediate Signals --
signal i_nibbleCount : STD_LOGIC_VECTOR (1 downto 0);
begin
process( clk, reset )
begin
if reset = '1' then
i_nibbleCount <= "11";
q <= (others => '0');
elsif rising_edge(clk) then
if load = '1' then
-- Load Nibble 3 --
if i_nibbleCount = "11" then
q(15) <= d(3);
q(14) <= d(2);
q(13) <= d(1);
q(12) <= d(0);
-- Load Nibble 2 --
elsif i_nibbleCount = "10" then
q(11) <= d(3);
q(10) <= d(2);
q(9) <= d(1);
q(8) <= d(0);
-- Load Nibble 1 --
elsif i_nibbleCount = "01" then
q(7) <= d(3);
q(6) <= d(2);
q(5) <= d(1);
q(4) <= d(0);
-- Load Nibble 0 --
elsif i_nibbleCount = "00" then
q(3) <= d(3);
q(2) <= d(2);
q(1) <= d(1);
q(0) <= d(0);
end if;
if i_nibbleCount = "00" then
i_nibbleCount <= "11";
else
i_nibbleCount <= i_nibbleCount - '1';
end if;
end if;
end if;
end process;
end Behavioral;
| unlicense | 5f0427eeae0f1e1595053b48a57126d3 | 0.524376 | 3.268507 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration.vhd | 1 | 75,248 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration.vhd
-- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:38 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for MCB Soft
-- Calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
-- correctly)
-- 1.2: 2/12/09: Many other changes.
-- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
-- STATE
-- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
-- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
-- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
-- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
-- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
-- RST_DELAY.
-- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
-- 16 clocks. Added PNSKEW option.
-- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
-- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
-- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
-- with 8bit TARGET_DQS_DELAY which
-- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
-- Changed DQS_COUNT* to DQS_DELAY*.
-- Changed MCB_SYSRST port back to wire (from reg).
-- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
-- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
-- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
-- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
-- 3.4: 03/04/10: Recoded the RST_Reg logic.
-- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
-- 3.6 03/10/10: Improvements to Reset logic.
-- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
-- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end entity mcb_soft_calibration;
architecture trans of mcb_soft_calibration is
constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
constant START : std_logic_vector(5 downto 0) := "000000";
constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
constant SKEW : std_logic_vector(5 downto 0) := "001100";
constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "010010";
constant WAIT7 : std_logic_vector(5 downto 0) := "010011";
constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "010100";
constant WAIT8 : std_logic_vector(5 downto 0) := "010101";
constant RST_DELAY : std_logic_vector(5 downto 0) := "010110";
constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "010111";
constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "011000";
constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "011001";
constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "011010";
constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "011011";
constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "011100";
constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "011101";
constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "011110";
constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "011111";
constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "100000";
constant START_DYN_CAL : std_logic_vector(5 downto 0) := "100001";
constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "100010";
constant WAIT9 : std_logic_vector(5 downto 0) := "100011";
constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "100100";
constant WAIT10 : std_logic_vector(5 downto 0) := "100101";
constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "100110";
constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "100111";
constant INCREMENT : std_logic_vector(5 downto 0) := "101000";
constant DECREMENT : std_logic_vector(5 downto 0) := "101001";
constant DONE : std_logic_vector(5 downto 0) := "101010";
constant RZQ : std_logic_vector(1 downto 0) := "00";
constant ZIO : std_logic_vector(1 downto 0) := "01";
constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
constant WRITE_MODE : std_logic := '0';
constant READ_MODE : std_logic := '1';
-- IOI Registers
constant NoOp : std_logic_vector(7 downto 0) := "00000000";
constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-- IOB Registers
constant PDrive : std_logic_vector(7 downto 0) := "10000000";
constant PTerm : std_logic_vector(7 downto 0) := "10000001";
constant NDrive : std_logic_vector(7 downto 0) := "10000010";
constant NTerm : std_logic_vector(7 downto 0) := "10000011";
constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
constant InputControl : std_logic_vector(7 downto 0) := "10000111";
constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-- No multi/divide is required when a 55 ohm resister is used on RZQ
-- localparam MULT = 1;
-- localparam DIV = 1;
-- use 7/4 scaling factor when the 100 ohm RZQ is used
constant MULT : integer := 7;
constant DIV : integer := 4;
constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
constant PSKEW_MULT : integer := 9;
constant PSKEW_DIV : integer := 8;
constant NSKEW_MULT : integer := 7;
constant NSKEW_DIV : integer := 8;
constant DQS_NUMERATOR : integer := 3;
constant DQS_DENOMINATOR : integer := 8;
constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
-- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
-- 3 for three eighths
constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := C_MEM_TZQINIT_MAXCNT + RST_CNT;
constant IN_TERM_PASS : std_logic := '0';
constant DYN_CAL_PASS : std_logic := '1';
component iodrp_mcb_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end component;
component iodrp_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end component;
signal P_Term : std_logic_vector(5 downto 0) := "000000";
signal N_Term : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
signal STATE : std_logic_vector(5 downto 0) := START;
signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
signal Active_IODRP : std_logic_vector(1 downto 0);
signal IODRPCTRLR_R_WB : std_logic := '0';
signal IODRPCTRLR_CMD_VALID : std_logic := '0';
signal IODRPCTRLR_USE_BKST : std_logic := '0';
signal MCB_CMD_VALID : std_logic := '0';
signal MCB_USE_BKST : std_logic := '0';
signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
signal IODRP_SDO : std_logic;
signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
signal counter_en : std_logic := '0'; -- counter enable for "count"
signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
signal START_BROADCAST : std_logic := '1'; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
-- state machine will wait for this to be high
signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
-- the Max Value changes by more than the threshold
signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
signal IODRPCTRLR_RDY_BUSY_N : std_logic;
signal IODRP_CS : std_logic;
signal MCB_READ_DATA : std_logic_vector(7 downto 0);
signal RST_reg : std_logic;
signal Block_Reset : std_logic;
signal MCB_UODATAVALID_U : std_logic;
signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
signal rst_tmp : std_logic;
signal LastPass_DynCal : std_logic;
signal First_In_Term_Done : std_logic;
signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
-- parameter = "CALIBRATION"
signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
-- one-time or dynamic parameters are 1
signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
-- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
signal Quarter_Max_Value : std_logic_vector(7 downto 0);
signal Half_Max_Value : std_logic_vector(7 downto 0);
signal PLL_LOCK_R1 : std_logic;
signal PLL_LOCK_R2 : std_logic;
signal MCB_RDY_BUSY_N : std_logic;
signal SELFREFRESH_REQ_R1 : std_logic;
signal SELFREFRESH_REQ_R2 : std_logic;
signal SELFREFRESH_REQ_R3 : std_logic;
signal SELFREFRESH_MCB_MODE_R1 : std_logic;
signal SELFREFRESH_MCB_MODE_R2 : std_logic;
signal SELFREFRESH_MCB_MODE_R3 : std_logic;
signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
signal START_DYN_CAL_STATE_R1 : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-- Declare intermediate signals for referenced outputs
signal IODRP_ADD_xilinx0 : std_logic;
signal IODRP_SDI_xilinx1 : std_logic;
signal MCB_UIADD_xilinx2 : std_logic;
signal MCB_UISDI_xilinx11 : std_logic;
signal MCB_UICS_xilinx6 : std_logic;
signal MCB_UIBROADCAST_xilinx4 : std_logic;
signal MCB_UIADDR_xilinx3 : std_logic_vector(4 downto 0);
signal MCB_UIDONECAL_xilinx7 : std_logic;
signal MCB_UIREAD_xilinx10 : std_logic;
signal SELFREFRESH_MODE_xilinx11 : std_logic;
signal Max_Value_int : std_logic_vector(7 downto 0);
signal Rst_condition1 : std_logic;
signal Rst_condition2 : std_logic;
signal non_violating_rst : std_logic;
signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
-- This function multiplies by a constant MULT and then divides by the DIV constant
function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
variable Result : integer := 0;
variable temp : std_logic_vector(14 downto 0) := "000000000000000";
begin
for count in 0 to (MULT-1) loop
temp := temp + ("0000000" & Input);
end loop;
Result := (to_integer(unsigned(temp))) / (DIV);
temp := std_logic_vector(to_unsigned(Result,15));
return temp(7 downto 0);
end function Mult_Divide;
attribute syn_preserve : boolean;
attribute syn_preserve of P_Term : signal is TRUE;
attribute syn_preserve of N_Term : signal is TRUE;
attribute syn_preserve of P_Term_Prev : signal is TRUE;
attribute syn_preserve of N_Term_Prev : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
attribute syn_preserve of Max_Value_Previous : signal is TRUE;
attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
attribute iob : string;
attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
begin
Max_Value <= Max_Value_int;
-- Drive referenced outputs
IODRP_ADD <= IODRP_ADD_xilinx0;
IODRP_SDI <= IODRP_SDI_xilinx1;
MCB_UIADD <= MCB_UIADD_xilinx2;
MCB_UISDI <= MCB_UISDI_xilinx11;
MCB_UICS <= MCB_UICS_xilinx6;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
MCB_UIADDR <= MCB_UIADDR_xilinx3;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
MCB_UIREAD <= MCB_UIREAD_xilinx10;
SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
-- skip dynamic input termination if either the one-time or dynamic parameters are 1
SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
-- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
else
DONE_SOFTANDHARD_CAL <= '0';
end if;
end if;
end process;
iodrp_controller_inst : iodrp_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => IODRPCTRLR_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => IODRPCTRLR_CMD_VALID,
rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
use_broadcast => '0',
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => IODRP_CS,
DRP_SDI => IODRP_SDI_xilinx1,
DRP_ADD => IODRP_ADD_xilinx0,
DRP_SDO => IODRP_SDO,
DRP_BKST => open
);
iodrp_mcb_controller_inst : iodrp_mcb_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => MCB_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => MCB_CMD_VALID,
rdy_busy_n => MCB_RDY_BUSY_N,
use_broadcast => MCB_USE_BKST,
drp_ioi_addr => MCB_UIADDR_xilinx3,
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => MCB_UICS_xilinx6,
DRP_SDI => MCB_UISDI_xilinx11,
DRP_ADD => MCB_UIADD_xilinx2,
DRP_BKST => MCB_UIBROADCAST_xilinx4,
DRP_SDO => MCB_UOSDO,
MCB_UIREAD => MCB_UIREAD_xilinx10
);
init_sequence: if (C_SIMULATION = "FALSE") generate
process (UI_CLK, RST) begin
if (RST = '1') then
WAIT_200us_COUNTER <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '1') then
WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
else
WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
end if;
end if;
end process;
end generate;
init_sequence_skip: if (C_SIMULATION = "TRUE") generate
WAIT_200us_COUNTER <= X"FFFF";
end generate;
gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
process (UI_CLK, RST) begin
if (RST = '1') then
CKE_Train <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
CKE_Train <= '0';
elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
CKE_Train <= '1';
end if;
end if;
end process;
end generate ;
gen_CKE_Train_b: if (C_MEM_TYPE /= "DDR2") generate
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
CKE_Train <= '0';
end if;
end process;
end generate ;
--********************************************
-- PLL_LOCK and RST signals
--********************************************
MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
process (UI_CLK, rst_tmp, RST) begin
if (rst_tmp = '1') then
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (RST = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets -- to DDR3)
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
if (Pre_SYSRST = '1') then
RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
else
if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
end if;
end if;
end if;
end process;
non_violating_rst <= RST and Rst_condition1;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter >= TZQINIT_MAXCNT) then
Rst_condition1 <= '1';
else
Rst_condition1 <= '0';
end if;
end if;
end process;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter < RST_CNT) then
Rst_condition2 <= '1';
else
Rst_condition2 <= '0';
end if;
end if;
end process;
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '0';
else
RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;
--********************************************
-- SUSPEND Logic
--********************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
-- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-- SELFREFRESH_REQ is clocked by user's application clock
SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
PLL_LOCK_R1 <= PLL_LOCK;
PLL_LOCK_R2 <= PLL_LOCK_R1;
end if;
end process;
-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
-- This is to make sure MCB get a locked sys_2x_clk before exiting
-- SELFREFRESH mode.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MCB_REQ <= '0';
elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R1 = '0') and (STATE = START_DYN_CAL)) then
SELFREFRESH_MCB_REQ <= '0';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R1 = '1')) then
SELFREFRESH_MCB_REQ <= '1';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
-- START_DYN_CAL is next state
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
end if;
end if;
end process;
-- Need to detect when SM entering START_DYN_CAL
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
START_DYN_CAL_STATE_R1 <= '0';
else
-- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
if (STATE = START_DYN_CAL) then
START_DYN_CAL_STATE_R1 <= '1';
else
START_DYN_CAL_STATE_R1 <= '0';
end if;
if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
elsif ((STATE = START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '0')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
end if;
end if;
end if;
end process;
-- SELFREFRESH_MCB_MODE deasserted status is hold off
-- until Soft_Calib has at least done one loop of DQS update.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
SELFREFRESH_MODE_xilinx11 <= '1';
elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
SELFREFRESH_MODE_xilinx11 <= '0';
end if;
end if;
end process;
--********************************************
--Comparitor for Dynamic Calibration circuit
--********************************************
Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
--*********************************************************************************************
--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
--*********************************************************************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then
count <= "000000";
elsif (counter_en = '1') then
count <= count + "000001";
else
count <= "000000";
end if;
end if;
end process;
--*********************************************************************************************
-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
--*********************************************************************************************
process (UI_CLK, MCB_UODATAVALID)
begin
if(MCB_UODATAVALID = '1') then
MCB_UODATAVALID_U <= '1';
elsif(UI_CLK'event and UI_CLK = '1') then
MCB_UODATAVALID_U <= MCB_UODATAVALID;
end if;
end process;
--**************************************************************************************************************
--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
--**************************************************************************************************************
process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
begin
case Active_IODRP is
when RZQ =>
RZQ_IODRP_CS <= IODRP_CS;
ZIO_IODRP_CS <= '0';
IODRP_SDO <= RZQ_IODRP_SDO;
when ZIO =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= IODRP_CS;
IODRP_SDO <= ZIO_IODRP_SDO;
when MCB_PORT =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
when others =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
end case;
end process;
--******************************************************************
--State Machine's Always block / Case statement for Next State Logic
--
--The WAIT1,2,etc states were required after every state where the
--DRP controller was used to do a write to the IODRPs - this is because
--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
--sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
--soley for the purpose of reducing power, particularly on RZQ as
--that pin is expected to have a permanent external resistor to gnd.
--******************************************************************
NEXT_STATE_LOGIC: process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then -- Synchronous reset
MCB_CMD_VALID <= '0';
MCB_UIADDR_xilinx3 <= "00000"; -- take control of UI/UO port
MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
MCB_UIDONECAL_xilinx7 <= '0';
MCB_USE_BKST <= '0';
MCB_UIDRPUPDATE <= '1';
Pre_SYSRST <= '1'; -- keeps MCB in reset
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
P_Term_Prev <= "000000";
N_Term_Prev <= "0000000";
Active_IODRP <= RZQ;
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
counter_en <= '0'; --flag that the First Dynamic Calibration completed
First_Dyn_Cal_Done <= '0';
Max_Value_int <= "00000000";
Max_Value_Previous <= "00000000";
STATE <= START;
DQS_DELAY <= "00000000";
DQS_DELAY_INITIAL <= "00000000";
TARGET_DQS_DELAY <= "00000000";
LastPass_DynCal <= IN_TERM_PASS;
First_In_Term_Done <= '0';
MCB_UICMD <= '0';
MCB_UICMDIN <= '0';
MCB_UIDQCOUNT <= "0000";
counter_inc <= "00000000";
counter_dec <= "00000000";
else
counter_en <= '0';
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_R_WB <= READ_MODE;
IODRPCTRLR_USE_BKST <= '0';
MCB_CMD_VALID <= '0'; --no inc or dec
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
MCB_USE_BKST <= '0';
MCB_UICMDIN <= '0';
DQS_DELAY <= DQS_DELAY;
TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
case STATE is
when START => --h00
MCB_UICMDEN <= '1'; -- take control of UI/UO port
MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
P_Term <= "000000";
N_Term <= "0000000";
Pre_SYSRST <= '1'; -- keeps MCB in reset
LastPass_DynCal <= IN_TERM_PASS;
if (SKIP_IN_TERM_CAL = 1) then
STATE <= WRITE_CALIBRATE;
elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= START;
end if;
--***************************
-- IOB INPUT TERMINATION CAL
--***************************
when LOAD_RZQ_NTERM => --h01
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= WAIT1;
end if;
when WAIT1 => --h02
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT1;
else
STATE <= LOAD_RZQ_PTERM;
end if;
when LOAD_RZQ_PTERM => --h03
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_PTERM;
else
STATE <= WAIT2;
end if;
when WAIT2 => --h04
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT2;
elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
else
STATE <= INC_PTERM;
end if;
when INC_PTERM => --h05
P_Term <= P_Term + "000001";
STATE <= LOAD_RZQ_PTERM;
when MULTIPLY_DIVIDE => -- h06
P_Term <= Mult_Divide(("00" & P_Term),MULT,DIV)(5 downto 0);
STATE <= LOAD_ZIO_PTERM;
when LOAD_ZIO_PTERM => --h07
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_PTERM;
else
STATE <= WAIT3;
end if;
when WAIT3 => --h08
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT3;
else
STATE <= LOAD_ZIO_NTERM;
end if;
when LOAD_ZIO_NTERM => --h09
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_NTERM;
else
STATE <= WAIT4;
end if;
when WAIT4 => --h0A
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
else
STATE <= INC_NTERM;
end if;
when INC_NTERM => --h0B
N_Term <= N_Term + "0000001";
STATE <= LOAD_ZIO_NTERM;
when SKEW => -- h0C
P_Term <= Mult_Divide(("00" & P_Term), PSKEW_MULT, PSKEW_DIV)(5 downto 0);
N_Term <= Mult_Divide(('0' & N_Term), NSKEW_MULT, NSKEW_DIV)(6 downto 0);
STATE <= WAIT_FOR_START_BROADCAST;
when WAIT_FOR_START_BROADCAST => --h0D
Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
-- keeping the MCB in calibration mode
Active_IODRP <= MCB_PORT;
if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
if (P_Term /= P_Term_Prev) then
STATE <= BROADCAST_PTERM;
P_Term_Prev <= P_Term;
elsif (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
when BROADCAST_PTERM => --h0E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
MCB_USE_BKST <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_PTERM;
else
STATE <= WAIT5;
end if;
when WAIT5 => --h0F
if ((not(MCB_RDY_BUSY_N)) = '1') then
STATE <= WAIT5;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
if (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT5; -- wait for a Refresh cycle
end if;
else
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
end if;
when BROADCAST_NTERM => -- h10
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_USE_BKST <= '1';
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_NTERM;
else
STATE <= WAIT6;
end if;
when WAIT6 => -- h11
if (MCB_RDY_BUSY_N = '0') then
STATE <= WAIT6;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT6; -- wait for a Refresh cycle
end if;
else
STATE <= OFF_RZQ_PTERM;
end if;
when OFF_RZQ_PTERM => -- h12
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
P_Term <= "000000";
N_Term <= "0000000";
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT7;
end if;
when WAIT7 => -- h13
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT7;
else
STATE <= OFF_ZIO_NTERM;
end if;
when OFF_ZIO_NTERM => -- h14
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_ZIO_NTERM;
else
STATE <= WAIT8;
end if;
when WAIT8 => -- h15
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT8;
else
if (First_In_Term_Done = '1') then
STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
else
STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
end if;
end if;
when RST_DELAY => -- h16
MCB_UICMDEN <= '0'; -- release control of UI/UO port
if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
STATE <= RST_DELAY;
else
STATE <= START_DYN_CAL_PRE;
end if;
--***************************
--DYNAMIC CALIBRATION PORTION
--***************************
when START_DYN_CAL_PRE => -- h17
LastPass_DynCal <= IN_TERM_PASS;
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '1'; -- SYSRST pulse
if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
else
STATE <= WAIT_FOR_UODONE;
end if;
when WAIT_FOR_UODONE => -- h18
Pre_SYSRST <= '0'; -- SYSRST pulse
if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
MCB_UICMDEN <= '1'; -- grab UICMDEN
DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= WAIT_FOR_UODONE;
end if;
when LDQS_WRITE_POS_INDELAY => -- h19
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_xilinx3 <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= LDQS_WAIT1;
end if;
when LDQS_WAIT1 => -- h1A
if (MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT1;
else
STATE <= LDQS_WRITE_NEG_INDELAY;
end if;
when LDQS_WRITE_NEG_INDELAY => -- h1B
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_xilinx3 <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= LDQS_WRITE_NEG_INDELAY;
else
STATE <= LDQS_WAIT2;
end if;
when LDQS_WAIT2 => -- 7'h1C
if(MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT2;
else
STATE <= UDQS_WRITE_POS_INDELAY;
end if;
when UDQS_WRITE_POS_INDELAY => -- 7'h1D
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_xilinx3 <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_POS_INDELAY;
else
STATE <= UDQS_WAIT1;
end if;
when UDQS_WAIT1 => -- 7'h1E
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT1;
else
STATE <= UDQS_WRITE_NEG_INDELAY;
end if;
when UDQS_WRITE_NEG_INDELAY => -- 7'h1F
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_xilinx3 <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_NEG_INDELAY;
else
STATE <= UDQS_WAIT2;
end if;
when UDQS_WAIT2 => -- 7'h20
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT2;
else
DQS_DELAY <= DQS_DELAY_INITIAL;
TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
STATE <= START_DYN_CAL;
end if;
when START_DYN_CAL => -- h21
Pre_SYSRST <= '0'; -- SYSRST not driven
counter_inc <= (others => '0');
counter_dec <= (others => '0');
if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
--IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
-- Alternate between Dynamic Input Termination and Dynamic Tuning routines
if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
LastPass_DynCal <= IN_TERM_PASS;
STATE <= LOAD_RZQ_NTERM;
else
LastPass_DynCal <= DYN_CAL_PASS;
STATE <= WRITE_CALIBRATE;
end if;
else
STATE <= START_DYN_CAL;
end if;
when WRITE_CALIBRATE => -- h22
Pre_SYSRST <= '0';
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
IODRPCTRLR_WRITE_DATA <= "00100000";
IODRPCTRLR_R_WB <= WRITE_MODE;
Active_IODRP <= RZQ;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= WRITE_CALIBRATE;
else
STATE <= WAIT9;
end if;
when WAIT9 => -- h23
counter_en <= '1';
if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
STATE <= WAIT9;
else
STATE <= READ_MAX_VALUE;
end if;
when READ_MAX_VALUE => -- h24
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
IODRPCTRLR_R_WB <= READ_MODE;
Max_Value_Previous <= Max_Value_int;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= READ_MAX_VALUE;
else
STATE <= WAIT10;
end if;
when WAIT10 => -- h25
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT10;
else
Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
if (First_In_Term_Done = '0') then
STATE <= RST_DELAY;
First_In_Term_Done <= '1';
else
STATE <= ANALYZE_MAX_VALUE;
end if;
end if;
when ANALYZE_MAX_VALUE => -- h26 only do a Inc or Dec during a REFRESH cycle.
if (First_Dyn_Cal_Done = '0')then
STATE <= FIRST_DYN_CAL;
elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
STATE <= DECREMENT; -- May need to Decrement
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
-- DQS_COUNT_VIRTUAL updated (could be negative value)
elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
STATE <= INCREMENT; -- May need to Increment
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
else
Max_Value_int <= Max_Value_Previous;
STATE <= START_DYN_CAL;
end if;
when FIRST_DYN_CAL => -- h27
First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
STATE <= START_DYN_CAL;
when INCREMENT => -- h28
STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "101" =>
counter_inc <= counter_inc + '1';
STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
-- if not at the upper limit yet, and you've waited 4 clks, increment
MCB_UILDQSINC <= '1';
MCB_UIUDQSINC <= '1';
DQS_DELAY <= DQS_DELAY + '1';
end if;
when "100" =>
if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
when DECREMENT => -- h29
STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
if (DQS_DELAY /= "00000000") then
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "011" =>
counter_dec <= counter_dec + '1';
STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
-- if not at the lower limit, and you've waited 4 clks, decrement
MCB_UILDQSDEC <= '1'; -- decrement
MCB_UIUDQSDEC <= '1'; -- decrement
DQS_DELAY <= DQS_DELAY - '1'; -- SBS
end if;
when "010" =>
if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
end if;
when DONE => -- h2A
Pre_SYSRST <= '0'; -- SYSRST cleared
MCB_UICMDEN <= '0'; -- release UICMDEN
STATE <= DONE;
when others =>
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '0'; -- SYSRST not driven
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= "00000000";
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= '0';
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
Active_IODRP <= ZIO;
Max_Value_Previous <= "00000000";
MCB_UILDQSINC <= '0'; -- no inc or dec
MCB_UIUDQSINC <= '0'; -- no inc or dec
MCB_UILDQSDEC <= '0'; -- no inc or dec
MCB_UIUDQSDEC <= '0'; -- no inc or dec
counter_en <= '0';
First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
Max_Value_int <= Max_Value_int;
STATE <= START;
end case;
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 | cc8f06c902ab86dbb0c0cbd4b5d3457b | 0.47568 | 4.316659 | false | false | false | false |
aleksandar-mitrevski/hw_sw | hybrid_velocity_counter/velocity_counter.vhd | 1 | 3,665 | library IEEE;
use IEEE.std_logic_1164.All;
entity HybridVelocityCounter is port (
clk : in std_logic;
encoder : in std_logic;
speed : out real;
measurementType: out std_logic);
end HybridVelocityCounter;
architecture velocity of HybridVelocityCounter is
type measurementTypes is (HighSpeed, LowSpeed);
constant clockFrequency : integer := 25; -- frequency in nanoseconds
constant samplingPeriod: integer := 1500; -- sampling period in nanoseconds
constant minimumHighSpeedCounter : integer := 5;
constant maximumLowSpeed : real := 0.005;
signal currentMeasurementType : measurementTypes := HighSpeed;
begin
speedMeasurement: process(clk)
variable pulseCounter : integer := 0;
variable timeChange : integer := 0;
variable counted : std_logic := '0';
variable timeReal : real;
variable currentSpeed : real;
variable measuringTime : std_logic;
begin
if rising_edge(clk) then
if currentMeasurementType = HighSpeed then
if encoder = '1' then
if counted = '0' then
pulseCounter := pulseCounter + 1;
counted := '1';
end if;
elsif counted = '1' then
counted := '0';
end if;
timeChange := timeChange + 2 * clockFrequency;
if timeChange >= samplingPeriod then
--we switch to a low-velocity mode if the pulse counter
--is below a predefined threshold
if pulseCounter < minimumHighSpeedCounter then
currentMeasurementType <= LowSpeed;
measurementType <= '1';
else
measurementType <= '0';
end if;
timeReal := real(samplingPeriod);
speed <= real(pulseCounter) / timeReal;
-- we reset the variables to allow for new measurements
pulseCounter := 0;
timeChange := 0;
counted := '0';
end if;
else
if encoder = '1' then
if measuringTime = '1' then
timeChange := timeChange + 2 * clockFrequency;
if counted = '0' then
timeReal := real(timeChange);
currentSpeed := 1.0 / timeReal;
if currentSpeed > maximumLowSpeed then
currentMeasurementType <= HighSpeed;
measurementType <= '0';
else
measurementType <= '1';
end if;
speed <= currentSpeed;
-- we reset the variables to allow for new measurements
timeChange := 0;
counted := '0';
measuringTime := '0';
end if;
else
counted := '1';
measuringTime := '1';
end if;
else
if measuringTime = '1' then
timeChange := timeChange + 2 * clockFrequency;
end if;
if counted = '1' then
counted := '0';
end if;
end if;
end if;
end if;
end process;
end velocity;
| mit | e63c769ebff582fc3c24dee4a571b050 | 0.461937 | 5.726563 | false | false | false | false |
masterdezign/cellular-automata-clash-fpga | src/vhdl/Cellular/Cellular/cellular_types.vhdl | 1 | 5,660 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package cellular_types is
type array_of_std_logic_vector_1 is array (integer range <>) of std_logic_vector(0 downto 0);
type array_of_std_logic is array (integer range <>) of std_logic;
type array_of_std_logic_vector_16 is array (integer range <>) of std_logic_vector(15 downto 0);
subtype rst_system is std_logic;
subtype clk_system is std_logic;
function toSLV (b : in boolean) return std_logic_vector;
function fromSLV (sl : in std_logic_vector) return boolean;
function tagToEnum (s : in signed) return boolean;
function dataToTag (b : in boolean) return signed;
function toSLV (slv : in std_logic_vector) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return std_logic_vector;
function toSLV (value : cellular_types.array_of_std_logic_vector_1) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return cellular_types.array_of_std_logic_vector_1;
function toSLV (sl : in std_logic) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return std_logic;
function toSLV (value : cellular_types.array_of_std_logic) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return cellular_types.array_of_std_logic;
function toSLV (value : cellular_types.array_of_std_logic_vector_16) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return cellular_types.array_of_std_logic_vector_16;
function toSLV (u : in unsigned) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return unsigned;
function toSLV (s : in signed) return std_logic_vector;
function fromSLV (slv : in std_logic_vector) return signed;
end;
package body cellular_types is
function toSLV (b : in boolean) return std_logic_vector is
begin
if b then
return "1";
else
return "0";
end if;
end;
function fromSLV (sl : in std_logic_vector) return boolean is
begin
if sl = "1" then
return true;
else
return false;
end if;
end;
function tagToEnum (s : in signed) return boolean is
begin
if s = to_signed(0,64) then
return false;
else
return true;
end if;
end;
function dataToTag (b : in boolean) return signed is
begin
if b then
return to_signed(1,64);
else
return to_signed(0,64);
end if;
end;
function toSLV (slv : in std_logic_vector) return std_logic_vector is
begin
return slv;
end;
function fromSLV (slv : in std_logic_vector) return std_logic_vector is
begin
return slv;
end;
function toSLV (value : cellular_types.array_of_std_logic_vector_1) return std_logic_vector is
alias ivalue : cellular_types.array_of_std_logic_vector_1(1 to value'length) is value;
variable result : std_logic_vector(1 to value'length * 1);
begin
for i in ivalue'range loop
result(((i - 1) * 1) + 1 to i*1) := toSLV(ivalue(i));
end loop;
return result;
end;
function fromSLV (slv : in std_logic_vector) return cellular_types.array_of_std_logic_vector_1 is
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
variable result : cellular_types.array_of_std_logic_vector_1(0 to slv'length / 1 - 1);
begin
for i in result'range loop
result(i) := islv(i * 1 to (i+1) * 1 - 1);
end loop;
return result;
end;
function toSLV (sl : in std_logic) return std_logic_vector is
begin
return std_logic_vector'(0 => sl);
end;
function fromSLV (slv : in std_logic_vector) return std_logic is
alias islv : std_logic_vector (0 to slv'length - 1) is slv;
begin
return islv(0);
end;
function toSLV (value : cellular_types.array_of_std_logic) return std_logic_vector is
alias ivalue : cellular_types.array_of_std_logic(1 to value'length) is value;
variable result : std_logic_vector(1 to value'length * 1);
begin
for i in ivalue'range loop
result(((i - 1) * 1) + 1 to i*1) := toSLV(ivalue(i));
end loop;
return result;
end;
function fromSLV (slv : in std_logic_vector) return cellular_types.array_of_std_logic is
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
variable result : cellular_types.array_of_std_logic(0 to slv'length / 1 - 1);
begin
for i in result'range loop
result(i) := fromSLV(islv(i * 1 to (i+1) * 1 - 1));
end loop;
return result;
end;
function toSLV (value : cellular_types.array_of_std_logic_vector_16) return std_logic_vector is
alias ivalue : cellular_types.array_of_std_logic_vector_16(1 to value'length) is value;
variable result : std_logic_vector(1 to value'length * 16);
begin
for i in ivalue'range loop
result(((i - 1) * 16) + 1 to i*16) := toSLV(ivalue(i));
end loop;
return result;
end;
function fromSLV (slv : in std_logic_vector) return cellular_types.array_of_std_logic_vector_16 is
alias islv : std_logic_vector(0 to slv'length - 1) is slv;
variable result : cellular_types.array_of_std_logic_vector_16(0 to slv'length / 16 - 1);
begin
for i in result'range loop
result(i) := islv(i * 16 to (i+1) * 16 - 1);
end loop;
return result;
end;
function toSLV (u : in unsigned) return std_logic_vector is
begin
return std_logic_vector(u);
end;
function fromSLV (slv : in std_logic_vector) return unsigned is
begin
return unsigned(slv);
end;
function toSLV (s : in signed) return std_logic_vector is
begin
return std_logic_vector(s);
end;
function fromSLV (slv : in std_logic_vector) return signed is
begin
return signed(slv);
end;
end;
| mit | 2e60efbe667a02a94785740324ac76b7 | 0.677562 | 3.367043 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/FPU/FPU.vhd | 1 | 9,252 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
USE work.UMDRISC_pkg.ALL;
entity FPU is
PORT (
--INPUT
CLOCK : in STD_LOGIC;
RESETN : in STD_LOGIC;
ENABLE : in STD_LOGIC;
-- Data from T1
IMMED : IN STD_LOGIC_VECTOR(DATA_WIDTH-13 DOWNTO 0); --[11:0] 12 bits
SIGNED_IMMED : IN STD_LOGIC_VECTOR(DATA_WIDTH-9 DOWNTO 0); --[15:0] 16 bits
--input Register
REG_DATA_IN : in STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); -- Register Data input for general and shadow reg
--CONTROL INPUT SIGNALS
--General Purpose Register interface
SRC1 : in STD_LOGIC_VECTOR(3 DOWNTO 0); -- General purpose Reg A Address
SRC2 : in STD_LOGIC_VECTOR(3 DOWNTO 0); -- General purpose Reg B Address
GP_DIN_SEL : in STD_LOGIC_VECTOR(3 DOWNTO 0); -- Reg Address to write to
GP_WE : in STD_LOGIC; -- write enable for general purpose register
--Shadow Register
SR_SEL : in STD_LOGIC_VECTOR(1 DOWNTO 0); -- Shadow Register Select
SR_DIN_SEL : in STD_LOGIC_VECTOR(1 DOWNTO 0); -- Shadow Register to write to
SR_WE : in STD_LOGIC; -- write enable for shadow register
--MUX's
SRC0_SEL : in STD_LOGIC; -- Select between immed and signed extension
SRC1_MUX : in STD_LOGIC;--_VECTOR(1 DOWNTO 0); -- Select between PC, RA, SR, DST_ADDR (4 select)
SRC2_MUX : in STD_LOGIC; -- Select between immed or Reg B (2 select)
--ALU
ALU_OPCODE : in STD_LOGIC_VECTOR(3 DOWNTO 0); -- OPCODE for the ALU
-- Program Counter
--PC : IN STD_LOGIC_VECTOR(PC_WIDTH-1 DOWNTO 0); --Program Counter
--OUTPUT
STORE_DATA : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); --Destination Data
DST_ADDR : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); --Destination Address
ALU_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
LDST_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0); -- output the load / store on the ALU
CCR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) --Condition Code Register (ALU)
);
end FPU;
architecture Structural of FPU is
---------- MUX ---------- ---------- ----------
component MUX_2to1 is
Port (
SEL : in STD_LOGIC;
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
component MUX_3to1 is
Port (
SEL : in STD_LOGIC_VECTOR (1 downto 0);
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_3 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
component MUX_4to1 is
Port (
SEL : in STD_LOGIC_VECTOR (1 downto 0);
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_3 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_4 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
---------- REG ---------- ---------- ----------
--Register Latch on Rising Edge
component RegR IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end component;
--Register Latch on Falling Edge
component RegF IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end component;
--Register With a Hold(Latch on Falling) while Reg Latch Rising Edge
component RegHold_F IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end component;
--4bit Register Latch on Rising Edge
component Reg4R IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
-------- 16 24bit General Purpose Reg ---------
component REG_S16 is
generic(
REG_WIDTH: integer:=4 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--RESETN : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
---------- 4 24bit Shadow Reg------- ----------
component SREG_4 is
generic(
REGS_WIDTH: integer:=2 -- select between 4 different possible registers
);
port(
CLOCK : in std_logic;
SR_WE : in std_logic;
-- RESETN : in std_logic;
--Shadow Register
SR_SEL : in std_logic_vector(REGS_WIDTH-1 downto 0);
SR_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
SR_IN_SEL : in std_logic_vector(REGS_WIDTH-1 downto 0);
SR_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
---------- ALU ---------- ---------- ----------
component ALU is
Port (
CLOCK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
RB : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0); -- Condition Codes (N,Z,V,C)
ALU_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
LDST_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0) -- Output from the Load/Store Routine
);
end component;
---------- SIGNALS ------ ---------- ----------
signal IMMEDS,SIGN,IM_OUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal IMMED0, SIG_EXT0 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal SR_OUT,IM_RB,DST_ADDRS,SD_RA : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal SRC1_S, SRC2_S : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal CCR_OUT : STD_LOGIC_VECTOR(3 downto 0);
signal OPERAND0, OPERAND1, OPERAND2 : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
--signal PC0 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal DST_DATA_OUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal ALU0 : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0); --,LDST_OUT
begin
IMMED0 <= std_logic_vector(resize(unsigned(IMMED), IMMED0'length));
SIG_EXT0 <= std_logic_vector(resize(unsigned(SIGNED_IMMED), SIGNED_IMMED'length));
--PC0 <= std_logic_vector(resize(unsigned(PC), PC0'length));
DST_ADDR <= DST_ADDRS;
U_IMMED: RegF PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => IMMED0,
OUTPUT => IMMEDS
);
U_SIGN_EXT: RegF PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => SIG_EXT0,
OUTPUT => SIGN
);
U_IM_MUX: MUX_2to1 PORT MAP (
SEL => SRC0_SEL,
IN_1 => IMMEDS,
IN_2 => SIGN,
OUTPUT => IM_OUT
);
U_REG16TGT: REG_S16 PORT MAP (
CLOCK => CLOCK,
--RESETN => RESETN,
WE => GP_WE,
REG_A_ADDR => SRC1,
REG_A => SRC1_S,
REG_B_ADDR => SRC2,
REG_B => SRC2_S,
REG_A_IN_ADDR => GP_DIN_SEL,
REG_A_IN => REG_DATA_IN
);
U_REG_SHADOW: SREG_4 PORT MAP (
CLOCK => CLOCK,
--RESETN => RESETN,
SR_WE => SR_WE,
SR_IN_SEL => SR_DIN_SEL,
SR_IN => REG_DATA_IN,
SR_SEL => SR_SEL,
SR_OUT => SR_OUT
);
U_Operand0: RegR PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => IM_OUT,
OUTPUT => Operand0
);
U_Operand1: RegR PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => SRC1_S,
OUTPUT => Operand1
);
U_Operand2: RegR PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => SRC2_S,
OUTPUT => Operand2
);
U_IM_RB_MUX: MUX_2to1 PORT MAP (
SEL => SRC2_MUX,
IN_1 => Operand0,
IN_2 => Operand2,
OUTPUT => IM_RB
);
U_SD_RA_MUX: MUX_2to1 PORT MAP (
SEL => SRC1_MUX,
IN_1 => Operand1,
IN_2 => SR_OUT,
OUTPUT => SD_RA
);
--U_SD_RA_MUX: MUX_4to1 PORT MAP (
-- SEL => SRC1_MUX,
-- IN_1 => Operand1,
-- IN_2 => SR_OUT,
-- IN_3 => DST_ADDRS,
-- IN_4 => PC0,
-- OUTPUT => SD_RA
--);
U_ALU: ALU PORT MAP (
CLOCK => CLOCK,
RA => SD_RA,
RB => IM_RB,
OPCODE => ALU_OPCODE,
CCR => CCR_OUT,
ALU_OUT => ALU0,
LDST_OUT => LDST_OUT
);
U_NZVC_REG: Reg4R PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => CCR_OUT,
OUTPUT => CCR
);
U_STORE_DATA: RegHold_F PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => IM_RB,
OUTPUT => STORE_DATA
);
U_ALU_OUT: RegR PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => ALU0,
OUTPUT => ALU_OUT
);
U_DST_ADDR: RegHold_F PORT MAP (
Clock => CLOCK,
RESETN => RESETN,
ENABLE => ENABLE,
INPUT => Operand1,
OUTPUT => DST_ADDRS
);
end Structural;
| mit | fc4c6ebe5b4b0b37f7d98c2a519dfd88 | 0.615867 | 2.651763 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/mem0.vhd | 1 | 45,416 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : mem0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/05/18 11:08:59 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mem0 is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 5000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 2
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_n : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic;
c3_p4_cmd_clk : in std_logic;
c3_p4_cmd_en : in std_logic;
c3_p4_cmd_instr : in std_logic_vector(2 downto 0);
c3_p4_cmd_bl : in std_logic_vector(5 downto 0);
c3_p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p4_cmd_empty : out std_logic;
c3_p4_cmd_full : out std_logic;
c3_p4_wr_clk : in std_logic;
c3_p4_wr_en : in std_logic;
c3_p4_wr_mask : in std_logic_vector(3 downto 0);
c3_p4_wr_data : in std_logic_vector(31 downto 0);
c3_p4_wr_full : out std_logic;
c3_p4_wr_empty : out std_logic;
c3_p4_wr_count : out std_logic_vector(6 downto 0);
c3_p4_wr_underrun : out std_logic;
c3_p4_wr_error : out std_logic;
c3_p5_cmd_clk : in std_logic;
c3_p5_cmd_en : in std_logic;
c3_p5_cmd_instr : in std_logic_vector(2 downto 0);
c3_p5_cmd_bl : in std_logic_vector(5 downto 0);
c3_p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p5_cmd_empty : out std_logic;
c3_p5_cmd_full : out std_logic;
c3_p5_rd_clk : in std_logic;
c3_p5_rd_en : in std_logic;
c3_p5_rd_data : out std_logic_vector(31 downto 0);
c3_p5_rd_full : out std_logic;
c3_p5_rd_empty : out std_logic;
c3_p5_rd_count : out std_logic_vector(6 downto 0);
c3_p5_rd_overflow : out std_logic;
c3_p5_rd_error : out std_logic
);
end mem0;
architecture arc of mem0 is
component memc3_infrastructure is
generic (
C_MEMCLK_PERIOD : integer;
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_cke : out std_logic;
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 2;
constant C3_CLKOUT1_DIVIDE : integer := 2;
constant C3_CLKOUT2_DIVIDE : integer := 16;
constant C3_CLKOUT3_DIVIDE : integer := 8;
constant C3_CLKFBOUT_MULT : integer := 4;
constant C3_DIVCLK_DIVIDE : integer := 1;
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := o"012345";
constant C3_ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := o"123450";
constant C3_ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := o"234501";
constant C3_ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := o"345012";
constant C3_ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := o"450123";
constant C3_ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := o"501234";
constant C3_ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := o"012345";
constant C3_ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := o"123450";
constant C3_ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := o"234501";
constant C3_ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := o"345012";
constant C3_ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := o"450123";
constant C3_ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := o"501234";
constant C3_MEM_TRAS : integer := 40000;
constant C3_MEM_TRCD : integer := 15000;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 70000;
constant C3_MEM_TRP : integer := 15000;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 2;
constant C3_MEM_TYPE : string := "DDR";
constant C3_MEM_DENSITY : string := "512Mb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 3;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 1;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_n => c3_sys_rst_n,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_p1_cmd_clk,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_p1_wr_clk,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_p1_rd_clk,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_wr_clk => c3_p2_wr_clk,
p2_wr_en => c3_p2_wr_en,
p2_wr_mask => c3_p2_wr_mask,
p2_wr_data => c3_p2_wr_data,
p2_wr_full => c3_p2_wr_full,
p2_wr_empty => c3_p2_wr_empty,
p2_wr_count => c3_p2_wr_count,
p2_wr_underrun => c3_p2_wr_underrun,
p2_wr_error => c3_p2_wr_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_rd_clk => c3_p3_rd_clk,
p3_rd_en => c3_p3_rd_en,
p3_rd_data => c3_p3_rd_data,
p3_rd_full => c3_p3_rd_full,
p3_rd_empty => c3_p3_rd_empty,
p3_rd_count => c3_p3_rd_count,
p3_rd_overflow => c3_p3_rd_overflow,
p3_rd_error => c3_p3_rd_error,
p4_cmd_clk => c3_p4_cmd_clk,
p4_cmd_en => c3_p4_cmd_en,
p4_cmd_instr => c3_p4_cmd_instr,
p4_cmd_bl => c3_p4_cmd_bl,
p4_cmd_byte_addr => c3_p4_cmd_byte_addr,
p4_cmd_empty => c3_p4_cmd_empty,
p4_cmd_full => c3_p4_cmd_full,
p4_wr_clk => c3_p4_wr_clk,
p4_wr_en => c3_p4_wr_en,
p4_wr_mask => c3_p4_wr_mask,
p4_wr_data => c3_p4_wr_data,
p4_wr_full => c3_p4_wr_full,
p4_wr_empty => c3_p4_wr_empty,
p4_wr_count => c3_p4_wr_count,
p4_wr_underrun => c3_p4_wr_underrun,
p4_wr_error => c3_p4_wr_error,
p5_cmd_clk => c3_p5_cmd_clk,
p5_cmd_en => c3_p5_cmd_en,
p5_cmd_instr => c3_p5_cmd_instr,
p5_cmd_bl => c3_p5_cmd_bl,
p5_cmd_byte_addr => c3_p5_cmd_byte_addr,
p5_cmd_empty => c3_p5_cmd_empty,
p5_cmd_full => c3_p5_cmd_full,
p5_rd_clk => c3_p5_rd_clk,
p5_rd_en => c3_p5_rd_en,
p5_rd_data => c3_p5_rd_data,
p5_rd_full => c3_p5_rd_full,
p5_rd_empty => c3_p5_rd_empty,
p5_rd_count => c3_p5_rd_count,
p5_rd_overflow => c3_p5_rd_overflow,
p5_rd_error => c3_p5_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;
| gpl-3.0 | 0e29341fc155ff850476fbf15b8868b4 | 0.432425 | 3.386221 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/control_unit_V2.vhd | 1 | 2,185 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:46:43 11/01/2015
-- Design Name:
-- Module Name: control_unit_V2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control_unit_V2 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
hlt : in STD_LOGIC;
op_en : out STD_LOGIC;
mem_en : out STD_LOGIC;
pc_en : out STD_LOGIC;
exe : out STD_LOGIC);
end control_unit_V2;
architecture Behavioral of control_unit_V2 is
-- Intermediate Signals --
signal cycle_counter : std_logic_vector( 2 downto 0 );
signal received_hlt : std_logic;
begin
-- Counter
process(clk, reset)
begin
if rising_edge(clk) then
--if reset = '1' then
--cycle_counter <= "000";
if cycle_counter = "101" then
cycle_counter <= "000";
else
cycle_counter <= cycle_counter + '1';
end if;
end if;
if reset = '1' then
cycle_counter <= "000";
end if;
end process;
-- HLT Detection
process(reset, hlt)
begin
if reset = '1' then
received_hlt <= '0';
else
if hlt = '1' then
received_hlt <= '1';
else
received_hlt <= received_hlt;
end if;
end if;
end process;
op_en <= '1' when (cycle_counter = "000" and received_hlt = '0') else '0';
mem_en <= '0' when ((cycle_counter = "000" or cycle_counter = "101") or received_hlt = '1') else '1';
pc_en <= '0' when (cycle_counter = "101" or received_hlt = '1') else '1';
exe <= '1' when (cycle_counter = "101" and received_hlt = '0') else '0';
end Behavioral;
| unlicense | edc100a0a94e0a8bdca843e6a2e2cb45 | 0.581236 | 3.213235 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/memc3_wrapper.vhd | 1 | 53,552 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : memc3_wrapper.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/06/04 11:24:37 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This module instantiates mcb_raw_wrapper module.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer := 2500;
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector := "000";
C_ARB_TIME_SLOT_1 : bit_vector := "000";
C_ARB_TIME_SLOT_2 : bit_vector := "000";
C_ARB_TIME_SLOT_3 : bit_vector := "000";
C_ARB_TIME_SLOT_4 : bit_vector := "000";
C_ARB_TIME_SLOT_5 : bit_vector := "000";
C_ARB_TIME_SLOT_6 : bit_vector := "000";
C_ARB_TIME_SLOT_7 : bit_vector := "000";
C_ARB_TIME_SLOT_8 : bit_vector := "000";
C_ARB_TIME_SLOT_9 : bit_vector := "000";
C_ARB_TIME_SLOT_10 : bit_vector := "000";
C_ARB_TIME_SLOT_11 : bit_vector := "000";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800000;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_MEM_ADDR_ORDER : string :="ROW_BANK_COLUMN";
C_MEM_TYPE : string :="DDR2";
C_MEM_DENSITY : string :="1Gb";
C_NUM_DQ_PINS : integer := 4;
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 5;
C_MEM_ADDR_WIDTH : integer := 14;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "FULL";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_CAS_LATENCY : integer:= 7;
C_MEM_DDR3_CAS_WR_LATENCY : integer:= 5;
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_MDDR_ODS : string := "FULL";
C_MC_CALIB_BYPASS : string := "NO";
C_LDQSP_TAP_DELAY_VAL : integer := 0;
C_UDQSP_TAP_DELAY_VAL : integer := 0;
C_LDQSN_TAP_DELAY_VAL : integer := 0;
C_UDQSN_TAP_DELAY_VAL : integer := 0;
C_DQ0_TAP_DELAY_VAL : integer := 0;
C_DQ1_TAP_DELAY_VAL : integer := 0;
C_DQ2_TAP_DELAY_VAL : integer := 0;
C_DQ3_TAP_DELAY_VAL : integer := 0;
C_DQ4_TAP_DELAY_VAL : integer := 0;
C_DQ5_TAP_DELAY_VAL : integer := 0;
C_DQ6_TAP_DELAY_VAL : integer := 0;
C_DQ7_TAP_DELAY_VAL : integer := 0;
C_DQ8_TAP_DELAY_VAL : integer := 0;
C_DQ9_TAP_DELAY_VAL : integer := 0;
C_DQ10_TAP_DELAY_VAL : integer := 0;
C_DQ11_TAP_DELAY_VAL : integer := 0;
C_DQ12_TAP_DELAY_VAL : integer := 0;
C_DQ13_TAP_DELAY_VAL : integer := 0;
C_DQ14_TAP_DELAY_VAL : integer := 0;
C_DQ15_TAP_DELAY_VAL : integer := 0;
C_SKIP_IN_TERM_CAL : integer := 0;
C_SKIP_DYNAMIC_CAL : integer := 0;
C_SIMULATION : string := "FALSE";
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "QUARTER";
C_CALIB_SOFT_IP : string := "TRUE"
);
port
(
-- high-speed PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
async_rst : in std_logic;
--User Port0 Interface Signals
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0) ;
p0_cmd_bl : in std_logic_vector(5 downto 0) ;
p0_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
-- Data Wr Port signals
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0) ;
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0) ;
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
--Data Rd Port signals
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0) ;
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0) ;
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
--User Port1 Interface Signals
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0) ;
p1_cmd_bl : in std_logic_vector(5 downto 0) ;
p1_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
-- Data Wr Port signals
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0) ;
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0) ;
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
--Data Rd Port signals
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0) ;
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0) ;
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
--User Port2 Interface Signals
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0) ;
p2_cmd_bl : in std_logic_vector(5 downto 0) ;
p2_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
--Data Wr Port signals
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0) ;
p2_wr_data : in std_logic_vector(31 downto 0) ;
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0) ;
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
--User Port3 Interface Signals
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0) ;
p3_cmd_bl : in std_logic_vector(5 downto 0) ;
p3_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
--Data Rd Port signals
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0) ;
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0) ;
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
--User Port4 Interface Signals
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0) ;
p4_cmd_bl : in std_logic_vector(5 downto 0) ;
p4_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
--Data Wr Port signals
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0) ;
p4_wr_data : in std_logic_vector(31 downto 0) ;
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0) ;
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
--User Port5 Interface Signals
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0) ;
p5_cmd_bl : in std_logic_vector(5 downto 0) ;
p5_cmd_byte_addr : in std_logic_vector(29 downto 0) ;
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
--Data Rd Port signals
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0) ;
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0) ;
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
-- memory interface signals
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_a : out std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcb3_dram_dqs : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
-- Calibration signals
mcb_drp_clk : in std_logic;
calib_done : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end entity;
architecture acch of memc3_wrapper is
component mcb_raw_wrapper IS
GENERIC (
C_MEMCLK_PERIOD : integer;
C_PORT_ENABLE : std_logic_vector(5 downto 0);
C_MEM_ADDR_ORDER : string;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0);
C_PORT_CONFIG : string;
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_MOBILE_PA_SR : string;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR3_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR3_RTT : string;
C_MEM_MDDR_ODS : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_RA : bit_vector(15 DOWNTO 0);
C_MC_CALIBRATION_BA : bit_vector(2 DOWNTO 0);
C_CALIB_SOFT_IP : string;
C_MC_CALIBRATION_CA : bit_vector(11 DOWNTO 0);
C_MC_CALIBRATION_CLK_DIV : integer;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
LDQSP_TAP_DELAY_VAL : integer;
UDQSP_TAP_DELAY_VAL : integer;
LDQSN_TAP_DELAY_VAL : integer;
UDQSN_TAP_DELAY_VAL : integer;
DQ0_TAP_DELAY_VAL : integer;
DQ1_TAP_DELAY_VAL : integer;
DQ2_TAP_DELAY_VAL : integer;
DQ3_TAP_DELAY_VAL : integer;
DQ4_TAP_DELAY_VAL : integer;
DQ5_TAP_DELAY_VAL : integer;
DQ6_TAP_DELAY_VAL : integer;
DQ7_TAP_DELAY_VAL : integer;
DQ8_TAP_DELAY_VAL : integer;
DQ9_TAP_DELAY_VAL : integer;
DQ10_TAP_DELAY_VAL : integer;
DQ11_TAP_DELAY_VAL : integer;
DQ12_TAP_DELAY_VAL : integer;
DQ13_TAP_DELAY_VAL : integer;
DQ14_TAP_DELAY_VAL : integer;
DQ15_TAP_DELAY_VAL : integer;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_SIMULATION : string ;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_SKIP_DYN_IN_TERM : integer;
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0)
);
PORT (
-- HIGH-SPEED PLL clock interface
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p0_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p0_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 DOWNTO 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 DOWNTO 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 DOWNTO 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 DOWNTO 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p1_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p1_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 DOWNTO 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 DOWNTO 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 DOWNTO 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 DOWNTO 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p2_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p2_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 DOWNTO 0);
p2_wr_data : in std_logic_vector(31 DOWNTO 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 DOWNTO 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 DOWNTO 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 DOWNTO 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p3_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p3_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 DOWNTO 0);
p3_wr_data : in std_logic_vector(31 DOWNTO 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 DOWNTO 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 DOWNTO 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 DOWNTO 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p4_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p4_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 DOWNTO 0);
p4_wr_data : in std_logic_vector(31 DOWNTO 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 DOWNTO 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 DOWNTO 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 DOWNTO 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 DOWNTO 0);
p5_cmd_bl : in std_logic_vector(5 DOWNTO 0);
p5_cmd_byte_addr : in std_logic_vector(29 DOWNTO 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 DOWNTO 0);
p5_wr_data : in std_logic_vector(31 DOWNTO 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 DOWNTO 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 DOWNTO 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 DOWNTO 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 DOWNTO 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : inout std_logic_vector(C_NUM_DQ_PINS-1 DOWNTO 0);
mcbx_dram_dqs : inout std_logic;
mcbx_dram_dqs_n : inout std_logic;
mcbx_dram_udqs : inout std_logic;
mcbx_dram_udqs_n : inout std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : inout std_logic;
zio : inout std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 DOWNTO 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 DOWNTO 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 DOWNTO 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 DOWNTO 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
signal uo_data : std_logic_vector(7 downto 0);
constant C_PORT_ENABLE : std_logic_vector(5 downto 0) := "111111";
constant C_PORT_CONFIG : string := "B32_B32_W32_R32_W32_R32";
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_0(2 downto 0) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(14 downto 12) & C_ARB_TIME_SLOT_0(17 downto 15));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_1(2 downto 0) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(14 downto 12) & C_ARB_TIME_SLOT_1(17 downto 15));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_2(2 downto 0) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(14 downto 12) & C_ARB_TIME_SLOT_2(17 downto 15));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_3(2 downto 0) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(14 downto 12) & C_ARB_TIME_SLOT_3(17 downto 15));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_4(2 downto 0) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(14 downto 12) & C_ARB_TIME_SLOT_4(17 downto 15));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_5(2 downto 0) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(14 downto 12) & C_ARB_TIME_SLOT_5(17 downto 15));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_6(2 downto 0) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(14 downto 12) & C_ARB_TIME_SLOT_6(17 downto 15));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_7(2 downto 0) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(14 downto 12) & C_ARB_TIME_SLOT_7(17 downto 15));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_8(2 downto 0) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(14 downto 12) & C_ARB_TIME_SLOT_8(17 downto 15));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_9(2 downto 0) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(14 downto 12) & C_ARB_TIME_SLOT_9(17 downto 15));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_10(2 downto 0) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(14 downto 12) & C_ARB_TIME_SLOT_10(17 downto 15));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := (C_ARB_TIME_SLOT_11(2 downto 0) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(14 downto 12) & C_ARB_TIME_SLOT_11(17 downto 15));
constant C_MC_CALIBRATION_CLK_DIV : integer := 1;
constant C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000";
constant C_SKIP_DYN_IN_TERM : integer := 1;
constant C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
constant C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := o"0";
constant C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
signal status : std_logic_vector(31 downto 0);
signal uo_data_valid : std_logic;
signal uo_cmd_ready_in : std_logic;
signal uo_refrsh_flag : std_logic;
signal uo_cal_start : std_logic;
signal uo_sdo : std_logic;
signal mcb3_zio : std_logic;
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of acch : architecture IS
"mig_v3_5_ddr_s6, Coregen 12.2";
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of acch : architecture IS "mcb3_ddr_s6,mig_v3_5,{LANGUAGE=VHDL, SYNTHESIS_TOOL=ISE, NO_OF_CONTROLLERS=1, AXI_ENABLE=0, MEM_INTERFACE_TYPE=DDR_SDRAM,CLK_PERIOD=5000, MEMORY_PART=mt46v32m16xx-5b-it, OUTPUT_DRV=FULL, PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, MEM_ADDR_ORDER=ROW_BANK_COLUMN, PORT_ENABLE=Port0_Port1_Port2_Port3_Port4_Port5, CLASS_ADDR=II, CLASS_DATA=II, INPUT_PIN_TERMINATION=UNCALIB_TERM, DATA_TERMINATION=50 Ohms, CLKFBOUT_MULT_F=4, CLKOUT_DIVIDE=2, DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended}";
begin
memc3_mcb_raw_wrapper_inst : mcb_raw_wrapper
generic map
(
C_MEMCLK_PERIOD => C_MEMCLK_PERIOD,
C_P0_MASK_SIZE => C_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => ARB_TIME_SLOT_11,
C_PORT_CONFIG => C_PORT_CONFIG,
C_PORT_ENABLE => C_PORT_ENABLE,
C_MEM_TRAS => C_MEM_TRAS,
C_MEM_TRCD => C_MEM_TRCD,
C_MEM_TREFI => C_MEM_TREFI,
C_MEM_TRFC => C_MEM_TRFC,
C_MEM_TRP => C_MEM_TRP,
C_MEM_TWR => C_MEM_TWR,
C_MEM_TRTP => C_MEM_TRTP,
C_MEM_TWTR => C_MEM_TWTR,
C_MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C_NUM_DQ_PINS,
C_MEM_TYPE => C_MEM_TYPE,
C_MEM_DENSITY => C_MEM_DENSITY,
C_MEM_BURST_LEN => C_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C_MEM_MDDR_ODS,
C_MC_CALIBRATION_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C_MC_CALIBRATION_DELAY,
C_MC_CALIB_BYPASS => C_MC_CALIB_BYPASS,
C_MC_CALIBRATION_RA => C_MC_CALIBRATION_RA,
C_MC_CALIBRATION_BA => C_MC_CALIBRATION_BA,
C_MC_CALIBRATION_CA => C_MC_CALIBRATION_CA,
C_CALIB_SOFT_IP => C_CALIB_SOFT_IP,
C_SIMULATION => C_SIMULATION,
C_SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
C_SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
LDQSP_TAP_DELAY_VAL => C_LDQSP_TAP_DELAY_VAL,
UDQSP_TAP_DELAY_VAL => C_UDQSP_TAP_DELAY_VAL,
LDQSN_TAP_DELAY_VAL => C_LDQSN_TAP_DELAY_VAL,
UDQSN_TAP_DELAY_VAL => C_UDQSN_TAP_DELAY_VAL,
DQ0_TAP_DELAY_VAL => C_DQ0_TAP_DELAY_VAL,
DQ1_TAP_DELAY_VAL => C_DQ1_TAP_DELAY_VAL,
DQ2_TAP_DELAY_VAL => C_DQ2_TAP_DELAY_VAL,
DQ3_TAP_DELAY_VAL => C_DQ3_TAP_DELAY_VAL,
DQ4_TAP_DELAY_VAL => C_DQ4_TAP_DELAY_VAL,
DQ5_TAP_DELAY_VAL => C_DQ5_TAP_DELAY_VAL,
DQ6_TAP_DELAY_VAL => C_DQ6_TAP_DELAY_VAL,
DQ7_TAP_DELAY_VAL => C_DQ7_TAP_DELAY_VAL,
DQ8_TAP_DELAY_VAL => C_DQ8_TAP_DELAY_VAL,
DQ9_TAP_DELAY_VAL => C_DQ9_TAP_DELAY_VAL,
DQ10_TAP_DELAY_VAL => C_DQ10_TAP_DELAY_VAL,
DQ11_TAP_DELAY_VAL => C_DQ11_TAP_DELAY_VAL,
DQ12_TAP_DELAY_VAL => C_DQ12_TAP_DELAY_VAL,
DQ13_TAP_DELAY_VAL => C_DQ13_TAP_DELAY_VAL,
DQ14_TAP_DELAY_VAL => C_DQ14_TAP_DELAY_VAL,
DQ15_TAP_DELAY_VAL => C_DQ15_TAP_DELAY_VAL
)
port map
(
sys_rst => async_rst,
sysclk_2x => sysclk_2x,
sysclk_2x_180 => sysclk_2x_180,
pll_ce_0 => pll_ce_0,
pll_ce_90 => pll_ce_90,
pll_lock => pll_lock,
mcbx_dram_addr => mcb3_dram_a,
mcbx_dram_ba => mcb3_dram_ba,
mcbx_dram_ras_n => mcb3_dram_ras_n,
mcbx_dram_cas_n => mcb3_dram_cas_n,
mcbx_dram_we_n => mcb3_dram_we_n,
mcbx_dram_cke => mcb3_dram_cke,
mcbx_dram_clk => mcb3_dram_ck,
mcbx_dram_clk_n => mcb3_dram_ck_n,
mcbx_dram_dq => mcb3_dram_dq,
mcbx_dram_odt => open,
mcbx_dram_ldm => mcb3_dram_dm,
mcbx_dram_udm => mcb3_dram_udm,
mcbx_dram_dqs => mcb3_dram_dqs,
mcbx_dram_dqs_n => open,
mcbx_dram_udqs => mcb3_dram_udqs,
mcbx_dram_udqs_n => open,
mcbx_dram_ddr3_rst => open,
calib_recal => '0',
rzq => mcb3_rzq,
zio => mcb3_zio,
ui_read => '0',
ui_add => '0',
ui_cs => '0',
ui_clk => mcb_drp_clk,
ui_sdi => '0',
ui_addr => (others => '0'),
ui_broadcast => '0',
ui_drp_update => '0',
ui_done_cal => '1',
ui_cmd => '0',
ui_cmd_in => '0',
ui_cmd_en => '0',
ui_dqcount => (others => '0'),
ui_dq_lower_dec => '0',
ui_dq_lower_inc => '0',
ui_dq_upper_dec => '0',
ui_dq_upper_inc => '0',
ui_udqs_inc => '0',
ui_udqs_dec => '0',
ui_ldqs_inc => '0',
ui_ldqs_dec => '0',
uo_data => uo_data,
uo_data_valid => uo_data_valid,
uo_done_cal => calib_done,
uo_cmd_ready_in => uo_cmd_ready_in,
uo_refrsh_flag => uo_refrsh_flag,
uo_cal_start => uo_cal_start,
uo_sdo => uo_sdo,
status => status,
selfrefresh_enter => '0',
selfrefresh_mode => selfrefresh_mode,
p0_arb_en => '1',
p0_cmd_clk => p0_cmd_clk,
p0_cmd_en => p0_cmd_en,
p0_cmd_instr => p0_cmd_instr,
p0_cmd_bl => p0_cmd_bl,
p0_cmd_byte_addr => p0_cmd_byte_addr,
p0_cmd_empty => p0_cmd_empty,
p0_cmd_full => p0_cmd_full,
p0_wr_clk => p0_wr_clk,
p0_wr_en => p0_wr_en,
p0_wr_mask => p0_wr_mask,
p0_wr_data => p0_wr_data,
p0_wr_full => p0_wr_full,
p0_wr_empty => p0_wr_empty,
p0_wr_count => p0_wr_count,
p0_wr_underrun => p0_wr_underrun,
p0_wr_error => p0_wr_error,
p0_rd_clk => p0_rd_clk,
p0_rd_en => p0_rd_en,
p0_rd_data => p0_rd_data,
p0_rd_full => p0_rd_full,
p0_rd_empty => p0_rd_empty,
p0_rd_count => p0_rd_count,
p0_rd_overflow => p0_rd_overflow,
p0_rd_error => p0_rd_error,
p1_arb_en => '1',
p1_cmd_clk => p1_cmd_clk,
p1_cmd_en => p1_cmd_en,
p1_cmd_instr => p1_cmd_instr,
p1_cmd_bl => p1_cmd_bl,
p1_cmd_byte_addr => p1_cmd_byte_addr,
p1_cmd_empty => p1_cmd_empty,
p1_cmd_full => p1_cmd_full,
p1_wr_clk => p1_wr_clk,
p1_wr_en => p1_wr_en,
p1_wr_mask => p1_wr_mask,
p1_wr_data => p1_wr_data,
p1_wr_full => p1_wr_full,
p1_wr_empty => p1_wr_empty,
p1_wr_count => p1_wr_count,
p1_wr_underrun => p1_wr_underrun,
p1_wr_error => p1_wr_error,
p1_rd_clk => p1_rd_clk,
p1_rd_en => p1_rd_en,
p1_rd_data => p1_rd_data,
p1_rd_full => p1_rd_full,
p1_rd_empty => p1_rd_empty,
p1_rd_count => p1_rd_count,
p1_rd_overflow => p1_rd_overflow,
p1_rd_error => p1_rd_error,
p2_arb_en => '1',
p2_cmd_clk => p2_cmd_clk,
p2_cmd_en => p2_cmd_en,
p2_cmd_instr => p2_cmd_instr,
p2_cmd_bl => p2_cmd_bl,
p2_cmd_byte_addr => p2_cmd_byte_addr,
p2_cmd_empty => p2_cmd_empty,
p2_cmd_full => p2_cmd_full,
p2_rd_clk => '0',
p2_rd_en => '0',
p2_rd_data => open,
p2_rd_full => open,
p2_rd_empty => open,
p2_rd_count => open,
p2_rd_overflow => open,
p2_rd_error => open,
p2_wr_clk => p2_wr_clk,
p2_wr_en => p2_wr_en,
p2_wr_mask => p2_wr_mask,
p2_wr_data => p2_wr_data,
p2_wr_full => p2_wr_full,
p2_wr_empty => p2_wr_empty,
p2_wr_count => p2_wr_count,
p2_wr_underrun => p2_wr_underrun,
p2_wr_error => p2_wr_error,
p3_arb_en => '1',
p3_cmd_clk => p3_cmd_clk,
p3_cmd_en => p3_cmd_en,
p3_cmd_instr => p3_cmd_instr,
p3_cmd_bl => p3_cmd_bl,
p3_cmd_byte_addr => p3_cmd_byte_addr,
p3_cmd_empty => p3_cmd_empty,
p3_cmd_full => p3_cmd_full,
p3_rd_clk => p3_rd_clk,
p3_rd_en => p3_rd_en,
p3_rd_data => p3_rd_data,
p3_rd_full => p3_rd_full,
p3_rd_empty => p3_rd_empty,
p3_rd_count => p3_rd_count,
p3_rd_overflow => p3_rd_overflow,
p3_rd_error => p3_rd_error,
p3_wr_clk => '0',
p3_wr_en => '0',
p3_wr_mask => (others => '0'),
p3_wr_data => (others => '0'),
p3_wr_full => open,
p3_wr_empty => open,
p3_wr_count => open,
p3_wr_underrun => open,
p3_wr_error => open,
p4_arb_en => '1',
p4_cmd_clk => p4_cmd_clk,
p4_cmd_en => p4_cmd_en,
p4_cmd_instr => p4_cmd_instr,
p4_cmd_bl => p4_cmd_bl,
p4_cmd_byte_addr => p4_cmd_byte_addr,
p4_cmd_empty => p4_cmd_empty,
p4_cmd_full => p4_cmd_full,
p4_rd_clk => '0',
p4_rd_en => '0',
p4_rd_data => open,
p4_rd_full => open,
p4_rd_empty => open,
p4_rd_count => open,
p4_rd_overflow => open,
p4_rd_error => open,
p4_wr_clk => p4_wr_clk,
p4_wr_en => p4_wr_en,
p4_wr_mask => p4_wr_mask,
p4_wr_data => p4_wr_data,
p4_wr_full => p4_wr_full,
p4_wr_empty => p4_wr_empty,
p4_wr_count => p4_wr_count,
p4_wr_underrun => p4_wr_underrun,
p4_wr_error => p4_wr_error,
p5_arb_en => '1',
p5_cmd_clk => p5_cmd_clk,
p5_cmd_en => p5_cmd_en,
p5_cmd_instr => p5_cmd_instr,
p5_cmd_bl => p5_cmd_bl,
p5_cmd_byte_addr => p5_cmd_byte_addr,
p5_cmd_empty => p5_cmd_empty,
p5_cmd_full => p5_cmd_full,
p5_rd_clk => p5_rd_clk,
p5_rd_en => p5_rd_en,
p5_rd_data => p5_rd_data,
p5_rd_full => p5_rd_full,
p5_rd_empty => p5_rd_empty,
p5_rd_count => p5_rd_count,
p5_rd_overflow => p5_rd_overflow,
p5_rd_error => p5_rd_error,
p5_wr_clk => '0',
p5_wr_en => '0',
p5_wr_mask => (others => '0'),
p5_wr_data => (others => '0'),
p5_wr_full => open,
p5_wr_empty => open,
p5_wr_count => open,
p5_wr_underrun => open,
p5_wr_error => open
);
end architecture;
| gpl-3.0 | 58ae4abdf8b965057af398f21c507828 | 0.431058 | 3.466149 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/io_decode.vhd | 1 | 1,282 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:43:05 11/16/2015
-- Design Name:
-- Module Name: io_decode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity io_decode is
Port ( select_line : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (3 downto 0));
end io_decode;
architecture Behavioral of io_decode is
signal i_select : STD_LOGIC_VECTOR(3 downto 0);
begin
i_select <= "0001" when select_line = "00" else
"0010" when select_line = "01" else
"0100" when select_line = "10" else "1111";
data <= "0000" when en = '0' else i_select;
end Behavioral;
| unlicense | 4455acc30da2c0a0867dadf31d831590 | 0.584243 | 3.748538 | false | false | false | false |
ErikAndren/fpga-sramtest | ClkPll.vhd | 1 | 14,737 | -- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: ClkPll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ClkPll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END ClkPll;
ARCHITECTURE SYN OF clkpll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=ClkPll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "ClkPll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClkPll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClkPll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClkPll.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClkPll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClkPll.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClkPll_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
| mit | 6d801a9fe2af38a853cf5e59ccadfb1c | 0.70021 | 3.37154 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/proyecto-final/i2s_output.vhd | 1 | 2,363 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Generate I2S audio stream and master clock for the PMODI2S.
-- The chip is a Cirrus Logic CS4344 DAC
--
-- Drive with a 100MHz clock for 48,828 samples per second
--
-- 'accepted' will strobe when 'data_l' and 'data_r' are latched
--
-- 'data_l' and 'data_r' are assumed to be signed values.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2s_output is
Port ( clk : in STD_LOGIC;
data_l : in STD_LOGIC_VECTOR (15 downto 0);
data_r : in STD_LOGIC_VECTOR (15 downto 0);
accepted : out STD_LOGIC;
i2s_sd : out STD_LOGIC;
i2s_lrclk : out STD_LOGIC;
i2s_sclk : out STD_LOGIC;
i2s_mclk : out STD_LOGIC);
end i2s_output;
architecture Behavioral of i2s_output is
signal advance : std_logic := '0';
signal divider : unsigned( 4 downto 0) := (others => '0');
signal step : unsigned( 5 downto 0) := (others => '0');
signal shift_out : std_logic_vector(16 downto 0) := (others => '0');
signal hold_r : std_logic_vector(15 downto 0) := (others => '0');
begin
i2s_lrclk <= std_logic(step(5));
i2s_mclk <= std_logic(divider(1));
i2s_sclk <= std_logic(step(0));
i2s_sd <= shift_out(shift_out'high);
process(clk)
begin
if rising_edge(clk) then
accepted <= '0';
if advance = '1' then
if step(0) = '1' then
shift_out <= shift_out(shift_out'high-1 downto 0) & '1';
if step(5 downto 1) = "01111" then
shift_out(15 downto 0) <= hold_r;
elsif step(5 downto 1) = "11111" then
shift_out(15 downto 0) <= data_l xor x"8000";
hold_r <= data_r xor x"8000";
accepted <= '1';
end if;
end if;
step <= step + 1;
end if;
if divider = 0 then
advance <= '1';
else
advance <= '0';
end if;
divider <= divider + 1;
end if;
end process;
end Behavioral;
| mit | fb36545ad25347e0cc7f19455f021c91 | 0.484977 | 3.61315 | false | false | false | false |
aleksandar-mitrevski/hw_sw | jk_flip_flop/jk_flip_flop.vhd | 1 | 656 | library IEEE;
use IEEE.std_logic_1164.All;
entity JKFlipFlop is port (
clk : in std_logic;
j : in std_logic;
k : in std_logic;
q_out : inout std_logic;
q_not_out : inout std_logic);
end JKFlipFlop;
architecture arch_jkff of JKFlipFlop is
begin
jkff: process (clk)
begin
if rising_edge (clk) then
if j = '0' and k = '1' then
q_out <= '0';
elsif j = '1' and k = '0' then
q_out <= '1';
elsif j = '1' and k = '1' then
q_out <= q_not_out;
end if;
end if;
end process;
q_not_out <= Not (q_out);
end arch_jkff; | mit | 5bcc42a4e8c49ce42e7ab5a055737396 | 0.5 | 3.153846 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/clock_new.vhd | 1 | 3,050 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : clock_new.vhd
-- /___/ /\ Timestamp : 11/29/2015 17:48:01
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle C:/Users/Bailey/Desktop/Nibble_Knowledge_CPU(1)/ipcore_dir/clock_new.xaw -st clock_new.vhd
--Design Name: clock_new
--Device: xc3s250e-vq100-4
--
-- Module clock_new
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 9.54 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clock_new is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end clock_new;
architecture BEHAVIORAL of clock_new is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| unlicense | d139cdbc9644087d1a3bdd6944f32431 | 0.476721 | 3.737745 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/mcb_soft_calibration_top.vhd | 1 | 21,038 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:38 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;
| gpl-3.0 | 0ac69601dada17c88d8b24f57e650581 | 0.54625 | 4.096184 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/netgen/translate/CPU_translate.vhd | 1 | 101,012 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: CPU_translate.vhd
-- /___/ /\ Timestamp: Sat Oct 31 19:36:39 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -tm CPU -w -dir netgen/translate -ofmt vhdl -sim CPU.ngd CPU_translate.vhd
-- Device : 3s250evq100-5
-- Input file : CPU.ngd
-- Output file : C:\Users\Colton\Desktop\Nibble_Knowledge_CPU\netgen\translate\CPU_translate.vhd
-- # of Entities : 1
-- Design Name : CPU
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity CPU is
port (
clk : in STD_LOGIC := 'X';
clk_out : out STD_LOGIC;
ram_write_enable : out STD_LOGIC;
reset : in STD_LOGIC := 'X';
ram_data : inout STD_LOGIC_VECTOR ( 3 downto 0 );
a_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_address : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end CPU;
architecture Structure of CPU is
signal Intern_clock_hundredHzClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_hundredHzClock_i_zero_27 : STD_LOGIC;
signal Intern_clock_hundredHzClock_i_zero_or0000_28 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_30 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_0 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_1 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_10 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_11 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_12 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_13 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_14 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_2 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_3 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_4 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_5 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_6 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_7 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_8 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_9 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq0000 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000012_89 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000025_90 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000049_91 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000058_92 : STD_LOGIC;
signal Intern_clock_kiloHzClock_i_zero_93 : STD_LOGIC;
signal Intern_clock_kiloHzClock_i_zero_or0000 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero_103 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero1 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero_or0000_105 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_tenHzClock_i_zero_114 : STD_LOGIC;
signal Intern_clock_tenHzClock_i_zero_or0000_115 : STD_LOGIC;
signal MEM_Mcount_i_nibbleCount : STD_LOGIC;
signal MEM_Mcount_i_nibbleCount1 : STD_LOGIC;
signal MEM_q_0_not0001 : STD_LOGIC;
signal MEM_q_10_not0001 : STD_LOGIC;
signal MEM_q_12_not0001 : STD_LOGIC;
signal MEM_q_4_not0001 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N102 : STD_LOGIC;
signal N104 : STD_LOGIC;
signal N106 : STD_LOGIC;
signal N107 : STD_LOGIC;
signal N108 : STD_LOGIC;
signal N109 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N110 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N114 : STD_LOGIC;
signal N120 : STD_LOGIC;
signal N122 : STD_LOGIC;
signal N123 : STD_LOGIC;
signal N124 : STD_LOGIC;
signal N125 : STD_LOGIC;
signal N126 : STD_LOGIC;
signal N127 : STD_LOGIC;
signal N128 : STD_LOGIC;
signal N129 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N130 : STD_LOGIC;
signal N131 : STD_LOGIC;
signal N132 : STD_LOGIC;
signal N133 : STD_LOGIC;
signal N134 : STD_LOGIC;
signal N135 : STD_LOGIC;
signal N32 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N38 : STD_LOGIC;
signal N39 : STD_LOGIC;
signal N41 : STD_LOGIC;
signal N42 : STD_LOGIC;
signal N44 : STD_LOGIC;
signal N45 : STD_LOGIC;
signal N47 : STD_LOGIC;
signal N49 : STD_LOGIC;
signal N50 : STD_LOGIC;
signal N56 : STD_LOGIC;
signal N57 : STD_LOGIC;
signal N58 : STD_LOGIC;
signal N59 : STD_LOGIC;
signal N64 : STD_LOGIC;
signal N65 : STD_LOGIC;
signal N67 : STD_LOGIC;
signal N69 : STD_LOGIC;
signal N70 : STD_LOGIC;
signal N72 : STD_LOGIC;
signal N73 : STD_LOGIC;
signal N75 : STD_LOGIC;
signal N76 : STD_LOGIC;
signal N78 : STD_LOGIC;
signal N79 : STD_LOGIC;
signal N81 : STD_LOGIC;
signal N82 : STD_LOGIC;
signal N84 : STD_LOGIC;
signal N85 : STD_LOGIC;
signal N87 : STD_LOGIC;
signal N88 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N90 : STD_LOGIC;
signal N91 : STD_LOGIC;
signal N93 : STD_LOGIC;
signal N95 : STD_LOGIC;
signal N96 : STD_LOGIC;
signal N98 : STD_LOGIC;
signal N99 : STD_LOGIC;
signal adder_16bit_N11 : STD_LOGIC;
signal adder_16bit_N3 : STD_LOGIC;
signal adder_16bit_N4 : STD_LOGIC;
signal adder_16bit_N5 : STD_LOGIC;
signal adder_16bit_bit11_cout_and0001 : STD_LOGIC;
signal adder_16bit_bit6_cout_and0001 : STD_LOGIC;
signal clk_BUFGP : STD_LOGIC;
signal cpu_alu_DECODER_N11 : STD_LOGIC;
signal cpu_alu_N0 : STD_LOGIC;
signal cpu_alu_N18 : STD_LOGIC;
signal cpu_alu_STAT_data_out_0_Q : STD_LOGIC;
signal cpu_alu_STAT_data_out_1_Q : STD_LOGIC;
signal cpu_alu_STAT_data_out_3_Q : STD_LOGIC;
signal cpu_alu_i_A_EN : STD_LOGIC;
signal cpu_alu_i_A_in_1_97 : STD_LOGIC;
signal cpu_alu_i_A_in_3_1 : STD_LOGIC;
signal cpu_alu_i_MSB_cin : STD_LOGIC;
signal cpu_alu_i_STAT_EN : STD_LOGIC;
signal cpu_alu_i_XORb_in_275 : STD_LOGIC;
signal cpu_alu_i_arith_S : STD_LOGIC;
signal cpu_alu_i_carry_in_277 : STD_LOGIC;
signal cpu_alu_i_stat_S : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter1 : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter2 : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter_val : STD_LOGIC;
signal cycle_control_unit_cycle_counter_or0000 : STD_LOGIC;
signal cycle_control_unit_exe_287 : STD_LOGIC;
signal cycle_control_unit_exe_mux0000 : STD_LOGIC;
signal cycle_control_unit_mem_en_289 : STD_LOGIC;
signal cycle_control_unit_mem_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_op_en_291 : STD_LOGIC;
signal cycle_control_unit_op_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_pc_en_293 : STD_LOGIC;
signal cycle_control_unit_pc_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_received_hlt_295 : STD_LOGIC;
signal cycle_control_unit_received_hlt_0_not0000 : STD_LOGIC;
signal i_hlt : STD_LOGIC;
signal i_jmp : STD_LOGIC;
signal i_pc_en_after_or : STD_LOGIC;
signal i_pc_prime_10_19_306 : STD_LOGIC;
signal i_pc_prime_10_69 : STD_LOGIC;
signal i_pc_prime_10_691_308 : STD_LOGIC;
signal i_pc_prime_10_8_309 : STD_LOGIC;
signal i_pc_prime_14_9_314 : STD_LOGIC;
signal i_pc_prime_4_17_320 : STD_LOGIC;
signal i_pc_prime_5_30_322 : STD_LOGIC;
signal i_pc_prime_5_4_323 : STD_LOGIC;
signal i_pc_prime_7_1_326 : STD_LOGIC;
signal i_pc_prime_7_2_327 : STD_LOGIC;
signal i_pc_prime_8_1_329 : STD_LOGIC;
signal i_pc_prime_9_35 : STD_LOGIC;
signal i_pc_prime_9_9_332 : STD_LOGIC;
signal i_received_hlt_333 : STD_LOGIC;
signal ram_address_0_OBUF_350 : STD_LOGIC;
signal ram_address_10_OBUF_351 : STD_LOGIC;
signal ram_address_11_OBUF_352 : STD_LOGIC;
signal ram_address_12_OBUF_353 : STD_LOGIC;
signal ram_address_13_OBUF_354 : STD_LOGIC;
signal ram_address_14_OBUF_355 : STD_LOGIC;
signal ram_address_15_OBUF_356 : STD_LOGIC;
signal ram_address_1_OBUF_357 : STD_LOGIC;
signal ram_address_2_OBUF_358 : STD_LOGIC;
signal ram_address_3_OBUF_359 : STD_LOGIC;
signal ram_address_4_OBUF_360 : STD_LOGIC;
signal ram_address_5_OBUF_361 : STD_LOGIC;
signal ram_address_6_OBUF_362 : STD_LOGIC;
signal ram_address_7_OBUF_363 : STD_LOGIC;
signal ram_address_8_OBUF_364 : STD_LOGIC;
signal ram_address_9_OBUF_365 : STD_LOGIC;
signal ram_data_i_data_to_ram_not0000_inv : STD_LOGIC;
signal reset_IBUF_373 : STD_LOGIC;
signal reset_IBUF1 : STD_LOGIC;
signal i_pc_prime_12_SW1_O : STD_LOGIC;
signal i_pc_prime_13_SW1_O : STD_LOGIC;
signal i_pc_prime_0_SW0_O : STD_LOGIC;
signal cpu_alu_DECODER_WE_SW0_O : STD_LOGIC;
signal i_pc_prime_4_17_O : STD_LOGIC;
signal adder_16bit_bit1_Mxor_s_xo_0_11_SW1_O : STD_LOGIC;
signal adder_16bit_bit1_Mxor_s_xo_0_11_SW3_O : STD_LOGIC;
signal adder_16bit_bit3_Mxor_s_xo_0_11_SW1_O : STD_LOGIC;
signal adder_16bit_bit3_Mxor_s_xo_0_11_SW3_O : STD_LOGIC;
signal adder_16bit_bit3_Mxor_s_xo_0_11_SW5_O : STD_LOGIC;
signal i_pc_prime_14_35_SW0_O : STD_LOGIC;
signal i_pc_prime_2_12_SW1_F_O : STD_LOGIC;
signal cpu_alu_i_A_in_2_SW0_O : STD_LOGIC;
signal clk_BUFGP_IBUFG_2 : STD_LOGIC;
signal VCC : STD_LOGIC;
signal GND : STD_LOGIC;
signal Intern_clock_hundredHzClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Intern_clock_kiloHzClock_Mcount_current_count_cy : STD_LOGIC_VECTOR ( 13 downto 0 );
signal Intern_clock_kiloHzClock_Mcount_current_count_lut : STD_LOGIC_VECTOR ( 14 downto 1 );
signal Intern_clock_kiloHzClock_current_count : STD_LOGIC_VECTOR ( 14 downto 0 );
signal Intern_clock_oneHZClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Intern_clock_tenHzClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal MEM_i_nibbleCount : STD_LOGIC_VECTOR ( 1 downto 0 );
signal MEM_q : STD_LOGIC_VECTOR ( 15 downto 0 );
signal PCreg_q : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 14 downto 0 );
signal cpu_alu_A_data_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cpu_alu_DECODER_stored_OP_Code : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cpu_alu_i_A_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cycle_control_unit_cycle_counter : STD_LOGIC_VECTOR ( 2 downto 0 );
signal i_data_frm_ram : STD_LOGIC_VECTOR ( 3 downto 0 );
signal i_pc_prime : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
XST_GND : X_ZERO
port map (
O => N0
);
XST_VCC : X_ONE
port map (
O => N1
);
i_received_hlt : X_LATCHE
generic map(
INIT => '1'
)
port map (
I => N0,
CLK => reset_IBUF_373,
SET => i_hlt,
O => i_received_hlt_333,
GE => VCC,
RST => GND
);
Intern_clock_hundredHzClock_i_zero : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => N1,
SRST => Intern_clock_hundredHzClock_i_zero_or0000_28,
O => Intern_clock_hundredHzClock_i_zero_27,
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_tenHzClock_i_zero : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => N1,
SRST => Intern_clock_tenHzClock_i_zero_or0000_115,
O => Intern_clock_tenHzClock_i_zero_114,
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_oneHZClock_i_zero : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => N1,
SRST => Intern_clock_oneHZClock_i_zero_or0000_105,
O => Intern_clock_oneHZClock_i_zero1,
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_i_zero : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => N1,
SRST => Intern_clock_kiloHzClock_i_zero_or0000,
O => Intern_clock_kiloHzClock_i_zero_93,
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_hundredHzClock_current_count_0 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_kiloHzClock_i_zero_93,
I => Intern_clock_hundredHzClock_Mcount_current_count,
SSET => reset_IBUF1,
O => Intern_clock_hundredHzClock_current_count(0),
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_hundredHzClock_current_count_1 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_kiloHzClock_i_zero_93,
I => Intern_clock_hundredHzClock_Mcount_current_count1,
SRST => reset_IBUF1,
O => Intern_clock_hundredHzClock_current_count(1),
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_hundredHzClock_current_count_2 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_kiloHzClock_i_zero_93,
I => Intern_clock_hundredHzClock_Mcount_current_count2,
SRST => reset_IBUF1,
O => Intern_clock_hundredHzClock_current_count(2),
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_hundredHzClock_current_count_3 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_kiloHzClock_i_zero_93,
I => Intern_clock_hundredHzClock_Mcount_current_count3,
SSET => reset_IBUF1,
O => Intern_clock_hundredHzClock_current_count(3),
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_tenHzClock_current_count_0 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_hundredHzClock_i_zero_27,
I => Intern_clock_tenHzClock_Mcount_current_count,
SSET => reset_IBUF1,
O => Intern_clock_tenHzClock_current_count(0),
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_tenHzClock_current_count_1 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_hundredHzClock_i_zero_27,
I => Intern_clock_tenHzClock_Mcount_current_count1,
SRST => reset_IBUF1,
O => Intern_clock_tenHzClock_current_count(1),
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_tenHzClock_current_count_2 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_hundredHzClock_i_zero_27,
I => Intern_clock_tenHzClock_Mcount_current_count2,
SRST => reset_IBUF1,
O => Intern_clock_tenHzClock_current_count(2),
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_tenHzClock_current_count_3 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_hundredHzClock_i_zero_27,
I => Intern_clock_tenHzClock_Mcount_current_count3,
SSET => reset_IBUF1,
O => Intern_clock_tenHzClock_current_count(3),
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_oneHZClock_current_count_0 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_tenHzClock_i_zero_114,
I => Intern_clock_oneHZClock_Mcount_current_count,
SSET => reset_IBUF1,
O => Intern_clock_oneHZClock_current_count(0),
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_oneHZClock_current_count_1 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_tenHzClock_i_zero_114,
I => Intern_clock_oneHZClock_Mcount_current_count1,
SRST => reset_IBUF1,
O => Intern_clock_oneHZClock_current_count(1),
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_oneHZClock_current_count_2 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_tenHzClock_i_zero_114,
I => Intern_clock_oneHZClock_Mcount_current_count2,
SRST => reset_IBUF1,
O => Intern_clock_oneHZClock_current_count(2),
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_oneHZClock_current_count_3 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
CE => Intern_clock_tenHzClock_i_zero_114,
I => Intern_clock_oneHZClock_Mcount_current_count3,
SSET => reset_IBUF1,
O => Intern_clock_oneHZClock_current_count(3),
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_0 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_0,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(0),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_1 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_1,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(1),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_2 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_2,
SRST => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(2),
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_current_count_3 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_3,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(3),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_4 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_4,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(4),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_5 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_5,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(5),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_6 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_6,
SRST => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(6),
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_current_count_7 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_7,
SRST => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(7),
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_current_count_8 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_8,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(8),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_9 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_9,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(9),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_10 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_10,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(10),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_11 : X_SFF
generic map(
INIT => '1'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_11,
SSET => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(11),
CE => VCC,
SET => GND,
RST => GND,
SRST => GND
);
Intern_clock_kiloHzClock_current_count_12 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_12,
SRST => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(12),
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_current_count_13 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_13,
SRST => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(13),
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_current_count_14 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => clk_BUFGP,
I => Intern_clock_kiloHzClock_Mcount_current_count_eqn_14,
SRST => reset_IBUF1,
O => Intern_clock_kiloHzClock_current_count(14),
CE => VCC,
SET => GND,
RST => GND,
SSET => GND
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_0_Q : X_MUX2
port map (
IB => N1,
IA => N0,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_30,
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_0_Q : X_XOR2
port map (
I0 => N1,
I1 => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_30,
O => Result(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_1_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(0),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(1),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_1_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(0),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(1),
O => Result(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_2_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(1),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(2),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_2_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(1),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(2),
O => Result(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_3_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(2),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(3),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_3_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(2),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(3),
O => Result(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_4_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(3),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(4),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_4_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(3),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(4),
O => Result(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_5_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(4),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(5),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_5_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(4),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(5),
O => Result(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_6_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(5),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(6),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_6_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(5),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(6),
O => Result(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_7_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(6),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(7),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_7_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(6),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(7),
O => Result(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_8_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(7),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(8),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_8_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(7),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(8),
O => Result(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_9_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(8),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(9),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_9_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(8),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(9),
O => Result(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_10_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(9),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(10),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_10_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(9),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(10),
O => Result(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_11_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(10),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(11),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_11_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(10),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(11),
O => Result(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_12_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(11),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(12),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_12_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(11),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(12),
O => Result(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_13_Q : X_MUX2
port map (
IB => Intern_clock_kiloHzClock_Mcount_current_count_cy(12),
IA => N1,
SEL => Intern_clock_kiloHzClock_Mcount_current_count_lut(13),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_13_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(12),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(13),
O => Result(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_14_Q : X_XOR2
port map (
I0 => Intern_clock_kiloHzClock_Mcount_current_count_cy(13),
I1 => Intern_clock_kiloHzClock_Mcount_current_count_lut(14),
O => Result(14)
);
PCreg_q_15 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(15),
O => PCreg_q(15),
SET => GND
);
PCreg_q_14 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(14),
O => PCreg_q(14),
SET => GND
);
PCreg_q_13 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(13),
O => PCreg_q(13),
SET => GND
);
PCreg_q_12 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(12),
O => PCreg_q(12),
SET => GND
);
PCreg_q_11 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(11),
O => PCreg_q(11),
SET => GND
);
PCreg_q_10 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(10),
O => PCreg_q(10),
SET => GND
);
PCreg_q_9 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(9),
O => PCreg_q(9),
SET => GND
);
PCreg_q_8 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(8),
O => PCreg_q(8),
SET => GND
);
PCreg_q_7 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(7),
O => PCreg_q(7),
SET => GND
);
PCreg_q_6 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(6),
O => PCreg_q(6),
SET => GND
);
PCreg_q_5 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(5),
O => PCreg_q(5),
SET => GND
);
PCreg_q_4 : X_FF
generic map(
INIT => '1'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
I => i_pc_prime(4),
SET => reset_IBUF1,
O => PCreg_q(4),
RST => GND
);
PCreg_q_3 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(3),
O => PCreg_q(3),
SET => GND
);
PCreg_q_2 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
RST => reset_IBUF1,
I => i_pc_prime(2),
O => PCreg_q(2),
SET => GND
);
PCreg_q_1 : X_FF
generic map(
INIT => '1'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
I => i_pc_prime(1),
SET => reset_IBUF1,
O => PCreg_q(1),
RST => GND
);
PCreg_q_0 : X_FF
generic map(
INIT => '1'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => i_pc_en_after_or,
I => i_pc_prime(0),
SET => reset_IBUF1,
O => PCreg_q(0),
RST => GND
);
MEM_i_nibbleCount_1 : X_FF
generic map(
INIT => '1'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cycle_control_unit_mem_en_289,
I => MEM_Mcount_i_nibbleCount1,
SET => reset_IBUF1,
O => MEM_i_nibbleCount(1),
RST => GND
);
MEM_i_nibbleCount_0 : X_FF
generic map(
INIT => '1'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cycle_control_unit_mem_en_289,
I => MEM_Mcount_i_nibbleCount,
SET => reset_IBUF1,
O => MEM_i_nibbleCount(0),
RST => GND
);
MEM_q_15 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_12_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(3),
O => MEM_q(15),
SET => GND
);
MEM_q_14 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_12_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(2),
O => MEM_q(14),
SET => GND
);
MEM_q_13 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_12_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(1),
O => MEM_q(13),
SET => GND
);
MEM_q_9 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_10_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(1),
O => MEM_q(9),
SET => GND
);
MEM_q_12 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_12_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(0),
O => MEM_q(12),
SET => GND
);
MEM_q_8 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_10_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(0),
O => MEM_q(8),
SET => GND
);
MEM_q_11 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_10_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(3),
O => MEM_q(11),
SET => GND
);
MEM_q_7 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_4_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(3),
O => MEM_q(7),
SET => GND
);
MEM_q_10 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_10_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(2),
O => MEM_q(10),
SET => GND
);
MEM_q_6 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_4_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(2),
O => MEM_q(6),
SET => GND
);
MEM_q_5 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_4_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(1),
O => MEM_q(5),
SET => GND
);
MEM_q_4 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_4_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(0),
O => MEM_q(4),
SET => GND
);
MEM_q_3 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_0_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(3),
O => MEM_q(3),
SET => GND
);
MEM_q_1 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_0_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(1),
O => MEM_q(1),
SET => GND
);
MEM_q_0 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_0_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(0),
O => MEM_q(0),
SET => GND
);
MEM_q_2 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => MEM_q_0_not0001,
RST => reset_IBUF1,
I => i_data_frm_ram(2),
O => MEM_q(2),
SET => GND
);
cycle_control_unit_cycle_counter_1 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_Mcount_cycle_counter_val,
I => cycle_control_unit_Mcount_cycle_counter1,
O => cycle_control_unit_cycle_counter(1),
CE => VCC,
SET => GND
);
cycle_control_unit_cycle_counter_0 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_cycle_counter_or0000,
I => cycle_control_unit_Mcount_cycle_counter,
SET => reset_IBUF1,
O => cycle_control_unit_cycle_counter(0),
CE => VCC
);
cycle_control_unit_cycle_counter_2 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_Mcount_cycle_counter_val,
I => cycle_control_unit_Mcount_cycle_counter2,
O => cycle_control_unit_cycle_counter(2),
CE => VCC,
SET => GND
);
cycle_control_unit_received_hlt : X_LATCHE
generic map(
INIT => '0'
)
port map (
RST => reset_IBUF1,
I => N1,
CLK => i_hlt,
GE => cycle_control_unit_received_hlt_0_not0000,
O => cycle_control_unit_received_hlt_295,
SET => GND
);
cycle_control_unit_op_en : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_cycle_counter_or0000,
I => cycle_control_unit_op_en_mux0000,
SET => reset_IBUF1,
O => cycle_control_unit_op_en_291,
CE => VCC
);
cycle_control_unit_exe : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_Mcount_cycle_counter_val,
I => cycle_control_unit_exe_mux0000,
O => cycle_control_unit_exe_287,
CE => VCC,
SET => GND
);
cycle_control_unit_mem_en : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_Mcount_cycle_counter_val,
I => cycle_control_unit_mem_en_mux0000,
O => cycle_control_unit_mem_en_289,
CE => VCC,
SET => GND
);
cycle_control_unit_pc_en : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
RST => cycle_control_unit_cycle_counter_or0000,
I => cycle_control_unit_pc_en_mux0000,
SET => reset_IBUF1,
O => cycle_control_unit_pc_en_293,
CE => VCC
);
cpu_alu_DECODER_stored_OP_Code_0 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cycle_control_unit_op_en_291,
I => i_data_frm_ram(0),
O => cpu_alu_DECODER_stored_OP_Code(0),
SET => GND,
RST => GND
);
cpu_alu_DECODER_stored_OP_Code_1 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cycle_control_unit_op_en_291,
I => i_data_frm_ram(1),
O => cpu_alu_DECODER_stored_OP_Code(1),
SET => GND,
RST => GND
);
cpu_alu_DECODER_stored_OP_Code_2 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cycle_control_unit_op_en_291,
I => i_data_frm_ram(2),
O => cpu_alu_DECODER_stored_OP_Code(2),
SET => GND,
RST => GND
);
cpu_alu_DECODER_stored_OP_Code_3 : X_FF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cycle_control_unit_op_en_291,
I => i_data_frm_ram(3),
O => cpu_alu_DECODER_stored_OP_Code(3),
SET => GND,
RST => GND
);
cpu_alu_STAT_data_out_0 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_STAT_EN,
I => cpu_alu_i_carry_in_277,
SRST => reset_IBUF1,
O => cpu_alu_STAT_data_out_0_Q,
SET => GND,
RST => GND,
SSET => GND
);
cpu_alu_STAT_data_out_1 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_STAT_EN,
I => i_hlt,
SRST => reset_IBUF1,
O => cpu_alu_STAT_data_out_1_Q,
SET => GND,
RST => GND,
SSET => GND
);
cpu_alu_STAT_data_out_3 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_STAT_EN,
I => cpu_alu_i_XORb_in_275,
SRST => reset_IBUF1,
O => cpu_alu_STAT_data_out_3_Q,
SET => GND,
RST => GND,
SSET => GND
);
cycle_control_unit_cycle_counter_or00001 : X_LUT3
generic map(
INIT => X"32"
)
port map (
ADR0 => i_hlt,
ADR1 => reset_IBUF1,
ADR2 => cycle_control_unit_received_hlt_295,
O => cycle_control_unit_cycle_counter_or0000
);
cycle_control_unit_Mcount_cycle_counter_val1 : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => reset_IBUF1,
ADR1 => i_hlt,
ADR2 => cycle_control_unit_received_hlt_295,
O => cycle_control_unit_Mcount_cycle_counter_val
);
i_ram_address_9_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(9),
ADR2 => PCreg_q(9),
O => ram_address_9_OBUF_365
);
i_ram_address_8_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(8),
ADR2 => PCreg_q(8),
O => ram_address_8_OBUF_364
);
i_ram_address_7_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(7),
ADR2 => PCreg_q(7),
O => ram_address_7_OBUF_363
);
i_ram_address_6_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(6),
ADR2 => PCreg_q(6),
O => ram_address_6_OBUF_362
);
i_ram_address_5_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(5),
ADR2 => PCreg_q(5),
O => ram_address_5_OBUF_361
);
i_ram_address_4_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(4),
ADR2 => PCreg_q(4),
O => ram_address_4_OBUF_360
);
i_ram_address_3_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(3),
ADR2 => PCreg_q(3),
O => ram_address_3_OBUF_359
);
i_ram_address_2_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(2),
ADR2 => PCreg_q(2),
O => ram_address_2_OBUF_358
);
i_ram_address_1_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(1),
ADR2 => PCreg_q(1),
O => ram_address_1_OBUF_357
);
i_ram_address_15_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(15),
ADR2 => PCreg_q(15),
O => ram_address_15_OBUF_356
);
i_ram_address_14_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(14),
ADR2 => PCreg_q(14),
O => ram_address_14_OBUF_355
);
i_ram_address_13_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(13),
ADR2 => PCreg_q(13),
O => ram_address_13_OBUF_354
);
i_ram_address_12_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(12),
ADR2 => PCreg_q(12),
O => ram_address_12_OBUF_353
);
i_ram_address_11_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(11),
ADR2 => PCreg_q(11),
O => ram_address_11_OBUF_352
);
i_ram_address_10_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(10),
ADR2 => PCreg_q(10),
O => ram_address_10_OBUF_351
);
i_ram_address_0_1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => MEM_q(0),
ADR2 => PCreg_q(0),
O => ram_address_0_OBUF_350
);
MEM_Mcount_i_nibbleCount_xor_1_11 : X_LUT2
generic map(
INIT => X"9"
)
port map (
ADR0 => MEM_i_nibbleCount(0),
ADR1 => MEM_i_nibbleCount(1),
O => MEM_Mcount_i_nibbleCount1
);
cycle_control_unit_Mcount_cycle_counter_xor_2_11 : X_LUT3
generic map(
INIT => X"62"
)
port map (
ADR0 => cycle_control_unit_cycle_counter(2),
ADR1 => cycle_control_unit_cycle_counter(0),
ADR2 => cycle_control_unit_cycle_counter(1),
O => cycle_control_unit_Mcount_cycle_counter2
);
cycle_control_unit_Mcount_cycle_counter_xor_1_11 : X_LUT3
generic map(
INIT => X"26"
)
port map (
ADR0 => cycle_control_unit_cycle_counter(1),
ADR1 => cycle_control_unit_cycle_counter(0),
ADR2 => cycle_control_unit_cycle_counter(2),
O => cycle_control_unit_Mcount_cycle_counter1
);
cycle_control_unit_pc_en_mux00001 : X_LUT4
generic map(
INIT => X"BF1F"
)
port map (
ADR0 => cycle_control_unit_cycle_counter(1),
ADR1 => cycle_control_unit_cycle_counter(0),
ADR2 => cycle_control_unit_cycle_counter(2),
ADR3 => cycle_control_unit_pc_en_293,
O => cycle_control_unit_pc_en_mux0000
);
cycle_control_unit_exe_mux00001 : X_LUT4
generic map(
INIT => X"A280"
)
port map (
ADR0 => cycle_control_unit_cycle_counter(2),
ADR1 => cycle_control_unit_cycle_counter(1),
ADR2 => cycle_control_unit_exe_287,
ADR3 => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_exe_mux0000
);
cycle_control_unit_op_en_mux00001 : X_LUT4
generic map(
INIT => X"8091"
)
port map (
ADR0 => cycle_control_unit_cycle_counter(1),
ADR1 => cycle_control_unit_cycle_counter(2),
ADR2 => cycle_control_unit_op_en_291,
ADR3 => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_op_en_mux0000
);
Intern_clock_tenHzClock_Mcount_current_count_xor_1_11 : X_LUT4
generic map(
INIT => X"9998"
)
port map (
ADR0 => Intern_clock_tenHzClock_current_count(0),
ADR1 => Intern_clock_tenHzClock_current_count(1),
ADR2 => Intern_clock_tenHzClock_current_count(2),
ADR3 => Intern_clock_tenHzClock_current_count(3),
O => Intern_clock_tenHzClock_Mcount_current_count1
);
Intern_clock_oneHZClock_Mcount_current_count_xor_1_11 : X_LUT4
generic map(
INIT => X"9998"
)
port map (
ADR0 => Intern_clock_oneHZClock_current_count(0),
ADR1 => Intern_clock_oneHZClock_current_count(1),
ADR2 => Intern_clock_oneHZClock_current_count(2),
ADR3 => Intern_clock_oneHZClock_current_count(3),
O => Intern_clock_oneHZClock_Mcount_current_count1
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_1_11 : X_LUT4
generic map(
INIT => X"9998"
)
port map (
ADR0 => Intern_clock_hundredHzClock_current_count(0),
ADR1 => Intern_clock_hundredHzClock_current_count(1),
ADR2 => Intern_clock_hundredHzClock_current_count(2),
ADR3 => Intern_clock_hundredHzClock_current_count(3),
O => Intern_clock_hundredHzClock_Mcount_current_count1
);
Intern_clock_tenHzClock_Mcount_current_count_xor_2_11 : X_LUT4
generic map(
INIT => X"C9C8"
)
port map (
ADR0 => Intern_clock_tenHzClock_current_count(1),
ADR1 => Intern_clock_tenHzClock_current_count(2),
ADR2 => Intern_clock_tenHzClock_current_count(0),
ADR3 => Intern_clock_tenHzClock_current_count(3),
O => Intern_clock_tenHzClock_Mcount_current_count2
);
Intern_clock_oneHZClock_Mcount_current_count_xor_2_11 : X_LUT4
generic map(
INIT => X"C9C8"
)
port map (
ADR0 => Intern_clock_oneHZClock_current_count(1),
ADR1 => Intern_clock_oneHZClock_current_count(2),
ADR2 => Intern_clock_oneHZClock_current_count(0),
ADR3 => Intern_clock_oneHZClock_current_count(3),
O => Intern_clock_oneHZClock_Mcount_current_count2
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_2_11 : X_LUT4
generic map(
INIT => X"C9C8"
)
port map (
ADR0 => Intern_clock_hundredHzClock_current_count(1),
ADR1 => Intern_clock_hundredHzClock_current_count(2),
ADR2 => Intern_clock_hundredHzClock_current_count(0),
ADR3 => Intern_clock_hundredHzClock_current_count(3),
O => Intern_clock_hundredHzClock_Mcount_current_count2
);
cycle_control_unit_mem_en_mux00001 : X_LUT4
generic map(
INIT => X"BE36"
)
port map (
ADR0 => cycle_control_unit_cycle_counter(1),
ADR1 => cycle_control_unit_cycle_counter(2),
ADR2 => cycle_control_unit_cycle_counter(0),
ADR3 => cycle_control_unit_mem_en_289,
O => cycle_control_unit_mem_en_mux0000
);
Intern_clock_tenHzClock_Mcount_current_count_xor_3_11 : X_LUT4
generic map(
INIT => X"AAA9"
)
port map (
ADR0 => Intern_clock_tenHzClock_current_count(3),
ADR1 => Intern_clock_tenHzClock_current_count(1),
ADR2 => Intern_clock_tenHzClock_current_count(0),
ADR3 => Intern_clock_tenHzClock_current_count(2),
O => Intern_clock_tenHzClock_Mcount_current_count3
);
Intern_clock_oneHZClock_Mcount_current_count_xor_3_11 : X_LUT4
generic map(
INIT => X"AAA9"
)
port map (
ADR0 => Intern_clock_oneHZClock_current_count(3),
ADR1 => Intern_clock_oneHZClock_current_count(1),
ADR2 => Intern_clock_oneHZClock_current_count(0),
ADR3 => Intern_clock_oneHZClock_current_count(2),
O => Intern_clock_oneHZClock_Mcount_current_count3
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_3_11 : X_LUT4
generic map(
INIT => X"AAA9"
)
port map (
ADR0 => Intern_clock_hundredHzClock_current_count(3),
ADR1 => Intern_clock_hundredHzClock_current_count(1),
ADR2 => Intern_clock_hundredHzClock_current_count(0),
ADR3 => Intern_clock_hundredHzClock_current_count(2),
O => Intern_clock_hundredHzClock_Mcount_current_count3
);
MEM_q_4_not00011 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => MEM_i_nibbleCount(0),
ADR1 => MEM_i_nibbleCount(1),
ADR2 => cycle_control_unit_mem_en_289,
O => MEM_q_4_not0001
);
MEM_q_12_not00011 : X_LUT3
generic map(
INIT => X"80"
)
port map (
ADR0 => MEM_i_nibbleCount(1),
ADR1 => MEM_i_nibbleCount(0),
ADR2 => cycle_control_unit_mem_en_289,
O => MEM_q_12_not0001
);
MEM_q_10_not00011 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => MEM_i_nibbleCount(1),
ADR1 => MEM_i_nibbleCount(0),
ADR2 => cycle_control_unit_mem_en_289,
O => MEM_q_10_not0001
);
MEM_q_0_not00011 : X_LUT3
generic map(
INIT => X"04"
)
port map (
ADR0 => MEM_i_nibbleCount(1),
ADR1 => cycle_control_unit_mem_en_289,
ADR2 => MEM_i_nibbleCount(0),
O => MEM_q_0_not0001
);
Intern_clock_tenHzClock_i_zero_or0000_SW0 : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => Intern_clock_tenHzClock_current_count(3),
ADR1 => Intern_clock_tenHzClock_current_count(2),
ADR2 => reset_IBUF1,
O => N9
);
Intern_clock_tenHzClock_i_zero_or0000 : X_LUT4
generic map(
INIT => X"FFFB"
)
port map (
ADR0 => Intern_clock_tenHzClock_current_count(0),
ADR1 => Intern_clock_hundredHzClock_i_zero_27,
ADR2 => Intern_clock_tenHzClock_current_count(1),
ADR3 => N9,
O => Intern_clock_tenHzClock_i_zero_or0000_115
);
Intern_clock_oneHZClock_i_zero_or0000_SW0 : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => Intern_clock_oneHZClock_current_count(3),
ADR1 => Intern_clock_oneHZClock_current_count(2),
ADR2 => reset_IBUF1,
O => N11
);
Intern_clock_oneHZClock_i_zero_or0000 : X_LUT4
generic map(
INIT => X"FFFB"
)
port map (
ADR0 => Intern_clock_oneHZClock_current_count(1),
ADR1 => Intern_clock_tenHzClock_i_zero_114,
ADR2 => Intern_clock_oneHZClock_current_count(0),
ADR3 => N11,
O => Intern_clock_oneHZClock_i_zero_or0000_105
);
Intern_clock_hundredHzClock_i_zero_or0000_SW0 : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => Intern_clock_hundredHzClock_current_count(3),
ADR1 => Intern_clock_hundredHzClock_current_count(2),
ADR2 => reset_IBUF1,
O => N13
);
Intern_clock_hundredHzClock_i_zero_or0000 : X_LUT4
generic map(
INIT => X"FFFB"
)
port map (
ADR0 => Intern_clock_hundredHzClock_current_count(1),
ADR1 => Intern_clock_kiloHzClock_i_zero_93,
ADR2 => Intern_clock_hundredHzClock_current_count(0),
ADR3 => N13,
O => Intern_clock_hundredHzClock_i_zero_or0000_28
);
cpu_alu_DECODER_STAT_EN_and00001 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => cpu_alu_i_A_EN,
ADR1 => cpu_alu_DECODER_stored_OP_Code(2),
ADR2 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_i_STAT_EN
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_15 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(1),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_1
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_01 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(0),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_0
);
cpu_alu_DECODER_HLT_and00002 : X_LUT3
generic map(
INIT => X"04"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(2),
ADR1 => N128,
ADR2 => cpu_alu_DECODER_stored_OP_Code(1),
O => i_hlt
);
i_pc_en_after_or1 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => cycle_control_unit_pc_en_293,
ADR1 => i_jmp,
O => i_pc_en_after_or
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_21 : X_LUT2
generic map(
INIT => X"2"
)
port map (
ADR0 => Result(2),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_2
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_31 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(3),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_3
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_41 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(4),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_4
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_51 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(5),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_5
);
Intern_clock_kiloHzClock_i_zero_or00001 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
ADR1 => reset_IBUF1,
O => Intern_clock_kiloHzClock_i_zero_or0000
);
Intern_clock_kiloHzClock_current_count_cmp_eq000012 : X_LUT4
generic map(
INIT => X"0001"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count(1),
ADR1 => Intern_clock_kiloHzClock_current_count(14),
ADR2 => Intern_clock_kiloHzClock_current_count(2),
ADR3 => Intern_clock_kiloHzClock_current_count(3),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000012_89
);
Intern_clock_kiloHzClock_current_count_cmp_eq000025 : X_LUT4
generic map(
INIT => X"0001"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count(4),
ADR1 => Intern_clock_kiloHzClock_current_count(5),
ADR2 => Intern_clock_kiloHzClock_current_count(6),
ADR3 => Intern_clock_kiloHzClock_current_count(7),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000025_90
);
Intern_clock_kiloHzClock_current_count_cmp_eq000049 : X_LUT4
generic map(
INIT => X"0001"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count(8),
ADR1 => Intern_clock_kiloHzClock_current_count(9),
ADR2 => Intern_clock_kiloHzClock_current_count(10),
ADR3 => Intern_clock_kiloHzClock_current_count(11),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000049_91
);
Intern_clock_kiloHzClock_current_count_cmp_eq000058 : X_LUT3
generic map(
INIT => X"01"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count(12),
ADR1 => Intern_clock_kiloHzClock_current_count(13),
ADR2 => Intern_clock_kiloHzClock_current_count(0),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000058_92
);
Intern_clock_kiloHzClock_current_count_cmp_eq000071 : X_LUT4
generic map(
INIT => X"8000"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count_cmp_eq000012_89,
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq000025_90,
ADR2 => Intern_clock_kiloHzClock_current_count_cmp_eq000049_91,
ADR3 => Intern_clock_kiloHzClock_current_count_cmp_eq000058_92,
O => Intern_clock_kiloHzClock_current_count_cmp_eq0000
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_61 : X_LUT2
generic map(
INIT => X"2"
)
port map (
ADR0 => Result(6),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_6
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_71 : X_LUT2
generic map(
INIT => X"2"
)
port map (
ADR0 => Result(7),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_7
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_81 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(8),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_8
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_91 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(9),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_9
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_101 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(10),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_10
);
cpu_alu_DECODER_Stat_S_and00001 : X_LUT3
generic map(
INIT => X"80"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(1),
ADR1 => cpu_alu_DECODER_stored_OP_Code(2),
ADR2 => cpu_alu_i_A_EN,
O => cpu_alu_i_stat_S
);
i_pc_prime_6_1 : X_LUT4
generic map(
INIT => X"BE14"
)
port map (
ADR0 => i_jmp,
ADR1 => adder_16bit_bit6_cout_and0001,
ADR2 => PCreg_q(6),
ADR3 => MEM_q(6),
O => i_pc_prime(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_111 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => Result(11),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_11
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_121 : X_LUT2
generic map(
INIT => X"2"
)
port map (
ADR0 => Result(12),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_12
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_131 : X_LUT2
generic map(
INIT => X"2"
)
port map (
ADR0 => Result(13),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_13
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_141 : X_LUT2
generic map(
INIT => X"2"
)
port map (
ADR0 => Result(14),
ADR1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_14
);
i_data_frm_ram_3_LogicTrst1 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => ram_data_i_data_to_ram_not0000_inv,
ADR1 => N56,
O => i_data_frm_ram(3)
);
cpu_alu_DECODER_Arith_S_and000011 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => cycle_control_unit_exe_287,
ADR1 => cpu_alu_DECODER_stored_OP_Code(3),
ADR2 => cpu_alu_DECODER_stored_OP_Code(0),
O => cpu_alu_i_A_EN
);
cpu_alu_DECODER_Arith_S_and00001 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(2),
ADR1 => cpu_alu_DECODER_stored_OP_Code(1),
ADR2 => cpu_alu_i_A_EN,
O => cpu_alu_i_arith_S
);
i_pc_prime_11_1 : X_LUT4
generic map(
INIT => X"A3AC"
)
port map (
ADR0 => MEM_q(11),
ADR1 => PCreg_q(11),
ADR2 => i_jmp,
ADR3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(11)
);
i_pc_prime_9_9 : X_LUT4
generic map(
INIT => X"0080"
)
port map (
ADR0 => PCreg_q(6),
ADR1 => PCreg_q(7),
ADR2 => PCreg_q(8),
ADR3 => PCreg_q(9),
O => i_pc_prime_9_9_332
);
i_pc_prime_10_8 : X_LUT2
generic map(
INIT => X"7"
)
port map (
ADR0 => PCreg_q(8),
ADR1 => PCreg_q(9),
O => i_pc_prime_10_8_309
);
i_pc_prime_10_19 : X_LUT4
generic map(
INIT => X"DFFF"
)
port map (
ADR0 => PCreg_q(6),
ADR1 => i_pc_prime_10_8_309,
ADR2 => PCreg_q(7),
ADR3 => N130,
O => i_pc_prime_10_19_306
);
i_data_frm_ram_2_LogicTrst1 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => ram_data_i_data_to_ram_not0000_inv,
ADR1 => N57,
O => i_data_frm_ram(2)
);
i_pc_prime_12_SW0 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(12),
ADR2 => PCreg_q(12),
O => N32
);
i_pc_prime_12_Q : X_LUT4
generic map(
INIT => X"D8F0"
)
port map (
ADR0 => PCreg_q(11),
ADR1 => N33,
ADR2 => N32,
ADR3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(12)
);
i_pc_prime_13_SW0 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(13),
ADR2 => PCreg_q(13),
O => N38
);
i_pc_prime_13_Q : X_LUT4
generic map(
INIT => X"D8F0"
)
port map (
ADR0 => PCreg_q(12),
ADR1 => N39,
ADR2 => N38,
ADR3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(13)
);
i_data_frm_ram_1_LogicTrst1 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => ram_data_i_data_to_ram_not0000_inv,
ADR1 => N58,
O => i_data_frm_ram(1)
);
i_pc_prime_14_9 : X_LUT4
generic map(
INIT => X"0080"
)
port map (
ADR0 => PCreg_q(11),
ADR1 => PCreg_q(12),
ADR2 => PCreg_q(13),
ADR3 => PCreg_q(14),
O => i_pc_prime_14_9_314
);
i_pc_prime_15_SW0 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(15),
ADR2 => PCreg_q(15),
O => N41
);
i_pc_prime_15_SW1 : X_LUT3
generic map(
INIT => X"B1"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(15),
ADR2 => MEM_q(15),
O => N42
);
i_pc_prime_15_Q : X_LUT4
generic map(
INIT => X"CCE4"
)
port map (
ADR0 => PCreg_q(14),
ADR1 => N41,
ADR2 => N42,
ADR3 => N132,
O => i_pc_prime(15)
);
i_pc_prime_0_SW1 : X_LUT4
generic map(
INIT => X"EB41"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(14),
ADR2 => PCreg_q(0),
ADR3 => MEM_q(0),
O => N45
);
i_pc_prime_0_Q : X_LUT4
generic map(
INIT => X"CCE4"
)
port map (
ADR0 => PCreg_q(15),
ADR1 => N44,
ADR2 => N45,
ADR3 => adder_16bit_N5,
O => i_pc_prime(0)
);
i_data_frm_ram_0_LogicTrst1 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => ram_data_i_data_to_ram_not0000_inv,
ADR1 => N59,
O => i_data_frm_ram(0)
);
cpu_alu_DECODER_WE : X_LUT4
generic map(
INIT => X"FFFB"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(0),
ADR1 => cycle_control_unit_exe_287,
ADR2 => cpu_alu_DECODER_stored_OP_Code(2),
ADR3 => N47,
O => ram_data_i_data_to_ram_not0000_inv
);
i_pc_prime_1_SW1 : X_LUT4
generic map(
INIT => X"F3E2"
)
port map (
ADR0 => adder_16bit_N11,
ADR1 => i_jmp,
ADR2 => MEM_q(1),
ADR3 => PCreg_q(1),
O => N50
);
adder_16bit_bit6_Mxor_s_xo_0_31 : X_LUT3
generic map(
INIT => X"80"
)
port map (
ADR0 => PCreg_q(1),
ADR1 => N131,
ADR2 => PCreg_q(2),
O => adder_16bit_N4
);
adder_16bit_bit11_cout_and00011 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => PCreg_q(9),
ADR1 => N133,
ADR2 => PCreg_q(10),
O => adder_16bit_bit11_cout_and0001
);
i_pc_prime_5_4 : X_LUT2
generic map(
INIT => X"7"
)
port map (
ADR0 => PCreg_q(3),
ADR1 => PCreg_q(4),
O => i_pc_prime_5_4_323
);
i_pc_prime_5_30 : X_LUT4
generic map(
INIT => X"4000"
)
port map (
ADR0 => PCreg_q(5),
ADR1 => PCreg_q(4),
ADR2 => PCreg_q(3),
ADR3 => adder_16bit_N4,
O => i_pc_prime_5_30_322
);
reset_IBUF : X_BUF
port map (
I => reset,
O => reset_IBUF1
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt : X_LUT2
generic map(
INIT => X"A"
)
port map (
ADR0 => Intern_clock_kiloHzClock_current_count(0),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_30,
ADR1 => GND
);
i_pc_prime_3_SW0_SW0 : X_LUT4
generic map(
INIT => X"F3E2"
)
port map (
ADR0 => adder_16bit_N4,
ADR1 => i_jmp,
ADR2 => MEM_q(3),
ADR3 => PCreg_q(3),
O => N64
);
i_pc_prime_3_SW0_SW1 : X_LUT4
generic map(
INIT => X"AE04"
)
port map (
ADR0 => i_jmp,
ADR1 => adder_16bit_N4,
ADR2 => PCreg_q(3),
ADR3 => MEM_q(3),
O => N65
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW0 : X_LUT2
generic map(
INIT => X"8"
)
port map (
ADR0 => PCreg_q(15),
ADR1 => PCreg_q(14),
O => N67
);
i_pc_prime_5_18_SW1 : X_LUT4
generic map(
INIT => X"AFAC"
)
port map (
ADR0 => MEM_q(5),
ADR1 => PCreg_q(5),
ADR2 => i_jmp,
ADR3 => i_pc_prime_5_30_322,
O => N70
);
i_pc_prime_4_11_SW0 : X_LUT4
generic map(
INIT => X"AFAC"
)
port map (
ADR0 => MEM_q(4),
ADR1 => PCreg_q(4),
ADR2 => i_jmp,
ADR3 => i_pc_prime_4_17_320,
O => N72
);
cpu_alu_i_A_in_2_11 : X_LUT4
generic map(
INIT => X"8CEF"
)
port map (
ADR0 => N58,
ADR1 => cpu_alu_A_data_out(1),
ADR2 => ram_data_i_data_to_ram_not0000_inv,
ADR3 => N134,
O => cpu_alu_N0
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW2 : X_LUT4
generic map(
INIT => X"ABA8"
)
port map (
ADR0 => N129,
ADR1 => PCreg_q(14),
ADR2 => PCreg_q(0),
ADR3 => N50,
O => N79
);
i_pc_prime_1_Q : X_LUT4
generic map(
INIT => X"CCE4"
)
port map (
ADR0 => PCreg_q(15),
ADR1 => N78,
ADR2 => N79,
ADR3 => adder_16bit_N5,
O => i_pc_prime(1)
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW4 : X_LUT4
generic map(
INIT => X"ABA8"
)
port map (
ADR0 => N135,
ADR1 => PCreg_q(14),
ADR2 => PCreg_q(0),
ADR3 => N76,
O => N82
);
i_pc_prime_2_23 : X_LUT4
generic map(
INIT => X"CCE4"
)
port map (
ADR0 => PCreg_q(15),
ADR1 => N81,
ADR2 => N82,
ADR3 => adder_16bit_N5,
O => i_pc_prime(2)
);
i_pc_prime_3_Q : X_LUT4
generic map(
INIT => X"F0D8"
)
port map (
ADR0 => N67,
ADR1 => N85,
ADR2 => N84,
ADR3 => adder_16bit_N5,
O => i_pc_prime(3)
);
i_pc_prime_5_59 : X_LUT4
generic map(
INIT => X"F0D8"
)
port map (
ADR0 => N67,
ADR1 => N88,
ADR2 => N87,
ADR3 => adder_16bit_N5,
O => i_pc_prime(5)
);
i_pc_prime_4_40 : X_LUT4
generic map(
INIT => X"F0D8"
)
port map (
ADR0 => N67,
ADR1 => N91,
ADR2 => N90,
ADR3 => adder_16bit_N5,
O => i_pc_prime(4)
);
cpu_alu_JMP_SW0_SW0 : X_LUT4
generic map(
INIT => X"FFFE"
)
port map (
ADR0 => cpu_alu_A_data_out(3),
ADR1 => cpu_alu_A_data_out(2),
ADR2 => cpu_alu_A_data_out(1),
ADR3 => cpu_alu_A_data_out(0),
O => N93
);
cpu_alu_JMP : X_LUT4
generic map(
INIT => X"0080"
)
port map (
ADR0 => cpu_alu_DECODER_N11,
ADR1 => cpu_alu_DECODER_stored_OP_Code(1),
ADR2 => cpu_alu_DECODER_stored_OP_Code(2),
ADR3 => N93,
O => i_jmp
);
i_pc_prime_14_35_SW1 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(14),
O => N96
);
i_pc_prime_14_35 : X_LUT4
generic map(
INIT => X"D8F0"
)
port map (
ADR0 => PCreg_q(14),
ADR1 => N96,
ADR2 => N95,
ADR3 => adder_16bit_N5,
O => i_pc_prime(14)
);
i_pc_prime_5_18_SW0 : X_MUX2
port map (
IA => N98,
IB => N99,
SEL => i_pc_prime_5_30_322,
O => N69
);
i_pc_prime_5_18_SW0_F : X_LUT4
generic map(
INIT => X"AE04"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(5),
ADR2 => PCreg_q(2),
ADR3 => MEM_q(5),
O => N98
);
i_pc_prime_5_18_SW0_G : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(5),
O => N99
);
i_pc_prime_2_12_SW0_F : X_LUT3
generic map(
INIT => X"62"
)
port map (
ADR0 => PCreg_q(2),
ADR1 => PCreg_q(1),
ADR2 => adder_16bit_N11,
O => N102
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0 : X_MUX2
port map (
IA => N106,
IB => N107,
SEL => N65,
O => N84
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0_F : X_LUT4
generic map(
INIT => X"2AAA"
)
port map (
ADR0 => N64,
ADR1 => PCreg_q(0),
ADR2 => PCreg_q(2),
ADR3 => PCreg_q(1),
O => N106
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0_G : X_LUT4
generic map(
INIT => X"FF80"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => PCreg_q(2),
ADR2 => PCreg_q(1),
ADR3 => N64,
O => N107
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2 : X_MUX2
port map (
IA => N108,
IB => N109,
SEL => N69,
O => N87
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2_F : X_LUT4
generic map(
INIT => X"F700"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => PCreg_q(1),
ADR2 => i_pc_prime_5_4_323,
ADR3 => N70,
O => N108
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2_G : X_LUT4
generic map(
INIT => X"FF08"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => PCreg_q(1),
ADR2 => i_pc_prime_5_4_323,
ADR3 => N70,
O => N109
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4 : X_MUX2
port map (
IA => N110,
IB => N111,
SEL => N73,
O => N90
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4_F : X_LUT4
generic map(
INIT => X"7F00"
)
port map (
ADR0 => PCreg_q(2),
ADR1 => PCreg_q(0),
ADR2 => PCreg_q(1),
ADR3 => N72,
O => N110
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4_G : X_LUT4
generic map(
INIT => X"FF80"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => PCreg_q(2),
ADR2 => PCreg_q(1),
ADR3 => N72,
O => N111
);
cpu_alu_i_A_in_0_SW2 : X_LUT4
generic map(
INIT => X"7363"
)
port map (
ADR0 => N59,
ADR1 => cpu_alu_A_data_out(0),
ADR2 => ram_data_i_data_to_ram_not0000_inv,
ADR3 => cpu_alu_i_arith_S,
O => N114
);
cpu_alu_i_A_in_0_Q : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => cpu_alu_i_stat_S,
ADR1 => cpu_alu_STAT_data_out_0_Q,
ADR2 => N114,
O => cpu_alu_i_A_in(0)
);
cpu_alu_ADDER_cell_3_cout1 : X_LUT4
generic map(
INIT => X"EF8C"
)
port map (
ADR0 => N57,
ADR1 => cpu_alu_A_data_out(2),
ADR2 => ram_data_i_data_to_ram_not0000_inv,
ADR3 => cpu_alu_N0,
O => cpu_alu_i_MSB_cin
);
cpu_alu_i_A_in_2_Q : X_LUT4
generic map(
INIT => X"1333"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(2),
ADR1 => N120,
ADR2 => cpu_alu_i_A_EN,
ADR3 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_i_A_in(2)
);
i_pc_prime_2_12_SW11 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(2),
ADR2 => N104,
O => N76
);
i_pc_prime_4_11_SW1 : X_MUX2
port map (
IA => N122,
IB => N123,
SEL => adder_16bit_N4,
O => N73
);
i_pc_prime_4_11_SW1_F : X_LUT4
generic map(
INIT => X"AE04"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(4),
ADR2 => PCreg_q(3),
ADR3 => MEM_q(4),
O => N122
);
i_pc_prime_4_11_SW1_G : X_LUT4
generic map(
INIT => X"BE14"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(4),
ADR2 => PCreg_q(3),
ADR3 => MEM_q(4),
O => N123
);
cpu_alu_i_carry_in : X_MUX2
port map (
IA => N124,
IB => N125,
SEL => cpu_alu_i_MSB_cin,
O => cpu_alu_i_carry_in_277
);
cpu_alu_i_carry_in_F : X_LUT4
generic map(
INIT => X"EC20"
)
port map (
ADR0 => i_data_frm_ram(3),
ADR1 => i_hlt,
ADR2 => cpu_alu_A_data_out(3),
ADR3 => cpu_alu_STAT_data_out_0_Q,
O => N124
);
cpu_alu_i_carry_in_G : X_LUT4
generic map(
INIT => X"F3E2"
)
port map (
ADR0 => cpu_alu_A_data_out(3),
ADR1 => i_hlt,
ADR2 => cpu_alu_STAT_data_out_0_Q,
ADR3 => i_data_frm_ram(3),
O => N125
);
cpu_alu_i_XORb_in : X_MUX2
port map (
IA => N126,
IB => N127,
SEL => cpu_alu_i_MSB_cin,
O => cpu_alu_i_XORb_in_275
);
cpu_alu_i_XORb_in_F : X_LUT4
generic map(
INIT => X"F3E2"
)
port map (
ADR0 => cpu_alu_A_data_out(3),
ADR1 => i_hlt,
ADR2 => cpu_alu_STAT_data_out_3_Q,
ADR3 => i_data_frm_ram(3),
O => N126
);
cpu_alu_i_XORb_in_G : X_LUT4
generic map(
INIT => X"EC20"
)
port map (
ADR0 => i_data_frm_ram(3),
ADR1 => i_hlt,
ADR2 => cpu_alu_A_data_out(3),
ADR3 => cpu_alu_STAT_data_out_3_Q,
O => N127
);
Intern_clock_oneHZClock_i_zero_BUFG : X_CKBUF
port map (
I => Intern_clock_oneHZClock_i_zero1,
O => Intern_clock_oneHZClock_i_zero_103
);
reset_IBUF_BUFG : X_CKBUF
port map (
I => reset_IBUF1,
O => reset_IBUF_373
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_1_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(1),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_2_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(2),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_3_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(3),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_4_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(4),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_5_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(5),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_6_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(6),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_7_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(7),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_8_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(8),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_9_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(9),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_10_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(10),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_11_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(11),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_12_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(12),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_13_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(13),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_14_INV_0 : X_INV
port map (
I => Intern_clock_kiloHzClock_current_count(14),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(14)
);
cycle_control_unit_Mcount_cycle_counter_xor_0_11_INV_0 : X_INV
port map (
I => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_Mcount_cycle_counter
);
MEM_Mcount_i_nibbleCount_xor_0_11_INV_0 : X_INV
port map (
I => MEM_i_nibbleCount(0),
O => MEM_Mcount_i_nibbleCount
);
Intern_clock_tenHzClock_Mcount_current_count_xor_0_11_INV_0 : X_INV
port map (
I => Intern_clock_tenHzClock_current_count(0),
O => Intern_clock_tenHzClock_Mcount_current_count
);
Intern_clock_oneHZClock_Mcount_current_count_xor_0_11_INV_0 : X_INV
port map (
I => Intern_clock_oneHZClock_current_count(0),
O => Intern_clock_oneHZClock_Mcount_current_count
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_0_11_INV_0 : X_INV
port map (
I => Intern_clock_hundredHzClock_current_count(0),
O => Intern_clock_hundredHzClock_Mcount_current_count
);
cycle_control_unit_received_hlt_0_not00001_INV_0 : X_INV
port map (
I => cycle_control_unit_received_hlt_295,
O => cycle_control_unit_received_hlt_0_not0000
);
cpu_alu_A_data_out_3 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_A_EN,
I => cpu_alu_i_A_in(3),
SRST => reset_IBUF1,
O => cpu_alu_A_data_out(3),
SET => GND,
RST => GND,
SSET => GND
);
cpu_alu_A_data_out_2 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_A_EN,
I => cpu_alu_i_A_in(2),
SRST => reset_IBUF1,
O => cpu_alu_A_data_out(2),
SET => GND,
RST => GND,
SSET => GND
);
cpu_alu_A_data_out_1 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_A_EN,
I => cpu_alu_i_A_in(1),
SRST => reset_IBUF1,
O => cpu_alu_A_data_out(1),
SET => GND,
RST => GND,
SSET => GND
);
cpu_alu_A_data_out_0 : X_SFF
generic map(
INIT => '0'
)
port map (
CLK => Intern_clock_oneHZClock_i_zero_103,
CE => cpu_alu_i_A_EN,
I => cpu_alu_i_A_in(0),
SRST => reset_IBUF1,
O => cpu_alu_A_data_out(0),
SET => GND,
RST => GND,
SSET => GND
);
i_pc_prime_9_351 : X_LUT4
generic map(
INIT => X"F888"
)
port map (
ADR0 => adder_16bit_bit6_cout_and0001,
ADR1 => i_pc_prime_9_9_332,
ADR2 => adder_16bit_N3,
ADR3 => PCreg_q(9),
O => i_pc_prime_9_35
);
i_pc_prime_9_35_f5 : X_MUX2
port map (
IA => i_pc_prime_9_35,
IB => MEM_q(9),
SEL => i_jmp,
O => i_pc_prime(9)
);
i_pc_prime_10_691 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(10),
ADR2 => i_pc_prime_10_19_306,
O => i_pc_prime_10_69
);
i_pc_prime_10_692 : X_LUT4
generic map(
INIT => X"AE04"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(9),
ADR2 => adder_16bit_N3,
ADR3 => MEM_q(10),
O => i_pc_prime_10_691_308
);
i_pc_prime_10_69_f5 : X_MUX2
port map (
IA => i_pc_prime_10_691_308,
IB => i_pc_prime_10_69,
SEL => PCreg_q(10),
O => i_pc_prime(10)
);
cpu_alu_i_A_in_1_971 : X_LUT4
generic map(
INIT => X"5F69"
)
port map (
ADR0 => i_data_frm_ram(1),
ADR1 => cpu_alu_N18,
ADR2 => cpu_alu_A_data_out(1),
ADR3 => cpu_alu_i_arith_S,
O => cpu_alu_i_A_in_1_97
);
cpu_alu_i_A_in_1_97_f5 : X_MUX2
port map (
IA => cpu_alu_i_A_in_1_97,
IB => cpu_alu_STAT_data_out_1_Q,
SEL => cpu_alu_i_stat_S,
O => cpu_alu_i_A_in(1)
);
i_pc_prime_7_1 : X_LUT4
generic map(
INIT => X"BF15"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(6),
ADR2 => adder_16bit_bit6_cout_and0001,
ADR3 => MEM_q(7),
O => i_pc_prime_7_1_326
);
i_pc_prime_7_2 : X_LUT4
generic map(
INIT => X"EC20"
)
port map (
ADR0 => adder_16bit_bit6_cout_and0001,
ADR1 => i_jmp,
ADR2 => PCreg_q(6),
ADR3 => MEM_q(7),
O => i_pc_prime_7_2_327
);
i_pc_prime_7_f5 : X_MUX2
port map (
IA => i_pc_prime_7_2_327,
IB => i_pc_prime_7_1_326,
SEL => PCreg_q(7),
O => i_pc_prime(7)
);
i_pc_prime_8_1 : X_LUT4
generic map(
INIT => X"6AAA"
)
port map (
ADR0 => PCreg_q(8),
ADR1 => PCreg_q(6),
ADR2 => PCreg_q(7),
ADR3 => adder_16bit_bit6_cout_and0001,
O => i_pc_prime_8_1_329
);
i_pc_prime_8_f5 : X_MUX2
port map (
IA => i_pc_prime_8_1_329,
IB => MEM_q(8),
SEL => i_jmp,
O => i_pc_prime(8)
);
cpu_alu_i_A_in_3_11 : X_LUT4
generic map(
INIT => X"7796"
)
port map (
ADR0 => cpu_alu_A_data_out(3),
ADR1 => i_data_frm_ram(3),
ADR2 => cpu_alu_i_MSB_cin,
ADR3 => cpu_alu_i_arith_S,
O => cpu_alu_i_A_in_3_1
);
cpu_alu_i_A_in_3_1_f5 : X_MUX2
port map (
IA => cpu_alu_i_A_in_3_1,
IB => cpu_alu_STAT_data_out_3_Q,
SEL => cpu_alu_i_stat_S,
O => cpu_alu_i_A_in(3)
);
cpu_alu_DECODER_HLT_and000011_LUT3_D_BUF : X_BUF
port map (
I => cpu_alu_DECODER_N11,
O => N128
);
cpu_alu_DECODER_HLT_and000011 : X_LUT3
generic map(
INIT => X"04"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(0),
ADR1 => cycle_control_unit_exe_287,
ADR2 => cpu_alu_DECODER_stored_OP_Code(3),
O => cpu_alu_DECODER_N11
);
i_pc_prime_12_SW1_LUT3_L_BUF : X_BUF
port map (
I => i_pc_prime_12_SW1_O,
O => N33
);
i_pc_prime_12_SW1 : X_LUT3
generic map(
INIT => X"B1"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(12),
ADR2 => MEM_q(12),
O => i_pc_prime_12_SW1_O
);
i_pc_prime_13_SW1_LUT4_L_BUF : X_BUF
port map (
I => i_pc_prime_13_SW1_O,
O => N39
);
i_pc_prime_13_SW1 : X_LUT4
generic map(
INIT => X"BE14"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(13),
ADR2 => PCreg_q(11),
ADR3 => MEM_q(13),
O => i_pc_prime_13_SW1_O
);
i_pc_prime_0_SW0_LUT3_L_BUF : X_BUF
port map (
I => i_pc_prime_0_SW0_O,
O => N44
);
i_pc_prime_0_SW0 : X_LUT3
generic map(
INIT => X"B1"
)
port map (
ADR0 => i_jmp,
ADR1 => PCreg_q(0),
ADR2 => MEM_q(0),
O => i_pc_prime_0_SW0_O
);
cpu_alu_DECODER_WE_SW0_LUT2_L_BUF : X_BUF
port map (
I => cpu_alu_DECODER_WE_SW0_O,
O => N47
);
cpu_alu_DECODER_WE_SW0 : X_LUT2
generic map(
INIT => X"B"
)
port map (
ADR0 => cpu_alu_DECODER_stored_OP_Code(3),
ADR1 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_DECODER_WE_SW0_O
);
i_pc_prime_1_SW0_LUT4_D_BUF : X_BUF
port map (
I => N49,
O => N129
);
i_pc_prime_1_SW0 : X_LUT4
generic map(
INIT => X"AE04"
)
port map (
ADR0 => i_jmp,
ADR1 => adder_16bit_N11,
ADR2 => PCreg_q(1),
ADR3 => MEM_q(1),
O => N49
);
adder_16bit_bit6_cout_and00011_LUT4_D_BUF : X_BUF
port map (
I => adder_16bit_bit6_cout_and0001,
O => N130
);
adder_16bit_bit6_cout_and00011 : X_LUT4
generic map(
INIT => X"8000"
)
port map (
ADR0 => PCreg_q(5),
ADR1 => PCreg_q(3),
ADR2 => PCreg_q(4),
ADR3 => adder_16bit_N4,
O => adder_16bit_bit6_cout_and0001
);
adder_16bit_bit6_Mxor_s_xo_0_21_LUT4_D_BUF : X_BUF
port map (
I => adder_16bit_N11,
O => N131
);
adder_16bit_bit6_Mxor_s_xo_0_21 : X_LUT4
generic map(
INIT => X"AEAA"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => PCreg_q(15),
ADR2 => adder_16bit_N5,
ADR3 => PCreg_q(14),
O => adder_16bit_N11
);
adder_16bit_bit15_Mxor_s_xo_0_11_LUT4_D_BUF : X_BUF
port map (
I => adder_16bit_N5,
O => N132
);
adder_16bit_bit15_Mxor_s_xo_0_11 : X_LUT4
generic map(
INIT => X"7FFF"
)
port map (
ADR0 => adder_16bit_bit11_cout_and0001,
ADR1 => PCreg_q(11),
ADR2 => PCreg_q(12),
ADR3 => PCreg_q(13),
O => adder_16bit_N5
);
adder_16bit_bit11_Mxor_s_xo_0_11_LUT4_D_BUF : X_BUF
port map (
I => adder_16bit_N3,
O => N133
);
adder_16bit_bit11_Mxor_s_xo_0_11 : X_LUT4
generic map(
INIT => X"7FFF"
)
port map (
ADR0 => adder_16bit_bit6_cout_and0001,
ADR1 => PCreg_q(6),
ADR2 => PCreg_q(7),
ADR3 => PCreg_q(8),
O => adder_16bit_N3
);
i_pc_prime_4_17_LUT3_L_BUF : X_BUF
port map (
I => i_pc_prime_4_17_O,
O => i_pc_prime_4_17_320
);
i_pc_prime_4_17 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => PCreg_q(3),
ADR1 => PCreg_q(4),
ADR2 => adder_16bit_N4,
O => i_pc_prime_4_17_O
);
cpu_alu_i_A_in_1_231_LUT3_D_BUF : X_BUF
port map (
I => cpu_alu_N18,
O => N134
);
cpu_alu_i_A_in_1_231 : X_LUT3
generic map(
INIT => X"73"
)
port map (
ADR0 => N59,
ADR1 => cpu_alu_A_data_out(0),
ADR2 => ram_data_i_data_to_ram_not0000_inv,
O => cpu_alu_N18
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW1_LUT3_L_BUF : X_BUF
port map (
I => adder_16bit_bit1_Mxor_s_xo_0_11_SW1_O,
O => N78
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW1 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => N49,
ADR2 => N50,
O => adder_16bit_bit1_Mxor_s_xo_0_11_SW1_O
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW3_LUT3_L_BUF : X_BUF
port map (
I => adder_16bit_bit1_Mxor_s_xo_0_11_SW3_O,
O => N81
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW3 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => PCreg_q(0),
ADR1 => N75,
ADR2 => N76,
O => adder_16bit_bit1_Mxor_s_xo_0_11_SW3_O
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW1_LUT4_L_BUF : X_BUF
port map (
I => adder_16bit_bit3_Mxor_s_xo_0_11_SW1_O,
O => N85
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW1 : X_LUT4
generic map(
INIT => X"EC4C"
)
port map (
ADR0 => PCreg_q(2),
ADR1 => N64,
ADR2 => PCreg_q(1),
ADR3 => N65,
O => adder_16bit_bit3_Mxor_s_xo_0_11_SW1_O
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW3_LUT4_L_BUF : X_BUF
port map (
I => adder_16bit_bit3_Mxor_s_xo_0_11_SW3_O,
O => N88
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW3 : X_LUT4
generic map(
INIT => X"FB40"
)
port map (
ADR0 => i_pc_prime_5_4_323,
ADR1 => PCreg_q(1),
ADR2 => N69,
ADR3 => N70,
O => adder_16bit_bit3_Mxor_s_xo_0_11_SW3_O
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW5_LUT4_L_BUF : X_BUF
port map (
I => adder_16bit_bit3_Mxor_s_xo_0_11_SW5_O,
O => N91
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW5 : X_LUT4
generic map(
INIT => X"F780"
)
port map (
ADR0 => PCreg_q(2),
ADR1 => PCreg_q(1),
ADR2 => N73,
ADR3 => N72,
O => adder_16bit_bit3_Mxor_s_xo_0_11_SW5_O
);
i_pc_prime_14_35_SW0_LUT4_L_BUF : X_BUF
port map (
I => i_pc_prime_14_35_SW0_O,
O => N95
);
i_pc_prime_14_35_SW0 : X_LUT4
generic map(
INIT => X"ACA0"
)
port map (
ADR0 => MEM_q(14),
ADR1 => i_pc_prime_14_9_314,
ADR2 => i_jmp,
ADR3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime_14_35_SW0_O
);
i_pc_prime_2_12_SW1_F_LUT3_L_BUF : X_BUF
port map (
I => i_pc_prime_2_12_SW1_F_O,
O => N104
);
i_pc_prime_2_12_SW1_F : X_LUT3
generic map(
INIT => X"F8"
)
port map (
ADR0 => adder_16bit_N11,
ADR1 => PCreg_q(1),
ADR2 => PCreg_q(2),
O => i_pc_prime_2_12_SW1_F_O
);
cpu_alu_i_A_in_2_SW0_LUT4_L_BUF : X_BUF
port map (
I => cpu_alu_i_A_in_2_SW0_O,
O => N120
);
cpu_alu_i_A_in_2_SW0 : X_LUT4
generic map(
INIT => X"8689"
)
port map (
ADR0 => cpu_alu_A_data_out(2),
ADR1 => i_data_frm_ram(2),
ADR2 => cpu_alu_i_arith_S,
ADR3 => cpu_alu_N0,
O => cpu_alu_i_A_in_2_SW0_O
);
i_pc_prime_2_12_SW01_LUT3_D_BUF : X_BUF
port map (
I => N75,
O => N135
);
i_pc_prime_2_12_SW01 : X_LUT3
generic map(
INIT => X"D8"
)
port map (
ADR0 => i_jmp,
ADR1 => MEM_q(2),
ADR2 => N102,
O => N75
);
clk_BUFGP_BUFG : X_CKBUF
port map (
I => clk_BUFGP_IBUFG_2,
O => clk_BUFGP
);
clk_BUFGP_IBUFG : X_CKBUF
port map (
I => clk,
O => clk_BUFGP_IBUFG_2
);
ram_data_3_IOBUF_IBUF : X_BUF
port map (
I => ram_data(3),
O => N56
);
ram_data_2_IOBUF_IBUF : X_BUF
port map (
I => ram_data(2),
O => N57
);
ram_data_1_IOBUF_IBUF : X_BUF
port map (
I => ram_data(1),
O => N58
);
ram_data_0_IOBUF_IBUF : X_BUF
port map (
I => ram_data(0),
O => N59
);
a_data_0_OBUF : X_OBUF
port map (
I => cpu_alu_A_data_out(0),
O => a_data(0)
);
a_data_1_OBUF : X_OBUF
port map (
I => cpu_alu_A_data_out(1),
O => a_data(1)
);
a_data_2_OBUF : X_OBUF
port map (
I => cpu_alu_A_data_out(2),
O => a_data(2)
);
a_data_3_OBUF : X_OBUF
port map (
I => cpu_alu_A_data_out(3),
O => a_data(3)
);
clk_out_OBUF : X_OBUF
port map (
I => i_received_hlt_333,
O => clk_out
);
ram_address_0_OBUF : X_OBUF
port map (
I => ram_address_0_OBUF_350,
O => ram_address(0)
);
ram_address_10_OBUF : X_OBUF
port map (
I => ram_address_10_OBUF_351,
O => ram_address(10)
);
ram_address_11_OBUF : X_OBUF
port map (
I => ram_address_11_OBUF_352,
O => ram_address(11)
);
ram_address_12_OBUF : X_OBUF
port map (
I => ram_address_12_OBUF_353,
O => ram_address(12)
);
ram_address_13_OBUF : X_OBUF
port map (
I => ram_address_13_OBUF_354,
O => ram_address(13)
);
ram_address_14_OBUF : X_OBUF
port map (
I => ram_address_14_OBUF_355,
O => ram_address(14)
);
ram_address_15_OBUF : X_OBUF
port map (
I => ram_address_15_OBUF_356,
O => ram_address(15)
);
ram_address_1_OBUF : X_OBUF
port map (
I => ram_address_1_OBUF_357,
O => ram_address(1)
);
ram_address_2_OBUF : X_OBUF
port map (
I => ram_address_2_OBUF_358,
O => ram_address(2)
);
ram_address_3_OBUF : X_OBUF
port map (
I => ram_address_3_OBUF_359,
O => ram_address(3)
);
ram_address_4_OBUF : X_OBUF
port map (
I => ram_address_4_OBUF_360,
O => ram_address(4)
);
ram_address_5_OBUF : X_OBUF
port map (
I => ram_address_5_OBUF_361,
O => ram_address(5)
);
ram_address_6_OBUF : X_OBUF
port map (
I => ram_address_6_OBUF_362,
O => ram_address(6)
);
ram_address_7_OBUF : X_OBUF
port map (
I => ram_address_7_OBUF_363,
O => ram_address(7)
);
ram_address_8_OBUF : X_OBUF
port map (
I => ram_address_8_OBUF_364,
O => ram_address(8)
);
ram_address_9_OBUF : X_OBUF
port map (
I => ram_address_9_OBUF_365,
O => ram_address(9)
);
ram_data_0_IOBUF_OBUFT : X_OBUFT
port map (
I => cpu_alu_A_data_out(0),
CTL => ram_data_i_data_to_ram_not0000_inv,
O => ram_data(0)
);
ram_data_1_IOBUF_OBUFT : X_OBUFT
port map (
I => cpu_alu_A_data_out(1),
CTL => ram_data_i_data_to_ram_not0000_inv,
O => ram_data(1)
);
ram_data_2_IOBUF_OBUFT : X_OBUFT
port map (
I => cpu_alu_A_data_out(2),
CTL => ram_data_i_data_to_ram_not0000_inv,
O => ram_data(2)
);
ram_data_3_IOBUF_OBUFT : X_OBUFT
port map (
I => cpu_alu_A_data_out(3),
CTL => ram_data_i_data_to_ram_not0000_inv,
O => ram_data(3)
);
ram_write_enable_OBUF : X_OBUF
port map (
I => ram_data_i_data_to_ram_not0000_inv,
O => ram_write_enable
);
NlwBlock_CPU_VCC : X_ONE
port map (
O => VCC
);
NlwBlock_CPU_GND : X_ZERO
port map (
O => GND
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
| unlicense | e20cab62ef8484411c509784dbbb6063 | 0.556073 | 2.807995 | false | false | false | false |
sgstair/ledsign | firmware/matrixdriver/main.vhd | 1 | 15,436 | --
-- This source is released under the MIT License (MIT)
--
-- Copyright (c) 2016 Stephen Stair ([email protected])
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity main is
Port (
clk : in STD_LOGIC;
fpgaled : buffer std_logic;
led_r0 : out std_logic;
led_g0 : out std_logic;
led_b0 : out std_logic;
led_r1 : out std_logic;
led_g1 : out std_logic;
led_b1 : out std_logic;
led_A : out std_logic;
led_B : out std_logic;
led_C : out std_logic;
led_D : out std_logic;
led_OE : out std_logic;
led_STB : out std_logic;
led_CLK : out std_logic;
flash_clk : inout std_logic;
flash_mosi : inout std_logic;
flash_miso : inout std_logic;
dbgio1 : inout std_logic;
usb_dp : inout std_logic;
usb_dm : inout std_logic;
usb_connect : inout std_logic
);
end main;
architecture Behavioral of main is
component framebuffer is
Generic ( RamSizeBits : integer := 14 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
frame_addr : in unsigned( (RamSizeBits-1) downto 0);
frame_readdata : out std_logic_vector(31 downto 0);
access_addr : in unsigned ( (RamSizeBits-1) downto 0);
access_readdata : out std_logic_vector(31 downto 0);
access_writedata : in std_logic_vector(31 downto 0);
access_writeenable : in std_logic );
end component;
component usb_device is
Port ( clk : in STD_LOGIC;
usb_dp : inout STD_LOGIC;
usb_dm : inout STD_LOGIC;
usb_connect : inout std_logic;
syncreset : in STD_LOGIC;
interface_addr : out unsigned(15 downto 0);
interface_read : in std_logic_vector(31 downto 0);
interface_write : out std_logic_vector(31 downto 0);
interface_re : out std_logic;
interface_we : out std_logic;
trace_byte : out std_logic_vector(7 downto 0);
trace_pulse : out std_logic);
end component;
component tracefifo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
write_data : in std_logic_vector(7 downto 0);
write_pulse : in std_logic;
read_data : out std_logic_vector(7 downto 0);
has_data : out std_logic;
read_pulse : in std_logic );
end component;
signal usb_addr : unsigned(15 downto 0);
signal usb_readdata : std_logic_vector(31 downto 0);
signal usb_writedata : std_logic_vector(31 downto 0);
signal usb_re : std_logic;
signal usb_we : std_logic;
signal counter : unsigned(29 downto 0) := (others => '0');
signal syncreset : std_logic := '1';
signal syncresetcount : unsigned(3 downto 0) := X"1";
signal request_scanline : std_logic := '0';
signal scanline_working : std_logic := '0';
signal scanline_complete : std_logic := '0';
signal scanline_y : unsigned(3 downto 0) := (others => '0');
signal scanline_out_y : unsigned(3 downto 0) := (others => '0');
signal scanline_r0 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_g0 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_b0 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_r1 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_g1 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_b1 : std_logic_vector(9 downto 0) := (others => '0');
signal scanline_pixel : std_logic := '0';
signal bit_position : unsigned(3 downto 0) := (others => '0');
signal led_on_time : unsigned(7 downto 0) := X"10";
signal led_on_counter : unsigned(17 downto 0) := (others => '0');
signal start_oe : std_logic := '0';
signal oe_working : std_logic := '0';
signal oe_done : std_logic := '0';
type led_state_type is ( startoutput, output, display, advance );
signal waitcount : unsigned(3 downto 0);
signal led_state : led_state_type := startoutput;
signal display_completed : std_logic := '0';
signal frameread_addr : unsigned(13 downto 0);
signal frameread_data : std_logic_vector(31 downto 0);
signal frameaccess_addr : unsigned(13 downto 0);
signal frameaccess_readdata : std_logic_vector(31 downto 0);
signal frameaccess_writedata : std_logic_vector(31 downto 0);
signal frameaccess_writeenable :std_logic;
signal pixel_delay : unsigned(1 downto 0);
signal scanline_state : unsigned(2 downto 0);
signal dummy_timer : unsigned(19 downto 0);
type spi_mode_type is (command, writeaddress, writedata);
signal spibits : std_logic_vector(31 downto 0);
signal spibit : unsigned(4 downto 0);
signal spimode : spi_mode_type;
signal spioutbyte : std_logic_vector(7 downto 0);
signal spi_write_address : std_logic_vector(15 downto 0);
signal spi_write_data : std_logic_vector(23 downto 0);
signal spi_address_toggle : std_logic;
signal spi_data_toggle : std_logic;
signal spi_trace_toggle : std_logic;
signal address_toggle_buffer : std_logic_vector(4 downto 0);
signal data_toggle_buffer : std_logic_vector(4 downto 0);
signal trace_toggle_buffer : std_logic_vector(4 downto 0);
signal trace_write : std_logic_vector(7 downto 0);
signal trace_read : std_logic_vector(7 downto 0);
signal trace_write_pulse : std_logic;
signal trace_read_pulse : std_logic;
signal trace_has_data : std_logic;
begin
framebufferram: framebuffer
generic map ( RamSizeBits => 14 )
port map (
clk => clk,
reset => syncreset,
frame_addr => frameread_addr,
frame_readdata => frameread_data,
access_addr => frameaccess_addr,
access_readdata => frameaccess_readdata,
access_writedata => frameaccess_writedata,
access_writeenable => frameaccess_writeenable
);
usb_device_inst : usb_device
port map (
clk => clk,
usb_dp => usb_dp,
usb_dm => usb_dm,
usb_connect => usb_connect,
syncreset => syncreset,
interface_addr => usb_addr,
interface_read => usb_readdata,
interface_write => usb_writedata,
interface_re => usb_re,
interface_we => usb_we,
trace_byte => trace_write,
trace_pulse => trace_write_pulse
);
traceblock : tracefifo
Port map (
clk => clk,
reset => syncreset,
write_data => trace_write,
write_pulse => trace_write_pulse,
read_data => trace_read,
has_data => trace_has_data,
read_pulse => trace_read_pulse
);
fpgaled <= '0';
process(clk)
begin
if clk'event and clk = '1' then
counter <= counter + 1;
-- Generate reset
if syncresetcount = 0 then
syncreset <= '0';
else
syncreset <= '1';
syncresetcount <= syncresetcount + 1;
end if;
end if;
end process;
-- System to pull data from the framebuffer for LED panel, two pixels per 4 cycles
process(clk)
begin
if clk'event and clk = '1' then
scanline_pixel <= '0';
if request_scanline = '1' then
if scanline_working = '0' then
scanline_working <= '1';
-- Prepare to read data
frameread_addr <= "00000" & scanline_y & "00000";
pixel_delay <= "00";
else
if scanline_complete = '0' then
case pixel_delay is
when "00" =>
frameread_addr(10) <= '0';
when "01" =>
frameread_addr(10) <= '1';
scanline_r0 <= "00" & frameread_data(23 downto 16);
scanline_g0 <= "00" & frameread_data(15 downto 8);
scanline_b0 <= "00" & frameread_data(7 downto 0);
when "10" =>
scanline_r1 <= "00" & frameread_data(23 downto 16);
scanline_g1 <= "00" & frameread_data(15 downto 8);
scanline_b1 <= "00" & frameread_data(7 downto 0);
scanline_pixel <= '1';
-- Advance to next pixel.
frameread_addr(4 downto 0) <= frameread_addr(4 downto 0) + 1;
when "11" =>
if frameread_addr(4 downto 0) = "00000" then
scanline_complete <= '1';
end if;
when others =>
end case;
pixel_delay <= pixel_delay + 1;
end if;
end if;
else
scanline_complete <= '0';
scanline_working <= '0';
end if;
if syncreset = '1' then
scanline_complete <= '0';
scanline_working <= '0';
end if;
end if;
end process;
-- System to output scanline data into the LED matrix
process(clk)
begin
if clk'event and clk = '1' then
case scanline_state is
when "000" =>
led_clk <= '0';
when "001" =>
led_r0 <= scanline_r0(to_integer(bit_position));
led_g0 <= scanline_g0(to_integer(bit_position));
led_b0 <= scanline_b0(to_integer(bit_position));
led_r1 <= scanline_r1(to_integer(bit_position));
led_g1 <= scanline_g1(to_integer(bit_position));
led_b1 <= scanline_b1(to_integer(bit_position));
led_clk <= '0';
scanline_state <= "010";
when "010" =>
led_clk <= '1';
scanline_state <= "011";
when "011" =>
led_clk <= '1';
scanline_state <= "000";
when others =>
scanline_state <= "000";
end case;
if scanline_pixel = '1' then
scanline_state <= "001";
end if;
if syncreset = '1' then
led_r0 <= '0';
led_g0 <= '0';
led_b0 <= '0';
led_r1 <= '0';
led_g1 <= '0';
led_b1 <= '0';
led_clk <= '0';
scanline_state <= "000";
end if;
end if;
end process;
-- System to output enable for a specific number of cycles
led_d <= scanline_out_y(3);
led_c <= scanline_out_y(2);
led_b <= scanline_out_y(1);
led_a <= scanline_out_y(0);
led_oe <= not oe_working;
process(clk)
begin
if clk'event and clk = '1' then
oe_done <= '0';
if oe_working = '1' then
led_on_counter <= led_on_counter - 1;
if led_on_counter = 0 then
oe_done <= '1';
oe_working <= '0';
end if;
end if;
if start_oe = '1' then
case to_integer(bit_position) is
when 0 => led_on_counter <= "0000000000" & led_on_time;
when 1 => led_on_counter <= "000000000" & led_on_time & "0";
when 2 => led_on_counter <= "00000000" & led_on_time & "00";
when 3 => led_on_counter <= "0000000" & led_on_time & "000";
when 4 => led_on_counter <= "000000" & led_on_time & "0000";
when 5 => led_on_counter <= "00000" & led_on_time & "00000";
when 6 => led_on_counter <= "0000" & led_on_time & "000000";
when 7 => led_on_counter <= "000" & led_on_time & "0000000";
when others =>
led_on_counter <= "0000000000" & led_on_time;
end case;
oe_working <= '1';
end if;
if syncreset = '1' then
oe_working <= '0';
end if;
end if;
end process;
-- Coordinating state machine
process(clk)
begin
if clk'event and clk = '1' then
led_STB <= '0';
start_oe <= '0';
case led_state is
when startoutput =>
-- start pushing data into the display for a scanline
request_scanline <= '1';
led_state <= output;
when output =>
-- Wait until we're done with the scanline and the previous display
waitcount <= (others => '0');
if scanline_complete = '1' and oe_working = '0' then
request_scanline <= '0';
led_state <= display;
end if;
when display =>
-- Add a few cycles of delay to prevent any potential bleeding issues while latching data.
waitcount <= waitcount + 1;
case to_integer(waitcount) is
when 5 =>
-- Strobe to latch data, latch scanline out bits
led_STB <= '1';
scanline_out_y <= scanline_y;
when 10 =>
-- Start the display and move on to the next phase.
start_oe <= '1';
led_state <= advance;
when others =>
end case;
when advance =>
-- advance to the next bit position or scanline.
if bit_position = 7 then
scanline_y <= scanline_y + 1;
bit_position <= (others => '0');
else
bit_position <= bit_position + 1;
end if;
led_state <= startoutput;
when others =>
led_state <= startoutput;
end case;
if syncreset='1' then
led_state <= startoutput;
bit_position <= (others => '0');
scanline_y <= (others => '0');
scanline_out_y <= (others => '0');
waitcount <= (others => '0');
end if;
end if;
end process;
-- SPI interface
process(clk)
begin
if clk'event and clk = '1' then
frameaccess_writeenable <= '0';
trace_read_pulse <= '0';
address_toggle_buffer <= spi_address_toggle & address_toggle_buffer(4 downto 1);
data_toggle_buffer <= spi_data_toggle & data_toggle_buffer(4 downto 1);
trace_toggle_buffer <= spi_trace_toggle & trace_toggle_buffer(4 downto 1);
if trace_toggle_buffer(1) /= trace_toggle_buffer(0) then
trace_read_pulse <= '1';
end if;
if data_toggle_buffer(1) /= data_toggle_buffer(0) then
frameaccess_writedata <= X"00" & spi_write_data;
frameaccess_writeenable <= '1';
end if;
if frameaccess_writeenable = '1' then
frameaccess_addr <= frameaccess_addr + 1; -- Advance address on the next cycle.
end if;
if address_toggle_buffer(1) /= address_toggle_buffer(0) then
frameaccess_addr <= unsigned(spi_write_address(13 downto 0));
end if;
if syncreset = '1' then
address_toggle_buffer <= (others => '0');
data_toggle_buffer <= (others => '0');
end if;
end if;
end process;
spibits(0) <= flash_mosi;
flash_miso <= 'Z' when dbgio1 = '1' else spioutbyte(7);
process(flash_clk)
begin
if dbgio1 = '1' then -- CS signal is inactive
spibit <= (others => '0');
spioutbyte <= (others => '0');
spimode <= command;
elsif flash_clk'event and flash_clk = '1' then
spibits(31 downto 1) <= spibits(30 downto 0); -- Shift bits and prepare for next cycle.
spioutbyte <= spioutbyte(6 downto 0) & '0';
spibit <= spibit + 1;
case spimode is
when command =>
if spibit = 7 then
-- Decide what to do based on command in spibits(7 downto 0).
-- For now just treat all command bytes as a write data command.
spibit <= (others => '0');
spimode <= writeaddress;
end if;
when writeaddress =>
if spibit = 15 then
spi_write_address <= spibits(15 downto 0);
spibit <= (others => '0');
spi_address_toggle <= not spi_address_toggle;
spimode <= writedata;
end if;
when writedata =>
if spibit = 23 then
spi_write_data <= spibits(23 downto 0);
spibit <= (others => '0');
spi_data_toggle <= not spi_data_toggle;
end if;
when others =>
end case;
if spibit(2 downto 0) = 7 then
spi_trace_toggle <= not spi_trace_toggle;
spioutbyte <= trace_read;
end if;
end if;
end process;
end Behavioral;
| mit | bbef8678a2f19f356b07e75f7054bd43 | 0.630474 | 3.136761 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/downcounter.vhd | 1 | 1,480 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity downcounter is
Generic ( period: integer:= 4;
WIDTH: integer:= 3);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
zero : out STD_LOGIC;
value: out STD_LOGIC_VECTOR(WIDTH-1 downto 0));
end downcounter;
architecture Behavioral of downcounter is
signal current_count: std_logic_vector(WIDTH-1 downto 0);
signal i_zero: std_logic;
-- Convert the max counter to a logic vector (this is done during synthesis)
constant max_count: std_logic_vector(WIDTH-1 downto 0) :=
std_logic_vector(to_unsigned(period, WIDTH));
-- Create a logic vector of proper length filled with zeros (also done during synthesis)
constant zeros: std_logic_vector(WIDTH-1 downto 0) := (others => '0');
begin
count: process(clk,reset) begin
if (rising_edge(clk)) then
if (reset = '1') then -- Synchronous reset
current_count <= max_count;
i_zero <= '0';
elsif (enable = '1') then -- When counter is enabled
if (current_count = zeros) then
current_count <= max_count;
i_zero <= '1';
else
current_count <= current_count - '1';
i_zero <= '0';
end if;
else
i_zero <= '0';
end if;
end if;
end process;
-- Connect internal signals to output
value <= current_count;
zero <= i_zero; -- Connect internal signals to output
end Behavioral; | unlicense | a68d6b3ffa28838f7a627baee2bbf50b | 0.645946 | 3.115789 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_io_mapping.vhd | 1 | 4,108 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:01:55 11/20/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/Desktop/Nibble_Knowledge_CPU(1)/tb_io_mapping.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: io_mapping
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_io_mapping IS
END tb_io_mapping;
ARCHITECTURE behavior OF tb_io_mapping IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT io_mapping
PORT(
address : IN std_logic_vector(15 downto 0);
data_in : IN std_logic_vector(3 downto 0);
data_out : OUT std_logic_vector(3 downto 0);
ram_data : INOUT std_logic_vector(3 downto 0);
bus_chip_select : OUT std_logic_vector(3 downto 0);
store : IN std_logic;
bus_data : INOUT std_logic_vector(3 downto 0);
bus_ready : IN std_logic;
oe : OUT std_logic;
bus_parity : IN std_logic;
clk : IN std_logic;
rst : IN std_logic
);
END COMPONENT;
--Inputs
signal address : std_logic_vector(15 downto 0) := (others => '0');
signal data_in : std_logic_vector(3 downto 0) := (others => '0');
signal store : std_logic := '0';
signal bus_ready : std_logic := '0';
signal bus_parity : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--BiDirs
signal ram_data : std_logic_vector(3 downto 0);
signal bus_data : std_logic_vector(3 downto 0);
--Outputs
signal data_out : std_logic_vector(3 downto 0);
signal bus_chip_select : std_logic_vector(3 downto 0);
signal oe : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: io_mapping PORT MAP (
address => address,
data_in => data_in,
data_out => data_out,
ram_data => ram_data,
bus_chip_select => bus_chip_select,
store => store,
bus_data => bus_data,
bus_ready => bus_ready,
oe => oe,
bus_parity => bus_parity,
clk => clk,
rst => rst
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '1';
wait for clk_period*10;
rst <= '0';
-- Test that a store to status only write the lower 2 bits
wait for clk_period*5;
address <= "0000000000000001";
store <= '1';
data_in <= "1101";
-- Test that a read from data reads corretly
wait for clk_period*5;
store <= '0';
address <= "0000000000000010";
data_in <= "0010";
-- Test that a write to the data reg works while CPU is doing other things
wait for clk_period*5;
address <= "0000000100100011";
ram_data <= "0110";
bus_data <= "1011";
wait for clk_period*5;
bus_data <= "0101";
wait for clk_period*5;
bus_data <= "ZZZZ";
wait for clk_period*5;
address <= "0000000000000001";
store <= '1';
data_in <= "0000";
wait for clk_period*5;
store <= '0';
wait;
end process;
END;
| unlicense | da6e69818187ab349014eebaa0cd402f | 0.584226 | 3.56907 | false | true | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/demo_tb/tb_nco.vhd | 1 | 9,126 | ---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the DDS Compiler datasheet for further information about this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- named "nco".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile nco.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl nco.ngc nco_netlist.vhd
--
-- Compile nco_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_nco is
end tb_nco;
architecture tb of tb_nco is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data master channel alias signals
signal m_axis_data_tdata_cosine : std_logic_vector(9 downto 0) := (others => '0');
-- Alias signals for each separate TDM channel (these are 1 cycle delayed relative to the above alias signals)
signal m_axis_data_channel : integer := 0; -- indicates TDM channel number of data master channel outputs
signal m_axis_data_tdata_cosine_c0 : std_logic_vector(9 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c1 : std_logic_vector(9 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.nco
port map (
aclk => aclk
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Run for long enough to produce 5 periods of outputs
wait for CLOCK_PERIOD * 125018;
-- End of test
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_cosine <= m_axis_data_tdata(9 downto 0) when m_axis_data_tvalid = '1';
-- Data master channel alias signals for each TDM channel
-- Note that these are one cycle later than the overall data master channel signals
process (aclk)
begin
if rising_edge(aclk) then
if m_axis_data_tvalid = '1' then
if m_axis_data_channel = 1 then
m_axis_data_channel <= 0;
else
m_axis_data_channel <= m_axis_data_channel + 1;
end if;
if m_axis_data_channel = 0 then
m_axis_data_tdata_cosine_c0 <= m_axis_data_tdata(9 downto 0);
elsif m_axis_data_channel = 1 then
m_axis_data_tdata_cosine_c1 <= m_axis_data_tdata(9 downto 0);
end if;
end if;
end if;
end process;
end tb;
| mit | 2bcf77953eb850ed7cea6259e244eb05 | 0.574184 | 4.733402 | false | false | false | false |
NuclearKev/iir-hardware | fir.vhd | 1 | 2,980 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- ready : in std_logic;
done : out std_logic;
-- coefficient
i_coeff_0 : in std_logic_vector(14 downto 0);
i_coeff_1 : in std_logic_vector(14 downto 0);
i_coeff_2 : in std_logic_vector(14 downto 0);
i_coeff_3 : in std_logic_vector(14 downto 0);
-- data input
i_data : in std_logic_vector(11 downto 0);
-- filtered data
o_data : out std_logic_vector(11 downto 0));
end fir;
architecture Behavioral of fir is
type t_data_pipe is array (0 to 3) of signed(11 downto 0);
type t_coeff is array (0 to 3) of signed(14 downto 0);
type t_mult is array (0 to 3) of signed(26 downto 0);
type t_add_st0 is array (0 to 1) of signed(26+1 downto 0);
signal r_coeff : t_coeff ;
signal p_data : t_data_pipe;
signal r_mult : t_mult;
signal r_add_st0 : t_add_st0;
signal r_add_st1 : signed(26+2 downto 0);
begin
p_input : process (i_rstb,i_clk)
begin
if(i_rstb='1') then
p_data <= (others=>(others=>'0'));
r_coeff <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
r_coeff(0) <= signed(i_coeff_0);
r_coeff(1) <= signed(i_coeff_1);
r_coeff(2) <= signed(i_coeff_2);
r_coeff(3) <= signed(i_coeff_3);
end if;
end process p_input;
p_mult : process (i_rstb,i_clk,p_data,r_coeff)
begin
if(i_rstb='1') then
r_mult <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 3 loop
r_mult(k) <= p_data(k) * r_coeff(k);
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk,r_mult)
begin
if(i_rstb='1') then
r_add_st0 <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 1 loop
r_add_st0(k) <= resize(r_mult(2*k),28) + resize(r_mult(2*k+1),28);
end loop;
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk,r_add_st0)
begin
if(i_rstb='1') then
r_add_st1 <= (others=>'0');
elsif(i_clk='1') then
r_add_st1 <= resize(r_add_st0(0),29) + resize(r_add_st0(1),29);
end if;
end process p_add_st1;
p_output : process (i_rstb,i_clk,r_add_st1)
begin
done <= '0';
if(i_rstb='1') then
o_data <= (others=>'0');
done <= '0';
elsif(i_clk='1') then
done <= '1';
o_data <= std_logic_vector(r_add_st1(28 downto 17));
end if;
end process p_output;
-- p_done : process (i_rstb, i_clk)
-- begin
-- if(i_rstb='0') then
-- done <= '0';
-- elsif(rising_edge(i_clk)) then
-- done <= '1';
-- end if;
-- end process p_done;
end Behavioral;
| lgpl-3.0 | c47ef7962bd54a1346002fef0cc10376 | 0.527181 | 2.751616 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/ipcore_dir/fifo32.vhd | 1 | 10,257 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo32.vhd when simulating
-- the core, fifo32. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo32 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END fifo32;
ARCHITECTURE fifo32_a OF fifo32 IS
-- synthesis translate_off
COMPONENT wrapped_fifo32
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fifo32 USE ENTITY XilinxCoreLib.fifo_generator_v8_1(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 1,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo32
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
wr_data_count => wr_data_count
);
-- synthesis translate_on
END fifo32_a;
| mit | ab4965891070306c53ba3655df79cd05 | 0.536902 | 3.32372 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/RegisterBank/RegisterBank.vhd | 1 | 1,754 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: REGBank
-- Project Name: REGBank
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Register Bank
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ALL;
entity RegBank is
GENERIC (DATA_WIDTH:positive:=16; REG_SIZE:positive:=4);
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
-- Register A
RegA_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegA : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Register B
RegB_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegB : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Input Register
RegIN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
RegIN_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegIN_WE : in STD_LOGIC
);
end RegBank;
architecture Behavioral of RegBank is
type Reg_Array_Type is array (0 to 15) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal RegArray: Reg_Array_Type;
begin
--Reg A
RegA <= RegArray(to_integer(unsigned(RegA_Sel)));
--Reg B
RegB <= RegArray(to_integer(unsigned(RegB_Sel)));
process(RST,CLK)
begin
if (RST = '1') then
RegArray <= (OTHERS => (OTHERS => '0'));
elsif (clk'event and clk='1') then
if (RegIN_WE = '1') then
RegArray(to_integer(unsigned(RegIN_Sel))) <= RegIN;
end if;
end if;
end process;
end Behavioral;
| mit | f757299ec6dfc3acc35d2f2ad8ef57da | 0.584379 | 3.543434 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/memoria/example_design/memoria_exdes.vhd | 2 | 4,328 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: memoria_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memoria_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END memoria_exdes;
ARCHITECTURE xilinx OF memoria_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT memoria IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : memoria
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | 443330a55d73a7d25780196589d9072d | 0.575323 | 4.857464 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/sounds_mem/example_design/sounds_mem_exdes.vhd | 2 | 4,344 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: sounds_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY sounds_mem_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END sounds_mem_exdes;
ARCHITECTURE xilinx OF sounds_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT sounds_mem IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : sounds_mem
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | cf5525f8dcd755c495b963f2b4d22487 | 0.575506 | 4.778878 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/SREG_4.vhd | 1 | 2,299 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: GenReg_16
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Handout Code: Dr.Fortier(c)
-- 16 General Purpose Registers
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Incorporated a memory init [1]
--
-- Additional Comments:
-- [1]: code adaptive from the following blog
-- http://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html
-- this site pointed to XST user guide
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SREG_4 is
generic(
REGS_WIDTH: integer:=2; -- select between 4 different possible registers
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
SR_WE : in std_logic;
--RESETN : in std_logic;
--Register OUT
SR_SEL : in std_logic_vector(REGS_WIDTH-1 downto 0);
SR_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
SR_IN_SEL : in std_logic_vector(REGS_WIDTH-1 downto 0);
SR_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end SREG_4;
architecture REG_S_ARCH of SREG_4 is
type ram_type is array (0 to 2**REGS_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal ram: ram_type := (
x"000000", -- 0
x"000000", -- 1
x"000000", -- 2
x"000000" -- 3
);
signal ADDR_S_REG: std_logic_vector(REGS_WIDTH-1 downto 0);
begin
process(CLOCK,SR_WE)
begin
if (CLOCK'event and CLOCK = '0') then
if (SR_WE = '1') then
ram(to_integer(unsigned(SR_IN_SEL))) <= SR_IN;
end if;
ADDR_S_REG <= SR_IN_SEL;
end if;
end process;
SR_OUT <= ram(to_integer(unsigned(ADDR_S_REG)));
end REG_S_ARCH;
| mit | 182be8d4349616bf10c725e333a2279a | 0.552849 | 3.288984 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/iodrp_mcb_controller.vhd | 1 | 19,049 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
constant READY : std_logic_vector(3 downto 0) := "0000";
constant DECIDE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_PHASE : std_logic_vector(3 downto 0) := "0010";
constant ADDR_TO_DATA_GAP : std_logic_vector(3 downto 0) := "0011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(3 downto 0) := "0100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(3 downto 0) := "0101";
constant DATA_PHASE : std_logic_vector(3 downto 0) := "0110";
constant ALMOST_READY : std_logic_vector(3 downto 0) := "0111";
constant ALMOST_READY2 : std_logic_vector(3 downto 0) := "1001";
constant ALMOST_READY3 : std_logic_vector(3 downto 0) := "1010";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state : std_logic_vector(3 downto 0);
signal nextstate : std_logic_vector(3 downto 0);
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 | 1ff8d9ec5f02a95683dba63a55b6b201 | 0.545908 | 3.713979 | false | false | false | false |
NuclearKev/iir-hardware | dmux.vhd | 1 | 2,150 | --------------------------------------------------------------------------------
-- Copyright (C) 2017 Kevin Bloom <kdb5pct.edu>
--
-- This program is free software: you can redistribute it and/or modify it under
-- the terms of the Lesser GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option) any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the Lesser GNU General Public License for more
-- details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description:
--
-- This IP was created as a part of the IIR Hardware proect. It will send the
-- input to one of the outputs based on the select.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dmux is
Port ( i_select : in STD_LOGIC_VECTOR(7 downto 0);
i : in STD_LOGIC;
o_0 : out STD_LOGIC;
o_1 : out STD_LOGIC;
o_2 : out STD_LOGIC;
o_3 : out STD_LOGIC;
o_4 : out STD_LOGIC;
o_5 : out STD_LOGIC;
o_6 : out STD_LOGIC;
o_7 : out STD_LOGIC);
end dmux;
architecture Behavioral of dmux is
begin
p_dmux : process (i_select)
begin
case i_select is
when x"00" =>
o_0 <= i;
when x"01" =>
o_1 <= i;
when x"02" =>
o_2 <= i;
when x"03" =>
o_3 <= i;
when x"04" =>
o_4 <= i;
when x"05" =>
o_5 <= i;
when x"06" =>
o_6 <= i;
when x"07" =>
o_7 <= i;
when others =>
-- do nothing
end case;
end process;
end Behavioral;
| lgpl-3.0 | 60359b1fb036eaad8ccd959493c3d190 | 0.487442 | 4.095238 | false | false | false | false |
NuclearKev/iir-hardware | temp.vhd | 1 | 2,665 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fir_filter_4 is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- coefficient
i_coeff_0 : in std_logic_vector( 7 downto 0);
i_coeff_1 : in std_logic_vector( 7 downto 0);
i_coeff_2 : in std_logic_vector( 7 downto 0);
i_coeff_3 : in std_logic_vector( 7 downto 0);
-- data input
i_data : in std_logic_vector( 7 downto 0);
-- filtered data
o_data : out std_logic_vector( 9 downto 0));
end fir_filter_4;
architecture rtl of fir_filter_4 is
type t_data_pipe is array (0 to 3) of signed(7 downto 0);
type t_coeff is array (0 to 3) of signed(7 downto 0);
type t_mult is array (0 to 3) of signed(15 downto 0);
type t_add_st0 is array (0 to 1) of signed(15+1 downto 0);
signal r_coeff : t_coeff ;
signal p_data : t_data_pipe;
signal r_mult : t_mult;
signal r_add_st0 : t_add_st0;
signal r_add_st1 : signed(15+2 downto 0);
begin
p_input : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
p_data <= (others=>(others=>'0'));
r_coeff <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
r_coeff(0) <= signed(i_coeff_0);
r_coeff(1) <= signed(i_coeff_1);
r_coeff(2) <= signed(i_coeff_2);
r_coeff(3) <= signed(i_coeff_3);
end if;
end process p_input;
p_mult : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
r_mult <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
for k in 0 to 3 loop
r_mult(k) <= p_data(k) * r_coeff(k);
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
r_add_st0 <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
for k in 0 to 1 loop
r_add_st0(k) <= resize(r_mult(2*k),17) + resize(r_mult(2*k+1),17);
end loop;
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
r_add_st1 <= (others=>'0');
elsif(rising_edge(i_clk)) then
r_add_st1 <= resize(r_add_st0(0),18) + resize(r_add_st0(1),18);
end if;
end process p_add_st1;
p_output : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
o_data <= (others=>'0');
elsif(rising_edge(i_clk)) then
o_data <= std_logic_vector(r_add_st1(17 downto 8));
end if;
end process p_output;
end rtl;
| lgpl-3.0 | 1c6dfd8bb9f2a10a022cb8ba2962ad02 | 0.539962 | 2.778936 | false | false | false | false |
sgstair/ledsign | firmware/matrixdriver/usb_device.vhd | 1 | 38,877 | --
-- This source is released under the MIT License (MIT)
--
-- Copyright (c) 2016 Stephen Stair ([email protected])
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity usb_device is
Port ( clk : in std_logic;
usb_dp : inout std_logic;
usb_dm : inout std_logic;
usb_connect : inout std_logic;
syncreset : in std_logic;
interface_addr : out unsigned(15 downto 0);
interface_read : in std_logic_vector(31 downto 0);
interface_write : out std_logic_vector(31 downto 0);
interface_re : out std_logic; -- Request read; Data will be present on the 2nd cycle after re was high
interface_we : out std_logic; -- Request write; address/write data will be latched and written.
trace_byte : out std_logic_vector(7 downto 0);
trace_pulse : out std_logic
);
end usb_device;
architecture Behavioral of usb_device is
component usb_phy is
port (
sysclk : in std_logic;
rst : in std_logic;
-- USB Physical interface
usb_dp : inout std_logic;
usb_dm : inout std_logic;
-- USB Reset
usb_reset : out std_logic; -- Indication that we received a reset signal
usb_hold_reset : in std_logic; -- Hold reset of the lower level high until this layer says it's ok to continue.
-- Transmit interface
usbtx_byte : in std_logic_vector(7 downto 0);
usbtx_sendbyte : in std_logic;
usbtx_lastbyte : in std_logic;
usbtxs_cansend : out std_logic;
usbtxs_abort : out std_logic;
usbtxs_sending : out std_logic;
usbtxs_underrunerror : out std_logic;
-- Receive interface
usbrx_byte : out std_logic_vector(7 downto 0);
usbrx_nextbyte : out std_logic;
usbrx_packetend : out std_logic;
usbrx_crcerror : out std_logic;
usbrx_bitstufferror : out std_logic;
usbrx_eopmissing : out std_logic;
usbrx_piderror : out std_logic;
usbrx_incomplete : out std_logic;
usbrx_syncerror : out std_logic;
usbrx_error : out std_logic
);
end component;
signal usb_reset : std_logic;
signal usb_hold_reset : std_logic;
signal usbtx_byte : std_logic_vector(7 downto 0);
signal usbtx_sendbyte : std_logic;
signal usbtx_lastbyte : std_logic;
signal usbtxs_cansend : std_logic;
signal usbtxs_abort : std_logic;
signal usbtxs_sending : std_logic;
signal usbtxs_underrunerror : std_logic;
signal usbrx_byte : std_logic_vector(7 downto 0);
signal usbrx_nextbyte : std_logic;
signal usbrx_packetend : std_logic;
signal usbrx_crcerror : std_logic;
signal usbrx_bitstufferror : std_logic;
signal usbrx_eopmissing : std_logic;
signal usbrx_piderror : std_logic;
signal usbrx_incomplete : std_logic;
signal usbrx_syncerror : std_logic;
signal usbrx_error : std_logic;
signal romaddr : unsigned(10 downto 0);
signal romdata : std_logic_vector(7 downto 0);
signal ramwritedata : std_logic_vector(7 downto 0);
signal ramwriteenable : std_logic;
signal ramreadaddr : unsigned(10 downto 0);
signal ramreaddata : std_logic_vector(7 downto 0);
type usb_state_type is (idle, ignore, ignoreack, setup1, setup2, out1, out2, in1, in2, setupdata, senddelay, sendstart, preoutdata, outdata, indata, inzlp, indone, sendack, sendstall);
type usb_setup_data_type is (invalid, sendzlp, sendzlpaddress, sendstatus, sendconfig, senddescriptor, continuedescriptor, recvvendor, sendvendor, completesetup);
signal usb_state : usb_state_type;
signal usb_setup_data : usb_setup_data_type;
signal usb_recvdata : std_logic;
signal usb_recvdataindex : std_logic;
signal usb_recvdatasetup : std_logic;
signal usb_address : std_logic_vector(6 downto 0);
signal usb_next_address : std_logic_vector(6 downto 0);
signal usb_latch_address : std_logic;
signal usb_byteindex : unsigned(6 downto 0);
signal usb_endp: unsigned(3 downto 0);
signal usb_requesttype : std_logic_vector(7 downto 0);
signal usb_request : std_logic_vector(7 downto 0);
signal usb_wValue : std_logic_vector(15 downto 0);
signal usb_wIndex : std_logic_vector(15 downto 0);
signal usb_wLength : unsigned(15 downto 0);
signal usb_loaddescriptorindex : unsigned(3 downto 0);
signal usb_descriptorlength : unsigned(7 downto 0);
signal usb_descriptorloc : unsigned(10 downto 0);
signal usb_completeonack : std_logic;
signal usb_advanceonack : std_logic;
signal usb_zlp_ack : std_logic;
signal usb_need_addr : unsigned(15 downto 0);
signal internal_addr : unsigned(15 downto 0);
signal usb_configuration : std_logic_vector(7 downto 0);
type internal_state_type is (idle, writedense);
signal internal_state : internal_state_type;
signal ram_doa : std_logic_vector(31 downto 0);
signal ram_dob : std_logic_vector(31 downto 0);
begin
usb_connect <= '1';
usb_hold_reset <= usb_reset or syncreset;
interface_addr <= usb_need_addr when internal_state = idle else internal_addr;
-- USB to the rest of the system interface
process(clk)
begin
if clk'event and clk='1' then
interface_we <= '0';
case internal_state is
when idle =>
when writedense =>
when others => internal_state <= idle;
end case;
if syncreset = '1' then
internal_state <= idle;
end if;
end if;
end process;
ramwriteenable <= '0';
ramwritedata <= (others => '0');
-- USB State machine;
process(clk)
begin
if clk'event and clk='1' then
usbtx_sendbyte <= '0';
usbtx_lastbyte <= '0';
usbtx_byte <= (others => '0');
trace_pulse <= '0';
if usbrx_nextbyte = '1' then
trace_pulse <= '1';
trace_byte <= usbrx_byte;
end if;
if usbtx_sendbyte = '1' then
trace_pulse <= '1';
trace_byte <= usbtx_byte;
end if;
case usb_state is
when idle =>
usb_byteindex <= (others => '0');
if usbrx_nextbyte = '1' then
usb_latch_address <= '0';
usb_advanceonack <= '0';
usb_completeonack <= '0';
case usbrx_byte(3 downto 0) is
when "0001" => -- OUT
usb_recvdata <= '0';
if usbrx_packetend = '0' then
usb_state <= out1;
end if;
when "1001" => -- IN
usb_recvdata <= '0';
if usbrx_packetend = '0' then
usb_state <= in1;
end if;
when "0101" => -- SOF
if usbrx_packetend = '0' then
usb_state <= ignore;
end if;
when "1101" => -- SETUP
usb_recvdata <= '0';
usb_zlp_ack <= '0';
if usbrx_packetend = '0' then
usb_state <= setup1;
end if;
when "0011" => -- DATA0
if usb_recvdata = '1' then
if usb_recvdataindex = '0' then
if usb_recvdatasetup = '1' then
if usbrx_packetend = '0' then
usb_state <= setupdata;
end if;
else
if usbrx_packetend = '1' then
usb_state <= idle;
else
usb_state <= indata;
end if;
end if;
else
-- Wrong data, but we were expecting data. Assume the sender did not get our ACK, and ACK again.
-- Todo: flag to tell when we have previously ACK'd something so we prevent acking blind.
usb_state <= ignoreack;
end if;
end if;
when "1011" => -- DATA1
if usb_setup_data = completesetup then
usb_state <= inzlp;
elsif usb_recvdata = '1' then
if usb_recvdataindex = '1' then
if usb_recvdatasetup = '0' then -- should always be 0
if usbrx_packetend = '1' then
usb_state <= idle;
else
usb_state <= indata;
end if;
end if;
else
-- Wrong data, but we were expecting data. Assume the sender did not get our ACK, and ACK again.
-- Todo: flag to tell when we have previously ACK'd something so we prevent acking blind.
usb_state <= ignoreack;
end if;
end if;
when "0010" => -- ACK
-- If we sent the packet it is ACKing, advance the data bit.
if usb_latch_address = '1' then
usb_address <= usb_next_address;
end if;
if usb_advanceonack = '1' then
usb_descriptorloc <= usb_descriptorloc + 64;
usb_descriptorlength <= usb_descriptorlength - 64;
end if;
if usb_completeonack = '1' then
usb_setup_data <= completesetup;
end if;
when "1010" => -- NAK
when others =>
if usbrx_packetend = '0' then
usb_state <= ignore;
end if;
end case;
end if;
when ignore =>
if usbrx_packetend = '1' then
usb_state <= idle;
end if;
when ignoreack =>
if usbrx_packetend = '1' then
usb_state <= sendack;
usb_recvdataindex <= not usb_recvdataindex; -- Flip this bit once so the ack will flip it back to what it was originally.
end if;
when setup1 =>
if usbrx_nextbyte = '1' then
if usb_address = usbrx_byte(6 downto 0) then
usb_state <= setup2;
else
usb_state <= idle;
end if;
usb_endp(0) <= usbrx_byte(7);
if usbrx_packetend = '1' then
usb_state <= idle;
end if;
end if;
when setup2 =>
if usbrx_nextbyte = '1' then
if usbrx_packetend = '1' then
usb_state <= idle;
else
usb_state <= ignore;
end if;
usb_endp(3 downto 1) <= unsigned(usbrx_byte(2 downto 0));
if usbrx_packetend = '1' and usbrx_error = '0' then
usb_recvdata <= '1';
usb_recvdatasetup <= '1';
usb_recvdataindex <= '0';
end if;
end if;
when in1 => -- Data to host
if usbrx_nextbyte = '1' then
if usb_address = usbrx_byte(6 downto 0) then
usb_state <= in2;
else
usb_state <= idle;
end if;
usb_endp(0) <= usbrx_byte(7);
if usbrx_packetend = '1' then
usb_state <= idle;
end if;
end if;
when in2 =>
if usbrx_nextbyte = '1' then
if usbrx_packetend = '1' then
usb_state <= idle;
else
usb_state <= ignore;
end if;
usb_endp(3 downto 1) <= unsigned(usbrx_byte(2 downto 0));
if usbrx_packetend = '1' and usbrx_error = '0' then
usb_state <= senddelay;
end if;
end if;
when out1 => -- Data from host
if usbrx_nextbyte = '1' then
if usb_address = usbrx_byte(6 downto 0) then
usb_state <= out2;
else
usb_state <= idle;
end if;
usb_endp(0) <= usbrx_byte(7);
if usbrx_packetend = '1' then
usb_state <= idle;
end if;
end if;
when out2 =>
if usbrx_nextbyte = '1' then
if usbrx_packetend = '1' then
usb_state <= idle;
else
usb_state <= ignore;
end if;
usb_endp(3 downto 1) <= unsigned(usbrx_byte(2 downto 0));
if usbrx_packetend = '1' and usbrx_error = '0' then
usb_recvdata <= '1';
usb_recvdatasetup <= '0';
end if;
end if;
when setupdata =>
usb_recvdata <= '0';
if usbrx_nextbyte = '1' then
if usbrx_packetend = '1' then
usb_state <= idle;
end if;
usb_setup_data <= invalid;
usb_byteindex <= usb_byteindex + 1;
case to_integer(usb_byteindex) is
when 0 =>
usb_requesttype <= usbrx_byte;
when 1 =>
usb_request <= usbrx_byte;
when 2 =>
usb_wValue(7 downto 0) <= usbrx_byte;
when 3 =>
usb_wValue(15 downto 8) <= usbrx_byte;
when 4 =>
usb_wIndex(7 downto 0) <= usbrx_byte;
when 5 =>
usb_wIndex(15 downto 8) <= usbrx_byte;
when 6 =>
usb_wLength(7 downto 0) <= unsigned(usbrx_byte);
when 7 =>
usb_wLength(15 downto 8) <= unsigned(usbrx_byte);
when 8 => -- CRC16 is included.
when 9 =>
if usbrx_packetend = '0' then
usb_state <= ignore;
end if;
if usbrx_error = '0' and usbrx_packetend = '1' then
usb_state <= sendack;
if usb_requesttype(6 downto 5) = "00" then -- Standard requests
case usb_request is
when X"00" => -- GET_STATUS
usb_setup_data <= sendstatus;
when X"05" => -- SET_ADDRESS
usb_setup_data <= sendzlpaddress;
usb_next_address <= usb_wValue(6 downto 0);
when X"06" => -- GET_DESCRIPTOR
if usb_requesttype = X"80" then
case usb_wValue(15 downto 8) is
when X"01" => -- Device descriptor
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"0";
when X"02" => -- Configuration descriptor
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"1";
when X"03" => -- String descriptor
case usb_wValue(7 downto 0) is
when X"00" => -- Language ID list
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"5";
when X"01" => -- Device name string
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"6";
when X"EE" => -- OS signature
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"4";
when others =>
end case;
when others =>
end case;
end if;
when X"08" => -- GET_CONFIGURATION
usb_setup_data <= sendconfig;
when X"09" => -- SET_CONFIGURATION
usb_setup_data <= sendzlp; -- don't care too much about configuration yet.
usb_configuration <= usb_wValue(7 downto 0);
when others =>
end case;
elsif usb_requesttype(6 downto 5) = "10" then -- Vendor requests
case usb_request is
when X"01" => -- Read/Write framebuffer data
when X"02" => -- Read/Write flash data
-- Not implemented
when X"03" => -- Reboot FPGA
-- Not implemented
when X"FE" => -- OS descriptor request
if usb_wIndex = X"0004" and usb_wValue(15 downto 8) = X"00" then
-- OS Feature descriptor
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"2";
elsif usb_wIndex = X"0005" and usb_wValue = X"0000" then
-- OS Extended Properties descriptor
usb_setup_data <= senddescriptor;
usb_loaddescriptorindex <= X"3";
end if;
when others =>
end case;
end if;
end if;
when others =>
end case;
end if;
when senddelay =>
usb_byteindex <= usb_byteindex + 1;
if usb_byteindex = 15 then
usb_state <= sendstart;
end if;
when sendstart =>
usb_byteindex <= (others => '0');
-- (invalid, sendzlp, sendzlpaddress, sendconfig, senddescriptor, recvvendor, sendvendor);
if usbtxs_cansend = '1' then
usbtx_sendbyte <= '1';
if usb_setup_data = invalid then
-- Send a STALL
usbtx_byte <= X"1E";
usbtx_lastbyte <= '1';
else
-- Send a DATA0/DATA1
if usb_recvdataindex = '0' then
usbtx_byte <= X"C3"; -- DATA0
else
usbtx_byte <= X"4B"; -- DATA1
end if;
end if;
-- Determine circumstance
case usb_setup_data is
when invalid =>
usb_state <= idle;
when sendzlp =>
usb_state <= idle;
usbtx_lastbyte <= '1';
when sendzlpaddress =>
usb_state <= idle;
usbtx_lastbyte <= '1';
usb_latch_address <= '1';
when continuedescriptor =>
if usb_descriptorlength = 0 then
usb_state <= idle;
usbtx_lastbyte <= '1';
else
usb_state <= preoutdata;
romaddr <= usb_descriptorloc;
end if;
when others =>
usb_state <= preoutdata;
end case;
end if;
when preoutdata =>
-- we have a few cycles before we have to send further data, figure out what we need to send
case usb_setup_data is
when senddescriptor =>
usb_byteindex <= usb_byteindex + 1;
case to_integer(usb_byteindex) is
when 0 =>
romaddr <= "000000" & usb_loaddescriptorindex & "0"; -- Read descriptor location
when 1 =>
romaddr(0) <= '1'; -- Read descriptor length
when 2 =>
usb_descriptorloc <= unsigned("0" & romdata & "00");
romaddr <= unsigned("0" & romdata & "00");
when 3 =>
usb_descriptorlength <= unsigned(romdata);
when 4 =>
usb_setup_data <= continuedescriptor;
usb_state <= outdata;
usb_byteindex <= (others => '0');
if usb_descriptorlength > usb_wLength then
usb_descriptorlength <= usb_wLength(7 downto 0);
end if;
when others =>
end case;
when others =>
usb_state <= outdata; -- No setup necessary.
end case;
if usbtxs_abort = '1' then
usb_state <= idle;
usb_setup_data <= invalid;
end if;
when outdata =>
if usbtxs_cansend = '1' and usbtx_sendbyte = '0' then
usbtx_sendbyte <= '1';
usb_byteindex <= usb_byteindex + 1;
case usb_setup_data is
when sendstatus =>
usbtx_byte <= X"00";
if usb_byteindex(5 downto 0) = 1 then
usbtx_lastbyte <= '1';
usb_zlp_ack <= '1';
usb_state <= idle;
end if;
when sendconfig =>
usbtx_byte <= usb_configuration;
usbtx_lastbyte <= '1';
usb_zlp_ack <= '1';
usb_state <= idle;
when continuedescriptor =>
usbtx_byte <= romdata;
romaddr <= romaddr + 1;
if usb_byteindex(5 downto 0) = 63 then
usbtx_lastbyte <= '1';
usb_completeonack <= '1';
usb_state <= idle;
if (usb_byteindex + 1) = usb_descriptorlength then
usb_setup_data <= sendzlp;
end if;
elsif (usb_byteindex + 1) = usb_descriptorlength then
usbtx_lastbyte <= '1';
usb_zlp_ack <= '1';
usb_advanceonack <= '1';
usb_state <= idle;
end if;
when others =>
-- Don't know how to proceed.
usbtx_byte <= X"EE";
usbtx_lastbyte <= '1';
usb_state <= idle;
end case;
end if;
if usbtxs_abort = '1' then
usb_state <= idle;
usb_setup_data <= invalid;
end if;
when indata =>
if usbrx_nextbyte = '1' then
usb_byteindex <= usb_byteindex + 1;
if usbrx_packetend = '1' then
usb_byteindex <= usb_byteindex - 1; -- Packet includes two trailing bytes for CRC16.
usb_state <= indone;
end if;
end if;
when inzlp =>
usb_setup_data <= invalid;
if usbrx_nextbyte = '1' then
usb_byteindex <= usb_byteindex + 1;
if usbrx_packetend = '1' then
usb_state <= sendstall;
if usb_byteindex = 1 then
usb_state <= sendack;
end if;
if usbrx_error = '1' then
usb_state <= idle;
end if;
end if;
end if;
when indone =>
-- We were sent a packet that we accepted and now we respond with ack/nak/stall
usb_zlp_ack <= '0';
usb_byteindex <= (others => '0');
usb_state <= sendstall;
if usb_byteindex = 0 then
if usb_zlp_ack = '1' then
usb_state <= sendack;
end if;
end if;
when sendack =>
usb_byteindex <= usb_byteindex + 1;
if usb_byteindex = 15 then
usb_byteindex <= usb_byteindex;
if usbtxs_cansend = '1' then
usbtx_sendbyte <= '1';
usbtx_lastbyte <= '1';
usbtx_byte <= X"D2"; -- ACK
usb_state <= idle;
usb_recvdataindex <= not usb_recvdataindex; -- Advance DATA0/DATA1 index on successful receipt.
end if;
end if;
when sendstall =>
usb_byteindex <= usb_byteindex + 1;
if usb_byteindex = 15 then
usb_byteindex <= usb_byteindex;
if usbtxs_cansend = '1' then
usbtx_sendbyte <= '1';
usbtx_lastbyte <= '1';
usbtx_byte <= X"1E"; -- STALL
usb_state <= idle;
end if;
end if;
when others =>
usb_state <= idle;
end case;
if syncreset = '1' or usb_reset = '1' then
usb_state <= idle;
usb_setup_data <= invalid;
usb_recvdata <= '0';
usb_recvdataindex <= '0';
usb_recvdatasetup <= '0';
usb_address <= (others => '0');
usb_next_address <= (others => '0');
usb_latch_address <= '0';
usb_configuration <= (others => '0');
end if;
end if;
end process;
-- Use initial memory contents of this RAM block to store USB descriptor information
-- Starting is an array of pairs of <location/4>, <byte length>
-- Descriptors in the system:
-- 0 Device Descriptor
-- 1 Configuration Descriptor
-- 2 OS Descriptor
-- 3 OS Extended Property Descriptor
-- 4 OS String Descriptor (String 0xEE)
-- 5 Language IDs string (string 0)
-- 6 Product name string (string 1)
RAMB16BWER_inst : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9,
DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0,
DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INITP_00 to INITP_07: Initial memory contents.
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_00 to INIT_3F: Initial memory contents.
INIT_00 => X"010000004c73544c4000000002000112000034420441123c831b281120091204",
INIT_01 => X"01050700004002810507000000ff020000040932800001010020020900000100",
INIT_02 => X"000000004253554e495701000000000000000001000401000000002800004002",
INIT_03 => X"6300690076006500440028000000010000010083000000000000000000000000",
INIT_04 => X"4e000000440049005500470065006300610066007200650074006e0049006500",
INIT_05 => X"34002d0061006500370039002d00630065006100340061003100370036007b00",
INIT_06 => X"62003000650039006500370066002d0039006400330038002d00350034003300",
INIT_07 => X"003000300031005400460053004d0312000000007d0037006300650030003500",
INIT_08 => X"00740061004d0020006e00670069005300640065004c033404090304000000fe",
INIT_09 => X"0000000000720065006c006c006f00720074006e006f00430020007800690072",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- INIT_A/INIT_B: Initial values on output port
INIT_A => X"000000000",
INIT_B => X"000000000",
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
-- Port A Data: 32-bit (each) output: Port A data
DOA => ram_doa, -- 32-bit output: A port data output
-- Port B Data: 32-bit (each) output: Port B data
DOB => ram_dob, -- 32-bit output: B port data output
-- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
ADDRA => std_logic_vector(romaddr) & "000", -- 14-bit input: A port address input
CLKA => clk, -- 1-bit input: A port clock input
ENA => '1', -- 1-bit input: A port enable input
REGCEA => '1', -- 1-bit input: A port register clock enable input
RSTA => syncreset, -- 1-bit input: A port register set/reset input
WEA => "000" & ramwriteenable, -- 4-bit input: Port A byte-wide write enable input
-- Port A Data: 32-bit (each) input: Port A data
DIA => X"000000" & ramwritedata, -- 32-bit input: A port data input
DIPA => X"0", -- 4-bit input: A port parity input
-- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
ADDRB => std_logic_vector(ramreadaddr) & "000", -- 14-bit input: B port address input
CLKB => clk, -- 1-bit input: B port clock input
ENB => '1', -- 1-bit input: B port enable input
REGCEB => '1', -- 1-bit input: B port register clock enable input
RSTB => syncreset, -- 1-bit input: B port register set/reset input
WEB => X"0", -- 4-bit input: Port B byte-wide write enable input
-- Port B Data: 32-bit (each) input: Port B data
DIB => (others => '0'), -- 32-bit input: B port data input
DIPB => (others => '0') -- 4-bit input: B port parity input
);
romdata <= ram_doa(7 downto 0);
ramreaddata <= ram_dob(7 downto 0);
usb_phy_inst : usb_phy
port map (
sysclk => clk,
rst => syncreset,
-- USB Physical interface
usb_dp => usb_dp,
usb_dm => usb_dm,
-- USB Reset
usb_reset => usb_reset,
usb_hold_reset => usb_hold_reset,
-- Transmit interface
usbtx_byte => usbtx_byte,
usbtx_sendbyte => usbtx_sendbyte,
usbtx_lastbyte => usbtx_lastbyte,
usbtxs_cansend => usbtxs_cansend,
usbtxs_abort => usbtxs_abort,
usbtxs_sending => usbtxs_sending,
usbtxs_underrunerror => usbtxs_underrunerror,
-- Receive interface
usbrx_byte => usbrx_byte,
usbrx_nextbyte => usbrx_nextbyte,
usbrx_packetend => usbrx_packetend,
usbrx_crcerror => usbrx_crcerror,
usbrx_bitstufferror => usbrx_bitstufferror,
usbrx_eopmissing => usbrx_eopmissing,
usbrx_piderror => usbrx_piderror,
usbrx_incomplete => usbrx_incomplete,
usbrx_syncerror => usbrx_syncerror,
usbrx_error => usbrx_error
);
end Behavioral;
| mit | 9c67fce8a2504fad76fc9d31cfcbc5ce | 0.530751 | 4.731865 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/Extra/RegHold_Rising.vhd | 1 | 1,617 | ------------------------------------------------------------
-- Notes:
-- HOLD Clocked on RISING EDGE
-- OUTPUT Clocked on FALLING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
-- 0.05 - Forked and added a input hold for the register
--
-- Additional Comments:
-- The register latches it's output data on the FALLING edge
-- Hold latch on the RISING edge
-- The main reason why I included a hold latch was to Prevent
-- Any register transfer faults that could occur.
-- Mostly acts as a safety buffer.
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegF_LATCH IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
--HOLD_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END RegF_LATCH;
ARCHITECTURE Behavior OF RegF_LATCH IS
SIGNAL HOLD : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--HOLD_OUT <= HOLD;
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
HOLD <= (OTHERS => '0');
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '0' THEN
OUTPUT <= HOLD;
END IF;
IF Clock'EVENT AND Clock = '1' THEN
HOLD <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | b6153344640d7dfe1e242d126f3ccd52 | 0.584416 | 3.306748 | false | false | false | false |
NuclearKev/iir-hardware | 2nd-order-iir.vhd | 1 | 4,600 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iir is
port (
i_clk : in std_logic;
i_coeff_clk : in std_logic;
i_rstb : in std_logic;
coeff_ready : in std_logic;
done : out std_logic;
-- coefficient
i_bcoeff : in std_logic_vector(14 downto 0);
i_acoeff : in std_logic_vector(14 downto 0);
-- data input
i_data : in std_logic_vector(11 downto 0);
-- filtered data
o_data : out std_logic_vector(31 downto 0));
end iir;
architecture Behavioral of iir is
type t_data_pipe is array (0 to 3) of signed(11 downto 0);
type t_fdata_pipe is array (0 to 3) of signed(11 downto 0);
type t_bcoeff is array (0 to 2) of signed(14 downto 0);
type t_acoeff is array (0 to 2) of signed(14 downto 0);
type t_mult is array (0 to 2) of signed(26 downto 0);
type t_fmult is array (0 to 2) of signed(26 downto 0);
type t_add_st0 is array (0 to 1) of signed(26+1 downto 0);
type t_fadd_st0 is array (0 to 1) of signed(26+1 downto 0);
signal r_bcoeff : t_bcoeff;
signal r_acoeff : t_acoeff;
signal p_data : t_data_pipe;
signal p_fdata : t_fdata_pipe;
signal r_mult : t_mult;
signal r_fmult : t_fmult;
signal r_add_st0 : t_add_st0;
signal r_fadd_st0 : t_fadd_st0;
signal r_add_st1 : signed(26+2 downto 0);
signal r_fadd_st1 : signed(26+2 downto 0);
signal r_final_sum : signed(26+5 downto 0);
signal out_buf : signed(11 downto 0);
signal coeff_loop : integer range 0 to 16 := 0; --only needs to go from 0 to 15
begin
--- Coefficent input ---
p_coeff_input : process (i_rstb, i_coeff_clk)
begin
if(coeff_ready='1') then
r_bcoeff <= (others=>(others=>'0'));
r_acoeff <= (others=>(others=>'0'));
coeff_loop <= 0;
elsif(rising_edge(i_coeff_clk)) then
if(coeff_loop /= 3) then
r_bcoeff(coeff_loop) <= signed(i_bcoeff);
r_acoeff(coeff_loop) <= signed(i_acoeff);
coeff_loop <= coeff_loop + 1;
elsif(coeff_loop = 3) then
-- do nothing
end if;
end if;
end process p_coeff_input;
--- Data input ---
p_data_input : process (i_rstb,i_clk)
begin
if(i_rstb='1') then
p_data <= (others=>(others=>'0'));
p_fdata <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
p_fdata <= out_buf & p_fdata(0 to p_fdata'length-2);
end if;
end process p_data_input;
--- Feedforward & Feedback ---
p_mult : process (i_rstb,i_clk,p_data,r_bcoeff,p_fdata,r_acoeff)
begin
if(i_rstb='1') then
r_mult <= (others=>(others=>'0'));
r_fmult <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 2 loop
r_mult(k) <= p_data(k) * r_bcoeff(k);
r_fmult(k) <= p_fdata(k) * r_acoeff(k); --k=2, zero
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk,r_mult,r_fmult)
begin
if(i_rstb='1') then
r_add_st0 <= (others=>(others=>'0'));
r_fadd_st0 <= (others=>(others=>'0'));
elsif(i_clk='1') then
r_add_st0(0) <= resize(r_mult(0),28) + resize(r_mult(1),28);
r_fadd_st0(0) <= resize(r_fmult(0),28) + resize(r_fmult(1),28);
r_add_st0(1) <= resize(r_mult(2),28);
r_fadd_st0(1) <= resize(r_fmult(2),28); --zero
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk,r_add_st0,r_fadd_st0)
begin
if(i_rstb='1') then
r_add_st1 <= (others=>'0');
r_fadd_st1 <= (others=>'0');
elsif(i_clk='1') then
r_add_st1 <= resize(r_add_st0(0),29) + resize(r_add_st0(1),29);
r_fadd_st1 <= resize(r_fadd_st0(0),29) + resize(r_fadd_st0(1),29);
end if;
end process p_add_st1;
p_final_sum : process (i_rstb,i_clk,r_add_st1,r_fadd_st1)
begin
if(i_rstb='1') then
r_final_sum <= (others=>'0');
elsif(i_clk='1') then
r_final_sum <= resize(r_add_st1,32) - resize(r_fadd_st1,32);
end if;
end process p_final_sum;
p_output : process (i_rstb,i_clk,r_final_sum,p_fdata,out_buf)
begin
done <= '0';
if(i_rstb='1') then
o_data <= (others=>'0');
done <= '0';
elsif(i_clk='1') then
done <= '1';
out_buf <= r_final_sum(26 downto 15); --this may change
o_data <= std_logic_vector(r_final_sum);
end if;
end process p_output;
end Behavioral;
| lgpl-3.0 | bb5a802ee4c3fa3c8610b516f3c14e0c | 0.550217 | 2.733214 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/Reg_Rising8.vhd | 1 | 1,640 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: RegF
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
--
-- Notes:
-- Clocked on RISING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the rising
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the RISING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegR8 IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(MEM_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(MEM_WIDTH-1 DOWNTO 0)
);
END RegR8;
ARCHITECTURE Behavior OF RegR8 IS
BEGIN
PROCESS(Resetn, Clock,ENABLE)
BEGIN
IF Resetn = '0' THEN
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | bf6372ee330c0ebc637618834d12b0cd | 0.530488 | 3.628319 | false | false | false | false |
sgstair/ledsign | firmware/matrixdriver/framebuffer.vhd | 1 | 5,175 | --
-- This source is released under the MIT License (MIT)
--
-- Copyright (c) 2016 Stephen Stair ([email protected])
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity framebuffer is
Generic ( RamSizeBits : integer := 14 );
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
frame_addr : in unsigned( (RamSizeBits-1) downto 0);
frame_readdata : out std_logic_vector(31 downto 0);
access_addr : in unsigned ( (RamSizeBits-1) downto 0);
access_readdata : out std_logic_vector(31 downto 0);
access_writedata : in std_logic_vector(31 downto 0);
access_writeenable : in std_logic );
end framebuffer;
architecture Behavioral of framebuffer is
constant BankBits : integer := RamSizeBits - 9;
constant RamBanks : integer := 2**BankBits;
constant RamBankMax : integer := (RamBanks-1);
type RamReadArray is array(0 to RamBankMax) of std_logic_vector(31 downto 0);
signal frameread_ram : RamReadArray;
signal accessread_ram : RamReadArray;
signal accesswriteenable : std_logic_vector(RamBankMax downto 0);
begin
frame_readdata <= frameread_ram(to_integer(frame_addr(frame_addr'left downto 9)));
access_readdata <= accessread_ram(to_integer(access_addr(access_addr'left downto 9)));
ram_generate:
for i in 0 to RamBankMax generate
accesswriteenable(i) <= access_writeenable when i = access_addr(access_addr'left downto 9) else '0';
ram : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 36, DATA_WIDTH_B => 36,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0, DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
DOA => frameread_ram(i), -- 32-bit output: A port data output
ADDRA => std_logic_vector(frame_addr(8 downto 0)) & "00000", -- 14-bit input: A port address input
CLKA => clk, -- 1-bit input: A port clock input
ENA => '1', -- 1-bit input: A port enable input
REGCEA => '1', -- 1-bit input: A port register clock enable input
RSTA => reset, -- 1-bit input: A port register set/reset input
WEA => "0000", -- 4-bit input: Port A byte-wide write enable input
DIA => (others => '0'), -- 32-bit input: A port data input
DIPA => (others => '0'),-- 4-bit input: A port parity input
DOB => accessread_ram(i), -- 32-bit output: A port data output
ADDRB => std_logic_vector(access_addr(8 downto 0)) & "00000", -- 14-bit input: B port address input
CLKB => clk, -- 1-bit input: B port clock input
ENB => '1', -- 1-bit input: B port enable input
REGCEB => '1', -- 1-bit input: B port register clock enable input
RSTB => reset, -- 1-bit input: B port register set/reset input
WEB => (others => accesswriteenable(i)), -- 4-bit input: Port B byte-wide write enable input
DIB => access_writedata, -- 32-bit input: B port data input
DIPB => (others => '0') -- 4-bit input: B port parity input
);
end generate;
end Behavioral;
| mit | f30a337c17c4aff5382d82e9c7750932 | 0.679807 | 3.427152 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_CPU_top_level.vhd | 1 | 4,890 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:17:07 10/23/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Nibble_Knowledge_CPU/tb_CPU_top_level.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CPU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_CPU_top_level IS
END tb_CPU_top_level;
ARCHITECTURE behavior OF tb_CPU_top_level IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU
PORT(
clk : IN std_logic;
reset : IN std_logic;
clk_out : out std_logic;
a_data : OUT std_logic_vector(3 downto 0);
ram_data : INOUT std_logic_vector(3 downto 0);
ram_address : OUT std_logic_vector(15 downto 0);
ram_write_enable : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--BiDirs
signal ram_data : std_logic_vector(3 downto 0);
--Outputs
signal ram_address : std_logic_vector(15 downto 0);
signal ram_write_enable : std_logic;
signal clk_out : std_logic;
signal a_data :std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU PORT MAP (
clk => clk,
reset => reset,
clk_out => clk_out,
ram_data => ram_data,
ram_address => ram_address,
ram_write_enable => ram_write_enable
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 1 ms;
reset <= '0';
ram_data <= "0001";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0011";
wait until rising_edge(clk_out);
ram_data <= "0110";
wait until rising_edge(clk_out);
L1 : loop
-- ADD 2 instruction
-- ADD 0x9
-- 0011 0000 0000 0000 1001
--OP cycle
ram_data <= "0001";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "1001";
wait until rising_edge(clk_out);
-- exe cycle
-- "0001" should be at mem location 0x0009
ram_data <= "0101";
wait until rising_edge(clk_out);
--OP Cycle
--STR 12
ram_data <= "0010";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "1100";
wait until rising_edge(clk_out);
-- exe cycle
ram_data <= "ZZZZ";
wait until rising_edge(clk_out);
--OP CYCLE
--JMP 1111
ram_data <= "0110";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "1111";
wait until rising_edge(clk_out);
--should store
wait until rising_edge(clk_out);
end loop;
-- L1 : loop
-- -- ADD 2 instruction
-- -- ADD 0x9
-- -- 0011 0000 0000 0000 1001
--
-- --OP cycle
--
-- ram_data <= "0011";
--
-- -- address cycles
-- wait for clk_period;
-- ram_data <= "0000";
-- wait for clk_period;
-- ram_data <= "0000";
-- wait for clk_period;
-- ram_data <= "0000";
-- wait for clk_period;
-- ram_data <= "1001";
-- wait for clk_period;
--
-- -- exe cycle
-- -- "0001" should be at mem location 0x0009
-- ram_data <= "0010";
-- wait for clk_period;
--
-- end loop;
wait;
end process;
END;
| unlicense | 71572e48b95c7bdc76e073884eb31e8c | 0.591616 | 3.191906 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/bitadder_16.vhd | 1 | 2,176 | -- 16 Bit Adder --
--
-- A Full 16 bit adder
-- Requires: bitadder_1.VHDL
--
-- Author: Colton Schmidt
-- Last Edited: 18/10/2015
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity bitadder_16 is
Port ( x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
s0 : out std_logic_vector(15 downto 0));
end bitadder_16;
architecture Behavioral of bitadder_16 is
-- Internal Signals --
signal c : std_logic_vector (15 downto 0):= "0000000000000000";
component bitadder_1
port( a,b,cin:in std_logic;
s,cout:out std_logic);
end component;
begin
bit1: bitadder_1 port map (a=>x(0), b=>y(0), s=>s0(0), cin=>c(0), cout=>c(1));
bit2: bitadder_1 port map (a=>x(1), b=>y(1), s=>s0(1), cin=>c(1), cout=>c(2));
bit3: bitadder_1 port map (a=>x(2), b=>y(2), s=>s0(2), cin=>c(2), cout=>c(3));
bit4: bitadder_1 port map (a=>x(3), b=>y(3), s=>s0(3), cin=>c(3), cout=>c(4));
bit5: bitadder_1 port map (a=>x(4), b=>y(4), s=>s0(4), cin=>c(4), cout=>c(5));
bit6: bitadder_1 port map (a=>x(5), b=>y(5), s=>s0(5), cin=>c(5), cout=>c(6));
bit7: bitadder_1 port map (a=>x(6), b=>y(6), s=>s0(6), cin=>c(6), cout=>c(7));
bit8: bitadder_1 port map (a=>x(7), b=>y(7), s=>s0(7), cin=>c(7), cout=>c(8));
bit9: bitadder_1 port map (a=>x(8), b=>y(8), s=>s0(8), cin=>c(8), cout=>c(9));
bit10: bitadder_1 port map (a=>x(9), b=>y(9), s=>s0(9), cin=>c(9), cout=>c(10));
bit11: bitadder_1 port map (a=>x(10), b=>y(10), s=>s0(10), cin=>c(10), cout=>c(11));
bit12: bitadder_1 port map (a=>x(11), b=>y(11), s=>s0(11), cin=>c(11), cout=>c(12));
bit13: bitadder_1 port map (a=>x(12), b=>y(12), s=>s0(12), cin=>c(12), cout=>c(13));
bit14: bitadder_1 port map (a=>x(13), b=>y(13), s=>s0(13), cin=>c(13), cout=>c(14));
bit15: bitadder_1 port map (a=>x(14), b=>y(14), s=>s0(14), cin=>c(14), cout=>c(15));
bit16: bitadder_1 port map (a=>x(15), b=>y(15), s=>s0(15), cin=>c(15), cout=>c(0));
end Behavioral; | unlicense | 49c18800a5b51e5436e65126026ce161 | 0.59329 | 2.290526 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/ipcore_dir/clk_dcm_pll.vhd | 1 | 6,457 | -- file: clk_dcm_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 40.960 0.000 50.0 596.692 50.000
-- CLK_OUT2 8.192 0.000 50.0 200.000 50.000
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 8.192 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_dcm_pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic;
CLK_OUT2 : out std_logic
);
end clk_dcm_pll;
architecture xilinx of clk_dcm_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_dcm_pll,clk_wiz_v3_1,{component_name=clk_dcm_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=122.0703125,clkin2_period=122.0703125,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out2_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 122.0703125,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out2_internal;
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkfx);
clkout2_buf : BUFG
port map
(O => clk_out2_internal,
I => clk0);
CLK_OUT2 <= clk_out2_internal;
end xilinx;
| mit | b8d795f31482cff79f0a7310db02e7f2 | 0.574415 | 4.220261 | false | false | false | false |
MattProtas/FPGA | Projects/DE0_Nano_Examples/SoC_FPGA/DE0_NANO_SOC_GHRD/soc_system/soc_system_inst.vhd | 1 | 19,821 | component soc_system is
port (
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
clk_clk : in std_logic := 'X'; -- clk
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
led_pio_external_connection_export : out std_logic_vector(7 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_system;
u0 : component soc_system
port map (
button_pio_external_connection_export => CONNECTED_TO_button_pio_external_connection_export, -- button_pio_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
dipsw_pio_external_connection_export => CONNECTED_TO_dipsw_pio_external_connection_export, -- dipsw_pio_external_connection.export
hps_0_f2h_cold_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_cold_reset_req_reset_n, -- hps_0_f2h_cold_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_debug_reset_req_reset_n, -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_stm_hw_events_stm_hwevents => CONNECTED_TO_hps_0_f2h_stm_hw_events_stm_hwevents, -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_f2h_warm_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_warm_reset_req_reset_n, -- hps_0_f2h_warm_reset_req.reset_n
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
led_pio_external_connection_export => CONNECTED_TO_led_pio_external_connection_export, -- led_pio_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| mit | bfbda48c16a08a5268bf8f4bd951f89f | 0.459412 | 2.955271 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/top.vhd | 1 | 24,037 | -------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
-- Copyright 2011 - 2012
--
-- Email: [email protected]
--
-- License: LGPL
--
-- If you would like a version with a different license for use
-- in commercial projects please contact the above email address
-- for more details.
-------------------------------------------------------------------
--
-- Copyright (C) 2011 - 2012 Ultra-Embedded.com
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.peripherals.all;
entity fpga_top is
generic
(
OSC_KHZ : integer := 8192;
CLK_KHZ : integer := (8192 * 7);
SD_CLK_KHZ : integer := 12288
);
Port
(
clk : in std_logic;
-- SRAM 1 (Left)
sram1_io : inout std_logic_vector(15 downto 0);
sram1_addr : out std_logic_vector(17 downto 0);
sram1_ub : out std_logic;
sram1_lb : out std_logic;
sram1_oe : out std_logic;
sram1_ce : out std_logic;
sram1_we : out std_logic;
-- UART
tx : in std_logic;
rx : out std_logic;
-- UEXT
uext : inout std_logic_vector(10 downto 3);
-- SD
sd_cs : out std_logic;
sd_do : in std_logic;
sd_di : out std_logic;
sd_clk : out std_logic;
-- DAC
dac_din : out std_logic;
dac_bck : out std_logic;
dac_lrc : out std_logic;
dac_mclk : out std_logic;
-- SPI Flash
flash_cs : inout std_logic;
flash_si : inout std_logic;
flash_so : in std_logic;
flash_sck : inout std_logic
);
end fpga_top;
architecture Behavioral of fpga_top is
-----------------------------------------------
-- Component Definitions
-----------------------------------------------
component ram
generic
(
-- Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1
);
port
(
-- Port A
clka_i : in std_logic;
ena_i : in std_logic;
wea_i : in std_logic_vector(3 downto 0);
addra_i : in std_logic_vector(31 downto 2);
dataa_i : in std_logic_vector(31 downto 0);
dataa_o : out std_logic_vector(31 downto 0);
-- Port B
clkb_i : in std_logic;
enb_i : in std_logic;
web_i : in std_logic_vector(3 downto 0);
addrb_i : in std_logic_vector(31 downto 2);
datab_i : in std_logic_vector(31 downto 0);
datab_o : out std_logic_vector(31 downto 0)
);
end component;
component fifo32
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
wr_data_count : out std_logic_vector(9 downto 0)
);
end component;
component dpram_4_1_xc6
port (
clka : in std_logic;
wea : in std_logic_vector(3 downto 0);
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(31 downto 0);
douta : out std_logic_vector(31 downto 0);
clkb : in std_logic;
web : in std_logic_vector(0 downto 0);
addrb : in std_logic_vector(9 downto 0);
dinb : in std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0)
);
end component;
component clk_dcm_pll
generic
(
CLK_MULTIPLY : integer := 5
);
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
component hw_multiplier
port
(
clk : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
p : out std_logic_vector(63 downto 0)
);
end component;
-----------------------------------------------
-- Signals
-----------------------------------------------
-- Clocks
signal clk57_34 : std_logic;
signal clk8_192 : std_logic;
-- Reset
signal reset : std_logic:= '1';
signal rst_next : std_logic:= '1';
-- External memory
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address : std_logic_vector(31 downto 0);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r : std_logic_vector(31 downto 0);
signal ram_read : std_logic;
signal ram_done : std_logic;
signal ram_busy : std_logic;
-- SRAM Data bus
signal sram_data_i : std_logic_vector(16-1 downto 0);
signal sram_data_o : std_logic_vector(16-1 downto 0);
signal sram_data_out_en : std_logic;
-- I/O peripheral bus
signal io_address : std_logic_vector(31 downto 0);
signal io_data_w : std_logic_vector(31 downto 0);
signal io_data_r : std_logic_vector(31 downto 0);
signal io_wr : std_logic_vector(3 downto 0);
signal io_rd : std_logic;
-- BootRAM interface
signal bram_mem_address : std_logic_vector(31 downto 0);
signal bram_mem_data_w : std_logic_vector(31 downto 0);
signal bram_mem_data_r : std_logic_vector(31 downto 0);
signal bram_mem_wr : std_logic_vector(3 downto 0);
-- Dual port RAM (cpu-side) interface (SD-DMA)
signal dpram_address1 : std_logic_vector(31 downto 0);
signal dpram_data_w1 : std_logic_vector(31 downto 0);
signal int_dpram_data_w1: std_logic_vector(31 downto 0);
signal dpram_data_r1 : std_logic_vector(31 downto 0);
signal int_dpram_data_r1: std_logic_vector(31 downto 0);
signal dpram_wr1 : std_logic_vector(3 downto 0);
signal int_dpram_wr1 : std_logic_vector(3 downto 0);
-- IRQ Status
signal intr_in : std_logic_vector(4-1 downto 0);
-- SD (DMA side) Memory
signal sd_mem_wr : std_logic;
signal sd_mem_addr : std_logic_vector(10-1 downto 0);
signal sd_mem_data_o : std_logic_vector(7 downto 0);
signal sd_mem_data_i : std_logic_vector(7 downto 0);
-- SD DMA Control
signal sd_dma_start : std_logic;
signal sd_dma_rx_only : std_logic;
signal sd_dma_busy : std_logic;
signal sd_dma_done : std_logic;
signal sd_dma_count : std_logic_vector(31 downto 0);
signal sd_dma_addr : std_logic_vector(31 downto 0);
-- Audio FIFO
signal fifo_wr : std_logic;
signal fifo_wr_data : std_logic_vector(31 downto 0);
signal fifo_rd : std_logic;
signal fifo_rd_data : std_logic_vector(31 downto 0);
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_count : std_logic_vector(9 downto 0);
signal fifo_underun : std_logic_vector(15 downto 0);
signal fifo_i2s_ur : std_logic;
signal fifo_low_thresh : std_logic_vector(9 downto 0);
signal fifo_low_intr : std_logic;
-- Multiplier
signal mult_in_a : std_logic_vector(31 downto 0);
signal mult_in_b : std_logic_vector(31 downto 0);
signal mult_p : std_logic_vector(63 downto 0);
-- RAM timing control
signal ram_timing : std_logic_vector(31 downto 0);
-----------------------------------------------
-- I/O Register Map
-----------------------------------------------
constant GPIO_OUT : std_logic_vector(7 downto 0) := X"30";
constant SPI_DMA_CTRL : std_logic_vector(7 downto 0) := X"40";
constant SPI_DMA_STAT : std_logic_vector(7 downto 0) := X"40";
constant SPI_DMA_ADDR : std_logic_vector(7 downto 0) := X"44";
constant MULT_A : std_logic_vector(7 downto 0) := X"60";
constant MULT_HI : std_logic_vector(7 downto 0) := X"60";
constant MULT_B : std_logic_vector(7 downto 0) := X"64";
constant MULT_LO : std_logic_vector(7 downto 0) := X"64";
constant AUDIO_FIFO_WRITE : std_logic_vector(7 downto 0) := X"70";
constant AUDIO_FIFO_UNDERUN : std_logic_vector(7 downto 0) := X"70";
constant AUDIO_FIFO_THRESH : std_logic_vector(7 downto 0) := X"74";
constant AUDIO_FIFO_STATUS : std_logic_vector(7 downto 0) := X"74";
constant SRAM_TIMING : std_logic_vector(7 downto 0) := X"E0";
begin
-----------------------------------------------
-- Instantiation
-----------------------------------------------
U0_DCM: clk_dcm_pll
generic map
(
CLK_MULTIPLY => (CLK_KHZ / OSC_KHZ)
)
port map
(
CLK_IN => clk,
CLK_OUT => clk57_34,
CLK_OUT2 => clk8_192
);
U1_RAM: ram
generic map ( block_count => 7 ) -- 56KB block RAM
port map
(
clka_i => clk57_34,
ena_i => '1',
wea_i => bram_mem_wr,
addra_i => bram_mem_address(31 downto 2),
dataa_i => bram_mem_data_w,
dataa_o => bram_mem_data_r,
clkb_i => clk57_34,
enb_i => '1',
web_i => "0000",
addrb_i => (others=>'0'),
datab_i => (others=>'0'),
datab_o => open
);
-- CPU SOC
U1_CPU: mpx_soc
generic map
(
CLK_KHZ => CLK_KHZ,
UART_BAUD => 115200,
EXTERNAL_INTERRUPTS => 4
)
port map
(
-- General - clocking & reset
clk_i => clk57_34,
rst_i => reset,
en_i => '1',
ext_intr_i => intr_in,
fault_o => open,
-- UART
uart_tx_o => rx,
uart_rx_i => tx,
-- BootRAM
int_mem_addr_o => bram_mem_address,
int_mem_data_o => bram_mem_data_w,
int_mem_data_i => bram_mem_data_r,
int_mem_wr_o => bram_mem_wr,
int_mem_rd_o => open,
-- External Memory
ext_mem_addr_o => ram_address,
ext_mem_data_o => ram_data_w,
ext_mem_data_i => ram_data_r,
ext_mem_wr_o => ram_byte_we,
ext_mem_rd_o => ram_read,
ext_mem_pause_i => ram_busy,
-- External IO
ext_io_addr_o => io_address,
ext_io_data_o => io_data_w,
ext_io_data_i => io_data_r,
ext_io_wr_o => io_wr,
ext_io_rd_o => io_rd,
ext_io_pause_i => io_rd,
-- External Shared / DP-RAM
ext_dpram_addr_o => dpram_address1,
ext_dpram_data_o => dpram_data_w1,
ext_dpram_data_i => dpram_data_r1,
ext_dpram_wr_o => dpram_wr1,
ext_dpram_rd_o => open,
ext_dpram_pause_i => '0',
-- SPI Flash
flash_cs_o => flash_cs,
flash_si_o => flash_si,
flash_so_i => flash_so,
flash_sck_o => flash_sck,
-- Debug Register Access
dbg_reg_addr_i => "000000000",
dbg_reg_out_o => open,
dbg_pc_o => open,
-- Debug UART Output
dbg_uart_data_o => open,
dbg_uart_wr_o => open
);
-- External SRAM (256x16) interface
U2_EXTMEM: asram16_if
generic map
(
EXT_ADDR_WIDTH => 18
)
port map
(
-- Clocking / Reset
clk_i => clk57_34,
rst_i => reset,
-- Timing control register
timing_ctrl_i => ram_timing,
-- Asynchronous SRAM interface
sram_address_o => sram1_addr,
sram_data_o => sram_data_o,
sram_data_i => sram_data_i,
sram_oe_o => sram1_oe,
sram_cs_o => sram1_ce,
sram_we_o => sram1_we,
sram_be_o(0) => sram1_lb,
sram_be_o(1) => sram1_ub,
sram_dir_out_o => sram_data_out_en,
-- Internal access
address_i => ram_address,
data_i => ram_data_w,
data_o => ram_data_r,
rd_i => ram_read,
wr_i => ram_byte_we,
busy_o => ram_busy
);
-- SD DMA memory (port A = 32-bit, port B = 8-bit)
U4_DPRAM: dpram_4_1_xc6
port map
(
-- Port A
clka => clk57_34,
wea => int_dpram_wr1,
addra => dpram_address1(10-1 downto 2),
dina => int_dpram_data_w1,
douta => int_dpram_data_r1,
-- Port B
clkb => clk57_34,
web(0) => sd_mem_wr,
addrb => sd_mem_addr(10-1 downto 0),
dinb => sd_mem_data_i,
doutb => sd_mem_data_o
);
-- Endian swap
int_dpram_data_w1 <= dpram_data_w1(7 downto 0) & dpram_data_w1(15 downto 8) & dpram_data_w1(23 downto 16) & dpram_data_w1(31 downto 24);
dpram_data_r1 <= int_dpram_data_r1(7 downto 0) & int_dpram_data_r1(15 downto 8) & int_dpram_data_r1(23 downto 16) & int_dpram_data_r1(31 downto 24);
int_dpram_wr1(3 downto 0) <= dpram_wr1(0) & dpram_wr1(1) & dpram_wr1(2) & dpram_wr1(3);
-- SD Card SPI Master DMA Interface
U3_SPI_DMA: spi_dma_ext
generic map ( MEM_ADDR_WIDTH => 10, XFER_COUNT_WIDTH => 32, TRANSFER_WIDTH => 8, SPI_CLK_DIV => (CLK_KHZ / SD_CLK_KHZ) )
port map
(
-- General
clk_i => clk57_34,
rst_i => reset,
-- Memory interface
mem_address_o => sd_mem_addr,
mem_data_o => sd_mem_data_i,
mem_data_i => sd_mem_data_o,
mem_rd_o => open,
mem_wr_o => sd_mem_wr,
-- SPI
spi_clk_o => sd_clk,
spi_ss_o => open,
spi_mosi_o => sd_di,
spi_miso_i => sd_do,
-- Control
xfer_count_i => sd_dma_count,
xfer_address_i => sd_dma_addr(10-1 downto 0),
xfer_start_i => sd_dma_start,
xfer_rx_only_i => sd_dma_rx_only,
xfer_done_o => sd_dma_done,
xfer_busy_o => sd_dma_busy
);
-- 8.192MHz clock / 6 -> 42666Hz
U5_I2S: i2s
generic map ( CLK_DIVISOR => 6 )
port map
(
-- General
clk_i => clk8_192,
rst_i => reset,
-- Audio PCM input (2x16-bit BE signed data)
pcm_data_i => fifo_rd_data,
pcm_fifo_empty_i => fifo_empty,
pcm_fifo_rd_o => fifo_rd,
pcm_fifo_ur_o => fifo_i2s_ur,
-- I2S output
ws_o => dac_lrc,
bclk_o => dac_bck,
data_o => dac_din
);
-- Audio FIFO (input side clk 57MHz, output side 8.192MHz)
U7_FIFO: fifo32
port map
(
-- Clock & Reset (system clock)
wr_clk => clk57_34,
rst => reset,
-- In
wr_en => fifo_wr,
din => fifo_wr_data,
-- Out
rd_clk => clk8_192,
rd_en => fifo_rd,
dout => fifo_rd_data,
-- Status
empty => fifo_empty,
full => fifo_full,
wr_data_count => fifo_count
);
-- Xilinx 32x32 multiplier (64-bit result)
U8_MULT: hw_multiplier
port map
(
clk => clk57_34,
a => mult_in_a,
b => mult_in_b,
p => mult_p
);
-----------------------------------------------
-- Implementation
-----------------------------------------------
-- Reset Generator
process (clk57_34)
begin
if (rising_edge(clk57_34)) then
if (rst_next = '0') then
reset <= '0';
else
rst_next <= '0';
end if;
end if;
end process;
-----------------------------------------------
-- IO memory space WRITE handler
-----------------------------------------------
process (reset,clk57_34)
begin
if (reset = '1') then
sd_cs <= '0';
-- SD
sd_dma_start <= '0';
sd_dma_rx_only <= '0';
sd_dma_count <= (others=>'0');
sd_dma_addr <= (others=>'0');
-- Audio FIFO
fifo_wr <= '0';
fifo_wr_data <= (others=>'0');
fifo_low_thresh <= (others=>'0');
fifo_low_intr <= '0';
-- Multiplier
mult_in_a <= (others=>'0');
mult_in_b <= (others=>'0');
-- Default (slow) SRAM timing
ram_timing <= X"00000777";
elsif (rising_edge(clk57_34)) then
-- SD
sd_dma_start <= '0';
-- Audio FIFO
fifo_wr <= '0';
-- FIFO below threshold?
if (fifo_count < fifo_low_thresh) then
fifo_low_intr <= '1';
else
fifo_low_intr <= '0';
end if;
-- IO Write Cycle
if (io_wr /= "0000") then
case io_address(7 downto 0) is
when GPIO_OUT =>
sd_cs <= io_data_w(8);
when SPI_DMA_CTRL =>
sd_dma_count <= io_data_w;
sd_dma_start <= '1';
when SPI_DMA_ADDR =>
sd_dma_addr <= "0" & io_data_w(30 downto 0);
sd_dma_rx_only <= io_data_w(31);
when MULT_A =>
mult_in_a <= io_data_w;
when MULT_B =>
mult_in_b <= io_data_w;
when AUDIO_FIFO_WRITE =>
fifo_wr_data <= io_data_w;
fifo_wr <= '1';
when AUDIO_FIFO_THRESH =>
fifo_low_thresh <= io_data_w(9 downto 0);
when SRAM_TIMING =>
ram_timing <= io_data_w;
when others =>
end case;
end if;
end if;
end process;
-----------------------------------------------
-- IO memory space READ handler
-----------------------------------------------
process (reset,clk57_34)
begin
if (reset = '1') then
io_data_r <= X"00000000";
fifo_underun <= (others=>'0');
elsif (rising_edge(clk57_34)) then
-- Audio buffer under-run detected?
if (fifo_i2s_ur = '1' and fifo_underun /= X"1111") then
fifo_underun <= fifo_underun + "1";
end if;
-- Read cycle?
if (io_rd = '1') then
case io_address(7 downto 0) is
when SPI_DMA_STAT =>
io_data_r <= X"000000" & "0000000" & sd_dma_busy;
when MULT_HI =>
io_data_r <= mult_p(63 downto 32);
when MULT_LO =>
io_data_r <= mult_p(31 downto 0);
when AUDIO_FIFO_UNDERUN =>
io_data_r <= X"0000" & fifo_underun;
fifo_underun <= (others=>'0');
when AUDIO_FIFO_STATUS =>
io_data_r <= X"000" & "00" & fifo_count & "00000" & fifo_low_intr & fifo_full & fifo_empty;
when others =>
io_data_r <= X"00000000";
end case;
end if;
end if;
end process;
-----------------------------------------------
-- Combinatorial
-----------------------------------------------
intr_in <= '0' & fifo_low_intr & '0' & sd_dma_done;
-----------------------------------------------
-- External Interface
-----------------------------------------------
-- SRAM Bi-direction data bus
sram1_io(0) <= sram_data_o(0) when sram_data_out_en = '1' else 'Z';
sram1_io(1) <= sram_data_o(1) when sram_data_out_en = '1' else 'Z';
sram1_io(2) <= sram_data_o(2) when sram_data_out_en = '1' else 'Z';
sram1_io(3) <= sram_data_o(3) when sram_data_out_en = '1' else 'Z';
sram1_io(4) <= sram_data_o(4) when sram_data_out_en = '1' else 'Z';
sram1_io(5) <= sram_data_o(5) when sram_data_out_en = '1' else 'Z';
sram1_io(6) <= sram_data_o(6) when sram_data_out_en = '1' else 'Z';
sram1_io(7) <= sram_data_o(7) when sram_data_out_en = '1' else 'Z';
sram1_io(8) <= sram_data_o(8) when sram_data_out_en = '1' else 'Z';
sram1_io(9) <= sram_data_o(9) when sram_data_out_en = '1' else 'Z';
sram1_io(10) <= sram_data_o(10) when sram_data_out_en = '1' else 'Z';
sram1_io(11) <= sram_data_o(11) when sram_data_out_en = '1' else 'Z';
sram1_io(12) <= sram_data_o(12) when sram_data_out_en = '1' else 'Z';
sram1_io(13) <= sram_data_o(13) when sram_data_out_en = '1' else 'Z';
sram1_io(14) <= sram_data_o(14) when sram_data_out_en = '1' else 'Z';
sram1_io(15) <= sram_data_o(15) when sram_data_out_en = '1' else 'Z';
sram_data_i(0) <= sram1_io(0);
sram_data_i(1) <= sram1_io(1);
sram_data_i(2) <= sram1_io(2);
sram_data_i(3) <= sram1_io(3);
sram_data_i(4) <= sram1_io(4);
sram_data_i(5) <= sram1_io(5);
sram_data_i(6) <= sram1_io(6);
sram_data_i(7) <= sram1_io(7);
sram_data_i(8) <= sram1_io(8);
sram_data_i(9) <= sram1_io(9);
sram_data_i(10) <= sram1_io(10);
sram_data_i(11) <= sram1_io(11);
sram_data_i(12) <= sram1_io(12);
sram_data_i(13) <= sram1_io(13);
sram_data_i(14) <= sram1_io(14);
sram_data_i(15) <= sram1_io(15);
-- UEXT connector
uext(3) <= '0';
uext(4) <= '0';
uext(5) <= '0';
uext(6) <= '0';
uext(7) <= '0';
uext(8) <= '0';
uext(9) <= '0';
uext(10) <= '0';
-- DAC MCLK (8.192MHz)
dac_mclk <= clk8_192;
end Behavioral;
| mit | ee80cfd4c389648ecffd818300fff048 | 0.461455 | 3.40902 | false | false | false | false |
alexandruioanp/Open-Logic-Analyzer | src/examples/uart.vhd | 1 | 7,098 | ----------------------------------------------------------------------------------
-- Creation Date: 21:12:48 05/06/2010
-- Module Name: RS232/UART Interface - Behavioral
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart is
generic (
CLK_FREQ : integer := 100; -- Main frequency (MHz)
SER_FREQ : integer := 115200 -- Baud rate (bps)
);
port (
-- Control
clk : in std_logic; -- Main clock
rst : in std_logic; -- Main reset
-- External Interface
rx : in std_logic; -- RS232 received serial data
tx : out std_logic; -- RS232 transmitted serial data
-- RS232/UART Configuration
par_en : in std_logic; -- Parity bit enable
-- uPC Interface
tx_req : in std_logic; -- Request SEND of data
tx_end : out std_logic; -- Data SENDED
tx_data : in std_logic_vector(7 downto 0); -- Data to transmit
rx_ready : out std_logic; -- Received data ready to uPC read
rx_data : out std_logic_vector(7 downto 0) -- Received data
);
end uart;
architecture Behavioral of uart is
-- Constants
constant UART_IDLE : std_logic := '1';
constant UART_START : std_logic := '0';
constant PARITY_EN : std_logic := '1';
constant RST_LVL : std_logic := '1';
-- Types
type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals
-- RX Signals
signal rx_fsm : state; -- Control of reception
signal rx_clk_en : std_logic; -- Received clock enable
signal rx_rcv_init : std_logic; -- Start of reception
signal rx_par_bit : std_logic; -- Calculated Parity bit
signal rx_data_deb : std_logic; -- Debounce RX data
signal rx_data_tmp : std_logic_vector(7 downto 0); -- Serial to parallel converter
signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits
-- TX Signals
signal tx_fsm : state; -- Control of transmission
signal tx_clk_en : std_logic; -- Transmited clock enable
signal tx_par_bit : std_logic; -- Calculated Parity bit
signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter
signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits
begin
tx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
tx_clk_en <= '1';
counter := 0;
else
tx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
tx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
tx_proc:process(clk)
variable data_cnt : std_logic_vector(2 downto 0);
begin
if clk'event and clk = '1' then
if tx_clk_en = '1' then
-- Default values
tx_end <= '0';
tx <= UART_IDLE;
-- FSM description
case tx_fsm is
-- Wait to transfer data
when idle =>
-- Send Init Bit
if tx_req = '1' then
tx <= UART_START;
tx_data_tmp <= tx_data;
tx_fsm <= data;
tx_data_cnt <= (others=>'1');
tx_par_bit <= '0';
end if;
-- Data receive
when data =>
tx <= tx_data_tmp(0);
tx_par_bit <= tx_par_bit xor tx_data_tmp(0);
if tx_data_cnt = 0 then
if par_en = PARITY_EN then
tx_fsm <= parity;
else
tx_fsm <= stop1;
end if;
tx_data_cnt <= (others=>'1');
else
tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
tx_data_cnt <= tx_data_cnt - 1;
end if;
when parity =>
tx <= tx_par_bit;
tx_fsm <= stop1;
-- End of communication
when stop1 =>
-- Send Stop Bit
tx <= UART_IDLE;
tx_fsm <= stop2;
when stop2 =>
-- Send Stop Bit
tx_end <= '1';
tx <= UART_IDLE;
tx_fsm <= idle;
-- Invalid States
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
tx_fsm <= idle;
tx_par_bit <= '0';
tx_data_tmp <= (others=>'0');
tx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
rx_debounceer:process(clk)
variable deb_buf : std_logic_vector(3 downto 0);
begin
if clk'event and clk = '1' then
-- Debounce logic
if deb_buf = "0000" then
rx_data_deb <= '0';
elsif deb_buf = "1111" then
rx_data_deb <= '1';
end if;
-- Data storage to debounce
deb_buf := deb_buf(2 downto 0) & rx;
end if;
end process;
rx_start_detect:process(clk)
variable rx_data_old : std_logic;
begin
if clk'event and clk = '1' then
-- Falling edge detection
if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then
rx_rcv_init <= '1';
else
rx_rcv_init <= '0';
end if;
-- Default assignments
rx_data_old := rx_data_deb;
-- Reset condition
if rst = RST_LVL then
rx_data_old := '0';
rx_rcv_init <= '0';
end if;
end if;
end process;
rx_clk_gen:process(clk)
variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
begin
if clk'event and clk = '1' then
-- Normal Operation
if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 or rx_rcv_init = '1' then
rx_clk_en <= '1';
counter := 0;
else
rx_clk_en <= '0';
counter := counter + 1;
end if;
-- Reset condition
if rst = RST_LVL then
rx_clk_en <= '0';
counter := 0;
end if;
end if;
end process;
rx_proc:process(clk)
begin
if clk'event and clk = '1' then
-- Default values
rx_ready <= '0';
-- Enable on UART rate
if rx_clk_en = '1' then
-- FSM description
case rx_fsm is
-- Wait to transfer data
when idle =>
if rx_data_deb = UART_START then
rx_fsm <= data;
end if;
rx_par_bit <= '0';
rx_data_cnt <= (others=>'0');
-- Data receive
when data =>
-- Check data to generate parity
if par_en = PARITY_EN then
rx_par_bit <= rx_par_bit xor rx;
end if;
if rx_data_cnt = 7 then
-- Data path
rx_data(7) <= rx;
for i in 0 to 6 loop
rx_data(i) <= rx_data_tmp(6-i);
end loop;
-- With parity verification
if par_en = PARITY_EN then
rx_fsm <= parity;
-- Without parity verification
else
rx_ready <= '1';
rx_fsm <= idle;
end if;
else
rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
rx_data_cnt <= rx_data_cnt + 1;
end if;
when parity =>
-- Check received parity
rx_fsm <= idle;
if rx_par_bit = rx then
rx_ready <= '1';
end if;
when others => null;
end case;
-- Reset condition
if rst = RST_LVL then
rx_fsm <= idle;
rx_ready <= '0';
rx_data <= (others=>'0');
rx_data_tmp <= (others=>'0');
rx_data_cnt <= (others=>'0');
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 3a897e58d5996c826982eb02b1fb74cc | 0.555227 | 2.70916 | false | false | false | false |
dtysky/Led_Array | VHDL_TEST/IMG3.vhd | 1 | 6,147 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: IMG3.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY IMG3 IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END IMG3;
ARCHITECTURE SYN OF img3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(39 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./ROM/IMG3.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 40,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/IMG3.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "40"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/IMG3.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 40 0 @q_a 0 0 40 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | c9b22f22c794964b5a0279572fa1824c | 0.666667 | 3.530729 | false | false | false | false |
dtysky/Led_Array | VHDL_TEST/IMG2.vhd | 1 | 6,147 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: IMG2.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY IMG2 IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END IMG2;
ARCHITECTURE SYN OF img2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(39 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./ROM/IMG2.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 40,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/IMG2.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "40"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/IMG2.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 40 0 @q_a 0 0 40 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG2.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 6c68cf8296cc928f885bf5c986092896 | 0.666667 | 3.530729 | false | false | false | false |
MattProtas/FPGA | Projects/DE0_Nano_Examples/SoC_FPGA/my_first_hps-fpga/fpga-rtl/soc_system/soc_system_inst.vhd | 1 | 19,113 | component soc_system is
port (
clk_clk : in std_logic := 'X'; -- clk
hps_0_f2h_cold_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_debug_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_f2h_stm_hw_events_stm_hwevents : in std_logic_vector(27 downto 0) := (others => 'X'); -- stm_hwevents
hps_0_f2h_warm_reset_req_reset_n : in std_logic := 'X'; -- reset_n
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_led_external_connection_export : out std_logic_vector(7 downto 0) -- export
);
end component soc_system;
u0 : component soc_system
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hps_0_f2h_cold_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_cold_reset_req_reset_n, -- hps_0_f2h_cold_reset_req.reset_n
hps_0_f2h_debug_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_debug_reset_req_reset_n, -- hps_0_f2h_debug_reset_req.reset_n
hps_0_f2h_stm_hw_events_stm_hwevents => CONNECTED_TO_hps_0_f2h_stm_hw_events_stm_hwevents, -- hps_0_f2h_stm_hw_events.stm_hwevents
hps_0_f2h_warm_reset_req_reset_n => CONNECTED_TO_hps_0_f2h_warm_reset_req_reset_n, -- hps_0_f2h_warm_reset_req.reset_n
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
pio_led_external_connection_export => CONNECTED_TO_pio_led_external_connection_export -- pio_led_external_connection.export
);
| mit | 7569ac70b967bbcdb8cf8ca7946de8d3 | 0.457804 | 2.913123 | false | false | false | false |
MattProtas/FPGA | Projects/DE0_Nano_Examples/SoC_FPGA/HPS_CONTROL_FPGA_LED/HPS_CONTROL_FPGA_LED/soc_system/soc_system_inst.vhd | 1 | 18,819 | component soc_system is
port (
button_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
clk_clk : in std_logic := 'X'; -- clk
dipsw_pio_external_connection_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
hps_0_h2f_reset_reset_n : out std_logic; -- reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
led_pio_external_connection_export : out std_logic_vector(7 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component soc_system;
u0 : component soc_system
port map (
button_pio_external_connection_export => CONNECTED_TO_button_pio_external_connection_export, -- button_pio_external_connection.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
dipsw_pio_external_connection_export => CONNECTED_TO_dipsw_pio_external_connection_export, -- dipsw_pio_external_connection.export
hps_0_h2f_reset_reset_n => CONNECTED_TO_hps_0_h2f_reset_reset_n, -- hps_0_h2f_reset.reset_n
hps_0_hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_0_hps_io.hps_io_emac1_inst_TX_CLK
hps_0_hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_0_hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_0_hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_0_hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_0_hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_0_hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_0_hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_0_hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_0_hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_0_hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_0_hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_0_hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_0_hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_0_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_0_hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_0_hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_0_hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_0_hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_0_hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_0_hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_0_hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_0_hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_0_hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_0_hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_0_hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_0_hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_0_hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_0_hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_0_hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_0_hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_0_hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_0_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_0_hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_0_hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_0_hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_0_hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_0_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_0_hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_0_hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_0_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_0_hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_0_hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_0_hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_0_hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_0_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_0_hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_0_hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_0_hps_io_hps_io_gpio_inst_GPIO40 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO40, -- .hps_io_gpio_inst_GPIO40
hps_0_hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_0_hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_0_hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_0_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
led_pio_external_connection_export => CONNECTED_TO_led_pio_external_connection_export, -- led_pio_external_connection.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
| mit | e42ef5a1c937d563b2f71cd41d908a21 | 0.454222 | 2.985721 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/program.vhd | 1 | 191,072 | -------------------------------------------------------------------
-- FPGA Audio Project SoC IP
-- V0.1
-- Ultra-Embedded.com
--
-- This file was derived from the Plasma project by Steve Rhoads.
-- It has been modified to support dual port block RAM and contains
-- the FPGA-Audio Bootloader image.
--
-- Original copyright notice:
--
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic
(
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 1
);
port
(
-- Port A
clka_i : in std_logic;
ena_i : in std_logic;
wea_i : in std_logic_vector(3 downto 0);
addra_i : in std_logic_vector(31 downto 2);
dataa_i : in std_logic_vector(31 downto 0);
dataa_o : out std_logic_vector(31 downto 0);
-- Port B
clkb_i : in std_logic;
enb_i : in std_logic;
web_i : in std_logic_vector(3 downto 0);
addrb_i : in std_logic_vector(31 downto 2);
datab_i : in std_logic_vector(31 downto 0);
datab_o : out std_logic_vector(31 downto 0)
);
end;
architecture logic of ram is
-----------------------------------------------
-- Signals
-----------------------------------------------
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
-- Which 8KB block
alias block_a_sel: std_logic_vector(2 downto 0) is addra_i(15 downto 13);
alias block_b_sel: std_logic_vector(2 downto 0) is addrb_i(15 downto 13);
-- Address within a 8KB block (without lower two bits)
alias block_a_addr : std_logic_vector(10 downto 0) is addra_i(12 downto 2);
alias block_b_addr : std_logic_vector(10 downto 0) is addrb_i(12 downto 2);
-- Block ena_i with 1 bit per memory block
signal block_a_enable: std_logic_vector(7 downto 0);
signal block_b_enable: std_logic_vector(7 downto 0);
-- Block Data Out
signal block_a_do: mem32_vector(7 downto 0);
signal block_b_do: mem32_vector(7 downto 0);
-- Remember which block was selected
signal block_a_sel_buf: std_logic_vector(2 downto 0);
signal block_b_sel_buf: std_logic_vector(2 downto 0);
constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
-----------------------------------------------
-- Port A
-----------------------------------------------
block_a_enable <= "00000001" when (ena_i='1') and (block_a_sel="000") else
"00000010" when (ena_i='1') and (block_a_sel="001") else
"00000100" when (ena_i='1') and (block_a_sel="010") else
"00001000" when (ena_i='1') and (block_a_sel="011") else
"00010000" when (ena_i='1') and (block_a_sel="100") else
"00100000" when (ena_i='1') and (block_a_sel="101") else
"01000000" when (ena_i='1') and (block_a_sel="110") else
"10000000" when (ena_i='1') and (block_a_sel="111") else
"00000000";
process (clka_i, block_a_sel) is
begin
if rising_edge(clka_i) then
block_a_sel_buf <= block_a_sel;
end if;
end process;
process (block_a_do, block_a_sel_buf) is
begin
dataa_o <= block_a_do(conv_integer(block_a_sel_buf));
end process;
-----------------------------------------------
-- Port B
-----------------------------------------------
block_b_enable <= "00000001" when (enb_i='1') and (block_b_sel="000") else
"00000010" when (enb_i='1') and (block_b_sel="001") else
"00000100" when (enb_i='1') and (block_b_sel="010") else
"00001000" when (enb_i='1') and (block_b_sel="011") else
"00010000" when (enb_i='1') and (block_b_sel="100") else
"00100000" when (enb_i='1') and (block_b_sel="101") else
"01000000" when (enb_i='1') and (block_b_sel="110") else
"10000000" when (enb_i='1') and (block_b_sel="111") else
"00000000";
process (clkb_i, block_b_sel) is
begin
if rising_edge(clkb_i) then
block_b_sel_buf <= block_b_sel;
end if;
end process;
process (block_b_do, block_b_sel_buf) is
begin
datab_o <= block_b_do(conv_integer(block_b_sel_buf));
end process;
-----------------------------------------------
-- BRAM
-----------------------------------------------
-- BLOCKS generation
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"00243c27038f8faf14af2c27000c40000008000c241400ac273c243c243c273c",
INIT_01 => X"0c263c0008020c263c0008020c263c0008020c263c0008020c263c0000008c00",
INIT_02 => X"0c00140010000c262426243c0c3c243c40afafafafaf270008020c263c000802",
INIT_03 => X"8f8f001430008c3cac3caf12240000af27000300083c0c020c0014000c240c02",
INIT_04 => X"82260c2610008000afaf2730038c3c240300038c001030008c3c3c08240c2703",
INIT_05 => X"2400900000243c001800108f000300140000008c3c8c3c000327038f8f001400",
INIT_06 => X"1424108f2d01110003af01af001424a0009000002424013c8f00148f2d01a014",
INIT_07 => X"8f8e3cafafaf2700080000008faf04af020c260caf3c2424af3c3caf27af0800",
INIT_08 => X"10afafafafafafafafafaf278faf03af27038f8f8f00142c00008e0004000000",
INIT_09 => X"00008f8e00040000008faf008e00008f3c3c24243c24afaf0000242410008f00",
INIT_0A => X"008faf008eafafa22610248f0010001000088f0018008faf000024008f00142c",
INIT_0B => X"04af00008f8eaf08241400008f8faf0c000024008f00142c00008f8e3c040000",
INIT_0C => X"af003c0024248f8f00082400008f240c001400040000008f00102c00008f8e00",
INIT_0D => X"8f8f028f0002002400008f000c0008af0caf000024248f001130009191a01025",
INIT_0E => X"24000824002490273c002531010091912512af0824a22427038f8f8f8f8f8f8f",
INIT_0F => X"00000800153000919126af082415302624120014001430142438000400003010",
INIT_10 => X"8f2400008f2400008f240c0008af0caf000024008f241000913014002490273c",
INIT_11 => X"4b42004153000000000000000000240832088fafaf2624242624020008240000",
INIT_12 => X"0000000000000000617420740a00617420740a0020740a0044214d5446004945",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(0)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"044202bde0b0bfb040bf82bd0000040000000000a560a4a0bd1d8404a5059c1c",
INIT_01 => X"0010100000000010100000000010100000000010100000000010100040008244",
INIT_02 => X"0000510050000052117310120013840480b0b1b2b3bfbd000000001010000000",
INIT_03 => X"b0bf0040420062035002bf02021004b0bd00e000000400600000500000040040",
INIT_04 => X"0410001080008480bfb0bd42e0420202e000e04200606300430202000400bde0",
INIT_05 => X"42e26682e8e70700a000a08800e00060646200a305420200e0bde0b0bf008000",
INIT_06 => X"6003408902050000e085258044464243006344e246e722078200408902056645",
INIT_07 => X"821110b1bfb0bd00000040008280408000001000bf1084a5b0040584bd880000",
INIT_08 => X"40b0b1b2b3b5b6b7bebfb4bd8285e084bde0b0b1bf0040425100020041004000",
INIT_09 => X"4300a302004100400082a600060040a4131e15161017a5a30000050360008380",
INIT_0A => X"0082a30003a0a66246a303a50055005600008200a000a5a20202a200a5004042",
INIT_0B => X"41a640008206a6000640c300a3a6a2000202a200a50040424400a40203410040",
INIT_0C => X"a6a6086663c6a5a6000004400082110000550040004000820060636400a40300",
INIT_0D => X"b7be20bf0080000440008200000000a500a202026205a3002242020902826008",
INIT_0E => X"63a200e70503e5c70400084a420a020a0640a600126206bde0b0b1b2b3b4b5b6",
INIT_0F => X"00000000224202090268a300032242e205e9004a00e8426063c202a10502c260",
INIT_10 => X"82044000820440008211000000a500a202026200a3054300026346654245c204",
INIT_11 => X"2152004c590000000000000000001100f70082a6a5310605f784800000044000",
INIT_12 => X"00000000000000006c65285242006c6528524200565242004900552141004e58",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(0)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"2008000000000000000000ff000068000000000000ff18000e000e0009008900",
INIT_01 => X"0008000000200009000000200009000000200009000000200009000000000020",
INIT_02 => X"0000ff00000000090009000000000900600000000000ff000020000800000020",
INIT_03 => X"000000ff000000200020000000868600ff000000001000200000ff0000200020",
INIT_04 => X"ff000000000000800000ff00000020ff00000000000000000020200000000000",
INIT_05 => X"001800183809001000000080000000ff1818000020002000000000000000ff00",
INIT_06 => X"ff00ff800040ff100080288018ff0000000018200009100080180080004000ff",
INIT_07 => X"800020000000ff000000f8008080ff80200102010000010200000080ff800000",
INIT_08 => X"0100000000000000000000ff80800080000000000000ff0310000000ff00f800",
INIT_09 => X"10000000000000f8008000000000f800000000002000000090880000010080a0",
INIT_0A => X"008000000000000a000000000000000000018000000000001616ff000000ff03",
INIT_0B => X"0000f8008000000100001000000000001616ff000000ff0310000000000000f8",
INIT_0C => X"001800200a000000000100f80080ff0000ff00ff00f8008000ff031800000000",
INIT_0D => X"0000100028f82000f80080000000010000001616ff000000000010000000ff0a",
INIT_0E => X"ff1001002a00000a001000ff5052000000000001000a00000000000000000000",
INIT_0F => X"18000100ff001000000a0001000000ff000000ff00ffffffff1030ff2c2cff00",
INIT_10 => X"8000f8008000f80080ff0000010000001616ff000000ff000000ff1800000a00",
INIT_11 => X"0045004c53000000000000000100ff010001800000000000000af8000100f800",
INIT_12 => X"00000000000000002972494f6f002972454f6f00324f6f0056004c0055005454",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(0)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"80c8001808101410051409e800140000000e004904fd2a008000900070006001",
INIT_01 => X"95f800003921950000003321950c00002d21951400002721951c000008000021",
INIT_02 => X"9500fb000b00864c49344500950024000014181c2024d800452195ec00003f21",
INIT_03 => X"101400fc080004000800140d0a030010e80008005900e3219500f7008600e321",
INIT_04 => X"ff016f01070000211410e801080400ff0800080800040100040000770d6f1808",
INIT_05 => X"01210021218800210a002318000800fb2a23001000100000081808101400fb00",
INIT_06 => X"e701e9148021fd210814211821fb0100000021238088210010211914802100fb",
INIT_07 => X"201000181c14e000f70009001018fc142113d0101400bc1810000010e818d500",
INIT_08 => X"102024282c34383c404430b81c20081c200814181c00f5e823001000fa000900",
INIT_09 => X"230010100015000900201000100009140000180400011418212143100c002021",
INIT_0A => X"0020100010141c08827243140027006200301c00c90018180300ff001800f4e8",
INIT_0B => X"0e10090020101449157f2a00141c18f90300ff001800f4e82300101000350009",
INIT_0C => X"142a002108011c1400bc0609001cfff900c500f40009002000cde82300101000",
INIT_0D => X"3c4021442109210609001c00f9004914f9180300ff15180026ff27010200b908",
INIT_0E => X"ff26e2010008000b002183ff2100848383301c5a01088348082024282c303438",
INIT_0F => X"2100ce00adff2701020814490622ffff803600bc00eefff9ff2140fa0300ff09",
INIT_10 => X"1c1809001c1809001cfff9004914f9180300ff001815e40083fffc2101000b00",
INIT_11 => X"00410021439494acacc4dcf40c64ffbcff301c1418800610010b0900bc180900",
INIT_12 => X"00000000000000000a6e6e4d6f000a6e784d6f000a4d6f00210054004c00215f",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(0)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(0),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(0)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(0),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(1)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(1)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(1)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(1)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(1),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(1)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(1),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(2)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(2)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(2)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(2)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(2),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(2)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(2),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(3)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(3)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(3)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(3)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(3),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(3)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(3),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(4)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(4)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(4)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(4)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(4),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(4)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(4),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(5)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(5)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(5)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(5)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(5),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(5)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(5),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(6)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(6)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(6)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(6)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(6),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(6)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(6),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(31 downto 24),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(31 downto 24),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(3),
DOB => block_b_do(7)(31 downto 24),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(31 downto 24),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(3)
);
ram_byte2 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(23 downto 16),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(23 downto 16),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(2),
DOB => block_b_do(7)(23 downto 16),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(23 downto 16),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(2)
);
ram_byte1 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(15 downto 8),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(15 downto 8),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(1),
DOB => block_b_do(7)(15 downto 8),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(15 downto 8),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(1)
);
ram_byte0 : RAMB16_S9_S9
generic map (
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DOA => block_a_do(7)(7 downto 0),
DOPA => open,
ADDRA => block_a_addr,
CLKA => clka_i,
DIA => dataa_i(7 downto 0),
DIPA => ZERO(0 downto 0),
ENA => block_a_enable(7),
SSRA => ZERO(0),
WEA => wea_i(0),
DOB => block_b_do(7)(7 downto 0),
DOPB => open,
ADDRB => block_b_addr,
CLKB => clkb_i,
DIB => datab_i(7 downto 0),
DIPB => ZERO(0 downto 0),
ENB => block_b_enable(7),
SSRB => ZERO(0),
WEB => web_i(0)
);
end generate; --block7
end; --architecture logic
| mit | b88023044d6a349d4a31ab1d88dbe0f2 | 0.82998 | 6.397214 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/RegHold_Falling8.vhd | 1 | 2,255 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: 24bit_Register
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
-- 24 bit register with a hold lock the input state just
-- incase input conflict later
--
-- Notes:
-- HOLD Clocked on FALLING EDGE
-- OUTPUT Clocked on rising EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
-- 0.05 - Forked and added a input hold for the register
--
-- Additional Comments:
-- The register latches it's output data on the Rising edge
-- Hold latch on the falling edge
-- The main reason why I included a hold latch was to Prevent
-- Any register transfer faults that could occur.
-- Mostly acts as a safety buffer.
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegHold_F8 IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(MEM_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(MEM_WIDTH-1 DOWNTO 0)
);
END RegHold_F8;
ARCHITECTURE Behavior OF RegHold_F8 IS
SIGNAL HOLD : STD_LOGIC_VECTOR(MEM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS(Resetn, Clock,ENABLE)
BEGIN
IF Resetn = '0' THEN
HOLD <= (OTHERS => '0');
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= HOLD;
END IF;
IF Clock'EVENT AND Clock = '0' THEN
HOLD <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 84908879330d0f3b77465a83d33ff7f8 | 0.562306 | 3.648867 | false | false | false | false |
aleksandar-mitrevski/hw_sw | up_down_counter/testbench.vhd | 1 | 1,337 | Library IEEE;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_unsigned.All;
Entity testbench Is End testbench;
Architecture tb_upDownCounter Of testbench Is
Signal clk : STD_LOGIC := '1';
Signal inputSwitch : STD_LOGIC := '0';
Signal led0 : STD_LOGIC;
Signal led1 : STD_LOGIC;
Signal led2 : STD_LOGIC;
Signal led3 : STD_LOGIC;
Signal counter : integer range 0 to 4;
Signal clockCounter : integer range 0 to 50000000;
Constant twenty_five_nsec : time := 25 ns;
Component upDownCounter Port (
clk: in STD_LOGIC;
inputSwitch : in STD_LOGIC;
led0 : out STD_LOGIC;
led1 : out STD_LOGIC;
led2 : out STD_LOGIC;
led3 : out STD_LOGIC;
counter : inout integer range 0 to 4;
clockCounter : inout integer range 0 to 5);
End Component upDownCounter;
Begin
upDownCounter1 : upDownCounter
Port Map (
inputSwitch => inputSwitch,
clk => clk,
led0 => led0,
led1 => led1,
led2 => led2,
led3 => led3,
counter => counter,
clockCounter => clockCounter);
create_twenty_Mhz: Process
Begin
Wait For twenty_five_nsec;
clk <= NOT clk;
End Process;
inputSwitch <= '1' After 500 ns,
'0' After 1500 ns;
End tb_upDownCounter; | mit | 95c410fc301ce0eea8eb2ac3f4c8d94c | 0.602842 | 3.734637 | false | true | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/memoria/simulation/memoria_tb.vhd | 2 | 4,349 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: memoria_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY memoria_tb IS
END ENTITY;
ARCHITECTURE memoria_tb_ARCH OF memoria_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
memoria_synth_inst:ENTITY work.memoria_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | f7956c054c6af7ed856af9f2cc675491 | 0.619913 | 4.676344 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/VGA Read - Write/scan_to_hex.vhd | 1 | 3,690 | --------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron, Daniel Noyes
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Scan to Hex
-- Module Name: scan_to_hex
-- Project Name: Risc Machine Project 1
-- Target Device: Spartan 3E Board
-- Tool versions: Xilinx 14.7
-- Description: This code takes in keystrokes and places them in a buffer.
-- The buffer is then read into a translator, changing it from scancode to hex values.
-- The hex values are then sent to the FPU once the enter key is pressed.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: N/A
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity scan_to_hex is
Port (
Send : in STD_LOGIC; -- tells when input signal happens
Resetn : in STD_LOGIC;
scancode : in STD_LOGIC_VECTOR (7 downto 0); -- The input code
output : out STD_LOGIC_VECTOR (23 downto 0); -- The output code
outCount : out STD_LOGIC_VECTOR (3 downto 0);
hexdebug : out STD_LOGIC_VECTOR (3 downto 0);
outbufdebug: out STD_LOGIC_VECTOR (63 downto 0)
);
end scan_to_hex;
architecture Behavioral of scan_to_hex is
--signal Counter : STD_LOGIC_VECTOR(3 downto 0):= (others => '0'); -- range (0 to 15);
signal Counter : integer range 0 to 15;
signal Hex : STD_LOGIC_VECTOR(3 downto 0);
signal OutB : STD_LOGIC_VECTOR(23 downto 0);
type Buff_type is array (0 to 15)
of std_logic_vector (3 downto 0);
signal Buff: Buff_type;
begin
outbufdebug(63 downto 60) <= Buff(0);
outbufdebug(59 downto 56) <= Buff(1);
outbufdebug(55 downto 52) <= Buff(2);
outbufdebug(51 downto 48) <= Buff(3);
outbufdebug(47 downto 44) <= Buff(4);
outbufdebug(43 downto 40) <= Buff(5);
outbufdebug(39 downto 36) <= Buff(6);
outbufdebug(35 downto 32) <= Buff(7);
outbufdebug(31 downto 28) <= Buff(8);
outbufdebug(27 downto 24) <= Buff(9);
outbufdebug(23 downto 20) <= Buff(10);
outbufdebug(19 downto 16) <= Buff(11);
outbufdebug(15 downto 12) <= Buff(12);
outbufdebug(11 downto 8) <= Buff(13);
outbufdebug(7 downto 4) <= Buff(14);
outbufdebug(3 downto 0) <= Buff(15);
outCount <= conv_std_logic_vector(counter, 4);
with scancode select
Hex<=x"0" when x"45",--0
x"1" when x"16",--1
x"2" when x"1e",--2
x"3" when x"26",--3
x"4" when x"25",--4
x"5" when x"2e",--5
x"6" when x"36",--6
x"7" when x"3d",--7
x"8" when x"3e",--8
x"9" when x"46",--9
x"A" when x"1c",--a
x"B" when x"32",--b
x"C" when x"21",--c
x"D" when x"23",--d
x"E" when x"24",--e
x"F" when x"2b",--f
"ZZZZ" when others;
Hexdebug <= Hex;
output <= OutB;
process(Send)
begin
if Resetn = '0' then
OutB <= (others => '0');
Buff <= (others => (others =>'0'));
else
-- Keyboard Complete Signal
if send'event and Send = '0' then
if scancode = X"5A" then -- Enter Key
OutB(23 downto 20) <= buff(counter - 6);
OutB(19 downto 16) <= buff(counter - 5);
OutB(15 downto 12) <= buff(counter - 4);
OutB(11 downto 8) <= buff(counter - 3);
OutB(7 downto 4) <= buff(counter - 2);
OutB(3 downto 0) <= buff(counter - 1);
else
if scancode = X"66" then
counter <= counter - 1;
else
buff(counter) <= Hex;
counter <= counter + 1;
end if;
end if;
end if;
end if;
end process;
-- "1111111" when x"66",-- backspace : Initially 1111111, changed to 0001000 due to lab
-- -- changed back, brandyn didn't have errors.
-- "1111111" when x"29",--space bar
-- "0000000" when others;
end Behavioral;
| mit | e2781502b50430187a653c7cdb65d8e6 | 0.609214 | 2.928571 | false | false | false | false |
ErikAndren/fpga-sramtest | tb.vhd | 1 | 4,849 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.Types.all;
entity tb is
end entity;
architecture rtl of tb is
signal Clk : bit1;
signal Rst_N : bit1;
component CY7C1365_FT
generic (
addr_bits : natural := 18;
data_bits : natural := 32;
mem_sizes : natural := 524288
);
port (
DQ : inout word(data_bits-1 downto 0);
ADDR : in word(addr_bits-1 downto 0);
ADV_N : in bit1;
CLK : in bit1;
ADSC_N : in bit1;
ASDP_N : in bit1;
BWa_N : in bit1;
BWb_N : in bit1;
BWc_N : in bit1;
BWd_N : in bit1;
GW_N : in bit1;
CE1_N : in bit1;
CE2 : in bit1;
CE3_N : in bit1;
OE_N : in bit1;
ZZ : in bit1
);
end component;
signal sram_addr : word(18-1 downto 0);
signal sram_dq : word(32-1 downto 0);
signal sram_oe_n : bit1;
signal sram_ce1_n : bit1;
signal sram_we : bit1;
signal sram_be_n0 : bit1;
signal sram_be_n1 : bit1;
signal sram_be_n2 : bit1;
signal sram_be_n3 : bit1;
signal sram_adsc : bit1;
signal sram_clk : bit1;
begin
ClkProc : process
begin
while true loop
Clk <= '0';
wait for 20 ns;
Clk <= '1';
wait for 20 ns;
end loop;
end process;
RstProc : Process
begin
Rst_N <= '0';
wait for 300 ns;
Rst_N <= '1';
wait;
end Process;
sram_dq <= (others => 'Z');
DUT : entity work.SramTest
port map (
RootClk => Clk,
ARst_N => Rst_N,
--
flash_sram_a2 => sram_addr(0),
flash_sram_a3 => sram_addr(1),
flash_sram_a4 => sram_addr(2),
flash_sram_a5 => sram_addr(3),
flash_sram_a6 => sram_addr(4),
flash_sram_a7 => sram_addr(5),
flash_sram_a8 => sram_addr(6),
flash_sram_a9 => sram_addr(7),
flash_sram_a10 => sram_addr(8),
flash_sram_a11 => sram_addr(9),
flash_sram_a12 => sram_addr(10),
flash_sram_a13 => sram_addr(11),
flash_sram_a14 => sram_addr(12),
flash_sram_a15 => sram_addr(13),
flash_sram_a16 => sram_addr(14),
flash_sram_a17 => sram_addr(15),
flash_sram_a18 => sram_addr(16),
flash_sram_a19 => sram_addr(17),
flash_sram_a20 => open,
--
flash_sram_dq0 => sram_dq(0),
flash_sram_dq1 => sram_dq(1),
flash_sram_dq2 => sram_dq(2),
flash_sram_dq3 => sram_dq(3),
flash_sram_dq4 => sram_dq(4),
flash_sram_dq5 => sram_dq(5),
flash_sram_dq6 => sram_dq(6),
flash_sram_dq7 => sram_dq(7),
flash_sram_dq8 => sram_dq(8),
flash_sram_dq9 => sram_dq(9),
flash_sram_dq10 => sram_dq(10),
flash_sram_dq11 => sram_dq(11),
flash_sram_dq12 => sram_dq(12),
flash_sram_dq13 => sram_dq(13),
flash_sram_dq14 => sram_dq(14),
flash_sram_dq15 => sram_dq(15),
flash_sram_dq16 => sram_dq(16),
flash_sram_dq17 => sram_dq(17),
flash_sram_dq18 => sram_dq(18),
flash_sram_dq19 => sram_dq(19),
flash_sram_dq20 => sram_dq(20),
flash_sram_dq21 => sram_dq(21),
flash_sram_dq22 => sram_dq(22),
flash_sram_dq23 => sram_dq(23),
flash_sram_dq24 => sram_dq(24),
flash_sram_dq25 => sram_dq(25),
flash_sram_dq26 => sram_dq(26),
flash_sram_dq27 => sram_dq(27),
flash_sram_dq28 => sram_dq(28),
flash_sram_dq29 => sram_dq(29),
flash_sram_dq30 => sram_dq(30),
flash_sram_dq31 => sram_dq(31),
--
sram_oe_n => sram_oe_n,
sram_ce1_n => sram_ce1_n,
sram_we => sram_we,
sram_be_n0 => sram_be_n0,
sram_be_n1 => sram_be_n1,
sram_be_n2 => sram_be_n2,
sram_be_n3 => sram_be_n3,
sram_adsc => sram_adsc,
sram_clk => sram_clk,
--
--
Btn0 => '1',
Btn1 => '1',
Btn2 => '1',
Btn3 => '1',
--
Led0 => open,
Led1 => open,
Led2 => open,
Led3 => open
);
Sram : CY7C1365_FT
generic map (
addr_bits => 18,
data_bits => 32,
mem_sizes => 524288
)
port map (
DQ => sram_dq,
ADDR => sram_addr(18-1 downto 0),
ADV_N => '1',
CLK => sram_clk,
ADSC_N => sram_adsc,
ASDP_N => '1',
BWa_N => sram_be_n0,
BWb_N => sram_be_n1,
BWc_N => sram_be_n2,
BWd_N => sram_be_n3,
GW_N => '1',
CE1_N => sram_ce1_n,
CE2 => '1',
CE3_N => '0',
OE_N => sram_oe_n,
ZZ => '0'
);
end architecture;
| mit | b5683e31a484ed14578688b242115200 | 0.474118 | 2.83236 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/clock_divider.vhd | 1 | 1,903 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
kHz: out STD_LOGIC
);
end clock_divider;
architecture Behavioral of clock_divider is
-- Signals:
signal kilohertz: STD_LOGIC;
signal hundredhertz: STD_LOGIC;
signal tenhertz: STD_LOGIC;
signal onehertz: STD_LOGIC;
-- Components:
-- This is kind of like a function prototype in C/C++
component downcounter is
Generic ( period: integer:= 4;
WIDTH: integer:= 3);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
zero : out STD_LOGIC;
value: out STD_LOGIC_VECTOR(WIDTH-1 downto 0));
end component;
begin
kiloHzClock: downcounter
generic map(
period => (10-1), -- "110 0001 1010 0111" in binary
--WIDTH => 15
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => '1',
zero => kilohertz,
value => open -- Leave open since we won't display this value
);
hundredHzClock: downcounter
generic map(
period => (10-1), -- Counts numbers between 0 and 9 -> that's 10 values!
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => kilohertz,
zero => hundredhertz,
value => open -- Leave open since we won't display this value
);
tenHzClock: downcounter
generic map(
period => (10-1), -- Counts numbers between 0 and 9 -> that's 10 values!
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => hundredhertz,
zero => tenhertz,
value => open -- Leave open since we won't display this value
);
oneHZClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => tenhertz,
zero => onehertz,
value => open
);
-- Connect internal signals to outputs
kHz <= onehertz;
end Behavioral;
| unlicense | 85e739352a2531f29773754c2054ca3d | 0.611666 | 3.236395 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/memoria/simulation/memoria_synth.vhd | 2 | 6,824 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: memoria_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY memoria_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE memoria_synth_ARCH OF memoria_synth IS
COMPONENT memoria_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: memoria_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 2a9717a4af2735f63a58eea1a70e44d6 | 0.580598 | 3.820829 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/mcb_raw_wrapper.vhd | 1 | 292,562 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_raw_wrapper.v
-- /___/ /\ Date Last Modified: $Date: 2010/06/04 11:24:37 $
-- \ \ / \ Date Created: Thu June 24 2008
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose:
--Reference:
-- This module is the intialization control logic of the memory interface.
-- All commands are issued from here acoording to the burst, CAS Latency and
-- the user commands.
--
-- Revised History:
-- Rev 1.1 - added port_enable assignment for all configurations and rearrange
-- assignment siganls according to port number
-- - added timescale directive -SN 7-28-08
-- - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through
-- 15 -SN 7-28-08
-- - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08
-- - removed ghighb, gpwrdnb, gsr, gwe in port declaration.
-- For now tb need to force the signals inside the MCB and Wrapper
-- until a glbl.v is ready. Not sure how to do this in NCVerilog
-- flow. -SN 7-28-08
--
-- Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08
-- Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5 - SN 8-8-08
-- Rev 1.4 -- update changes that required by MCB core. - SN 9-11-09
-- Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08
-- delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90
-- delay_we_90 ,delay_address,delay_ba_90 =
-- --removed :assign #50 delay_dqnum = dqnum;
-- --removed :assign #50 delay_dqpum = dqpum;
-- --removed :assign #50 delay_dqnlm = dqnlm;
-- --removed :assign #50 delay_dqplm = dqplm;
-- --removed : delay_dqsIO_w_en_90_n
-- --removed : delay_dqsIO_w_en_90_p
-- --removed : delay_dqsIO_w_en_0
-- -- corrected spelling error: C_MEM_RTRAS
-- Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip. 1-12-09
-- -- rename the memc_wrapper.v to mcb_raw_wrapper.v
-- Rev 1.7 -- -- .READEN is removed in IODRP2_MCB 1-28-09
-- -- connection has been updated
-- Rev 1.8 -- update memory parameter equations. 1-30_2009
-- -- added portion of Soft IP
-- -- CAL_CLK_DIV is not used but MCB still has it
-- Rev 1.9 -- added Error checking for Invalid command to unidirectional port
-- Rev 1.10 -- changed the backend connection so that Simulation will work while
-- sw tools try to fix the model issues. 2-3-2009
-- sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.
-- It is acutally 180 degree difference.
-- Rev 1.11 -- Added MCB_Soft_Calibration_top.
-- Rev 1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009
-- Rev 1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.
-- Rev 1.14 -- Added minium condition for tRTP valud/
-- REv 1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top. 6-16-2009
-- Rev 1.16 -- Fixed the WTR for DDR. 6-23-2009
-- Rev 1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009
-- Rev 1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010
-- Rev 1.19 -- Added soft fix to support refresh command. 7-15-2009.
-- Rev 1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable
-- Dynamic DQS calibration in Soft Calibration module.
-- Rev 1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if
-- RTT value is set to "disabled"
-- -- Corrected the UIUDQSDEC connection between soft_calib and MCB.
-- -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010
-- Rev 1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- Rev 1.23 -- Fixed CR 558661. In Config "B64B64" mode, mig_p5_wr_data <= p1_wr_data(63 downto 32).
--*************************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_raw_wrapper is
generic(
C_MEMCLK_PERIOD : integer := 2500;
C_PORT_ENABLE : std_logic_vector(5 downto 0) := (others => '1');
C_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C_ARB_NUM_TIME_SLOTS : integer := 12;
C_ARB_TIME_SLOT_0 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_1 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_2 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_3 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_4 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_5 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_ARB_TIME_SLOT_6 : bit_vector(17 downto 0):= "000" & "001" & "010" & "011" & "100" & "101";
C_ARB_TIME_SLOT_7 : bit_vector(17 downto 0):= "001" & "010" & "011" & "100" & "101" & "000";
C_ARB_TIME_SLOT_8 : bit_vector(17 downto 0):= "010" & "011" & "100" & "101" & "000" & "011";
C_ARB_TIME_SLOT_9 : bit_vector(17 downto 0):= "011" & "100" & "101" & "000" & "001" & "010";
C_ARB_TIME_SLOT_10 : bit_vector(17 downto 0):= "100" & "101" & "000" & "001" & "010" & "011";
C_ARB_TIME_SLOT_11 : bit_vector(17 downto 0):= "101" & "000" & "001" & "010" & "011" & "100";
C_PORT_CONFIG : string := "B32_B32_W32_W32_W32_W32";
C_MEM_TRAS : integer := 45000;
C_MEM_TRCD : integer := 12500;
C_MEM_TREFI : integer := 7800;
C_MEM_TRFC : integer := 127500;
C_MEM_TRP : integer := 12500;
C_MEM_TWR : integer := 15000;
C_MEM_TRTP : integer := 7500;
C_MEM_TWTR : integer := 7500;
C_NUM_DQ_PINS : integer := 8;
C_MEM_TYPE : string := "DDR3";
C_MEM_DENSITY : string := "512M";
C_MEM_BURST_LEN : integer := 8;
C_MEM_CAS_LATENCY : integer := 4;
C_MEM_ADDR_WIDTH : integer := 13;
C_MEM_BANKADDR_WIDTH : integer := 3;
C_MEM_NUM_COL_BITS : integer := 11;
C_MEM_DDR3_CAS_LATENCY : integer := 7;
C_MEM_MOBILE_PA_SR : string := "FULL";
C_MEM_DDR1_2_ODS : string := "FULL";
C_MEM_DDR3_ODS : string := "DIV6";
C_MEM_DDR2_RTT : string := "50OHMS";
C_MEM_DDR3_RTT : string := "DIV2";
C_MEM_MDDR_ODS : string := "FULL";
C_MEM_DDR2_DIFF_DQS_EN : string := "YES";
C_MEM_DDR2_3_PA_SR : string := "OFF";
C_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
C_MEM_DDR3_AUTO_SR : string := "ENABLED";
C_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
C_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIB_BYPASS : string := "NO";
C_MC_CALIBRATION_RA : bit_vector(15 downto 0) := X"0000";
C_MC_CALIBRATION_BA : bit_vector(2 downto 0) := "000";
C_CALIB_SOFT_IP : string := "TRUE";
C_SKIP_IN_TERM_CAL : integer := 0; --provides option to skip the input termination calibration
C_SKIP_DYNAMIC_CAL : integer := 0; --provides option to skip the dynamic delay calibration
C_SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
--- ADDED for 1.0 silicon support to bypass Calibration //////
-- 07-10-09 chipl
--////////////////////////////////////////////////////////////
LDQSP_TAP_DELAY_VAL : integer := 0;
UDQSP_TAP_DELAY_VAL : integer := 0;
LDQSN_TAP_DELAY_VAL : integer := 0;
UDQSN_TAP_DELAY_VAL : integer := 0;
DQ0_TAP_DELAY_VAL : integer := 0;
DQ1_TAP_DELAY_VAL : integer := 0;
DQ2_TAP_DELAY_VAL : integer := 0;
DQ3_TAP_DELAY_VAL : integer := 0;
DQ4_TAP_DELAY_VAL : integer := 0;
DQ5_TAP_DELAY_VAL : integer := 0;
DQ6_TAP_DELAY_VAL : integer := 0;
DQ7_TAP_DELAY_VAL : integer := 0;
DQ8_TAP_DELAY_VAL : integer := 0;
DQ9_TAP_DELAY_VAL : integer := 0;
DQ10_TAP_DELAY_VAL : integer := 0;
DQ11_TAP_DELAY_VAL : integer := 0;
DQ12_TAP_DELAY_VAL : integer := 0;
DQ13_TAP_DELAY_VAL : integer := 0;
DQ14_TAP_DELAY_VAL : integer := 0;
DQ15_TAP_DELAY_VAL : integer := 0;
C_MC_CALIBRATION_CA : bit_vector(11 downto 0) := X"000";
C_MC_CALIBRATION_CLK_DIV : integer := 1;
C_MC_CALIBRATION_MODE : string := "CALIBRATION";
C_MC_CALIBRATION_DELAY : string := "HALF";
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32
);
PORT (
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
sys_rst : in std_logic;
p0_arb_en : in std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_arb_en : in std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_arb_en : in std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_arb_en : in std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
p4_arb_en : in std_logic;
p4_cmd_clk : in std_logic;
p4_cmd_en : in std_logic;
p4_cmd_instr : in std_logic_vector(2 downto 0);
p4_cmd_bl : in std_logic_vector(5 downto 0);
p4_cmd_byte_addr : in std_logic_vector(29 downto 0);
p4_cmd_empty : out std_logic;
p4_cmd_full : out std_logic;
p4_wr_clk : in std_logic;
p4_wr_en : in std_logic;
p4_wr_mask : in std_logic_vector(3 downto 0);
p4_wr_data : in std_logic_vector(31 downto 0);
p4_wr_full : out std_logic;
p4_wr_empty : out std_logic;
p4_wr_count : out std_logic_vector(6 downto 0);
p4_wr_underrun : out std_logic;
p4_wr_error : out std_logic;
p4_rd_clk : in std_logic;
p4_rd_en : in std_logic;
p4_rd_data : out std_logic_vector(31 downto 0);
p4_rd_full : out std_logic;
p4_rd_empty : out std_logic;
p4_rd_count : out std_logic_vector(6 downto 0);
p4_rd_overflow : out std_logic;
p4_rd_error : out std_logic;
p5_arb_en : in std_logic;
p5_cmd_clk : in std_logic;
p5_cmd_en : in std_logic;
p5_cmd_instr : in std_logic_vector(2 downto 0);
p5_cmd_bl : in std_logic_vector(5 downto 0);
p5_cmd_byte_addr : in std_logic_vector(29 downto 0);
p5_cmd_empty : out std_logic;
p5_cmd_full : out std_logic;
p5_wr_clk : in std_logic;
p5_wr_en : in std_logic;
p5_wr_mask : in std_logic_vector(3 downto 0);
p5_wr_data : in std_logic_vector(31 downto 0);
p5_wr_full : out std_logic;
p5_wr_empty : out std_logic;
p5_wr_count : out std_logic_vector(6 downto 0);
p5_wr_underrun : out std_logic;
p5_wr_error : out std_logic;
p5_rd_clk : in std_logic;
p5_rd_en : in std_logic;
p5_rd_data : out std_logic_vector(31 downto 0);
p5_rd_full : out std_logic;
p5_rd_empty : out std_logic;
p5_rd_count : out std_logic_vector(6 downto 0);
p5_rd_overflow : out std_logic;
p5_rd_error : out std_logic;
mcbx_dram_addr : out std_logic_vector(C_MEM_ADDR_WIDTH - 1 downto 0);
mcbx_dram_ba : out std_logic_vector(C_MEM_BANKADDR_WIDTH - 1 downto 0);
mcbx_dram_ras_n : out std_logic;
mcbx_dram_cas_n : out std_logic;
mcbx_dram_we_n : out std_logic;
mcbx_dram_cke : out std_logic;
mcbx_dram_clk : out std_logic;
mcbx_dram_clk_n : out std_logic;
mcbx_dram_dq : INOUT std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
mcbx_dram_dqs : INOUT std_logic;
mcbx_dram_dqs_n : INOUT std_logic;
mcbx_dram_udqs : INOUT std_logic;
mcbx_dram_udqs_n : INOUT std_logic;
mcbx_dram_udm : out std_logic;
mcbx_dram_ldm : out std_logic;
mcbx_dram_odt : out std_logic;
mcbx_dram_ddr3_rst : out std_logic;
calib_recal : in std_logic;
rzq : INOUT std_logic;
zio : INOUT std_logic;
ui_read : in std_logic;
ui_add : in std_logic;
ui_cs : in std_logic;
ui_clk : in std_logic;
ui_sdi : in std_logic;
ui_addr : in std_logic_vector(4 downto 0);
ui_broadcast : in std_logic;
ui_drp_update : in std_logic;
ui_done_cal : in std_logic;
ui_cmd : in std_logic;
ui_cmd_in : in std_logic;
ui_cmd_en : in std_logic;
ui_dqcount : in std_logic_vector(3 downto 0);
ui_dq_lower_dec : in std_logic;
ui_dq_lower_inc : in std_logic;
ui_dq_upper_dec : in std_logic;
ui_dq_upper_inc : in std_logic;
ui_udqs_inc : in std_logic;
ui_udqs_dec : in std_logic;
ui_ldqs_inc : in std_logic;
ui_ldqs_dec : in std_logic;
uo_data : out std_logic_vector(7 downto 0);
uo_data_valid : out std_logic;
uo_done_cal : out std_logic;
uo_cmd_ready_in : out std_logic;
uo_refrsh_flag : out std_logic;
uo_cal_start : out std_logic;
uo_sdo : out std_logic;
status : out std_logic_vector(31 downto 0);
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end mcb_raw_wrapper;
architecture aarch of mcb_raw_wrapper is
component mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR3" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end component;
constant C_OSERDES2_DATA_RATE_OQ : STRING := "SDR";
constant C_OSERDES2_DATA_RATE_OT : STRING := "SDR";
constant C_OSERDES2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_OSERDES2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_OSERDES2_OUTPUT_MODE_SE : STRING := "SINGLE_ENDED";
constant C_OSERDES2_OUTPUT_MODE_DIFF : STRING := "DIFFERENTIAL";
constant C_BUFPLL_0_LOCK_SRC : STRING := "LOCK_TO_0";
constant C_DQ_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQ_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQ_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
constant C_DQS_IODRP2_DATA_RATE : STRING := "SDR";
constant C_DQS_IODRP2_SERDES_MODE_MASTER : STRING := "MASTER";
constant C_DQS_IODRP2_SERDES_MODE_SLAVE : STRING := "SLAVE";
-- MIG always set the below ADD_LATENCY to zero
constant C_MEM_DDR3_ADD_LATENCY : STRING := "OFF";
constant C_MEM_DDR2_ADD_LATENCY : INTEGER := 0;
constant C_MEM_MOBILE_TC_SR : INTEGER := 0;
-- convert the memory timing to memory clock units. I
constant MEM_RAS_VAL : INTEGER := ((C_MEM_TRAS + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RCD_VAL : INTEGER := ((C_MEM_TRCD + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_REFI_VAL : INTEGER := ((C_MEM_TREFI + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RFC_VAL : INTEGER := ((C_MEM_TRFC + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_RP_VAL : INTEGER := ((C_MEM_TRP + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
constant MEM_WR_VAL : INTEGER := ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
function cdiv return integer is
begin
if ( (C_MEM_TRTP mod C_MEMCLK_PERIOD)>0) then
return (C_MEM_TRTP/C_MEMCLK_PERIOD)+1;
else
return (C_MEM_TRTP/C_MEMCLK_PERIOD);
end if;
end function cdiv;
constant MEM_RTP_VAL1 : INTEGER := cdiv;
function MEM_RTP_CYC1 return integer is
begin
if (MEM_RTP_VAL1 < 4 and C_MEM_TYPE = "DDR3") then
return 4;
else if(MEM_RTP_VAL1 < 2) then
return 2;
else
return MEM_RTP_VAL1;
end if;
end if;
end function MEM_RTP_CYC1;
constant MEM_RTP_VAL : INTEGER := MEM_RTP_CYC1;
function MEM_WTR_CYC return integer is
begin
if (C_MEM_TYPE = "DDR") then
return 2;
elsif (C_MEM_TYPE = "DDR3") then
return 4;
elsif (C_MEM_TYPE = "MDDR" OR C_MEM_TYPE = "LPDDR") then
return C_MEM_TWTR;
elsif (C_MEM_TYPE = "DDR2" AND (((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) then
return ((C_MEM_TWTR + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);
elsif (C_MEM_TYPE = "DDR2")then
return 2;
else
return 3;
end if;
end function MEM_WTR_CYC;
constant MEM_WTR_VAL : INTEGER := MEM_WTR_CYC;
function DDR2_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR2")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR2_WRT_RECOVERY_CYC;
constant C_MEM_DDR2_WRT_RECOVERY : INTEGER := DDR2_WRT_RECOVERY_CYC;
function DDR3_WRT_RECOVERY_CYC return integer is
begin
if (not(C_MEM_TYPE = "DDR3")) then
return 5;
else
return ((C_MEM_TWR + C_MEMCLK_PERIOD - 1) / C_MEMCLK_PERIOD);
end if;
end function DDR3_WRT_RECOVERY_CYC;
constant C_MEM_DDR3_WRT_RECOVERY : INTEGER := DDR3_WRT_RECOVERY_CYC;
----------------------------------------------------------------------------
-- signla Declarations
----------------------------------------------------------------------------
signal addr_in0 : std_logic_vector(31 downto 0);
signal allzero : std_logic_vector(127 downto 0) := (others => '0');
signal dqs_out_p : std_logic;
signal dqs_out_n : std_logic;
signal dqs_sys_p : std_logic; --from dqs_gen to IOclk network
signal dqs_sys_n : std_logic; --from dqs_gen to IOclk network
signal udqs_sys_p: std_logic;
signal udqs_sys_n: std_logic;
signal dqs_p : std_logic; -- open net now ?
signal dqs_n : std_logic; -- open net now ?
-- IOI and IOB enable/tristate interface
signal dqIO_w_en_0 : std_logic; --enable DQ pads
signal dqsIO_w_en_90_p : std_logic; --enable p side of DQS
signal dqsIO_w_en_90_n : std_logic; --enable n side of DQS
--memory chip control interface
signal address_90 : std_logic_vector(14 downto 0);
signal ba_90 : std_logic_vector(2 downto 0);
signal ras_90 : std_logic;
signal cas_90 : std_logic;
signal we_90 : std_logic;
signal cke_90 : std_logic;
signal odt_90 : std_logic;
signal rst_90 : std_logic;
-- calibration IDELAY control signals
signal ioi_drp_clk : std_logic; --DRP interface - synchronous clock output
signal ioi_drp_addr : std_logic_vector(4 downto 0); --DRP interface - IOI selection
signal ioi_drp_sdo : std_logic; --DRP interface - serial output for commmands
signal ioi_drp_sdi : std_logic; --DRP interface - serial input for commands
signal ioi_drp_cs : std_logic; --DRP interface - chip select doubles as DONE signal
signal ioi_drp_add : std_logic; --DRP interface - serial address signal
signal ioi_drp_broadcast : std_logic;
signal ioi_drp_train : std_logic;
-- Calibration datacapture siganls
signal dqdonecount : std_logic_vector(3 downto 0); --select signal for the datacapture 16 to 1 mux
signal dq_in_p : std_logic; --positive signal sent to calibration logic
signal dq_in_n : std_logic; --negative signal sent to calibration logic
signal cal_done: std_logic;
--DQS calibration interface
signal udqs_n : std_logic;
signal udqs_p : std_logic;
signal udqs_dqocal_p : std_logic;
signal udqs_dqocal_n : std_logic;
-- MUI enable interface
signal df_en_n90 : std_logic;
--INTERNAL signal FOR DRP chain
-- IOI <-> MUI
signal ioi_int_tmp : std_logic;
signal dqo_n : std_logic_vector(15 downto 0);
signal dqo_p : std_logic_vector(15 downto 0);
signal dqnlm : std_logic;
signal dqplm : std_logic;
signal dqnum : std_logic;
signal dqpum : std_logic;
-- IOI <-> IOB routes
signal ioi_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal ioi_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal ioi_cas : std_logic;
signal ioi_ck : std_logic;
signal ioi_ckn : std_logic;
signal ioi_cke : std_logic;
signal ioi_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal ioi_dqs : std_logic;
signal ioi_dqsn : std_logic;
signal ioi_udqs : std_logic;
signal ioi_udqsn : std_logic;
signal ioi_odt : std_logic;
signal ioi_ras : std_logic;
signal ioi_rst : std_logic;
signal ioi_we : std_logic;
signal ioi_udm : std_logic;
signal ioi_ldm : std_logic;
signal in_dq : std_logic_vector(15 downto 0);
signal in_pre_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal in_dqs : std_logic;
signal in_pre_dqsp : std_logic;
signal in_pre_dqsn : std_logic;
signal in_pre_udqsp : std_logic;
signal in_pre_udqsn : std_logic;
signal in_udqs : std_logic;
-- Memory tri-state control signals
signal t_addr : std_logic_vector(C_MEM_ADDR_WIDTH-1 downto 0);
signal t_ba : std_logic_vector(C_MEM_BANKADDR_WIDTH-1 downto 0);
signal t_cas : std_logic;
signal t_ck : std_logic;
signal t_ckn : std_logic;
signal t_cke : std_logic;
signal t_dq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal t_dqs : std_logic;
signal t_dqsn : std_logic;
signal t_udqs : std_logic;
signal t_udqsn : std_logic;
signal t_odt : std_logic;
signal t_ras : std_logic;
signal t_rst : std_logic;
signal t_we : std_logic;
signal t_udm : std_logic;
signal t_ldm : std_logic;
signal idelay_dqs_ioi_s : std_logic;
signal idelay_dqs_ioi_m : std_logic;
signal idelay_udqs_ioi_s : std_logic;
signal idelay_udqs_ioi_m : std_logic;
signal dqs_pin : std_logic;
signal udqs_pin : std_logic;
-- USER Interface signals
-- translated memory addresses
signal p0_cmd_ra : std_logic_vector(14 downto 0);
signal p0_cmd_ba : std_logic_vector(2 downto 0);
signal p0_cmd_ca : std_logic_vector(11 downto 0);
signal p1_cmd_ra : std_logic_vector(14 downto 0);
signal p1_cmd_ba : std_logic_vector(2 downto 0);
signal p1_cmd_ca : std_logic_vector(11 downto 0);
signal p2_cmd_ra : std_logic_vector(14 downto 0);
signal p2_cmd_ba : std_logic_vector(2 downto 0);
signal p2_cmd_ca : std_logic_vector(11 downto 0);
signal p3_cmd_ra : std_logic_vector(14 downto 0);
signal p3_cmd_ba : std_logic_vector(2 downto 0);
signal p3_cmd_ca : std_logic_vector(11 downto 0);
signal p4_cmd_ra : std_logic_vector(14 downto 0);
signal p4_cmd_ba : std_logic_vector(2 downto 0);
signal p4_cmd_ca : std_logic_vector(11 downto 0);
signal p5_cmd_ra : std_logic_vector(14 downto 0);
signal p5_cmd_ba : std_logic_vector(2 downto 0);
signal p5_cmd_ca : std_logic_vector(11 downto 0);
-- user command wires mapped from logical ports to physical ports
signal mig_p0_arb_en : std_logic;
signal mig_p0_cmd_clk : std_logic;
signal mig_p0_cmd_en : std_logic;
signal mig_p0_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p0_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p0_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p0_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p0_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p0_cmd_empty : std_logic;
signal mig_p0_cmd_full : std_logic;
signal mig_p1_arb_en : std_logic;
signal mig_p1_cmd_clk : std_logic;
signal mig_p1_cmd_en : std_logic;
signal mig_p1_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p1_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p1_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p1_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p1_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p1_cmd_empty : std_logic;
signal mig_p1_cmd_full : std_logic;
signal mig_p2_arb_en : std_logic;
signal mig_p2_cmd_clk : std_logic;
signal mig_p2_cmd_en : std_logic;
signal mig_p2_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p2_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p2_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p2_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p2_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p2_cmd_empty : std_logic;
signal mig_p2_cmd_full : std_logic;
signal mig_p3_arb_en : std_logic;
signal mig_p3_cmd_clk : std_logic;
signal mig_p3_cmd_en : std_logic;
signal mig_p3_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p3_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p3_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p3_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p3_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p3_cmd_empty : std_logic;
signal mig_p3_cmd_full : std_logic;
signal mig_p4_arb_en : std_logic;
signal mig_p4_cmd_clk : std_logic;
signal mig_p4_cmd_en : std_logic;
signal mig_p4_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p4_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p4_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p4_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p4_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p4_cmd_empty : std_logic;
signal mig_p4_cmd_full : std_logic;
signal mig_p5_arb_en : std_logic;
signal mig_p5_cmd_clk : std_logic;
signal mig_p5_cmd_en : std_logic;
signal mig_p5_cmd_ra : std_logic_vector(14 downto 0);
signal mig_p5_cmd_ba : std_logic_vector(2 downto 0);
signal mig_p5_cmd_ca : std_logic_vector(11 downto 0);
signal mig_p5_cmd_instr : std_logic_vector(2 downto 0);
signal mig_p5_cmd_bl : std_logic_vector(5 downto 0);
signal mig_p5_cmd_empty : std_logic;
signal mig_p5_cmd_full : std_logic;
signal mig_p0_wr_clk : std_logic;
signal mig_p0_rd_clk : std_logic;
signal mig_p1_wr_clk : std_logic;
signal mig_p1_rd_clk : std_logic;
signal mig_p2_clk : std_logic;
signal mig_p3_clk : std_logic;
signal mig_p4_clk : std_logic;
signal mig_p5_clk : std_logic;
signal mig_p0_wr_en : std_logic;
signal mig_p0_rd_en : std_logic;
signal mig_p1_wr_en : std_logic;
signal mig_p1_rd_en : std_logic;
signal mig_p2_en : std_logic;
signal mig_p3_en : std_logic;
signal mig_p4_en : std_logic;
signal mig_p5_en : std_logic;
signal mig_p0_wr_data : std_logic_vector(31 downto 0);
signal mig_p1_wr_data : std_logic_vector(31 downto 0);
signal mig_p2_wr_data : std_logic_vector(31 downto 0);
signal mig_p3_wr_data : std_logic_vector(31 downto 0);
signal mig_p4_wr_data : std_logic_vector(31 downto 0);
signal mig_p5_wr_data : std_logic_vector(31 downto 0);
signal mig_p0_wr_mask : std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
signal mig_p1_wr_mask : std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
signal mig_p2_wr_mask : std_logic_vector(3 downto 0);
signal mig_p3_wr_mask : std_logic_vector(3 downto 0);
signal mig_p4_wr_mask : std_logic_vector(3 downto 0);
signal mig_p5_wr_mask : std_logic_vector(3 downto 0);
signal mig_p0_rd_data : std_logic_vector(31 downto 0);
signal mig_p1_rd_data : std_logic_vector(31 downto 0);
signal mig_p2_rd_data : std_logic_vector(31 downto 0);
signal mig_p3_rd_data : std_logic_vector(31 downto 0);
signal mig_p4_rd_data : std_logic_vector(31 downto 0);
signal mig_p5_rd_data : std_logic_vector(31 downto 0);
signal mig_p0_rd_overflow : std_logic;
signal mig_p1_rd_overflow : std_logic;
signal mig_p2_overflow : std_logic;
signal mig_p3_overflow : std_logic;
signal mig_p4_overflow : std_logic;
signal mig_p5_overflow : std_logic;
signal mig_p0_wr_underrun : std_logic;
signal mig_p1_wr_underrun : std_logic;
signal mig_p2_underrun : std_logic;
signal mig_p3_underrun : std_logic;
signal mig_p4_underrun : std_logic;
signal mig_p5_underrun : std_logic;
signal mig_p0_rd_error : std_logic;
signal mig_p0_wr_error : std_logic;
signal mig_p1_rd_error : std_logic;
signal mig_p1_wr_error : std_logic;
signal mig_p2_error : std_logic;
signal mig_p3_error : std_logic;
signal mig_p4_error : std_logic;
signal mig_p5_error : std_logic;
signal mig_p0_wr_count : std_logic_vector(6 downto 0);
signal mig_p1_wr_count : std_logic_vector(6 downto 0);
signal mig_p0_rd_count : std_logic_vector(6 downto 0);
signal mig_p1_rd_count : std_logic_vector(6 downto 0);
signal mig_p2_count : std_logic_vector(6 downto 0);
signal mig_p3_count : std_logic_vector(6 downto 0);
signal mig_p4_count : std_logic_vector(6 downto 0);
signal mig_p5_count : std_logic_vector(6 downto 0);
signal mig_p0_wr_full : std_logic;
signal mig_p1_wr_full : std_logic;
signal mig_p0_rd_empty : std_logic;
signal mig_p1_rd_empty : std_logic;
signal mig_p0_wr_empty : std_logic;
signal mig_p1_wr_empty : std_logic;
signal mig_p0_rd_full : std_logic;
signal mig_p1_rd_full : std_logic;
signal mig_p2_full : std_logic;
signal mig_p3_full : std_logic;
signal mig_p4_full : std_logic;
signal mig_p5_full : std_logic;
signal mig_p2_empty : std_logic;
signal mig_p3_empty : std_logic;
signal mig_p4_empty : std_logic;
signal mig_p5_empty : std_logic;
-- SELFREESH control signal for suspend feature
signal selfrefresh_mcb_enter : std_logic;
signal selfrefresh_mcb_mode : std_logic;
signal MCB_SYSRST : std_logic;
signal ioclk0 : std_logic;
signal ioclk90 : std_logic;
signal hard_done_cal : std_logic;
signal uo_data_int : std_logic_vector(7 downto 0);
signal uo_data_valid_int : std_logic;
signal uo_cmd_ready_in_int : std_logic;
signal syn_uiclk_pll_lock : std_logic;
signal int_sys_rst : std_logic;
--testing
signal ioi_drp_update : std_logic;
signal aux_sdi_sdo : std_logic_vector(7 downto 0);
signal mcb_recal : std_logic;
signal mcb_ui_read : std_logic;
signal mcb_ui_add : std_logic;
signal mcb_ui_cs : std_logic;
signal mcb_ui_clk : std_logic;
signal mcb_ui_sdi : std_logic;
signal mcb_ui_addr : STD_LOGIC_vector(4 downto 0);
signal mcb_ui_broadcast : std_logic;
signal mcb_ui_drp_update : std_logic;
signal mcb_ui_done_cal : std_logic;
signal mcb_ui_cmd : std_logic;
signal mcb_ui_cmd_in : std_logic;
signal mcb_ui_cmd_en : std_logic;
signal mcb_ui_dqcount : std_logic_vector(3 downto 0);
signal mcb_ui_dq_lower_dec : std_logic;
signal mcb_ui_dq_lower_inc : std_logic;
signal mcb_ui_dq_upper_dec : std_logic;
signal mcb_ui_dq_upper_inc : std_logic;
signal mcb_ui_udqs_inc : std_logic;
signal mcb_ui_udqs_dec : std_logic;
signal mcb_ui_ldqs_inc : std_logic;
signal mcb_ui_ldqs_dec : std_logic;
signal DONE_SOFTANDHARD_CAL : std_logic;
signal ck_shiftout0_1 : std_logic;
signal ck_shiftout0_2 : std_logic;
signal ck_shiftout1_3 : std_logic;
signal ck_shiftout1_4 : std_logic;
signal udm_oq : std_logic;
signal udm_t : std_logic;
signal ldm_oq : std_logic;
signal ldm_t : std_logic;
signal dqsp_oq : std_logic;
signal dqsp_tq : std_logic;
signal dqs_shiftout0_1 : std_logic;
signal dqs_shiftout0_2 : std_logic;
signal dqs_shiftout1_3 : std_logic;
signal dqs_shiftout1_4 : std_logic;
signal dqsn_oq : std_logic;
signal dqsn_tq : std_logic;
signal udqsp_oq : std_logic;
signal udqsp_tq : std_logic;
signal udqs_shiftout0_1 : std_logic;
signal udqs_shiftout0_2 : std_logic;
signal udqs_shiftout1_3 : std_logic;
signal udqs_shiftout1_4 : std_logic;
signal udqsn_oq : std_logic;
signal udqsn_tq : std_logic;
signal aux_sdi_out_dqsp : std_logic;
signal aux_sdi_out_udqsp : std_logic;
signal aux_sdi_out_udqsn : std_logic;
signal aux_sdi_out_0 : std_logic;
signal aux_sdi_out_1 : std_logic;
signal aux_sdi_out_2 : std_logic;
signal aux_sdi_out_3 : std_logic;
signal aux_sdi_out_5 : std_logic;
signal aux_sdi_out_6 : std_logic;
signal aux_sdi_out_7 : std_logic;
signal aux_sdi_out_9 : std_logic;
signal aux_sdi_out_10 : std_logic;
signal aux_sdi_out_11 : std_logic;
signal aux_sdi_out_12 : std_logic;
signal aux_sdi_out_13 : std_logic;
signal aux_sdi_out_14 : std_logic;
signal aux_sdi_out_15 : std_logic;
signal aux_sdi_out_8 : std_logic;
signal aux_sdi_out_dqsn : std_logic;
signal aux_sdi_out_4 : std_logic;
signal aux_sdi_out_udm : std_logic;
signal aux_sdi_out_ldm : std_logic;
signal uo_cal_start_int : std_logic;
signal cke_train : std_logic;
signal dq_oq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal dq_tq : std_logic_vector(C_NUM_DQ_PINS-1 downto 0);
signal p0_wr_full_i : std_logic;
signal p0_rd_empty_i : std_logic;
signal p1_wr_full_i : std_logic;
signal p1_rd_empty_i : std_logic;
signal pllclk1 : std_logic_vector(1 downto 0);
signal pllce1 : std_logic_vector(1 downto 0);
signal uo_refrsh_flag_xhdl23 : std_logic;
SIGNAL uo_sdo_xhdl24 : STD_LOGIC;
signal Max_Value_Cal_Error : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute max_fanout of int_sys_rst : signal is "1";
attribute syn_maxfan of int_sys_rst : signal is 1;
begin
uo_cmd_ready_in <= uo_cmd_ready_in_int;
uo_data_valid <= uo_data_valid_int;
uo_data <= uo_data_int;
uo_refrsh_flag <= uo_refrsh_flag_xhdl23;
uo_sdo <= uo_sdo_xhdl24;
p0_wr_full <= p0_wr_full_i;
p0_rd_empty <= p0_rd_empty_i;
p1_wr_full <= p1_wr_full_i;
p1_rd_empty <= p1_rd_empty_i;
ioclk0 <= sysclk_2x;
ioclk90 <= sysclk_2x_180;
pllclk1 <= (ioclk90 & ioclk0);
pllce1 <= (pll_ce_90 & pll_ce_0);
-- Added 2/22 - Add flop to pll_lock status signal to improve timing
process (ui_clk)
begin
if (ui_clk'event and ui_clk = '1') then
syn_uiclk_pll_lock <= pll_lock;
end if;
end process;
int_sys_rst <= sys_rst or not(syn_uiclk_pll_lock);
--Address Remapping
-- Byte Address remapping
--
-- Bank Address[x:0] & Row Address[x:0] & Column Address[x:0]
-- column address remap for port 0
x16_addr : if(C_NUM_DQ_PINS = 16) generate -- port bus remapping sections for CONFIG 2 15,3,12
x16_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate -- C_MEM_ADDR_ORDER = 0 : Bank Row Column
-- port 0 address remapping
x16_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr( C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr (C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS + 1) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1 ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate --Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS downto + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate; --x16_addr_rbc
x16_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x16_rbc_n_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p0_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p0_cmd_ca <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p0_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p0_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1)& p0_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 1 address remapping
x16_rbc_n_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p1_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p1_cmd_ca <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p1_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p1_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS+1) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 2 address remapping
x16_rbc_n_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p2_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p2_cmd_ca <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p2_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p2_cmd_ca <= (allzero( 12 downto C_MEM_NUM_COL_BITS +1)& p2_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 3 address remapping
x16_rbc_n_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p3_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p3_cmd_ca <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p3_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p3_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1)& p3_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 4 address remapping
x16_rbc_n_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p4_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p4_cmd_ca <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p4_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p4_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
-- port 5 address remapping
x16_rbc_n_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_a15 : if (C_MEM_ADDR_WIDTH = 15 ) generate --row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1);
end generate;
x16_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15 )) generate --row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS downto C_MEM_NUM_COL_BITS + 1));
end generate;
x16_rbc_n_p5_c12 : if (C_MEM_NUM_COL_BITS = 12 ) generate --column
p5_cmd_ca <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1);
end generate;
x16_rbc_n_p5_c12_n : if (not(C_MEM_NUM_COL_BITS = 12 )) generate --column
p5_cmd_ca <= (allzero(12 downto C_MEM_NUM_COL_BITS +1) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS downto 1));
end generate;
end generate;--x16_addr_rbc_n
end generate; --x16_addr
x8_addr : if(C_NUM_DQ_PINS = 8) generate
x8_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x8_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 2 address remapping
x8_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,2,10 ***
end generate;
x8_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ); --14,3,10
end generate;
x8_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS )); --14,3,10
end generate;
x8_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc
x8_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x8_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca(11 downto 0) <= p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 1 address remapping
x8_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca(11 downto 0) <= p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
--port 2 address remapping
x8_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca(11 downto 0) <= p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 3 address remapping
x8_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca(11 downto 0) <= p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 4 address remapping
x8_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH) &
p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca(11 downto 0) <= p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
-- port 5 address remapping
x8_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH)&
p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS );
end generate;
x8_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1 downto C_MEM_NUM_COL_BITS ));
end generate;
x8_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca(11 downto 0) <= p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0);
end generate;
x8_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca(11 downto 0) <= (allzero(11 downto C_MEM_NUM_COL_BITS) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 1 downto 0));
end generate;
end generate; --x8_addr_rbc_n
end generate; --x8_addr
x4_addr : if(C_NUM_DQ_PINS = 4) generate
x4_addr_rbc : if (C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN") generate
-- port 0 address remapping
x4_p0_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p0_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_p1_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p1_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_p2_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p2_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_p3_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p3_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5:if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_p4_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p4_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_p5_a15 : if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ba3 : if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_p5_ba3_n : if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0'); --14,3,11
end generate;
x4_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5
end generate; --x4_addr_rbc
x4_addr_rbc_n : if (not(C_MEM_ADDR_ORDER = "ROW_BANK_COLUMN")) generate
-- port 0 address remapping
x4_rbc_n_p0_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p0_cmd_ba <= p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p0_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p0_cmd_ra <= p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p0_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p0_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p0_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p0_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p0_cmd_ca <= (p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p0_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p0_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p0_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 1 address remapping
x4_rbc_n_p1_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p1_cmd_ba <= p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p1_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p1_cmd_ra <= p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p1_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p1_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p1_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p1_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p1_cmd_ca <= (p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p1_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p1_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p1_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 2 address remapping
x4_rbc_n_p2_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p2_cmd_ba <= p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p2_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p2_cmd_ra <= p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p2_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p2_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p2_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p2_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p2_cmd_ca <= (p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p2_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p2_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p2_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 3 address remapping
x4_rbc_n_p3_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p3_cmd_ba <= p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p3_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p3_cmd_ra <= p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p3_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p3_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p3_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p3_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p3_cmd_ca <= (p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p3_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p3_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p3_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_p4_p5_n: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
-- port 4 address remapping
x4_rbc_n_p4_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p4_cmd_ba <= p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p4_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p4_cmd_ra <= p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p4_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p4_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p4_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p4_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p4_cmd_ca <= (p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p4_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p4_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p4_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
-- port 5 address remapping
x4_rbc_n_p5_ba3 :if (C_MEM_BANKADDR_WIDTH = 3 ) generate --Bank
p5_cmd_ba <= p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_ba3_n :if (not(C_MEM_BANKADDR_WIDTH = 3 )) generate --Bank
p5_cmd_ba <= (allzero(2 downto C_MEM_BANKADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_BANKADDR_WIDTH + C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_a15: if (C_MEM_ADDR_WIDTH = 15) generate -- Row
p5_cmd_ra <= p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1);
end generate;
x4_rbc_n_p5_a15_n : if (not(C_MEM_ADDR_WIDTH = 15)) generate --Row
p5_cmd_ra <= (allzero(14 downto C_MEM_ADDR_WIDTH ) & p5_cmd_byte_addr(C_MEM_ADDR_WIDTH + C_MEM_NUM_COL_BITS - 2 downto C_MEM_NUM_COL_BITS - 1));
end generate;
x4_rbc_n_p5_ca12 : if (C_MEM_NUM_COL_BITS = 12) generate --Column
p5_cmd_ca <= (p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
x4_rbc_n_p5_ca12_n : if (not(C_MEM_NUM_COL_BITS = 12)) generate --Column
p5_cmd_ca <= (allzero(11 downto C_MEM_NUM_COL_BITS ) & p5_cmd_byte_addr(C_MEM_NUM_COL_BITS - 2 downto 0) & '0');
end generate;
end generate; --x4_p4_p5_n
end generate; --x4_addr_rbc_n
end generate; --x4_addr
-- if(C_PORT_CONFIG[183:160] == "B32") begin : u_config1_0
u_config1_0: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
--synthesis translate_off
-- PORT2
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 2";
end if;
end process;
process (p2_cmd_en,p2_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32") and
p2_cmd_en = '1' and p2_cmd_instr(2) = '0' and p2_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 2";
end if;
end process;
-- PORT3
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 3";
end if;
end process;
process (p3_cmd_en,p3_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") and
p3_cmd_en = '1' and p3_cmd_instr(2) = '0' and p3_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 3";
end if;
end process;
-- PORT4
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 4";
end if;
end process;
process (p4_cmd_en,p4_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") and
p4_cmd_en = '1' and p4_cmd_instr(2) = '0' and p4_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 4";
end if;
end process;
-- PORT5
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '1') then
report "ERROR - Invalid Command for write only port 5";
end if;
end process;
process (p5_cmd_en,p5_cmd_instr)
begin
if((C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") and
p5_cmd_en = '1' and p5_cmd_instr(2) = '0' and p5_cmd_instr(0) = '0') then
report "ERROR - Invalid Command for read only port 5";
end if;
end process;
--synthesis translate_on
-- the local declaration of input port signals doesn't work. The mig_p1_xxx through mig_p5_xxx always ends up
-- high Z even though there are signals on p1_cmd_xxx through p5_cmd_xxxx.
-- The only solutions that I have is to have MIG tool remove the entire internal codes that doesn't belongs to the Configuration..
--
-- Inputs from Application CMD Port
p0_cmd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty;
p0_cmd_full <= mig_p0_cmd_full ;
end generate;
p0_cmd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
end generate;
p1_cmd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p1_cmd_empty;
p1_cmd_full <= mig_p1_cmd_full ;
end generate;
p1_cmd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
end generate;
p2_cmd_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p2_cmd_empty;
p2_cmd_full <= mig_p2_cmd_full ;
end generate;
p2_cmd_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
end generate;
p3_cmd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_arb_en <= p3_arb_en ;
mig_p3_cmd_clk <= p3_cmd_clk ;
mig_p3_cmd_en <= p3_cmd_en ;
mig_p3_cmd_ra <= p3_cmd_ra ;
mig_p3_cmd_ba <= p3_cmd_ba ;
mig_p3_cmd_ca <= p3_cmd_ca ;
mig_p3_cmd_instr <= p3_cmd_instr;
mig_p3_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
p3_cmd_empty <= mig_p3_cmd_empty;
p3_cmd_full <= mig_p3_cmd_full ;
end generate;
p3_cmd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
p3_cmd_empty <= '0';
p3_cmd_full <= '0';
end generate;
p4_cmd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_arb_en <= p4_arb_en ;
mig_p4_cmd_clk <= p4_cmd_clk ;
mig_p4_cmd_en <= p4_cmd_en ;
mig_p4_cmd_ra <= p4_cmd_ra ;
mig_p4_cmd_ba <= p4_cmd_ba ;
mig_p4_cmd_ca <= p4_cmd_ca ;
mig_p4_cmd_instr <= p4_cmd_instr;
mig_p4_cmd_bl <= ((p4_cmd_instr(2) or p4_cmd_bl(5)) & p4_cmd_bl(4 downto 0)) ;
p4_cmd_empty <= mig_p4_cmd_empty;
p4_cmd_full <= mig_p4_cmd_full ;
end generate;
p4_cmd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
end generate;
p5_cmd_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_arb_en <= p5_arb_en ;
mig_p5_cmd_clk <= p5_cmd_clk ;
mig_p5_cmd_en <= p5_cmd_en ;
mig_p5_cmd_ra <= p5_cmd_ra ;
mig_p5_cmd_ba <= p5_cmd_ba ;
mig_p5_cmd_ca <= p5_cmd_ca ;
mig_p5_cmd_instr <= p5_cmd_instr;
mig_p5_cmd_bl <= ((p5_cmd_instr(2) or p5_cmd_bl(5)) & p5_cmd_bl(4 downto 0)) ;
p5_cmd_empty <= mig_p5_cmd_empty;
p5_cmd_full <= mig_p5_cmd_full ;
end generate;
p5_cmd_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
end generate;
p0_wr_rd_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
mig_p0_wr_data <= p0_wr_data(31 downto 0);
p0_rd_data <= mig_p0_rd_data;
p0_rd_full <= mig_p0_rd_full;
p0_rd_empty_i <= mig_p0_rd_empty;
p0_rd_error <= mig_p0_rd_error;
p0_wr_error <= mig_p0_wr_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p0_wr_full_i <= mig_p0_wr_full;
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_wr_rd_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_rd_en <= '0';
mig_p0_wr_mask <= (others => '0');
mig_p0_wr_data <= (others => '0');
p0_rd_data <= (others => '0');
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
p0_rd_error <= '0';
p0_wr_error <= '0';
p0_rd_overflow <= '0';
p0_wr_underrun <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_wr_rd_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_clk <= p1_rd_clk;
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_rd_en <= p1_rd_en;
p1_rd_data <= mig_p1_rd_data;
p1_rd_empty_i <= mig_p1_rd_empty;
p1_rd_full <= mig_p1_rd_full;
p1_rd_error <= mig_p1_rd_error;
p1_wr_error <= mig_p1_wr_error;
p1_rd_overflow <= mig_p1_rd_overflow;
p1_wr_underrun <= mig_p1_wr_underrun;
p1_wr_empty <= mig_p1_wr_empty;
p1_wr_full_i <= mig_p1_wr_full;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count ;
end generate;
p1_wr_rd_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p1_wr_en <= '0';
mig_p1_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_rd_en <= '0';
p1_rd_data <= (others => '0');
p1_rd_empty_i <= '0';
p1_rd_full <= '0';
p1_rd_error <= '0';
p1_wr_error <= '0';
p1_rd_overflow <= '0';
p1_wr_underrun <= '0';
p1_wr_empty <= '0';
p1_wr_full_i <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
end generate;
--whenever PORT 2 is in Write mode
-- xhdl272 : IF (C_PORT_CONFIG(23 downto 21) = "B32" AND C_PORT_CONFIG(15 downto 13) = "W32") GENERATE
--u_config1_2W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "W32") generate
u_config1_2W: if( C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32"
) generate
p2_wr_ena: if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_wr_clk;
mig_p2_wr_data <= p2_wr_data(31 downto 0);
mig_p2_wr_mask <= p2_wr_mask(3 downto 0);
mig_p2_en <= p2_wr_en;-- this signal will not shown up if the port 5 is for read dir
p2_wr_error <= mig_p2_error;
p2_wr_full <= mig_p2_full;
p2_wr_empty <= mig_p2_empty;
p2_wr_underrun <= mig_p2_underrun;
p2_wr_count <= mig_p2_count ;-- wr port
end generate;
p2_wr_dis: if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
mig_p2_en <= '0';
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
p2_rd_data <= (others => '0');
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
-- p2_rd_error <= '0';
end generate;
--u_config1_2R: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(119 downto 96) = "R32") generate
u_config1_2R: if(C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" ) generate
p2_rd_ena : if (C_PORT_ENABLE(2) = '1') generate
mig_p2_clk <= p2_rd_clk;
p2_rd_data <= mig_p2_rd_data;
mig_p2_en <= p2_rd_en;
p2_rd_overflow <= mig_p2_overflow;
p2_rd_error <= mig_p2_error;
p2_rd_full <= mig_p2_full;
p2_rd_empty <= mig_p2_empty;
p2_rd_count <= mig_p2_count ;-- wr port
end generate;
p2_rd_dis : if (C_PORT_ENABLE(2) = '0') generate
mig_p2_clk <= '0';
p2_rd_data <= (others => '0');
mig_p2_en <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
p2_rd_count <= (others => '0');
end generate;
mig_p2_wr_data <= (others => '0');
mig_p2_wr_mask <= (others => '0');
p2_wr_error <= '0';
p2_wr_full <= '0';
p2_wr_empty <= '0';
p2_wr_underrun <= '0';
p2_wr_count <= (others => '0');
end generate;
--u_config1_3W: if(C_PORT_CONFIG(183 downto 160) = "B32" and C_PORT_CONFIG(87 downto 64) = "W32") generate --whenever PORT 3 is in Write mode
u_config1_3W: if(
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate --whenever PORT 3 is in Write mode
p3_wr_ena: if (C_PORT_ENABLE(3) = '1')generate
mig_p3_clk <= p3_wr_clk;
mig_p3_wr_data <= p3_wr_data(31 downto 0);
mig_p3_wr_mask <= p3_wr_mask(3 downto 0);
mig_p3_en <= p3_wr_en;
p3_wr_full <= mig_p3_full;
p3_wr_empty <= mig_p3_empty;
p3_wr_underrun <= mig_p3_underrun;
p3_wr_count <= mig_p3_count ;-- wr port
p3_wr_error <= mig_p3_error;
end generate;
p3_wr_dis: if (C_PORT_ENABLE(3) = '0')generate
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p3_en <= '0';
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
end generate;
p3_rd_overflow <= '0';
p3_rd_error <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_data <= (others => '0');
end generate;
u_config1_3R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32") generate
p3_rd_ena: if (C_PORT_ENABLE(3) = '1') generate
mig_p3_clk <= p3_rd_clk;
p3_rd_data <= mig_p3_rd_data;
mig_p3_en <= p3_rd_en; -- this signal will not shown up if the port 5 is for write dir
p3_rd_overflow <= mig_p3_overflow;
p3_rd_error <= mig_p3_error;
p3_rd_full <= mig_p3_full;
p3_rd_empty <= mig_p3_empty;
p3_rd_count <= mig_p3_count ;-- wr port
end generate;
p3_rd_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p3_clk <= '0';
mig_p3_en <= '0';
p3_rd_overflow <= '0';
p3_rd_full <= '0';
p3_rd_empty <= '0';
p3_rd_count <= (others => '0');
p3_rd_error <= '0';
p3_rd_data <= (others => '0');
end generate;
p3_wr_full <= '0';
p3_wr_empty <= '0';
p3_wr_underrun <= '0';
p3_wr_count <= (others => '0');
p3_wr_error <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
end generate;
u_config1_4W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 4 is in Write mode
p4_wr_ena : if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_wr_clk;
mig_p4_wr_data <= p4_wr_data(31 downto 0);
mig_p4_wr_mask <= p4_wr_mask(3 downto 0);
mig_p4_en <= p4_wr_en;-- this signal will not shown up if the port 5 is for read dir
p4_wr_full <= mig_p4_full;
p4_wr_empty <= mig_p4_empty;
p4_wr_underrun <= mig_p4_underrun;
p4_wr_count <= mig_p4_count ;-- wr port
p4_wr_error <= mig_p4_error;
end generate;
p4_wr_dis : if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p4_en <= '0';
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
end generate;
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
p4_rd_data <= (others => '0');
end generate;
u_config1_4R : if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32") generate
p4_rd_ena: if (C_PORT_ENABLE(4) = '1') generate
mig_p4_clk <= p4_rd_clk;
p4_rd_data <= mig_p4_rd_data;
mig_p4_en <= p4_rd_en; -- this signal will not shown up if the port 5 is for write dir
p4_rd_overflow <= mig_p4_overflow;
p4_rd_error <= mig_p4_error;
p4_rd_full <= mig_p4_full;
p4_rd_empty <= mig_p4_empty;
p4_rd_count <= mig_p4_count ;-- wr port
end generate;
p4_rd_dis: if (C_PORT_ENABLE(4) = '0') generate
mig_p4_clk <= '0';
p4_rd_data <= (others => '0');
mig_p4_en <= '0';
p4_rd_overflow <= '0';
p4_rd_error <= '0';
p4_rd_full <= '0';
p4_rd_empty <= '0';
p4_rd_count <= (others => '0');
end generate;
p4_wr_full <= '0';
p4_wr_empty <= '0';
p4_wr_underrun <= '0';
p4_wr_count <= (others => '0');
p4_wr_error <= '0';
mig_p4_wr_data <= (others => '0');
mig_p4_wr_mask <= (others => '0');
end generate;
u_config1_5W: if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_W32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_W32") generate
-- whenever PORT 5 is in Write mode
p5_wr_ena: if (C_PORT_ENABLE(5) = '1') generate
mig_p5_clk <= p5_wr_clk;
mig_p5_wr_data <= p5_wr_data(31 downto 0);
mig_p5_wr_mask <= p5_wr_mask(3 downto 0);
mig_p5_en <= p5_wr_en;
p5_wr_full <= mig_p5_full;
p5_wr_empty <= mig_p5_empty;
p5_wr_underrun <= mig_p5_underrun;
p5_wr_count <= mig_p5_count ;
p5_wr_error <= mig_p5_error;
end generate;
p5_wr_dis: if (C_PORT_ENABLE(5) = '0') generate
mig_p5_clk <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p5_en <= '0';
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
end generate;
p5_rd_data <= (others => '0');
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
u_config1_5R :if(
C_PORT_CONFIG = "B32_B32_R32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_R32_W32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_R32_W32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_R32_R32" or
C_PORT_CONFIG = "B32_B32_W32_W32_W32_R32") generate
p5_rd_ena:if (C_PORT_ENABLE(5) = '1')generate
mig_p5_clk <= p5_rd_clk;
p5_rd_data <= mig_p5_rd_data;
mig_p5_en <= p5_rd_en;
p5_rd_overflow <= mig_p5_overflow;
p5_rd_error <= mig_p5_error;
p5_rd_full <= mig_p5_full;
p5_rd_empty <= mig_p5_empty;
p5_rd_count <= mig_p5_count ;
end generate;
p5_rd_dis:if (C_PORT_ENABLE(5) = '0')generate
mig_p5_clk <= '0';
p5_rd_data <= (others => '0');
mig_p5_en <= '0';
p5_rd_overflow <= '0';
p5_rd_error <= '0';
p5_rd_full <= '0';
p5_rd_empty <= '0';
p5_rd_count <= (others => '0');
end generate;
p5_wr_full <= '0';
p5_wr_empty <= '0';
p5_wr_underrun <= '0';
p5_wr_count <= (others => '0');
p5_wr_error <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
end generate;
--//////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
----
---- B32_B32_B32_B32
----
--///////////////////////////////////////////////////////////////////////////
--//////////////////////////////////////////////////////////////////////////
u_config_2 : if(C_PORT_CONFIG = "B32_B32_B32_B32" ) generate
-- Inputs from Application CMD Port
-- ************* need to hook up rd /wr error outputs
p0_c2_ena: if (C_PORT_ENABLE(0) = '1') generate
-- command port signals
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p0_rd_en <= p0_rd_en;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask <= p0_wr_mask(3 downto 0);
p0_wr_count <= mig_p0_wr_count;
p0_rd_count <= mig_p0_rd_count ;
end generate;
p0_c2_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_rd_en <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
end generate;
p1_c2_ena: if (C_PORT_ENABLE(1) = '1') generate
-- command port signals
mig_p1_arb_en <= p1_arb_en ;
mig_p1_cmd_clk <= p1_cmd_clk ;
mig_p1_cmd_en <= p1_cmd_en ;
mig_p1_cmd_ra <= p1_cmd_ra ;
mig_p1_cmd_ba <= p1_cmd_ba ;
mig_p1_cmd_ca <= p1_cmd_ca ;
mig_p1_cmd_instr <= p1_cmd_instr;
mig_p1_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
-- Data port signals
mig_p1_wr_en <= p1_wr_en;
mig_p1_wr_clk <= p1_wr_clk;
mig_p1_rd_en <= p1_rd_en;
mig_p1_wr_data <= p1_wr_data(31 downto 0);
mig_p1_wr_mask <= p1_wr_mask(3 downto 0);
mig_p1_rd_clk <= p1_rd_clk;
p1_wr_count <= mig_p1_wr_count;
p1_rd_count <= mig_p1_rd_count;
end generate;
p1_c2_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
-- Data port signals
mig_p1_wr_en <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_en <= '0';
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
mig_p1_rd_clk <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
end generate;
p2_c2_ena :if (C_PORT_ENABLE(2) = '1') generate
--MCB Physical port Logical Port
mig_p2_arb_en <= p2_arb_en ;
mig_p2_cmd_clk <= p2_cmd_clk ;
mig_p2_cmd_en <= p2_cmd_en ;
mig_p2_cmd_ra <= p2_cmd_ra ;
mig_p2_cmd_ba <= p2_cmd_ba ;
mig_p2_cmd_ca <= p2_cmd_ca ;
mig_p2_cmd_instr <= p2_cmd_instr;
mig_p2_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
mig_p2_en <= p2_rd_en;
mig_p2_clk <= p2_rd_clk;
mig_p3_en <= p2_wr_en;
mig_p3_clk <= p2_wr_clk;
mig_p3_wr_data <= p2_wr_data(31 downto 0);
mig_p3_wr_mask <= p2_wr_mask(3 downto 0);
p2_wr_count <= mig_p3_count;
p2_rd_count <= mig_p2_count;
end generate;
p2_c2_dis :if (C_PORT_ENABLE(2) = '0') generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_en <= '0';
mig_p3_clk <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_count <= (others => '0');
end generate;
p3_c2_ena: if (C_PORT_ENABLE(3) = '1') generate
--MCB Physical port Logical Port
mig_p4_arb_en <= p3_arb_en ;
mig_p4_cmd_clk <= p3_cmd_clk ;
mig_p4_cmd_en <= p3_cmd_en ;
mig_p4_cmd_ra <= p3_cmd_ra ;
mig_p4_cmd_ba <= p3_cmd_ba ;
mig_p4_cmd_ca <= p3_cmd_ca ;
mig_p4_cmd_instr <= p3_cmd_instr;
mig_p4_cmd_bl <= ((p3_cmd_instr(2) or p3_cmd_bl(5)) & p3_cmd_bl(4 downto 0)) ;
mig_p4_clk <= p3_rd_clk;
mig_p4_en <= p3_rd_en;
mig_p5_clk <= p3_wr_clk;
mig_p5_en <= p3_wr_en;
mig_p5_wr_data <= p3_wr_data(31 downto 0);
mig_p5_wr_mask <= p3_wr_mask(3 downto 0);
p3_rd_count <= mig_p4_count;
p3_wr_count <= mig_p5_count;
end generate;
p3_c2_dis: if (C_PORT_ENABLE(3) = '0') generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p4_clk <= '0';
mig_p4_en <= '0';
mig_p5_clk <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
p3_rd_count <= (others => '0');
p3_wr_count <= (others => '0');
end generate;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p1_cmd_empty <= mig_p1_cmd_empty ;
p1_cmd_full <= mig_p1_cmd_full ;
p2_cmd_empty <= mig_p2_cmd_empty ;
p2_cmd_full <= mig_p2_cmd_full ;
p3_cmd_empty <= mig_p4_cmd_empty ;
p3_cmd_full <= mig_p4_cmd_full ;
-- outputs to Applications User Port
p0_rd_data <= mig_p0_rd_data;
p1_rd_data <= mig_p1_rd_data;
p2_rd_data <= mig_p2_rd_data;
p3_rd_data <= mig_p4_rd_data;
p0_rd_empty_i <= mig_p0_rd_empty;
p1_rd_empty_i <= mig_p1_rd_empty;
p2_rd_empty <= mig_p2_empty;
p3_rd_empty <= mig_p4_empty;
p0_rd_full <= mig_p0_rd_full;
p1_rd_full <= mig_p1_rd_full;
p2_rd_full <= mig_p2_full;
p3_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error;
p1_rd_error <= mig_p1_rd_error;
p2_rd_error <= mig_p2_error;
p3_rd_error <= mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow;
p1_rd_overflow <= mig_p1_rd_overflow;
p2_rd_overflow <= mig_p2_overflow;
p3_rd_overflow <= mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun;
p1_wr_underrun <= mig_p1_wr_underrun;
p2_wr_underrun <= mig_p3_underrun;
p3_wr_underrun <= mig_p5_underrun;
p0_wr_empty <= mig_p0_wr_empty;
p1_wr_empty <= mig_p1_wr_empty;
p2_wr_empty <= mig_p3_empty;
p3_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p0_wr_full;
p1_wr_full_i <= mig_p1_wr_full;
p2_wr_full <= mig_p3_full;
p3_wr_full <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error;
p1_wr_error <= mig_p1_wr_error;
p2_wr_error <= mig_p3_error;
p3_wr_error <= mig_p5_error;
-- unused ports signals
p4_cmd_empty <= '0';
p4_cmd_full <= '0';
mig_p2_wr_mask <= (others => '0');
mig_p4_wr_mask <= (others => '0');
mig_p2_wr_data <= (others => '0');
mig_p4_wr_data <= (others => '0');
p5_cmd_empty <= '0';
p5_cmd_full <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_arb_en <= '0'; -- physical cmd port 3 is not used in this config
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--
--
-- --//////////////////////////////////////////////////////////////////////////
-- --///////////////////////////////////////////////////////////////////////////
-- ----
-- ---- B64_B32_B32
-- ----
-- --///////////////////////////////////////////////////////////////////////////
-- --//////////////////////////////////////////////////////////////////////////
--
--
--
u_config_3:if(C_PORT_CONFIG = "B64_B32_B32" ) generate
-- Inputs from Application CMD Port
p0_c3_ena : if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
p0_rd_empty_i <= mig_p1_rd_empty;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_wr_count <= mig_p1_wr_count; -- B64 for port 0, map most significant port to output
p0_rd_count <= mig_p1_rd_count;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
end generate;
p0_c3_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
p0_rd_empty_i <= '0';
p0_rd_data <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_empty <= '0';
p0_wr_error <= '0';
p0_wr_full_i <= '0';
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
end generate;
p1_c3_ena: if (C_PORT_ENABLE(1) = '1')generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
p1_cmd_empty <= mig_p2_cmd_empty;
p1_cmd_full <= mig_p2_cmd_full;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en;
p1_rd_data <= mig_p2_rd_data;
p1_wr_count <= mig_p3_count;
p1_rd_count <= mig_p2_count;
p1_wr_empty <= mig_p3_empty;
p1_wr_error <= mig_p3_error;
p1_wr_full_i <= mig_p3_full;
p1_wr_underrun <= mig_p3_underrun;
p1_rd_overflow <= mig_p2_overflow;
p1_rd_error <= mig_p2_error;
p1_rd_full <= mig_p2_full;
p1_rd_empty_i <= mig_p2_empty;
end generate;
p1_c3_dis: if (C_PORT_ENABLE(1) = '0')generate
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
mig_p3_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p2_clk <= '0';
mig_p3_clk <= '0';
p1_rd_data <= (others => '0');
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_empty <= '0';
p1_wr_error <= '0';
p1_wr_full_i <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
end generate;
p2_c3_ena: if (C_PORT_ENABLE(2) = '1')generate
mig_p4_arb_en <= p2_arb_en ;
mig_p4_cmd_clk <= p2_cmd_clk ;
mig_p4_cmd_en <= p2_cmd_en ;
mig_p4_cmd_ra <= p2_cmd_ra ;
mig_p4_cmd_ba <= p2_cmd_ba ;
mig_p4_cmd_ca <= p2_cmd_ca ;
mig_p4_cmd_instr <= p2_cmd_instr;
mig_p4_cmd_bl <= ((p2_cmd_instr(2) or p2_cmd_bl(5)) & p2_cmd_bl(4 downto 0)) ;
p2_cmd_empty <= mig_p4_cmd_empty ;
p2_cmd_full <= mig_p4_cmd_full ;
mig_p5_en <= p2_wr_en;
mig_p5_wr_data <= p2_wr_data(31 downto 0);
mig_p5_wr_mask <= p2_wr_mask(3 downto 0);
mig_p4_en <= p2_rd_en;
mig_p4_clk <= p2_rd_clk;
mig_p5_clk <= p2_wr_clk;
p2_rd_data <= mig_p4_rd_data;
p2_wr_count <= mig_p5_count;
p2_rd_count <= mig_p4_count;
p2_wr_empty <= mig_p5_empty;
p2_wr_full <= mig_p5_full;
p2_wr_error <= mig_p5_error;
p2_wr_underrun <= mig_p5_underrun;
p2_rd_overflow <= mig_p4_overflow;
p2_rd_error <= mig_p4_error;
p2_rd_full <= mig_p4_full;
p2_rd_empty <= mig_p4_empty;
end generate;
p2_c3_dis: if (C_PORT_ENABLE(2) = '0')generate
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
p2_cmd_empty <= '0';
p2_cmd_full <= '0';
mig_p5_en <= '0';
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p4_en <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
p2_rd_data <= (others => '0');
p2_wr_count <= (others => '0');
p2_rd_count <= (others => '0');
p2_wr_empty <= '0';
p2_wr_full <= '0';
p2_wr_error <= '0';
p2_wr_underrun <= '0';
p2_rd_overflow <= '0';
p2_rd_error <= '0';
p2_rd_full <= '0';
p2_rd_empty <= '0';
end generate;
-- MCB's port 1,3,5 is not used in this Config mode
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
u_config_4 : if(C_PORT_CONFIG = "B64_B64" ) generate
-- Inputs from Application CMD Port
p0_c4_ena: if (C_PORT_ENABLE(0) = '1') generate
mig_p0_arb_en <= p0_arb_en ;
mig_p1_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
p0_rd_data <= (mig_p1_rd_data & mig_p0_rd_data);
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
p0_wr_empty <= mig_p1_wr_empty;
p0_wr_full_i <= mig_p1_wr_full;
p0_wr_error <= mig_p1_wr_error or mig_p0_wr_error;
p0_wr_count <= mig_p1_wr_count;
p0_rd_count <= mig_p1_rd_count;
p0_wr_underrun <= mig_p1_wr_underrun or mig_p0_wr_underrun;
p0_rd_overflow <= mig_p1_rd_overflow or mig_p0_rd_overflow;
p0_rd_error <= mig_p1_rd_error or mig_p0_rd_error;
p0_rd_full <= mig_p1_rd_full;
p0_rd_empty_i <= mig_p1_rd_empty;
end generate;
p0_c4_dis: if (C_PORT_ENABLE(0) = '0') generate
mig_p0_arb_en <= '0';
mig_p0_cmd_clk <= '0';
mig_p0_cmd_en <= '0';
mig_p0_cmd_ra <= (others => '0');
mig_p0_cmd_ba <= (others => '0');
mig_p0_cmd_ca <= (others => '0');
mig_p0_cmd_instr <= (others => '0');
mig_p0_cmd_bl <= (others => '0');
mig_p0_wr_clk <= '0';
mig_p0_rd_clk <= '0';
mig_p1_wr_clk <= '0';
mig_p1_rd_clk <= '0';
mig_p0_wr_en <= '0';
mig_p1_wr_en <= '0';
mig_p0_wr_data <= (others => '0');
mig_p0_wr_mask <= (others => '0');
mig_p1_wr_data <= (others => '0');
mig_p1_wr_mask <= (others => '0');
-- mig_p1_wr_en <= (others => '0');
mig_p0_rd_en <= '0';
mig_p1_rd_en <= '0';
p0_rd_data <= (others => '0');
p0_cmd_empty <= '0';
p0_cmd_full <= '0';
p0_wr_empty <= '0';
p0_wr_full_i <= '0';
p0_wr_error <= '0';
p0_wr_count <= (others => '0');
p0_rd_count <= (others => '0');
p0_wr_underrun <= '0';
p0_rd_overflow <= '0';
p0_rd_error <= '0';
p0_rd_full <= '0';
p0_rd_empty_i <= '0';
end generate;
p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate
mig_p2_arb_en <= p1_arb_en ;
mig_p2_cmd_clk <= p1_cmd_clk ;
mig_p2_cmd_en <= p1_cmd_en ;
mig_p2_cmd_ra <= p1_cmd_ra ;
mig_p2_cmd_ba <= p1_cmd_ba ;
mig_p2_cmd_ca <= p1_cmd_ca ;
mig_p2_cmd_instr <= p1_cmd_instr;
mig_p2_cmd_bl <= ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0)) ;
mig_p2_clk <= p1_rd_clk;
mig_p3_clk <= p1_wr_clk;
mig_p4_clk <= p1_rd_clk;
mig_p5_clk <= p1_wr_clk;
mig_p3_en <= p1_wr_en and not p1_wr_full_i;
mig_p5_en <= p1_wr_en and not p1_wr_full_i;
mig_p3_wr_data <= p1_wr_data(31 downto 0);
mig_p3_wr_mask <= p1_wr_mask(3 downto 0);
mig_p5_wr_data <= p1_wr_data(63 downto 32);
mig_p5_wr_mask <= p1_wr_mask(3 downto 0);
mig_p2_en <= p1_rd_en and not p1_rd_empty_i;
mig_p4_en <= p1_rd_en and not p1_rd_empty_i;
p1_cmd_empty <= mig_p2_cmd_empty ;
p1_cmd_full <= mig_p2_cmd_full ;
p1_wr_count <= mig_p5_count;
p1_rd_count <= mig_p4_count;
p1_wr_full_i <= mig_p5_full;
p1_wr_error <= mig_p5_error or mig_p5_error;
p1_wr_empty <= mig_p5_empty;
p1_wr_underrun <= mig_p3_underrun or mig_p5_underrun;
p1_rd_overflow <= mig_p4_overflow;
p1_rd_error <= mig_p4_error;
p1_rd_full <= mig_p4_full;
p1_rd_empty_i <= mig_p4_empty;
p1_rd_data <= (mig_p4_rd_data & mig_p2_rd_data);
end generate;
p1_c4_dis: if (C_PORT_ENABLE(1) = '0') generate
mig_p2_arb_en <= '0';
-- mig_p3_arb_en <= (others => '0');
-- mig_p4_arb_en <= (others => '0');
-- mig_p5_arb_en <= (others => '0');
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p2_clk <= '0';
mig_p3_clk <= '0';
mig_p4_clk <= '0';
mig_p5_clk <= '0';
mig_p3_en <= '0';
mig_p5_en <= '0';
mig_p3_wr_data <= (others => '0');
mig_p3_wr_mask <= (others => '0');
mig_p5_wr_data <= (others => '0');
mig_p5_wr_mask <= (others => '0');
mig_p2_en <= '0';
mig_p4_en <= '0';
p1_cmd_empty <= '0';
p1_cmd_full <= '0';
p1_wr_count <= (others => '0');
p1_rd_count <= (others => '0');
p1_wr_full_i <= '0';
p1_wr_error <= '0';
p1_wr_empty <= '0';
p1_wr_underrun <= '0';
p1_rd_overflow <= '0';
p1_rd_error <= '0';
p1_rd_full <= '0';
p1_rd_empty_i <= '0';
p1_rd_data <= (others => '0');
end generate;
-- unused MCB's signals in this configuration
mig_p3_arb_en <= '0';
mig_p4_arb_en <= '0';
mig_p5_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
end generate;
--*******************************BEGIN OF CONFIG 5 SIGNALS ********************************
u_config_5: if(C_PORT_CONFIG = "B128" ) generate
-- Inputs from Application CMD Port
mig_p0_arb_en <= p0_arb_en ;
mig_p0_cmd_clk <= p0_cmd_clk ;
mig_p0_cmd_en <= p0_cmd_en ;
mig_p0_cmd_ra <= p0_cmd_ra ;
mig_p0_cmd_ba <= p0_cmd_ba ;
mig_p0_cmd_ca <= p0_cmd_ca ;
mig_p0_cmd_instr <= p0_cmd_instr;
mig_p0_cmd_bl <= ((p0_cmd_instr(2) or p0_cmd_bl(5)) & p0_cmd_bl(4 downto 0)) ;
p0_cmd_empty <= mig_p0_cmd_empty ;
p0_cmd_full <= mig_p0_cmd_full ;
-- Inputs from Application User Port
mig_p0_wr_clk <= p0_wr_clk;
mig_p0_rd_clk <= p0_rd_clk;
mig_p1_wr_clk <= p0_wr_clk;
mig_p1_rd_clk <= p0_rd_clk;
mig_p2_clk <= p0_rd_clk;
mig_p3_clk <= p0_wr_clk;
mig_p4_clk <= p0_rd_clk;
mig_p5_clk <= p0_wr_clk;
mig_p0_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p1_wr_en <= p0_wr_en and not p0_wr_full_i;
mig_p3_en <= p0_wr_en and not p0_wr_full_i;
mig_p5_en <= p0_wr_en and not p0_wr_full_i;
mig_p0_wr_data <= p0_wr_data(31 downto 0);
mig_p0_wr_mask(3 downto 0) <= p0_wr_mask(3 downto 0);
mig_p1_wr_data <= p0_wr_data(63 downto 32);
mig_p1_wr_mask(3 downto 0) <= p0_wr_mask(7 downto 4);
mig_p3_wr_data <= p0_wr_data(95 downto 64);
mig_p3_wr_mask(3 downto 0) <= p0_wr_mask(11 downto 8);
mig_p5_wr_data <= p0_wr_data(127 downto 96);
mig_p5_wr_mask(3 downto 0) <= p0_wr_mask(15 downto 12);
mig_p0_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p1_rd_en <= p0_rd_en and not p0_rd_empty_i;
mig_p2_en <= p0_rd_en and not p0_rd_empty_i;
mig_p4_en <= p0_rd_en and not p0_rd_empty_i;
-- outputs to Applications User Port
p0_rd_data <= (mig_p4_rd_data & mig_p2_rd_data & mig_p1_rd_data & mig_p0_rd_data);
p0_rd_empty_i <= mig_p4_empty;
p0_rd_full <= mig_p4_full;
p0_rd_error <= mig_p0_rd_error or mig_p1_rd_error or mig_p2_error or mig_p4_error;
p0_rd_overflow <= mig_p0_rd_overflow or mig_p1_rd_overflow or mig_p2_overflow or mig_p4_overflow;
p0_wr_underrun <= mig_p0_wr_underrun or mig_p1_wr_underrun or mig_p3_underrun or mig_p5_underrun;
p0_wr_empty <= mig_p5_empty;
p0_wr_full_i <= mig_p5_full;
p0_wr_error <= mig_p0_wr_error or mig_p1_wr_error or mig_p3_error or mig_p5_error;
p0_wr_count <= mig_p5_count;
p0_rd_count <= mig_p4_count;
-- unused MCB's siganls in this configuration
mig_p1_arb_en <= '0';
mig_p1_cmd_clk <= '0';
mig_p1_cmd_en <= '0';
mig_p1_cmd_ra <= (others => '0');
mig_p1_cmd_ba <= (others => '0');
mig_p1_cmd_ca <= (others => '0');
mig_p1_cmd_instr <= (others => '0');
mig_p1_cmd_bl <= (others => '0');
mig_p2_arb_en <= '0';
mig_p2_cmd_clk <= '0';
mig_p2_cmd_en <= '0';
mig_p2_cmd_ra <= (others => '0');
mig_p2_cmd_ba <= (others => '0');
mig_p2_cmd_ca <= (others => '0');
mig_p2_cmd_instr <= (others => '0');
mig_p2_cmd_bl <= (others => '0');
mig_p3_arb_en <= '0';
mig_p3_cmd_clk <= '0';
mig_p3_cmd_en <= '0';
mig_p3_cmd_ra <= (others => '0');
mig_p3_cmd_ba <= (others => '0');
mig_p3_cmd_ca <= (others => '0');
mig_p3_cmd_instr <= (others => '0');
mig_p3_cmd_bl <= (others => '0');
mig_p4_arb_en <= '0';
mig_p4_cmd_clk <= '0';
mig_p4_cmd_en <= '0';
mig_p4_cmd_ra <= (others => '0');
mig_p4_cmd_ba <= (others => '0');
mig_p4_cmd_ca <= (others => '0');
mig_p4_cmd_instr <= (others => '0');
mig_p4_cmd_bl <= (others => '0');
mig_p5_arb_en <= '0';
mig_p5_cmd_clk <= '0';
mig_p5_cmd_en <= '0';
mig_p5_cmd_ra <= (others => '0');
mig_p5_cmd_ba <= (others => '0');
mig_p5_cmd_ca <= (others => '0');
mig_p5_cmd_instr <= (others => '0');
mig_p5_cmd_bl <= (others => '0');
--*******************************END OF CONFIG 5 SIGNALS ********************************
end generate;
uo_cal_start <= uo_cal_start_int;
samc_0: MCB
GENERIC MAP
( PORT_CONFIG => C_PORT_CONFIG,
MEM_WIDTH => C_NUM_DQ_PINS ,
MEM_TYPE => C_MEM_TYPE ,
MEM_BURST_LEN => C_MEM_BURST_LEN ,
MEM_ADDR_ORDER => C_MEM_ADDR_ORDER,
MEM_CAS_LATENCY => C_MEM_CAS_LATENCY,
MEM_DDR3_CAS_LATENCY => C_MEM_DDR3_CAS_LATENCY ,
MEM_DDR2_WRT_RECOVERY => C_MEM_DDR2_WRT_RECOVERY ,
MEM_DDR3_WRT_RECOVERY => C_MEM_DDR3_WRT_RECOVERY ,
MEM_MOBILE_PA_SR => C_MEM_MOBILE_PA_SR ,
MEM_DDR1_2_ODS => C_MEM_DDR1_2_ODS ,
MEM_DDR3_ODS => C_MEM_DDR3_ODS ,
MEM_DDR2_RTT => C_MEM_DDR2_RTT ,
MEM_DDR3_RTT => C_MEM_DDR3_RTT ,
MEM_DDR3_ADD_LATENCY => C_MEM_DDR3_ADD_LATENCY ,
MEM_DDR2_ADD_LATENCY => C_MEM_DDR2_ADD_LATENCY ,
MEM_MOBILE_TC_SR => C_MEM_MOBILE_TC_SR ,
MEM_MDDR_ODS => C_MEM_MDDR_ODS ,
MEM_DDR2_DIFF_DQS_EN => C_MEM_DDR2_DIFF_DQS_EN ,
MEM_DDR2_3_PA_SR => C_MEM_DDR2_3_PA_SR ,
MEM_DDR3_CAS_WR_LATENCY => C_MEM_DDR3_CAS_WR_LATENCY,
MEM_DDR3_AUTO_SR => C_MEM_DDR3_AUTO_SR ,
MEM_DDR2_3_HIGH_TEMP_SR => C_MEM_DDR2_3_HIGH_TEMP_SR,
MEM_DDR3_DYN_WRT_ODT => C_MEM_DDR3_DYN_WRT_ODT ,
MEM_RA_SIZE => C_MEM_ADDR_WIDTH ,
MEM_BA_SIZE => C_MEM_BANKADDR_WIDTH ,
MEM_CA_SIZE => C_MEM_NUM_COL_BITS ,
MEM_RAS_VAL => MEM_RAS_VAL ,
MEM_RCD_VAL => MEM_RCD_VAL ,
MEM_REFI_VAL => MEM_REFI_VAL ,
MEM_RFC_VAL => MEM_RFC_VAL ,
MEM_RP_VAL => MEM_RP_VAL ,
MEM_WR_VAL => MEM_WR_VAL ,
MEM_RTP_VAL => MEM_RTP_VAL ,
MEM_WTR_VAL => MEM_WTR_VAL ,
CAL_BYPASS => C_MC_CALIB_BYPASS,
CAL_RA => C_MC_CALIBRATION_RA,
CAL_BA => C_MC_CALIBRATION_BA ,
CAL_CA => C_MC_CALIBRATION_CA,
CAL_CLK_DIV => C_MC_CALIBRATION_CLK_DIV,
CAL_DELAY => C_MC_CALIBRATION_DELAY,
-- CAL_CALIBRATION_MODE=> C_MC_CALIBRATION_MODE,
ARB_NUM_TIME_SLOTS => C_ARB_NUM_TIME_SLOTS,
ARB_TIME_SLOT_0 => C_ARB_TIME_SLOT_0,
ARB_TIME_SLOT_1 => C_ARB_TIME_SLOT_1,
ARB_TIME_SLOT_2 => C_ARB_TIME_SLOT_2,
ARB_TIME_SLOT_3 => C_ARB_TIME_SLOT_3,
ARB_TIME_SLOT_4 => C_ARB_TIME_SLOT_4,
ARB_TIME_SLOT_5 => C_ARB_TIME_SLOT_5,
ARB_TIME_SLOT_6 => C_ARB_TIME_SLOT_6,
ARB_TIME_SLOT_7 => C_ARB_TIME_SLOT_7,
ARB_TIME_SLOT_8 => C_ARB_TIME_SLOT_8,
ARB_TIME_SLOT_9 => C_ARB_TIME_SLOT_9,
ARB_TIME_SLOT_10 => C_ARB_TIME_SLOT_10,
ARB_TIME_SLOT_11 => C_ARB_TIME_SLOT_11
) PORT MAP
(
-- HIGH-SPEED PLL clock interface
PLLCLK => pllclk1,
PLLCE => pllce1,
PLLLOCK => '1',
-- DQS CLOCK NETWork interface
DQSIOIN => idelay_dqs_ioi_s,
DQSIOIP => idelay_dqs_ioi_m,
UDQSIOIN => idelay_udqs_ioi_s,
UDQSIOIP => idelay_udqs_ioi_m,
--DQSPIN => in_pre_dqsp,
DQI => in_dq,
-- RESETS - GLOBAl and local
SYSRST => MCB_SYSRST ,
-- command port 0
P0ARBEN => mig_p0_arb_en,
P0CMDCLK => mig_p0_cmd_clk,
P0CMDEN => mig_p0_cmd_en,
P0CMDRA => mig_p0_cmd_ra,
P0CMDBA => mig_p0_cmd_ba,
P0CMDCA => mig_p0_cmd_ca,
P0CMDINSTR => mig_p0_cmd_instr,
P0CMDBL => mig_p0_cmd_bl,
P0CMDEMPTY => mig_p0_cmd_empty,
P0CMDFULL => mig_p0_cmd_full,
-- command port 1
P1ARBEN => mig_p1_arb_en,
P1CMDCLK => mig_p1_cmd_clk,
P1CMDEN => mig_p1_cmd_en,
P1CMDRA => mig_p1_cmd_ra,
P1CMDBA => mig_p1_cmd_ba,
P1CMDCA => mig_p1_cmd_ca,
P1CMDINSTR => mig_p1_cmd_instr,
P1CMDBL => mig_p1_cmd_bl,
P1CMDEMPTY => mig_p1_cmd_empty,
P1CMDFULL => mig_p1_cmd_full,
-- command port 2
P2ARBEN => mig_p2_arb_en,
P2CMDCLK => mig_p2_cmd_clk,
P2CMDEN => mig_p2_cmd_en,
P2CMDRA => mig_p2_cmd_ra,
P2CMDBA => mig_p2_cmd_ba,
P2CMDCA => mig_p2_cmd_ca,
P2CMDINSTR => mig_p2_cmd_instr,
P2CMDBL => mig_p2_cmd_bl,
P2CMDEMPTY => mig_p2_cmd_empty,
P2CMDFULL => mig_p2_cmd_full,
-- command port 3
P3ARBEN => mig_p3_arb_en,
P3CMDCLK => mig_p3_cmd_clk,
P3CMDEN => mig_p3_cmd_en,
P3CMDRA => mig_p3_cmd_ra,
P3CMDBA => mig_p3_cmd_ba,
P3CMDCA => mig_p3_cmd_ca,
P3CMDINSTR => mig_p3_cmd_instr,
P3CMDBL => mig_p3_cmd_bl,
P3CMDEMPTY => mig_p3_cmd_empty,
P3CMDFULL => mig_p3_cmd_full,
-- command port 4 -- don't care in config 2
P4ARBEN => mig_p4_arb_en,
P4CMDCLK => mig_p4_cmd_clk,
P4CMDEN => mig_p4_cmd_en,
P4CMDRA => mig_p4_cmd_ra,
P4CMDBA => mig_p4_cmd_ba,
P4CMDCA => mig_p4_cmd_ca,
P4CMDINSTR => mig_p4_cmd_instr,
P4CMDBL => mig_p4_cmd_bl,
P4CMDEMPTY => mig_p4_cmd_empty,
P4CMDFULL => mig_p4_cmd_full,
-- command port 5-- don't care in config 2
P5ARBEN => mig_p5_arb_en,
P5CMDCLK => mig_p5_cmd_clk,
P5CMDEN => mig_p5_cmd_en,
P5CMDRA => mig_p5_cmd_ra,
P5CMDBA => mig_p5_cmd_ba,
P5CMDCA => mig_p5_cmd_ca,
P5CMDINSTR => mig_p5_cmd_instr,
P5CMDBL => mig_p5_cmd_bl,
P5CMDEMPTY => mig_p5_cmd_empty,
P5CMDFULL => mig_p5_cmd_full,
-- IOI & IOB SIGNals/tristate interface
DQIOWEN0 => dqIO_w_en_0,
DQSIOWEN90P => dqsIO_w_en_90_p,
DQSIOWEN90N => dqsIO_w_en_90_n,
-- IOB MEMORY INTerface signals
ADDR => address_90,
BA => ba_90 ,
RAS => ras_90 ,
CAS => cas_90 ,
WE => we_90 ,
CKE => cke_90 ,
ODT => odt_90 ,
RST => rst_90 ,
-- CALIBRATION DRP interface
IOIDRPCLK => ioi_drp_clk ,
IOIDRPADDR => ioi_drp_addr ,
IOIDRPSDO => ioi_drp_sdo ,
IOIDRPSDI => ioi_drp_sdi ,
IOIDRPCS => ioi_drp_cs ,
IOIDRPADD => ioi_drp_add ,
IOIDRPBROADCAST => ioi_drp_broadcast ,
IOIDRPTRAIN => ioi_drp_train ,
IOIDRPUPDATE => ioi_drp_update ,
-- CALIBRATION DAtacapture interface
--SPECIAL COMMANDs
RECAL => mcb_recal ,
UIREAD => mcb_ui_read,
UIADD => mcb_ui_add ,
UICS => mcb_ui_cs ,
UICLK => mcb_ui_clk ,
UISDI => mcb_ui_sdi ,
UIADDR => mcb_ui_addr ,
UIBROADCAST => mcb_ui_broadcast,
UIDRPUPDATE => mcb_ui_drp_update,
UIDONECAL => mcb_ui_done_cal,
UICMD => mcb_ui_cmd,
UICMDIN => mcb_ui_cmd_in,
UICMDEN => mcb_ui_cmd_en,
UIDQCOUNT => mcb_ui_dqcount,
UIDQLOWERDEC => mcb_ui_dq_lower_dec,
UIDQLOWERINC => mcb_ui_dq_lower_inc,
UIDQUPPERDEC => mcb_ui_dq_upper_dec,
UIDQUPPERINC => mcb_ui_dq_upper_inc,
UIUDQSDEC => mcb_ui_udqs_dec,
UIUDQSINC => mcb_ui_udqs_inc,
UILDQSDEC => mcb_ui_ldqs_dec,
UILDQSINC => mcb_ui_ldqs_inc,
UODATA => uo_data_int,
UODATAVALID => uo_data_valid_int,
UODONECAL => hard_done_cal ,
UOCMDREADYIN => uo_cmd_ready_in_int,
UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
UOCALSTART => uo_cal_start_int,
UOSDO => uo_sdo_xhdl24,
--CONTROL SIGNALS
STATUS => status,
SELFREFRESHENTER => selfrefresh_mcb_enter,
SELFREFRESHMODE => selfrefresh_mcb_mode,
------------------------------------------------
--MUIs
------------------------------------------------
P0RDDATA => mig_p0_rd_data ( 31 downto 0),
P1RDDATA => mig_p1_rd_data ( 31 downto 0),
P2RDDATA => mig_p2_rd_data ( 31 downto 0),
P3RDDATA => mig_p3_rd_data ( 31 downto 0),
P4RDDATA => mig_p4_rd_data ( 31 downto 0),
P5RDDATA => mig_p5_rd_data ( 31 downto 0),
LDMN => dqnlm ,
UDMN => dqnum ,
DQON => dqo_n ,
DQOP => dqo_p ,
LDMP => dqplm ,
UDMP => dqpum ,
P0RDCOUNT => mig_p0_rd_count ,
P0WRCOUNT => mig_p0_wr_count ,
P1RDCOUNT => mig_p1_rd_count ,
P1WRCOUNT => mig_p1_wr_count ,
P2COUNT => mig_p2_count ,
P3COUNT => mig_p3_count ,
P4COUNT => mig_p4_count ,
P5COUNT => mig_p5_count ,
-- NEW ADDED FIFo status siganls
-- MIG USER PORT 0
P0RDEMPTY => mig_p0_rd_empty,
P0RDFULL => mig_p0_rd_full,
P0RDOVERFLOW => mig_p0_rd_overflow,
P0WREMPTY => mig_p0_wr_empty,
P0WRFULL => mig_p0_wr_full,
P0WRUNDERRUN => mig_p0_wr_underrun,
-- MIG USER PORT 1
P1RDEMPTY => mig_p1_rd_empty,
P1RDFULL => mig_p1_rd_full,
P1RDOVERFLOW => mig_p1_rd_overflow,
P1WREMPTY => mig_p1_wr_empty,
P1WRFULL => mig_p1_wr_full,
P1WRUNDERRUN => mig_p1_wr_underrun,
-- MIG USER PORT 2
P2EMPTY => mig_p2_empty,
P2FULL => mig_p2_full,
P2RDOVERFLOW => mig_p2_overflow,
P2WRUNDERRUN => mig_p2_underrun,
P3EMPTY => mig_p3_empty ,
P3FULL => mig_p3_full ,
P3RDOVERFLOW => mig_p3_overflow,
P3WRUNDERRUN => mig_p3_underrun ,
-- MIG USER PORT 3
P4EMPTY => mig_p4_empty,
P4FULL => mig_p4_full,
P4RDOVERFLOW => mig_p4_overflow,
P4WRUNDERRUN => mig_p4_underrun,
P5EMPTY => mig_p5_empty ,
P5FULL => mig_p5_full ,
P5RDOVERFLOW => mig_p5_overflow,
P5WRUNDERRUN => mig_p5_underrun,
---------------------------------------------------------
P0WREN => mig_p0_wr_en,
P0RDEN => mig_p0_rd_en,
P1WREN => mig_p1_wr_en,
P1RDEN => mig_p1_rd_en,
P2EN => mig_p2_en,
P3EN => mig_p3_en,
P4EN => mig_p4_en,
P5EN => mig_p5_en,
-- WRITE MASK BIts connection
P0RWRMASK => mig_p0_wr_mask(3 downto 0),
P1RWRMASK => mig_p1_wr_mask(3 downto 0),
P2WRMASK => mig_p2_wr_mask(3 downto 0),
P3WRMASK => mig_p3_wr_mask(3 downto 0),
P4WRMASK => mig_p4_wr_mask(3 downto 0),
P5WRMASK => mig_p5_wr_mask(3 downto 0),
-- DATA WRITE COnnection
P0WRDATA => mig_p0_wr_data(31 downto 0),
P1WRDATA => mig_p1_wr_data(31 downto 0),
P2WRDATA => mig_p2_wr_data(31 downto 0),
P3WRDATA => mig_p3_wr_data(31 downto 0),
P4WRDATA => mig_p4_wr_data(31 downto 0),
P5WRDATA => mig_p5_wr_data(31 downto 0),
P0WRERROR => mig_p0_wr_error,
P1WRERROR => mig_p1_wr_error,
P0RDERROR => mig_p0_rd_error,
P1RDERROR => mig_p1_rd_error,
P2ERROR => mig_p2_error,
P3ERROR => mig_p3_error,
P4ERROR => mig_p4_error,
P5ERROR => mig_p5_error,
-- USER SIDE DAta ports clock
-- 128 BITS CONnections
P0WRCLK => mig_p0_wr_clk ,
P1WRCLK => mig_p1_wr_clk ,
P0RDCLK => mig_p0_rd_clk ,
P1RDCLK => mig_p1_rd_clk ,
P2CLK => mig_p2_clk ,
P3CLK => mig_p3_clk ,
P4CLK => mig_p4_clk ,
P5CLK => mig_p5_clk
);
--//////////////////////////////////////////////////////
--// Input Termination Calibration
--//////////////////////////////////////////////////////
uo_done_cal <= DONE_SOFTANDHARD_CAL WHEN (C_CALIB_SOFT_IP = "TRUE") ELSE
hard_done_cal;
gen_term_calib : IF (C_CALIB_SOFT_IP = "TRUE") GENERATE
mcb_soft_calibration_top_inst : mcb_soft_calibration_top
generic map ( C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => C_SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => C_SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => C_SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
PORT MAP (
UI_CLK => ui_clk,
RST => int_sys_rst,
IOCLK => ioclk0,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL,
PLL_LOCK => pll_lock,
SELFREFRESH_REQ => selfrefresh_enter, -- from user app
SELFREFRESH_MCB_MODE => selfrefresh_mcb_mode, -- from MCB
SELFREFRESH_MCB_REQ => selfrefresh_mcb_enter, -- to mcb
SELFREFRESH_MODE => selfrefresh_mode, -- to user app
MCB_UIADD => mcb_ui_add,
MCB_UISDI => mcb_ui_sdi,
MCB_UOSDO => uo_sdo_xhdl24,
MCB_UODONECAL => hard_done_cal,
MCB_UOREFRSHFLAG => uo_refrsh_flag_xhdl23,
MCB_UICS => mcb_ui_cs,
MCB_UIDRPUPDATE => mcb_ui_drp_update,
MCB_UIBROADCAST => mcb_ui_broadcast,
MCB_UIADDR => mcb_ui_addr,
MCB_UICMDEN => mcb_ui_cmd_en,
MCB_UIDONECAL => mcb_ui_done_cal,
MCB_UIDQLOWERDEC => mcb_ui_dq_lower_dec,
MCB_UIDQLOWERINC => mcb_ui_dq_lower_inc,
MCB_UIDQUPPERDEC => mcb_ui_dq_upper_dec,
MCB_UIDQUPPERINC => mcb_ui_dq_upper_inc,
MCB_UILDQSDEC => mcb_ui_ldqs_dec,
MCB_UILDQSINC => mcb_ui_ldqs_inc,
MCB_UIREAD => mcb_ui_read,
MCB_UIUDQSDEC => mcb_ui_udqs_dec,
MCB_UIUDQSINC => mcb_ui_udqs_inc,
MCB_RECAL => mcb_recal,
MCB_SYSRST => MCB_SYSRST,
MCB_UICMD => mcb_ui_cmd,
MCB_UICMDIN => mcb_ui_cmd_in,
MCB_UIDQCOUNT => mcb_ui_dqcount,
MCB_UODATA => uo_data_int,
MCB_UODATAVALID => uo_data_valid_int,
MCB_UOCMDREADY => uo_cmd_ready_in_int,
MCB_UO_CAL_START => uo_cal_start_int,
RZQ_PIN => rzq,
ZIO_PIN => zio,
CKE_Train => cke_train
);
mcb_ui_clk <= ui_clk;
END GENERATE;
gen_no_term_calib : if (NOT(C_CALIB_SOFT_IP = "TRUE")) generate
DONE_SOFTANDHARD_CAL <= '0';
MCB_SYSRST <= int_sys_rst;
mcb_recal <= calib_recal;
mcb_ui_read <= ui_read;
mcb_ui_add <= ui_add;
mcb_ui_cs <= ui_cs;
mcb_ui_clk <= ui_clk;
mcb_ui_sdi <= ui_sdi;
mcb_ui_addr <= ui_addr;
mcb_ui_broadcast <= ui_broadcast;
mcb_ui_drp_update <= ui_drp_update;
mcb_ui_done_cal <= ui_done_cal;
mcb_ui_cmd <= ui_cmd;
mcb_ui_cmd_in <= ui_cmd_in;
mcb_ui_cmd_en <= ui_cmd_en;
mcb_ui_dqcount <= ui_dqcount;
mcb_ui_dq_lower_dec <= ui_dq_lower_dec;
mcb_ui_dq_lower_inc <= ui_dq_lower_inc;
mcb_ui_dq_upper_dec <= ui_dq_upper_dec;
mcb_ui_dq_upper_inc <= ui_dq_upper_inc;
mcb_ui_udqs_inc <= ui_udqs_inc;
mcb_ui_udqs_dec <= ui_udqs_dec;
mcb_ui_ldqs_inc <= ui_ldqs_inc;
mcb_ui_ldqs_dec <= ui_ldqs_dec;
end generate;
--//////////////////////////////////////////////////////
--//ODDRDES2 instantiations
--//////////////////////////////////////////////////////
--------
--ADDR
--------
gen_addr_oserdes2 : FOR addr_ioi IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
ioi_addr_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_addr(addr_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_addr(addr_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => address_90(addr_ioi),
D2 => address_90(addr_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--BA
--------
gen_ba_oserdes2 : FOR ba_ioi IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
ioi_ba_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ba(ba_ioi),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ba(ba_ioi),
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ba_90(ba_ioi),
D2 => ba_90(ba_ioi),
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--CAS
--------
ioi_cas_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_cas,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cas,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cas_90,
D2 => cas_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CKE
--------
ioi_cke_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 15
)
PORT MAP (
OQ => ioi_cke,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_cke,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => cke_90,
D2 => cke_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => cke_train
);
--------
--ODT
--------
xhdl330 : IF (C_MEM_TYPE = "DDR3" OR C_MEM_TYPE = "DDR2") GENERATE
ioi_odt_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => ioi_odt,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_odt,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => odt_90,
D2 => odt_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--RAS
--------
ioi_ras_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ras,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ras,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => ras_90,
D2 => ras_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--RST
--------
xhdl331 : IF (C_MEM_TYPE = "DDR3") GENERATE
ioi_rst_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_rst,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_rst,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => rst_90,
D2 => rst_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
END GENERATE;
--------
--WE
--------
ioi_we_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_we,
TQ => t_we,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => we_90,
D2 => we_90,
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--CK
--------
ioi_ck_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ioi_ck,
SHIFTOUT1 => open,--ck_shiftout0_1,
SHIFTOUT2 => open,--ck_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => t_ck,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => '0', --int_sys_rst
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
----------
----CKN
----------
-- ioi_ckn_0 : OSERDES2
-- GENERIC MAP (
-- BYPASS_GCLK_FF => TRUE,
-- DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
-- DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
-- OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
-- SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
-- DATA_WIDTH => 2
-- )
-- PORT MAP (
-- OQ => ioi_ckn,
-- SHIFTOUT1 => open,
-- SHIFTOUT2 => open,
-- SHIFTOUT3 => open,--ck_shiftout1_3,
-- SHIFTOUT4 => open,--ck_shiftout1_4,
-- TQ => t_ckn,
-- CLK0 => ioclk0,
-- CLK1 => '0',
-- CLKDIV => '0',
-- D1 => '1',
-- D2 => '0',
-- D3 => '0',
-- D4 => '0',
-- IOCE => pll_ce_0,
-- OCE => '1',
-- RST => '0',
-- SHIFTIN1 => '0',
-- SHIFTIN2 => '0',
-- SHIFTIN3 => '0',
-- SHIFTIN4 => '0',
-- T1 => '0',
-- T2 => '0',
-- T3 => '0',
-- T4 => '0',
-- TCE => '1',
-- TRAIN => '0'
-- );
--
--------
--UDM
--------
ioi_udm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => udm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqpum,
D2 => dqnum,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--LDM
--------
ioi_ldm_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
)
PORT MAP (
OQ => ldm_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => ldm_t,
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqplm,
D2 => dqnlm,
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQ
--------
gen_dq : FOR dq IN 0 TO C_NUM_DQ_PINS-1 GENERATE
oserdes2_dq_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2,
TRAIN_PATTERN => 5
)
PORT MAP (
OQ => dq_oq(dq),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dq_tq(dq),
CLK0 => ioclk90,
CLK1 => '0',
CLKDIV => '0',
D1 => dqo_p(dq),
D2 => dqo_n(dq),
D3 => '0',
D4 => '0',
IOCE => pll_ce_90,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqIO_w_en_0,
T2 => dqIO_w_en_0,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => ioi_drp_train
);
END GENERATE;
--------
--DQSP
--------
oserdes2_dqsp_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsp_oq,
SHIFTOUT1 => open,--dqs_shiftout0_1,
SHIFTOUT2 => open,--dqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => dqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--dqs_shiftout1_3,
SHIFTIN4 => '0',--dqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--DQSN
--------
oserdes2_dqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => dqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--dqs_shiftout1_3,
SHIFTOUT4 => open,--dqs_shiftout1_4,
TQ => dqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--dqs_shiftout0_1,
SHIFTIN2 => '0',--dqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
--------
--UDQSP
--------
oserdeS2_UDQSP_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_MASTER,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsp_oq,
SHIFTOUT1 => open,--udqs_shiftout0_1,
SHIFTOUT2 => open,--udqs_shiftout0_2,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TQ => udqsp_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '0',
D2 => '1',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTIN3 => '0',--udqs_shiftout1_3,
SHIFTIN4 => '0',--udqs_shiftout1_4,
T1 => dqsIO_w_en_90_n,
t2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
tce => '1',
train => '0'
);
--------
--UDQSN
--------
oserdes2_udqsn_0 : OSERDES2
GENERIC MAP (
BYPASS_GCLK_FF => TRUE,
DATA_RATE_OQ => C_OSERDES2_DATA_RATE_OQ,
DATA_RATE_OT => C_OSERDES2_DATA_RATE_OT,
OUTPUT_MODE => C_OSERDES2_OUTPUT_MODE_SE,
SERDES_MODE => C_OSERDES2_SERDES_MODE_SLAVE,
DATA_WIDTH => 2
-- TRAIN_PATTERN => 0
)
PORT MAP (
OQ => udqsn_oq,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,--udqs_shiftout1_3,
SHIFTOUT4 => open,--udqs_shiftout1_4,
TQ => udqsn_tq,
CLK0 => ioclk0,
CLK1 => '0',
CLKDIV => '0',
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => pll_ce_0,
OCE => '1',
RST => int_sys_rst,
SHIFTIN1 => '0',--udqs_shiftout0_1,
SHIFTIN2 => '0',--udqs_shiftout0_2,
SHIFTIN3 => '0',
SHIFTIN4 => '0',
T1 => dqsIO_w_en_90_n,
T2 => dqsIO_w_en_90_p,
T3 => '0',
T4 => '0',
TCE => '1',
TRAIN => '0'
);
------------------------------------------------------
--*********************************** OSERDES2 instantiations end *******************************************
------------------------------------------------------
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
---#####################################--X16 MEMORY WIDTH-#############################################
dq_15_0_data : if (C_NUM_DQ_PINS = 16) GENERATE
--////////////////////////////////////////////////
--DQ14
--////////////////////////////////////////////////
iodrp2_DQ_14 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ14_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_14,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(14),
DQSOUTN => open,
DQSOUTP => in_dq(14),
SDO => open,
TOUT => t_dq(14),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_15,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(14),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(14),
SDI => ioi_drp_sdo,
T => dq_tq(14)
);
--////////////////////////////////////////////////
--DQ15
--////////////////////////////////////////////////
iodrp2_dq_15 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ15_TAP_DELAY_VAL,
MCB_ADDRESS => 7,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_15,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(15),
DQSOUTN => open,
DQSOUTP => in_dq(15),
SDO => open,
TOUT => t_dq(15),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(15),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(15),
SDI => ioi_drp_sdo,
T => dq_tq(15)
);
--////////////////////////////////////////////////
--DQ12
--////////////////////////////////////////////////
iodrp2_DQ_12 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ12_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_12,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(12),
DQSOUTN => open,
DQSOUTP => in_dq(12),
SDO => open,
TOUT => t_dq(12),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_13,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(12),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(12),
SDI => ioi_drp_sdo,
T => dq_tq(12)
);
--////////////////////////////////////////////////
--DQ13
--////////////////////////////////////////////////
iodrp2_dq_13 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ13_TAP_DELAY_VAL,
MCB_ADDRESS => 6,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_13,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(13),
DQSOUTN => open,
DQSOUTP => in_dq(13),
SDO => open,
TOUT => t_dq(13),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_14,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(13),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(13),
SDI => ioi_drp_sdo,
T => dq_tq(13)
);
--/////////
--UDQSP
--/////////
iodrp2_UDQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqs,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_m,
SDO => open,
TOUT => t_udqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsp_oq,
SDI => ioi_drp_sdo,
T => udqsp_tq
);
--/////////
--UDQSN
--/////////
iodrp2_udqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => UDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 14,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_udqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udqsn,
DQSOUTN => open,
DQSOUTP => idelay_udqs_ioi_s,
SDO => open,
TOUT => t_udqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_12,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_udqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udqsn_oq,
SDI => ioi_drp_sdo,
T => udqsn_tq
);
--/////////////////////////////////////////////////
--//DQ10
--////////////////////////////////////////////////
iodrp2_DQ_10 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ10_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_10,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(10),
DQSOUTN => open,
DQSOUTP => in_dq(10),
SDO => open,
TOUT => t_dq(10),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_11,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(10),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(10),
SDI => ioi_drp_sdo,
T => dq_tq(10)
);
--/////////////////////////////////////////////////
--//DQ11
--////////////////////////////////////////////////
iodrp2_dq_11 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ11_TAP_DELAY_VAL,
MCB_ADDRESS => 5,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_11,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(11),
DQSOUTN => open,
DQSOUTP => in_dq(11),
SDO => open,
TOUT => t_dq(11),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_udqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(11),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(11),
SDI => ioi_drp_sdo,
T => dq_tq(11)
);
--/////////////////////////////////////////////////
--//DQ8
--////////////////////////////////////////////////
iodrp2_DQ_8 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ8_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_8,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(8),
DQSOUTN => open,
DQSOUTP => in_dq(8),
SDO => open,
TOUT => t_dq(8),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_9,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(8),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(8),
SDI => ioi_drp_sdo,
T => dq_tq(8)
);
--/////////////////////////////////////////////////
--//DQ9
--////////////////////////////////////////////////
iodrp2_dq_9 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ9_TAP_DELAY_VAL,
MCB_ADDRESS => 4,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_9,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(9),
DQSOUTN => open,
DQSOUTP => in_dq(9),
SDO => open,
TOUT => t_dq(9),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_10,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(9),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(9),
SDI => ioi_drp_sdo,
T => dq_tq(9)
);
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_8,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X8 MEMORY WIDTH-#############################################
dq_7_0_data : if (C_NUM_DQ_PINS = 8) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--/////////
--//DQSP
--/////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--/////////
--//DQSN
--/////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--/////////////////////////////////////////////////
--//DQ6
--////////////////////////////////////////////////
iodrp2_DQ_6 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ6_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_6,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(6),
DQSOUTN => open,
DQSOUTP => in_dq(6),
SDO => open,
TOUT => t_dq(6),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_7,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(6),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(6),
SDI => ioi_drp_sdo,
T => dq_tq(6)
);
--/////////////////////////////////////////////////
--//DQ7
--////////////////////////////////////////////////
iodrp2_dq_7 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ7_TAP_DELAY_VAL,
MCB_ADDRESS => 3,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_7,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(7),
DQSOUTN => open,
DQSOUTP => in_dq(7),
SDO => open,
TOUT => t_dq(7),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsp,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(7),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(7),
SDI => ioi_drp_sdo,
T => dq_tq(7)
);
--/////////////////////////////////////////////////
--//DQ4
--////////////////////////////////////////////////
iodrp2_DQ_4 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ4_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_4,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(4),
DQSOUTN => open,
DQSOUTP => in_dq(4),
SDO => open,
TOUT => t_dq(4),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_5,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(4),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(4),
SDI => ioi_drp_sdo,
T => dq_tq(4)
);
--/////////////////////////////////////////////////
--//DQ5
--////////////////////////////////////////////////
iodrp2_dq_5 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ5_TAP_DELAY_VAL,
MCB_ADDRESS => 2,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_5,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(5),
DQSOUTN => open,
DQSOUTP => in_dq(5),
SDO => open,
TOUT => t_dq(5),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_6,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(5),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(5),
SDI => ioi_drp_sdo,
T => dq_tq(5)
);
--NEED TO GENERATE UDM so that user won't instantiate in this location
--/////////////////////////////////////////////////
--//UDM
--////////////////////////////////////////////////
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--/////////////////////////////////////////////////
--//LDM
--////////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
---#####################################--X4 MEMORY WIDTH-#############################################
dq_3_0_data : if (C_NUM_DQ_PINS = 4) GENERATE
--/////////////////////////////////////////////////
--//DQ0
--////////////////////////////////////////////////
iodrp2_DQ_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ0_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_0,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(0),
DQSOUTN => open,
DQSOUTP => in_dq(0),
SDO => open,
TOUT => t_dq(0),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_1,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(0),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(0),
SDI => ioi_drp_sdo,
T => dq_tq(0)
);
--/////////////////////////////////////////////////
--//DQ1
--////////////////////////////////////////////////
iodrp2_dq_1 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ1_TAP_DELAY_VAL,
MCB_ADDRESS => 0,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_1,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(1),
DQSOUTN => open,
DQSOUTP => in_dq(1),
SDO => open,
TOUT => t_dq(1),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => '0',
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(1),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(1),
SDI => ioi_drp_sdo,
T => dq_tq(1)
);
--/////////////////////////////////////////////////
--//DQ2
--////////////////////////////////////////////////
iodrp2_DQ_2 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ2_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_2,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(2),
DQSOUTN => open,
DQSOUTP => in_dq(2),
SDO => open,
TOUT => t_dq(2),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_3,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(2),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(2),
SDI => ioi_drp_sdo,
T => dq_tq(2)
);
--/////////////////////////////////////////////////
--//DQ3
--////////////////////////////////////////////////
iodrp2_dq_3 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => DQ3_TAP_DELAY_VAL,
MCB_ADDRESS => 1,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_3,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dq(3),
DQSOUTN => open,
DQSOUTP => in_dq(3),
SDO => open,
TOUT => t_dq(3),
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_0,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dq(3),
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dq_oq(3),
SDI => ioi_drp_sdo,
T => dq_tq(3)
);
--///////////////////////////////////////////////
--DQSP
--///////////////////////////////////////////////
iodrp2_DQSP_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSP_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsp,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqs,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_m,
SDO => open,
TOUT => t_dqs,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_dqsn,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsp_oq,
SDI => ioi_drp_sdo,
T => dqsp_tq
);
--///////////////////////////////////////////////
--DQSN
--///////////////////////////////////////////////
iodrp2_dqsn_0 : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQS_IODRP2_DATA_RATE,
IDELAY_VALUE => LDQSN_TAP_DELAY_VAL,
MCB_ADDRESS => 15,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQS_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_dqsn,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_dqsn,
DQSOUTN => open,
DQSOUTP => idelay_dqs_ioi_s,
SDO => open,
TOUT => t_dqsn,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_2,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => in_pre_dqsp,
IOCLK0 => ioclk0,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => dqsn_oq,
SDI => ioi_drp_sdo,
T => dqsn_tq
);
--///////////////////////////////////////////////
--UDM
--//////////////////////////////////////////////
--NEED TO GENERATE UDM so that user won't instantiate in this location
iodrp2_dq_udm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_MASTER,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => ioi_drp_sdi,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_udm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_udm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_ldm,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => udm_oq,
SDI => ioi_drp_sdo,
T => udm_t
);
--///////////////////////////////////////////////
--LDM
--//////////////////////////////////////////////
iodrp2_dq_ldm : IODRP2_MCB
GENERIC MAP (
DATA_RATE => C_DQ_IODRP2_DATA_RATE,
IDELAY_VALUE => 0,
MCB_ADDRESS => 8,
ODELAY_VALUE => 0,
SERDES_MODE => C_DQ_IODRP2_SERDES_MODE_SLAVE,
SIM_TAPDELAY_VALUE => 10
)
PORT MAP (
AUXSDO => aux_sdi_out_ldm,
DATAOUT => open,
DATAOUT2 => open,
DOUT => ioi_ldm,
DQSOUTN => open,
DQSOUTP => open,
SDO => open,
TOUT => t_ldm,
ADD => ioi_drp_add,
AUXADDR => ioi_drp_addr,
AUXSDOIN => aux_sdi_out_4,
BKST => ioi_drp_broadcast,
CLK => ioi_drp_clk,
CS => ioi_drp_cs,
IDATAIN => '0',
IOCLK0 => ioclk90,
IOCLK1 => '0',
MEMUPDATE => ioi_drp_update,
ODATAIN => ldm_oq,
SDI => ioi_drp_sdo,
T => ldm_t
);
end generate;
------------------------------------------------
--&&&&&&&&&&&&&&&&&&&&&&&&&&&&&& IODRP2 instantiations end &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
------------------------------------------------
-------^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--IOBs instantiations
-- this part need more inputs from design team
-- for now just use as listed in fpga.v
-----^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- DRAM Address
gen_addr_obuft : FOR addr_i IN 0 TO C_MEM_ADDR_WIDTH - 1 GENERATE
iob_addr_inst : OBUFT
PORT MAP (
I => ioi_addr(addr_i),
T => t_addr(addr_i),
O => mcbx_dram_addr(addr_i)
);
END GENERATE;
gen_ba_obuft : FOR ba_i IN 0 TO C_MEM_BANKADDR_WIDTH - 1 GENERATE
iob_ba_inst : OBUFT
PORT MAP (
I => ioi_ba(ba_i),
T => t_ba(ba_i),
O => mcbx_dram_ba(ba_i)
);
END GENERATE;
-- DRAM control
--RAS
iob_ras : OBUFT
PORT MAP (
O => mcbx_dram_ras_n,
I => ioi_ras,
T => t_ras
);
--CAS
iob_cas : OBUFT
PORT MAP (
O => mcbx_dram_cas_n,
I => ioi_cas,
T => t_cas
);
--WE
iob_we : OBUFT
PORT MAP (
O => mcbx_dram_we_n,
I => ioi_we,
T => t_we
);
--CKE
iob_cke : OBUFT
PORT MAP (
O => mcbx_dram_cke,
I => ioi_cke,
T => t_cke
);
--DDR3 RST
gen_ddr3_rst : IF (C_MEM_TYPE = "DDR3") GENERATE
iob_rst : OBUFT
PORT MAP (
O => mcbx_dram_ddr3_rst,
I => ioi_rst,
T => t_rst
);
END GENERATE;
--ODT
gen_dram_odt : IF ((C_MEM_TYPE = "DDR3" AND (not(C_MEM_DDR3_RTT = "OFF") OR not(C_MEM_DDR3_DYN_WRT_ODT = "OFF")))
OR (C_MEM_TYPE = "DDR2" AND not(C_MEM_DDR2_RTT = "OFF")) ) GENERATE
iob_odt : OBUFT
PORT MAP (
O => mcbx_dram_odt,
I => ioi_odt,
t => t_odt
);
END GENERATE;
--MEMORY CLOCK
iob_clk : OBUFTDS
PORT MAP (
I => ioi_ck,
T => t_ck,
O => mcbx_dram_clk,
OB => mcbx_dram_clk_n
);
--DQ
gen_dq_iobuft : FOR dq_i IN 0 TO C_NUM_DQ_PINS-1 GENERATE
gen_iob_dq_inst : IOBUF
PORT MAP (
IO => mcbx_dram_dq(dq_i),
I => ioi_dq(dq_i),
T => t_dq(dq_i),
O => in_pre_dq(dq_i)
);
END GENERATE;
-- x4 and x8
--DQS
gen_dqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO")))) generate
iob_dqs : IOBUF
PORT MAP (
IO => mcbx_dram_dqs,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
--DQSP/DQSN
gen_dqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
iob_dqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_dqs,
IOB => mcbx_dram_dqs_n,
I => ioi_dqs,
T => t_dqs,
O => in_pre_dqsp
);
end generate;
-- x16
--UDQS
gen_udqs_iobuf : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUF
PORT MAP (
IO => mcbx_dram_udqs,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
----UDQSP/UDQSN
gen_udqs_iobufds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES"))) and C_NUM_DQ_PINS = 16) generate
iob_udqs : IOBUFDS
PORT MAP (
IO => mcbx_dram_udqs,
IOB => mcbx_dram_udqs_n,
I => ioi_udqs,
T => t_udqs,
O => in_pre_udqsp
);
end generate;
-- DQS PULLDWON
gen_dqs_pullupdn: if(C_MEM_TYPE = "DDR" or C_MEM_TYPE ="MDDR" or (C_MEM_TYPE = "DDR2" and (C_MEM_DDR2_DIFF_DQS_EN = "NO"))) generate
dqs_pulldown : PULLDOWN port map (O => mcbx_dram_dqs);
end generate;
gen_dqs_pullupdn_ds : if((C_MEM_TYPE = "DDR3" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "YES")))) generate
dqs_pulldown :PULLDOWN port map (O => mcbx_dram_dqs);
dqs_n_pullup : PULLUP port map (O => mcbx_dram_dqs_n);
end generate;
-- DQSN PULLUP
gen_udqs_pullupdn : if((C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) and C_NUM_DQ_PINS = 16) generate
udqs_pulldown : PULLDOWN port map (O => mcbx_dram_udqs);
end generate;
gen_udqs_pullupdn_ds : if ((C_NUM_DQ_PINS = 16) and not(C_MEM_TYPE = "DDR" or C_MEM_TYPE = "MDDR" or (C_MEM_TYPE = "DDR2" and
(C_MEM_DDR2_DIFF_DQS_EN = "NO"))) ) generate
udqs_pulldown :PULLDOWN port map (O => mcbx_dram_udqs);
udqs_n_pullup : PULLUP port map (O => mcbx_dram_udqs_n);
end generate;
--UDM
gen_udm : if(C_NUM_DQ_PINS = 16) generate
iob_udm : OBUFT
PORT MAP (
I => ioi_udm,
T => t_udm,
O => mcbx_dram_udm
);
end generate;
--LDM
iob_ldm : OBUFT
PORT MAP (
I => ioi_ldm,
T => t_ldm,
O => mcbx_dram_ldm
);
end aarch;
| gpl-3.0 | 85973941fb291fa3e58661e963b948de | 0.420977 | 3.317556 | false | false | false | false |
aleksandar-mitrevski/hw_sw | jk_flip_flop/testbench.vhd | 1 | 2,484 | library IEEE;
use IEEE.std_logic_1164.All;
use IEEE.std_logic_unsigned.All;
entity testbench is end testbench;
architecture tb_jkff of testbench is
signal clk : std_logic := '0';
signal j : std_logic;
signal k : std_logic;
signal q_out : std_logic;
signal q_not_out : std_logic;
constant twenty_five_nsec : time := 25 ns;
component JKFlipFlop port (
clk : in std_logic;
j : in std_logic;
k : in std_logic;
q_out : inout std_logic;
q_not_out : inout std_logic);
end component JKFlipFlop;
begin
JKFlipFlop1 : JKFlipFlop
port map (
clk => clk,
j => j,
k => k,
q_out => q_out,
q_not_out => q_not_out);
create_twenty_Mhz: process
begin
wait for twenty_five_nsec;
clk <= NOT clk;
end process;
check_q: process
begin
wait for 50 ns;
j <= '0';
k <= '1';
wait for 30 ns;
assert q_out = '0' report "1 failed";
wait for 20 ns;
j <= '1';
k <= '0';
wait for 30 ns;
assert q_out = '1' report "2 failed";
wait for 20 ns;
j <= '0';
k <= '0';
wait for 30 ns;
assert q_out = '1' report "3 failed";
wait for 20 ns;
j <= '1';
k <= '1';
wait for 30 ns;
assert q_out = '0' report "4 failed";
wait for 20 ns;
j <= '0';
k <= '1';
wait for 30 ns;
assert q_out = '0' report "5 failed";
wait for 20 ns;
j <= '1';
k <= '1';
wait for 30 ns;
assert q_out = '1' report "6 failed";
wait for 20 ns;
j <= '0';
k <= '0';
wait for 30 ns;
assert q_out = '1' report "7 failed";
wait for 20 ns;
j <= '1';
k <= '0';
wait for 30 ns;
assert q_out = '1' report "8 failed";
wait for 20 ns;
j <= '1';
k <= '1';
wait for 30 ns;
assert q_out = '0' report "9 failed";
wait for 20 ns;
j <= '1';
k <= '0';
wait for 30 ns;
assert q_out = '1' report "10 failed";
wait for 20 ns;
j <= '0';
k <= '1';
wait for 30 ns;
assert q_out = '0' report "11 failed";
wait for 20 ns;
j <= '0';
k <= '0';
wait for 30 ns;
assert q_out = '0' report "12 failed";
wait;
end process;
end tb_jkff; | mit | 2933222636ea8cd33d5129eab8393ed1 | 0.454509 | 3.421488 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/TB_SREG_4.vhd | 1 | 2,682 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:59 03/16/2014
-- Design Name:
-- Module Name: TB_SREG_4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_SREG_4 is
end TB_SREG_4;
architecture Behavioral of TB_SREG_4 is
component SREG_4 is
generic(
REG_WIDTH: integer:=2 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
SR_WE : in std_logic;
RESETN : in std_logic;
--Shadow Register
SR_SEL : in std_logic_vector(REG_WIDTH-1 downto 0);
SR_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
SR_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT REG_WIDTH:integer:=2;
signal CLOCK : STD_LOGIC := '0';
signal SR_WE : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal SR_SEL : std_logic_vector(REG_WIDTH-1 downto 0);
signal SR_OUT : std_logic_vector(DATA_WIDTH-1 downto 0);
signal SR_IN : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: SREG_4 port map(
CLOCK => Clock,
SR_WE => SR_WE,
RESETN => RESETN,
SR_SEL => SR_SEL,
SR_OUT => SR_OUT,
SR_IN => SR_IN
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
SR_SEL <= "00";
--Reset disable
RESETN <= '1'; wait for 2*period;
--Write to each Register(4)
SR_IN <= x"FFFFF0";
wait for 2*period;
SR_WE <= '1'; wait for 2*period;
SR_WE <= '0'; wait for 2*period;
SR_IN <= x"FFFF0F";
SR_SEL <= "01";
SR_WE <= '1'; wait for 2*period;
SR_WE <= '0'; wait for 2*period;
SR_IN <= x"FFF0FF";
SR_SEL <= "10";
SR_WE <= '1'; wait for 2*period;
SR_WE <= '0'; wait for 2*period;
SR_IN <= x"FF0FFF";
SR_SEL <= "11";
SR_WE <= '1'; wait for 2*period;
SR_WE <= '0'; wait for 2*period;
--Read from each register
SR_SEL <= "00"; wait for 2*period;
SR_SEL <= "01"; wait for 2*period;
SR_SEL <= "10"; wait for 2*period;
SR_SEL <= "11"; wait for 2*period;
end process;
end Behavioral;
| mit | 0fb116adcf4ca52db52741ad12ea75ee | 0.578673 | 2.808377 | false | false | false | false |
aleksandar-mitrevski/hw_sw | filtered_edge_detector/filter_edge_detector_testbench.vhd | 1 | 1,595 | library IEEE;
use IEEE.std_logic_1164.All;
entity filtered_edge_detector_testbench is end filtered_edge_detector_testbench;
architecture tb_filtered_edge_detector of filtered_edge_detector_testbench is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal level : std_logic := '0';
signal levelFiltered : std_logic := '0';
signal tick : std_logic;
constant twenty_five_nsec : time := 25 ns;
component FilteredEdgeDetector port (
clk : in std_logic;
reset : in std_logic;
level : in std_logic;
levelFiltered : inout std_logic;
tick : out std_logic);
end component FilteredEdgeDetector;
begin
FilteredEdgeDetector1 : FilteredEdgeDetector
port map (
clk => clk,
reset => reset,
level => level,
levelFiltered => levelFiltered,
tick => tick);
create_twenty_Mhz: process
begin
wait for twenty_five_nsec;
clk <= NOT clk;
end process;
level <= '1' after 20 ns,
'0' after 40 ns,
'1' after 100 ns,
'0' after 210 ns,
'1' after 225 ns,
'0' after 300 ns,
'1' after 500 ns,
'0' after 520 ns,
'1' after 540 ns,
'0' after 700 ns,
'1' after 730 ns,
'0' after 740 ns,
'1' after 900 ns,
'0' after 1100 ns,
'1' after 1300 ns,
'0' after 1340 ns,
'1' after 1350 ns,
'0' after 1500 ns;
end tb_filtered_edge_detector; | mit | a34dcd6658ef36a36e357ad195a39fb8 | 0.541066 | 3.918919 | false | true | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/ipcore_dir/clock_new.vhd | 1 | 3,099 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : clock_new.vhd
-- /___/ /\ Timestamp : 11/29/2015 17:47:16
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st C:\Users\Bailey\Desktop\Nibble_Knowledge_CPU(1)\ipcore_dir\.\clock_new.xaw C:\Users\Bailey\Desktop\Nibble_Knowledge_CPU(1)\ipcore_dir\.\clock_new
--Design Name: clock_new
--Device: xc3s250e-vq100-4
--
-- Module clock_new
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.05 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 9.54 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clock_new is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end clock_new;
architecture BEHAVIORAL of clock_new is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
| unlicense | 2c2f322830d76567d4995a0b2789ea5d | 0.4808 | 3.706938 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/TB_RAM_8x24.vhd | 1 | 2,500 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:59 03/16/2014
-- Design Name:
-- Module Name: TB_DUAL_RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_RAM_8x24 is
end TB_RAM_8x24;
architecture Behavioral of TB_RAM_8x24 is
component RAM_8x24 is
generic(
RAM_WIDTH: integer:=8; -- 00 - FF choice
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--RESETN : in std_logic;
--OUTPUT RAM
OUT_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
OUT_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
--INPUT RAM
IN_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
IN_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT RAM_WIDTH:integer:=8;
signal CLOCK : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal IN_ADDR : std_logic_vector(RAM_WIDTH-1 downto 0);
signal IN_DATA : std_logic_vector(DATA_WIDTH-1 downto 0);
signal OUT_ADDR : std_logic_vector(RAM_WIDTH-1 downto 0);
signal OUT_DATA : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: RAM_8x24 port map(
CLOCK => Clock,
WE => WE,
IN_ADDR => IN_ADDR,
IN_DATA => IN_DATA,
OUT_ADDR => OUT_ADDR,
OUT_DATA => OUT_DATA
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
IN_ADDR <= (others => '0');
OUT_ADDR <= (others => '0');
IN_DATA <= x"FFFFFF";wait for 2*period;
--Enabling the register
WE <= '1'; wait for 2*period;
WE <= '0';
IN_ADDR <= x"01";
WE <= '1'; wait for 2*period;
WE <= '0';
IN_DATA <= x"333333"; wait for 50*period;
IN_ADDR <= x"01";
WE <= '1'; wait for 2*period;
WE <= '0';
OUT_ADDR <= X"01"; wait for 2*period;
OUT_ADDR <= X"02";
end process;
end Behavioral;
| mit | 1bafda27d5f916b51e36c4069ecf04a7 | 0.5788 | 2.890173 | false | false | false | false |
dtysky/Led_Array | VHDL_TEST/IMG1.vhd | 1 | 6,147 | -- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: IMG1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY IMG1 IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END IMG1;
ARCHITECTURE SYN OF img1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (39 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(39 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "./ROM/IMG1.mif",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 7,
width_a => 40,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "./ROM/IMG1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "40"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "./ROM/IMG1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 40 0 @q_a 0 0 40 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL IMG1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 0a2556c88049d36118dc9866e0b7f785 | 0.666667 | 3.530729 | false | false | false | false |
NuclearKev/iir-hardware | mux.vhd | 1 | 2,056 | --------------------------------------------------------------------------------
-- Copyright (C) 2017 Kevin Bloom <kdb5pct.edu>
--
-- This program is free software: you can redistribute it and/or modify it under
-- the terms of the Lesser GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option) any
-- later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the Lesser GNU General Public License for more
-- details.
--
-- You should have received a copy of the Lesser GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description:
--
-- This IP was created as a part of the IIR Hardware project. It will send an
-- input to the output based on the select.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux is
Port ( i_select : in STD_LOGIC_VECTOR (7 downto 0);
i_0 : in STD_LOGIC_VECTOR (11 downto 0);
i_1 : in STD_LOGIC_VECTOR (11 downto 0);
i_2 : in STD_LOGIC_VECTOR (11 downto 0);
i_3 : in STD_LOGIC_VECTOR (11 downto 0);
i_4 : in STD_LOGIC_VECTOR (11 downto 0);
i_5 : in STD_LOGIC_VECTOR (11 downto 0);
o : out STD_LOGIC_VECTOR (11 downto 0));
end mux;
architecture Behavioral of mux is
begin
p_dmux : process (i_select)
begin
case i_select is
when x"00" =>
o <= i_0;
when x"01" =>
o <= i_1;
when x"02" =>
o <= i_2;
when x"03" =>
o <= i_3;
when others =>
-- do nothing
end case;
end process;
end Behavioral;
| lgpl-3.0 | 1628f9adce1c7636c924615815f5fb95 | 0.521887 | 4.230453 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/RegisterBank/RegisterBank_TB.vhd | 1 | 3,891 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: REGBank_TB
-- Project Name: REGBank
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Register Bank Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY RegBank_tb IS
GENERIC (DATA_WIDTH:positive:=16; REG_SIZE:positive:=4);
END RegBank_tb;
ARCHITECTURE behavior OF RegBank_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RegBank
GENERIC (DATA_WIDTH:positive:=16; REG_SIZE:positive:=4);
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
-- Register A
RegA_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegA : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Register B
RegB_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegB : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Input Register
RegIN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
RegIN_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegIN_WE : in STD_LOGIC
);
END COMPONENT;
--Inputs
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
-- Register A
SIGNAL RegA_Sel : STD_LOGIC_VECTOR (REG_SIZE-1 downto 0):= (others=>'0');
SIGNAL RegA : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0):= (others=>'0');
-- Register B
SIGNAL RegB_Sel : STD_LOGIC_VECTOR (REG_SIZE-1 downto 0):= (others=>'0');
SIGNAL RegB : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0):= (others=>'0');
-- Input Register
SIGNAL RegIN : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0):= (others=>'0');
SIGNAL RegIN_Sel : STD_LOGIC_VECTOR (REG_SIZE-1 downto 0):= (others=>'0');
SIGNAL RegIN_WE : STD_LOGIC:= '0';
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: REGBank PORT MAP( CLK => CLK,
RST => RST,
RegA_Sel => RegA_Sel,
RegA => RegA,
RegB_Sel => RegB_Sel,
RegB => RegB,
RegIN => RegIN,
RegIN_Sel => RegIN_Sel,
RegIN_WE => RegIN_WE);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
RST <= '1';
wait for 2*period;
RST <= '0';
wait for 100 ns;
report "Start Register Bank Test Bench" severity NOTE;
--Test Read
RegA_Sel <= X"0"; -- 0
RegB_Sel <= X"0"; -- 0
wait for 2*period;
RegB_Sel <= X"1"; -- 0
wait for 2*period;
RegB_Sel <= X"F"; -- 0
wait for 2*period;
RegIN <= (OTHERS => '1');
RegIN_Sel <= X"F"; -- 0
RegIN_WE <= '1';
wait for 2*period;
RegIN_WE <= '0';
-- END Reg Test --
report "Finish Register Bank Test Bench" severity NOTE;
wait; -- will wait forever
END PROCESS;
END;
| mit | 0a85505ba0acf43532a53bbdd37e6f87 | 0.493446 | 3.871642 | false | true | false | false |
Reiuiji/VHDL-Emporium | VHDL/Program_Counter.vhd | 1 | 888 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
GENERIC(
COUNT_WIDTH:INTEGER := 24--;
--MEM_LIMIT:INTEGER := 8* 256 -- 256 Bytes
);
Port (
CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
PROGRAM_COUNTER : out STD_LOGIC_VECTOR (COUNT_WIDTH-1 downto 0)
);
end counter;
architecture Behavioral of counter is
signal PC : std_logic_vector(COUNT_WIDTH-1 downto 0):= (others => '0'); --<= (others <= "0"); -- Program Counter
begin
process (CLOCK, RESET)
begin
if (RESET = '1') then
PC <= (OTHERS => '0');
elsif CLOCK = '0' and CLOCK'event then
if ENABLE = '1' then
if PC = x"FF" then --MEM_LIMIT) then
PC <= (OTHERS => '0');
else
PC <= PC + 1;
end if;
end if;
end if;
end process;
PROGRAM_COUNTER <= PC;
end Behavioral;
| mit | d7b036d5902fd4c2039823f41e3ebbc4 | 0.612613 | 2.801262 | false | false | false | false |
dtysky/Led_Array | VHDL_TEST/LED.vhd | 1 | 8,204 | --A program for testing.
--copyright(c) 2014 dtysky
--This program is free software; you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation; either version 2 of the License, or
--(at your option) any later version.
--This program is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License along
--with this program; if not, write to the Free Software Foundation, Inc.,
--51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
------------------------------------------------------------------------
--实现方案：
--由于FIFO输入和输出只能为偶数倍关系，输入又必为32或16bits，所以最后将其调整：
--设立三类FIFO，其中后两类为普通的图片双缓存，第一类为转换
--写入时就按16bits写入！（为了满足要求，由于每一个模块总数据为120*38=4560=285*16），充分利用DM（数据掩码），将RAM作为先后两个RAM对待！
--写入时，一次写入856个16bits数据，丢掉最后一个
--写入时，分为两个1024*16bits的usb数据包，第一个包拥有500*16bits的有效图像数据，第二个有356*16bits，最后一个为随便数据
--读出时，按照16bits读出！顺序写入一个第一类FIFO
--读出时，每张图片第一块总突发次数为125，第二块总突发次数为89（最后一个16bits扔掉）
--第一类FIFO为16bits输入，16bits输出；二三类FIFO为80bits输入，40bis输出
--第一类FIFO和二三类之间插入一个80bits信号做缓存（80=16*5=80*1）
--经计算，每10us需更新一次图片，用此方法，保证FIFO数据流跑到240M（DDR2数据流速度），一次更新只需不到2us，满足要求
--所有输出到RAM的信号初值为0
--再锁定尚待加入
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity LED is
generic
(
constant r20_con:integer:=2047; ------------20r/s时每一度间隔计数（clk_contorl下）
constant opic_con:integer:=1023; ------------刷一张图片一遍计数
constant unlock_con:integer:=4095 ------------解锁计数
);
port
(
inclk:in std_logic;
data_buffer_a:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_b:out std_logic_vector(39 downto 0):=x"0000000000";
data_buffer_c:out std_logic_vector(39 downto 0):=x"0000000000";
en_row_a:out std_logic:='0';
en_row_b:out std_logic:='0';
en_row_c:out std_logic_vector(1 downto 0):="00"; --------分割为两个管脚，分配同一信号
en_col_a_1,en_col_a_2,en_col_a_3:out std_logic:='0';
en_col_b_1,en_col_b_2,en_col_b_3:out std_logic:='0';
en_col_c_1,en_col_c_2,en_col_c_3:out std_logic:='0'
);
end entity;
architecture ledx of LED is
component PLL is
port
(
inclk0:in std_logic;
locked:out std_logic;
c0:out std_logic
);
end component;
component IMG1 is
port
(
clock:in std_logic;
address:in std_logic_vector(6 downto 0);
q:out std_logic_vector(39 downto 0)
);
end component;
component IMG2 is
port
(
clock:in std_logic;
address:in std_logic_vector(6 downto 0);
q:out std_logic_vector(39 downto 0)
);
end component;
component IMG3 is
port
(
clock:in std_logic;
address:in std_logic_vector(6 downto 0);
q:out std_logic_vector(39 downto 0)
);
end component;
-------------------图片行-----------------
signal pic_row_ab:bit_vector(37 downto 0):="01111111111111111111111111111111111111";
signal pic_row_c_h:bit_vector(37 downto 0):="01111111111111111111111111111111111111";
signal pic_row_c_l:bit_vector(37 downto 0):="11111111111111111101111111111111111111";
------------------测试用ROM---------------
signal rom_addr:std_logic_vector(6 downto 0):="0000000";
signal rom_clk:std_logic:='0';
signal rom_data1,rom_data2,rom_data3:std_logic_vector(39 downto 0);
--signal test:bit_vector(39 downto 0):=x"0000000001";
signal test_a:bit_vector(39 downto 0):=x"FF00000000";
signal test_b:bit_vector(39 downto 0):=x"0000FF0000";
signal test_c:bit_vector(39 downto 0):=x"00000000FF";
signal clk_self:std_logic;
signal pll_lock:std_logic;
begin
PLLX:PLL
port map
(
inclk0=>inclk,
c0=>clk_self,
locked=>pll_lock
);
ROM1:IMG1
port map
(
clock=>rom_clk,
address=>rom_addr,
q=>rom_data1
);
ROM2:IMG2
port map
(
clock=>rom_clk,
address=>rom_addr,
q=>rom_data2
);
ROM3:IMG3
port map
(
clock=>rom_clk,
address=>rom_addr,
q=>rom_data3
);
CONTROL:process(clk_self,pll_lock)
variable con_control_work:integer range 0 to 63:=0;
begin
if clk_self'event and clk_self='1' and pll_lock='1' then
case con_control_work is
when 50 =>
con_control_work:=0;
when others =>
con_control_work:=con_control_work+1;
end case;
case con_control_work is
when 0 =>
data_buffer_a<=x"0000000000";
data_buffer_b<=x"0000000000";
data_buffer_c<=x"0000000000";
en_row_a<='0';
en_row_b<='0';
en_row_c<="00";
when 1=>
en_col_a_1<='1';
en_col_b_1<='1';
en_col_c_1<='1';
when 2 =>
en_col_a_2<='1';
en_col_b_2<='1';
en_col_c_2<='1';
when 3 =>
en_col_a_3<='1';
en_col_b_3<='1';
en_col_c_3<='1';
when 4 =>
en_col_a_1<='0';
en_col_b_1<='0';
en_col_c_1<='0';
en_col_a_2<='0';
en_col_b_2<='0';
en_col_c_2<='0';
en_col_a_3<='0';
en_col_b_3<='0';
en_col_c_3<='0';
when 5 =>
data_buffer_a<=x"FFFFFFFFFF";
when 6 =>
en_row_a<='1';
when 7 =>
en_row_b<='1';
when 8 =>
data_buffer_c<=x"FFFFFFFFFF";
when 9 =>
en_row_c<="11";
when 10 =>
en_row_a<='0';
en_row_b<='0';
en_row_c<="00";
when 12 =>
data_buffer_a<=x"0000000000";
data_buffer_c<=x"0000000000";
when 15 =>
rom_clk<='1';
when 16 =>
rom_clk<='0';
rom_addr<=rom_addr+1;
when 17 =>
data_buffer_a<=rom_data1;
when 18 =>
data_buffer_b<=rom_data2;
when 19 =>
data_buffer_c<=rom_data3;
when 20 =>
-- en_col_a_1<='1';
-- en_col_b_1<='1';
-- en_col_c_1<='1';
en_col_a_3<='1';
en_col_b_3<='1';
en_col_c_3<='1';
when 21 =>
rom_clk<='1';
when 22 =>
rom_clk<='0';
rom_addr<=rom_addr+1;
when 23 =>
data_buffer_a<=rom_data1;
when 24 =>
data_buffer_b<=rom_data2;
when 25 =>
data_buffer_c<=rom_data3;
when 26 =>
-- en_col_a_2<='1';
-- en_col_b_2<='1';
-- en_col_c_2<='1';
en_col_a_1<='1';
en_col_b_1<='1';
en_col_c_1<='1';
when 27 =>
rom_clk<='1';
when 28 =>
rom_clk<='0';
if rom_addr=113 then
rom_addr<="0000000";
else
rom_addr<=rom_addr+1;
end if;
when 29 =>
data_buffer_a<=rom_data1;
when 30 =>
data_buffer_b<=rom_data2;
when 31 =>
data_buffer_c<=rom_data3;
when 32 =>
-- en_col_a_3<='1';
-- en_col_b_3<='1';
-- en_col_c_3<='1';
en_col_a_2<='1';
en_col_b_2<='1';
en_col_c_2<='1';
when 33 =>
data_buffer_a(39 downto 2)<=to_stdlogicvector(pic_row_ab);
when 34=>
en_row_a<='1';
when 35=>
en_row_b<='1';
when 36 =>
if pic_row_c_h(37)='0' then
data_buffer_c(19 downto 1)<="0111111111111111111";
elsif pic_row_c_h(18)='0' then
data_buffer_c(19 downto 1)<="1111111111111111111";
else
data_buffer_c(19 downto 1)<=to_stdlogicvector(pic_row_c_h(18 downto 0));
end if;
if pic_row_c_l(0)='0' then
data_buffer_c(38 downto 20)<="1111111111111111110";
else
data_buffer_c(38 downto 20)<=to_stdlogicvector(pic_row_c_l(37 downto 19));
end if;
when 37 =>
en_row_c<="11";
when 50 =>
pic_row_ab<=pic_row_ab rol 1;
pic_row_c_h<=pic_row_c_h rol 1;
pic_row_c_l<=pic_row_c_l ror 1;
--test<=test rol 1;
--test<= not test;
when others =>
null;
end case;
end if;
end process;
end ledx; | gpl-2.0 | 9d2b41f5ad86f4341edc01084c07ea3e | 0.60067 | 2.326887 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/test/24bit_Register_tb_Hold_latch.vhd | 1 | 2,582 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE ieee.numeric_std.ALL;
USE work.UMDRISC_pkg.ALL;
entity RegR_LATCH_tb is
end RegR_LATCH_tb;
architecture Behavioral of RegR_LATCH_tb is
component RegR_LATCH is
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
HOLD_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end component;
signal CLOCK : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal ENABLE : STD_LOGIC := '0';
signal D : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q2 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q3 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q4 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
--DEBUG TO SEE THE OUTPUT OF HOLD
signal H : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal H2 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal H3 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal H4 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
constant period : time := 10 ns;
begin
-- Register 1
Reg1: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => D,
HOLD_OUT => H,
OUTPUT => Q
);
-- Register 2
Reg2: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => Q,
HOLD_OUT => H2,
OUTPUT => Q2
);
-- Register 3
Reg3: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => Q2,
HOLD_OUT => H3,
OUTPUT => Q3
);
-- Register 4
Reg4: RegR_LATCH port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
INPUT => Q3,
HOLD_OUT => H4,
OUTPUT => Q4
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
--Reset disable
RESETN <= '1'; wait for period;
assert (Q = 00) report "Failed READ. [OUT_Port0]=" & integer'image(to_integer(unsigned(Q))) severity ERROR;
D <= x"FFFFFF";
--Enabling the register
ENABLE <= '1'; wait for 2*period;
-- Test each input via loop
for i in 0 to 256 loop
D <= std_logic_vector(to_signed(i,D'length)); wait for 2*period;
end loop;
end process;
end Behavioral;
| mit | 3067b3ebd6bef634e2d720a8aefc7a12 | 0.627808 | 2.779333 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Control Flow/TB_MUX_2to1.vhd | 1 | 1,066 | library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_MUX_2to1 is
end TB_MUX_2to1;
architecture Behavioral of TB_MUX_2to1 is
component MUX_2to1 is
Port (
SEL : in STD_LOGIC; -- 2 bits
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal SEL : STD_LOGIC;
signal IN_1,IN_2 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal OUTPUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 2 TO 1 MUX
MUX1: MUX_2to1 port map(
SEL => SEL,
IN_1 => IN_1,
IN_2 => IN_2,
output => output
);
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
--Set up the four inputs
IN_1 <= x"111111";
IN_2 <= x"222222";
--Test the Select for each input
SEL <= '0'; wait for 2*period;
SEL <= '1'; wait for 2*period;
end process;
end Behavioral;
| mit | 2d461da7bf00323f4b481abb99e70654 | 0.643527 | 2.645161 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/Inst_Memory.vhd | 1 | 4,824 | ------------------------------------------------------------
-- implemented the 8 Byte X 24 byte memory
--
-- Instruction memory on it is the following:
--
-- ADDI R0, 2 ; ADDI R0<-2 500002
-- ADDI R1, 1 ; ADDI R1<-1 510001
-- ADD R0, R1 ; ADD R0<-R0 + R1 001000
-- AND R0, R1 ; AND R0<-R0 & R1 201000
-- OR R0, R1 ; OR R0<-R0 or R1 301000
-- ADD R0, R1 ; ADD R0<-R0 + R1 001000
-- MOV R5, R0 ; R5 <- R0 450000
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity RAM_8x24 is
generic(
RAM_WIDTH: integer:=8; -- 00 - FF choice
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--OUTPUT RAM
OUT_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
OUT_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
--INPUT RAM
IN_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
IN_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end RAM_8x24;
architecture RAM_ARCH of RAM_8x24 is
type ram_type is array (0 to 2**RAM_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM : ram_type := (
x"500002", x"510001", x"001000", x"201000", x"301000", x"001000", x"450000", x"000000", -- 00 - 07
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 08 - 0F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 10 - 17
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 18 - 1F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 20 - 27
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 28 - 2F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 30 - 37
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 38 - 3F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 40 - 47
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 48 - 4F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 50 - 57
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 58 - 5F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 60 - 67
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 68 - 6F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 70 - 77
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 78 - 7F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 80 - 87
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 88 - 8F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 90 - 97
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 98 - 9F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A0 - A7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A8 - AF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B0 - B7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B8 - BF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C0 - C7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C8 - CF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D0 - D7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D8 - DF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E0 - E7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E8 - EF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- F0 - F7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000" -- F8 - FF
);
signal ADDR_IN: std_logic_vector(RAM_WIDTH-1 downto 0);
begin
process(CLOCK,WE)
begin
if (CLOCK'event and CLOCK = '0') then
if (WE = '1') then
RAM(to_integer(unsigned(IN_ADDR))) <= IN_DATA;
end if;
ADDR_IN <= OUT_ADDR;
end if;
end process;
OUT_DATA <= RAM(to_integer(unsigned(ADDR_IN)));
end RAM_ARCH;
| mit | 903868e2c55130a2c0b16dc9a8296d46 | 0.580224 | 2.637507 | false | false | false | false |
aleksandar-mitrevski/hw_sw | explorer/explorer.vhd | 1 | 1,085 | library ieee;
use ieee.std_logic_1164.all;
use work.exploration_pkg.all;
entity Explorer is port (
currentCell : in integer;
currentOrientation : in real;
currentCellsInView : in gridArray;
numberOfNuggetsToCollect : in integer;
next_goal : out integer);
end Explorer;
architecture explorer of Explorer is
component ExplorationGrid
port(currentCellsInView: in gridArray;
grid : out gridArray);
end component;
signal currentCellsinView : gridArray;
signal grid : gridArray;
begin
componentMap : ExplorationGrid port map (currentCellsInView => currentCellsInView, grid => grid);
process(numberOfNuggetsToCollect)
variable mapExplored : std_logic := '0';
begin
mapExplored := isGridExplored(grid, numberOfNuggetsToCollect);
if mapExplored = '1' then
next_goal <= -1;
else
if numberOfNuggetsToCollect = 0 then
next_goal <= calculateCosts(currentCell, currentOrientation, grid);
end if;
end if;
end process;
end explorer; | mit | e1eabce17cd5f549760de18dded1bbde | 0.671889 | 3.847518 | false | false | false | false |
aleksandar-mitrevski/hw_sw | up_down_counter/upDownCounter.vhd | 1 | 2,366 | ------------------------------------------------------
-- A simple up/down counter in the [0,4] range
-- whose direction is controlled by an input switch;
-- the value of the counter is displayed by four LEDs
--
-- Author: Aleksandar Mitrevski
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
entity upDownCounter is
Port (clk: in STD_LOGIC;
inputSwitch : in STD_LOGIC;
led0 : out STD_LOGIC;
led1 : out STD_LOGIC;
led2 : out STD_LOGIC;
led3 : out STD_LOGIC;
counter : inout integer range 0 to 4;
clockCounter : inout integer range 0 to 50000000);
end upDownCounter;
architecture Behavioral of upDownCounter is
Signal ledArrayValues : std_logic_vector(0 to 3);
begin
counterUpdate: Process(clk, clockCounter, counter, ledArrayValues)
begin
if (rising_edge(clk)) then
if clockCounter = 50000000 then
clockCounter <= 0;
if inputSwitch = '1' then
if counter = 0 then
counter <= 4;
ledArrayValues <= "1111";
else
if counter = 1 then
ledArrayValues <= "0000";
elsif counter = 2 then
ledArrayValues <= "1000";
elsif counter = 3 then
ledArrayValues <= "1100";
else
ledArrayValues <= "1110";
end if;
counter <= counter - 1;
end if;
else
if counter = 4 then
counter <= 0;
ledArrayValues <= "0000";
else
if counter = 0 then
ledArrayValues <= "1000";
elsif counter = 1 then
ledArrayValues <= "1100";
elsif counter = 2 then
ledArrayValues <= "1110";
else
ledArrayValues <= "1111";
end if;
counter <= counter + 1;
end if;
end if;
else
clockCounter <= clockCounter + 1;
end if;
end if;
end Process;
led0 <= ledArrayValues(0);
led1 <= ledArrayValues(1);
led2 <= ledArrayValues(2);
led3 <= ledArrayValues(3);
end Behavioral; | mit | 8c38e682c79027526c631cb9641d49ca | 0.484784 | 4.713147 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/test/24bit_Register_tb.vhd | 1 | 2,095 | library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity Reg24_tb is
end Reg24_tb;
architecture Behavioral of Reg24_tb is
component Reg24 is
GENERIC(
DATA_WIDTH:INTEGER := 24
);
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end component;
signal CLOCK : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal ENABLE : STD_LOGIC := '0';
signal D : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q2 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q3 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
signal Q4 : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
constant period : time := 10 ns;
begin
-- Register 1
Reg1: Reg24 port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
D => D,
Q => Q
);
-- Register 2
Reg2: Reg24 port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
D => Q,
Q => Q2
);
-- Register 3
Reg3: Reg24 port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
D => Q2,
Q => Q3
);
-- Register 4
Reg4: Reg24 port map(
CLOCK => Clock,
RESETN => Resetn,
ENABLE => ENABLE,
D => Q3,
Q => Q4
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
--Reset disable
RESETN <= '1'; wait for period;
assert (Q = 00) report "Failed READ. [OUT_Port0]=" & integer'image(to_integer(unsigned(Q))) severity ERROR;
D <= x"FFFFFF";
--Enabling the register
ENABLE <= '1'; wait for 2*period;
-- Test each input via loop
for i in 0 to 256 loop
D <= std_logic_vector(to_signed(i,D'length)); wait for 2*period;
end loop;
end process;
end Behavioral;
| mit | 38a9925892ab981b697ef1c9a2453b3e | 0.619093 | 2.756579 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/io_mapping.vhd | 1 | 4,797 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:13:34 11/16/2015
-- Design Name:
-- Module Name: io_mapping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity io_mapping is
Port ( address : in STD_LOGIC_VECTOR (15 downto 0);
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
ram_data : inout STD_LOGIC_VECTOR (3 downto 0);
bus_chip_select : out STD_LOGIC_VECTOR (3 downto 0); -- The chip select lines from the bus
store : in STD_LOGIC;
bus_data : inout STD_LOGIC_VECTOR (3 downto 0); -- The data lines from the bus
bus_ready : in STD_LOGIC; --Ready from the bus
oe : out STD_LOGIC;
bus_status_out : out STD_LOGIC_VECTOR(1 downto 0);
bus_parity : in STD_LOGIC; --Parity from the bus
clk : in STD_LOGIC;
rst : in STD_LOGIC;
read_mode : in STD_LOGIC
);
end io_mapping;
architecture Behavioral of io_mapping is
component Reg is
Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end component;
component io_decode is
Port ( select_line : in STD_LOGIC_VECTOR (1 downto 0);
en : in STD_LOGIC;
data : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal i_data_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_NOR_result : STD_LOGIC;
signal i_reg_data_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_data_out : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_data_en : STD_LOGIC;
signal i_data_bus : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_status_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_status_out : STD_LOGIC_VECTOR(3 downto 0);
--signal i_reg_status_en : STD_LOGIC_VECTOR;
signal i_reg_cs_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_reg_cs_out : STD_LOGIC_VECTOR(3 downto 0);
--signal i_reg_cs_en : STD_LOGIC_VECTOR;
signal i_select : STD_LOGIC_VECTOR(1 downto 0);
signal i_decode_en : STD_LOGIC;
signal i_reg_enables : STD_LOGIC_VECTOR(3 downto 0);
signal i_rst_or : STD_LOGIC;
begin
DECODE: io_decode
port map( select_line => i_select,
en => i_decode_en,
data => i_reg_enables);
REG_DATA: Reg
port map( data_in => i_reg_data_in,
data_out => i_reg_data_out,
enable => i_reg_data_en,
clk => clk,
rst => rst
);
REG_STATUS: Reg
port map( data_in => i_reg_status_in,
data_out => i_reg_status_out,
enable => i_reg_enables(1),
clk => clk,
rst => rst
);
REG_CHIP_SELECT: Reg
port map( data_in => i_reg_cs_in,
data_out => i_reg_cs_out,
enable => i_reg_enables(0),
clk => clk,
rst => rst
);
i_NOR_result <= NOT(address(15) OR address(14) OR address(13) OR address(12)
OR address(11) OR address(10) OR address(9) OR address(8)
OR address(7) OR address(6) OR address(5) OR address(4)
OR address(3) OR address(2));
i_rst_or <= (NOT rst) AND i_NOR_result;
i_decode_en <= ((i_NOR_result AND store) AND (address(0) NAND address(1))) when rst = '0' else '1';
oe <= store;
i_select <= address(1 downto 0) when i_rst_or = '1' else "11";
--Register enable signals
i_reg_data_en <= read_mode OR i_reg_enables(2);
i_reg_status_out(1) <= bus_ready;
i_reg_status_out(0) <= bus_parity;
bus_status_out <= i_reg_status_out(3 downto 2);
--Register inputs and outputs
i_reg_data_in <= data_in when i_decode_en = '1' else i_data_bus;
i_reg_status_in <= data_in(3) & data_in(2) & bus_ready & bus_parity;
i_reg_cs_in <= data_in;
--Data selects
data_out <= ram_data when i_select = "11" else
i_reg_data_out when i_select = "10" else
i_reg_status_out(3 downto 2) & bus_ready & bus_parity when i_select = "01" else
i_reg_cs_out when i_select = "00";
--Tristates
i_data_bus <= "ZZZZ" when read_mode = '0' else bus_data;
bus_data <= "ZZZZ" when read_mode = '1' else i_reg_data_out;
bus_chip_select <= i_reg_cs_out;
ram_data <= data_in when store = '1' else "ZZZZ";
end Behavioral;
| unlicense | 58da9f4f51f2c34404cd2709d5a4b08e | 0.599124 | 3.07303 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Control Flow/TB_MUX_4to1.vhd | 1 | 1,373 | library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_MUX_4to1 is
end TB_MUX_4to1;
architecture Behavioral of TB_MUX_4to1 is
component MUX_4to1 is
Port (
SEL : in STD_LOGIC_VECTOR (1 downto 0); -- 4 bits
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_3 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_4 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal SEL : STD_LOGIC_VECTOR (1 downto 0);
signal IN_1,IN_2,IN_3,IN_4 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal OUTPUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 4 TO 1 MUX
MUX1: MUX_4to1 port map(
SEL => SEL,
IN_1 => IN_1,
IN_2 => IN_2,
IN_3 => IN_3,
IN_4 => IN_4,
output => output
);
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
--Set up the four inputs
IN_1 <= x"111111";
IN_2 <= x"222222";
IN_3 <= x"333333";
IN_4 <= x"444444";
--Test the Select for each input
SEL <= "00"; wait for 2*period;
SEL <= "01"; wait for 2*period;
SEL <= "10"; wait for 2*period;
SEL <= "11"; wait for 2*period;
end process;
end Behavioral;
| mit | 692a803fe0a1a1052b77ce5a8ad20735 | 0.629279 | 2.566355 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/ipcore_dir/hw_multiplier.vhd | 1 | 4,208 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file hw_multiplier.vhd when simulating
-- the core, hw_multiplier. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY hw_multiplier IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END hw_multiplier;
ARCHITECTURE hw_multiplier_a OF hw_multiplier IS
-- synthesis translate_off
COMPONENT wrapped_hw_multiplier
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_hw_multiplier USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 32,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 32,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 1,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 63,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_hw_multiplier
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END hw_multiplier_a;
| mit | 519d8c4a9a9ae6e9bd7afcbeb342acc8 | 0.539449 | 4.629263 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/dcm0.vhd | 1 | 5,883 | -- file: dcm0.vhd
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 200.000 0.000 N/A 217.125 N/A
-- CLK_OUT2 50.000 0.000 N/A 207.125 N/A
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 48.000 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm0 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic;
CLK_VALID : out std_logic
);
end dcm0;
architecture xilinx of dcm0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm0,clk_wiz_v1_4,{component_name=dcm0,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,diff_ext_feedback=false,primtype_sel=DCM_CLKGEN,num_out_clk=2,clkin1_period=20.83333,clkin2_period=20.83333,use_power_down=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfx : std_logic;
signal clkfx180_unused : std_logic;
signal clkfxdv : std_logic;
signal clkfbout : std_logic;
-- Dynamic programming unused signals
signal progdone_unused : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(2 downto 1);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_clkgen_inst: DCM_CLKGEN
generic map
(CLKFXDV_DIVIDE => 4,
CLKFX_DIVIDE => 6,
CLKFX_MULTIPLY => 25,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000)
port map
-- Input clock
(CLKIN => clkin1,
-- Output clocks
CLKFX => clkfx,
CLKFX180 => clkfx180_unused,
CLKFXDV => clkfxdv,
-- Ports for dynamic phase shift
PROGCLK => '0',
PROGEN => '0',
PROGDATA => '0',
PROGDONE => progdone_unused,
-- Other control and status signals
FREEZEDCM => '0',
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET);
LOCKED <= locked_internal;
CLK_VALID <= ( locked_internal and ( not status_internal(2) ) );
-- Output buffering
-------------------------------------
clkout1_buf : AUTOBUF
generic map
(BUFFER_TYPE => "BUFG")
port map
(O => CLK_OUT1,
I => clkfx);
clkout2_buf : AUTOBUF
generic map
(BUFFER_TYPE => "BUFG")
port map
(O => CLK_OUT2,
I => clkfxdv);
end xilinx;
| gpl-3.0 | e29ed7b9de7e559cdb64b66c8bbaf8d4 | 0.577087 | 4.294161 | false | false | false | false |
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