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Reiuiji/VHDL-Emporium | VHDL/Registers/Reg_Falling.vhd | 1 | 1,657 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: RegF
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
-- 24 bit register
--
-- Notes:
-- Clock on FALLING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the FALLING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegF IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END RegF;
ARCHITECTURE Behavior OF RegF IS
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '0' THEN
OUTPUT <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 0b3719514e5dcbc02415358a933ada2d | 0.52927 | 3.657837 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/Reg_Rising.vhd | 1 | 1,639 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: RegF
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
--
-- Notes:
-- Clocked on RISING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the rising
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the RISING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegR IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END RegR;
ARCHITECTURE Behavior OF RegR IS
BEGIN
PROCESS(Resetn, Clock,ENABLE)
BEGIN
IF Resetn = '0' THEN
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 1262ea4e13631bf6fc64a11c1e984b86 | 0.530201 | 3.650334 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_cpu_with_io.vhd | 1 | 5,706 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:33:29 11/23/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/Desktop/Nibble_Knowledge_CPU(1)/tb_cpu_with_io.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: CPU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_cpu_with_io IS
END tb_cpu_with_io;
ARCHITECTURE behavior OF tb_cpu_with_io IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT CPU
PORT(
clk : IN std_logic;
reset : IN std_logic;
clk_out : OUT std_logic;
a_data : OUT std_logic_vector(3 downto 0);
ram_data : INOUT std_logic_vector(3 downto 0);
ram_address : OUT std_logic_vector(15 downto 0);
ram_write_enable : OUT std_logic;
bus_ready : IN std_logic;
oe : OUT std_logic;
bus_parity : IN std_logic;
bus_status_out : OUT std_logic_vector(1 downto 0);
bus_data : INOUT std_logic_vector(3 downto 0);
bus_chip_select : OUT std_logic_vector(3 downto 0);
read_mode : IN STD_LOGIC_VECTOR
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal bus_ready : std_logic := '0';
signal bus_parity : std_logic := '0';
--BiDirs
signal ram_data : std_logic_vector(3 downto 0);
signal bus_data : std_logic_vector(3 downto 0);
--Outputs
signal clk_out : std_logic;
signal a_data : std_logic_vector(3 downto 0);
signal ram_address : std_logic_vector(15 downto 0);
signal ram_write_enable : std_logic;
signal oe : std_logic;
signal bus_status_out : std_logic_vector(1 downto 0);
signal bus_chip_select : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CPU PORT MAP (
clk => clk,
reset => reset,
clk_out => clk_out,
a_data => a_data,
ram_data => ram_data,
ram_address => ram_address,
ram_write_enable => ram_write_enable,
bus_ready => bus_ready,
oe => oe,
bus_parity => bus_parity,
bus_status_out => bus_status_out,
bus_data => bus_data,
bus_chip_select => bus_chip_select,
read_mode => read_mode
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '1';
wait for 1 ms;
reset <= '0';
-- insert stimulus here
ram_data <= "0001";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0010";
wait until rising_edge(clk_out);
ram_data <= "0110";
wait until rising_edge(clk_out);
--OP Cycle
--STR 0
ram_data <= "0010";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
-- exe cycle
ram_data <= "ZZZZ";
wait until rising_edge(clk_out);
L1 : loop
-- ADD 2 instruction
-- ADD 0x9
-- 0011 0000 0000 0000 1001
--OP cycle
ram_data <= "0001";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "1001";
wait until rising_edge(clk_out);
-- exe cycle
-- "0001" should be at mem location 0x0009
ram_data <= "0101";
wait until rising_edge(clk_out);
--OP Cycle
--STR 12
ram_data <= "0010";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "1100";
wait until rising_edge(clk_out);
-- exe cycle
ram_data <= "ZZZZ";
wait until rising_edge(clk_out);
--OP CYCLE
--JMP 1111
ram_data <= "0110";
-- address cycles
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "0000";
wait until rising_edge(clk_out);
ram_data <= "1111";
wait until rising_edge(clk_out);
--should store
wait until rising_edge(clk_out);
end loop;
wait;
end process;
END;
| unlicense | ab94bce12839f720c576407b2be7cb32 | 0.59341 | 3.302083 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/ipcore_dir/dpram_4_1_xc6.vhd | 1 | 6,049 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2012 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file dpram_4_1_xc6.vhd when simulating
-- the core, dpram_4_1_xc6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY dpram_4_1_xc6 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END dpram_4_1_xc6;
ARCHITECTURE dpram_4_1_xc6_a OF dpram_4_1_xc6 IS
-- synthesis translate_off
COMPONENT wrapped_dpram_4_1_xc6
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_dpram_4_1_xc6 USE ENTITY XilinxCoreLib.blk_mem_gen_v6_1(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 8,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 256,
c_read_depth_b => 1024,
c_read_width_a => 32,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 1,
c_use_byte_web => 1,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 4,
c_web_width => 1,
c_write_depth_a => 256,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_dpram_4_1_xc6
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END dpram_4_1_xc6_a;
| mit | 64b4d993a812a2c5b9988be5d036caab | 0.537114 | 3.794856 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/RAM_8x24_RW.vhd | 1 | 5,405 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: GenReg_16
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Handout Code: Dr.Fortier(c)
-- 16 General Purpose Registers
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Incorporated a memory init [1]
-- 0.03 - Implemented read/write based on one input
--
-- Additional Comments:
-- [1]: code adaptive from the following blog
-- http://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html
-- this site pointed to XST user guide
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity RAM_8x24RW is
generic(
RAM_WIDTH: integer:=8; -- 00 - FF choice
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
READ_WRITE : in std_logic; -- 0: read, 1: write
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
ADDR_IN : in std_logic_vector(RAM_WIDTH-1 downto 0);
--output
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end RAM_8x24RW;
architecture RAM_ARCH of RAM_8x24RW is
type ram_type is array (0 to 2**RAM_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM : ram_type := (
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 00 - 07
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 08 - 0F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 10 - 17
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 18 - 1F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 20 - 27
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 28 - 2F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 30 - 37
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 38 - 3F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 40 - 47
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 48 - 4F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 50 - 57
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 58 - 5F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 60 - 67
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 68 - 6F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 70 - 77
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 78 - 7F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 80 - 87
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 88 - 8F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 90 - 97
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 98 - 9F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A0 - A7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A8 - AF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B0 - B7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B8 - BF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C0 - C7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C8 - CF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D0 - D7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D8 - DF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E0 - E7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E8 - EF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- F0 - F7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000" -- F8 - FF
);
signal ADDR: std_logic_vector(RAM_WIDTH-1 downto 0);
begin
process(CLOCK,READ_WRITE)
begin
if (CLOCK'event and CLOCK = '0') then
if (READ_WRITE = '1') then --Write
RAM(to_integer(unsigned(ADDR_IN))) <= DATA_IN;
end if;
ADDR <= ADDR_IN;
end if;
end process;
DATA_OUT <= RAM(to_integer(unsigned(ADDR)));
end RAM_ARCH;
| mit | 8ce96b4c2cb8cf77c8dd62b155514d35 | 0.580759 | 2.856765 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Control Flow/TB_MUX_3to1.vhd | 1 | 1,337 | library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_MUX_3to1 is
end TB_MUX_3to1;
architecture Behavioral of TB_MUX_3to1 is
component MUX_3to1 is
Port (
SEL : in STD_LOGIC_VECTOR (1 downto 0); -- 3 bits
IN_1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
IN_3 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end component;
signal SEL : STD_LOGIC_VECTOR (1 downto 0);
signal IN_1,IN_2,IN_3 : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal OUTPUT : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 3 TO 1 MUX
MUX1: MUX_3to1 port map(
SEL => SEL,
IN_1 => IN_1,
IN_2 => IN_2,
IN_3 => IN_3,
output => output
);
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
--Set up the four inputs
IN_1 <= x"111111";
IN_2 <= x"222222";
IN_3 <= x"333333";
--Test the Select for each input
SEL <= "00"; wait for 2*period;
SEL <= "01"; wait for 2*period;
SEL <= "10"; wait for 2*period;
--incase you put 11 which does not exist, 0 will be outputed
SEL <= "11"; wait for 2*period;
end process;
end Behavioral;
| mit | 442d2d68ddf59bafcab2c3197fd04ac6 | 0.639491 | 2.642292 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/memoria/example_design/memoria_prod.vhd | 2 | 9,914 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: memoria_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : memoria.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 11264
-- C_READ_DEPTH_A : 11264
-- C_ADDRA_WIDTH : 14
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 11264
-- C_READ_DEPTH_B : 11264
-- C_ADDRB_WIDTH : 14
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY memoria_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END memoria_prod;
ARCHITECTURE xilinx OF memoria_prod IS
COMPONENT memoria_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : memoria_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | ea67954947ec5706e9563feec97d738d | 0.49536 | 3.841147 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/VGA Read - Write/scan_to_hex_tb.vhd | 1 | 3,771 | --------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron, Daniel Noyes
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Scan to Hex Testbench
-- Module Name: scan_to_hex_tb
-- Project Name: Risc Machine Project 1
-- Target Device: Spartan 3E Board
-- Tool versions: Xilinx 14.7
-- Description: This is the testbench for reading scancodes and changing them into hex.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY scan_to_hex_tb IS
END scan_to_hex_tb;
ARCHITECTURE behavior OF scan_to_hex_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT scan_to_hex
PORT(
Send : IN std_logic;
Resetn : IN std_logic;
scancode : IN std_logic_vector(7 downto 0);
output : OUT std_logic_vector(23 downto 0);
outCount : out STD_LOGIC_VECTOR (3 downto 0);
hexdebug : out STD_LOGIC_VECTOR (3 downto 0);
outbufdebug : out STD_LOGIC_VECTOR (63 downto 0)
);
END COMPONENT;
--Inputs
signal Send : std_logic := '0';
signal Resetn : std_logic := '0';
signal scancode : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal hexdebug : std_logic_vector(3 downto 0);
signal output : std_logic_vector(23 downto 0);
signal counter : std_logic_vector(3 downto 0);
signal outbufdebug : STD_LOGIC_VECTOR (63 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: scan_to_hex PORT MAP (
Send => Send,
Resetn => Resetn,
scancode => scancode,
output => output,
outCount => counter,
hexdebug => hexdebug,
outbufdebug => outbufdebug
);
-- Stimulus process
stim_proc: process
begin
Resetn <= '1';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"26";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"26";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"16";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"5A";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"36";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"46";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"36";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"46";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"23";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"23";
wait for 20 ns;
send <= '0';
wait for 20 ns;
send <= '1';
scancode <= x"5A";
wait for 20 ns;
send <= '0';
end process;
END;
| mit | 1ee819b0d18af129803295eb0296ecb8 | 0.579952 | 3.273438 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/Reg_4bit_Rising.vhd | 1 | 1,613 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: RegF
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
--
-- Notes:
-- Clocked on RISING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the rising
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the RISING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY Reg4R IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END Reg4R;
ARCHITECTURE Behavior OF Reg4R IS
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | a752f8b1c955cc3c49a47b200045bded | 0.525728 | 3.649321 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/netgen/synthesis/CPU_synthesis.vhd | 1 | 88,074 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: CPU_synthesis.vhd
-- /___/ /\ Timestamp: Sat Oct 31 19:35:20 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm CPU -w -dir netgen/synthesis -ofmt vhdl -sim CPU.ngc CPU_synthesis.vhd
-- Device : xc3s250e-5-vq100
-- Input file : CPU.ngc
-- Output file : C:\Users\Colton\Desktop\Nibble_Knowledge_CPU\netgen\synthesis\CPU_synthesis.vhd
-- # of Entities : 1
-- Design Name : CPU
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity CPU is
port (
clk : in STD_LOGIC := 'X';
clk_out : out STD_LOGIC;
ram_write_enable : out STD_LOGIC;
reset : in STD_LOGIC := 'X';
ram_data : inout STD_LOGIC_VECTOR ( 3 downto 0 );
a_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_address : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end CPU;
architecture Structure of CPU is
signal Intern_clock_hundredHzClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_hundredHzClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_hundredHzClock_i_zero_8 : STD_LOGIC;
signal Intern_clock_hundredHzClock_i_zero_or0000_9 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_0 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_1 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_10 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_11 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_12 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_13 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_14 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_2 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_3 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_4 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_5 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_6 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_7 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_8 : STD_LOGIC;
signal Intern_clock_kiloHzClock_Mcount_current_count_eqn_9 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq0000 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000012_70 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000025_71 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000049_72 : STD_LOGIC;
signal Intern_clock_kiloHzClock_current_count_cmp_eq000058_73 : STD_LOGIC;
signal Intern_clock_kiloHzClock_i_zero_74 : STD_LOGIC;
signal Intern_clock_kiloHzClock_i_zero_or0000 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_oneHZClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero_84 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero1 : STD_LOGIC;
signal Intern_clock_oneHZClock_i_zero_or0000_86 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count1 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count2 : STD_LOGIC;
signal Intern_clock_tenHzClock_Mcount_current_count3 : STD_LOGIC;
signal Intern_clock_tenHzClock_i_zero_95 : STD_LOGIC;
signal Intern_clock_tenHzClock_i_zero_or0000_96 : STD_LOGIC;
signal MEM_Mcount_i_nibbleCount : STD_LOGIC;
signal MEM_Mcount_i_nibbleCount1 : STD_LOGIC;
signal MEM_q_0_not0001 : STD_LOGIC;
signal MEM_q_10_not0001 : STD_LOGIC;
signal MEM_q_12_not0001 : STD_LOGIC;
signal MEM_q_4_not0001 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal N102 : STD_LOGIC;
signal N104 : STD_LOGIC;
signal N106 : STD_LOGIC;
signal N107 : STD_LOGIC;
signal N108 : STD_LOGIC;
signal N109 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N110 : STD_LOGIC;
signal N111 : STD_LOGIC;
signal N114 : STD_LOGIC;
signal N120 : STD_LOGIC;
signal N122 : STD_LOGIC;
signal N123 : STD_LOGIC;
signal N124 : STD_LOGIC;
signal N125 : STD_LOGIC;
signal N126 : STD_LOGIC;
signal N127 : STD_LOGIC;
signal N128 : STD_LOGIC;
signal N129 : STD_LOGIC;
signal N13 : STD_LOGIC;
signal N130 : STD_LOGIC;
signal N131 : STD_LOGIC;
signal N132 : STD_LOGIC;
signal N133 : STD_LOGIC;
signal N134 : STD_LOGIC;
signal N135 : STD_LOGIC;
signal N32 : STD_LOGIC;
signal N33 : STD_LOGIC;
signal N38 : STD_LOGIC;
signal N39 : STD_LOGIC;
signal N41 : STD_LOGIC;
signal N42 : STD_LOGIC;
signal N44 : STD_LOGIC;
signal N45 : STD_LOGIC;
signal N47 : STD_LOGIC;
signal N49 : STD_LOGIC;
signal N50 : STD_LOGIC;
signal N56 : STD_LOGIC;
signal N57 : STD_LOGIC;
signal N58 : STD_LOGIC;
signal N59 : STD_LOGIC;
signal N64 : STD_LOGIC;
signal N65 : STD_LOGIC;
signal N67 : STD_LOGIC;
signal N69 : STD_LOGIC;
signal N70 : STD_LOGIC;
signal N72 : STD_LOGIC;
signal N73 : STD_LOGIC;
signal N75 : STD_LOGIC;
signal N76 : STD_LOGIC;
signal N78 : STD_LOGIC;
signal N79 : STD_LOGIC;
signal N81 : STD_LOGIC;
signal N82 : STD_LOGIC;
signal N84 : STD_LOGIC;
signal N85 : STD_LOGIC;
signal N87 : STD_LOGIC;
signal N88 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N90 : STD_LOGIC;
signal N91 : STD_LOGIC;
signal N93 : STD_LOGIC;
signal N95 : STD_LOGIC;
signal N96 : STD_LOGIC;
signal N98 : STD_LOGIC;
signal N99 : STD_LOGIC;
signal adder_16bit_N11 : STD_LOGIC;
signal adder_16bit_N3 : STD_LOGIC;
signal adder_16bit_N4 : STD_LOGIC;
signal adder_16bit_N5 : STD_LOGIC;
signal adder_16bit_bit11_cout_and0001 : STD_LOGIC;
signal adder_16bit_bit6_cout_and0001 : STD_LOGIC;
signal clk_BUFGP_231 : STD_LOGIC;
signal cpu_alu_DECODER_N11 : STD_LOGIC;
signal cpu_alu_N0 : STD_LOGIC;
signal cpu_alu_N18 : STD_LOGIC;
signal cpu_alu_STAT_data_out_0_Q : STD_LOGIC;
signal cpu_alu_STAT_data_out_1_Q : STD_LOGIC;
signal cpu_alu_STAT_data_out_3_Q : STD_LOGIC;
signal cpu_alu_i_A_EN : STD_LOGIC;
signal cpu_alu_i_A_in_1_97 : STD_LOGIC;
signal cpu_alu_i_A_in_3_1 : STD_LOGIC;
signal cpu_alu_i_MSB_cin : STD_LOGIC;
signal cpu_alu_i_STAT_EN : STD_LOGIC;
signal cpu_alu_i_XORb_in_256 : STD_LOGIC;
signal cpu_alu_i_arith_S : STD_LOGIC;
signal cpu_alu_i_carry_in_258 : STD_LOGIC;
signal cpu_alu_i_stat_S : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter1 : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter2 : STD_LOGIC;
signal cycle_control_unit_Mcount_cycle_counter_val : STD_LOGIC;
signal cycle_control_unit_cycle_counter_or0000 : STD_LOGIC;
signal cycle_control_unit_exe_268 : STD_LOGIC;
signal cycle_control_unit_exe_mux0000 : STD_LOGIC;
signal cycle_control_unit_mem_en_270 : STD_LOGIC;
signal cycle_control_unit_mem_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_op_en_272 : STD_LOGIC;
signal cycle_control_unit_op_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_pc_en_274 : STD_LOGIC;
signal cycle_control_unit_pc_en_mux0000 : STD_LOGIC;
signal cycle_control_unit_received_hlt_276 : STD_LOGIC;
signal cycle_control_unit_received_hlt_0_not0000 : STD_LOGIC;
signal i_hlt : STD_LOGIC;
signal i_jmp : STD_LOGIC;
signal i_pc_en_after_or : STD_LOGIC;
signal i_pc_prime_10_19_287 : STD_LOGIC;
signal i_pc_prime_10_69 : STD_LOGIC;
signal i_pc_prime_10_691_289 : STD_LOGIC;
signal i_pc_prime_10_8_290 : STD_LOGIC;
signal i_pc_prime_14_9_295 : STD_LOGIC;
signal i_pc_prime_4_17_301 : STD_LOGIC;
signal i_pc_prime_5_30_303 : STD_LOGIC;
signal i_pc_prime_5_4_304 : STD_LOGIC;
signal i_pc_prime_7_1_307 : STD_LOGIC;
signal i_pc_prime_7_2_308 : STD_LOGIC;
signal i_pc_prime_8_1_310 : STD_LOGIC;
signal i_pc_prime_9_35 : STD_LOGIC;
signal i_pc_prime_9_9_313 : STD_LOGIC;
signal i_received_hlt_314 : STD_LOGIC;
signal ram_address_0_OBUF_331 : STD_LOGIC;
signal ram_address_10_OBUF_332 : STD_LOGIC;
signal ram_address_11_OBUF_333 : STD_LOGIC;
signal ram_address_12_OBUF_334 : STD_LOGIC;
signal ram_address_13_OBUF_335 : STD_LOGIC;
signal ram_address_14_OBUF_336 : STD_LOGIC;
signal ram_address_15_OBUF_337 : STD_LOGIC;
signal ram_address_1_OBUF_338 : STD_LOGIC;
signal ram_address_2_OBUF_339 : STD_LOGIC;
signal ram_address_3_OBUF_340 : STD_LOGIC;
signal ram_address_4_OBUF_341 : STD_LOGIC;
signal ram_address_5_OBUF_342 : STD_LOGIC;
signal ram_address_6_OBUF_343 : STD_LOGIC;
signal ram_address_7_OBUF_344 : STD_LOGIC;
signal ram_address_8_OBUF_345 : STD_LOGIC;
signal ram_address_9_OBUF_346 : STD_LOGIC;
signal ram_data_i_data_to_ram_not0000_inv : STD_LOGIC;
signal reset_IBUF_354 : STD_LOGIC;
signal reset_IBUF1 : STD_LOGIC;
signal Intern_clock_hundredHzClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Intern_clock_kiloHzClock_Mcount_current_count_cy : STD_LOGIC_VECTOR ( 13 downto 0 );
signal Intern_clock_kiloHzClock_Mcount_current_count_lut : STD_LOGIC_VECTOR ( 14 downto 1 );
signal Intern_clock_kiloHzClock_current_count : STD_LOGIC_VECTOR ( 14 downto 0 );
signal Intern_clock_oneHZClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Intern_clock_tenHzClock_current_count : STD_LOGIC_VECTOR ( 3 downto 0 );
signal MEM_i_nibbleCount : STD_LOGIC_VECTOR ( 1 downto 0 );
signal MEM_q : STD_LOGIC_VECTOR ( 15 downto 0 );
signal PCreg_q : STD_LOGIC_VECTOR ( 15 downto 0 );
signal Result : STD_LOGIC_VECTOR ( 14 downto 0 );
signal cpu_alu_A_data_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cpu_alu_DECODER_stored_OP_Code : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cpu_alu_i_A_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cycle_control_unit_cycle_counter : STD_LOGIC_VECTOR ( 2 downto 0 );
signal i_data_frm_ram : STD_LOGIC_VECTOR ( 3 downto 0 );
signal i_pc_prime : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N1
);
i_received_hlt : LDP
port map (
D => N0,
G => reset_IBUF_354,
PRE => i_hlt,
Q => i_received_hlt_314
);
Intern_clock_hundredHzClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_hundredHzClock_i_zero_or0000_9,
Q => Intern_clock_hundredHzClock_i_zero_8
);
Intern_clock_tenHzClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_tenHzClock_i_zero_or0000_96,
Q => Intern_clock_tenHzClock_i_zero_95
);
Intern_clock_oneHZClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_oneHZClock_i_zero_or0000_86,
Q => Intern_clock_oneHZClock_i_zero1
);
Intern_clock_kiloHzClock_i_zero : FDR
port map (
C => clk_BUFGP_231,
D => N1,
R => Intern_clock_kiloHzClock_i_zero_or0000,
Q => Intern_clock_kiloHzClock_i_zero_74
);
Intern_clock_hundredHzClock_current_count_0 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count,
S => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(0)
);
Intern_clock_hundredHzClock_current_count_1 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count1,
R => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(1)
);
Intern_clock_hundredHzClock_current_count_2 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count2,
R => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(2)
);
Intern_clock_hundredHzClock_current_count_3 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_kiloHzClock_i_zero_74,
D => Intern_clock_hundredHzClock_Mcount_current_count3,
S => reset_IBUF1,
Q => Intern_clock_hundredHzClock_current_count(3)
);
Intern_clock_tenHzClock_current_count_0 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count,
S => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(0)
);
Intern_clock_tenHzClock_current_count_1 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count1,
R => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(1)
);
Intern_clock_tenHzClock_current_count_2 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count2,
R => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(2)
);
Intern_clock_tenHzClock_current_count_3 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_hundredHzClock_i_zero_8,
D => Intern_clock_tenHzClock_Mcount_current_count3,
S => reset_IBUF1,
Q => Intern_clock_tenHzClock_current_count(3)
);
Intern_clock_oneHZClock_current_count_0 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count,
S => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(0)
);
Intern_clock_oneHZClock_current_count_1 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count1,
R => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(1)
);
Intern_clock_oneHZClock_current_count_2 : FDRE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count2,
R => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(2)
);
Intern_clock_oneHZClock_current_count_3 : FDSE
port map (
C => clk_BUFGP_231,
CE => Intern_clock_tenHzClock_i_zero_95,
D => Intern_clock_oneHZClock_Mcount_current_count3,
S => reset_IBUF1,
Q => Intern_clock_oneHZClock_current_count(3)
);
Intern_clock_kiloHzClock_current_count_0 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_0,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(0)
);
Intern_clock_kiloHzClock_current_count_1 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_1,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(1)
);
Intern_clock_kiloHzClock_current_count_2 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_2,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(2)
);
Intern_clock_kiloHzClock_current_count_3 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_3,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(3)
);
Intern_clock_kiloHzClock_current_count_4 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_4,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(4)
);
Intern_clock_kiloHzClock_current_count_5 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_5,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(5)
);
Intern_clock_kiloHzClock_current_count_6 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_6,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(6)
);
Intern_clock_kiloHzClock_current_count_7 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_7,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(7)
);
Intern_clock_kiloHzClock_current_count_8 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_8,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(8)
);
Intern_clock_kiloHzClock_current_count_9 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_9,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(9)
);
Intern_clock_kiloHzClock_current_count_10 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_10,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(10)
);
Intern_clock_kiloHzClock_current_count_11 : FDS
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_11,
S => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(11)
);
Intern_clock_kiloHzClock_current_count_12 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_12,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(12)
);
Intern_clock_kiloHzClock_current_count_13 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_13,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(13)
);
Intern_clock_kiloHzClock_current_count_14 : FDR
port map (
C => clk_BUFGP_231,
D => Intern_clock_kiloHzClock_Mcount_current_count_eqn_14,
R => reset_IBUF1,
Q => Intern_clock_kiloHzClock_current_count(14)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_0_Q : MUXCY
port map (
CI => N1,
DI => N0,
S => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11,
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_0_Q : XORCY
port map (
CI => N1,
LI => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11,
O => Result(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_1_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(0),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(1),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_1_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(0),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(1),
O => Result(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_2_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(1),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(2),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_2_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(1),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(2),
O => Result(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_3_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(2),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(3),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_3_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(2),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(3),
O => Result(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_4_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(3),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(4),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_4_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(3),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(4),
O => Result(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_5_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(4),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(5),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_5_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(4),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(5),
O => Result(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_6_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(5),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(6),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_6_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(5),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(6),
O => Result(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_7_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(6),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(7),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_7_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(6),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(7),
O => Result(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_8_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(7),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(8),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_8_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(7),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(8),
O => Result(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_9_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(8),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(9),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_9_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(8),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(9),
O => Result(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_10_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(9),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(10),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_10_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(9),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(10),
O => Result(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_11_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(10),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(11),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_11_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(10),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(11),
O => Result(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_12_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(11),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(12),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_12_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(11),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(12),
O => Result(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_13_Q : MUXCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(12),
DI => N1,
S => Intern_clock_kiloHzClock_Mcount_current_count_lut(13),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_13_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(12),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(13),
O => Result(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_xor_14_Q : XORCY
port map (
CI => Intern_clock_kiloHzClock_Mcount_current_count_cy(13),
LI => Intern_clock_kiloHzClock_Mcount_current_count_lut(14),
O => Result(14)
);
PCreg_q_15 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(15),
Q => PCreg_q(15)
);
PCreg_q_14 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(14),
Q => PCreg_q(14)
);
PCreg_q_13 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(13),
Q => PCreg_q(13)
);
PCreg_q_12 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(12),
Q => PCreg_q(12)
);
PCreg_q_11 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(11),
Q => PCreg_q(11)
);
PCreg_q_10 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(10),
Q => PCreg_q(10)
);
PCreg_q_9 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(9),
Q => PCreg_q(9)
);
PCreg_q_8 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(8),
Q => PCreg_q(8)
);
PCreg_q_7 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(7),
Q => PCreg_q(7)
);
PCreg_q_6 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(6),
Q => PCreg_q(6)
);
PCreg_q_5 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(5),
Q => PCreg_q(5)
);
PCreg_q_4 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
D => i_pc_prime(4),
PRE => reset_IBUF1,
Q => PCreg_q(4)
);
PCreg_q_3 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(3),
Q => PCreg_q(3)
);
PCreg_q_2 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
CLR => reset_IBUF1,
D => i_pc_prime(2),
Q => PCreg_q(2)
);
PCreg_q_1 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
D => i_pc_prime(1),
PRE => reset_IBUF1,
Q => PCreg_q(1)
);
PCreg_q_0 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => i_pc_en_after_or,
D => i_pc_prime(0),
PRE => reset_IBUF1,
Q => PCreg_q(0)
);
MEM_i_nibbleCount_1 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_mem_en_270,
D => MEM_Mcount_i_nibbleCount1,
PRE => reset_IBUF1,
Q => MEM_i_nibbleCount(1)
);
MEM_i_nibbleCount_0 : FDPE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_mem_en_270,
D => MEM_Mcount_i_nibbleCount,
PRE => reset_IBUF1,
Q => MEM_i_nibbleCount(0)
);
MEM_q_15 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(15)
);
MEM_q_14 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(14)
);
MEM_q_13 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(13)
);
MEM_q_9 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(9)
);
MEM_q_12 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_12_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(12)
);
MEM_q_8 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(8)
);
MEM_q_11 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(11)
);
MEM_q_7 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(7)
);
MEM_q_10 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_10_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(10)
);
MEM_q_6 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(6)
);
MEM_q_5 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(5)
);
MEM_q_4 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_4_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(4)
);
MEM_q_3 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(3),
Q => MEM_q(3)
);
MEM_q_1 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(1),
Q => MEM_q(1)
);
MEM_q_0 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(0),
Q => MEM_q(0)
);
MEM_q_2 : FDCE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => MEM_q_0_not0001,
CLR => reset_IBUF1,
D => i_data_frm_ram(2),
Q => MEM_q(2)
);
cycle_control_unit_cycle_counter_1 : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_Mcount_cycle_counter1,
Q => cycle_control_unit_cycle_counter(1)
);
cycle_control_unit_cycle_counter_0 : FDCP
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_cycle_counter_or0000,
D => cycle_control_unit_Mcount_cycle_counter,
PRE => reset_IBUF1,
Q => cycle_control_unit_cycle_counter(0)
);
cycle_control_unit_cycle_counter_2 : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_Mcount_cycle_counter2,
Q => cycle_control_unit_cycle_counter(2)
);
cycle_control_unit_received_hlt : LDCE
port map (
CLR => reset_IBUF1,
D => N1,
G => i_hlt,
GE => cycle_control_unit_received_hlt_0_not0000,
Q => cycle_control_unit_received_hlt_276
);
cycle_control_unit_op_en : FDCP
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_cycle_counter_or0000,
D => cycle_control_unit_op_en_mux0000,
PRE => reset_IBUF1,
Q => cycle_control_unit_op_en_272
);
cycle_control_unit_exe : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_exe_mux0000,
Q => cycle_control_unit_exe_268
);
cycle_control_unit_mem_en : FDC
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_Mcount_cycle_counter_val,
D => cycle_control_unit_mem_en_mux0000,
Q => cycle_control_unit_mem_en_270
);
cycle_control_unit_pc_en : FDCP
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CLR => cycle_control_unit_cycle_counter_or0000,
D => cycle_control_unit_pc_en_mux0000,
PRE => reset_IBUF1,
Q => cycle_control_unit_pc_en_274
);
cpu_alu_DECODER_stored_OP_Code_0 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(0),
Q => cpu_alu_DECODER_stored_OP_Code(0)
);
cpu_alu_DECODER_stored_OP_Code_1 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(1),
Q => cpu_alu_DECODER_stored_OP_Code(1)
);
cpu_alu_DECODER_stored_OP_Code_2 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(2),
Q => cpu_alu_DECODER_stored_OP_Code(2)
);
cpu_alu_DECODER_stored_OP_Code_3 : FDE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cycle_control_unit_op_en_272,
D => i_data_frm_ram(3),
Q => cpu_alu_DECODER_stored_OP_Code(3)
);
cpu_alu_STAT_data_out_0 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_STAT_EN,
D => cpu_alu_i_carry_in_258,
R => reset_IBUF1,
Q => cpu_alu_STAT_data_out_0_Q
);
cpu_alu_STAT_data_out_1 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_STAT_EN,
D => i_hlt,
R => reset_IBUF1,
Q => cpu_alu_STAT_data_out_1_Q
);
cpu_alu_STAT_data_out_3 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_STAT_EN,
D => cpu_alu_i_XORb_in_256,
R => reset_IBUF1,
Q => cpu_alu_STAT_data_out_3_Q
);
cycle_control_unit_cycle_counter_or00001 : LUT3
generic map(
INIT => X"32"
)
port map (
I0 => i_hlt,
I1 => reset_IBUF1,
I2 => cycle_control_unit_received_hlt_276,
O => cycle_control_unit_cycle_counter_or0000
);
cycle_control_unit_Mcount_cycle_counter_val1 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => reset_IBUF1,
I1 => i_hlt,
I2 => cycle_control_unit_received_hlt_276,
O => cycle_control_unit_Mcount_cycle_counter_val
);
i_ram_address_9_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(9),
I2 => PCreg_q(9),
O => ram_address_9_OBUF_346
);
i_ram_address_8_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(8),
I2 => PCreg_q(8),
O => ram_address_8_OBUF_345
);
i_ram_address_7_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(7),
I2 => PCreg_q(7),
O => ram_address_7_OBUF_344
);
i_ram_address_6_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(6),
I2 => PCreg_q(6),
O => ram_address_6_OBUF_343
);
i_ram_address_5_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(5),
I2 => PCreg_q(5),
O => ram_address_5_OBUF_342
);
i_ram_address_4_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(4),
I2 => PCreg_q(4),
O => ram_address_4_OBUF_341
);
i_ram_address_3_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(3),
I2 => PCreg_q(3),
O => ram_address_3_OBUF_340
);
i_ram_address_2_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(2),
I2 => PCreg_q(2),
O => ram_address_2_OBUF_339
);
i_ram_address_1_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(1),
I2 => PCreg_q(1),
O => ram_address_1_OBUF_338
);
i_ram_address_15_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(15),
I2 => PCreg_q(15),
O => ram_address_15_OBUF_337
);
i_ram_address_14_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(14),
I2 => PCreg_q(14),
O => ram_address_14_OBUF_336
);
i_ram_address_13_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(13),
I2 => PCreg_q(13),
O => ram_address_13_OBUF_335
);
i_ram_address_12_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(12),
I2 => PCreg_q(12),
O => ram_address_12_OBUF_334
);
i_ram_address_11_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(11),
I2 => PCreg_q(11),
O => ram_address_11_OBUF_333
);
i_ram_address_10_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(10),
I2 => PCreg_q(10),
O => ram_address_10_OBUF_332
);
i_ram_address_0_1 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => MEM_q(0),
I2 => PCreg_q(0),
O => ram_address_0_OBUF_331
);
MEM_Mcount_i_nibbleCount_xor_1_11 : LUT2
generic map(
INIT => X"9"
)
port map (
I0 => MEM_i_nibbleCount(0),
I1 => MEM_i_nibbleCount(1),
O => MEM_Mcount_i_nibbleCount1
);
cycle_control_unit_Mcount_cycle_counter_xor_2_11 : LUT3
generic map(
INIT => X"62"
)
port map (
I0 => cycle_control_unit_cycle_counter(2),
I1 => cycle_control_unit_cycle_counter(0),
I2 => cycle_control_unit_cycle_counter(1),
O => cycle_control_unit_Mcount_cycle_counter2
);
cycle_control_unit_Mcount_cycle_counter_xor_1_11 : LUT3
generic map(
INIT => X"26"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(0),
I2 => cycle_control_unit_cycle_counter(2),
O => cycle_control_unit_Mcount_cycle_counter1
);
cycle_control_unit_pc_en_mux00001 : LUT4
generic map(
INIT => X"BF1F"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(0),
I2 => cycle_control_unit_cycle_counter(2),
I3 => cycle_control_unit_pc_en_274,
O => cycle_control_unit_pc_en_mux0000
);
cycle_control_unit_exe_mux00001 : LUT4
generic map(
INIT => X"A280"
)
port map (
I0 => cycle_control_unit_cycle_counter(2),
I1 => cycle_control_unit_cycle_counter(1),
I2 => cycle_control_unit_exe_268,
I3 => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_exe_mux0000
);
cycle_control_unit_op_en_mux00001 : LUT4
generic map(
INIT => X"8091"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(2),
I2 => cycle_control_unit_op_en_272,
I3 => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_op_en_mux0000
);
Intern_clock_tenHzClock_Mcount_current_count_xor_1_11 : LUT4
generic map(
INIT => X"9998"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(0),
I1 => Intern_clock_tenHzClock_current_count(1),
I2 => Intern_clock_tenHzClock_current_count(2),
I3 => Intern_clock_tenHzClock_current_count(3),
O => Intern_clock_tenHzClock_Mcount_current_count1
);
Intern_clock_oneHZClock_Mcount_current_count_xor_1_11 : LUT4
generic map(
INIT => X"9998"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(0),
I1 => Intern_clock_oneHZClock_current_count(1),
I2 => Intern_clock_oneHZClock_current_count(2),
I3 => Intern_clock_oneHZClock_current_count(3),
O => Intern_clock_oneHZClock_Mcount_current_count1
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_1_11 : LUT4
generic map(
INIT => X"9998"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(0),
I1 => Intern_clock_hundredHzClock_current_count(1),
I2 => Intern_clock_hundredHzClock_current_count(2),
I3 => Intern_clock_hundredHzClock_current_count(3),
O => Intern_clock_hundredHzClock_Mcount_current_count1
);
Intern_clock_tenHzClock_Mcount_current_count_xor_2_11 : LUT4
generic map(
INIT => X"C9C8"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(1),
I1 => Intern_clock_tenHzClock_current_count(2),
I2 => Intern_clock_tenHzClock_current_count(0),
I3 => Intern_clock_tenHzClock_current_count(3),
O => Intern_clock_tenHzClock_Mcount_current_count2
);
Intern_clock_oneHZClock_Mcount_current_count_xor_2_11 : LUT4
generic map(
INIT => X"C9C8"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(1),
I1 => Intern_clock_oneHZClock_current_count(2),
I2 => Intern_clock_oneHZClock_current_count(0),
I3 => Intern_clock_oneHZClock_current_count(3),
O => Intern_clock_oneHZClock_Mcount_current_count2
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_2_11 : LUT4
generic map(
INIT => X"C9C8"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(1),
I1 => Intern_clock_hundredHzClock_current_count(2),
I2 => Intern_clock_hundredHzClock_current_count(0),
I3 => Intern_clock_hundredHzClock_current_count(3),
O => Intern_clock_hundredHzClock_Mcount_current_count2
);
cycle_control_unit_mem_en_mux00001 : LUT4
generic map(
INIT => X"BE36"
)
port map (
I0 => cycle_control_unit_cycle_counter(1),
I1 => cycle_control_unit_cycle_counter(2),
I2 => cycle_control_unit_cycle_counter(0),
I3 => cycle_control_unit_mem_en_270,
O => cycle_control_unit_mem_en_mux0000
);
Intern_clock_tenHzClock_Mcount_current_count_xor_3_11 : LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(3),
I1 => Intern_clock_tenHzClock_current_count(1),
I2 => Intern_clock_tenHzClock_current_count(0),
I3 => Intern_clock_tenHzClock_current_count(2),
O => Intern_clock_tenHzClock_Mcount_current_count3
);
Intern_clock_oneHZClock_Mcount_current_count_xor_3_11 : LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(3),
I1 => Intern_clock_oneHZClock_current_count(1),
I2 => Intern_clock_oneHZClock_current_count(0),
I3 => Intern_clock_oneHZClock_current_count(2),
O => Intern_clock_oneHZClock_Mcount_current_count3
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_3_11 : LUT4
generic map(
INIT => X"AAA9"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(3),
I1 => Intern_clock_hundredHzClock_current_count(1),
I2 => Intern_clock_hundredHzClock_current_count(0),
I3 => Intern_clock_hundredHzClock_current_count(2),
O => Intern_clock_hundredHzClock_Mcount_current_count3
);
MEM_q_4_not00011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => MEM_i_nibbleCount(0),
I1 => MEM_i_nibbleCount(1),
I2 => cycle_control_unit_mem_en_270,
O => MEM_q_4_not0001
);
MEM_q_12_not00011 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => MEM_i_nibbleCount(1),
I1 => MEM_i_nibbleCount(0),
I2 => cycle_control_unit_mem_en_270,
O => MEM_q_12_not0001
);
MEM_q_10_not00011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => MEM_i_nibbleCount(1),
I1 => MEM_i_nibbleCount(0),
I2 => cycle_control_unit_mem_en_270,
O => MEM_q_10_not0001
);
MEM_q_0_not00011 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => MEM_i_nibbleCount(1),
I1 => cycle_control_unit_mem_en_270,
I2 => MEM_i_nibbleCount(0),
O => MEM_q_0_not0001
);
Intern_clock_tenHzClock_i_zero_or0000_SW0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(3),
I1 => Intern_clock_tenHzClock_current_count(2),
I2 => reset_IBUF1,
O => N9
);
Intern_clock_tenHzClock_i_zero_or0000 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => Intern_clock_tenHzClock_current_count(0),
I1 => Intern_clock_hundredHzClock_i_zero_8,
I2 => Intern_clock_tenHzClock_current_count(1),
I3 => N9,
O => Intern_clock_tenHzClock_i_zero_or0000_96
);
Intern_clock_oneHZClock_i_zero_or0000_SW0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(3),
I1 => Intern_clock_oneHZClock_current_count(2),
I2 => reset_IBUF1,
O => N11
);
Intern_clock_oneHZClock_i_zero_or0000 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => Intern_clock_oneHZClock_current_count(1),
I1 => Intern_clock_tenHzClock_i_zero_95,
I2 => Intern_clock_oneHZClock_current_count(0),
I3 => N11,
O => Intern_clock_oneHZClock_i_zero_or0000_86
);
Intern_clock_hundredHzClock_i_zero_or0000_SW0 : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(3),
I1 => Intern_clock_hundredHzClock_current_count(2),
I2 => reset_IBUF1,
O => N13
);
Intern_clock_hundredHzClock_i_zero_or0000 : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => Intern_clock_hundredHzClock_current_count(1),
I1 => Intern_clock_kiloHzClock_i_zero_74,
I2 => Intern_clock_hundredHzClock_current_count(0),
I3 => N13,
O => Intern_clock_hundredHzClock_i_zero_or0000_9
);
cpu_alu_DECODER_STAT_EN_and00001 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => cpu_alu_i_A_EN,
I1 => cpu_alu_DECODER_stored_OP_Code(2),
I2 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_i_STAT_EN
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_15 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(1),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_1
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_01 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(0),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_0
);
cpu_alu_DECODER_HLT_and00002 : LUT3
generic map(
INIT => X"04"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(2),
I1 => N128,
I2 => cpu_alu_DECODER_stored_OP_Code(1),
O => i_hlt
);
i_pc_en_after_or1 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => cycle_control_unit_pc_en_274,
I1 => i_jmp,
O => i_pc_en_after_or
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_21 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(2),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_2
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_31 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(3),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_3
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_41 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(4),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_4
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_51 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(5),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_5
);
Intern_clock_kiloHzClock_i_zero_or00001 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
I1 => reset_IBUF1,
O => Intern_clock_kiloHzClock_i_zero_or0000
);
Intern_clock_kiloHzClock_current_count_cmp_eq000012 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(1),
I1 => Intern_clock_kiloHzClock_current_count(14),
I2 => Intern_clock_kiloHzClock_current_count(2),
I3 => Intern_clock_kiloHzClock_current_count(3),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000012_70
);
Intern_clock_kiloHzClock_current_count_cmp_eq000025 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(4),
I1 => Intern_clock_kiloHzClock_current_count(5),
I2 => Intern_clock_kiloHzClock_current_count(6),
I3 => Intern_clock_kiloHzClock_current_count(7),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000025_71
);
Intern_clock_kiloHzClock_current_count_cmp_eq000049 : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(8),
I1 => Intern_clock_kiloHzClock_current_count(9),
I2 => Intern_clock_kiloHzClock_current_count(10),
I3 => Intern_clock_kiloHzClock_current_count(11),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000049_72
);
Intern_clock_kiloHzClock_current_count_cmp_eq000058 : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(12),
I1 => Intern_clock_kiloHzClock_current_count(13),
I2 => Intern_clock_kiloHzClock_current_count(0),
O => Intern_clock_kiloHzClock_current_count_cmp_eq000058_73
);
Intern_clock_kiloHzClock_current_count_cmp_eq000071 : LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count_cmp_eq000012_70,
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq000025_71,
I2 => Intern_clock_kiloHzClock_current_count_cmp_eq000049_72,
I3 => Intern_clock_kiloHzClock_current_count_cmp_eq000058_73,
O => Intern_clock_kiloHzClock_current_count_cmp_eq0000
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_61 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(6),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_6
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_71 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(7),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_7
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_81 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(8),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_8
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_91 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(9),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_9
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_101 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(10),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_10
);
cpu_alu_DECODER_Stat_S_and00001 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(1),
I1 => cpu_alu_DECODER_stored_OP_Code(2),
I2 => cpu_alu_i_A_EN,
O => cpu_alu_i_stat_S
);
i_pc_prime_6_1 : LUT4
generic map(
INIT => X"BE14"
)
port map (
I0 => i_jmp,
I1 => adder_16bit_bit6_cout_and0001,
I2 => PCreg_q(6),
I3 => MEM_q(6),
O => i_pc_prime(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_111 : LUT2
generic map(
INIT => X"E"
)
port map (
I0 => Result(11),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_11
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_121 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(12),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_12
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_131 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(13),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_13
);
Intern_clock_kiloHzClock_Mcount_current_count_eqn_141 : LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Result(14),
I1 => Intern_clock_kiloHzClock_current_count_cmp_eq0000,
O => Intern_clock_kiloHzClock_Mcount_current_count_eqn_14
);
i_data_frm_ram_3_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N56,
O => i_data_frm_ram(3)
);
cpu_alu_DECODER_Arith_S_and000011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => cycle_control_unit_exe_268,
I1 => cpu_alu_DECODER_stored_OP_Code(3),
I2 => cpu_alu_DECODER_stored_OP_Code(0),
O => cpu_alu_i_A_EN
);
cpu_alu_DECODER_Arith_S_and00001 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(2),
I1 => cpu_alu_DECODER_stored_OP_Code(1),
I2 => cpu_alu_i_A_EN,
O => cpu_alu_i_arith_S
);
i_pc_prime_11_1 : LUT4
generic map(
INIT => X"A3AC"
)
port map (
I0 => MEM_q(11),
I1 => PCreg_q(11),
I2 => i_jmp,
I3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(11)
);
i_pc_prime_9_9 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => PCreg_q(6),
I1 => PCreg_q(7),
I2 => PCreg_q(8),
I3 => PCreg_q(9),
O => i_pc_prime_9_9_313
);
i_pc_prime_10_8 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => PCreg_q(8),
I1 => PCreg_q(9),
O => i_pc_prime_10_8_290
);
i_pc_prime_10_19 : LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => PCreg_q(6),
I1 => i_pc_prime_10_8_290,
I2 => PCreg_q(7),
I3 => N130,
O => i_pc_prime_10_19_287
);
i_data_frm_ram_2_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N57,
O => i_data_frm_ram(2)
);
i_pc_prime_12_SW0 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(12),
I2 => PCreg_q(12),
O => N32
);
i_pc_prime_12_Q : LUT4
generic map(
INIT => X"D8F0"
)
port map (
I0 => PCreg_q(11),
I1 => N33,
I2 => N32,
I3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(12)
);
i_pc_prime_13_SW0 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(13),
I2 => PCreg_q(13),
O => N38
);
i_pc_prime_13_Q : LUT4
generic map(
INIT => X"D8F0"
)
port map (
I0 => PCreg_q(12),
I1 => N39,
I2 => N38,
I3 => adder_16bit_bit11_cout_and0001,
O => i_pc_prime(13)
);
i_data_frm_ram_1_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N58,
O => i_data_frm_ram(1)
);
i_pc_prime_14_9 : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => PCreg_q(11),
I1 => PCreg_q(12),
I2 => PCreg_q(13),
I3 => PCreg_q(14),
O => i_pc_prime_14_9_295
);
i_pc_prime_15_SW0 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(15),
I2 => PCreg_q(15),
O => N41
);
i_pc_prime_15_SW1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(15),
I2 => MEM_q(15),
O => N42
);
i_pc_prime_15_Q : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(14),
I1 => N41,
I2 => N42,
I3 => N132,
O => i_pc_prime(15)
);
i_pc_prime_0_SW1 : LUT4
generic map(
INIT => X"EB41"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(14),
I2 => PCreg_q(0),
I3 => MEM_q(0),
O => N45
);
i_pc_prime_0_Q : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(15),
I1 => N44,
I2 => N45,
I3 => adder_16bit_N5,
O => i_pc_prime(0)
);
i_data_frm_ram_0_LogicTrst1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => ram_data_i_data_to_ram_not0000_inv,
I1 => N59,
O => i_data_frm_ram(0)
);
cpu_alu_DECODER_WE : LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(0),
I1 => cycle_control_unit_exe_268,
I2 => cpu_alu_DECODER_stored_OP_Code(2),
I3 => N47,
O => ram_data_i_data_to_ram_not0000_inv
);
i_pc_prime_1_SW1 : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => adder_16bit_N11,
I1 => i_jmp,
I2 => MEM_q(1),
I3 => PCreg_q(1),
O => N50
);
adder_16bit_bit6_Mxor_s_xo_0_31 : LUT3
generic map(
INIT => X"80"
)
port map (
I0 => PCreg_q(1),
I1 => N131,
I2 => PCreg_q(2),
O => adder_16bit_N4
);
adder_16bit_bit11_cout_and00011 : LUT3
generic map(
INIT => X"20"
)
port map (
I0 => PCreg_q(9),
I1 => N133,
I2 => PCreg_q(10),
O => adder_16bit_bit11_cout_and0001
);
i_pc_prime_5_4 : LUT2
generic map(
INIT => X"7"
)
port map (
I0 => PCreg_q(3),
I1 => PCreg_q(4),
O => i_pc_prime_5_4_304
);
i_pc_prime_5_30 : LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => PCreg_q(5),
I1 => PCreg_q(4),
I2 => PCreg_q(3),
I3 => adder_16bit_N4,
O => i_pc_prime_5_30_303
);
reset_IBUF : IBUF
port map (
I => reset,
O => reset_IBUF1
);
clk_out_OBUF : OBUF
port map (
I => i_received_hlt_314,
O => clk_out
);
ram_write_enable_OBUF : OBUF
port map (
I => ram_data_i_data_to_ram_not0000_inv,
O => ram_write_enable
);
a_data_3_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(3),
O => a_data(3)
);
a_data_2_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(2),
O => a_data(2)
);
a_data_1_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(1),
O => a_data(1)
);
a_data_0_OBUF : OBUF
port map (
I => cpu_alu_A_data_out(0),
O => a_data(0)
);
ram_address_15_OBUF : OBUF
port map (
I => ram_address_15_OBUF_337,
O => ram_address(15)
);
ram_address_14_OBUF : OBUF
port map (
I => ram_address_14_OBUF_336,
O => ram_address(14)
);
ram_address_13_OBUF : OBUF
port map (
I => ram_address_13_OBUF_335,
O => ram_address(13)
);
ram_address_12_OBUF : OBUF
port map (
I => ram_address_12_OBUF_334,
O => ram_address(12)
);
ram_address_11_OBUF : OBUF
port map (
I => ram_address_11_OBUF_333,
O => ram_address(11)
);
ram_address_10_OBUF : OBUF
port map (
I => ram_address_10_OBUF_332,
O => ram_address(10)
);
ram_address_9_OBUF : OBUF
port map (
I => ram_address_9_OBUF_346,
O => ram_address(9)
);
ram_address_8_OBUF : OBUF
port map (
I => ram_address_8_OBUF_345,
O => ram_address(8)
);
ram_address_7_OBUF : OBUF
port map (
I => ram_address_7_OBUF_344,
O => ram_address(7)
);
ram_address_6_OBUF : OBUF
port map (
I => ram_address_6_OBUF_343,
O => ram_address(6)
);
ram_address_5_OBUF : OBUF
port map (
I => ram_address_5_OBUF_342,
O => ram_address(5)
);
ram_address_4_OBUF : OBUF
port map (
I => ram_address_4_OBUF_341,
O => ram_address(4)
);
ram_address_3_OBUF : OBUF
port map (
I => ram_address_3_OBUF_340,
O => ram_address(3)
);
ram_address_2_OBUF : OBUF
port map (
I => ram_address_2_OBUF_339,
O => ram_address(2)
);
ram_address_1_OBUF : OBUF
port map (
I => ram_address_1_OBUF_338,
O => ram_address(1)
);
ram_address_0_OBUF : OBUF
port map (
I => ram_address_0_OBUF_331,
O => ram_address(0)
);
Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => Intern_clock_kiloHzClock_current_count(0),
O => Intern_clock_kiloHzClock_Mcount_current_count_cy_0_rt_11
);
i_pc_prime_3_SW0_SW0 : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => adder_16bit_N4,
I1 => i_jmp,
I2 => MEM_q(3),
I3 => PCreg_q(3),
O => N64
);
i_pc_prime_3_SW0_SW1 : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => adder_16bit_N4,
I2 => PCreg_q(3),
I3 => MEM_q(3),
O => N65
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW0 : LUT2
generic map(
INIT => X"8"
)
port map (
I0 => PCreg_q(15),
I1 => PCreg_q(14),
O => N67
);
i_pc_prime_5_18_SW1 : LUT4
generic map(
INIT => X"AFAC"
)
port map (
I0 => MEM_q(5),
I1 => PCreg_q(5),
I2 => i_jmp,
I3 => i_pc_prime_5_30_303,
O => N70
);
i_pc_prime_4_11_SW0 : LUT4
generic map(
INIT => X"AFAC"
)
port map (
I0 => MEM_q(4),
I1 => PCreg_q(4),
I2 => i_jmp,
I3 => i_pc_prime_4_17_301,
O => N72
);
cpu_alu_i_A_in_2_11 : LUT4
generic map(
INIT => X"8CEF"
)
port map (
I0 => N58,
I1 => cpu_alu_A_data_out(1),
I2 => ram_data_i_data_to_ram_not0000_inv,
I3 => N134,
O => cpu_alu_N0
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW2 : LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => N129,
I1 => PCreg_q(14),
I2 => PCreg_q(0),
I3 => N50,
O => N79
);
i_pc_prime_1_Q : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(15),
I1 => N78,
I2 => N79,
I3 => adder_16bit_N5,
O => i_pc_prime(1)
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW4 : LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => N135,
I1 => PCreg_q(14),
I2 => PCreg_q(0),
I3 => N76,
O => N82
);
i_pc_prime_2_23 : LUT4
generic map(
INIT => X"CCE4"
)
port map (
I0 => PCreg_q(15),
I1 => N81,
I2 => N82,
I3 => adder_16bit_N5,
O => i_pc_prime(2)
);
i_pc_prime_3_Q : LUT4
generic map(
INIT => X"F0D8"
)
port map (
I0 => N67,
I1 => N85,
I2 => N84,
I3 => adder_16bit_N5,
O => i_pc_prime(3)
);
i_pc_prime_5_59 : LUT4
generic map(
INIT => X"F0D8"
)
port map (
I0 => N67,
I1 => N88,
I2 => N87,
I3 => adder_16bit_N5,
O => i_pc_prime(5)
);
i_pc_prime_4_40 : LUT4
generic map(
INIT => X"F0D8"
)
port map (
I0 => N67,
I1 => N91,
I2 => N90,
I3 => adder_16bit_N5,
O => i_pc_prime(4)
);
cpu_alu_JMP_SW0_SW0 : LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => cpu_alu_A_data_out(2),
I2 => cpu_alu_A_data_out(1),
I3 => cpu_alu_A_data_out(0),
O => N93
);
cpu_alu_JMP : LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => cpu_alu_DECODER_N11,
I1 => cpu_alu_DECODER_stored_OP_Code(1),
I2 => cpu_alu_DECODER_stored_OP_Code(2),
I3 => N93,
O => i_jmp
);
i_pc_prime_14_35_SW1 : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => i_jmp,
I1 => MEM_q(14),
O => N96
);
i_pc_prime_14_35 : LUT4
generic map(
INIT => X"D8F0"
)
port map (
I0 => PCreg_q(14),
I1 => N96,
I2 => N95,
I3 => adder_16bit_N5,
O => i_pc_prime(14)
);
i_pc_prime_5_18_SW0 : MUXF5
port map (
I0 => N98,
I1 => N99,
S => i_pc_prime_5_30_303,
O => N69
);
i_pc_prime_5_18_SW0_F : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(5),
I2 => PCreg_q(2),
I3 => MEM_q(5),
O => N98
);
i_pc_prime_5_18_SW0_G : LUT2
generic map(
INIT => X"D"
)
port map (
I0 => i_jmp,
I1 => MEM_q(5),
O => N99
);
i_pc_prime_2_12_SW0_F : LUT3
generic map(
INIT => X"62"
)
port map (
I0 => PCreg_q(2),
I1 => PCreg_q(1),
I2 => adder_16bit_N11,
O => N102
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0 : MUXF5
port map (
I0 => N106,
I1 => N107,
S => N65,
O => N84
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0_F : LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => N64,
I1 => PCreg_q(0),
I2 => PCreg_q(2),
I3 => PCreg_q(1),
O => N106
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW0_G : LUT4
generic map(
INIT => X"FF80"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(2),
I2 => PCreg_q(1),
I3 => N64,
O => N107
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2 : MUXF5
port map (
I0 => N108,
I1 => N109,
S => N69,
O => N87
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2_F : LUT4
generic map(
INIT => X"F700"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(1),
I2 => i_pc_prime_5_4_304,
I3 => N70,
O => N108
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW2_G : LUT4
generic map(
INIT => X"FF08"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(1),
I2 => i_pc_prime_5_4_304,
I3 => N70,
O => N109
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4 : MUXF5
port map (
I0 => N110,
I1 => N111,
S => N73,
O => N90
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4_F : LUT4
generic map(
INIT => X"7F00"
)
port map (
I0 => PCreg_q(2),
I1 => PCreg_q(0),
I2 => PCreg_q(1),
I3 => N72,
O => N110
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW4_G : LUT4
generic map(
INIT => X"FF80"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(2),
I2 => PCreg_q(1),
I3 => N72,
O => N111
);
cpu_alu_i_A_in_0_SW2 : LUT4
generic map(
INIT => X"7363"
)
port map (
I0 => N59,
I1 => cpu_alu_A_data_out(0),
I2 => ram_data_i_data_to_ram_not0000_inv,
I3 => cpu_alu_i_arith_S,
O => N114
);
cpu_alu_i_A_in_0_Q : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => cpu_alu_i_stat_S,
I1 => cpu_alu_STAT_data_out_0_Q,
I2 => N114,
O => cpu_alu_i_A_in(0)
);
cpu_alu_ADDER_cell_3_cout1 : LUT4
generic map(
INIT => X"EF8C"
)
port map (
I0 => N57,
I1 => cpu_alu_A_data_out(2),
I2 => ram_data_i_data_to_ram_not0000_inv,
I3 => cpu_alu_N0,
O => cpu_alu_i_MSB_cin
);
cpu_alu_i_A_in_2_Q : LUT4
generic map(
INIT => X"1333"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(2),
I1 => N120,
I2 => cpu_alu_i_A_EN,
I3 => cpu_alu_DECODER_stored_OP_Code(1),
O => cpu_alu_i_A_in(2)
);
i_pc_prime_2_12_SW11 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(2),
I2 => N104,
O => N76
);
i_pc_prime_4_11_SW1 : MUXF5
port map (
I0 => N122,
I1 => N123,
S => adder_16bit_N4,
O => N73
);
i_pc_prime_4_11_SW1_F : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(4),
I2 => PCreg_q(3),
I3 => MEM_q(4),
O => N122
);
i_pc_prime_4_11_SW1_G : LUT4
generic map(
INIT => X"BE14"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(4),
I2 => PCreg_q(3),
I3 => MEM_q(4),
O => N123
);
cpu_alu_i_carry_in : MUXF5
port map (
I0 => N124,
I1 => N125,
S => cpu_alu_i_MSB_cin,
O => cpu_alu_i_carry_in_258
);
cpu_alu_i_carry_in_F : LUT4
generic map(
INIT => X"EC20"
)
port map (
I0 => i_data_frm_ram(3),
I1 => i_hlt,
I2 => cpu_alu_A_data_out(3),
I3 => cpu_alu_STAT_data_out_0_Q,
O => N124
);
cpu_alu_i_carry_in_G : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => i_hlt,
I2 => cpu_alu_STAT_data_out_0_Q,
I3 => i_data_frm_ram(3),
O => N125
);
cpu_alu_i_XORb_in : MUXF5
port map (
I0 => N126,
I1 => N127,
S => cpu_alu_i_MSB_cin,
O => cpu_alu_i_XORb_in_256
);
cpu_alu_i_XORb_in_F : LUT4
generic map(
INIT => X"F3E2"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => i_hlt,
I2 => cpu_alu_STAT_data_out_3_Q,
I3 => i_data_frm_ram(3),
O => N126
);
cpu_alu_i_XORb_in_G : LUT4
generic map(
INIT => X"EC20"
)
port map (
I0 => i_data_frm_ram(3),
I1 => i_hlt,
I2 => cpu_alu_A_data_out(3),
I3 => cpu_alu_STAT_data_out_3_Q,
O => N127
);
Intern_clock_oneHZClock_i_zero_BUFG : BUFG
port map (
I => Intern_clock_oneHZClock_i_zero1,
O => Intern_clock_oneHZClock_i_zero_84
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_231
);
reset_IBUF_BUFG : BUFG
port map (
I => reset_IBUF1,
O => reset_IBUF_354
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_1_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(1),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(1)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_2_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(2),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(2)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_3_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(3),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(3)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_4_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(4),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(4)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_5_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(5),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(5)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_6_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(6),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(6)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_7_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(7),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(7)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_8_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(8),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(8)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_9_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(9),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(9)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_10_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(10),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(10)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_11_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(11),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(11)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_12_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(12),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(12)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_13_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(13),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(13)
);
Intern_clock_kiloHzClock_Mcount_current_count_lut_14_INV_0 : INV
port map (
I => Intern_clock_kiloHzClock_current_count(14),
O => Intern_clock_kiloHzClock_Mcount_current_count_lut(14)
);
cycle_control_unit_Mcount_cycle_counter_xor_0_11_INV_0 : INV
port map (
I => cycle_control_unit_cycle_counter(0),
O => cycle_control_unit_Mcount_cycle_counter
);
MEM_Mcount_i_nibbleCount_xor_0_11_INV_0 : INV
port map (
I => MEM_i_nibbleCount(0),
O => MEM_Mcount_i_nibbleCount
);
Intern_clock_tenHzClock_Mcount_current_count_xor_0_11_INV_0 : INV
port map (
I => Intern_clock_tenHzClock_current_count(0),
O => Intern_clock_tenHzClock_Mcount_current_count
);
Intern_clock_oneHZClock_Mcount_current_count_xor_0_11_INV_0 : INV
port map (
I => Intern_clock_oneHZClock_current_count(0),
O => Intern_clock_oneHZClock_Mcount_current_count
);
Intern_clock_hundredHzClock_Mcount_current_count_xor_0_11_INV_0 : INV
port map (
I => Intern_clock_hundredHzClock_current_count(0),
O => Intern_clock_hundredHzClock_Mcount_current_count
);
cycle_control_unit_received_hlt_0_not00001_INV_0 : INV
port map (
I => cycle_control_unit_received_hlt_276,
O => cycle_control_unit_received_hlt_0_not0000
);
ram_data_3_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(3),
T => ram_data_i_data_to_ram_not0000_inv,
O => N56,
IO => ram_data(3)
);
cpu_alu_A_data_out_3 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(3),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(3)
);
ram_data_2_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(2),
T => ram_data_i_data_to_ram_not0000_inv,
O => N57,
IO => ram_data(2)
);
cpu_alu_A_data_out_2 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(2),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(2)
);
ram_data_1_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(1),
T => ram_data_i_data_to_ram_not0000_inv,
O => N58,
IO => ram_data(1)
);
cpu_alu_A_data_out_1 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(1),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(1)
);
ram_data_0_IOBUF : IOBUF
port map (
I => cpu_alu_A_data_out(0),
T => ram_data_i_data_to_ram_not0000_inv,
O => N59,
IO => ram_data(0)
);
cpu_alu_A_data_out_0 : FDRE
port map (
C => Intern_clock_oneHZClock_i_zero_84,
CE => cpu_alu_i_A_EN,
D => cpu_alu_i_A_in(0),
R => reset_IBUF1,
Q => cpu_alu_A_data_out(0)
);
i_pc_prime_9_351 : LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => adder_16bit_bit6_cout_and0001,
I1 => i_pc_prime_9_9_313,
I2 => adder_16bit_N3,
I3 => PCreg_q(9),
O => i_pc_prime_9_35
);
i_pc_prime_9_35_f5 : MUXF5
port map (
I0 => i_pc_prime_9_35,
I1 => MEM_q(9),
S => i_jmp,
O => i_pc_prime(9)
);
i_pc_prime_10_691 : LUT3
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(10),
I2 => i_pc_prime_10_19_287,
O => i_pc_prime_10_69
);
i_pc_prime_10_692 : LUT4
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(9),
I2 => adder_16bit_N3,
I3 => MEM_q(10),
O => i_pc_prime_10_691_289
);
i_pc_prime_10_69_f5 : MUXF5
port map (
I0 => i_pc_prime_10_691_289,
I1 => i_pc_prime_10_69,
S => PCreg_q(10),
O => i_pc_prime(10)
);
cpu_alu_i_A_in_1_971 : LUT4
generic map(
INIT => X"5F69"
)
port map (
I0 => i_data_frm_ram(1),
I1 => cpu_alu_N18,
I2 => cpu_alu_A_data_out(1),
I3 => cpu_alu_i_arith_S,
O => cpu_alu_i_A_in_1_97
);
cpu_alu_i_A_in_1_97_f5 : MUXF5
port map (
I0 => cpu_alu_i_A_in_1_97,
I1 => cpu_alu_STAT_data_out_1_Q,
S => cpu_alu_i_stat_S,
O => cpu_alu_i_A_in(1)
);
i_pc_prime_7_1 : LUT4
generic map(
INIT => X"BF15"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(6),
I2 => adder_16bit_bit6_cout_and0001,
I3 => MEM_q(7),
O => i_pc_prime_7_1_307
);
i_pc_prime_7_2 : LUT4
generic map(
INIT => X"EC20"
)
port map (
I0 => adder_16bit_bit6_cout_and0001,
I1 => i_jmp,
I2 => PCreg_q(6),
I3 => MEM_q(7),
O => i_pc_prime_7_2_308
);
i_pc_prime_7_f5 : MUXF5
port map (
I0 => i_pc_prime_7_2_308,
I1 => i_pc_prime_7_1_307,
S => PCreg_q(7),
O => i_pc_prime(7)
);
i_pc_prime_8_1 : LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => PCreg_q(8),
I1 => PCreg_q(6),
I2 => PCreg_q(7),
I3 => adder_16bit_bit6_cout_and0001,
O => i_pc_prime_8_1_310
);
i_pc_prime_8_f5 : MUXF5
port map (
I0 => i_pc_prime_8_1_310,
I1 => MEM_q(8),
S => i_jmp,
O => i_pc_prime(8)
);
cpu_alu_i_A_in_3_11 : LUT4
generic map(
INIT => X"7796"
)
port map (
I0 => cpu_alu_A_data_out(3),
I1 => i_data_frm_ram(3),
I2 => cpu_alu_i_MSB_cin,
I3 => cpu_alu_i_arith_S,
O => cpu_alu_i_A_in_3_1
);
cpu_alu_i_A_in_3_1_f5 : MUXF5
port map (
I0 => cpu_alu_i_A_in_3_1,
I1 => cpu_alu_STAT_data_out_3_Q,
S => cpu_alu_i_stat_S,
O => cpu_alu_i_A_in(3)
);
cpu_alu_DECODER_HLT_and000011 : LUT3_D
generic map(
INIT => X"04"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(0),
I1 => cycle_control_unit_exe_268,
I2 => cpu_alu_DECODER_stored_OP_Code(3),
LO => N128,
O => cpu_alu_DECODER_N11
);
i_pc_prime_12_SW1 : LUT3_L
generic map(
INIT => X"B1"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(12),
I2 => MEM_q(12),
LO => N33
);
i_pc_prime_13_SW1 : LUT4_L
generic map(
INIT => X"BE14"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(13),
I2 => PCreg_q(11),
I3 => MEM_q(13),
LO => N39
);
i_pc_prime_0_SW0 : LUT3_L
generic map(
INIT => X"B1"
)
port map (
I0 => i_jmp,
I1 => PCreg_q(0),
I2 => MEM_q(0),
LO => N44
);
cpu_alu_DECODER_WE_SW0 : LUT2_L
generic map(
INIT => X"B"
)
port map (
I0 => cpu_alu_DECODER_stored_OP_Code(3),
I1 => cpu_alu_DECODER_stored_OP_Code(1),
LO => N47
);
i_pc_prime_1_SW0 : LUT4_D
generic map(
INIT => X"AE04"
)
port map (
I0 => i_jmp,
I1 => adder_16bit_N11,
I2 => PCreg_q(1),
I3 => MEM_q(1),
LO => N129,
O => N49
);
adder_16bit_bit6_cout_and00011 : LUT4_D
generic map(
INIT => X"8000"
)
port map (
I0 => PCreg_q(5),
I1 => PCreg_q(3),
I2 => PCreg_q(4),
I3 => adder_16bit_N4,
LO => N130,
O => adder_16bit_bit6_cout_and0001
);
adder_16bit_bit6_Mxor_s_xo_0_21 : LUT4_D
generic map(
INIT => X"AEAA"
)
port map (
I0 => PCreg_q(0),
I1 => PCreg_q(15),
I2 => adder_16bit_N5,
I3 => PCreg_q(14),
LO => N131,
O => adder_16bit_N11
);
adder_16bit_bit15_Mxor_s_xo_0_11 : LUT4_D
generic map(
INIT => X"7FFF"
)
port map (
I0 => adder_16bit_bit11_cout_and0001,
I1 => PCreg_q(11),
I2 => PCreg_q(12),
I3 => PCreg_q(13),
LO => N132,
O => adder_16bit_N5
);
adder_16bit_bit11_Mxor_s_xo_0_11 : LUT4_D
generic map(
INIT => X"7FFF"
)
port map (
I0 => adder_16bit_bit6_cout_and0001,
I1 => PCreg_q(6),
I2 => PCreg_q(7),
I3 => PCreg_q(8),
LO => N133,
O => adder_16bit_N3
);
i_pc_prime_4_17 : LUT3_L
generic map(
INIT => X"20"
)
port map (
I0 => PCreg_q(3),
I1 => PCreg_q(4),
I2 => adder_16bit_N4,
LO => i_pc_prime_4_17_301
);
cpu_alu_i_A_in_1_231 : LUT3_D
generic map(
INIT => X"73"
)
port map (
I0 => N59,
I1 => cpu_alu_A_data_out(0),
I2 => ram_data_i_data_to_ram_not0000_inv,
LO => N134,
O => cpu_alu_N18
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW1 : LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => PCreg_q(0),
I1 => N49,
I2 => N50,
LO => N78
);
adder_16bit_bit1_Mxor_s_xo_0_11_SW3 : LUT3_L
generic map(
INIT => X"D8"
)
port map (
I0 => PCreg_q(0),
I1 => N75,
I2 => N76,
LO => N81
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW1 : LUT4_L
generic map(
INIT => X"EC4C"
)
port map (
I0 => PCreg_q(2),
I1 => N64,
I2 => PCreg_q(1),
I3 => N65,
LO => N85
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW3 : LUT4_L
generic map(
INIT => X"FB40"
)
port map (
I0 => i_pc_prime_5_4_304,
I1 => PCreg_q(1),
I2 => N69,
I3 => N70,
LO => N88
);
adder_16bit_bit3_Mxor_s_xo_0_11_SW5 : LUT4_L
generic map(
INIT => X"F780"
)
port map (
I0 => PCreg_q(2),
I1 => PCreg_q(1),
I2 => N73,
I3 => N72,
LO => N91
);
i_pc_prime_14_35_SW0 : LUT4_L
generic map(
INIT => X"ACA0"
)
port map (
I0 => MEM_q(14),
I1 => i_pc_prime_14_9_295,
I2 => i_jmp,
I3 => adder_16bit_bit11_cout_and0001,
LO => N95
);
i_pc_prime_2_12_SW1_F : LUT3_L
generic map(
INIT => X"F8"
)
port map (
I0 => adder_16bit_N11,
I1 => PCreg_q(1),
I2 => PCreg_q(2),
LO => N104
);
cpu_alu_i_A_in_2_SW0 : LUT4_L
generic map(
INIT => X"8689"
)
port map (
I0 => cpu_alu_A_data_out(2),
I1 => i_data_frm_ram(2),
I2 => cpu_alu_i_arith_S,
I3 => cpu_alu_N0,
LO => N120
);
i_pc_prime_2_12_SW01 : LUT3_D
generic map(
INIT => X"D8"
)
port map (
I0 => i_jmp,
I1 => MEM_q(2),
I2 => N102,
LO => N135,
O => N75
);
end Structure;
| unlicense | 3aab75e33281d4e44a5b4e7f21e53bd4 | 0.565899 | 2.788299 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/demo_tb/tb_nco.vhd | 1 | 8,019 | ---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the DDS Compiler datasheet for further information about this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- named "nco".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile nco.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl nco.ngc nco_netlist.vhd
--
-- Compile nco_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_nco is
end tb_nco;
architecture tb of tb_nco is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data master channel alias signals
signal m_axis_data_tdata_cosine : std_logic_vector(15 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.nco
port map (
aclk => aclk
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Run for long enough to produce 5 periods of outputs
wait for CLOCK_PERIOD * 5;
-- End of test
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_cosine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1';
end tb;
| mit | 7b4c1b4ca01479dbe2752ff6dea0e99e | 0.566031 | 4.968401 | false | false | false | false |
ErikAndren/fpga-sramtest | SramTest.vhd | 1 | 6,888 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.Types.all;
entity SramTest is
port (
RootClk : in bit1;
ARst_N : in bit1;
--
flash_sram_a2 : out bit1;
flash_sram_a3 : out bit1;
flash_sram_a4 : out bit1;
flash_sram_a5 : out bit1;
flash_sram_a6 : out bit1;
flash_sram_a7 : out bit1;
flash_sram_a8 : out bit1;
flash_sram_a9 : out bit1;
flash_sram_a10 : out bit1;
flash_sram_a11 : out bit1;
flash_sram_a12 : out bit1;
flash_sram_a13 : out bit1;
flash_sram_a14 : out bit1;
flash_sram_a15 : out bit1;
flash_sram_a16 : out bit1;
flash_sram_a17 : out bit1;
flash_sram_a18 : out bit1;
flash_sram_a19 : out bit1;
flash_sram_a20 : out bit1;
--
flash_sram_dq0 : inout bit1;
flash_sram_dq1 : inout bit1;
flash_sram_dq2 : inout bit1;
flash_sram_dq3 : inout bit1;
flash_sram_dq4 : inout bit1;
flash_sram_dq5 : inout bit1;
flash_sram_dq6 : inout bit1;
flash_sram_dq7 : inout bit1;
flash_sram_dq8 : inout bit1;
flash_sram_dq9 : inout bit1;
flash_sram_dq10 : inout bit1;
flash_sram_dq11 : inout bit1;
flash_sram_dq12 : inout bit1;
flash_sram_dq13 : inout bit1;
flash_sram_dq14 : inout bit1;
flash_sram_dq15 : inout bit1;
flash_sram_dq16 : inout bit1;
flash_sram_dq17 : inout bit1;
flash_sram_dq18 : inout bit1;
flash_sram_dq19 : inout bit1;
flash_sram_dq20 : inout bit1;
flash_sram_dq21 : inout bit1;
flash_sram_dq22 : inout bit1;
flash_sram_dq23 : inout bit1;
flash_sram_dq24 : inout bit1;
flash_sram_dq25 : inout bit1;
flash_sram_dq26 : inout bit1;
flash_sram_dq27 : inout bit1;
flash_sram_dq28 : inout bit1;
flash_sram_dq29 : inout bit1;
flash_sram_dq30 : inout bit1;
flash_sram_dq31 : inout bit1;
--
sram_oe_n : out bit1;
sram_ce1_n : out bit1;
sram_we : out bit1;
sram_be_n0 : out bit1;
sram_be_n1 : out bit1;
sram_be_n2 : out bit1;
sram_be_n3 : out bit1;
sram_adsc : out bit1;
sram_clk : out bit1;
--
Btn0 : in bit1;
Btn1 : in bit1;
Btn2 : in bit1;
Btn3 : in bit1;
--
Led0 : out bit1;
Led1 : out bit1;
Led2 : out bit1;
Led3 : out bit1
);
end entity SramTest;
architecture rtl of SramTest is
constant AddrW : positive := 19;
constant DataW : positive := 32;
--
signal Clk : bit1;
signal Rst_N : bit1;
--
signal SramAddr : word(AddrW-1 downto 0);
signal SramDataOut : word(DataW-1 downto 0);
signal SramWe : bit1;
signal SramRe : bit1;
signal SramDataIn : word(DataW-1 downto 0);
begin
RstSync : entity work.ResetSync
port map (
Clk => Clk,
AsyncRst => ARst_N,
--
Rst_N => Rst_N
);
ClkPll0 : entity work.ClkPll
Port map (
inclk0 => RootClk,
c0 => Clk
);
StimGen : entity work.SramTestGen
generic map (
AddrW => AddrW,
DataW => DataW
)
port map (
Clk => Clk,
Rst_N => Rst_N,
--
Btn0 => Btn0,
Btn1 => Btn1,
Btn2 => Btn2,
Btn3 => Btn3,
--
We => SramWe,
Re => SramRe,
Addr => SramAddr,
Data => SramDataOut
);
-- Leds are active low
Led0 <= SramDataIn(0);
Led1 <= SramDataIn(1);
Led2 <= SramDataIn(2);
Led3 <= SramDataIn(3);
SramControl : entity work.SramController
generic map (
AddrW => AddrW,
DataW => DataW
)
port map (
Clk => Clk,
Rst_N => Rst_N,
-- Internal interface
Addr => SramAddr,
D => SramDataOut,
We => SramWe,
Re => SramRe,
Q => SramDataIn,
-- External interface
flash_sram_a2 => flash_sram_a2,
flash_sram_a3 => flash_sram_a3,
flash_sram_a4 => flash_sram_a4,
flash_sram_a5 => flash_sram_a5,
flash_sram_a6 => flash_sram_a6,
flash_sram_a7 => flash_sram_a7,
flash_sram_a8 => flash_sram_a8,
flash_sram_a9 => flash_sram_a9,
flash_sram_a10 => flash_sram_a10,
flash_sram_a11 => flash_sram_a11,
flash_sram_a12 => flash_sram_a12,
flash_sram_a13 => flash_sram_a13,
flash_sram_a14 => flash_sram_a14,
flash_sram_a15 => flash_sram_a15,
flash_sram_a16 => flash_sram_a16,
flash_sram_a17 => flash_sram_a17,
flash_sram_a18 => flash_sram_a18,
flash_sram_a19 => flash_sram_a19,
flash_sram_a20 => flash_sram_a20,
--
flash_sram_dq0 => flash_sram_dq0,
flash_sram_dq1 => flash_sram_dq1,
flash_sram_dq2 => flash_sram_dq2,
flash_sram_dq3 => flash_sram_dq3,
flash_sram_dq4 => flash_sram_dq4,
flash_sram_dq5 => flash_sram_dq5,
flash_sram_dq6 => flash_sram_dq6,
flash_sram_dq7 => flash_sram_dq7,
flash_sram_dq8 => flash_sram_dq8,
flash_sram_dq9 => flash_sram_dq9,
flash_sram_dq10 => flash_sram_dq10,
flash_sram_dq11 => flash_sram_dq11,
flash_sram_dq12 => flash_sram_dq12,
flash_sram_dq13 => flash_sram_dq13,
flash_sram_dq14 => flash_sram_dq14,
flash_sram_dq15 => flash_sram_dq15,
flash_sram_dq16 => flash_sram_dq16,
flash_sram_dq17 => flash_sram_dq17,
flash_sram_dq18 => flash_sram_dq18,
flash_sram_dq19 => flash_sram_dq19,
flash_sram_dq20 => flash_sram_dq20,
flash_sram_dq21 => flash_sram_dq21,
flash_sram_dq22 => flash_sram_dq22,
flash_sram_dq23 => flash_sram_dq23,
flash_sram_dq24 => flash_sram_dq24,
flash_sram_dq25 => flash_sram_dq25,
flash_sram_dq26 => flash_sram_dq26,
flash_sram_dq27 => flash_sram_dq27,
flash_sram_dq28 => flash_sram_dq28,
flash_sram_dq29 => flash_sram_dq29,
flash_sram_dq30 => flash_sram_dq30,
flash_sram_dq31 => flash_sram_dq31,
--
sram_oe => sram_oe_n,
sram_ce1_n => sram_ce1_n,
sram_we => sram_we,
sram_be_n0 => sram_be_n0,
sram_be_n1 => sram_be_n1,
sram_be_n2 => sram_be_n2,
sram_be_n3 => sram_be_n3,
sram_adsc => sram_adsc,
sram_clk => sram_clk
);
end architecture;
| mit | e954f8bd2565d84fa740bf08c41b4474 | 0.513937 | 3.00786 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/sounds_mem/simulation/bmg_stim_gen.vhd | 2 | 12,572 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (15 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"sounds_mem.mif",
DEFAULT_DATA,
32,
16);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 9dd5c72edf00df8298d51d5342e60e4a | 0.547407 | 3.682484 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/sounds_mem/example_design/sounds_mem_prod.vhd | 2 | 9,916 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: sounds_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : sounds_mem.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 16
-- C_READ_DEPTH_A : 16
-- C_ADDRA_WIDTH : 4
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 16
-- C_READ_DEPTH_B : 16
-- C_ADDRB_WIDTH : 4
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY sounds_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END sounds_mem_prod;
ARCHITECTURE xilinx OF sounds_mem_prod IS
COMPONENT sounds_mem_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : sounds_mem_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | d888d96258a29783d8d953d6ce536e8d | 0.494756 | 3.816782 | false | false | false | false |
ErikAndren/fpga-sramtest | SramController.vhd | 1 | 8,064 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.Types.all;
entity SramController is
generic (
AddrW : positive;
DataW : positive
);
port (
Clk : in bit1;
Rst_N : in bit1;
-- Internal interface
Addr : in word(AddrW-1 downto 0);
D : in word(DataW-1 downto 0);
We : in bit1;
Re : in bit1;
Q : out word(32-1 downto 0);
-- External interface
flash_sram_a2 : out bit1;
flash_sram_a3 : out bit1;
flash_sram_a4 : out bit1;
flash_sram_a5 : out bit1;
flash_sram_a6 : out bit1;
flash_sram_a7 : out bit1;
flash_sram_a8 : out bit1;
flash_sram_a9 : out bit1;
flash_sram_a10 : out bit1;
flash_sram_a11 : out bit1;
flash_sram_a12 : out bit1;
flash_sram_a13 : out bit1;
flash_sram_a14 : out bit1;
flash_sram_a15 : out bit1;
flash_sram_a16 : out bit1;
flash_sram_a17 : out bit1;
flash_sram_a18 : out bit1;
flash_sram_a19 : out bit1;
flash_sram_a20 : out bit1;
--
flash_sram_dq0 : inout bit1;
flash_sram_dq1 : inout bit1;
flash_sram_dq2 : inout bit1;
flash_sram_dq3 : inout bit1;
flash_sram_dq4 : inout bit1;
flash_sram_dq5 : inout bit1;
flash_sram_dq6 : inout bit1;
flash_sram_dq7 : inout bit1;
flash_sram_dq8 : inout bit1;
flash_sram_dq9 : inout bit1;
flash_sram_dq10 : inout bit1;
flash_sram_dq11 : inout bit1;
flash_sram_dq12 : inout bit1;
flash_sram_dq13 : inout bit1;
flash_sram_dq14 : inout bit1;
flash_sram_dq15 : inout bit1;
flash_sram_dq16 : inout bit1;
flash_sram_dq17 : inout bit1;
flash_sram_dq18 : inout bit1;
flash_sram_dq19 : inout bit1;
flash_sram_dq20 : inout bit1;
flash_sram_dq21 : inout bit1;
flash_sram_dq22 : inout bit1;
flash_sram_dq23 : inout bit1;
flash_sram_dq24 : inout bit1;
flash_sram_dq25 : inout bit1;
flash_sram_dq26 : inout bit1;
flash_sram_dq27 : inout bit1;
flash_sram_dq28 : inout bit1;
flash_sram_dq29 : inout bit1;
flash_sram_dq30 : inout bit1;
flash_sram_dq31 : inout bit1;
--
sram_oe : out bit1;
sram_ce1_n : out bit1;
sram_we : out bit1;
sram_be_n0 : out bit1;
sram_be_n1 : out bit1;
sram_be_n2 : out bit1;
sram_be_n3 : out bit1;
-- Adsc controls address latching
sram_adsc : out bit1;
sram_clk : out bit1
);
end entity SramController;
architecture rtl of SramController is
signal sram_be_n, sram_be_d : bit1;
signal sram_oe_n, sram_oe_d : bit1;
signal sram_addr : word(AddrW-1 downto 0);
signal sram_we_n, sram_we_d : bit1;
signal sram_dq, sram_dq_d, sram_dq_rec : word(DataW-1 downto 0);
begin -- rtl
SramClkFeed : sram_clk <= Clk;
SramAddrFeed : sram_addr <= Addr(AddrW-1 downto 0);
QFeed : Q <= sram_dq_rec;
CmdDec : process (We, Re)
begin
sram_oe_n <= '1';
sram_ce1_n <= '1';
sram_we_n <= '1';
sram_be_n <= '1';
sram_adsc <= '1';
if (We = '1') then
sram_ce1_n <= '0';
sram_we_n <= '0';
sram_be_n <= '0';
sram_oe_n <= '1';
sram_adsc <= '0';
end if;
if (Re = '1') then
sram_ce1_n <= '0';
sram_we_n <= '1';
sram_oe_n <= '0';
sram_be_n <= '1';
sram_adsc <= '0';
end if;
end process;
CmdFlop : process (Clk, Rst_N)
begin -- process CmdFlop
if Rst_N = '0' then -- asynchronous reset (active low)
sram_we_d <= '1';
sram_be_d <= '1';
sram_oe_d <= '1';
elsif rising_edge(Clk) then
sram_we_d <= sram_we_n;
sram_be_d <= sram_be_n;
sram_oe_d <= sram_oe_n;
if sram_oe_d = '0' then
sram_dq_rec <= sram_dq;
else
sram_dq_d <= D;
end if;
end if;
end process CmdFlop;
sram_be_n0 <= sram_be_d;
sram_be_n1 <= sram_be_d;
sram_be_n2 <= sram_be_d;
sram_be_n3 <= sram_be_d;
sram_we <= sram_we_d;
sram_oe <= sram_oe_d;
flash_sram_dq0 <= sram_dq_d(0) when sram_oe_d = '1' else 'Z';
flash_sram_dq1 <= sram_dq_d(1) when sram_oe_d = '1' else 'Z';
flash_sram_dq2 <= sram_dq_d(2) when sram_oe_d = '1' else 'Z';
flash_sram_dq3 <= sram_dq_d(3) when sram_oe_d = '1' else 'Z';
flash_sram_dq4 <= sram_dq_d(4) when sram_oe_d = '1' else 'Z';
flash_sram_dq5 <= sram_dq_d(5) when sram_oe_d = '1' else 'Z';
flash_sram_dq6 <= sram_dq_d(6) when sram_oe_d = '1' else 'Z';
flash_sram_dq7 <= sram_dq_d(7) when sram_oe_d = '1' else 'Z';
flash_sram_dq8 <= sram_dq_d(8) when sram_oe_d = '1' else 'Z';
flash_sram_dq9 <= sram_dq_d(9) when sram_oe_d = '1' else 'Z';
flash_sram_dq10 <= sram_dq_d(10) when sram_oe_d = '1' else 'Z';
flash_sram_dq11 <= sram_dq_d(11) when sram_oe_d = '1' else 'Z';
flash_sram_dq12 <= sram_dq_d(12) when sram_oe_d = '1' else 'Z';
flash_sram_dq13 <= sram_dq_d(13) when sram_oe_d = '1' else 'Z';
flash_sram_dq14 <= sram_dq_d(14) when sram_oe_d = '1' else 'Z';
flash_sram_dq15 <= sram_dq_d(15) when sram_oe_d = '1' else 'Z';
flash_sram_dq16 <= sram_dq_d(16) when sram_oe_d = '1' else 'Z';
flash_sram_dq17 <= sram_dq_d(17) when sram_oe_d = '1' else 'Z';
flash_sram_dq18 <= sram_dq_d(18) when sram_oe_d = '1' else 'Z';
flash_sram_dq19 <= sram_dq_d(19) when sram_oe_d = '1' else 'Z';
flash_sram_dq20 <= sram_dq_d(20) when sram_oe_d = '1' else 'Z';
flash_sram_dq21 <= sram_dq_d(21) when sram_oe_d = '1' else 'Z';
flash_sram_dq22 <= sram_dq_d(22) when sram_oe_d = '1' else 'Z';
flash_sram_dq23 <= sram_dq_d(23) when sram_oe_d = '1' else 'Z';
flash_sram_dq24 <= sram_dq_d(24) when sram_oe_d = '1' else 'Z';
flash_sram_dq25 <= sram_dq_d(25) when sram_oe_d = '1' else 'Z';
flash_sram_dq26 <= sram_dq_d(26) when sram_oe_d = '1' else 'Z';
flash_sram_dq27 <= sram_dq_d(27) when sram_oe_d = '1' else 'Z';
flash_sram_dq28 <= sram_dq_d(28) when sram_oe_d = '1' else 'Z';
flash_sram_dq29 <= sram_dq_d(29) when sram_oe_d = '1' else 'Z';
flash_sram_dq30 <= sram_dq_d(30) when sram_oe_d = '1' else 'Z';
flash_sram_dq31 <= sram_dq_d(31) when sram_oe_d = '1' else 'Z';
--
sram_dq <= flash_sram_dq31 &
flash_sram_dq30 &
flash_sram_dq29 &
flash_sram_dq28 &
flash_sram_dq27 &
flash_sram_dq26 &
flash_sram_dq25 &
flash_sram_dq24 &
flash_sram_dq23 &
flash_sram_dq22 &
flash_sram_dq21 &
flash_sram_dq20 &
flash_sram_dq19 &
flash_sram_dq18 &
flash_sram_dq17 &
flash_sram_dq16 &
flash_sram_dq15 &
flash_sram_dq14 &
flash_sram_dq13 &
flash_sram_dq12 &
flash_sram_dq11 &
flash_sram_dq10 &
flash_sram_dq9 &
flash_sram_dq8 &
flash_sram_dq7 &
flash_sram_dq6 &
flash_sram_dq5 &
flash_sram_dq4 &
flash_sram_dq3 &
flash_sram_dq2 &
flash_sram_dq1 &
flash_sram_dq0;
flash_sram_a2 <= sram_addr(0);
flash_sram_a3 <= sram_addr(1);
flash_sram_a4 <= sram_addr(2);
flash_sram_a5 <= sram_addr(3);
flash_sram_a6 <= sram_addr(4);
flash_sram_a7 <= sram_addr(5);
flash_sram_a8 <= sram_addr(6);
flash_sram_a9 <= sram_addr(7);
flash_sram_a10 <= sram_addr(8);
flash_sram_a11 <= sram_addr(9);
flash_sram_a12 <= sram_addr(10);
flash_sram_a13 <= sram_addr(11);
flash_sram_a14 <= sram_addr(12);
flash_sram_a15 <= sram_addr(13);
flash_sram_a16 <= sram_addr(14);
flash_sram_a17 <= sram_addr(15);
flash_sram_a18 <= sram_addr(16);
flash_sram_a19 <= sram_addr(17);
flash_sram_a20 <= sram_addr(18);
end rtl;
| mit | 4cedbb40082c60be43e1067a81634d5f | 0.533234 | 2.63788 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/CPU-TopLevel.vhd | 1 | 6,764 | ----------------------------------------------------------------------------------
-- Company: Nibble Knowledge
-- Engineer: Colton Schmidt
--
-- Create Date: 10:41:09 10/15/2015
-- Design Name:
-- Module Name: CPU-TopLevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU is
Port ( clk : in STD_LOGIC;
reset : in STD_Logic;
hlt_out : out STD_LOGIC;
clk_out : out std_logic;
--for testing A value
a_data : out STD_LOGIC_VECTOR (3 downto 0);
ram_data : inout STD_LOGIC_VECTOR (3 downto 0);
ram_address : out STD_LOGIC_VECTOR (15 downto 0);
ram_write_enable : out STD_LOGIC;
bus_ready : in STD_LOGIC;
oe : out STD_LOGIC;
bus_parity : in STD_LOGIC;
bus_status_out : out STD_LOGIC_VECTOR(1 downto 0);
bus_data : inout STD_LOGIC_VECTOR(3 downto 0);
bus_chip_select : out STD_LOGIC_VECTOR(3 downto 0);
read_mode : in STD_LOGIC);
end CPU;
architecture Behavioral of CPU is
component io_mapping is
Port ( address : in STD_LOGIC_VECTOR (15 downto 0);
data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
ram_data : inout STD_LOGIC_VECTOR (3 downto 0);
bus_chip_select : out STD_LOGIC_VECTOR (3 downto 0); -- The chip select lines from the bus
store : in STD_LOGIC;
bus_data : inout STD_LOGIC_VECTOR (3 downto 0); -- The data lines from the bus
bus_ready : in STD_LOGIC; --Ready from the bus
bus_status_out : out STD_LOGIC_VECTOR(1 downto 0);
oe : out STD_LOGIC;
bus_parity : in STD_LOGIC; --Parity from the bus
clk : in STD_LOGIC;
rst : in STD_LOGIC;
read_mode : in STD_LOGIC
);
end component;
component register16 is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC);
end component;
component bitadder_16 is
Port ( x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
s0 : out std_logic_vector(15 downto 0));
end component;
component alu_complete is
Port ( exe : in STD_LOGIC;
OP_EN : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (3 downto 0);
WE : out STD_LOGIC;
JMP : out STD_LOGIC;
HLT : out STD_LOGIC;
STR : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
clk_fast : in std_logic;
rst : in STD_LOGIC);
end component;
component control_unit_V2 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
hlt : in STD_LOGIC;
exe : out STD_LOGIC;
op_en : out STD_LOGIC;
mem_en : out STD_LOGIC;
pc_en : out STD_LOGIC);
end component;
component register16_with_we is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (15 downto 0);
q : out STD_LOGIC_VECTOR (15 downto 0);
we : in STD_LOGIC);
end component;
component clock_divider_V2 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end component;
-- Internal Signals --
-- Clock Divider Signals --
signal i_clk : std_logic;
-- Control Unit Signals
signal i_op_en : std_logic;
signal i_exe : std_logic;
signal i_mem_en: std_logic;
signal i_pc_en : std_logic;
-- RAM signals
signal i_data_frm_ram: std_logic_vector(3 downto 0);
signal i_data_to_ram : std_logic_vector(3 downto 0);
signal i_ram_address : std_logic_vector(15 downto 0);
signal i_ram_we : std_logic;
-- PC reg signals
signal i_pc_prime : std_logic_vector(15 downto 0);
signal i_pc : std_logic_vector(15 downto 0);
signal i_incmtd_pc: std_logic_vector(15 downto 0);
-- MEM reg signals
signal i_mem_addr : std_logic_vector(15 downto 0);
-- ALU Signals
signal i_hlt : std_logic;
signal i_jmp : std_logic;
signal i_pc_en_after_or :std_logic;
signal i_str : std_logic;
-- other signals
signal i_received_hlt : std_logic;
begin
IOMAP: io_mapping
Port map( address => i_ram_address,
data_in => i_data_to_ram,
data_out => i_data_frm_ram,
ram_data => ram_data,
bus_chip_select => bus_chip_select,
store => i_str,
bus_data => bus_data, -- The data lines from the bus
bus_ready => bus_ready, --Ready from the bus
oe => oe,
bus_status_out => bus_status_out,
bus_parity => bus_parity,
clk => i_clk,
rst => reset,
read_mode => read_mode
);
MEM: register16
Port map( clk => i_clk,
reset => reset,
d => i_data_frm_ram,
q => i_mem_addr,
load => i_mem_en);
adder_16bit: bitadder_16
Port map( x => i_pc,
y => "0000000000000001",
s0 => i_incmtd_pc);
cpu_alu: alu_complete
Port map( clk => i_clk,
clk_fast => clk,
rst => reset,
OP_EN => i_op_en,
exe => i_exe,
data_in => i_data_frm_ram,
data_out => i_data_to_ram,
JMP => i_jmp,
HLT => i_hlt,
WE => i_ram_we,
STR => i_str);
cycle_control_unit: control_unit_V2
Port map( clk => i_clk,
reset => reset,
hlt => i_hlt,
exe => i_exe,
op_en => i_op_en,
mem_en => i_mem_en,
pc_en => i_pc_en);
PCreg: register16_with_we
Port map( clk => i_clk,
reset => reset,
d => i_pc_prime,
q => i_pc,
we => i_pc_en_after_or);
Intern_clock: clock_divider_V2
Port map( clk => clk,
reset => reset,
clk_out => i_clk);
-- Jump Mux
i_pc_prime <= i_mem_addr when (i_jmp = '1') else i_incmtd_pc;
-- Ram Access Mux
i_ram_address <= i_mem_addr when (i_exe = '1') else i_pc;
--Enable for PC
i_pc_en_after_or <= i_pc_en OR i_jmp;
-- RAM signals
ram_address <= i_ram_address;
ram_write_enable <= i_ram_we;
hlt_out <= i_received_hlt;
a_data <= i_data_to_ram;
clk_out <= i_clk;
process( clk )
begin
if( i_hlt = '1' )then
i_received_hlt <= '1';
elsif ( reset = '1' ) then
i_received_hlt <= '0';
end if;
end process;
end Behavioral;
| unlicense | cff219bc55685f47b7e3ee241b92175e | 0.57126 | 2.839631 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/tb_register16.vhd | 1 | 3,250 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:40:19 10/22/2015
-- Design Name:
-- Module Name: C:/Users/Colton/Nibble_Knowledge_CPU/tb_register16.vhd
-- Project Name: Nibble_Knowledge_CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register16
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_register16 IS
END tb_register16;
ARCHITECTURE behavior OF tb_register16 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register16
PORT(
d : IN std_logic_vector(3 downto 0);
q : OUT std_logic_vector(15 downto 0);
clk : IN std_logic;
reset : IN std_logic;
load : IN std_logic
);
END COMPONENT;
--Inputs
signal d : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal load : std_logic := '0';
--Outputs
signal q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register16 PORT MAP (
d => d,
q => q,
clk => clk,
reset => reset,
load => load
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
-- insert stimulus here
-- Load nibble3
load <= '1';
d <= "0011";
-- Load nibble2
wait for clk_period;
d <= "0010";
-- Load nibble1
wait for clk_period;
d <= "0001";
-- Load nibble0
wait for clk_period;
d <= "1010";
wait for clk_period;
load <= '0';
-- Simulate Junk
-- execute stage
d <= "1101";
wait for clk_period;
-- op code stage
d <= "1001";
wait for clk_period;
-- new address
-- Load nibble3
load <= '1';
d <= "1100";
-- Load nibble2
wait for clk_period;
d <= "0100";
-- Load nibble1
wait for clk_period;
d <= "1000";
-- Load nibble0
wait for clk_period;
d <= "0101";
wait for clk_period;
load <= '0';
-- Simulate Junk
-- execute stage
d <= "1111";
wait for clk_period;
-- op code stage
d <= "1101";
wait;
end process;
END;
| unlicense | e31b86effb5dc14fd77a42b299eb166a | 0.568 | 3.559693 | false | false | false | false |
aleksandar-mitrevski/hw_sw | filtered_edge_detector/filtered_edge_detector.vhd | 1 | 3,324 | library ieee;
use ieee.std_logic_1164.all;
entity FilteredEdgeDetector is port (
clk, reset: in std_logic;
level : in std_logic;
levelFiltered : inout std_logic;
tick : out std_logic);
end FilteredEdgeDetector;
architecture filtered_edge_detector of FilteredEdgeDetector is
------------------------------------------------
--! Edge detector local signals
------------------------------------------------
-- Moore machine states
type state_type is (zero, edge, one);
signal state_reg, state_next : state_type;
------------------------------------------------
--! Filter local signals
------------------------------------------------
-- shift register outputs
signal q1 : std_logic := '0';
signal q2 : std_logic := '0';
signal q3 : std_logic := '0';
signal q4 : std_logic := '0';
-- jk flip flop output
signal q : std_logic := '0';
signal q_not : std_logic := '1';
begin
------------------------------------------------
--! Updates the flip flops in the shift register
------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
q4 <= q3;
q3 <= q2;
q2 <= q1;
q1 <= level;
end if;
end process;
------------------------------------------------
--! Updates the filter's jk flip flop
------------------------------------------------
process(q1,q2,q3,q4)
variable j : std_logic := '0';
variable k : std_logic := '0';
begin
j := q2 and q3 and q4;
k := (not q2) and (not q3) and (not q4);
if j = '0' and k = '1' then
q <= '0';
elsif j = '1' and k = '0' then
q <= '1';
elsif j = '1' and k = '1' then
q <= q_not;
end if;
end process;
q_not <= not q;
------------------------------------------------
--! Outputs the value of the filter
------------------------------------------------
process(q)
begin
levelFiltered <= q;
end process;
------------------------------------------------
--! Updates the state of the edge detector
------------------------------------------------
process(clk, reset)
begin
if reset='1' then
state_reg <= zero;
elsif rising_edge(clk) then
state_reg <= state_next;
end if;
end process;
------------------------------------------------
--! Updates the next state of the edge detector
--! and outputs the detector value
------------------------------------------------
process(state_reg, levelFiltered)
begin
state_next <= state_reg;
tick <= '0';
case state_reg is
when zero =>
if levelFiltered = '1' then
state_next <= edge;
end if;
when edge =>
tick <= '1';
if levelFiltered = '1' then
state_next <= one;
else
state_next <= zero;
end if;
when one =>
if levelFiltered = '0' then
state_next <= zero;
end if;
end case;
end process;
end filtered_edge_detector; | mit | 29d985c78f73a7462e4a4bb2d9ee9ef0 | 0.391697 | 4.81042 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/PC_RegHold_Falling.vhd | 1 | 2,300 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: 24bit_Register
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
-- 24 bit register with a hold lock the input state just
-- incase input conflict later
--
-- Notes:
-- HOLD Clocked on FALLING EDGE
-- OUTPUT Clocked on rising EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
-- 0.05 - Forked and added a input hold for the register
-- 0.06 - Forked and used as a PC register
--
-- Additional Comments:
-- The register latches it's output data on the Rising edge
-- Hold latch on the falling edge
-- The main reason why I included a hold latch was to Prevent
-- Any register transfer faults that could occur.
-- Mostly acts as a safety buffer.
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY PC_RegHold_F IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(PC_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(PC_WIDTH-1 DOWNTO 0)
);
END PC_RegHold_F;
ARCHITECTURE Behavior OF PC_RegHold_F IS
SIGNAL HOLD : STD_LOGIC_VECTOR(PC_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
HOLD <= (OTHERS => '0');
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= HOLD;
END IF;
IF Clock'EVENT AND Clock = '0' THEN
HOLD <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 4109167a789a06c437d5fc0a7d791f35 | 0.561304 | 3.616352 | false | false | false | false |
sgstair/ledsign | firmware/matrixdriver/usb_phy.vhd | 1 | 21,698 | --
-- This source is released under the MIT License (MIT)
--
-- Copyright (c) 2016 Stephen Stair ([email protected])
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity usb_phy is
port (
sysclk : in std_logic;
rst : in std_logic;
-- USB Physical interface
usb_dp : inout std_logic;
usb_dm : inout std_logic;
-- USB Reset
usb_reset : out std_logic; -- Indication that we received a reset signal
usb_hold_reset : in std_logic; -- Hold reset of the lower level high until this layer says it's ok to continue.
-- Transmit interface
usbtx_byte : in std_logic_vector(7 downto 0);
usbtx_sendbyte : in std_logic;
usbtx_lastbyte : in std_logic;
usbtxs_cansend : out std_logic;
usbtxs_abort : out std_logic;
usbtxs_sending : out std_logic;
usbtxs_underrunerror : out std_logic;
-- Receive interface
usbrx_byte : out std_logic_vector(7 downto 0);
usbrx_nextbyte : out std_logic;
usbrx_packetend : out std_logic;
usbrx_crcerror : out std_logic;
usbrx_bitstufferror : out std_logic;
usbrx_eopmissing : out std_logic;
usbrx_piderror : out std_logic;
usbrx_incomplete : out std_logic;
usbrx_syncerror : out std_logic;
usbrx_error : out std_logic
);
end usb_phy;
architecture a of usb_phy is
signal usb_stable : std_logic;
signal usb_validbit : std_logic;
signal usb_se0 : std_logic;
signal usb_bit : std_logic;
signal usb_buffer : std_logic_vector(7 downto 0);
signal usb_drivebit : std_logic;
signal usb_drivese0 : std_logic;
signal usb_out : std_logic;
signal usbi_ringpulse : std_logic;
signal usbi_ring : std_logic_vector(4 downto 0);
signal usbi_ringnext : std_logic;
signal usbi_rxactive : std_logic;
signal usbi_txactive : std_logic;
signal usbi_pid : std_logic_vector(3 downto 0);
signal usbi_lastbits : std_logic_vector(5 downto 0);
signal usbi_crc5 : std_logic_vector(4 downto 0);
signal usbi_crc16 : std_logic_vector(15 downto 0);
signal usbi_crcbit : std_logic;
signal usbi_crcenable : std_logic;
signal usbi_crcreset : std_logic;
signal usbi_crc5ok : std_logic;
signal usbi_crc16ok : std_logic;
signal usbi_rxcrcvalid : std_logic;
signal usbi_rxcrclastvalid : std_logic;
signal usbi_crcengaged : std_logic;
signal usbi_usingcrc : std_logic;
signal usbi_usecrc16 : std_logic;
signal usbi_bytebuffered : std_logic;
signal usbi_receivedlastbyte : std_logic;
signal usbi_byte : std_logic_vector(7 downto 0);
signal usbi_bit : unsigned(2 downto 0);
signal usbi_tempbyte : std_logic_vector(7 downto 0);
signal usbi_decide : std_logic;
signal usbi_decide_next : std_logic;
signal usbi_rxlevel : std_logic;
signal usbi_resetring : std_logic_vector(4 downto 0);
signal usbi_resetcounter : unsigned(4 downto 0);
signal usbi_bitstufferrordetected : std_logic;
signal usbi_rxwaitforeop : std_logic;
signal usbi_rxbytetemp : std_logic_vector(7 downto 0);
signal usbi_rxbytevalid : std_logic;
signal usbrx_ipacketend : std_logic;
signal usbrx_ierror : std_logic;
signal usbtxs_icansend : std_logic;
signal usbrx_inextbyte : std_logic;
-- The following error fields are cleared at the start of a packet, flagged immediately upon hitting them, and guaranteed to be accurate when packetend pulses.
signal usbrxi_crcerror : std_logic; -- Packet was terminated early due to CRC error
signal usbrxi_bitstufferror : std_logic; -- Packet was terminated early due to bit stuffing error
signal usbrxi_eopmissing : std_logic; -- Packet was terminated because it was too long.
signal usbrxi_piderror : std_logic; -- PID field is incorrect (compliment mismatch) - This may also lead to an incorrect CRC error from using the wrong CRC.
signal usbrxi_incomplete : std_logic; -- Packet was obviously incomplete (not a multiple of 8 bits)
signal usbrxi_syncerror: std_logic; -- Packet sync field was not correct.
signal usbrxi_byte : std_logic_vector(7 downto 0);
type usb_state is (sync, pid, content, crc1, crc2, eop );
signal usbrxstate : usb_state;
signal usbtxstate : usb_state;
begin
usbrx_packetend <= usbrx_ipacketend;
usbrx_nextbyte <= usbrx_inextbyte;
usbrx_error <= usbrx_ierror;
usbtxs_cansend <= usbtxs_icansend;
usbrx_byte <= usbrxi_byte;
-- USB front end
process(sysclk, rst)
variable buffer_dp : std_logic;
variable buffer_dm : std_logic;
variable temp : std_logic_vector(1 downto 0);
begin
if rst = '1' then
usb_validbit <= '0';
usb_se0 <= '0';
usb_bit <= '0';
usb_buffer <= (others => '0');
usb_stable <= '0';
usb_dp <= 'Z';
usb_dm <= 'Z';
elsif sysclk'event and sysclk='1' then
buffer_dp := usb_buffer(5);
buffer_dm := usb_buffer(4);
usb_validbit <= '0';
usb_se0 <= '0';
usb_bit <= '0';
temp(1) := buffer_dp;
temp(0) := buffer_dm;
-- Simulation helper
if(temp(0) = 'H') then
temp(0) := '1';
end if;
if(temp(0) = 'L') then
temp(0) := '0';
end if;
if(temp(1) = 'H') then
temp(1) := '1';
end if;
if(temp(1) = 'L') then
temp(1) := '0';
end if;
case (temp) is
when "00" => usb_se0 <= '1';
when "01" => usb_validbit <= '1'; usb_bit <= '0';
when "10" => usb_validbit <= '1'; usb_bit <= '1';
when "11" =>
when others =>
end case;
usb_stable <= '0';
if(usb_buffer(7 downto 6) = usb_buffer(5 downto 4)) then
usb_stable <= '1';
end if;
if(usb_drivebit = '1') then
usb_dp <= usb_out;
usb_dm <= not usb_out;
elsif(usb_drivese0 = '1') then
usb_dp <= '0';
usb_dm <= '0';
else
usb_dp <= 'Z';
usb_dm <= 'Z';
end if;
usb_buffer <= usb_buffer(5 downto 0) & usb_dp & usb_dm;
-- DP in 7, DM in 6
end if;
end process;
-- Rx/Tx. This section translates the USB interface to a byte stream, handles bit stuffing and identifies/generates CRC.
-- This section makes only the most limited attempt to decode the USB packets, just provides the overall byte stream sending and receiving.
-- The CRC values are checked internally and included in the data byte stream. (CRC5 vs CRC16 is determined from the PID field)
-- Outgoing data automatically generates CRC5 and CRC16 depending on PID.
usbrx_crcerror <= usbrxi_crcerror;
usbrx_bitstufferror <= usbrxi_bitstufferror;
usbrx_eopmissing <= usbrxi_eopmissing;
usbrx_piderror <= usbrxi_piderror;
usbrx_incomplete <= usbrxi_incomplete;
usbrx_syncerror <= usbrxi_syncerror;
usbrx_ierror <= usbrxi_crcerror or usbrxi_bitstufferror or usbrxi_eopmissing or usbrxi_piderror or usbrxi_incomplete or usbrxi_syncerror;
-- Ring is a 5-bit shift register clock divider configurable to restart at a specific time.
-- pulse usbi_ringnext to 1 to cause ring(0) to be high next cycle, and every 5th cycle after that.
usbi_ringpulse <= usbi_ringnext or usbi_ring(0);
process(sysclk, rst)
begin
if rst = '1' then
usbi_ring <= (others => '0');
elsif sysclk'event and sysclk='1' then
if usbi_ringnext = '1' then
usbi_ring (1 downto 0) <= "10";
elsif(usbi_ring(3 downto 0) = "0000") then
usbi_ring <= usbi_ring(3 downto 0) & '1';
else
usbi_ring <= usbi_ring(3 downto 0) & '0';
end if;
end if;
end process;
-- Reset detection logic
process(sysclk, rst)
begin
if rst = '1' then
usbi_resetring <= (others => '0');
usbi_resetcounter <= (others => '0');
usb_reset <= '0';
elsif sysclk'event and sysclk='1' then
if(usb_se0 = '0') then
usb_reset <= '0';
usbi_resetcounter <= (others => '0');
else
if(usbi_resetring(0) = '1') then
if usbi_resetcounter < 30 then
usbi_resetcounter <= usbi_resetcounter + 1;
else
usb_reset <= '1';
end if;
end if;
end if;
if(usbi_resetring(3 downto 0) = "0000") then
usbi_resetring <= usbi_resetring(3 downto 0) & '1';
else
usbi_resetring <= usbi_resetring(3 downto 0) & '0';
end if;
end if;
end process;
usbtxs_sending <= usbi_txactive;
usbtxs_icansend <= ((not usbi_txactive) or ((not usbi_bytebuffered) and (not usbi_receivedlastbyte))) and (not usbi_rxactive);
usbi_usecrc16 <= '1' when usbi_pid(1 downto 0) = "11" else '0';
usbi_rxcrcvalid <= usbi_crc16ok when usbi_usecrc16 = '1' else usbi_crc5ok;
process(sysclk, rst)
variable temp_bit : std_logic;
variable usbi_decide_next_2 : std_logic;
begin
if rst = '1' then
usb_drivebit <= '0';
usb_drivese0 <= '0';
usb_out <= '0';
usbtxs_abort <= '0';
usbtxs_underrunerror <= '0';
usbrxi_byte <= (others => '0');
usbrx_inextbyte <= '0';
usbrx_ipacketend <= '0';
usbrxi_crcerror <= '0';
usbrxi_bitstufferror <= '0';
usbrxi_eopmissing <= '0';
usbrxi_piderror <= '0';
usbrxi_incomplete <= '0';
usbrxi_syncerror <= '0';
usbi_decide <= '0';
usbi_decide_next <= '0';
usbi_ringnext <= '0';
usbi_rxactive <= '0';
usbi_txactive <= '0';
usbi_pid <= (others => '0');
usbi_byte <= (others => '0');
usbi_tempbyte <= (others => '0');
usbi_bit <= (others => '0');
usbi_crcreset <= '0';
usbi_crcenable <= '0';
usbi_crcbit <= '0';
usbi_rxlevel <= '1';
usbrxstate <= sync;
usbtxstate <= sync;
usbi_bytebuffered <= '0';
usbi_usingcrc <= '0';
usbi_receivedlastbyte <= '0';
usbi_bitstufferrordetected <= '0';
usbi_rxbytetemp <= (others => '0');
usbi_rxbytevalid <= '0';
usbi_crcengaged <= '0';
usbi_rxwaitforeop <= '0';
elsif sysclk'event and sysclk='1' then
-- set pulse-drive signals to 0 here, so they will typically only be active for the single cycle they are driven.
usbtxs_abort <= '0';
usbrx_inextbyte <= '0';
usbrx_ipacketend <= '0';
usbi_ringnext <= '0';
usbi_crcenable <= '0';
usbi_crcreset <= '0';
usbi_decide_next_2 := '0';
if usb_hold_reset = '1' then -- Usb chipset will hold this signal until the software asks to reset. Ignore all traffic.
-- Cancel any pending transactions.
usbtxs_abort <= '1';
usbi_txactive <= '0';
usbrx_inextbyte <= '0';
usbrx_ipacketend <= '0';
usb_drivebit <= '0';
usb_drivese0 <= '0';
usb_out <= '0';
if usbi_rxactive = '1' then
usbrx_inextbyte <= '1';
usbrx_ipacketend <= '1';
usbrxi_incomplete <= '1';
usbi_rxactive <= '0';
end if;
elsif usbi_rxactive = '1' then
if usbi_rxwaitforeop = '1' then
if usb_se0 = '0' and usb_validbit = '1' and usb_bit = '1' and usb_stable = '1' then
-- End condition. Assume that the higher layer will not start a response packet until the appropriate time has passed (just a few cycles away)
usbi_rxactive <= '0';
end if;
else
if(usbi_ringpulse = '1') then
-- Todo: consider flagging error if !usb_validbit, which suggests the incoming data is not stable.
-- This is probably not a concern, invalid data is unlikely to pass the other checks.
if(usb_se0 = '1') then
-- End of packet condition, wrap up.
if usbi_bit = "000" then
-- Ended on an even packet boundary, good!
usbrxi_crcerror <= usbi_crcengaged and (not usbi_rxcrcvalid);
elsif usbi_bit = "001" then
-- Ended after a single bit, this may be dribble - confirm the previous bit was a valid end point for the packet.
usbrxi_crcerror <= usbi_crcengaged and (not usbi_rxcrcvalid);
else
-- Ended at a poor location. Flag this as an error.
usbrxi_incomplete <= '1';
end if;
if usbrxstate /= content then -- Ensure we have at least received PID.
usbrxi_incomplete <= '1';
end if;
usbrxi_byte <= usbi_rxbytetemp;
usbrx_inextbyte <= '1';
usbrx_ipacketend <= '1';
usbi_rxwaitforeop <= '1';
else
usbrxi_bitstufferror <= usbrxi_bitstufferror or usbi_bitstufferrordetected;
usbi_bitstufferrordetected <= '0';
temp_bit := usb_bit xor usbi_rxlevel xor '1';
usbi_rxlevel <= usb_bit;
if(usbi_lastbits = "111111") then
if(temp_bit = '1') then
usbi_bitstufferrordetected <= '1'; -- There is one specific circumstance in which this should not immediately flag an error.
-- This could happen legitimiately if this is a repeat of the last bit in the packet (dribble)
end if;
-- Otherwise just a normally bit stuffed bit.
else
-- This was not a bitstuff bit, so go ahead and record it as a received bit.
if(usbi_bit = "011") then
usbi_crcengaged <= usbi_usingcrc; -- need to know at the end of the packet whether we were using CRC for more than a single bit time.
end if;
usbi_byte <= temp_bit & usbi_byte(7 downto 1);
usbi_bit <= usbi_bit + 1;
usbi_decide_next_2 := '1';
usbi_crcbit <= temp_bit;
usbi_crcenable <= usbi_usingcrc;
usbi_rxcrclastvalid <= usbi_rxcrcvalid; -- Keep track of CRC valid of the previous bit, also for dribble compensation.
end if;
usbi_lastbits <= usbi_lastbits(4 downto 0) & temp_bit;
end if;
end if;
if(usbi_decide = '1') then
-- Determine what to do with the newly received bit.
if(usbi_bit = "000") then
usbrxi_byte <= usbi_rxbytetemp;
usbrx_inextbyte <= usbi_rxbytevalid;
usbi_rxbytetemp <= usbi_byte;
usbi_rxbytevalid <= '0';
case usbrxstate is
when sync =>
if usbi_byte /= X"80" then
usbrxi_syncerror <= '1';
end if;
usbrxstate <= pid;
when pid =>
usbi_rxbytevalid <= '1';
usbrxstate <= content;
usbi_usingcrc <= '1';
usbi_pid <= usbi_byte(3 downto 0);
if usbi_byte(3 downto 0) /= (not usbi_byte(7 downto 4)) then
usbrxi_piderror <= '1';
end if;
when content =>
usbi_rxbytevalid <= '1';
when others =>
end case;
end if;
end if;
end if;
elsif usbi_txactive = '1' then
-- When TX is active, we are always sending a bit, unless EOP.
if(usbi_ringpulse = '1') then
-- Every 5 cycles (12MHz pulse)
usb_drivese0 <= '0';
if usbi_lastbits = "111111" then
-- Transmit bit stuffing, highest priority
usb_out <= not usb_out;
usb_drivebit <= '1';
usbi_lastbits <= usbi_lastbits(4 downto 0) & '0';
elsif usbtxstate = eop then
-- Send EOP for 2 bits
if usbi_bit = "010" then
-- We have completed our two bits. Drive J for a cycle..
usbi_txactive <= '0';
usb_drivebit <= '1';
usb_out <= '1';
usb_drivese0 <= '0';
elsif usbi_bit = "011" then
-- Finished driving J, return to idle.
usb_drivebit <= '0';
usb_drivese0 <= '0';
usbi_txactive <= '0';
else
usb_drivebit <= '0';
usb_drivese0 <= '1';
end if;
usbi_bit <= usbi_bit + 1;
else
-- Send next bit in byte.
usb_drivebit <= '1';
usb_out <= usbi_byte(0) xor usb_out xor '1'; -- Next bit is NRZI encoded
usbi_crcbit <= usbi_byte(0);
usbi_lastbits <= usbi_lastbits(4 downto 0) & usbi_byte(0);
usbi_byte <= '0' & usbi_byte(7 downto 1);
usbi_bit <= usbi_bit + 1;
usbi_decide_next_2 := '1'; -- advance the state machine on the next cycle based on the new bit position.
usbi_crcenable <= usbi_usingcrc;
end if;
end if;
if(usbi_decide = '1') then
-- Decision phase
if(usbi_bit = "000") then
-- Advance to next byte
if(usbi_bytebuffered = '1') then
usbi_byte <= usbi_tempbyte;
usbi_bytebuffered <= '0';
else
if(usbi_receivedlastbyte = '1') then
-- Send CRC if CRC16, otherwise EOP
if (usbtxstate = content or usbtxstate = pid) and usbi_usecrc16 = '1' then -- consider moving this block and above _byte logic out to a 3rd cycle, for performance reasons.
-- expressions feeding to _byte and _tempbyte could become expensive with this approach.
-- Capture & send CRC16
usbi_byte <= not usbi_crc16(7 downto 0);
usbi_tempbyte <= not usbi_crc16(15 downto 8);
usbi_bytebuffered <= '1';
usbtxstate <= crc1;
else
-- End packet here.
usbtxstate <= eop;
end if;
else
-- Underrun error
usbtxs_underrunerror <= '1';
usbtxs_abort <= '1';
usbi_txactive <= '0';
end if;
end if;
case usbtxstate is
when sync =>
usbtxstate <= pid;
usbi_pid <= usbi_tempbyte(3 downto 0); -- Save PID
when pid =>
if usbi_receivedlastbyte = '0' then
usbtxstate <= content;
usbi_usingcrc <= '1';
end if;
when content =>
when crc1 =>
--usbtxstate <= crc2; -- not really necessary. Above logic will bring us to EOP after CRC.
when crc2 =>
--usbtxstate <= eop;
when eop =>
end case;
end if;
-- CRC5 case, if we completed the 3rd bit of the last byte, acquire crc5 and send it.
if usbtxstate = content and usbi_receivedlastbyte = '1' and usbi_bytebuffered = '0' then
if usbi_bit = "011" and usbi_usecrc16 = '0' then
usbi_byte(4 downto 0) <= not usbi_crc5;
end if;
end if;
end if;
-- Get moar bytes
if usbtx_sendbyte = '1' then
-- Simple logic, just trust the upper layer to only send that the right time.
usbi_bytebuffered <= '1';
usbi_tempbyte <= usbtx_byte;
usbi_receivedlastbyte <= usbtx_lastbyte;
end if;
else
-- Identify if we should start tx or rx.
usbi_bit <= (others => '0');
usb_drivebit <= '0';
usb_drivese0 <= '0';
usb_out <= '1'; -- Idle state is J, differential 1.
usbi_lastbits <= (others => '0');
usbi_decide <= '0';
usbi_usingcrc <= '0';
usbi_bytebuffered <= '0';
usbi_receivedlastbyte <= '0';
usbi_crcreset <= '1';
usbi_rxlevel <= '1';
usbi_rxwaitforeop <= '0';
usbi_rxbytevalid <= '0';
usbi_crcengaged <= '0';
if usb_validbit = '1' and usb_bit = '0' and usb_stable = '1' then
-- Start receiving a packet
-- validbit is set when the signal has been stable for 2 cycles.
-- Set the ringnext flag so next cycle we will receive the first pulse, and every 5th cycle beyond.
-- The 3rd cycle we receive the bit should be right in the middle of the bit time for the best conditions possible.
usbi_rxactive <= '1';
usbi_ringnext <= '1';
usbrxstate <= sync;
-- Clear error flags
usbrxi_crcerror <= '0';
usbrxi_bitstufferror <= '0';
usbrxi_eopmissing <= '0';
usbrxi_piderror <= '0';
usbrxi_incomplete <= '0';
usbrxi_syncerror <= '0';
elsif usbtx_sendbyte = '1' then
-- This should never occur when receiving a byte due to design of the layer above this one.
usbi_txactive <= '1';
usbi_tempbyte <= usbtx_byte;
usbi_byte <= "10000000"; -- Sync byte
usbtxstate <= sync;
usbi_ringnext <= '1'; -- Cause pulse next cycle.
usbi_bytebuffered <= '1';
usbtxs_underrunerror <= '0';
usbi_receivedlastbyte <= usbtx_lastbyte;
end if;
end if;
usbi_decide <= usbi_decide_next;
usbi_decide_next <= usbi_decide_next_2; -- Delay decision by 2 cycles so the CRC is complete before we decide.
end if;
end process;
usbi_crc5ok <= '1' when usbi_crc5 = "00110" else '0';
usbi_crc16ok <= '1' when usbi_crc16 = "1011000000000001" else '0';
-- usb interface crc
process(sysclk, rst)
begin
if rst = '1' then
usbi_crc5 <= (others => '1');
usbi_crc16 <= (others => '1');
elsif sysclk'event and sysclk='1' then
if usbi_crcreset = '1' then
-- Reset CRC values
usbi_crc5 <= (others => '1');
usbi_crc16 <= (others => '1');
elsif usbi_crcenable = '1' then
-- Advance CRC computation based on usbi_crcbit
-- Doing this backwards from how the spec describes, in order to have the bits here easily transferred to bytes for sending.
if((usbi_crc16(0) xor usbi_crcbit) = '1') then
usbi_crc16 <= ('0' & usbi_crc16(15 downto 1)) xor "1010000000000001";
else
usbi_crc16 <= ('0' & usbi_crc16(15 downto 1));
end if;
if((usbi_crc5(0) xor usbi_crcbit) = '1') then
usbi_crc5 <= ('0' & usbi_crc5(4 downto 1)) xor "10100";
else
usbi_crc5 <= ('0' & usbi_crc5(4 downto 1));
end if;
end if;
end if;
end process;
end a;
| mit | 65e71917f6b0f2b0b3f99b6db1e43326 | 0.616601 | 3.080352 | false | false | false | false |
s3rvac/fit-projects | HSC/usr_proc_kit.vhd | 2 | 15,892 | -- ========================================================================
-- Projekt do pøedmìtu HSC
-- -----------------------
--
-- Jméno a Pøíjmení: Petr Zemek
--
-- Login: xzemek02
-- Datum: 28.12.2008
--
-- ========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- ------------------------ Entity declaration --------------------------------
entity USR_PROC is
port (
-- Øídicí signály
CLK : in std_logic;
RESET : in std_logic;
-- Rozhraní procesoru PicoBlaze
CPU_PORT_ID : in std_logic_vector(7 downto 0);
CPU_WRITE_STROBE : in std_logic;
CPU_READ_STROBE : in std_logic;
CPU_OUT_PORT : in std_logic_vector(7 downto 0);
CPU_IN_PORT : out std_logic_vector(7 downto 0);
-- Rozhraní 9-okolí
R0,R1,R2 : in std_logic_vector(7 downto 0);
R3,R4,R5 : in std_logic_vector(7 downto 0);
R6,R7,R8 : in std_logic_vector(7 downto 0);
-- Øízení vstupu dat
INPUT_FIFO_FULL : in std_logic;
INPUT_FIFO_EMPTY : in std_logic;
INPUT_FIFO_DATA : in std_logic_vector(7 downto 0);
NEXT_PIXEL : out std_logic;
-- Výstupní rozhraní
OUT_DATA : out std_logic_vector(7 downto 0);
OUT_DATA_VLD : out std_logic
);
end USR_PROC;
-- ------------------------- Architecture declaration -------------------------
architecture behav of USR_PROC is
-- Mapování registrù do adresového prostoru procesoru PicoBlaze
constant PORT_REG_R0 : std_logic_vector(7 downto 0):=X"00";
constant PORT_REG_R1 : std_logic_vector(7 downto 0):=X"01";
constant PORT_REG_R2 : std_logic_vector(7 downto 0):=X"02";
constant PORT_REG_R3 : std_logic_vector(7 downto 0):=X"03";
constant PORT_REG_R4 : std_logic_vector(7 downto 0):=X"04";
constant PORT_REG_R5 : std_logic_vector(7 downto 0):=X"05";
constant PORT_REG_R6 : std_logic_vector(7 downto 0):=X"06";
constant PORT_REG_R7 : std_logic_vector(7 downto 0):=X"07";
constant PORT_REG_R8 : std_logic_vector(7 downto 0):=X"08";
constant PORT_REG_Rout : std_logic_vector(7 downto 0):=X"20";
constant PORT_REG_MEDIAN : std_logic_vector(7 downto 0):=X"21";
constant PORT_REG_STATUS : std_logic_vector(7 downto 0):=X"FE";
constant PORT_REG_CONTROL : std_logic_vector(7 downto 0):=X"FF";
-- Øídicí registr
signal reg_control : std_logic_vector(7 downto 0);
signal reg_control_we : std_logic;
-- Status registr
signal reg_status : std_logic_vector(7 downto 0);
-- Výstupní registr
signal reg_Rout : std_logic_vector(7 downto 0);
signal reg_Rout_vld : std_logic;
signal reg_Rout_we : std_logic;
-- 9-okolí bylo právì posunuto v obraze o jeden pixel
signal pixels_shifted : std_logic;
-- Median
signal median_value : std_logic_vector(7 downto 0);
-- Serazovaci sit
signal A0 : std_logic_vector(7 downto 0);
signal A1 : std_logic_vector(7 downto 0);
signal A2 : std_logic_vector(7 downto 0);
signal A3 : std_logic_vector(7 downto 0);
signal A5 : std_logic_vector(7 downto 0);
signal A6 : std_logic_vector(7 downto 0);
signal A7 : std_logic_vector(7 downto 0);
signal A8 : std_logic_vector(7 downto 0);
signal B0 : std_logic_vector(7 downto 0);
signal B1 : std_logic_vector(7 downto 0);
signal B3 : std_logic_vector(7 downto 0);
signal B4 : std_logic_vector(7 downto 0);
signal B5 : std_logic_vector(7 downto 0);
signal B7 : std_logic_vector(7 downto 0);
signal C0 : std_logic_vector(7 downto 0);
signal C2 : std_logic_vector(7 downto 0);
signal C3 : std_logic_vector(7 downto 0);
signal C4 : std_logic_vector(7 downto 0);
signal C5 : std_logic_vector(7 downto 0);
signal C8 : std_logic_vector(7 downto 0);
signal D0 : std_logic_vector(7 downto 0);
signal D1 : std_logic_vector(7 downto 0);
signal D2 : std_logic_vector(7 downto 0);
signal D4 : std_logic_vector(7 downto 0);
signal D6 : std_logic_vector(7 downto 0);
signal D8 : std_logic_vector(7 downto 0);
signal E2 : std_logic_vector(7 downto 0);
signal E4 : std_logic_vector(7 downto 0);
signal E6 : std_logic_vector(7 downto 0);
signal E8 : std_logic_vector(7 downto 0);
signal F1 : std_logic_vector(7 downto 0);
signal F3 : std_logic_vector(7 downto 0);
signal F4 : std_logic_vector(7 downto 0);
signal F6 : std_logic_vector(7 downto 0);
signal G3 : std_logic_vector(7 downto 0);
signal G4 : std_logic_vector(7 downto 0);
signal reg_A0 : std_logic_vector(7 downto 0);
signal reg_A1 : std_logic_vector(7 downto 0);
signal reg_A2 : std_logic_vector(7 downto 0);
signal reg_A3 : std_logic_vector(7 downto 0);
signal reg_A5 : std_logic_vector(7 downto 0);
signal reg_A6 : std_logic_vector(7 downto 0);
signal reg_A7 : std_logic_vector(7 downto 0);
signal reg_A8 : std_logic_vector(7 downto 0);
signal reg_B0 : std_logic_vector(7 downto 0);
signal reg_B1 : std_logic_vector(7 downto 0);
signal reg_B3 : std_logic_vector(7 downto 0);
signal reg_B4 : std_logic_vector(7 downto 0);
signal reg_B5 : std_logic_vector(7 downto 0);
signal reg_B7 : std_logic_vector(7 downto 0);
signal reg_C0 : std_logic_vector(7 downto 0);
signal reg_C2 : std_logic_vector(7 downto 0);
signal reg_C3 : std_logic_vector(7 downto 0);
signal reg_C4 : std_logic_vector(7 downto 0);
signal reg_C5 : std_logic_vector(7 downto 0);
signal reg_C8 : std_logic_vector(7 downto 0);
signal reg_D0 : std_logic_vector(7 downto 0);
signal reg_D1 : std_logic_vector(7 downto 0);
signal reg_D2 : std_logic_vector(7 downto 0);
signal reg_D4 : std_logic_vector(7 downto 0);
signal reg_D6 : std_logic_vector(7 downto 0);
signal reg_D8 : std_logic_vector(7 downto 0);
signal reg_E2 : std_logic_vector(7 downto 0);
signal reg_E4 : std_logic_vector(7 downto 0);
signal reg_E6 : std_logic_vector(7 downto 0);
signal reg_E8 : std_logic_vector(7 downto 0);
signal reg_F1 : std_logic_vector(7 downto 0);
signal reg_F3 : std_logic_vector(7 downto 0);
signal reg_F4 : std_logic_vector(7 downto 0);
signal reg_F6 : std_logic_vector(7 downto 0);
signal reg_G3 : std_logic_vector(7 downto 0);
signal reg_G4 : std_logic_vector(7 downto 0);
begin
-- ------------------------ HW akcelerace ---------------------------------
-- ------------------- Serazovani pomoci radici site ----------------------
-- [[0,8], [1,5], [2,6], [3,7]]
sort1 : process(R0, R8, R1, R5, R2, R6, R3, R7)
begin
-- [0,8]
if R0 < R8 then
A0 <= R0;
A8 <= R8;
else
A0 <= R8;
A8 <= R0;
end if;
-- [1,5]
if R1 < R5 then
A1 <= R1;
A5 <= R5;
else
A1 <= R5;
A5 <= R1;
end if;
-- [2,6]
if R2 < R6 then
A2 <= R2;
A6 <= R6;
else
A2 <= R6;
A6 <= R2;
end if;
-- [3,7]
if R3 < R7 then
A3 <= R3;
A7 <= R7;
else
A3 <= R7;
A7 <= R3;
end if;
end process sort1;
-- [[0,4], [1,3], [5,7]]
sort2 : process(A0, R4, A1, A3, A5, A7)
begin
-- [0,4]
if A0 < R4 then
B0 <= A0;
B4 <= R4;
else
B0 <= R4;
B4 <= A0;
end if;
-- [1,3]
if A1 < A3 then
B1 <= A1;
B3 <= A3;
else
B1 <= A3;
B3 <= A1;
end if;
-- [5,7]
if A5 < A7 then
B5 <= A5;
B7 <= A7;
else
B5 <= A7;
B7 <= A5;
end if;
end process sort2;
-- [[4,8], [0,2], [3,5]]
sort3 : process(B4, A8, B0, A2, B3, B5)
begin
-- [4,8]
if B4 < A8 then
C4 <= B4;
C8 <= A8;
else
C4 <= A8;
C8 <= B4;
end if;
-- [0,2]
if B0 < A2 then
C0 <= B0;
C2 <= A2;
else
C0 <= A2;
C2 <= B0;
end if;
-- [3,5]
if B3 < B5 then
C3 <= B3;
C5 <= B5;
else
C3 <= B5;
C5 <= B3;
end if;
end process sort3;
-- Naplneni registru
process(CLK)
begin
if ((CLK'event) and (CLK = '1')) then
reg_C4 <= C4;
reg_A6 <= A6;
reg_C2 <= C2;
reg_C8 <= C8;
reg_C0 <= C0;
reg_B1 <= B1;
end if;
end process;
-- [[4,6], [2,8], [0,1]]
sort4 : process(reg_C4, reg_A6, reg_C2, reg_C8, reg_C0, reg_B1)
begin
-- [4,6]
if reg_C4 < reg_A6 then
D4 <= reg_C4;
D6 <= reg_A6;
else
D4 <= reg_A6;
D6 <= reg_C4;
end if;
-- [2,8]
if reg_C2 < reg_C8 then
D2 <= reg_C2;
D8 <= reg_C8;
else
D2 <= reg_C8;
D8 <= reg_C2;
end if;
-- [0,1]
if reg_C0 < reg_B1 then
D0 <= reg_C0;
D1 <= reg_B1;
else
D0 <= reg_B1;
D1 <= reg_C0;
end if;
end process sort4;
-- [[2,4], [6,8]]
sort5 : process(D2, D4, D6, D8)
begin
-- [2,4]
if D2 < D4 then
E2 <= D2;
E4 <= D4;
else
E2 <= D4;
E4 <= D2;
end if;
-- [6,8]
if D6 < D8 then
E6 <= D6;
E8 <= D8;
else
E6 <= D8;
E8 <= D6;
end if;
end process sort5;
-- Naplneni registru
process(CLK)
begin
if ((CLK'event) and (CLK = '1')) then
reg_E2 <= E2;
reg_C3 <= C3;
reg_E4 <= E4;
reg_C5 <= C5;
reg_E6 <= E6;
reg_B7 <= B7;
reg_D1 <= D1;
reg_E8 <= E8;
end if;
end process;
-- [[2,3], [4,5], [6,7], [1,8]]
sort6 : process(reg_E2, reg_C3, reg_E4, reg_C5, reg_E6, reg_B7, reg_D1, reg_E8)
begin
-- [2,3]
if reg_E2 < reg_C3 then
F3 <= reg_C3;
else
F3 <= reg_E2;
end if;
-- [4,5]
if reg_E4 < reg_C5 then
F4 <= reg_E4;
else
F4 <= reg_C5;
end if;
-- [6,7]
if reg_E6 < reg_B7 then
F6 <= reg_E6;
else
F6 <= reg_B7;
end if;
-- [1,8]
if reg_D1 < reg_E8 then
F1 <= reg_D1;
else
F1 <= reg_E8;
end if;
end process sort6;
-- [[1,4], [3,6]]
sort7 : process(F1, F3, F4, F6)
begin
if F1 < F4 then
if F3 < F6 then
if F3 < F4 then
median_value <= F4;
else
median_value <= F3;
end if;
else
if F6 < F4 then
median_value <= F4;
else
median_value <= F6;
end if;
end if;
else
if F3 < F6 then
if F3 < F1 then
median_value <= F1;
else
median_value <= F3;
end if;
else
if F6 < F1 then
median_value <= F1;
else
median_value <= F6;
end if;
end if;
end if;
end process sort7;
-- ---------------- Posun 9-okolí v obraze o 1 pixel ---------------------
-- Signalizace posunu 9-okolí v obrazu o jeden pixel
NEXT_PIXEL <= reg_control_we and CPU_OUT_PORT(0);
-- 9-okolí bylo právì posunuto v obraze o jeden pixel
-- (zpo¾dìní NEXT_PIXEL signálu o 1 takt CLK)
shift_pixels_proc : process (CLK)
begin
if CLK'event and CLK = '1' then
pixels_shifted <= reg_control_we and CPU_OUT_PORT(0);
end if;
end process shift_pixels_proc;
-- ----------------------- Øídicí registr --------------------------------
control_register : process (CLK, RESET)
begin
if RESET = '1' then
reg_control <= (others => '0');
elsif CLK'event and CLK = '1' then
if reg_control_we = '1' then
reg_control <= CPU_OUT_PORT;
end if;
end if;
end process control_register;
-- ----------------------- Stavový registr -------------------------------
reg_status <= (7 downto 2 => '0') & INPUT_FIFO_FULL &
(not INPUT_FIFO_EMPTY);
-- ----------------------- Výstupní registr ------------------------------
output_register : process (CLK, RESET)
begin
if RESET = '1' then
reg_Rout <= (others => '0');
elsif CLK'event and CLK = '1' then
if reg_Rout_we = '1' then
reg_Rout <= CPU_OUT_PORT;
end if;
end if;
end process output_register;
-- Výstupní data jsou nejprve ulo¾ena do registru reg_Rout a a¾ pak
-- (po 1 hodinovém cyklu) odeslány na výstup. Potvrzení dat signálem
-- OUT_DATA_VLD je tedy nutné zpozdit také o 1 hodinový cyklus.
output_valid : process (CLK, RESET)
begin
if CLK'event and CLK = '1' then
reg_Rout_vld <= reg_Rout_we;
end if;
end process output_valid;
-- Pøiøazení dat na výstup
OUT_DATA <= reg_Rout;
OUT_DATA_VLD <= reg_Rout_vld;
-- ------------------------ Adresový dekodér ------------------------------
--
-- Port Pøístup Popis
-- --------------------------------------------------------------------
--
-- 0x20 Read, Write Registr Rout pro vysílání výsledkù
--
-- 0x21 ... Volné porty - je mo¾né vlo¾it vlastní
-- registry pro komunikaci mezi procesorem
-- akcelerovanou èástí
-- 0x21 Read Registr REG_MEDIAN s vypoctenym medianem
--
-- 0xFE Read Registr má na 0-tém bitu indikaci stavu vstupní
-- fronty. Pokud je bit nastaven, jsou ve FIFO
-- pamìti data z kamery.
--
-- 0xFF Read/Write Zápisem jednièky na 0-tý bit se posune
-- 9-okolí o jeden pixel.
--
-- -------------- Zápisy do registrù ------------
-- Zápis do registru Rout
reg_Rout_we <= '1' when (CPU_PORT_ID=PORT_REG_Rout and
CPU_WRITE_STROBE='1') else
'0';
-- Zápis do registru Control
reg_control_we<= '1' when (CPU_PORT_ID=PORT_REG_CONTROL and
CPU_WRITE_STROBE='1') else
'0';
-- -------------- Ètení z registrù --------------
adec_read : process (CPU_PORT_ID, reg_Rout, reg_status, reg_control,
median_value)
begin
CPU_IN_PORT <= (others => '0');
case CPU_PORT_ID is
-- Registr s vypoctenym medianem
when PORT_REG_MEDIAN => CPU_IN_PORT <= median_value;
-- Výstupní registr
when PORT_REG_Rout => CPU_IN_PORT <= reg_Rout;
-- Øídicí a status registr
when PORT_REG_STATUS => CPU_IN_PORT <= reg_status;
when PORT_REG_CONTROL => CPU_IN_PORT <= reg_control;
when others=> null;
end case;
end process adec_read;
end behav;
| gpl-2.0 | 972166dd53c7836f7100098f77cec6ce | 0.476152 | 3.241942 | false | false | false | false |
sgstair/ledsign | firmware/matrixdriver/tracefifo.vhd | 1 | 5,275 | --
-- This source is released under the MIT License (MIT)
--
-- Copyright (c) 2016 Stephen Stair ([email protected])
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity tracefifo is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
write_data : in std_logic_vector(7 downto 0);
write_pulse : in std_logic;
read_data : out std_logic_vector(7 downto 0);
has_data : out std_logic;
read_pulse : in std_logic );
end tracefifo;
architecture Behavioral of tracefifo is
signal ramout_data : std_logic_vector(31 downto 0);
signal ramwrite_data : std_logic_vector(31 downto 0);
signal ramwrite_pulse : std_logic;
signal write_address : unsigned(10 downto 0);
signal nextwrite_address : unsigned(10 downto 0);
signal read_address : unsigned(10 downto 0);
begin
read_data <= X"EE" when write_address = read_address else ramout_data(7 downto 0);
has_data <= '0' when write_address = read_address else '1';
nextwrite_address <= write_address + 1;
process(clk)
begin
if clk'event and clk='1' then
ramwrite_pulse <= '0';
if ramwrite_pulse = '1' then
write_address <= nextwrite_address;
elsif write_pulse = '1' and write_data /= X"FF" then
if nextwrite_address /= read_address then
ramwrite_data(7 downto 0) <= write_data;
ramwrite_pulse <= '1';
end if; -- Discard data that would overwrite head.
end if;
if read_pulse = '1' then
if read_address /= write_address then
read_address <= read_address + 1;
end if;
end if;
if reset = '1' then
write_address <= (others => '0');
read_address <= (others => '0');
end if;
end if;
end process;
ram : RAMB16BWER
generic map (
-- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
DATA_WIDTH_A => 9, DATA_WIDTH_B => 9,
-- DOA_REG/DOB_REG: Optional output register (0 or 1)
DOA_REG => 0, DOB_REG => 0,
-- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
EN_RSTRAM_A => TRUE,
EN_RSTRAM_B => TRUE,
-- INIT_FILE: Optional file used to specify initial RAM contents
INIT_FILE => "NONE",
-- RSTTYPE: "SYNC" or "ASYNC"
RSTTYPE => "SYNC",
-- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
RST_PRIORITY_A => "CE",
RST_PRIORITY_B => "CE",
-- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
SIM_COLLISION_CHECK => "ALL",
-- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
SIM_DEVICE => "SPARTAN6",
-- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
-- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST"
)
port map (
DOA => ramout_data, -- 32-bit output: A port data output
ADDRA => std_logic_vector(read_address) & "000", -- 14-bit input: A port address input
CLKA => clk, -- 1-bit input: A port clock input
ENA => '1', -- 1-bit input: A port enable input
REGCEA => '1', -- 1-bit input: A port register clock enable input
RSTA => reset, -- 1-bit input: A port register set/reset input
WEA => "0000", -- 4-bit input: Port A byte-wide write enable input
DIA => (others => '0'), -- 32-bit input: A port data input
DIPA => (others => '0'),-- 4-bit input: A port parity input
ADDRB => std_logic_vector(write_address) & "000", -- 14-bit input: B port address input
CLKB => clk, -- 1-bit input: B port clock input
ENB => '1', -- 1-bit input: B port enable input
REGCEB => '1', -- 1-bit input: B port register clock enable input
RSTB => reset, -- 1-bit input: B port register set/reset input
WEB => (others => ramwrite_pulse), -- 4-bit input: Port B byte-wide write enable input
DIB => ramwrite_data, -- 32-bit input: B port data input
DIPB => (others => '0') -- 4-bit input: B port parity input
);
end Behavioral;
| mit | 5306d57b60f47db2920e3af625191842 | 0.668057 | 3.323882 | false | false | false | false |
aleksandar-mitrevski/hw_sw | explorer/exploration_pkg.vhd | 1 | 5,183 | library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use work.vector_pkg.all;
package exploration_pkg is
constant NUMBER_OF_CELLS : integer := 256;
constant NUMBER_OF_ROWS : integer := 16;
constant CELLS_PER_ROW : integer := 16;
constant CELL_HEIGHT : real := 14.4;
constant CELL_WIDTH : real := 8.8;
constant LINEAR_COST : real := 0.2;
constant ANGULAR_COST : real := 0.8;
constant INFINITY : real := 10000000.0;
type gridArray is array (0 to NUMBER_OF_CELLS-1) of std_logic;
type cellsAndCostsArray is array (integer range <>) of CellsAndCosts;
type integer_array is array (integer range <>) of integer;
type real_array is array (integer range <>) of real;
function isGridExplored(grid : gridArray) return std_logic;
function calculateCosts(currentCell : integer, currentOrientation : real, grid : gridArray) return integer;
function calculateCellCost(cell: integer, currentCell : integer, orientation : real) return real;
function normaliseAngle(angle : real) return real;
end;
package body exploration_pkg is
--- Returns '1' if all cells in 'grid' have been marked '1', and, in addition,
--- 'numberOfNuggetsToCollect' is equal to 0; returns '0' otherwise.
---
--- Arguments:
--- grid -- A GridArray array representing a boolean grid.
--- numberOfNuggetToCollect -- An integer denoting the number of visible nuggets that need to be collected.
---
function isGridExplored(grid : gridArray, numberOfNuggetsToCollect : integer) return std_logic is
variable isExplored : std_logic := '1';
begin
isExplored := '1';
for i in 0 to NUMBER_OF_CELLS-1 loop
if grid(i) = '0' then
isExplored := '0';
end if;
end loop;
if isExplored = '1' and numberOfNuggetsToCollect > 0 then
isExplored := '0';
end if;
return isExplored;
end isGridExplored;
--- Calculates a cost for each of the unexplored cells given the current position and orientation of the robot.
---
--- Arguments:
--- currentCell -- An index denoting the current position of a robot.
--- currentOrientation -- A floating-point number denoting a robot's orientation.
--- grid -- A GridArray array representing a boolean grid.
---
--- Returns:
--- minimumCostCell -- An index denoting the cell with lowest combined linear and angular cost.
---
function calculateCosts(currentCell : integer, currentOrientation : real, grid : gridArray) return integer is
variable cellCosts: real_array(0 to NUMBER_OF_CELLS);
variable minimumCost : real;
variable minimumCostCell : integer;
begin
for i in 0 to NUMBER_OF_CELLS loop
if i = currentCell or grid(cell) = '1' then
cellCosts(i) := INFINITY;
else
cellCosts(i) := calculateCellCost(i, currentCell, currentOrientation);
end if;
end loop;
minimumCost := cellCosts(0);
minimumCostCell := 0;
for i in 1 to NUMBER_OF_CELLS loop
if minimumCost > cellCosts(i) then
minimumCost := cellCosts(i);
minimumcCostCell := i;
end if;
end loop;
return minimumCostCell;
end;
--- Calculates the cost of 'cell' with respect to 'currentCell' and 'orientation'.
---
--- Arguments:
--- cell -- Index of a cell.
--- currentCell -- An index denoting the current position of a robot.
--- orientation --A floating-point number denoting a robot's orientation.
---
--- Returns:
--- cost -- A floating-point number representing the calculated cost.
---
function calculateCellCost(cell: integer, currentCell : integer, orientation : real) return real is
variable cost : real := 0.0;
variable dotProduct : real;
variable vectorToCell : Vector;
variable directionVector : Vector;
variable linearDistance : real;
variable angularDistance : real;
begin
vectorToCell.x := (real(cell) * CELL_WIDTH) - (real(currentCell) * CELL_WIDTH);
vectorToCell.y := (real(cell) * CELL_HEIGHT) - (real(currentCell) * CELL_HEIGHT);
linearDistance := sqrt((xDistance * xDistance) + (yDistance * yDistance));
directionVector.x := cos(orientation);
directionVector.y := sin(orientation);
dotProduct := vectorToCell.x * directionVector.x + vectorToCell.y * directionVector.y;
angularDistance := normaliseAngle(arccos(dotProduct / norm(vectorToCell)));
cost = LINEAR_COST * linearDistance + ANGULAR_COST * angularDistance;
return cost;
end calculateCellCost;
--- Transforms 'angle' so that it lies in the (0,2*pi) range.
---
--- Arguments:
--- angle -- A floating-point number representing an angle.
---
function normaliseAngle(angle : real) return real is
begin
if angle < 0 then
angle = angle + 2.0 * MATH_PI;
end if;
return angle;
end normaliseAngle;
end package body; | mit | c20d9ecc4071fba7e88d0cc4c4d3f649 | 0.633803 | 3.968606 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/alu_decode.vhd | 1 | 4,470 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:20:45 10/21/2015
-- Design Name:
-- Module Name: alu_decode - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu_decode is
Port ( exe : in STD_LOGIC;
OP_EN : in STD_LOGIC;
clk : in STD_LOGIC;
clk_fast: in std_logic;
rst : in STD_LOGIC;
OP_Code : in STD_LOGIC_VECTOR(3 downto 0);
WE : out STD_LOGIC;
A_EN : out STD_LOGIC;
STAT_EN : out STD_LOGIC;
HLT : out STD_LOGIC;
JMP : out STD_LOGIC;
Arith_S : out STD_LOGIC;
Stat_S : out STD_LOGIC;
LOD_S : out STD_LOGIC;
STR : out STD_LOGIC);
end alu_decode;
architecture Behavioral of alu_decode is
signal stored_OP_Code : STD_LOGIC_VECTOR(3 downto 0);
signal i_WE : std_logic;
begin
process(clk)
--ADD A RESET THAT SETS OPCODE TO NOP
begin
if clk' event and clk = '1' then
--Write op_code into temp storage
if OP_EN = '1' then
stored_OP_Code <= OP_Code;
end if;
end if;
end process;
--process(clk)
--begin
-- --Execute instruction
--
-- if rst = '1' then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- elsif exe = '1' then
-- --HLT
-- if stored_OP_Code = "0000" then
-- i_WE <= '1';
-- HLT <= '1';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- --LOD
-- elsif stored_OP_Code = "0001" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '0';
-- JMP <= '0';
-- LOD_S <= '1';
--
-- --STR
-- elsif stored_OP_Code = "0010" then
--
--
-- --if i_WE = '1' then
-- -- i_WE <= '0';
-- --else
-- -- i_WE <= '1';
-- --end if;
--
-- i_WE <= '0';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- --ADD
-- elsif stored_OP_Code = "0011" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '1';
-- JMP <= '0';
-- Arith_S <= '0';
-- Stat_S <= '0';
-- LOD_S <= '0';
--
-- --NOP
-- elsif stored_OP_Code = "0100" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
--
-- --NND
-- elsif stored_OP_Code = "0101" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '0';
-- JMP <= '0';
-- Arith_S <= '1';
-- Stat_S <= '0';
-- LOD_S <= '0';
--
-- --CXA
-- elsif stored_OP_Code = "0111" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '1';
-- STAT_EN <= '0';
-- JMP <= '0';
-- Stat_S <= '1';
-- LOD_S <= '0';
--
-- --JMP
-- elsif stored_OP_Code = "0110" then
-- i_WE <= '1';
-- HLT <= '0';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '1';
--
-- --Unknown - halt the CPU
-- else
-- i_WE <= '1';
-- HLT <= '1';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
-- end if;
--
--
--
-- else
-- HLT <= '0';
-- i_WE <= '1';
-- A_EN <= '0';
-- STAT_EN <= '0';
-- JMP <= '0';
-- end if;
--
--end process;
-- Decoder Combinational Logic --
-- Active Low WE
WE <= '0' when ( stored_OP_code = "0010" and exe = '1' and clk = '1') else '1';
STR <= '1' when (stored_OP_code = "0010" and exe = '1') else '0';
-- HLT
HLT <= '1' when( stored_OP_code = "0000" and exe = '1') else '0';
-- A_EN
A_EN <= '1' when( (stored_OP_code = "0001" or stored_OP_code = "0011" or stored_OP_code = "0101" or stored_OP_code = "0111") and exe = '1' ) else '0';
-- STAT_EN
STAT_EN <= '1' when( stored_OP_code = "0011" and exe = '1') else '0';
-- JMP
JMP <= '1' when( stored_OP_code = "0110" and exe = '1') else '0';
-- Arith_S
Arith_S <= '1' when( stored_OP_code = "0101" and exe = '1') else '0';
-- Stat_S
Stat_S <= '1' when( stored_OP_code = "0111" and exe = '1') else '0';
-- LOD_S
LOD_S <= '1' when( stored_OP_code = "0001" and exe = '1') else '0';
end Behavioral;
| unlicense | a22245793c2d2248c02d8f8dcac9a937 | 0.464653 | 2.430669 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/CON SOLO NCO/tec-drums/ipcore_dir/demo_tb/tb_sound_module.vhd | 1 | 9,209 | ---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the DDS Compiler datasheet for further information about this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- named "sound_module".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile sound_module.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl sound_module.ngc sound_module_netlist.vhd
--
-- Compile sound_module_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_sound_module is
end tb_sound_module;
architecture tb of tb_sound_module is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data master channel alias signals
signal m_axis_data_tdata_sine : std_logic_vector(15 downto 0) := (others => '0');
-- Alias signals for each separate TDM channel (these are 1 cycle delayed relative to the above alias signals)
signal m_axis_data_channel : integer := 0; -- indicates TDM channel number of data master channel outputs
signal m_axis_data_tdata_sine_c0 : std_logic_vector(15 downto 0) := (others => '0');
signal m_axis_data_tdata_sine_c1 : std_logic_vector(15 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.sound_module
port map (
aclk => aclk
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Run for long enough to produce 5 periods of outputs
wait for CLOCK_PERIOD * 10;
-- End of test
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_sine <= m_axis_data_tdata(15 downto 0) when m_axis_data_tvalid = '1';
-- Data master channel alias signals for each TDM channel
-- Note that these are one cycle later than the overall data master channel signals
process (aclk)
begin
if rising_edge(aclk) then
if m_axis_data_tvalid = '1' then
if m_axis_data_channel = 1 then
m_axis_data_channel <= 0;
else
m_axis_data_channel <= m_axis_data_channel + 1;
end if;
if m_axis_data_channel = 0 then
m_axis_data_tdata_sine_c0 <= m_axis_data_tdata(15 downto 0);
elsif m_axis_data_channel = 1 then
m_axis_data_tdata_sine_c1 <= m_axis_data_tdata(15 downto 0);
end if;
end if;
end if;
end process;
end tb;
| mit | 9414f6ad44d008a74f8f7bf8dbd16261 | 0.575741 | 4.734704 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/Referencias/fpga/clk_dcm_pll.vhd | 1 | 6,510 | -- file: clk_dcm_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 40.960 0.000 50.0 596.692 50.000
-- CLK_OUT2 8.192 0.000 50.0 200.000 50.000
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 8.192 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_dcm_pll is
generic
(
CLK_MULTIPLY : integer := 5
);
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic;
CLK_OUT2 : out std_logic
);
end clk_dcm_pll;
architecture xilinx of clk_dcm_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_dcm_pll,clk_wiz_v3_1,{component_name=clk_dcm_pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=122.0703125,clkin2_period=122.0703125,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clk_out2_internal : std_logic;
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => CLK_MULTIPLY,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 122.0703125,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= clk_out2_internal;
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkfx);
clkout2_buf : BUFG
port map
(O => clk_out2_internal,
I => clk0);
CLK_OUT2 <= clk_out2_internal;
end xilinx;
| mit | 31a9403b89fdc176a5e7649bb252893d | 0.575269 | 4.205426 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.orig.vhd | 1 | 11,602 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_MEMCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 2;
C_CLKOUT1_DIVIDE : integer := 2;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 4;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
U_BUFG_CLK1 : BUFG
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in
);
process (clk0_bufg, sys_rst)
begin
if (clk0_bufg'event and clk0_bufg = '1') then
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
rst_tmp <= sys_rst or not(powerup_pll_locked);
async_rst <= rst_tmp;
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| gpl-3.0 | 051faea5aba1a4f88ec9ea4881af7030 | 0.530598 | 4.053809 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/test/24bit_register_falling_clocked.vhd | 1 | 1,000 | ------------------------------------------------------------
-- Notes:
-- Clock on FALLING EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
--
-- Additional Comments:
-- The register latches it's data on the FALLING edge
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use UMDRISC.ALL;
ENTITY Reg24 IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END Reg24;
ARCHITECTURE Behavior OF Reg24 IS
BEGIN
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0');
ELSIF Clock'EVENT AND Clock = '0' THEN
IF ENABLE = '1' THEN
Q <= D;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 78fabc76d61ddaaa66a2ba14c3bacb9e | 0.541 | 3.184713 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/data_flow_controller.vhd | 1 | 1,722 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:19:13 10/19/2015
-- Design Name:
-- Module Name: data_flow_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity data_flow_controller is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
mem_reg_we : out STD_LOGIC;
alu_op_en : out STD_LOGIC;
execute : out STD_LOGIC);
end data_flow_controller;
architecture Behavioral of data_flow_controller is
-- Intermediate Signals --
signal cycle_counter : STD_LOGIC_VECTOR(2 downto 0);
begin
process( clk, reset )
begin
if reset = '1' then
cycle_counter <= "110";
alu_op_en <= '1';
mem_reg_we <= '0';
execute <= '0';
elsif falling_edge(clk) then
-- Cycle 1 --
if cycle_counter = "110" then
-- Cycle 2 --
elsif cycle_counter = "101" then
end if;
if cycle_counter = "000" then
cycle_counter <= "110";
else
cycle_counter <= cycle_counter - 1;
end if;
end if;
end process;
end Behavioral;
| unlicense | d3199519be2842ce0cbd539f623e1a4c | 0.554007 | 3.648305 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/TB_GenReg_16v2.vhd | 1 | 2,689 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:59 03/16/2014
-- Design Name:
-- Module Name: TB_DUAL_RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_REG_S16 is
end TB_REG_S16;
architecture Behavioral of TB_REG_S16 is
component REG_S16 is
generic(
REG_WIDTH: integer:=4 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT REG_WIDTH:integer:=4;
signal CLOCK : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal REG_A_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_B_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_B : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_A_IN_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A_IN : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: REG_S16 port map(
CLOCK => Clock,
WE => WE,
REG_A_ADDR => REG_A_ADDR,
REG_A => REG_A,
REG_B_ADDR => REG_B_ADDR,
REG_B => REG_B,
REG_A_IN_ADDR => REG_A_IN_ADDR,
REG_A_IN => REG_A_IN
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
REG_A_ADDR <= (others => '0');
REG_B_ADDR <= (others => '0');
REG_A_IN_ADDR <= (others => '0');
REG_A_IN <= x"FFFFFF";wait for 2*period;
--Enabling the register
WE <= '1'; wait for 2*period;
WE <= '0';
REG_A_IN_ADDR <= x"1";
WE <= '1'; wait for 2*period;
WE <= '0';
REG_B_ADDR <= x"1"; wait for 50*period;
end process;
end Behavioral;
| mit | cd8fec851c85232308290cb0854b4130 | 0.597248 | 2.772165 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/memc3_infrastructure.vhd | 2 | 10,566 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.5
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/06/10 13:30:57 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_MEMCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 2;
C_CLKOUT1_DIVIDE : integer := 2;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 4;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_n : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_MEMCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_MEMCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
begin
sys_rst <= not(sys_rst_n) when (C_RST_ACT_LOW /= 0) else sys_rst_n;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
U_BUFG_CLK1 : BUFG
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in
);
process (clk0_bufg, sys_rst)
begin
if (clk0_bufg'event and clk0_bufg = '1') then
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
rst_tmp <= sys_rst or not(powerup_pll_locked);
async_rst <= rst_tmp;
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;
| gpl-3.0 | 32b783b27a5b59eb0e75f170a8fb2d18 | 0.547795 | 3.967706 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/memoria/simulation/bmg_stim_gen.vhd | 2 | 12,585 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (11263 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"memoria.mif",
DEFAULT_DATA,
32,
11264);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>11264 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 11264 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 96d6f25286d04b90ea109cee5805c1ab | 0.547954 | 3.685212 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/sounds_mem/simulation/sounds_mem_synth.vhd | 2 | 6,839 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: sounds_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY sounds_mem_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE sounds_mem_synth_ARCH OF sounds_mem_synth IS
COMPONENT sounds_mem_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: sounds_mem_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 8489607a35ac026f8bdfff8d4702d465 | 0.58064 | 3.79102 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Lab4/tests/Spartan3VGATest/vgatest.vhd | 1 | 4,046 | --------------------------------------------------------------------------------
-- Company: Department of Computer Science, University of Texas at San Antonio
-- Engineer: Chia-Tien Dan Lo ([email protected])
--
-- Create Date: 11:01:23 08/20/06
-- Design Name:
-- Module Name: vgatest - behavioral
-- Project Name:
-- Target Device: Xilinx Spartan 3 xc3s200 on Didilent Spartan-3 Starter Kit Board
-- Tool versions: ISE 8.1.03i
-- Description: This VGA test will draw a single color page and change color
-- every one second. VGA resolution is 640x480 @25 MHZ 8 colors
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Pin Assignment:
-- MET clk50_in loc = T9
-- NET red_out LOC=R12;
-- NET green_out LOC=T12;
-- NET blue_out LOC=R11;
-- NET hs_out LOC=R9;
-- NET vs_out LOC=T10;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_11 64.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgatest is
port(clk50_in : in std_logic;
red_out : out std_logic;
green_out : out std_logic;
blue_out : out std_logic;
hs_out : out std_logic;
vs_out : out std_logic);
end vgatest;
architecture behavioral of vgatest is
signal clk25 : std_logic;
signal hcounter : integer range 0 to 800;
signal vcounter : integer range 0 to 521;
signal color: std_logic_vector(2 downto 0);
begin
-- generate a 25Mhz clock
process (clk50_in)
begin
if clk50_in'event and clk50_in='1' then
clk25 <= not clk25;
end if;
end process;
-- change color every one second
p1: process (clk25)
variable cnt: integer;
begin
if clk25'event and clk25='1' then
cnt := cnt + 1;
if cnt = 25000000 then
color <= color + "001";
cnt := 0;
end if;
end if;
end process;
p2: process (clk25, hcounter, vcounter)
variable x: integer range 0 to 639;
variable y: integer range 0 to 479;
begin
-- hcounter counts from 0 to 799
-- vcounter counts from 0 to 520
-- x coordinate: 0 - 639 (x = hcounter - 144, i.e., hcounter -Tpw-Tbp)
-- y coordinate: 0 - 479 (y = vcounter - 31, i.e., vcounter-Tpw-Tbp)
x := hcounter - 144;
y := vcounter - 31;
if clk25'event and clk25 = '1' then
-- To draw a pixel in (x0, y0), simply test if the ray trace to it
-- and set its color to any value between 1 to 7. The following example simply sets
-- the whole display area to a single-color wash, which is changed every one
-- second.
if x < 640 and y < 480 then
red_out <= color(0);
green_out <= color(1);
blue_out <= color(2);
else
-- if not traced, set it to "black" color
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
-- Here is the timing for horizontal synchronization.
-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
-- Pulse width: Tpw = 96 cycles @ 25 MHz
-- Back porch: Tbp = 48 cycles
-- Display time: Tdisp = 640 cycles
-- Front porch: Tfp = 16 cycles
-- Sync pulse time (total cycles) Ts = 800 cycles
if hcounter > 0 and hcounter < 97 then
hs_out <= '0';
else
hs_out <= '1';
end if;
-- Here is the timing for vertical synchronization.
-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
-- Pulse width: Tpw = 1600 cycles (2 lines) @ 25 MHz
-- Back porch: Tbp = 23200 cycles (29 lines)
-- Display time: Tdisp = 38400 cycles (480 lines)
-- Front porch: Tfp = 8000 cycles (10 lines)
-- Sync pulse time (total cycles) Ts = 416800 cycles (521 lines)
if vcounter > 0 and vcounter < 3 then
vs_out <= '0';
else
vs_out <= '1';
end if;
-- horizontal counts from 0 to 799
hcounter <= hcounter+1;
if hcounter = 800 then
vcounter <= vcounter+1;
hcounter <= 0;
end if;
-- vertical counts from 0 to 519
if vcounter = 521 then
vcounter <= 0;
end if;
end if;
end process;
end behavioral;
| mit | c81009c0ddd6358e21649a9413ec1192 | 0.605536 | 3.292107 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/control_unit.vhd | 1 | 2,754 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:23:52 10/22/2015
-- Design Name:
-- Module Name: control_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control_unit is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
hlt : in STD_LOGIC;
exe : out STD_LOGIC;
pc_en : out STD_LOGIC;
op_en : out STD_LOGIC;
mem_en : out STD_LOGIC);
end control_unit;
architecture Behavioral of control_unit is
-- Intermediate Signals --
signal cycle_counter : std_logic_vector( 2 downto 0 );
signal received_hlt : std_logic;
begin
process( clk )
begin
if reset = '1' then
cycle_counter <= "001";
exe <= '0';
op_en <= '1';
mem_en <= '0';
pc_en <= '1';
received_hlt <= '0';
elsif received_hlt = '0' then
if hlt = '1' then
cycle_counter <= "000";
exe <= '0';
op_en <= '0';
mem_en <= '0';
pc_en <= '0';
received_hlt <= '1';
elsif rising_edge(clk) then
-- Cycle 1 --
-- OP code --
if cycle_counter = "000" then
exe <= '0';
op_en <= '1';
mem_en <= '0';
pc_en <= '1';
-- Cycle 2, 3, 4 --
-- Address Writing --
elsif cycle_counter = "001" or cycle_counter = "010" or cycle_counter = "011" then
exe <= '0';
op_en <= '0';
mem_en <= '1';
pc_en <= '1';
-- Cycles 5 --
-- Execute --
elsif cycle_counter = "100" then
exe <= '0';
op_en <= '0';
mem_en <= '1';
pc_en <= '1';
-- Cycles 6 --
-- Execute --
elsif cycle_counter = "101" then
exe <= '1';
op_en <= '0';
mem_en <= '0';
pc_en <= '0';
end if;
if cycle_counter = "101" then
cycle_counter <= "000";
else
cycle_counter <= cycle_counter + '1';
end if;
else
end if;
else
cycle_counter <= "000";
exe <= '0';
op_en <= '0';
mem_en <= '0';
pc_en <= '0';
end if;
end process;
end Behavioral;
| unlicense | e1e224fe6cf80d2132cfa84a2adf7111 | 0.484386 | 3.066815 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/Reg.vhd | 2 | 1,294 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:13 10/22/2015
-- Design Name:
-- Module Name: Reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Reg is
Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end Reg;
architecture Behavioral of Reg is
begin
process(clk, rst)
begin
if clk' event and clk = '1' then
if enable = '1' then
data_out <= data_in;
end if;
end if;
if rst = '1' then
data_out <= "0000";
end if;
end process;
end Behavioral;
| unlicense | bdffa66c950704a7068d1f9611ad3c75 | 0.560278 | 3.68661 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/TB_GenReg_16.vhd | 1 | 2,356 | library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_REG_S16 is
end TB_REG_S16;
architecture Behavioral of TB_REG_S16 is
component REG_S16 is
generic(
REG_WIDTH: integer:=4 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
WE : in std_logic;
RESETN : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT REG_WIDTH:integer:=4;
signal CLOCK : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal RESETN : STD_LOGIC := '0';
signal REG_A_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_B_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_B : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_A_IN_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A_IN : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: REG_S16 port map(
CLOCK => Clock,
WE => WE,
RESETN => RESETN,
REG_A_ADDR => REG_A_ADDR,
REG_A => REG_A,
REG_B_ADDR => REG_B_ADDR,
REG_B => REG_B,
REG_A_IN_ADDR => REG_A_IN_ADDR,
REG_A_IN => REG_A_IN
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
REG_A_ADDR <= (others => '0');
REG_B_ADDR <= (others => '0');
REG_A_IN_ADDR <= (others => '0');
--Reset disable
RESETN <= '1'; wait for 2*period;
REG_A_IN <= x"FFFFFF";wait for 2*period;
--Enabling the register
WE <= '1'; wait for 2*period;
WE <= '0';
REG_A_IN_ADDR <= x"1";
WE <= '1'; wait for 2*period;
WE <= '0';
REG_B_ADDR <= x"1"; wait for 50*period;
end process;
end Behavioral;
| mit | cf3541d3902f43d9b073f6952d9a131c | 0.637946 | 2.586169 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/RegHold_Falling.vhd | 1 | 2,255 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: 24bit_Register
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Presenation Code: Dr.Fortier(c)
-- 24 bit register with a hold lock the input state just
-- incase input conflict later
--
-- Notes:
-- HOLD Clocked on FALLING EDGE
-- OUTPUT Clocked on rising EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
-- 0.05 - Forked and added a input hold for the register
--
-- Additional Comments:
-- The register latches it's output data on the Rising edge
-- Hold latch on the falling edge
-- The main reason why I included a hold latch was to Prevent
-- Any register transfer faults that could occur.
-- Mostly acts as a safety buffer.
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
ENTITY RegHold_F IS
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END RegHold_F;
ARCHITECTURE Behavior OF RegHold_F IS
SIGNAL HOLD : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS(Resetn, Clock,ENABLE)
BEGIN
IF Resetn = '0' THEN
HOLD <= (OTHERS => '0');
OUTPUT <= (OTHERS => '0');
ELSIF ENABLE = '1' THEN
IF Clock'EVENT AND Clock = '1' THEN
OUTPUT <= HOLD;
END IF;
IF Clock'EVENT AND Clock = '0' THEN
HOLD <= INPUT;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 00184ac606a2b5bb6bb96abcf230a671 | 0.562306 | 3.666667 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Registers/test/24bit_register_falling_clocked_With_HoldLatch.vhd | 1 | 1,609 | ------------------------------------------------------------
-- Notes:
-- HOLD Clocked on FALLING EDGE
-- OUTPUT Clocked on rising EDGE
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Cleaned up Code given
-- 0.03 - Incorporated a enable switch
-- 0.04 - Have the register latch data on the falling
-- clock cycle.
-- 0.05 - Forked and added a input hold for the register
--
-- Additional Comments:
-- The register latches it's output data on the Rising edge
-- Hold latch on the falling edge
-- The main reason why I included a hold latch was to Prevent
-- Any register transfer faults that could occur.
-- Mostly acts as a safety buffer.
--
-----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY Reg24_LATCH IS
GENERIC(
DATA_WIDTH:INTEGER := 24
);
PORT(
Clock : IN STD_LOGIC;
Resetn : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
HOLD_OUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
END Reg24_LATCH;
ARCHITECTURE Behavior OF Reg24_LATCH IS
SIGNAL HOLD : STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
HOLD_OUT <= HOLD;
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
HOLD <= (OTHERS => '0');
OUTPUT <= (OTHERS => '0');
ELSE
IF (ENABLE = '1') AND Clock'EVENT THEN
IF Clock = '1' THEN
OUTPUT <= HOLD;
ELSE
HOLD <= INPUT;
END IF;
END IF;
END IF;
END PROCESS;
END Behavior;
| mit | 5eb517712bd08da2033f09956adbaeb9 | 0.579863 | 3.317526 | false | false | false | false |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/ipcore_dir/sounds_mem/simulation/sounds_mem_tb.vhd | 2 | 4,367 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: sounds_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY sounds_mem_tb IS
END ENTITY;
ARCHITECTURE sounds_mem_tb_ARCH OF sounds_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
sounds_mem_synth_inst:ENTITY work.sounds_mem_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | 2b69a0caeb569140ad42aa70c770a89b | 0.620105 | 4.60654 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/clock_divider_V2.vhd | 1 | 2,690 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:39:36 11/01/2015
-- Design Name:
-- Module Name: clock_divider_V2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock_divider_V2 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out : out STD_LOGIC);
end clock_divider_V2;
architecture Behavioral of clock_divider_V2 is
-- Components --
component downcounter is
Generic ( period: integer:= 4;
WIDTH: integer:= 3);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
zero : out STD_LOGIC;
value: out STD_LOGIC_VECTOR(WIDTH-1 downto 0));
end component;
-- Internal Signals --
signal kilohertz: STD_LOGIC;
signal hundredhertz: STD_LOGIC;
signal tenhertz: STD_LOGIC;
signal onehertz: STD_LOGIC;
signal counter_value : STD_LOGIC_VECTOR( 3 downto 0 );
signal i_clk_out : std_logic;
begin
kiloHzClock: downcounter
generic map(
period => (39-1),
WIDTH => 15
)
port map (
clk => clk,
reset => reset,
enable => '1',
zero => kilohertz,
value => open
);
hundredHzClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => kilohertz,
zero => hundredhertz,
value => counter_value
);
tenHzClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => hundredhertz,
zero => tenhertz,
value => open
);
oneHZClock: downcounter
generic map(
period => (10-1),
WIDTH => 4
)
port map (
clk => clk,
reset => reset,
enable => tenhertz,
zero => onehertz,
value => open
);
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
i_clk_out <= '1';
elsif (counter_value = "1000") then -- switch polarity every half period
i_clk_out <= '0';
else
i_clk_out <= '1';
end if;
end if;
end process;
clk_out <= i_clk_out;
end Behavioral;
| unlicense | 3b2c674ee566803c26e37835bbc477ff | 0.572491 | 3.337469 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/VGA Read - Write/data_to_ascii.vhd | 1 | 2,907 | --------------------------------------------------------------------------------
-- Company: UMD ECE
-- Engineers: Benjamin Doiron
--
-- Create Date: 12:35:25 03/26/2014
-- Design Name: Data To Ascii
-- Module Name: data_to_ascii
-- Project Name: Risc Machine Project 1
-- Target Device: Spartan 3E Board
-- Tool versions: Xilinx 14.7
-- Description: This code takes in output data from the FPU and
-- begins the process of outputting it to screen. Data is sent through
-- and each grouping of hex data is read individually. Data is collected and
-- sent to the VGA as though it were keyboard data.
--
-- Currently this is in modification and will change drastically to suit
-- the needs of the lab.
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: N/A
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity data_to_ascii is
Port (
clk : in STD_LOGIC;
IN_DATA : in STD_LOGIC_VECTOR (23 downto 0);
OUT_ASCII : out STD_LOGIC_VECTOR (7 downto 0);
debugoutput : out STD_LOGIC_VECTOR (7 downto 0)
);
end data_to_ascii;
architecture Behavioral of data_to_ascii is
signal counter: integer range 0 to 6;
signal datacode : STD_LOGIC_VECTOR(3 downto 0);
signal output : STD_LOGIC_VECTOR (7 downto 0);
begin
process(clk)
begin
if(clk'event and clk = '1') then
case counter is
when 0 => datacode <= IN_DATA (23 downto 20);
when 1 => datacode <= IN_DATA (19 downto 16);
when 2 => datacode <= IN_DATA (15 downto 12);
when 3 => datacode <= IN_DATA (11 downto 8);
when 4 => datacode <= IN_DATA ( 7 downto 4);
when others => datacode <= IN_DATA ( 3 downto 0);
end case;
case datacode is
when x"0" => output <= x"30";
when x"1" => output <= x"31";
when x"2" => output <= x"32";
when x"3" => output <= x"33";
when x"4" => output <= x"34";
when x"5" => output <= x"35";
when x"6" => output <= x"36";
when x"7" => output <= x"37";
when x"8" => output <= x"38";
when x"9" => output <= x"39";
when x"A" => output <= x"41";
when x"B" => output <= x"42";
when x"C" => output <= x"43";
when x"D" => output <= x"44";
when x"E" => output <= x"45";
when x"F" => output <= x"46";
when others => output <= x"00";
end case;
debugoutput <= output;
if (output > x"00") then
OUT_ASCII <= output;
end if;
if (counter > 4) then
counter <= counter + 1;
else
counter <= 0;
end if;
end if;
end process;
-- There needs to be something that prevents it from reading the same data over and over
-- maybe a flag saying when new dats is sent out?
-- Then maybe we could put the data into a buffer or something.
-- Right now there could be issues.
end Behavioral; | mit | b6b1eccdbc1cafcf85c3c1f5dff49b47 | 0.589611 | 3.177049 | false | false | false | false |
NuclearKev/iir-hardware | FSM-iir.vhd | 1 | 6,285 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
sample_trig : in std_logic;
done : out std_logic;
-- coefficient
--i_bcoeff_0 : in std_logic_vector(14 downto 0);
--i_bcoeff_1 : in std_logic_vector(14 downto 0);
--i_bcoeff_2 : in std_logic_vector(14 downto 0);
--i_acoeff_1 : in std_logic_vector(14 downto 0);
--i_acoeff_2 : in std_logic_vector(14 downto 0);
-- data input
i_data : in std_logic_vector(15 downto 0);
-- filtered data
o_data : out std_logic_vector(15 downto 0));
end iir;
architecture Behavioral of iir is
type t_data_pipe is array (0 to 2) of signed(15 downto 0);
type t_fdata_pipe is array (0 to 1) of signed(15 downto 0);
type t_bcoeff is array (0 to 2) of signed(15 downto 0);
type t_acoeff is array (0 to 1) of signed(15 downto 0);
type t_mult is array (0 to 2) of signed(31 downto 0);
type t_fmult is array (0 to 1) of signed(31 downto 0);
signal r_bcoeff : t_bcoeff;
signal r_acoeff : t_acoeff;
signal p_data : t_data_pipe;
signal p_fdata : t_fdata_pipe;
signal r_mult : t_mult;
signal r_fmult : t_fmult;
signal r_odata : signed(15 downto 0);
signal r_add : signed(31+1 downto 0);
signal r_fadd : signed(31+1 downto 0);
signal r_final_sum : signed(31+2 downto 0);
-- state machine signals
type state_type is (idle_state, data_state, mult_state, add_state, final_state, data_out_state);
signal state_reg, state_next : state_type;
signal data, data_done, mult, mult_done, add, add_done, final, final_done, data_out, data_out_done : std_logic;
begin
p_state_change : process (i_rstb,i_clk)
begin
if(i_rstb='1') then
state_reg <= idle_state;
elsif (rising_edge(i_clk)) then
state_reg <= state_next;
end if;
end process p_state_change;
process(state_reg, sample_trig,data_done,mult_done,add_done,final_done,data_out_done)
begin
-- defaults
data <= '0';
mult <= '0';
add <= '0';
data_out <= '0';
case state_reg is
when idle_state =>
data_out <= '0';
if(sample_trig = '1') then
state_next <= data_state;
else
state_next <= idle_state;
end if;
when data_state =>
data <= '1';
if(data_done='1') then
state_next <= mult_state;
data <= '0';
else
state_next <= data_state;
end if;
when mult_state=>
mult <= '1';
if(mult_done='1') then
state_next <= add_state;
mult <= '0';
else
state_next <= mult_state;
end if;
when add_state =>
add <= '1';
if(add_done='1') then
state_next <= final_state;
add <= '0';
else
state_next <= add_state;
end if;
when final_state =>
final <= '1';
if(final_done='1') then
state_next <= data_out_state;
final <= '0';
else
state_next <= final_state;
end if;
when data_out_state =>
data_out <= '1';
if(data_out_done='1') then
state_next <= idle_state;
data_out <= '0';
else
state_next <= data_out_state;
end if;
end case;
end process;
--- Data input ---
p_data_input : process (i_rstb,i_clk,data)
begin
if(i_rstb='1') then
p_data <= (others=>(others=>'0'));
p_fdata <= (others=>(others=>'0'));
data_done <= '0';
elsif(rising_edge(i_clk)) then
if(data = '1') then
p_data <= signed(i_data)&p_data(0 to p_data'length-2); --this might need to change to a minus 8
p_fdata(1) <= p_fdata(0);
p_fdata(0) <= r_odata;
r_bcoeff(0) <= x"2F61";
r_bcoeff(1) <= x"A13C";
r_bcoeff(2) <= x"2F61";
r_acoeff(0) <= x"E86B";
r_acoeff(1) <= x"0000";
data_done <= '1';
else
data_done <= '0';
end if;
end if;
end process p_data_input;
--- Feedforward & Feedback ---
p_mult : process (i_rstb,i_clk,mult)
begin
if(i_rstb='1') then
r_mult <= (others=>(others=>'0'));
r_fmult <= (others=>(others=>'0'));
mult_done <= '0';
elsif(rising_edge(i_clk)) then
if(mult='1') then
r_mult(0) <= p_data(0) * r_bcoeff(0);
r_mult(1) <= p_data(1) * r_bcoeff(1);
r_mult(2) <= p_data(2) * r_bcoeff(2);
r_fmult(0) <= p_fdata(0) * r_acoeff(0);
r_fmult(1) <= p_fdata(1) * r_acoeff(1);
mult_done <= '1';
else
mult_done <= '0';
end if;
end if;
end process p_mult;
p_add : process (i_rstb,i_clk,add)
begin
if(i_rstb='1') then
r_add <=(others=>'0');
r_fadd <=(others=>'0');
add_done <= '0';
elsif(rising_edge(i_clk)) then
if(add = '1') then
r_add <= resize(r_mult(0),33) + resize(r_mult(1),33) + resize(r_mult(2),33);
r_fadd <= resize(r_fmult(0),33) + resize(r_fmult(1),33);
add_done <= '1';
else
add_done <= '0';
end if;
end if;
end process p_add;
p_final_sum : process (i_rstb,i_clk,final)
begin
if(i_rstb='1') then
r_final_sum <= (others=>'0');
final_done <= '0';
elsif(rising_edge(i_clk)) then
if(final='1') then
r_final_sum <= resize(r_add, 34) - resize(r_fadd,34);
final_done <= '1';
else
final_done <= '0';
end if;
end if;
end process p_final_sum;
--- Output ---
p_output : process (i_rstb,i_clk,data_out)
begin
if(i_rstb='1') then
o_data <= (others=>'0');
done <= '0';
data_out_done <= '0';
elsif(rising_edge(i_clk)) then
if(data_out = '1') then
done <= '1';
r_odata <= r_final_sum(33 downto 18);
o_data <= std_logic_vector(r_final_sum(33 downto 18));
data_out_done <= '1';
else
done <= '0';
data_out_done <= '0';
end if;
end if;
end process p_output;
end Behavioral;
| lgpl-3.0 | ddff6557fe5c0b48ea8c5e2a03a0baa4 | 0.508671 | 2.982914 | false | false | false | false |
vpereira/golden_unicorn | bin/fpga/ipcore_dir/mem0/user_design/rtl/iodrp_controller.vhd | 1 | 14,635 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2010/03/21 17:21:17 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 02/06/09: Initial version for MIG wrapper.
-- 1.1: 02/01/09: updates to indentations.
-- 1.2: 02/12/09: changed non-blocking assignments to blocking ones
-- for state machine always block. Also, assigned
-- intial value to load_shift_n to avoid latch
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues
-- to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
-- added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end entity iodrp_controller;
architecture trans of iodrp_controller is
constant READY : std_logic_vector(2 downto 0) := "000";
constant DECIDE : std_logic_vector(2 downto 0) := "001";
constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010";
constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101";
constant DATA_PHASE : std_logic_vector(2 downto 0) := "110";
constant ALMOST_READY : std_logic_vector(2 downto 0) := "111";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(7 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal capture_read_data : std_logic;
signal state : std_logic_vector(2 downto 0);
signal nextstate : std_logic_vector(2 downto 0);
signal data_out_mux : std_logic_vector(7 downto 0);
signal DRP_SDI_pre : std_logic;
signal ALMOST_READY_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
begin
--synthesis translate_off
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY => -- case(state)
-- state_ascii <= "ALMOST_READY";
-- when others =>
-- null;
-- end case;
-- end process;
--synthesis translate_on
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when (state = READY) else '0';
data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
data_reg;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "00000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
-- capture_read_data <= 1'b0;
read_data <= "00000000";
else
-- capture_read_data <= (state == DATA_PHASE);
-- if(capture_read_data)
if (state = ALMOST_READY) then
-- else
-- read_data <= read_data;
read_data <= shift_through_reg;
end if;
end if;
end if;
end process;
ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD <= ADDR_PHASE_ST1;
DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
-- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
-- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the read access.
when ADDR_PHASE =>
if (BIT_CNT7 = '1') then
if (rd_not_write_reg = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
nextstate <= READY;
when others =>
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 | b5643c753d23883c8aef4f3971d78377 | 0.558661 | 3.872718 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/RegisterBank/RegisterBankInt.vhd | 1 | 2,952 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: REGBank
-- Project Name: REGBank
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Register Bank with interupt mode
-- When the system enters interupt mode the
-- registers will swapped with a temporal
-- register bank that will only last till
-- interupt mode is complete and will resume
-- previous register bank.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ALL;
entity RegBankInt is
GENERIC (DATA_WIDTH:positive:=16; REG_SIZE:positive:=4);
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
-- Register A
RegA_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegA : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Register B
RegB_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegB : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
-- Input Register
RegIN : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
RegIN_Sel : in STD_LOGIC_VECTOR (REG_SIZE-1 downto 0);
RegIN_WE : in STD_LOGIC;
-- Interupt Mode
RegIntMode : in STD_LOGIC
);
end RegBankInt;
architecture Behavioral of RegBankInt is
signal RA,RAI : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal RB,RBI : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
type Reg_Array_Type is array (0 to 15) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
signal RegArray: Reg_Array_Type;
signal IntRegArray: Reg_Array_Type;
begin
--Reg A
RA <= RegArray(to_integer(unsigned(RegA_Sel)));
--Reg B
RB <= RegArray(to_integer(unsigned(RegB_Sel)));
--Reg A Interupt Bank
RAI <= IntRegArray(to_integer(unsigned(RegA_Sel)));
--Reg B Interupt Bank
RBI <= IntRegArray(to_integer(unsigned(RegB_Sel)));
--Process to handle updates of the register bank
process(RST,CLK)
begin
if (RST = '1') then
RegArray <= (OTHERS => (OTHERS => '0'));
IntRegArray <= (OTHERS => (OTHERS => '0'));
elsif (clk'event and clk='1') then
if (RegIntMode = '0') then
if (RegIN_WE = '1') then
RegArray(to_integer(unsigned(RegIN_Sel))) <= RegIN;
end if;
IntRegArray <= (OTHERS => (OTHERS => '0'));
else
if (RegIN_WE = '1') then
IntRegArray(to_integer(unsigned(RegIN_Sel))) <= RegIN;
end if;
end if;
end if;
end process;
--Select which bank is being used
WITH RegIntMode SELECT
RegA <= RA WHEN '0',
RAI WHEN '1',
RA WHEN OTHERS;
WITH RegIntMode SELECT
RegB <= RB WHEN '0',
RBI WHEN '1',
RB WHEN OTHERS;
end Behavioral;
| mit | 9717fc004398ef954eb0f3c40f80dd4b | 0.594173 | 3.586877 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/CPU_RAM.vhd | 1 | 2,208 | ----------------------------------------------------------------------------------
-- Company: Nibble Knowledge
-- Engineer: Colton Schmidt
--
-- Create Date: 13:27:13 10/18/2015
-- Design Name:
-- Module Name: CPU_RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: A simulation of the CPU memory. Code is a modified version of code from:
-- https://www.doulos.com/knowhow/vhdl_designers_guide/models/simple_ram_model/
--
-- Copyright of orignal code: 2008 Douglos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU_RAM is
Port ( data : inout STD_LOGIC_VECTOR (3 downto 0);
address : in STD_LOGIC_VECTOR (15 downto 0);
write_enable : in STD_LOGIC;
clk : in STD_LOGIC;
chip_select : out std_logic_vector(3 downto 0);
data_buss : out std_logic_vector(3 downto 0);
parity_chk : in std_logic;
io_read : out std_logic;
io_write : out std_logic;
io_ready : in std_logic);
end CPU_RAM;
architecture Behavioral of CPU_RAM is
type ram is array (0 to (2**16)-1) of STD_LOGIC_VECTOR (3 downto 0);
--Internal Signals --
--signal cpu_ram : ram( 0 to (2**16)-1, 0 to 3) := (others => ( others => ( others => '0')));
signal cpu_ram : ram;
begin
process(clk) is
begin
if rising_edge(clk) then
if write_enable = '1' then
cpu_ram(to_integer(unsigned(address))) <= data;
else
data <= cpu_ram(to_integer(unsigned(address)));
end if;
end if;
end process;
-- IO Mapping
-- OUT
chip_select <= cpu_ram( 0 );
data_buss <= cpu_ram( 2 );
io_read <= cpu_ram( 1, 0);
io_write <= cpu_ram( 1, 1);
-- IN
cpu_ram( 1, 3) <= parity_chk;
cpu_ram( 1, 2) <= io_ready;
end Behavioral;
| unlicense | 278f30a6fc51310da6958100e8c38c21 | 0.59375 | 3.22807 | false | false | false | false |
NuclearKev/iir-hardware | iir.vhd | 1 | 5,781 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iir is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- ready : in std_logic;
done : out std_logic;
-- coefficient
i_b_0 : in std_logic_vector(14 downto 0);
i_b_1 : in std_logic_vector(14 downto 0);
i_b_2 : in std_logic_vector(14 downto 0);
i_b_3 : in std_logic_vector(14 downto 0);
i_a_1 : in std_logic_vector(14 downto 0);
i_a_2 : in std_logic_vector(14 downto 0);
i_a_3 : in std_logic_vector(14 downto 0);
-- data input
i_data : in std_logic_vector(11 downto 0);
-- filtered data
o_data : out std_logic_vector(11 downto 0));
end iir;
architecture Behavioral of iir is
type t_data_pipe is array (0 to 3) of signed(11 downto 0);
type t_fdata_pipe is array (0 to 3) of signed(11 downto 0);
type t_bcoeff is array (0 to 3) of signed(14 downto 0);
type t_acoeff is array (0 to 3) of signed(14 downto 0);
type t_mult is array (0 to 3) of signed(26 downto 0);
type t_fmult is array (0 to 3) of signed(26 downto 0);
type t_add_st0 is array (0 to 1) of signed(26+1 downto 0);
type t_fadd_st0 is array (0 to 1) of signed(26+1 downto 0);
signal r_bcoeff : t_bcoeff;
signal r_acoeff : t_acoeff;
signal p_data : t_data_pipe;
signal p_fdata : t_fdata_pipe;
signal r_mult : t_mult;
signal r_fmult : t_fmult;
signal r_add_st0 : t_add_st0;
signal r_fadd_st0 : t_fadd_st0;
signal r_add_st1 : signed(26+2 downto 0);
signal r_fadd_st1 : signed(26+2 downto 0);
signal r_final_sum : signed(26+2 downto 0);
signal out_buf : signed(11 downto 0);
begin
--- Data input ---
p_input : process (i_rstb,i_clk)
begin
if(i_rstb='1') then
p_data <= (others=>(others=>'0'));
p_fdata <= (others=>(others=>'0'));
r_bcoeff <= (others=>(others=>'0'));
r_acoeff <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
p_fdata <= out_buf & p_fdata(0 to p_fdata'length-2);
r_bcoeff(0) <= signed(i_b_0);
r_bcoeff(1) <= signed(i_b_1);
r_bcoeff(2) <= signed(i_b_2);
r_bcoeff(3) <= signed(i_b_3);
r_acoeff(0) <= signed(i_a_1);
r_acoeff(1) <= signed(i_a_2);
r_acoeff(2) <= signed(i_a_3);
-- r_acoeff(3) <= signed('0');
end if;
end process p_input;
--- Feedforward ---
p_mult : process (i_rstb,i_clk,p_data,r_bcoeff,p_fdata,r_acoeff)
begin
if(i_rstb='1') then
r_mult <= (others=>(others=>'0'));
r_fmult <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 3 loop
r_mult(k) <= p_data(k) * r_bcoeff(k);
r_fmult(k) <= p_fdata(k) * r_acoeff(k);
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk,r_mult,r_fmult)
begin
if(i_rstb='1') then
r_add_st0 <= (others=>(others=>'0'));
r_fadd_st0 <= (others=>(others=>'0'));
elsif(i_clk='1') then
for k in 0 to 1 loop
r_add_st0(k) <= resize(r_mult(2*k),28) + resize(r_mult(2*k+1),28);
r_fadd_st0(k) <= resize(r_fmult(2*k),28) + resize(r_fmult(2*k+1),28);
end loop;
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk,r_add_st0,r_fadd_st0)
begin
if(i_rstb='1') then
r_add_st1 <= (others=>'0');
r_fadd_st1 <= (others=>'0');
elsif(i_clk='1') then
r_add_st1 <= resize(r_add_st0(0),29) + resize(r_add_st0(1),29);
r_fadd_st1 <= resize(r_fadd_st0(0),29) + resize(r_fadd_st0(1),29);
end if;
end process p_add_st1;
--- Feedback ---
-- p_fmult : process (i_rstb,i_clk,p_fdata,r_acoeff)
-- begin
-- if(i_rstb='1') then
-- r_fmult <= (others=>(others=>'0'));
-- elsif(i_clk='1') then
-- for k in 0 to 3 loop
-- r_fmult(k) <= p_fdata(k) * r_acoeff(k);
-- end loop;
-- end if;
-- end process p_fmult;
-- p_fadd_st0 : process (i_rstb,i_clk,r_fmult)
-- begin
-- if(i_rstb='1') then
-- r_fadd_st0 <= (others=>(others=>'0'));
-- elsif(i_clk='1') then
-- for k in 0 to 1 loop
-- r_fadd_st0(k) <= resize(r_fmult(2*k),28) + resize(r_fmult(2*k+1),28);
-- end loop;
-- end if;
-- end process p_fadd_st0;
-- p_fadd_st1 : process (i_rstb,i_clk,r_fadd_st0)
-- begin
-- if(i_rstb='1') then
-- r_fadd_st1 <= (others=>'0');
-- elsif(i_clk='1') then
-- r_fadd_st1 <= resize(r_fadd_st0(0),29) + resize(r_fadd_st0(1),29);
-- end if;
-- end process p_fadd_st1;
p_final_sum : process (i_rstb,i_clk,r_add_st1,r_fadd_st1)
begin
if(i_rstb='1') then
r_final_sum <= (others=>'0');
elsif(i_clk='1') then
r_final_sum <= r_add_st1 - r_fadd_st1;
end if;
end process p_final_sum;
p_output : process (i_rstb,i_clk,r_final_sum,p_fdata,out_buf)
begin
done <= '0';
if(i_rstb='1') then
o_data <= (others=>'0');
done <= '0';
elsif(i_clk='1') then
done <= '1';
out_buf <= r_final_sum(26 downto 15);
o_data <= std_logic_vector(out_buf);
end if;
end process p_output;
-- p_done : process (i_rstb, i_clk)
-- begin
-- if(i_rstb='0') then
-- done <= '0';
-- elsif(rising_edge(i_clk)) then
-- done <= '1';
-- end if;
-- end process p_done;
end Behavioral;
| lgpl-3.0 | 74f49474afb9fa0eaa9c57e518dfaf07 | 0.508736 | 2.588894 | false | false | false | false |
aleksandar-mitrevski/hw_sw | hybrid_velocity_counter/testbench.vhd | 1 | 2,190 | library IEEE;
use IEEE.std_logic_1164.All;
use std.textio.all;
entity testbench is end testbench;
architecture tb_velocity of testbench is
signal clk : std_logic := '0';
signal encoder : std_logic := '0';
signal speed : real;
signal measurementType : std_logic;
file encoder_switching_times : text open read_mode is "switching_times.dat";
constant twenty_five_nsec : time := 25 ns;
component HybridVelocityCounter port (
clk : in std_logic;
encoder : in std_logic;
speed : out real;
measurementType: out std_logic);
end component HybridVelocityCounter;
begin
HybridVelocityCounter1 : HybridVelocityCounter
port map (
clk => clk,
encoder => encoder,
speed => speed,
measurementType => measurementType);
create_twenty_Mhz: process
begin
wait for twenty_five_nsec;
clk <= NOT clk;
end process;
change_encoder: process
variable currentLine : line;
variable waitTime : time;
variable timeChange : integer := 0;
begin
while not (endfile(encoder_switching_times)) loop
if timeChange = 1500 then
assert measurementType = '0' report "1 failed";
elsif timeChange = 3000 then
assert measurementType = '0' report "2 failed";
elsif timeChange = 4500 then
assert measurementType = '1' report "3 failed";
elsif timeChange = 6000 then
assert measurementType = '1' report "4 failed";
elsif timeChange = 7500 then
assert measurementType = '1' report "5 failed";
elsif timeChange = 9000 then
assert measurementType = '1' report "6 failed";
elsif timeChange = 10500 then
assert measurementType = '0' report "7 failed";
end if;
readline(encoder_switching_times, currentLine);
read(currentLine, waitTime);
timeChange := timeChange + (waitTime / 1 ns);
wait for waitTime;
encoder <= not encoder;
end loop;
wait;
end process;
end tb_velocity;
| mit | d1e9151b5e8fc621482a32f2b922470a | 0.596347 | 4.506173 | false | false | false | false |
ErikAndren/fpga-sramtest | SramTestGen.vhd | 1 | 2,929 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity SramTestGen is
generic (
AddrW : positive;
DataW : positive);
port (
Clk : in bit1;
Rst_N : in bit1;
--
Btn0 : in bit1;
Btn1 : in bit1;
Btn2 : in bit1;
Btn3 : in bit1;
--
We : out bit1;
Re : out bit1;
Addr : out word(AddrW-1 downto 0);
Data : out word(DataW-1 downto 0)
);
end entity SramTestGen;
architecture rtl of SramTestGen is
constant StartCnt : positive := 25000000;
signal StartCnt_D, StartCnt_N : word(bits(StartCnt)-1 downto 0);
signal Data_D, Data_N : word(4-1 downto 0);
signal Addr_D, Addr_N : word(2-1 downto 0);
signal Btn_D : word(4-1 downto 0);
signal StrobeCnt_D, StrobeCnt_N : word(bits(StartCnt)-1 downto 0);
begin -- rtl
StimSync : process (Clk, Rst_N)
begin -- process Stim
if Rst_N = '0' then -- asynchronous reset (active low)
StartCnt_D <= conv_word(StartCnt, StartCnt_D'length);
Data_D <= (others => '0');
Addr_D <= (others => '0');
Btn_D <= (others => '1');
StrobeCnt_D <= conv_word(StartCnt, StrobeCnt_D'length);
elsif Clk'event and Clk = '1' then -- rising clock edge
StartCnt_D <= StartCnt_N;
Data_D <= Data_N;
Addr_D <= Addr_N;
Btn_D <= Btn3 & Btn2 & Btn1 & Btn0;
StrobeCnt_D <= StrobeCnt_N;
end if;
end process StimSync;
StimAsync : process (StartCnt_D, Data_D, Addr_D, StrobeCnt_D, Btn0, Btn1)
begin
StartCnt_N <= StartCnt_D;
StrobeCnt_N <= StrobeCnt_D - 1;
--
We <= '0';
Re <= '0';
Addr <= (others => '0');
Data <= (others => '0');
Data_N <= Data_D;
Addr_N <= Addr_D;
if StartCnt_D > 0 then
StartCnt_N <= StartCnt_D - 1;
end if;
-- Perform write
if StartCnt_D = 12 then
We <= '1';
Addr <= (others => '0');
Data <= xt0("1111", Data'length);
end if;
if StartCnt_D = 10 then
We <= '1';
Addr <= conv_word(1, Addr'length);
Data <= xt0("1110", Data'length);
end if;
if StartCnt_D = 8 then
We <= '1';
Addr <= conv_word(2, Addr'length);
Data <= xt0("1100", Data'length);
end if;
if StartCnt_D = 6 then
We <= '1';
Addr <= conv_word(3, Addr'length);
Data <= xt0("1000", Data'length);
end if;
-- Perform first read
if StartCnt_D = 1 then
Re <= '1';
Addr <= (others => '0');
end if;
if (StrobeCnt_D = 0) then
if (Btn0 = '0') then
Addr_N <= Addr_D + 1;
Re <= '1';
Addr <= xt0(Addr_D + 1, Addr'length);
end if;
if (Btn1 = '0') then
Addr_N <= Addr_D - 1;
Re <= '1';
Addr <= xt0(Addr_D - 1, Addr'length);
end if;
end if;
end process;
end rtl;
| mit | 94d16a4d49e8b953e7b75af81d77063b | 0.523387 | 2.885714 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/REG_S16.vhd | 1 | 2,692 | ------------------------------------------------------------
-- School: University of Massachusetts Dartmouth --
-- Department: Computer and Electrical Engineering --
-- Class: ECE 368 Digital Design --
-- Engineer: Daniel Noyes --
-- Massarrah Tannous --
------------------------------------------------------------
--
-- Create Date: Spring 2014
-- Module Name: GenReg_16
-- Project Name: UMD-RISC 24
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- Code was modified from Handout Code: Dr.Fortier(c)
-- 16 General Purpose Registers
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- 0.01 - File Created
-- 0.02 - Incorporated a memory init [1]
--
-- Additional Comments:
-- [1]: code adaptive from the following blog
-- http://myfpgablog.blogspot.com/2011/12/memory-initialization-methods.html
-- this site pointed to XST user guide
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity REG_S16 is
generic(
REG_WIDTH: integer:=4; -- select between 16 different possible registers
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--RESETN : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end REG_S16;
architecture REG_ARCH of REG_S16 is
type ram_type is array (0 to 2**REG_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal ram: ram_type := (
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 0 - 7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000" -- 8 - F
);
signal ADDR_A_REG: std_logic_vector(REG_WIDTH-1 downto 0);
signal ADDR_B_REG: std_logic_vector(REG_WIDTH-1 downto 0);
begin
process(CLOCK,WE)
begin
if (CLOCK'event and CLOCK = '0') then
if (WE = '1') then
ram(to_integer(unsigned(REG_A_IN_ADDR))) <= REG_A_IN;
end if;
ADDR_A_REG <= REG_A_ADDR;
ADDR_B_REG <= REG_B_ADDR;
end if;
end process;
REG_A <= ram(to_integer(unsigned(ADDR_A_REG)));
REG_B <= ram(to_integer(unsigned(ADDR_B_REG)));
end REG_ARCH;
| mit | eb3d4d3c646ba7dc332b410b8fcd2db4 | 0.57578 | 3.112139 | false | false | false | false |
Reiuiji/VHDL-Emporium | VHDL/Memory/RAM_8x24.vhd | 1 | 4,424 | ------------------------------------------------------------
-- 8 Byte X 24 byte memory
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity RAM_8x24 is
generic(
RAM_WIDTH: integer:=8; -- 00 - FF choice
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--OUTPUT RAM
OUT_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
OUT_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
--INPUT RAM
IN_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
IN_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end RAM_8x24;
architecture RAM_ARCH of RAM_8x24 is
type ram_type is array (0 to 2**RAM_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM : ram_type := (
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 00 - 07
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 08 - 0F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 10 - 17
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 18 - 1F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 20 - 27
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 28 - 2F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 30 - 37
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 38 - 3F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 40 - 47
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 48 - 4F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 50 - 57
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 58 - 5F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 60 - 67
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 68 - 6F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 70 - 77
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 78 - 7F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 80 - 87
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 88 - 8F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 90 - 97
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 98 - 9F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A0 - A7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A8 - AF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B0 - B7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B8 - BF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C0 - C7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C8 - CF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D0 - D7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D8 - DF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E0 - E7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E8 - EF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- F0 - F7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000" -- F8 - FF
);
signal ADDR_IN: std_logic_vector(RAM_WIDTH-1 downto 0);
begin
process(CLOCK,WE)
begin
if (CLOCK'event and CLOCK = '0') then
if (WE = '1') then
RAM(to_integer(unsigned(IN_ADDR))) <= IN_DATA;
end if;
ADDR_IN <= OUT_ADDR;
end if;
end process;
OUT_DATA <= RAM(to_integer(unsigned(ADDR_IN)));
end RAM_ARCH;
| mit | a095e1b5bb3ac04290cb50580ef8239e | 0.588834 | 2.673112 | false | false | false | false |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/ddr2_phy_alt_mem_phy_seq.vhd | 2 | 647,533 | --
-- -----------------------------------------------------------------------------
-- Abstract : constants package for the non-levelling AFI PHY sequencer
-- The constant package (alt_mem_phy_constants_pkg) contains global
-- 'constants' which are fixed thoughout the sequencer and will not
-- change (for constants which may change between sequencer
-- instances generics are used)
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr2_phy_alt_mem_phy_constants_pkg is
-- -------------------------------
-- Register number definitions
-- -------------------------------
constant c_max_mode_reg_index : natural := 13; -- number of MR bits..
-- Top bit of vector (i.e. width -1) used for address decoding :
constant c_debug_reg_addr_top : natural := 3;
constant c_mmi_access_codeword : std_logic_vector(31 downto 0) := X"00D0_0DEB"; -- to check for legal Avalon interface accesses
-- Register addresses.
constant c_regofst_cal_status : natural := 0;
constant c_regofst_debug_access : natural := 1;
constant c_regofst_hl_css : natural := 2;
constant c_regofst_mr_register_a : natural := 5;
constant c_regofst_mr_register_b : natural := 6;
constant c_regofst_codvw_status : natural := 12;
constant c_regofst_if_param : natural := 13;
constant c_regofst_if_test : natural := 14; -- pll_phs_shft, ac_1t, extra stuff
constant c_regofst_test_status : natural := 15;
constant c_hl_css_reg_cal_dis_bit : natural := 0;
constant c_hl_css_reg_phy_initialise_dis_bit : natural := 1;
constant c_hl_css_reg_init_dram_dis_bit : natural := 2;
constant c_hl_css_reg_write_ihi_dis_bit : natural := 3;
constant c_hl_css_reg_write_btp_dis_bit : natural := 4;
constant c_hl_css_reg_write_mtp_dis_bit : natural := 5;
constant c_hl_css_reg_read_mtp_dis_bit : natural := 6;
constant c_hl_css_reg_rrp_reset_dis_bit : natural := 7;
constant c_hl_css_reg_rrp_sweep_dis_bit : natural := 8;
constant c_hl_css_reg_rrp_seek_dis_bit : natural := 9;
constant c_hl_css_reg_rdv_dis_bit : natural := 10;
constant c_hl_css_reg_poa_dis_bit : natural := 11;
constant c_hl_css_reg_was_dis_bit : natural := 12;
constant c_hl_css_reg_adv_rd_lat_dis_bit : natural := 13;
constant c_hl_css_reg_adv_wr_lat_dis_bit : natural := 14;
constant c_hl_css_reg_prep_customer_mr_setup_dis_bit : natural := 15;
constant c_hl_css_reg_tracking_dis_bit : natural := 16;
constant c_hl_ccs_num_stages : natural := 17;
-- -----------------------------------------------------
-- Constants for DRAM addresses used during calibration:
-- -----------------------------------------------------
-- the mtp training pattern is x30F5
-- 1. write 0011 0000 and 1100 0000 such that one location will contains 0011 0000
-- 2. write in 1111 0101
-- also require locations containing all ones and all zeros
-- default choice of calibration burst length (overriden to 8 for reads for DDR3 devices)
constant c_cal_burst_len : natural := 4;
constant c_cal_ofs_step_size : natural := 8;
constant c_cal_ofs_zeros : natural := 0 * c_cal_ofs_step_size;
constant c_cal_ofs_ones : natural := 1 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_0 : natural := 2 * c_cal_ofs_step_size;
constant c_cal_ofs_x30_almt_1 : natural := 3 * c_cal_ofs_step_size;
constant c_cal_ofs_xF5 : natural := 5 * c_cal_ofs_step_size;
constant c_cal_ofs_wd_lat : natural := 6 * c_cal_ofs_step_size;
constant c_cal_data_len : natural := c_cal_ofs_wd_lat + c_cal_ofs_step_size;
constant c_cal_ofs_mtp : natural := 6*c_cal_ofs_step_size;
constant c_cal_ofs_mtp_len : natural := 4*4;
constant c_cal_ofs_01_pairs : natural := 2 * c_cal_burst_len;
constant c_cal_ofs_10_pairs : natural := 3 * c_cal_burst_len;
constant c_cal_ofs_1100_step : natural := 4 * c_cal_burst_len;
constant c_cal_ofs_0011_step : natural := 5 * c_cal_burst_len;
-- -----------------------------------------------------
-- Reset values. - These are chosen as default values for one PHY variation
-- with DDR2 memory and CAS latency 6, however in each calibration
-- mode these values will be set for a given PHY configuration.
-- -----------------------------------------------------
constant c_default_rd_lat : natural := 20;
constant c_default_wr_lat : natural := 5;
-- -----------------------------------------------------
-- Errorcodes
-- -----------------------------------------------------
-- implemented
constant C_SUCCESS : natural := 0;
constant C_ERR_RESYNC_NO_VALID_PHASES : natural := 5; -- No valid data-valid windows found
constant C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS : natural := 6; -- Multiple equally-sized data valid windows
constant C_ERR_RESYNC_NO_INVALID_PHASES : natural := 7; -- No invalid data-valid windows found. Training patterns are designed so that there should always be at least one invalid phase.
constant C_ERR_CRITICAL : natural := 15; -- A condition that can't happen just happened.
constant C_ERR_READ_MTP_NO_VALID_ALMT : natural := 23;
constant C_ERR_READ_MTP_BOTH_ALMT_PASS : natural := 24;
constant C_ERR_WD_LAT_DISAGREEMENT : natural := 22; -- MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS copies of write-latency are written to memory. If all of these are not the same this error is generated.
constant C_ERR_MAX_RD_LAT_EXCEEDED : natural := 25;
constant C_ERR_MAX_TRK_SHFT_EXCEEDED : natural := 26;
-- not implemented yet
constant c_err_ac_lat_some_beats_are_different : natural := 1; -- implies DQ_1T setup failure or earlier.
constant c_err_could_not_find_read_lat : natural := 2; -- dodgy RDP setup
constant c_err_could_not_find_write_lat : natural := 3; -- dodgy WDP setup
constant c_err_clock_cycle_iteration_timeout : natural := 8; -- depends on srate calling error -- GENERIC
constant c_err_clock_cycle_it_timeout_rdp : natural := 9;
constant c_err_clock_cycle_it_timeout_rdv : natural := 10;
constant c_err_clock_cycle_it_timeout_poa : natural := 11;
constant c_err_pll_ack_timeout : natural := 13;
constant c_err_WindowProc_multiple_rsc_windows : natural := 16;
constant c_err_WindowProc_window_det_no_ones : natural := 17;
constant c_err_WindowProc_window_det_no_zeros : natural := 18;
constant c_err_WindowProc_undefined : natural := 19; -- catch all
constant c_err_tracked_mmc_offset_overflow : natural := 20;
constant c_err_no_mimic_feedback : natural := 21;
constant c_err_ctrl_ack_timeout : natural := 32;
constant c_err_ctrl_done_timeout : natural := 33;
-- -----------------------------------------------------
-- PLL phase locations per device family
-- (unused but a limited set is maintained here for reference)
-- -----------------------------------------------------
constant c_pll_resync_phs_select_ciii : natural := 5;
constant c_pll_mimic_phs_select_ciii : natural := 4;
constant c_pll_resync_phs_select_siii : natural := 5;
constant c_pll_mimic_phs_select_siii : natural := 7;
-- -----------------------------------------------------
-- Maximum sizing constraints
-- -----------------------------------------------------
constant C_MAX_NUM_PLL_RSC_PHASES : natural := 32;
-- -----------------------------------------------------
-- IO control Params
-- -----------------------------------------------------
constant c_set_oct_to_rs : std_logic := '0';
constant c_set_oct_to_rt : std_logic := '1';
constant c_set_odt_rt : std_logic := '1';
constant c_set_odt_off : std_logic := '0';
--
end ddr2_phy_alt_mem_phy_constants_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : record package for the non-levelling AFI sequencer
-- The record package (alt_mem_phy_record_pkg) is used to combine
-- command and status signals (into records) to be passed between
-- sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr2_phy_alt_mem_phy_record_pkg is
-- set some maximum constraints to bound natural numbers below
constant c_max_num_dqs_groups : natural := 24;
constant c_max_num_pins : natural := 8;
constant c_max_ranks : natural := 16;
constant c_max_pll_steps : natural := 80;
-- a prefix for all report signals to identify phy and sequencer block
--
constant record_report_prefix : string := "ddr2_phy_alt_mem_phy_record_pkg : ";
type t_family is (
cyclone3,
stratix2,
stratix3
);
-- -----------------------------------------------------------------------
-- the following are required for the non-levelling AFI PHY sequencer block interfaces
-- -----------------------------------------------------------------------
-- admin mode register settings (from mmi block)
type t_admin_ctrl is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
end record;
function defaults return t_admin_ctrl;
-- current admin status
type t_admin_stat is record
mr0 : std_logic_vector(12 downto 0);
mr1 : std_logic_vector(12 downto 0);
mr2 : std_logic_vector(12 downto 0);
mr3 : std_logic_vector(12 downto 0);
init_done : std_logic;
end record;
function defaults return t_admin_stat;
-- mmi to iram ctrl signals
type t_iram_ctrl is record
addr : natural range 0 to 1023;
wdata : std_logic_vector(31 downto 0);
write : std_logic;
read : std_logic;
end record;
function defaults return t_iram_ctrl;
-- broadcast iram status to mmi and dgrb
type t_iram_stat is record
rdata : std_logic_vector(31 downto 0);
done : std_logic;
err : std_logic;
err_code : std_logic_vector(3 downto 0);
init_done : std_logic;
out_of_mem : std_logic;
contested_access : std_logic;
end record;
function defaults return t_iram_stat;
-- codvw status signals from dgrb to mmi block
type t_dgrb_mmi is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record;
function defaults return t_dgrb_mmi;
-- signal to id which block is active
type t_ctrl_active_block is (
idle,
admin,
dgwb,
dgrb,
proc, -- unused in non-levelling AFI sequencer
setup, -- unused in non-levelling AFI sequencer
iram
);
function ret_proc return t_ctrl_active_block;
function ret_dgrb return t_ctrl_active_block;
-- control record for dgwb, dgrb, iram and admin blocks:
-- the possible commands
type t_ctrl_cmd_id is (
cmd_idle,
-- initialisation stages
cmd_phy_initialise,
cmd_init_dram,
cmd_prog_cal_mr,
cmd_write_ihi,
-- calibration stages
cmd_write_btp,
cmd_write_mtp,
cmd_read_mtp,
cmd_rrp_reset,
cmd_rrp_sweep,
cmd_rrp_seek,
cmd_rdv,
cmd_poa,
cmd_was,
-- advertise controller settings and re-configure for customer operation mode.
cmd_prep_adv_rd_lat,
cmd_prep_adv_wr_lat,
cmd_prep_customer_mr_setup,
cmd_tr_due
);
-- which block should execute each command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block;
-- specify command operands as a record
type t_command_op is record
current_cs : natural range 0 to c_max_ranks-1; -- which chip select is being calibrated
single_bit : std_logic; -- current operation should be single bit
mtp_almt : natural range 0 to 1; -- signals mtp alignment to be used for operation
end record;
function defaults return t_command_op;
-- command request record (sent to each block)
type t_ctrl_command is record
command : t_ctrl_cmd_id;
command_op : t_command_op;
command_req : std_logic;
end record;
function defaults return t_ctrl_command;
-- a generic status record for each block
type t_ctrl_stat is record
command_ack : std_logic;
command_done : std_logic;
command_result : std_logic_vector(7 downto 0 );
command_err : std_logic;
end record;
function defaults return t_ctrl_stat;
-- push interface for dgwb / dgrb blocks (only the dgrb uses this interface at present)
type t_iram_push is record
iram_done : std_logic;
iram_write : std_logic;
iram_wordnum : natural range 0 to 511; -- acts as an offset to current location (max = 80 pll steps *2 sweeps and 80 pins)
iram_bitnum : natural range 0 to 31; -- for bitwise packing modes
iram_pushdata : std_logic_vector(31 downto 0); -- only bit zero used for bitwise packing_mode
end record;
function defaults return t_iram_push;
-- control block "master" state machine
type t_master_sm_state is
(
s_reset,
s_phy_initialise, -- wait for dll lock and init done flag from iram
s_init_dram, -- dram initialisation - reset sequence
s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
s_write_ihi, -- write header information in iRAM
s_cal, -- check if calibration to be executed
s_write_btp, -- write burst training pattern
s_write_mtp, -- write more training pattern
s_read_mtp, -- read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
s_rrp_reset, -- read resync phase setup - reset initial conditions
s_rrp_sweep, -- read resync phase setup - sweep phases per chip select
s_rrp_seek, -- read resync phase setup - seek correct phase
s_rdv, -- read data valid setup
s_was, -- write datapath setup (ac to write data timing)
s_adv_rd_lat, -- advertise read latency
s_adv_wr_lat, -- advertise write latency
s_poa, -- calibrate the postamble (dqs based capture only)
s_tracking_setup, -- perform tracking (1st pass to setup mimic window)
s_prep_customer_mr_setup, -- apply user mode register settings (in admin block)
s_tracking, -- perform tracking (subsequent passes in user mode)
s_operational, -- calibration successful and in user mode
s_non_operational -- calibration unsuccessful and in user mode
);
-- record (set in mmi block) to disable calibration states
type t_hl_css_reg is record
phy_initialise_dis : std_logic;
init_dram_dis : std_logic;
write_ihi_dis : std_logic;
cal_dis : std_logic;
write_btp_dis : std_logic;
write_mtp_dis : std_logic;
read_mtp_dis : std_logic;
rrp_reset_dis : std_logic;
rrp_sweep_dis : std_logic;
rrp_seek_dis : std_logic;
rdv_dis : std_logic;
poa_dis : std_logic;
was_dis : std_logic;
adv_rd_lat_dis : std_logic;
adv_wr_lat_dis : std_logic;
prep_customer_mr_setup_dis : std_logic;
tracking_dis : std_logic;
end record;
function defaults return t_hl_css_reg;
-- record (set in ctrl block) to identify when a command has been acknowledged
type t_cal_stage_ack_seen is record
cal : std_logic;
phy_initialise : std_logic;
init_dram : std_logic;
write_ihi : std_logic;
write_btp : std_logic;
write_mtp : std_logic;
read_mtp : std_logic;
rrp_reset : std_logic;
rrp_sweep : std_logic;
rrp_seek : std_logic;
rdv : std_logic;
poa : std_logic;
was : std_logic;
adv_rd_lat : std_logic;
adv_wr_lat : std_logic;
prep_customer_mr_setup : std_logic;
tracking_setup : std_logic;
end record;
function defaults return t_cal_stage_ack_seen;
-- ctrl to mmi block interface (calibration status)
type t_ctrl_mmi is record
master_state_r : t_master_sm_state;
ctrl_calibration_success : std_logic;
ctrl_calibration_fail : std_logic;
ctrl_current_stage_done : std_logic;
ctrl_current_stage : t_ctrl_cmd_id;
ctrl_current_active_block : t_ctrl_active_block;
ctrl_cal_stage_ack_seen : t_cal_stage_ack_seen;
ctrl_err_code : std_logic_vector(7 downto 0);
end record;
function defaults return t_ctrl_mmi;
-- mmi to ctrl block interface (calibration control signals)
type t_mmi_ctrl is record
hl_css : t_hl_css_reg;
calibration_start : std_logic;
tracking_period_ms : natural range 0 to 255;
tracking_orvd_to_10ms : std_logic;
end record;
function defaults return t_mmi_ctrl;
-- algorithm parameterisation (generated in mmi block)
type t_algm_paramaterisation is record
num_phases_per_tck_pll : natural range 1 to c_max_pll_steps;
nominal_dqs_delay : natural range 0 to 4;
pll_360_sweeps : natural range 0 to 15;
nominal_poa_phase_lead : natural range 0 to 7;
maximum_poa_delay : natural range 0 to 15;
odt_enabled : boolean;
extend_octrt_by : natural range 0 to 15;
delay_octrt_by : natural range 0 to 15;
tracking_period_ms : natural range 0 to 255;
end record;
-- interface between mmi and pll to control phase shifting
type t_mmi_pll_reconfig is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
end record;
type t_pll_mmi is record
pll_busy : std_logic;
err : std_logic_vector(1 downto 0);
end record;
-- specify the iram configuration this is default
-- currently always dq_bitwise packing and a write mode of overwrite_ram
type t_iram_packing_mode is (
dq_bitwise,
dq_wordwise
);
type t_iram_write_mode is (
overwrite_ram,
or_into_ram,
and_into_ram
);
type t_ctrl_iram is record
packing_mode : t_iram_packing_mode;
write_mode : t_iram_write_mode;
active_block : t_ctrl_active_block;
end record;
function defaults return t_ctrl_iram;
-- -----------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFI PHY sequencer
-- -----------------------------------------------------------------------
type t_sc_ctrl_if is record
read : std_logic;
write : std_logic;
dqs_group_sel : std_logic_vector( 4 downto 0);
sc_in_group_sel : std_logic_vector( 5 downto 0);
wdata : std_logic_vector(45 downto 0);
op_type : std_logic_vector( 1 downto 0);
end record;
function defaults return t_sc_ctrl_if;
type t_sc_stat is record
rdata : std_logic_vector(45 downto 0);
busy : std_logic;
error_det : std_logic;
err_code : std_logic_vector(1 downto 0);
sc_cap : std_logic_vector(7 downto 0);
end record;
function defaults return t_sc_stat;
type t_element_to_reconfigure is (
pp_t9,
pp_t10,
pp_t1,
dqslb_rsc_phs,
dqslb_poa_phs_ofst,
dqslb_dqs_phs,
dqslb_dq_phs_ofst,
dqslb_dq_1t,
dqslb_dqs_1t,
dqslb_rsc_1t,
dqslb_div2_phs,
dqslb_oct_t9,
dqslb_oct_t10,
dqslb_poa_t7,
dqslb_poa_t11,
dqslb_dqs_dly,
dqslb_lvlng_byps
);
type t_sc_type is (
DQS_LB,
DQS_DQ_DM_PINS,
DQ_DM_PINS,
dqs_dqsn_pins,
dq_pin,
dqs_pin,
dm_pin,
dq_pins
);
type t_sc_int_ctrl is record
group_num : natural range 0 to c_max_num_dqs_groups;
group_type : t_sc_type;
pin_num : natural range 0 to c_max_num_pins;
sc_element : t_element_to_reconfigure;
prog_val : std_logic_vector(3 downto 0);
ram_set : std_logic;
sc_update : std_logic;
end record;
function defaults return t_sc_int_ctrl;
-- -----------------------------------------------------------------------
-- record and functions for instant on mode
-- -----------------------------------------------------------------------
-- ranges on the below are not important because this logic is not synthesised
type t_preset_cal is record
codvw_phase : natural range 0 to 2*c_max_pll_steps;-- rsc phase
codvw_size : natural range 0 to c_max_pll_steps; -- rsc size (unused but reported)
rlat : natural; -- advertised read latency ctl_rlat (in phy clock cycles)
rdv_lat : natural; -- read data valid latency decrements needed (in memory clock cycles)
wlat : natural; -- advertised write latency ctl_wlat (in phy clock cycles)
ac_1t : std_logic; -- address / command 1t delay setting (HR only)
poa_lat : natural; -- poa latency decrements needed (in memory clock cycles)
end record;
-- the below are hardcoded (do not change)
constant c_ddr_default_cl : natural := 3;
constant c_ddr2_default_cl : natural := 6;
constant c_ddr3_default_cl : natural := 6;
constant c_ddr2_default_cwl : natural := 5;
constant c_ddr3_default_cwl : natural := 5;
constant c_ddr2_default_al : natural := 0;
constant c_ddr3_default_al : natural := 0;
constant c_ddr_default_rl : integer := c_ddr_default_cl;
constant c_ddr2_default_rl : integer := c_ddr2_default_cl + c_ddr2_default_al;
constant c_ddr3_default_rl : integer := c_ddr3_default_cl + c_ddr3_default_al;
constant c_ddr_default_wl : integer := 1;
constant c_ddr2_default_wl : integer := c_ddr2_default_cwl + c_ddr2_default_al;
constant c_ddr3_default_wl : integer := c_ddr3_default_cwl + c_ddr3_default_al;
function defaults return t_preset_cal;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal;
--
end ddr2_phy_alt_mem_phy_record_pkg;
--
package body ddr2_phy_alt_mem_phy_record_pkg IS
-- -----------------------------------------------------------------------
-- function implementations for the above declarations
-- these are mainly default conditions for records
-- -----------------------------------------------------------------------
function defaults return t_admin_ctrl is
variable output : t_admin_ctrl;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_admin_stat is
variable output : t_admin_stat;
begin
output.mr0 := (others => '0');
output.mr1 := (others => '0');
output.mr2 := (others => '0');
output.mr3 := (others => '0');
return output;
end function;
function defaults return t_iram_ctrl is
variable output : t_iram_ctrl;
begin
output.addr := 0;
output.wdata := (others => '0');
output.write := '0';
output.read := '0';
return output;
end function;
function defaults return t_iram_stat is
variable output : t_iram_stat;
begin
output.rdata := (others => '0');
output.done := '0';
output.err := '0';
output.err_code := (others => '0');
output.init_done := '0';
output.out_of_mem := '0';
output.contested_access := '0';
return output;
end function;
function defaults return t_dgrb_mmi is
variable output : t_dgrb_mmi;
begin
output.cal_codvw_phase := (others => '0');
output.cal_codvw_size := (others => '0');
output.codvw_trk_shift := (others => '0');
output.codvw_grt_one_dvw := '0';
return output;
end function;
function ret_proc return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := proc;
return output;
end function;
function ret_dgrb return t_ctrl_active_block is
variable output : t_ctrl_active_block;
begin
output := dgrb;
return output;
end function;
function defaults return t_ctrl_iram is
variable output : t_ctrl_iram;
begin
output.packing_mode := dq_bitwise;
output.write_mode := overwrite_ram;
output.active_block := idle;
return output;
end function;
function defaults return t_command_op is
variable output : t_command_op;
begin
output.current_cs := 0;
output.single_bit := '0';
output.mtp_almt := 0;
return output;
end function;
function defaults return t_ctrl_command is
variable output : t_ctrl_command;
begin
output.command := cmd_idle;
output.command_req := '0';
output.command_op := defaults;
return output;
end function;
-- decode which block is associated with which command
function curr_active_block (
ctrl_cmd_id : t_ctrl_cmd_id
) return t_ctrl_active_block is
begin
case ctrl_cmd_id is
when cmd_idle => return idle;
when cmd_phy_initialise => return idle;
when cmd_init_dram => return admin;
when cmd_prog_cal_mr => return admin;
when cmd_write_ihi => return iram;
when cmd_write_btp => return dgwb;
when cmd_write_mtp => return dgwb;
when cmd_read_mtp => return dgrb;
when cmd_rrp_reset => return dgrb;
when cmd_rrp_sweep => return dgrb;
when cmd_rrp_seek => return dgrb;
when cmd_rdv => return dgrb;
when cmd_poa => return dgrb;
when cmd_was => return dgwb;
when cmd_prep_adv_rd_lat => return dgrb;
when cmd_prep_adv_wr_lat => return dgrb;
when cmd_prep_customer_mr_setup => return admin;
when cmd_tr_due => return dgrb;
when others => return idle;
end case;
end function;
function defaults return t_ctrl_stat is
variable output : t_ctrl_stat;
begin
output.command_ack := '0';
output.command_done := '0';
output.command_err := '0';
output.command_result := (others => '0');
return output;
end function;
function defaults return t_iram_push is
variable output : t_iram_push;
begin
output.iram_done := '0';
output.iram_write := '0';
output.iram_wordnum := 0;
output.iram_bitnum := 0;
output.iram_pushdata := (others => '0');
return output;
end function;
function defaults return t_hl_css_reg is
variable output : t_hl_css_reg;
begin
output.phy_initialise_dis := '0';
output.init_dram_dis := '0';
output.write_ihi_dis := '0';
output.cal_dis := '0';
output.write_btp_dis := '0';
output.write_mtp_dis := '0';
output.read_mtp_dis := '0';
output.rrp_reset_dis := '0';
output.rrp_sweep_dis := '0';
output.rrp_seek_dis := '0';
output.rdv_dis := '0';
output.poa_dis := '0';
output.was_dis := '0';
output.adv_rd_lat_dis := '0';
output.adv_wr_lat_dis := '0';
output.prep_customer_mr_setup_dis := '0';
output.tracking_dis := '0';
return output;
end function;
function defaults return t_cal_stage_ack_seen is
variable output : t_cal_stage_ack_seen;
begin
output.cal := '0';
output.phy_initialise := '0';
output.init_dram := '0';
output.write_ihi := '0';
output.write_btp := '0';
output.write_mtp := '0';
output.read_mtp := '0';
output.rrp_reset := '0';
output.rrp_sweep := '0';
output.rrp_seek := '0';
output.rdv := '0';
output.poa := '0';
output.was := '0';
output.adv_rd_lat := '0';
output.adv_wr_lat := '0';
output.prep_customer_mr_setup := '0';
output.tracking_setup := '0';
return output;
end function;
function defaults return t_mmi_ctrl is
variable output : t_mmi_ctrl;
begin
output.hl_css := defaults;
output.calibration_start := '0';
output.tracking_period_ms := 0;
output.tracking_orvd_to_10ms := '0';
return output;
end function;
function defaults return t_ctrl_mmi is
variable output : t_ctrl_mmi;
begin
output.master_state_r := s_reset;
output.ctrl_calibration_success := '0';
output.ctrl_calibration_fail := '0';
output.ctrl_current_stage_done := '0';
output.ctrl_current_stage := cmd_idle;
output.ctrl_current_active_block := idle;
output.ctrl_cal_stage_ack_seen := defaults;
output.ctrl_err_code := (others => '0');
return output;
end function;
-------------------------------------------------------------------------
-- the following are required for compliance to levelling AFI PHY interface but
-- are non-functional for non-levelling AFi PHY sequencer
-------------------------------------------------------------------------
function defaults return t_sc_ctrl_if is
variable output : t_sc_ctrl_if;
begin
output.read := '0';
output.write := '0';
output.dqs_group_sel := (others => '0');
output.sc_in_group_sel := (others => '0');
output.wdata := (others => '0');
output.op_type := (others => '0');
return output;
end function;
function defaults return t_sc_stat is
variable output : t_sc_stat;
begin
output.rdata := (others => '0');
output.busy := '0';
output.error_det := '0';
output.err_code := (others => '0');
output.sc_cap := (others => '0');
return output;
end function;
function defaults return t_sc_int_ctrl is
variable output : t_sc_int_ctrl;
begin
output.group_num := 0;
output.group_type := DQ_PIN;
output.pin_num := 0;
output.sc_element := pp_t9;
output.prog_val := (others => '0');
output.ram_set := '0';
output.sc_update := '0';
return output;
end function;
-- -----------------------------------------------------------------------
-- functions for instant on mode
--
--
-- Guide on how to use:
--
-- The following factors effect the setup of the PHY:
-- - AC Phase - phase at which address/command signals launched wrt PHY clock
-- - this effects the read/write latency
-- - MR settings - CL, CWL, AL
-- - Data rate - HR or FR (DDR/DDR2 only)
-- - Family - datapaths are subtly different for each
-- - Memory type - DDR/DDR2/DDR3 (different latency behaviour - see specs)
--
-- Instant on mode is designed to work for the following subset of the
-- above factors:
-- - AC Phase - out of the box defaults, which is 240 degrees for SIII type
-- families (includes SIV, HCIII, HCIV), else 90 degrees
-- - MR Settings - DDR - CL 3 only
-- - DDR2 - CL 3,4,5,6, AL 0
-- - DDR3 - CL 5,6 CWL 5, AL 0
-- - Data rate - All
-- - Families - All
-- - Memory type - All
--
-- Hints on bespoke setup for parameters outside the above or if the
-- datapath is modified (only for VHDL sim mode):
--
-- Step 1 - Run simulation with REDUCE_SIM_TIME mode 2 (FAST)
--
-- Step 2 - From the output log find the following text:
-- # -----------------------------------------------------------------------
-- **** ALTMEMPHY CALIBRATION has completed ****
-- Status:
-- calibration has : PASSED
-- PHY read latency (ctl_rlat) is : 14
-- address/command to PHY write latency (ctl_wlat) is : 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32
-- calibrated centre of data valid window size : 24
-- chosen address and command 1T delay: no 1T delay
-- poa 'dec' adjustments = 27
-- rdv 'dec' adjustments = 25
-- # -----------------------------------------------------------------------
--
-- Step 3 - Convert the text to bespoke instant on settings at the end of the
-- setup_instant_on function using the
-- override_instant_on function, note type is t_preset_cal
--
-- The mapping is as follows:
--
-- PHY read latency (ctl_rlat) is : 14 => rlat := 14
-- address/command to PHY write latency (ctl_wlat) is : 2 => wlat := 2
-- read resynch phase calibration report:
-- calibrated centre of data valid window phase : 32 => codvw_phase := 32
-- calibrated centre of data valid window size : 24 => codvw_size := 24
-- chosen address and command 1T delay: no 1T delay => ac_1t := '0'
-- poa 'dec' adjustments = 27 => poa_lat := 27
-- rdv 'dec' adjustments = 25 => rdv_lat := 25
--
-- Step 4 - Try running in REDUCE_SIM_TIME mode 1 (SUPERFAST mode)
--
-- Step 5 - If still fails observe the behaviour of the controller, for the
-- following symptoms:
-- - If first 2 beats of read data lost (POA enable too late) - inc poa_lat by 1 (poa_lat is number of POA decrements not actual latency)
-- - If last 2 beats of read data lost (POA enable too early) - dec poa_lat by 1
-- - If ctl_rdata_valid misaligned to ctl_rdata then alter number of RDV adjustments (rdv_lat)
-- - If write data is not 4-beat aligned (when written into memory) toggle ac_1t (HR only)
-- - If read data is not 4-beat aligned (but write data is) add 360 degrees to phase (PLL_STEPS_PER_CYCLE) mod 2*PLL_STEPS_PER_CYCLE (HR only)
--
-- Step 6 - If the above fails revert to REDUCE_SIM_TIME = 2 (FAST) mode
--
-- --------------------------------------------------------------------------
-- defaults
function defaults return t_preset_cal is
variable output : t_preset_cal;
begin
output.codvw_phase := 0;
output.codvw_size := 0;
output.wlat := 0;
output.rlat := 0;
output.rdv_lat := 0;
output.ac_1t := '1'; -- default on for FR
output.poa_lat := 0;
return output;
end function;
-- Functions to extract values from MR
-- return cl (for DDR memory 2*cl because of 1/2 cycle latencies)
procedure mr0_to_cl (memory_type : string;
mr0 : std_logic_vector(15 downto 0);
cl : out natural;
half_cl : out std_logic) is
variable v_cl : natural;
begin
half_cl := '0';
if memory_type = "DDR" then -- DDR memories
-- returns cl*2 because of 1/2 latencies
v_cl := to_integer(unsigned(mr0(5 downto 4)));
-- integer values of cl
if mr0(6) = '0' then
assert v_cl > 1 report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
end if;
if mr0(6) = '1' then
assert (v_cl = 1 or v_cl = 2) report record_report_prefix & "invalid cas latency for DDR memory, should be in range 1.5-3" severity failure;
half_cl := '1';
end if;
elsif memory_type = "DDR2" then -- DDR2 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)));
-- sanity checks
assert (v_cl > 1 and v_cl < 7) report record_report_prefix & "invalid cas latency for DDR2 memory, should be in range 2-6 but equals " & integer'image(v_cl) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
v_cl := to_integer(unsigned(mr0(6 downto 4)))+4;
--sanity checks
assert mr0(2) = '0' report record_report_prefix & "invalid cas latency for DDR3 memory, bit a2 in mr0 is set" severity failure;
assert v_cl /= 4 report record_report_prefix & "invalid cas latency for DDR3 memory, bits a6:4 set to zero" severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
cl := v_cl;
end procedure;
function mr1_to_al (memory_type : string;
mr1 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable al : natural;
begin
if memory_type = "DDR" then -- DDR memories
-- unsupported so return zero
al := 0;
elsif memory_type = "DDR2" then -- DDR2 memories
al := to_integer(unsigned(mr1(5 downto 3)));
assert al < 6 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
elsif memory_type = "DDR3" then -- DDR3 memories
al := to_integer(unsigned(mr1(4 downto 3)));
assert al /= 3 report record_report_prefix & "invalid additive latency for DDR2 memory, should be in range 0-5 but equals " & integer'image(al) severity failure;
if al /= 0 then -- CL-1 or CL-2
al := cl - al;
end if;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return al;
end function;
-- return cwl
function mr2_to_cwl (memory_type : string;
mr2 : std_logic_vector(15 downto 0);
cl : natural) return natural is
variable cwl : natural;
begin
if memory_type = "DDR" then -- DDR memories
cwl := 1;
elsif memory_type = "DDR2" then -- DDR2 memories
cwl := cl - 1;
elsif memory_type = "DDR3" then -- DDR3 memories
cwl := to_integer(unsigned(mr2(5 downto 3))) + 5;
--sanity checks
assert cwl < 9 report record_report_prefix & "invalid cas write latency for DDR3 memory, should be in range 5-8 but equals " & integer'image(cwl) severity failure;
else
report record_report_prefix & "Undefined memory type " & memory_type severity failure;
end if;
return cwl;
end function;
-- -----------------------------------
-- Functions to determine which family group
-- Include any family alias here
-- -----------------------------------
function is_siii(family_id : natural) return boolean is
begin
if family_id = 3 or family_id = 5 then
return true;
else
return false;
end if;
end function;
function is_ciii(family_id : natural) return boolean is
begin
if family_id = 2 then
return true;
else
return false;
end if;
end function;
function is_aii(family_id : natural) return boolean is
begin
if family_id = 4 then
return true;
else
return false;
end if;
end function;
function is_sii(family_id : natural) return boolean is
begin
if family_id = 1 then
return true;
else
return false;
end if;
end function;
-- -----------------------------------
-- Functions to lookup hardcoded values
-- on per family basis
-- DDR: CL = 3
-- DDR2: CL = 6, CWL = 5, AL = 0
-- DDR3: CL = 6, CWL = 5, AL = 0
-- -----------------------------------
-- default ac phase = 240
function siii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural
) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 8;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 16;
v_output.rdv_lat := 21;
v_output.ac_1t := '0';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 2;
v_output.rlat := 15;
v_output.rdv_lat := 23;
v_output.ac_1t := '0';
v_output.poa_lat := 24;
end if;
-- adapt settings for ac_phase (default 240 degrees so leave commented)
-- if dwidth_ratio = 2 then
-- v_output.wlat := v_output.wlat - 1;
-- v_output.rlat := v_output.rlat - 1;
-- v_output.rdv_lat := v_output.rdv_lat + 1;
-- v_output.poa_lat := v_output.poa_lat + 1;
-- else
-- v_output.ac_1t := not v_output.ac_1t;
-- end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function ciii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 11; --unused
else
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 27; --unused
end if;
elsif memory_type = "DDR2" then -- CAS = 6
if dwidth_ratio = 2 then
v_output.codvw_phase := 3*pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 8; --unused
else
v_output.codvw_phase := pll_steps + 3*pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 25; --unused
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps/2;
return v_output;
end function;
-- default ac phase = 90
function sii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 15;
v_output.rdv_lat := 11;
v_output.poa_lat := 13;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 18;
v_output.rdv_lat := 8;
v_output.poa_lat := 10;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 20;
end if;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
-- default ac phase = 90
function aii_family_settings (dwidth_ratio : integer;
memory_type : string;
pll_steps : natural) return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
if memory_type = "DDR" then -- CAS = 3
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 16;
v_output.rdv_lat := 10;
v_output.poa_lat := 15;
else
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 1;
v_output.rlat := 13;
v_output.rdv_lat := 27;
v_output.ac_1t := '1';
v_output.poa_lat := 24;
end if;
elsif memory_type = "DDR2" then
if dwidth_ratio = 2 then
v_output.codvw_phase := pll_steps/4;
v_output.wlat := 5;
v_output.rlat := 19;
v_output.rdv_lat := 7;
v_output.poa_lat := 12;
else
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
elsif memory_type = "DDR3" then -- HR only, CAS = 6
v_output.codvw_phase := pll_steps + pll_steps/4;
v_output.wlat := 3;
v_output.rlat := 14;
v_output.rdv_lat := 25;
v_output.ac_1t := '1';
v_output.poa_lat := 22;
end if;
-- adapt settings for ac_phase (hardcode for 90 degrees)
if dwidth_ratio = 2 then
v_output.wlat := v_output.wlat + 1;
v_output.rlat := v_output.rlat + 1;
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.ac_1t := not v_output.ac_1t;
end if;
v_output.codvw_size := pll_steps;
return v_output;
end function;
function is_odd(num : integer) return boolean is
variable v_num : integer;
begin
v_num := num;
if v_num - (v_num/2)*2 = 0 then
return false;
else
return true;
end if;
end function;
------------------------------------------------
-- top level function to setup instant on mode
------------------------------------------------
function override_instant_on return t_preset_cal is
variable v_output : t_preset_cal;
begin
v_output := defaults;
-- add in overrides here
return v_output;
end function;
function setup_instant_on (sim_time_red : natural;
family_id : natural;
memory_type : string;
dwidth_ratio : natural;
pll_steps : natural;
mr0 : std_logic_vector(15 downto 0);
mr1 : std_logic_vector(15 downto 0);
mr2 : std_logic_vector(15 downto 0)) return t_preset_cal is
variable v_output : t_preset_cal;
variable v_cl : natural; -- cas latency
variable v_half_cl : std_logic; -- + 0.5 cycles (DDR only)
variable v_al : natural; -- additive latency (ddr2/ddr3 only)
variable v_cwl : natural; -- cas write latency (ddr3 only)
variable v_rl : integer range 0 to 15;
variable v_wl : integer;
variable v_delta_rl : integer range -10 to 10; -- from given defaults
variable v_delta_wl : integer; -- from given defaults
variable v_debug : boolean;
begin
v_debug := true;
v_output := defaults;
if sim_time_red = 1 then -- only set if STR equals 1
-- ----------------------------------------
-- extract required parameters from MRs
-- ----------------------------------------
mr0_to_cl(memory_type, mr0, v_cl, v_half_cl);
v_al := mr1_to_al(memory_type, mr1, v_cl);
v_cwl := mr2_to_cwl(memory_type, mr2, v_cl);
v_rl := v_cl + v_al;
v_wl := v_cwl + v_al;
if v_debug then
report record_report_prefix & "Extracted MR parameters" & LF &
"CAS = " & integer'image(v_cl) & LF &
"CWL = " & integer'image(v_cwl) & LF &
"AL = " & integer'image(v_al) & LF;
end if;
-- ----------------------------------------
-- apply per family, memory type and dwidth_ratio static setup
-- ----------------------------------------
if is_siii(family_id) then
v_output := siii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_ciii(family_id) then
v_output := ciii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_aii(family_id) then
v_output := aii_family_settings(dwidth_ratio, memory_type, pll_steps);
elsif is_sii(family_id) then
v_output := sii_family_settings(dwidth_ratio, memory_type, pll_steps);
end if;
-- ----------------------------------------
-- correct for different cwl, cl and al settings
-- ----------------------------------------
if memory_type = "DDR" then
v_delta_rl := v_rl - c_ddr_default_rl;
v_delta_wl := v_wl - c_ddr_default_wl;
elsif memory_type = "DDR2" then
v_delta_rl := v_rl - c_ddr2_default_rl;
v_delta_wl := v_wl - c_ddr2_default_wl;
else -- DDR3
v_delta_rl := v_rl - c_ddr3_default_rl;
v_delta_wl := v_wl - c_ddr3_default_wl;
end if;
if v_debug then
report record_report_prefix & "Extracted memory latency (and delta from default)" & LF &
"RL = " & integer'image(v_rl) & LF &
"WL = " & integer'image(v_wl) & LF &
"delta RL = " & integer'image(v_delta_rl) & LF &
"delta WL = " & integer'image(v_delta_wl) & LF;
end if;
if dwidth_ratio = 2 then
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl;
elsif dwidth_ratio = 4 then
-- adjust wdp settings
v_output.wlat := v_output.wlat + v_delta_wl/2;
if is_odd(v_delta_wl) then -- add / sub 1t write latency
-- toggle ac_1t in all cases
v_output.ac_1t := not v_output.ac_1t;
if v_delta_wl < 0 then -- sub 1 from latency
if v_output.ac_1t = '0' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat - 1;
end if;
else -- add 1 to latency
if v_output.ac_1t = '1' then -- phy_clk cc boundary
v_output.wlat := v_output.wlat + 1;
end if;
end if;
-- update read latency
if v_output.ac_1t = '1' then -- added 1t to address/command so inc read_lat
v_delta_rl := v_delta_rl + 1;
else -- subtracted 1t from address/command so dec read_lat
v_delta_rl := v_delta_rl - 1;
end if;
end if;
-- adjust rdp settings
v_output.rlat := v_output.rlat + v_delta_rl/2;
v_output.rdv_lat := v_output.rdv_lat - v_delta_rl;
v_output.poa_lat := v_output.poa_lat - v_delta_rl;
if memory_type = "DDR3" then
if is_odd(v_delta_rl) xor is_odd(v_delta_wl) then
if is_aii(family_id) then
v_output.rdv_lat := v_output.rdv_lat - 1;
v_output.poa_lat := v_output.poa_lat - 1;
else
v_output.rdv_lat := v_output.rdv_lat + 1;
v_output.poa_lat := v_output.poa_lat + 1;
end if;
end if;
end if;
if is_odd(v_delta_rl) then
if v_delta_rl > 0 then -- add 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
v_output.rlat := v_output.rlat + 1;
end if;
else -- subtract 1t
if v_output.codvw_phase < pll_steps then
v_output.codvw_phase := v_output.codvw_phase + pll_steps;
v_output.rlat := v_output.rlat - 1;
else
v_output.codvw_phase := v_output.codvw_phase - pll_steps;
end if;
end if;
end if;
end if;
if v_half_cl = '1' and is_ciii(family_id) then
v_output.codvw_phase := v_output.codvw_phase - pll_steps/2;
end if;
end if;
return v_output;
end function;
--
END ddr2_phy_alt_mem_phy_record_pkg;
--/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
-- use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any
-- output files any of the foregoing (including device programming or
-- simulation files), and any associated documentation or information are
-- expressly subject to the terms and conditions of the Altera Program
-- License Subscription Agreement or other applicable license agreement,
-- including, without limitation, that your use is for the sole purpose
-- of programming logic devices manufactured by Altera and sold by Altera
-- or its authorized distributors. Please refer to the applicable
-- agreement for further details. */
--
-- -----------------------------------------------------------------------------
-- Abstract : address and command package, shared between all variations of
-- the AFI sequencer
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is
-- used to combine DRAM address and command signals in one record
-- and unify the functions operating on this record.
--
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr2_phy_alt_mem_phy_addr_cmd_pkg is
-- the following are bounds on the maximum range of address and command signals
constant c_max_addr_bits : natural := 15;
constant c_max_ba_bits : natural := 3;
constant c_max_ranks : natural := 16;
constant c_max_mode_reg_bit : natural := 12;
constant c_max_cmds_per_clk : natural := 4; -- quarter rate
-- a prefix for all report signals to identify phy and sequencer block
--
constant ac_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (addr_cmd_pkg) : ";
-- -------------------------------------------------------------
-- this record represents a single mem_clk command cycle
-- -------------------------------------------------------------
type t_addr_cmd is record
addr : natural range 0 to 2**c_max_addr_bits - 1;
ba : natural range 0 to 2**c_max_ba_bits - 1;
cas_n : boolean;
ras_n : boolean;
we_n : boolean;
cke : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
cs_n : natural range 2**c_max_ranks - 1 downto 0; -- bounded max of 8 ranks
odt : natural range 0 to 2**c_max_ranks - 1; -- bounded max of 8 ranks
rst_n : boolean;
end record t_addr_cmd;
-- -------------------------------------------------------------
-- this vector is used to describe the fact that for slower clock domains
-- mutiple commands per clock can be issued and encapsulates all these options in a
-- type which can scale with rate
-- -------------------------------------------------------------
type t_addr_cmd_vector is array (natural range <>) of t_addr_cmd;
-- -------------------------------------------------------------
-- this record is used to define the memory interface type and allow packing and checking
-- (it should be used as a generic to a entity or from a poject level constant)
-- -------------------------------------------------------------
-- enumeration for mem_type
type t_mem_type is
(
DDR,
DDR2,
DDR3
);
-- memory interface configuration parameters
type t_addr_cmd_config_rec is record
num_addr_bits : natural;
num_ba_bits : natural;
num_cs_bits : natural;
num_ranks : natural;
cmds_per_clk : natural range 1 to c_max_cmds_per_clk; -- commands per clock cycle (equal to DWIDTH_RATIO/2)
mem_type : t_mem_type;
end record;
-- -----------------------------------
-- the following type is used to switch between signals
-- (for example, in the mask function below)
-- -----------------------------------
type t_addr_cmd_signals is
(
addr,
ba,
cas_n,
ras_n,
we_n,
cke,
cs_n,
odt,
rst_n
);
-- -----------------------------------
-- odt record
-- to hold the odt settings
-- (an odt_record) per rank (in odt_array)
-- -----------------------------------
type t_odt_record is record
write : natural;
read : natural;
end record t_odt_record;
type t_odt_array is array (natural range <>) of t_odt_record;
-- -------------------------------------------------------------
-- exposed functions and procedures
--
-- these functions cover the following memory types:
-- DDR3, DDR2, DDR
--
-- and the following operations:
-- MRS, REF, PRE, PREA, ACT,
-- WR, WRS8, WRS4, WRA, WRAS8, WRAS4,
-- RD, RDS8, RDS4, RDA, RDAS8, RDAS4,
--
-- for DDR3 on the fly burst length setting for reads/writes
-- is supported
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function int_pup_reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector;
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector;
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector;
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector;
function refresh ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function self_refresh_entry ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector;
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector;
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector;
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector;
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: currently only supports DDR/DDR2 memories
-- -------------------------------------------------------------
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array;
-- -------------------------------------------------------------
-- the following function enables assignment to the constant config_rec
-- -------------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec;
-- -------------------------------------------------------------
-- the following function and procedure unpack address and
-- command signals from the t_addr_cmd_vector format
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector);
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector);
-- -------------------------------------------------------------
-- the following functions perform bit masking to 0 or 1 (as
-- specified by mask_value) to a chosen address/command signal (signal_name)
-- across all signal bits or to a selected bit (mask_bit)
-- -------------------------------------------------------------
-- mask all signal bits procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic) return t_addr_cmd_vector;
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic);
-- mask signal bit (mask_bit) procedure
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural) return t_addr_cmd_vector;
--
end ddr2_phy_alt_mem_phy_addr_cmd_pkg;
--
package body ddr2_phy_alt_mem_phy_addr_cmd_pkg IS
-- -------------------------------------------------------------
-- Basic functions for a single command
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := 0;
v_retval.ba := 0;
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (Same as default with cke and rst_n 0 )
-- -------------------------------------------------------------
function reset ( config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := defaults(config_rec);
v_retval.cke := 0;
if config_rec.mem_type = DDR3 then
v_retval.rst_n := true;
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues deselect (command) JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '1'; -- set AP bit high
v_retval.addr := to_integer(v_addr);
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - 1 - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned( c_max_addr_bits -1 downto 0);
begin
v_retval := previous;
v_addr := to_unsigned(previous.addr, c_max_addr_bits);
v_addr(10) := '0'; -- set AP bit low
v_retval.addr := to_integer(v_addr);
v_retval.ba := bank;
v_retval.ras_n := true;
v_retval.cas_n := false;
v_retval.we_n := true;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) - ranks;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits - 1;
row : in natural range 0 to 2**c_max_addr_bits - 1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.addr := row;
v_retval.ba := bank;
v_retval.cas_n := false;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := previous.odt;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports writes of burst length 4 or 8, the requested length was: " & integer'image(op_length) severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory writes" severity failure;
end if;
-- set a/c signal assignments for write
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := ranks;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks -1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr : unsigned(c_max_addr_bits-1 downto 0);
begin
-- calculate correct address signal
v_addr := to_unsigned(col, c_max_addr_bits);
-- note pin A10 is used for AP, therfore shift the value from A10 onto A11.
v_retval.addr := to_integer(v_addr(9 downto 0));
if v_addr(10) = '1' then
v_retval.addr := v_retval.addr + 2**11;
end if;
if auto_prech = true then -- set AP bit (A10)
v_retval.addr := v_retval.addr + 2**10;
end if;
if config_rec.mem_type = DDR3 then
if op_length = 8 then -- set BL_OTF sel bit (A12)
v_retval.addr := v_retval.addr + 2**12;
elsif op_length = 4 then
null;
else
report ac_report_prefix & "DDR3 DRAM only supports reads of burst length 4 or 8" severity failure;
end if;
elsif config_rec.mem_type = DDR2 or config_rec.mem_type = DDR then
null;
else
report ac_report_prefix & "only DDR memories are supported for memory reads" severity failure;
end if;
-- set a/c signals for read command
v_retval.ba := bank;
v_retval.cas_n := true;
v_retval.ras_n := false;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := false;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.rst_n := false;
-- addr, BA and ODT are don't care therfore leave as previous value
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_addr_remap : unsigned(c_max_mode_reg_bit downto 0);
begin
v_retval.cas_n := true;
v_retval.ras_n := true;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - ranks;
v_retval.odt := 0;
v_retval.rst_n := false;
v_retval.ba := mode_register_num;
v_retval.addr := to_integer(unsigned(mode_reg_value));
if remap_addr_and_ba = true then
v_addr_remap := unsigned(mode_reg_value);
v_addr_remap(8 downto 7) := v_addr_remap(7) & v_addr_remap(8);
v_addr_remap(6 downto 5) := v_addr_remap(5) & v_addr_remap(6);
v_addr_remap(4 downto 3) := v_addr_remap(3) & v_addr_remap(4);
v_retval.addr := to_integer(v_addr_remap);
v_addr_remap := to_unsigned(mode_register_num, c_max_mode_reg_bit + 1);
v_addr_remap(1 downto 0) := v_addr_remap(0) & v_addr_remap(1);
v_retval.ba := to_integer(v_addr_remap);
end if;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- -------------------------------------------------------------
function maintain_pd_or_sr (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd;
ranks : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval := previous;
v_retval.cke := (2 ** config_rec.num_ranks) - 1 - ranks;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCS (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 0; -- clear bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK at a time.
-- -------------------------------------------------------------
function ZQCL (config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
)
return t_addr_cmd
is
variable v_retval : t_addr_cmd;
begin
v_retval.cas_n := false;
v_retval.ras_n := false;
v_retval.we_n := true;
v_retval.cke := (2 ** config_rec.num_ranks) -1;
v_retval.cs_n := (2 ** config_rec.num_cs_bits) -1 - rank;
v_retval.rst_n := false;
v_retval.addr := 1024; -- set bit 10
v_retval.ba := 0;
v_retval.odt := 0;
return v_retval;
end function;
-- -------------------------------------------------------------
-- functions acting on all clock cycles from whatever rate
-- in halfrate clock domain issues 1 command per clock
-- in quarter rate issues 1 command per clock
-- In the above cases they will be correctly aligned using the
-- ALTMEMPHY 2T and 4T SDC
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- defaults the bus no JEDEC abbreviated name
-- -------------------------------------------------------------
function defaults (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => defaults(config_rec));
return v_retval;
end function;
-- -------------------------------------------------------------
-- resets the addr/cmd signal (same as default with cke 0)
-- -------------------------------------------------------------
function reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => reset(config_rec));
return v_retval;
end function;
function int_pup_reset (config_rec : in t_addr_cmd_config_rec
) return t_addr_cmd_vector
is
variable v_addr_cmd_config_rst : t_addr_cmd_config_rec;
begin
v_addr_cmd_config_rst := config_rec;
v_addr_cmd_config_rst.num_ranks := c_max_ranks;
return reset(v_addr_cmd_config_rst);
end function;
-- -------------------------------------------------------------
-- issues a deselect command JEDEC abbreviated name: DES
-- -------------------------------------------------------------
function deselect ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(a_previous'range);
begin
for rate in a_previous'range loop
v_retval(rate) := deselect(config_rec, a_previous(a_previous'high));
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a precharge all command JEDEC abbreviated name: PREA
-- -------------------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_all(config_rec, previous(a_previous'high), ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- precharge (close) a bank JEDEC abbreviated name: PRE
-- -------------------------------------------------------------
function precharge_bank ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1;
bank : in natural range 0 to 2**c_max_ba_bits -1
) return t_addr_cmd_vector
is
alias a_previous : t_addr_cmd_vector(previous'range) is previous;
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in a_previous'range loop
v_retval(rate) := precharge_bank(config_rec, previous(a_previous'high), ranks, bank);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a activate (open row) JEDEC abbreviated name: ACT
-- -------------------------------------------------------------
function activate ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
row : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := activate(config_rec, previous(previous'high), bank, row, ranks);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a write command JEDEC abbreviated name:WR, WRA
-- WRS4, WRAS4
-- WRS8, WRAS8
--
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL
-- Auto Precharge (AP)
-- -------------------------------------------------------------
function write ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := write(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a read command JEDEC abbreviated name: RD, RDA
-- RDS4, RDAS4
-- RDS8, RDAS8
-- has the ability to support:
-- DDR3:
-- BL4, BL8, fixed BL
-- Auto Precharge (AP)
-- DDR2, DDR:
-- fixed BL, Auto Precharge (AP)
-- -------------------------------------------------------------
function read ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
bank : in natural range 0 to 2**c_max_ba_bits -1;
col : in natural range 0 to 2**c_max_addr_bits -1;
ranks : in natural range 0 to 2**c_max_ranks - 1;
op_length : in natural range 1 to 8;
auto_prech : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := read(config_rec, previous(previous'high), bank, col, ranks, op_length, auto_prech);
-- use dwidth_ratio/2 as in FR = 0 , HR = 1, and in future QR = 2 tCK setup + 1 tCK hold
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a refresh command JEDEC abbreviated name: REF
-- -------------------------------------------------------------
function refresh (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for rate in previous'range loop
v_retval(rate) := refresh(config_rec, previous(previous'high), ranks);
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh_entry command JEDEC abbreviated name: SRE
-- -------------------------------------------------------------
function self_refresh_entry (config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
)return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := enter_sr_pd_mode(config_rec, refresh(config_rec, previous, ranks), ranks);
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a self_refresh exit or power_down exit command
-- JEDEC abbreviated names: SRX, PDX
-- -------------------------------------------------------------
function exit_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := maintain_pd_or_sr(config_rec, previous, ranks);
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) or v_mask_workings_b(i);
end loop;
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- cause the selected ranks to enter Self-refresh or Powerdown mode
-- JEDEC abbreviated names: PDE,
-- SRE (if a refresh is concurrently issued to the same ranks)
-- -------------------------------------------------------------
function enter_sr_pd_mode ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
variable v_mask_workings : std_logic_vector(config_rec.num_ranks -1 downto 0);
variable v_mask_workings_b : std_logic_vector(config_rec.num_ranks -1 downto 0);
begin
v_retval := previous;
v_mask_workings_b := std_logic_vector(to_unsigned(ranks, config_rec.num_ranks));
for rate in 0 to config_rec.cmds_per_clk - 1 loop
if rate >= config_rec.cmds_per_clk / 2 then -- maintain command but clear CS of subsequenct command slots
v_mask_workings := std_logic_vector(to_unsigned(v_retval(rate).cke, config_rec.num_ranks));
for i in v_mask_workings_b'range loop
v_mask_workings(i) := v_mask_workings(i) and not v_mask_workings_b(i);
end loop;
v_retval(rate).cke := to_integer(unsigned(v_mask_workings)); -- almost irrelevant. but optimises logic slightly for Quater rate
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- Issues a mode register set command JEDEC abbreviated name: MRS
-- -------------------------------------------------------------
function load_mode ( config_rec : in t_addr_cmd_config_rec;
mode_register_num : in natural range 0 to 3;
mode_reg_value : in std_logic_vector(c_max_mode_reg_bit downto 0);
ranks : in natural range 0 to 2**c_max_ranks -1;
remap_addr_and_ba : in boolean
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => load_mode(config_rec, mode_register_num, mode_reg_value, ranks, remap_addr_and_ba));
for rate in v_retval'range loop
if rate /= config_rec.cmds_per_clk/2 then
v_retval(rate).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- maintains SR or PD mode on slected ranks.
-- NOTE: does not affect previous command
-- -------------------------------------------------------------
function maintain_pd_or_sr ( config_rec : in t_addr_cmd_config_rec;
previous : in t_addr_cmd_vector;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
for command in v_retval'range loop
v_retval(command) := maintain_pd_or_sr(config_rec, previous(command), ranks);
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (long) JEDEC abbreviated name: ZQCL
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCL ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCL(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- -------------------------------------------------------------
-- issues a ZQ cal (short) JEDEC abbreviated name: ZQCS
-- NOTE - can only be issued to a single RANK ata a time.
-- -------------------------------------------------------------
function ZQCS ( config_rec : in t_addr_cmd_config_rec;
rank : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in v_retval'range loop
v_retval(command) := ZQCS(config_rec, rank);
if command * 2 /= config_rec.cmds_per_clk then
v_retval(command).cs_n := (2 ** config_rec.num_cs_bits) -1;
end if;
end loop;
return v_retval;
end function;
-- ----------------------
-- Additional Rank manipulation functions (main use DDR3)
-- -------------
-- -----------------------------------
-- set the chip select for a group of ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or not mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable v_mask_workings : std_logic_vector(config_rec.num_cs_bits-1 downto 0);
begin
v_retval := record_to_mask;
v_mask_workings := std_logic_vector(to_unsigned(record_to_mask.cs_n, config_rec.num_cs_bits));
for i in mem_ac_swapped_ranks'range loop
v_mask_workings(i):= v_mask_workings(i) or mem_ac_swapped_ranks(i);
end loop;
v_retval.cs_n := to_integer(unsigned(v_mask_workings));
return v_retval;
end function;
-- -----------------------------------
-- set the chip select for a group of ranks in a way which handles diffrent rates
-- -----------------------------------
function all_unreversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_unreversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- -----------------------------------
-- inverse of the above handling ranks
-- -----------------------------------
function all_reversed_ranks ( config_rec : in t_addr_cmd_config_rec;
record_to_mask : in t_addr_cmd_vector;
mem_ac_swapped_ranks : in std_logic_vector
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
for command in record_to_mask'range loop
v_retval(command) := all_reversed_ranks(config_rec, record_to_mask(command), mem_ac_swapped_ranks);
end loop;
return v_retval;
end function;
-- --------------------------------------------------
-- Program a single control word onto RDIMM.
-- This is accomplished rather goofily by asserting all chip selects
-- and then writing out both the addr/data of the word onto the addr/ba bus
-- --------------------------------------------------
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd
is
variable v_retval : t_addr_cmd;
variable ba : std_logic_vector(2 downto 0);
variable addr : std_logic_vector(4 downto 0);
begin
v_retval := defaults(config_rec);
v_retval.cs_n := 0;
ba := control_word_addr(3) & control_word_data(3) & control_word_data(2);
v_retval.ba := to_integer(unsigned(ba));
addr := control_word_data(1) & control_word_data(0) & control_word_addr(2) &
control_word_addr(1) & control_word_addr(0);
v_retval.addr := to_integer(unsigned(addr));
return v_retval;
end function;
function program_rdimm_register ( config_rec : in t_addr_cmd_config_rec;
control_word_addr : in std_logic_vector(3 downto 0);
control_word_data : in std_logic_vector(3 downto 0)
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_retval := (others => program_rdimm_register(config_rec, control_word_addr, control_word_data));
return v_retval;
end function;
-- --------------------------------------------------
-- overloaded functions, to simplify use, or provide simplified functionality
-- --------------------------------------------------
-- ----------------------------------------------------
-- Precharge all, defaulting all bits.
-- ----------------------------------------------------
function precharge_all ( config_rec : in t_addr_cmd_config_rec;
ranks : in natural range 0 to 2**c_max_ranks -1
) return t_addr_cmd_vector
is
variable v_retval : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1) := defaults(config_rec);
begin
v_retval := precharge_all(config_rec, v_retval, ranks);
return v_retval;
end function;
-- ----------------------------------------------------
-- perform DLL reset through mode registers
-- ----------------------------------------------------
function dll_reset ( config_rec : in t_addr_cmd_config_rec;
mode_reg_val : in std_logic_vector;
rank_num : in natural range 0 to 2**c_max_ranks - 1;
reorder_addr_bits : in boolean
) return t_addr_cmd_vector is
variable int_mode_reg : std_logic_vector(mode_reg_val'range);
variable output : t_addr_cmd_vector(0 to config_rec.cmds_per_clk - 1);
begin
int_mode_reg := mode_reg_val;
int_mode_reg(8) := '1'; -- set DLL reset bit.
output := load_mode(config_rec, 0, int_mode_reg, rank_num, reorder_addr_bits);
return output;
end function;
-- -------------------------------------------------------------
-- package configuration functions
-- -------------------------------------------------------------
-- -------------------------------------------------------------
-- the following function sets up the odt settings
-- NOTES: supports DDR/DDR2/DDR3 SDRAM memories
-- -------------------------------------------------------------
function set_odt_values (ranks : natural;
ranks_per_slot : natural;
mem_type : in string
) return t_odt_array is
variable v_num_slots : natural;
variable v_cs : natural range 0 to ranks-1;
variable v_odt_values : t_odt_array(0 to ranks-1);
variable v_cs_addr : unsigned(ranks-1 downto 0);
begin
if mem_type = "DDR" then
-- ODT not supported for DDR memory so set default off
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 0;
v_odt_values(v_cs).read := 0;
end loop;
elsif mem_type = "DDR2" then
-- odt setting as implemented in the altera high-performance controller for ddr2 memories
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr);
v_odt_values(v_cs).read := v_odt_values(v_cs).write;
end loop;
end if;
elsif mem_type = "DDR3" then
assert (ranks rem ranks_per_slot = 0) report ac_report_prefix & "number of ranks per slot must be a multiple of number of ranks" severity failure;
v_num_slots := ranks/ranks_per_slot;
if v_num_slots = 1 then
-- special condition for 1 slot (i.e. DIMM) (2^n, n=0,1,2,... ranks only)
-- set odt on one chip for writes and no odt for reads
for v_cs in 0 to ranks-1 loop
v_odt_values(v_cs).write := 2**v_cs; -- on on the rank being written to
v_odt_values(v_cs).read := 0;
end loop;
else
-- if > 1 slot, set 1 odt enable on neighbouring slot for read and write
-- as an example consider the below for 4 slots with 2 ranks per slot
-- access to CS[0] or CS[1], enable ODT[2] or ODT[3]
-- access to CS[2] or CS[3], enable ODT[0] or ODT[1]
-- access to CS[4] or CS[5], enable ODT[6] or ODT[7]
-- access to CS[6] or CS[7], enable ODT[4] or ODT[5]
-- the logic below implements the above for varying ranks and ranks_per slot
-- under the condition that ranks/ranks_per_slot is integer
for v_cs in 0 to ranks-1 loop
v_cs_addr := to_unsigned(v_cs, ranks);
v_cs_addr(ranks_per_slot-1) := not v_cs_addr(ranks_per_slot-1);
v_odt_values(v_cs).write := 2**to_integer(v_cs_addr) + 2**(v_cs); -- turn on a neighbouring slots cs and current rank being written to
v_odt_values(v_cs).read := 2**to_integer(v_cs_addr);
end loop;
end if;
else
report ac_report_prefix & "unknown mem_type specified in the set_odt_values function in addr_cmd_pkg package" severity failure;
end if;
return v_odt_values;
end function;
-- -----------------------------------------------------------
-- set constant values to config_rec
-- ----------------------------------------------------------
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
num_ranks : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
variable v_config_rec : t_addr_cmd_config_rec;
begin
v_config_rec.num_addr_bits := num_addr_bits;
v_config_rec.num_ba_bits := num_ba_bits;
v_config_rec.num_cs_bits := num_cs_bits;
v_config_rec.num_ranks := num_ranks;
v_config_rec.cmds_per_clk := dwidth_ratio/2;
if mem_type = "DDR" then
v_config_rec.mem_type := DDR;
elsif mem_type = "DDR2" then
v_config_rec.mem_type := DDR2;
elsif mem_type = "DDR3" then
v_config_rec.mem_type := DDR3;
else
report ac_report_prefix & "unknown mem_type specified in the set_config_rec function in addr_cmd_pkg package" severity failure;
end if;
return v_config_rec;
end function;
-- The non-levelled sequencer doesn't make a distinction between CS_WIDTH and NUM_RANKS. In this case,
-- just set the two to be the same.
function set_config_rec ( num_addr_bits : in natural;
num_ba_bits : in natural;
num_cs_bits : in natural;
dwidth_ratio : in natural range 1 to c_max_cmds_per_clk;
mem_type : in string
) return t_addr_cmd_config_rec
is
begin
return set_config_rec(num_addr_bits, num_ba_bits, num_cs_bits, num_cs_bits, dwidth_ratio, mem_type);
end function;
-- -----------------------------------------------------------
-- unpack and pack address and command signals from and to t_addr_cmd_vector
-- -----------------------------------------------------------
-- -------------------------------------------------------------
-- convert from t_addr_cmd_vector to expanded addr/cmd signals
-- -------------------------------------------------------------
procedure unpack_addr_cmd_vector( addr_cmd_vector : in t_addr_cmd_vector;
config_rec : in t_addr_cmd_config_rec;
addr : out std_logic_vector;
ba : out std_logic_vector;
cas_n : out std_logic_vector;
ras_n : out std_logic_vector;
we_n : out std_logic_vector;
cke : out std_logic_vector;
cs_n : out std_logic_vector;
odt : out std_logic_vector;
rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
v_vec_len := config_rec.cmds_per_clk;
v_mem_if_ranks := config_rec.num_ranks;
for v_i in 0 to v_vec_len-1 loop
assert addr_cmd_vector(v_i).addr < 2**config_rec.num_addr_bits report ac_report_prefix &
"value of addr exceeds range of number of address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).ba < 2**config_rec.num_ba_bits report ac_report_prefix &
"value of ba exceeds range of number of bank address bits in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).odt < 2**v_mem_if_ranks report ac_report_prefix &
"value of odt exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cs_n < 2**config_rec.num_cs_bits report ac_report_prefix &
"value of cs_n exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
assert addr_cmd_vector(v_i).cke < 2**v_mem_if_ranks report ac_report_prefix &
"value of cke exceeds range of number of ranks in unpack_addr_cmd_vector procedure" severity failure;
v_addr((v_i+1)*config_rec.num_addr_bits - 1 downto v_i*config_rec.num_addr_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).addr,config_rec.num_addr_bits));
v_ba((v_i+1)*config_rec.num_ba_bits - 1 downto v_i*config_rec.num_ba_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).ba,config_rec.num_ba_bits));
v_cke((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cke,v_mem_if_ranks));
v_cs_n((v_i+1)*config_rec.num_cs_bits - 1 downto v_i*config_rec.num_cs_bits) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).cs_n,config_rec.num_cs_bits));
v_odt((v_i+1)*v_mem_if_ranks - 1 downto v_i*v_mem_if_ranks) := std_logic_vector(to_unsigned(addr_cmd_vector(v_i).odt,v_mem_if_ranks));
if (addr_cmd_vector(v_i).cas_n) then v_cas_n(v_i) := '0'; else v_cas_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).ras_n) then v_ras_n(v_i) := '0'; else v_ras_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).we_n) then v_we_n(v_i) := '0'; else v_we_n(v_i) := '1'; end if;
if (addr_cmd_vector(v_i).rst_n) then v_rst_n(v_i) := '0'; else v_rst_n(v_i) := '1'; end if;
end loop;
addr := v_addr;
ba := v_ba;
cke := v_cke;
cs_n := v_cs_n;
odt := v_odt;
cas_n := v_cas_n;
ras_n := v_ras_n;
we_n := v_we_n;
rst_n := v_rst_n;
end procedure;
procedure unpack_addr_cmd_vector( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal addr : out std_logic_vector;
signal ba : out std_logic_vector;
signal cas_n : out std_logic_vector;
signal ras_n : out std_logic_vector;
signal we_n : out std_logic_vector;
signal cke : out std_logic_vector;
signal cs_n : out std_logic_vector;
signal odt : out std_logic_vector;
signal rst_n : out std_logic_vector
)
is
variable v_mem_if_ranks : natural range 0 to 2**c_max_ranks - 1;
variable v_vec_len : natural range 1 to 4;
variable v_seq_ac_addr : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_addr_bits - 1 downto 0);
variable v_seq_ac_ba : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ba_bits - 1 downto 0);
variable v_seq_ac_cas_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_ras_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_we_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
variable v_seq_ac_cke : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_cs_n : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_cs_bits - 1 downto 0);
variable v_seq_ac_odt : std_logic_vector(config_rec.cmds_per_clk * config_rec.num_ranks - 1 downto 0);
variable v_seq_ac_rst_n : std_logic_vector(config_rec.cmds_per_clk - 1 downto 0);
begin
unpack_addr_cmd_vector (
addr_cmd_vector,
config_rec,
v_seq_ac_addr,
v_seq_ac_ba,
v_seq_ac_cas_n,
v_seq_ac_ras_n,
v_seq_ac_we_n,
v_seq_ac_cke,
v_seq_ac_cs_n,
v_seq_ac_odt,
v_seq_ac_rst_n);
addr <= v_seq_ac_addr;
ba <= v_seq_ac_ba;
cas_n <= v_seq_ac_cas_n;
ras_n <= v_seq_ac_ras_n;
we_n <= v_seq_ac_we_n;
cke <= v_seq_ac_cke;
cs_n <= v_seq_ac_cs_n;
odt <= v_seq_ac_odt;
rst_n <= v_seq_ac_rst_n;
end procedure;
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_
-- -----------------------------------------------------------
-- -----------------------------------------------------------
-- function to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then v_addr_cmd_vector(v_i).addr := 0; else v_addr_cmd_vector(v_i).addr := (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then v_addr_cmd_vector(v_i).ba := 0; else v_addr_cmd_vector(v_i).ba := (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cas_n := true; else v_addr_cmd_vector(v_i).cas_n := false; end if;
when ras_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).ras_n := true; else v_addr_cmd_vector(v_i).ras_n := false; end if;
when we_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).we_n := true; else v_addr_cmd_vector(v_i).we_n := false; end if;
when cke => if (mask_value = '0') then v_addr_cmd_vector(v_i).cke := 0; else v_addr_cmd_vector(v_i).cke := (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).cs_n := 0; else v_addr_cmd_vector(v_i).cs_n := (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then v_addr_cmd_vector(v_i).odt := 0; else v_addr_cmd_vector(v_i).odt := (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then v_addr_cmd_vector(v_i).rst_n := true; else v_addr_cmd_vector(v_i).rst_n := false; end if;
when others => report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
-- -----------------------------------------------------------
-- procedure to mask each bit of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
procedure mask( config_rec : in t_addr_cmd_config_rec;
signal addr_cmd_vector : inout t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic
)
is
variable v_i : integer;
begin
for v_i in 0 to (config_rec.cmds_per_clk)-1 loop
case signal_name is
when addr => if (mask_value = '0') then addr_cmd_vector(v_i).addr <= 0; else addr_cmd_vector(v_i).addr <= (2 ** config_rec.num_addr_bits) - 1; end if;
when ba => if (mask_value = '0') then addr_cmd_vector(v_i).ba <= 0; else addr_cmd_vector(v_i).ba <= (2 ** config_rec.num_ba_bits) - 1; end if;
when cas_n => if (mask_value = '0') then addr_cmd_vector(v_i).cas_n <= true; else addr_cmd_vector(v_i).cas_n <= false; end if;
when ras_n => if (mask_value = '0') then addr_cmd_vector(v_i).ras_n <= true; else addr_cmd_vector(v_i).ras_n <= false; end if;
when we_n => if (mask_value = '0') then addr_cmd_vector(v_i).we_n <= true; else addr_cmd_vector(v_i).we_n <= false; end if;
when cke => if (mask_value = '0') then addr_cmd_vector(v_i).cke <= 0; else addr_cmd_vector(v_i).cke <= (2**config_rec.num_ranks) -1; end if;
when cs_n => if (mask_value = '0') then addr_cmd_vector(v_i).cs_n <= 0; else addr_cmd_vector(v_i).cs_n <= (2**config_rec.num_cs_bits) -1; end if;
when odt => if (mask_value = '0') then addr_cmd_vector(v_i).odt <= 0; else addr_cmd_vector(v_i).odt <= (2**config_rec.num_ranks) -1; end if;
when rst_n => if (mask_value = '0') then addr_cmd_vector(v_i).rst_n <= true; else addr_cmd_vector(v_i).rst_n <= false; end if;
when others => report ac_report_prefix & "masking not supported for the given signal name" severity failure;
end case;
end loop;
end procedure;
-- -----------------------------------------------------------
-- function to mask a given bit (mask_bit) of signal signal_name in addr_cmd_vector with mask_value
-- -----------------------------------------------------------
function mask ( config_rec : in t_addr_cmd_config_rec;
addr_cmd_vector : in t_addr_cmd_vector;
signal_name : in t_addr_cmd_signals;
mask_value : in std_logic;
mask_bit : in natural
) return t_addr_cmd_vector
is
variable v_i : integer;
variable v_addr : std_logic_vector(config_rec.num_addr_bits-1 downto 0); -- v_addr is bit vector of address
variable v_ba : std_logic_vector(config_rec.num_ba_bits-1 downto 0); -- v_addr is bit vector of bank address
variable v_vec_len : natural range 0 to 4;
variable v_addr_cmd_vector : t_addr_cmd_vector(0 to config_rec.cmds_per_clk -1);
begin
v_addr_cmd_vector := addr_cmd_vector;
v_vec_len := config_rec.cmds_per_clk;
for v_i in 0 to v_vec_len-1 loop
case signal_name is
when addr =>
v_addr := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).addr,v_addr'length));
v_addr(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).addr := to_integer(unsigned(v_addr));
when ba =>
v_ba := std_logic_vector(to_unsigned(v_addr_cmd_vector(v_i).ba,v_ba'length));
v_ba(mask_bit) := mask_value;
v_addr_cmd_vector(v_i).ba := to_integer(unsigned(v_ba));
when others =>
report ac_report_prefix & "bit masking not supported for the given signal name" severity failure;
end case;
end loop;
return v_addr_cmd_vector;
end function;
--
end ddr2_phy_alt_mem_phy_addr_cmd_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram addressing package for the non-levelling AFI PHY sequencer
-- The iram address package (alt_mem_phy_iram_addr_pkg) is
-- used to define the base addresses used for iram writes
-- during calibration.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
package ddr2_phy_alt_mem_phy_iram_addr_pkg IS
constant c_ihi_size : natural := 8;
type t_base_hdr_addresses is record
base_hdr : natural;
rrp : natural;
safe_dummy : natural;
required_addr_bits : natural;
end record;
function defaults return t_base_hdr_addresses;
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural;
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses;
--
end ddr2_phy_alt_mem_phy_iram_addr_pkg;
--
package body ddr2_phy_alt_mem_phy_iram_addr_pkg IS
-- set some safe default values
function defaults return t_base_hdr_addresses is
variable temp : t_base_hdr_addresses;
begin
temp.base_hdr := 0;
temp.rrp := 0;
temp.safe_dummy := 0;
temp.required_addr_bits := 1;
return temp;
end function;
-- this function determines now many times the PLL phases are swept through per pin
-- i.e. an n * 360 degree phase sweep
function rrp_pll_phase_mult (dwidth_ratio : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
begin
if dwidth_ratio = 2 and dqs_capture = 1 then
v_output := 2; -- if dqs_capture then a 720 degree sweep needed in FR
else
v_output := (dwidth_ratio/2);
end if;
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_full_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := dq_pins * (((v_phase_mul * pll_phases) + 31) / 32);
return v_output;
end function;
-- function to calculate how many words are required for a rrp sweep over all pins
function iram_wd_for_one_pin_rrp ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
dqs_capture : in natural
)
return natural
is
variable v_output : natural;
variable v_phase_mul : natural;
begin
-- determine the n * 360 degrees of sweep required
v_phase_mul := rrp_pll_phase_mult(dwidth_ratio, dqs_capture);
-- calculate output size
v_output := ((v_phase_mul * pll_phases) + 31) / 32;
return v_output;
end function;
-- return iram addresses
function calc_iram_addresses ( dwidth_ratio : in natural;
pll_phases : in natural;
dq_pins : in natural;
num_ranks : in natural;
dqs_capture : in natural
)
return t_base_hdr_addresses
is
variable working : t_base_hdr_addresses;
variable temp : natural;
variable v_required_words : natural;
begin
working.base_hdr := 0;
working.rrp := working.base_hdr + c_ihi_size;
-- work out required number of address bits
-- + for 1 full rrp calibration
v_required_words := iram_wd_for_full_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2; -- +2 for header + footer
-- * loop per cs
v_required_words := v_required_words * num_ranks;
-- + for 1 rrp_seek result
v_required_words := v_required_words + 3; -- 1 header, 1 word result, 1 footer
-- + 2 mtp_almt passes
v_required_words := v_required_words + 2 * (iram_wd_for_one_pin_rrp(dwidth_ratio, pll_phases, dq_pins, dqs_capture) + 2);
-- + for 2 read_mtp result calculation
v_required_words := v_required_words + 3*2; -- 1 header, 1 word result, 1 footer
-- * possible dwidth_ratio/2 iterations for different ac_nt settings
v_required_words := v_required_words * (dwidth_ratio / 2);
working.safe_dummy := working.rrp + v_required_words;
temp := working.safe_dummy;
working.required_addr_bits := 0;
while (temp >= 1) loop
working.required_addr_bits := working.required_addr_bits + 1;
temp := temp /2;
end loop;
return working;
end function calc_iram_addresses;
--
END ddr2_phy_alt_mem_phy_iram_addr_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : register package for the non-levelling AFI PHY sequencer
-- The registers package (alt_mem_phy_regs_pkg) is used to
-- combine the definition of the registers for the mmi status
-- registers and functions/procedures applied to the registers
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
--
package ddr2_phy_alt_mem_phy_regs_pkg is
-- a prefix for all report signals to identify phy and sequencer block
--
constant regs_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (register package) : ";
-- ---------------------------------------------------------------
-- register declarations with associated functions of:
-- default - assign default values
-- write - write data into the reg (from avalon i/f)
-- read - read data from the reg (sent to the avalon i/f)
-- write_clear - clear reg to all zeros
-- ---------------------------------------------------------------
-- TYPE DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
type t_cal_status is record
iram_addr_width : std_logic_vector(3 downto 0);
out_of_mem : std_logic;
contested_access : std_logic;
cal_fail : std_logic;
cal_success : std_logic;
ctrl_err_code : std_logic_vector(7 downto 0);
trefi_failure : std_logic;
int_ac_1t : std_logic;
dqs_capture : std_logic;
iram_present : std_logic;
active_block : std_logic_vector(3 downto 0);
current_stage : std_logic_vector(7 downto 0);
end record;
-- codvw status
type t_codvw_status is record
cal_codvw_phase : std_logic_vector(7 downto 0);
cal_codvw_size : std_logic_vector(7 downto 0);
codvw_trk_shift : std_logic_vector(11 downto 0);
codvw_grt_one_dvw : std_logic;
end record t_codvw_status;
-- test status report
type t_test_status is record
ack_seen : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
pll_mmi_err : std_logic_vector(1 downto 0);
pll_busy : std_logic;
end record;
-- define all the read only registers :
type t_ro_regs is record
cal_status : t_cal_status;
codvw_status : t_codvw_status;
test_status : t_test_status;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
type t_hl_css is record
hl_css : std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
cal_start : std_logic;
end record t_hl_css;
-- Mode register A
type t_mr_register_a is record
mr0 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr1 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_a;
-- Mode register B
type t_mr_register_b is record
mr2 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
mr3 : std_logic_vector(c_max_mode_reg_index -1 downto 0);
end record t_mr_register_b;
-- algorithm parameterisation register
type t_parameterisation_reg_a is record
nominal_poa_phase_lead : std_logic_vector(3 downto 0);
maximum_poa_delay : std_logic_vector(3 downto 0);
num_phases_per_tck_pll : std_logic_vector(3 downto 0);
pll_360_sweeps : std_logic_vector(3 downto 0);
nominal_dqs_delay : std_logic_vector(2 downto 0);
extend_octrt_by : std_logic_vector(3 downto 0);
delay_octrt_by : std_logic_vector(3 downto 0);
end record;
-- test signal register
type t_if_test_reg is record
pll_phs_shft_phase_sel : natural range 0 to 15;
pll_phs_shft_up_wc : std_logic;
pll_phs_shft_dn_wc : std_logic;
ac_1t_toggle : std_logic; -- unused
tracking_period_ms : std_logic_vector(7 downto 0); -- 0 = as fast as possible approx in ms
tracking_units_are_10us : std_logic;
end record;
-- define all the read/write registers
type t_rw_regs is record
mr_reg_a : t_mr_register_a;
mr_reg_b : t_mr_register_b;
rw_hl_css : t_hl_css;
rw_param_reg : t_parameterisation_reg_a;
rw_if_test : t_if_test_reg;
end record;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
type t_mmi_regs is record
rw_regs : t_rw_regs;
ro_regs : t_ro_regs;
enable_writes : std_logic;
end record;
-- FUNCTION DECLARATIONS
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- cal_status
function defaults return t_cal_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status;
function read (reg : t_cal_status) return std_logic_vector;
-- codvw status
function defaults return t_codvw_status;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status;
function read (reg : in t_codvw_status) return std_logic_vector;
-- test status report
function defaults return t_test_status;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status;
function read (reg : t_test_status) return std_logic_vector;
-- define all the read only registers
function defaults return t_ro_regs;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write Registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Calibration control register
-- high level calibration stage set register comprises a bit vector for
-- the calibration stage coding and the 1 control bit.
function defaults return t_hl_css;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_hl_css;
function read (reg : in t_hl_css) return std_logic_vector;
procedure write_clear (signal reg : inout t_hl_css);
-- Mode register A
-- mode registers 0 and 1 (mr and emr1)
function defaults return t_mr_register_a;
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a;
function read (reg : in t_mr_register_a) return std_logic_vector;
-- Mode register B
-- mode registers 2 and 3 (emr2 and emr3) - not present in ddr DRAM
function defaults return t_mr_register_b;
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b;
function read (reg : in t_mr_register_b) return std_logic_vector;
-- algorithm parameterisation register
function defaults return t_parameterisation_reg_a;
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a;
-- test signal register
function defaults return t_if_test_reg;
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg;
function read ( reg : in t_if_test_reg) return std_logic_vector;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg;
procedure write_clear (signal reg : inout t_if_test_reg);
-- define all the read/write registers
function defaults return t_rw_regs;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs;
procedure write_clear (signal regs : inout t_rw_regs);
-- >>>>>>>>>>>>>>>>>>>>>>>
-- Group all registers
-- >>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0));
-- >>>>>>>>>>>>>>>>>>>>>>>
-- functions to communicate register settings to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl;
function pack_record ( ip_regs : t_rw_regs) return t_algm_paramaterisation;
-- >>>>>>>>>>>>>>>>>>>>>>>
-- helper functions
-- >>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css ) return t_hl_css_reg;
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector;
-- encoding of stage and active block for register setting
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id) return std_logic_vector;
function encode_active_block (active_block : t_ctrl_active_block) return std_logic_vector;
--
end ddr2_phy_alt_mem_phy_regs_pkg;
--
package body ddr2_phy_alt_mem_phy_regs_pkg is
-- >>>>>>>>>>>>>>>>>>>>
-- Read Only Registers
-- >>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- CODVW status report
-- ---------------------------------------------------------------
function defaults return t_codvw_status is
variable temp: t_codvw_status;
begin
temp.cal_codvw_phase := (others => '0');
temp.cal_codvw_size := (others => '0');
temp.codvw_trk_shift := (others => '0');
temp.codvw_grt_one_dvw := '0';
return temp;
end function;
function defaults ( dgrb_mmi : t_dgrb_mmi
) return t_codvw_status is
variable temp: t_codvw_status;
begin
temp := defaults;
temp.cal_codvw_phase := dgrb_mmi.cal_codvw_phase;
temp.cal_codvw_size := dgrb_mmi.cal_codvw_size;
temp.codvw_trk_shift := dgrb_mmi.codvw_trk_shift;
temp.codvw_grt_one_dvw := dgrb_mmi.codvw_grt_one_dvw;
return temp;
end function;
function read (reg : in t_codvw_status) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0);
begin
temp := (others => '0');
temp(31 downto 24) := reg.cal_codvw_phase;
temp(23 downto 16) := reg.cal_codvw_size;
temp(15 downto 4) := reg.codvw_trk_shift;
temp(0) := reg.codvw_grt_one_dvw;
return temp;
end function;
-- ---------------------------------------------------------------
-- Calibration status report
-- ---------------------------------------------------------------
function defaults return t_cal_status is
variable temp: t_cal_status;
begin
temp.iram_addr_width := (others => '0');
temp.out_of_mem := '0';
temp.contested_access := '0';
temp.cal_fail := '0';
temp.cal_success := '0';
temp.ctrl_err_code := (others => '0');
temp.trefi_failure := '0';
temp.int_ac_1t := '0';
temp.dqs_capture := '0';
temp.iram_present := '0';
temp.active_block := (others => '0');
temp.current_stage := (others => '0');
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
USE_IRAM : in std_logic;
dqs_capture : in natural;
int_ac_1t : in std_logic;
trefi_failure : in std_logic;
iram_status : in t_iram_stat;
IRAM_AWIDTH : in natural
) return t_cal_status is
variable temp : t_cal_status;
begin
temp := defaults;
temp.iram_addr_width := std_logic_vector(to_unsigned(IRAM_AWIDTH, temp.iram_addr_width'length));
temp.out_of_mem := iram_status.out_of_mem;
temp.contested_access := iram_status.contested_access;
temp.cal_fail := ctrl_mmi.ctrl_calibration_fail;
temp.cal_success := ctrl_mmi.ctrl_calibration_success;
temp.ctrl_err_code := ctrl_mmi.ctrl_err_code;
temp.trefi_failure := trefi_failure;
temp.int_ac_1t := int_ac_1t;
if dqs_capture = 1 then
temp.dqs_capture := '1';
elsif dqs_capture = 0 then
temp.dqs_capture := '0';
else
report regs_report_prefix & " invalid value for dqs_capture constant of " & integer'image(dqs_capture) severity failure;
end if;
temp.iram_present := USE_IRAM;
temp.active_block := encode_active_block(ctrl_mmi.ctrl_current_active_block);
temp.current_stage := encode_current_stage(ctrl_mmi.ctrl_current_stage);
return temp;
end function;
-- read for mmi status register
function read ( reg : t_cal_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output( 7 downto 0) := reg.current_stage;
output(11 downto 8) := reg.active_block;
output(12) := reg.iram_present;
output(13) := reg.dqs_capture;
output(14) := reg.int_ac_1t;
output(15) := reg.trefi_failure;
output(23 downto 16) := reg.ctrl_err_code;
output(24) := reg.cal_success;
output(25) := reg.cal_fail;
output(26) := reg.contested_access;
output(27) := reg.out_of_mem;
output(31 downto 28) := reg.iram_addr_width;
return output;
end function;
-- ---------------------------------------------------------------
-- Test status report
-- ---------------------------------------------------------------
function defaults return t_test_status is
variable temp: t_test_status;
begin
temp.ack_seen := (others => '0');
temp.pll_mmi_err := (others => '0');
temp.pll_busy := '0';
return temp;
end function;
function defaults ( ctrl_mmi : in t_ctrl_mmi;
pll_mmi : in t_pll_mmi;
rw_if_test : t_if_test_reg
) return t_test_status is
variable temp : t_test_status;
begin
temp := defaults;
temp.ack_seen := pack_ack_seen(ctrl_mmi.ctrl_cal_stage_ack_seen);
temp.pll_mmi_err := pll_mmi.err;
temp.pll_busy := pll_mmi.pll_busy or rw_if_test.pll_phs_shft_up_wc or rw_if_test.pll_phs_shft_dn_wc;
return temp;
end function;
-- read for mmi status register
function read ( reg : t_test_status
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
output(31 downto 32-c_hl_ccs_num_stages) := reg.ack_seen;
output( 5 downto 4) := reg.pll_mmi_err;
output(0) := reg.pll_busy;
return output;
end function;
-------------------------------------------------
-- FOR ALL RO REGS:
-------------------------------------------------
function defaults return t_ro_regs is
variable temp: t_ro_regs;
begin
temp.cal_status := defaults;
temp.codvw_status := defaults;
return temp;
end function;
function defaults (dgrb_mmi : t_dgrb_mmi;
ctrl_mmi : t_ctrl_mmi;
pll_mmi : t_pll_mmi;
rw_if_test : t_if_test_reg;
USE_IRAM : std_logic;
dqs_capture : natural;
int_ac_1t : std_logic;
trefi_failure : std_logic;
iram_status : t_iram_stat;
IRAM_AWIDTH : natural
) return t_ro_regs is
variable output : t_ro_regs;
begin
output := defaults;
output.cal_status := defaults(ctrl_mmi, USE_IRAM, dqs_capture, int_ac_1t, trefi_failure, iram_status, IRAM_AWIDTH);
output.codvw_status := defaults(dgrb_mmi);
output.test_status := defaults(ctrl_mmi, pll_mmi, rw_if_test);
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- Read / Write registers
-- >>>>>>>>>>>>>>>>>>>>>>>>
-- ---------------------------------------------------------------
-- mode register set A
-- ---------------------------------------------------------------
function defaults return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := (others => '0');
temp.mr1 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr0 : in std_logic_vector;
mr1 : in std_logic_vector
) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp := defaults;
temp.mr0 := mr0(temp.mr0'range);
temp.mr1 := mr1(temp.mr1'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_a is
variable temp :t_mr_register_a;
begin
temp.mr0 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr1 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_a) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr0;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr1;
return temp;
end function;
-- ---------------------------------------------------------------
-- mode register set B
-- ---------------------------------------------------------------
function defaults return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := (others => '0');
temp.mr3 := (others => '0');
return temp;
end function;
-- apply default mode register settings to register
function defaults ( mr2 : in std_logic_vector;
mr3 : in std_logic_vector
) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp := defaults;
temp.mr2 := mr2(temp.mr2'range);
temp.mr3 := mr3(temp.mr3'range);
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_mr_register_b is
variable temp :t_mr_register_b;
begin
temp.mr2 := wdata_in(c_max_mode_reg_index -1 downto 0);
temp.mr3 := wdata_in(c_max_mode_reg_index -1 + 16 downto 16);
return temp;
end function;
function read (reg : in t_mr_register_b) return std_logic_vector is
variable temp : std_logic_vector(31 downto 0) := (others => '0');
begin
temp(c_max_mode_reg_index -1 downto 0) := reg.mr2;
temp(c_max_mode_reg_index -1 + 16 downto 16) := reg.mr3;
return temp;
end function;
-- ---------------------------------------------------------------
-- HL CSS (high level calibration state status)
-- ---------------------------------------------------------------
function defaults return t_hl_css is
variable temp : t_hl_css;
begin
temp.hl_css := (others => '0');
temp.cal_start := '0';
return temp;
end function;
function defaults ( C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
) return t_hl_css is
variable temp: t_hl_css;
begin
temp := defaults;
temp.hl_css := temp.hl_css OR C_HL_STAGE_ENABLE;
return temp;
end function;
function read ( reg : in t_hl_css) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp(30 downto 30-c_hl_ccs_num_stages+1) := reg.hl_css;
temp(0) := reg.cal_start;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0) )return t_hl_css is
variable reg : t_hl_css;
begin
reg.hl_css := wdata_in(30 downto 30-c_hl_ccs_num_stages+1);
reg.cal_start := wdata_in(0);
return reg;
end function;
procedure write_clear (signal reg : inout t_hl_css) is
begin
reg.cal_start <= '0';
end procedure;
-- ---------------------------------------------------------------
-- paramaterisation of sequencer through Avalon interface
-- ---------------------------------------------------------------
function defaults return t_parameterisation_reg_a is
variable temp : t_parameterisation_reg_a;
begin
temp.nominal_poa_phase_lead := (others => '0');
temp.maximum_poa_delay := (others => '0');
temp.pll_360_sweeps := "0000";
temp.num_phases_per_tck_pll := "0011";
temp.nominal_dqs_delay := (others => '0');
temp.extend_octrt_by := "0100";
temp.delay_octrt_by := "0000";
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural
) return t_parameterisation_reg_a is
variable temp: t_parameterisation_reg_a;
begin
temp := defaults;
temp.num_phases_per_tck_pll := std_logic_vector(to_unsigned(PLL_STEPS_PER_CYCLE /8 , temp.num_phases_per_tck_pll'high + 1 ));
temp.pll_360_sweeps := std_logic_vector(to_unsigned(pll_360_sweeps , temp.pll_360_sweeps'high + 1 ));
temp.nominal_dqs_delay := std_logic_vector(to_unsigned(NOM_DQS_PHASE_SETTING , temp.nominal_dqs_delay'high + 1 ));
temp.extend_octrt_by := std_logic_vector(to_unsigned(5 , temp.extend_octrt_by'high + 1 ));
temp.delay_octrt_by := std_logic_vector(to_unsigned(6 , temp.delay_octrt_by'high + 1 ));
return temp;
end function;
function read ( reg : in t_parameterisation_reg_a) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := reg.pll_360_sweeps;
temp( 7 downto 4) := reg.num_phases_per_tck_pll;
temp(10 downto 8) := reg.nominal_dqs_delay;
temp(19 downto 16) := reg.nominal_poa_phase_lead;
temp(23 downto 20) := reg.maximum_poa_delay;
temp(27 downto 24) := reg.extend_octrt_by;
temp(31 downto 28) := reg.delay_octrt_by;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_parameterisation_reg_a is
variable reg : t_parameterisation_reg_a;
begin
reg.pll_360_sweeps := wdata_in( 3 downto 0);
reg.num_phases_per_tck_pll := wdata_in( 7 downto 4);
reg.nominal_dqs_delay := wdata_in(10 downto 8);
reg.nominal_poa_phase_lead := wdata_in(19 downto 16);
reg.maximum_poa_delay := wdata_in(23 downto 20);
reg.extend_octrt_by := wdata_in(27 downto 24);
reg.delay_octrt_by := wdata_in(31 downto 28);
return reg;
end function;
-- ---------------------------------------------------------------
-- t_if_test_reg - additional test support register
-- ---------------------------------------------------------------
function defaults return t_if_test_reg is
variable temp : t_if_test_reg;
begin
temp.pll_phs_shft_phase_sel := 0;
temp.pll_phs_shft_up_wc := '0';
temp.pll_phs_shft_dn_wc := '0';
temp.ac_1t_toggle := '0';
temp.tracking_period_ms := "10000000"; -- 127 ms interval
temp.tracking_units_are_10us := '0';
return temp;
end function;
-- reset the paramterisation reg to given values
function defaults ( TRACKING_INTERVAL_IN_MS : in natural
) return t_if_test_reg is
variable temp: t_if_test_reg;
begin
temp := defaults;
temp.tracking_period_ms := std_logic_vector(to_unsigned(TRACKING_INTERVAL_IN_MS, temp.tracking_period_ms'length));
return temp;
end function;
function read ( reg : in t_if_test_reg) return std_logic_vector is
variable temp : std_logic_vector (31 downto 0) := (others => '0');
begin
temp( 3 downto 0) := std_logic_vector(to_unsigned(reg.pll_phs_shft_phase_sel,4));
temp(4) := reg.pll_phs_shft_up_wc;
temp(5) := reg.pll_phs_shft_dn_wc;
temp(16) := reg.ac_1t_toggle;
temp(15 downto 8) := reg.tracking_period_ms;
temp(20) := reg.tracking_units_are_10us;
return temp;
end function;
function write (wdata_in : std_logic_vector(31 downto 0)) return t_if_test_reg is
variable reg : t_if_test_reg;
begin
reg.pll_phs_shft_phase_sel := to_integer(unsigned(wdata_in( 3 downto 0)));
reg.pll_phs_shft_up_wc := wdata_in(4);
reg.pll_phs_shft_dn_wc := wdata_in(5);
reg.ac_1t_toggle := wdata_in(16);
reg.tracking_period_ms := wdata_in(15 downto 8);
reg.tracking_units_are_10us := wdata_in(20);
return reg;
end function;
procedure write_clear (signal reg : inout t_if_test_reg) is
begin
reg.ac_1t_toggle <= '0';
reg.pll_phs_shft_up_wc <= '0';
reg.pll_phs_shft_dn_wc <= '0';
end procedure;
-- ---------------------------------------------------------------
-- RW Regs, record of read/write register records (to simplify handling)
-- ---------------------------------------------------------------
function defaults return t_rw_regs is
variable temp : t_rw_regs;
begin
temp.mr_reg_a := defaults;
temp.mr_reg_b := defaults;
temp.rw_hl_css := defaults;
temp.rw_param_reg := defaults;
temp.rw_if_test := defaults;
return temp;
end function;
function defaults(
mr0 : in std_logic_vector;
mr1 : in std_logic_vector;
mr2 : in std_logic_vector;
mr3 : in std_logic_vector;
NOM_DQS_PHASE_SETTING : in natural;
PLL_STEPS_PER_CYCLE : in natural;
pll_360_sweeps : in natural;
TRACKING_INTERVAL_IN_MS : in natural;
C_HL_STAGE_ENABLE : in std_logic_vector(c_hl_ccs_num_stages-1 downto 0)
)return t_rw_regs is
variable temp : t_rw_regs;
begin
temp := defaults;
temp.mr_reg_a := defaults(mr0, mr1);
temp.mr_reg_b := defaults(mr2, mr3);
temp.rw_param_reg := defaults(NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
pll_360_sweeps);
temp.rw_if_test := defaults(TRACKING_INTERVAL_IN_MS);
temp.rw_hl_css := defaults(C_HL_STAGE_ENABLE);
return temp;
end function;
procedure write_clear (signal regs : inout t_rw_regs) is
begin
write_clear(regs.rw_if_test);
write_clear(regs.rw_hl_css);
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- All mmi registers:
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function defaults return t_mmi_regs is
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs.rw_regs := defaults;
v_mmi_regs.ro_regs := defaults;
v_mmi_regs.enable_writes := '0';
return v_mmi_regs;
end function;
function v_read (mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
begin
output := (others => '0');
case address is
-- status register
when c_regofst_cal_status => output := read (mmi_regs.ro_regs.cal_status);
-- debug access register
when c_regofst_debug_access =>
if (mmi_regs.enable_writes = '1') then
output := c_mmi_access_codeword;
else
output := (others => '0');
end if;
-- test i/f to check which stages have acknowledged a command and pll checks
when c_regofst_test_status => output := read(mmi_regs.ro_regs.test_status);
-- mode registers
when c_regofst_mr_register_a => output := read(mmi_regs.rw_regs.mr_reg_a);
when c_regofst_mr_register_b => output := read(mmi_regs.rw_regs.mr_reg_b);
-- codvw r/o status register
when c_regofst_codvw_status => output := read(mmi_regs.ro_regs.codvw_status);
-- read/write registers
when c_regofst_hl_css => output := read(mmi_regs.rw_regs.rw_hl_css);
when c_regofst_if_param => output := read(mmi_regs.rw_regs.rw_param_reg);
when c_regofst_if_test => output := read(mmi_regs.rw_regs.rw_if_test);
when others => report regs_report_prefix & "MMI registers detected an attempt to read to non-existant register location" severity warning;
-- set illegal addr interrupt.
end case;
return output;
end function;
function read (signal mmi_regs : in t_mmi_regs;
address : in natural
) return std_logic_vector is
variable output : std_logic_vector(31 downto 0);
variable v_mmi_regs : t_mmi_regs;
begin
v_mmi_regs := mmi_regs;
output := v_read(v_mmi_regs, address);
return output;
end function;
procedure write (mmi_regs : inout t_mmi_regs;
address : in natural;
wdata : in std_logic_vector(31 downto 0)) is
begin
-- intercept writes to codeword. This needs to be set for iRAM access :
if address = c_regofst_debug_access then
if wdata = c_mmi_access_codeword then
mmi_regs.enable_writes := '1';
else
mmi_regs.enable_writes := '0';
end if;
else
case address is
-- read only registers
when c_regofst_cal_status |
c_regofst_codvw_status |
c_regofst_test_status =>
report regs_report_prefix & "MMI registers detected an attempt to write to read only register number" & integer'image(address) severity failure;
-- read/write registers
when c_regofst_mr_register_a => mmi_regs.rw_regs.mr_reg_a := write(wdata);
when c_regofst_mr_register_b => mmi_regs.rw_regs.mr_reg_b := write(wdata);
when c_regofst_hl_css => mmi_regs.rw_regs.rw_hl_css := write(wdata);
when c_regofst_if_param => mmi_regs.rw_regs.rw_param_reg := write(wdata);
when c_regofst_if_test => mmi_regs.rw_regs.rw_if_test := write(wdata);
when others => -- set illegal addr interrupt.
report regs_report_prefix & "MMI registers detected an attempt to write to non existant register, with expected number" & integer'image(address) severity failure;
end case;
end if;
end procedure;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- the following functions enable register data to be communicated to other sequencer blocks
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function pack_record ( ip_regs : t_rw_regs
) return t_algm_paramaterisation is
variable output : t_algm_paramaterisation;
begin
-- default assignments
output.num_phases_per_tck_pll := 16;
output.pll_360_sweeps := 1;
output.nominal_dqs_delay := 2;
output.nominal_poa_phase_lead := 1;
output.maximum_poa_delay := 5;
output.odt_enabled := false;
output.num_phases_per_tck_pll := to_integer(unsigned(ip_regs.rw_param_reg.num_phases_per_tck_pll)) * 8;
case ip_regs.rw_param_reg.nominal_dqs_delay is
when "010" => output.nominal_dqs_delay := 2;
when "001" => output.nominal_dqs_delay := 1;
when "000" => output.nominal_dqs_delay := 0;
when "011" => output.nominal_dqs_delay := 3;
when others => report regs_report_prefix &
"there is a unsupported number of DQS taps (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_dqs_delay))) &
") being advertised as the standard value" severity error;
end case;
case ip_regs.rw_param_reg.nominal_poa_phase_lead is
when "0001" => output.nominal_poa_phase_lead := 1;
when "0010" => output.nominal_poa_phase_lead := 2;
when "0011" => output.nominal_poa_phase_lead := 3;
when "0000" => output.nominal_poa_phase_lead := 0;
when others => report regs_report_prefix &
"there is an unsupported nominal postamble phase lead paramater set (" &
natural'image(to_integer(unsigned(ip_regs.rw_param_reg.nominal_poa_phase_lead))) &
")" severity error;
end case;
if ( (ip_regs.mr_reg_a.mr1(2) = '1')
or (ip_regs.mr_reg_a.mr1(6) = '1')
or (ip_regs.mr_reg_a.mr1(9) = '1')
) then
output.odt_enabled := true;
end if;
output.pll_360_sweeps := to_integer(unsigned(ip_regs.rw_param_reg.pll_360_sweeps));
output.maximum_poa_delay := to_integer(unsigned(ip_regs.rw_param_reg.maximum_poa_delay));
output.extend_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.extend_octrt_by));
output.delay_octrt_by := to_integer(unsigned(ip_regs.rw_param_reg.delay_octrt_by));
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_pll_reconfig is
variable output : t_mmi_pll_reconfig;
begin
output.pll_phs_shft_phase_sel := ip_regs.rw_if_test.pll_phs_shft_phase_sel;
output.pll_phs_shft_up_wc := ip_regs.rw_if_test.pll_phs_shft_up_wc;
output.pll_phs_shft_dn_wc := ip_regs.rw_if_test.pll_phs_shft_dn_wc;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_admin_ctrl is
variable output : t_admin_ctrl := defaults;
begin
output.mr0 := ip_regs.mr_reg_a.mr0;
output.mr1 := ip_regs.mr_reg_a.mr1;
output.mr2 := ip_regs.mr_reg_b.mr2;
output.mr3 := ip_regs.mr_reg_b.mr3;
return output;
end function;
function pack_record (ip_regs : t_rw_regs) return t_mmi_ctrl is
variable output : t_mmi_ctrl := defaults;
begin
output.hl_css := to_t_hl_css_reg (ip_regs.rw_hl_css);
output.calibration_start := ip_regs.rw_hl_css.cal_start;
output.tracking_period_ms := to_integer(unsigned(ip_regs.rw_if_test.tracking_period_ms));
output.tracking_orvd_to_10ms := ip_regs.rw_if_test.tracking_units_are_10us;
return output;
end function;
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
-- Helper functions :
-- >>>>>>>>>>>>>>>>>>>>>>>>>>
function to_t_hl_css_reg (hl_css : t_hl_css
) return t_hl_css_reg is
variable output : t_hl_css_reg := defaults;
begin
output.phy_initialise_dis := hl_css.hl_css(c_hl_css_reg_phy_initialise_dis_bit);
output.init_dram_dis := hl_css.hl_css(c_hl_css_reg_init_dram_dis_bit);
output.write_ihi_dis := hl_css.hl_css(c_hl_css_reg_write_ihi_dis_bit);
output.cal_dis := hl_css.hl_css(c_hl_css_reg_cal_dis_bit);
output.write_btp_dis := hl_css.hl_css(c_hl_css_reg_write_btp_dis_bit);
output.write_mtp_dis := hl_css.hl_css(c_hl_css_reg_write_mtp_dis_bit);
output.read_mtp_dis := hl_css.hl_css(c_hl_css_reg_read_mtp_dis_bit);
output.rrp_reset_dis := hl_css.hl_css(c_hl_css_reg_rrp_reset_dis_bit);
output.rrp_sweep_dis := hl_css.hl_css(c_hl_css_reg_rrp_sweep_dis_bit);
output.rrp_seek_dis := hl_css.hl_css(c_hl_css_reg_rrp_seek_dis_bit);
output.rdv_dis := hl_css.hl_css(c_hl_css_reg_rdv_dis_bit);
output.poa_dis := hl_css.hl_css(c_hl_css_reg_poa_dis_bit);
output.was_dis := hl_css.hl_css(c_hl_css_reg_was_dis_bit);
output.adv_rd_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_rd_lat_dis_bit);
output.adv_wr_lat_dis := hl_css.hl_css(c_hl_css_reg_adv_wr_lat_dis_bit);
output.prep_customer_mr_setup_dis := hl_css.hl_css(c_hl_css_reg_prep_customer_mr_setup_dis_bit);
output.tracking_dis := hl_css.hl_css(c_hl_css_reg_tracking_dis_bit);
return output;
end function;
-- pack the ack seen record element into a std_logic_vector
function pack_ack_seen ( cal_stage_ack_seen : in t_cal_stage_ack_seen
) return std_logic_vector is
variable v_output: std_logic_vector(c_hl_ccs_num_stages-1 downto 0);
variable v_start : natural range 0 to c_hl_ccs_num_stages-1;
begin
v_output := (others => '0');
v_output(c_hl_css_reg_cal_dis_bit ) := cal_stage_ack_seen.cal;
v_output(c_hl_css_reg_phy_initialise_dis_bit ) := cal_stage_ack_seen.phy_initialise;
v_output(c_hl_css_reg_init_dram_dis_bit ) := cal_stage_ack_seen.init_dram;
v_output(c_hl_css_reg_write_ihi_dis_bit ) := cal_stage_ack_seen.write_ihi;
v_output(c_hl_css_reg_write_btp_dis_bit ) := cal_stage_ack_seen.write_btp;
v_output(c_hl_css_reg_write_mtp_dis_bit ) := cal_stage_ack_seen.write_mtp;
v_output(c_hl_css_reg_read_mtp_dis_bit ) := cal_stage_ack_seen.read_mtp;
v_output(c_hl_css_reg_rrp_reset_dis_bit ) := cal_stage_ack_seen.rrp_reset;
v_output(c_hl_css_reg_rrp_sweep_dis_bit ) := cal_stage_ack_seen.rrp_sweep;
v_output(c_hl_css_reg_rrp_seek_dis_bit ) := cal_stage_ack_seen.rrp_seek;
v_output(c_hl_css_reg_rdv_dis_bit ) := cal_stage_ack_seen.rdv;
v_output(c_hl_css_reg_poa_dis_bit ) := cal_stage_ack_seen.poa;
v_output(c_hl_css_reg_was_dis_bit ) := cal_stage_ack_seen.was;
v_output(c_hl_css_reg_adv_rd_lat_dis_bit ) := cal_stage_ack_seen.adv_rd_lat;
v_output(c_hl_css_reg_adv_wr_lat_dis_bit ) := cal_stage_ack_seen.adv_wr_lat;
v_output(c_hl_css_reg_prep_customer_mr_setup_dis_bit) := cal_stage_ack_seen.prep_customer_mr_setup;
v_output(c_hl_css_reg_tracking_dis_bit ) := cal_stage_ack_seen.tracking_setup;
return v_output;
end function;
-- reg encoding of current stage
function encode_current_stage (ctrl_cmd_id : t_ctrl_cmd_id
) return std_logic_vector is
variable output : std_logic_vector(7 downto 0);
begin
case ctrl_cmd_id is
when cmd_idle => output := X"00";
when cmd_phy_initialise => output := X"01";
when cmd_init_dram |
cmd_prog_cal_mr => output := X"02";
when cmd_write_ihi => output := X"03";
when cmd_write_btp => output := X"04";
when cmd_write_mtp => output := X"05";
when cmd_read_mtp => output := X"06";
when cmd_rrp_reset => output := X"07";
when cmd_rrp_sweep => output := X"08";
when cmd_rrp_seek => output := X"09";
when cmd_rdv => output := X"0A";
when cmd_poa => output := X"0B";
when cmd_was => output := X"0C";
when cmd_prep_adv_rd_lat => output := X"0D";
when cmd_prep_adv_wr_lat => output := X"0E";
when cmd_prep_customer_mr_setup => output := X"0F";
when cmd_tr_due => output := X"10";
when others =>
null;
report regs_report_prefix & "unknown cal command (" & t_ctrl_cmd_id'image(ctrl_cmd_id) & ") seen in encode_current_stage function" severity failure;
end case;
return output;
end function;
-- reg encoding of current active block
function encode_active_block (active_block : t_ctrl_active_block
) return std_logic_vector is
variable output : std_logic_vector(3 downto 0);
begin
case active_block is
when idle => output := X"0";
when admin => output := X"1";
when dgwb => output := X"2";
when dgrb => output := X"3";
when proc => output := X"4";
when setup => output := X"5";
when iram => output := X"6";
when others =>
output := X"7";
report regs_report_prefix & "unknown active_block seen in encode_active_block function" severity failure;
end case;
return output;
end function;
--
end ddr2_phy_alt_mem_phy_regs_pkg;
--
-- -----------------------------------------------------------------------------
-- Abstract : mmi block for the non-levelling AFI PHY sequencer
-- This is an optional block with an Avalon interface and status
-- register instantiations to enhance the debug capabilities of
-- the sequencer. The format of the block is:
-- a) an Avalon interface which supports different avalon and
-- sequencer clock sources
-- b) mmi status registers (which hold information about the
-- successof the calibration)
-- c) a read interface to the iram to enable debug through the
-- avalon interface.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
--
entity ddr2_phy_alt_mem_phy_mmi is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DQS_CAPTURE : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural;
AV_IF_ADDR_WIDTH : natural;
MEM_IF_MEMTYPE : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : std_logic_vector(15 downto 0);
PHY_DEF_MR_2ND : std_logic_vector(15 downto 0);
PHY_DEF_MR_3RD : std_logic_vector(15 downto 0);
PHY_DEF_MR_4TH : std_logic_vector(15 downto 0);
PRESET_RLAT : natural; -- read latency preset value
CAPABILITIES : natural; -- sequencer capabilities flags
USE_IRAM : std_logic; -- RFU
IRAM_AWIDTH : natural;
TRACKING_INTERVAL_IN_MS : natural;
READ_LAT_WIDTH : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock)
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH -1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic;
-- mmi to admin interface
regs_admin_ctrl : out t_admin_ctrl;
admin_regs_status : in t_admin_stat;
trefi_failure : in std_logic;
-- mmi to iram interface
mmi_iram : out t_iram_ctrl;
mmi_iram_enable_writes : out std_logic;
iram_status : in t_iram_stat;
-- mmi to control interface
mmi_ctrl : out t_mmi_ctrl;
ctrl_mmi : in t_ctrl_mmi;
int_ac_1t : in std_logic;
invert_ac_1t : out std_logic;
-- global parameterisation record
parameterisation_rec : out t_algm_paramaterisation;
-- mmi pll interface
pll_mmi : in t_pll_mmi;
mmi_pll : out t_mmi_pll_reconfig;
-- codvw status signals
dgrb_mmi : in t_dgrb_mmi
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr2_phy_alt_mem_phy_regs_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr2_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr2_phy_alt_mem_phy_mmi IS
-- maximum function
function max (a, b : natural) return natural is
begin
if a > b then
return a;
else
return b;
end if;
end function;
-- -------------------------------------------
-- constant definitions
-- -------------------------------------------
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE);
constant c_response_lat : natural := 6;
constant c_codeword : std_logic_vector(31 downto 0) := c_mmi_access_codeword;
constant c_int_iram_start_size : natural := max(IRAM_AWIDTH, 4);
-- enable for ctrl state machine states
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(CAPABILITIES, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
-- a prefix for all report signals to identify phy and sequencer block
--
constant mmi_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (mmi) : ";
-- --------------------------------------------
-- internal signals
-- --------------------------------------------
-- internal clock domain register interface signals
signal int_wdata : std_logic_vector(31 downto 0);
signal int_rdata : std_logic_vector(31 downto 0);
signal int_address : std_logic_vector(AV_IF_ADDR_WIDTH-1 downto 0);
signal int_read : std_logic;
signal int_cs : std_logic;
signal int_write : std_logic;
signal waitreq_int : std_logic;
-- register storage
-- contains:
-- read only (ro_regs)
-- read/write (rw_regs)
-- enable_writes flag
signal mmi_regs : t_mmi_regs := defaults;
signal mmi_rw_regs_initialised : std_logic;
-- this counter ensures that the mmi waits for c_response_lat clocks before
-- responding to a new Avalon request
signal waitreq_count : natural range 0 to 15;
signal waitreq_count_is_zero : std_logic;
-- register error signals
signal int_ac_1t_r : std_logic;
signal trefi_failure_r : std_logic;
-- iram ready - calibration complete and USE_IRAM high
signal iram_ready : std_logic;
begin -- architecture struct
-- the following signals are reserved for future use
invert_ac_1t <= '0';
-- --------------------------------------------------------------
-- generate for synchronous avalon interface
-- --------------------------------------------------------------
simply_registered_avalon : if RESYNCHRONISE_AVALON_DBG = 0 generate
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
elsif rising_edge(clk) then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= dbg_seq_cs;
end if;
end process;
seq_dbg_rd_data <= int_rdata;
seq_dbg_waitrequest <= waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate simply_registered_avalon;
-- --------------------------------------------------------------
-- clock domain crossing for asynchronous mmi interface
-- --------------------------------------------------------------
re_synchronise_avalon : if RESYNCHRONISE_AVALON_DBG = 1 generate
--clock domain crossing signals
signal ccd_new_cmd : std_logic;
signal ccd_new_cmd_ack : std_logic;
signal ccd_cmd_done : std_logic;
signal ccd_cmd_done_ack : std_logic;
signal ccd_rd_data : std_logic_vector(dbg_seq_wr_data'range);
signal ccd_cmd_done_ack_t : std_logic;
signal ccd_cmd_done_ack_2t : std_logic;
signal ccd_cmd_done_ack_3t : std_logic;
signal ccd_cmd_done_t : std_logic;
signal ccd_cmd_done_2t : std_logic;
signal ccd_cmd_done_3t : std_logic;
signal ccd_new_cmd_t : std_logic;
signal ccd_new_cmd_2t : std_logic;
signal ccd_new_cmd_3t : std_logic;
signal ccd_new_cmd_ack_t : std_logic;
signal ccd_new_cmd_ack_2t : std_logic;
signal ccd_new_cmd_ack_3t : std_logic;
signal cmd_pending : std_logic;
signal seq_clk_waitreq_int : std_logic;
begin
process (rst_n, clk)
begin
if rst_n = '0' then
int_wdata <= (others => '0');
int_address <= (others => '0');
int_read <= '0';
int_write <= '0';
int_cs <= '0';
ccd_new_cmd_ack <= '0';
ccd_new_cmd_t <= '0';
ccd_new_cmd_2t <= '0';
ccd_new_cmd_3t <= '0';
elsif rising_edge(clk) then
ccd_new_cmd_t <= ccd_new_cmd;
ccd_new_cmd_2t <= ccd_new_cmd_t;
ccd_new_cmd_3t <= ccd_new_cmd_2t;
if ccd_new_cmd_3t = '0' and ccd_new_cmd_2t = '1' then
int_wdata <= dbg_seq_wr_data;
int_address <= dbg_seq_addr;
int_read <= dbg_seq_rd;
int_write <= dbg_seq_wr;
int_cs <= '1';
ccd_new_cmd_ack <= '1';
elsif ccd_new_cmd_3t = '1' and ccd_new_cmd_2t = '0' then
ccd_new_cmd_ack <= '0';
end if;
if int_cs = '1' and waitreq_int= '0' then
int_cs <= '0';
int_read <= '0';
int_write <= '0';
end if;
end if;
end process;
-- process to generate new cmd
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_new_cmd <= '0';
ccd_new_cmd_ack_t <= '0';
ccd_new_cmd_ack_2t <= '0';
ccd_new_cmd_ack_3t <= '0';
cmd_pending <= '0';
elsif rising_edge(dbg_seq_clk) then
ccd_new_cmd_ack_t <= ccd_new_cmd_ack;
ccd_new_cmd_ack_2t <= ccd_new_cmd_ack_t;
ccd_new_cmd_ack_3t <= ccd_new_cmd_ack_2t;
if ccd_new_cmd = '0' and dbg_seq_cs = '1' and cmd_pending = '0' then
ccd_new_cmd <= '1';
cmd_pending <= '1';
elsif ccd_new_cmd_ack_2t = '1' and ccd_new_cmd_ack_3t = '0' then
ccd_new_cmd <= '0';
end if;
-- use falling edge of cmd_done
if cmd_pending = '1' and ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
cmd_pending <= '0';
end if;
end if;
end process;
-- process to take read data back and transfer it across the clock domains
process (rst_n, clk)
begin
if rst_n = '0' then
ccd_cmd_done <= '0';
ccd_rd_data <= (others => '0');
ccd_cmd_done_ack_3t <= '0';
ccd_cmd_done_ack_2t <= '0';
ccd_cmd_done_ack_t <= '0';
elsif rising_edge(clk) then
if ccd_cmd_done_ack_2t = '1' and ccd_cmd_done_ack_3t = '0' then
ccd_cmd_done <= '0';
elsif waitreq_int = '0' then
ccd_cmd_done <= '1';
ccd_rd_data <= int_rdata;
end if;
ccd_cmd_done_ack_3t <= ccd_cmd_done_ack_2t;
ccd_cmd_done_ack_2t <= ccd_cmd_done_ack_t;
ccd_cmd_done_ack_t <= ccd_cmd_done_ack;
end if;
end process;
process (dbg_seq_rst_n, dbg_seq_clk)
begin
if dbg_seq_rst_n = '0' then
ccd_cmd_done_ack <= '0';
ccd_cmd_done_3t <= '0';
ccd_cmd_done_2t <= '0';
ccd_cmd_done_t <= '0';
seq_dbg_rd_data <= (others => '0');
seq_clk_waitreq_int <= '1';
elsif rising_edge(dbg_seq_clk) then
seq_clk_waitreq_int <= '1';
if ccd_cmd_done_2t = '1' and ccd_cmd_done_3t = '0' then
seq_clk_waitreq_int <= '0';
ccd_cmd_done_ack <= '1';
seq_dbg_rd_data <= ccd_rd_data; -- if read
elsif ccd_cmd_done_2t = '0' and ccd_cmd_done_3t = '1' then
ccd_cmd_done_ack <= '0';
end if;
ccd_cmd_done_3t <= ccd_cmd_done_2t;
ccd_cmd_done_2t <= ccd_cmd_done_t;
ccd_cmd_done_t <= ccd_cmd_done;
end if;
end process;
seq_dbg_waitrequest <= seq_clk_waitreq_int and (dbg_seq_rd or dbg_seq_wr) and dbg_seq_cs;
end generate re_synchronise_avalon;
-- register some inputs for speed.
process (rst_n, clk)
begin
if rst_n = '0' then
int_ac_1t_r <= '0';
trefi_failure_r <= '0';
elsif rising_edge(clk) then
int_ac_1t_r <= int_ac_1t;
trefi_failure_r <= trefi_failure;
end if;
end process;
-- mmi not able to write to iram in current instance of mmi block
mmi_iram_enable_writes <= '0';
-- check if iram ready
process (rst_n, clk)
begin
if rst_n = '0' then
iram_ready <= '0';
elsif rising_edge(clk) then
if USE_IRAM = '0' then
iram_ready <= '0';
else
if ctrl_mmi.ctrl_calibration_success = '1' or ctrl_mmi.ctrl_calibration_fail = '1' then
iram_ready <= '1';
else
iram_ready <= '0';
end if;
end if;
end if;
end process;
-- --------------------------------------------------------------
-- single registered process for mmi access.
-- --------------------------------------------------------------
process (rst_n, clk)
variable v_mmi_regs : t_mmi_regs;
begin
if rst_n = '0' then
mmi_regs <= defaults;
mmi_rw_regs_initialised <= '0';
-- this register records whether the c_codeword has been written to address 0x0001
-- once it has, then other writes are accepted.
mmi_regs.enable_writes <= '0';
int_rdata <= (others => '0');
waitreq_int <= '1';
-- clear wait request counter
waitreq_count <= 0;
waitreq_count_is_zero <= '1';
-- iram interface defaults
mmi_iram <= defaults;
elsif rising_edge(clk) then
-- default assignment
waitreq_int <= '1';
write_clear(mmi_regs.rw_regs);
-- only initialise rw_regs once after hard reset
if mmi_rw_regs_initialised = '0' then
mmi_rw_regs_initialised <= '1';
--reset all read/write regs and read path ouput registers and apply default MRS Settings.
mmi_regs.rw_regs <= defaults(PHY_DEF_MR_1ST,
PHY_DEF_MR_2ND,
PHY_DEF_MR_3RD,
PHY_DEF_MR_4TH,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps, -- number of times 360 degrees is swept
TRACKING_INTERVAL_IN_MS,
c_hl_stage_enable);
end if;
-- bit packing input data structures into the ro_regs structure, for reading
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
USE_IRAM,
MEM_IF_DQS_CAPTURE,
int_ac_1t_r,
trefi_failure_r,
iram_status,
IRAM_AWIDTH);
-- write has priority over read
if int_write = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register write
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
v_mmi_regs := mmi_regs;
write(v_mmi_regs, to_integer(unsigned(int_address(3 downto 0))), int_wdata);
if mmi_regs.enable_writes = '1' then
v_mmi_regs.rw_regs.rw_hl_css.hl_css := c_hl_stage_enable or v_mmi_regs.rw_regs.rw_hl_css.hl_css;
end if;
mmi_regs <= v_mmi_regs;
-- handshake for safe transactions
waitreq_int <= '0';
waitreq_count <= c_response_lat;
-- iram write just handshake back (no write supported)
else
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif int_read = '1' and int_cs = '1' and waitreq_count_is_zero = '1' and waitreq_int = '1' then
-- mmi local register read
if to_integer(unsigned(int_address(int_address'high downto 4))) = 0 then
int_rdata <= read(mmi_regs, to_integer(unsigned(int_address(3 downto 0))));
waitreq_count <= c_response_lat;
waitreq_int <= '0'; -- acknowledge read command regardless.
-- iram being addressed
elsif to_integer(unsigned(int_address(int_address'high downto c_int_iram_start_size))) = 1
and iram_ready = '1'
then
mmi_iram.read <= '1';
mmi_iram.addr <= to_integer(unsigned(int_address(IRAM_AWIDTH -1 downto 0)));
if iram_status.done = '1' then
waitreq_int <= '0';
mmi_iram.read <= '0';
waitreq_count <= c_response_lat;
int_rdata <= iram_status.rdata;
end if;
else -- respond and keep the interface from hanging
int_rdata <= x"DEADBEEF";
waitreq_int <= '0';
waitreq_count <= c_response_lat;
end if;
elsif waitreq_count /= 0 then
waitreq_count <= waitreq_count -1;
-- if performing a write, set back to defaults. If not, default anyway
mmi_iram <= defaults;
end if;
if waitreq_count = 1 or waitreq_count = 0 then
waitreq_count_is_zero <= '1'; -- as it will be next clock cycle
else
waitreq_count_is_zero <= '0';
end if;
-- supply iram read data when ready
if iram_status.done = '1' then
int_rdata <= iram_status.rdata;
end if;
end if;
end process;
-- pack the registers into the output data structures
regs_admin_ctrl <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : admin block for the non-levelling AFI PHY sequencer
-- The admin block supports the autonomy of the sequencer from
-- the memory interface controller. In this task admin handles
-- memory initialisation (incl. the setting of mode registers)
-- and memory refresh, bank activation and pre-charge commands
-- (during memory interface calibration). Once calibration is
-- complete admin is 'idle' and control of the memory device is
-- passed to the users chosen memory interface controller. The
-- supported memory types are exclusively DDR, DDR2 and DDR3.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr2_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr2_phy_alt_mem_phy_admin is
generic (
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
ADV_LAT_WIDTH : natural;
MEM_IF_DQSN_EN : natural;
MEM_IF_MEMTYPE : string;
-- calibration address information
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
MEM_IF_CAL_BASE_ROW : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
NON_OP_EVAL_MD : string; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
-- timing parameters
MEM_IF_CLK_PS : natural;
TINIT_TCK : natural; -- initial delay
TINIT_RST : natural -- used for DDR3 device support
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- the 2 signals below are unused for non-levelled sequencer (maintained for equivalent interface to levelled sequencer)
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- addr/cmd interface
seq_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
seq_ac_sel : out std_logic;
-- determined from MR settings
enable_odt : out std_logic;
-- interface to the mmi block
regs_admin_ctrl_rec : in t_admin_ctrl;
admin_regs_status_rec : out t_admin_stat;
trefi_failure : out std_logic;
-- interface to the ctrl block
ctrl_admin : in t_ctrl_command;
admin_ctrl : out t_ctrl_stat;
-- interface with dgrb/dgwb blocks
ac_access_req : in std_logic;
ac_access_gnt : out std_logic;
-- calibration status signals (from ctrl block)
cal_fail : in std_logic;
cal_success : in std_logic;
-- recalibrate request issued
ctl_recalibrate_req : in std_logic
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr2_phy_alt_mem_phy_admin is
constant c_max_mode_reg_index : natural := 12;
-- timing below is safe for range 80-400MHz operation - taken from worst case DDR2 (JEDEC JESD79-2E) / DDR3 (JESD79-3B)
-- Note: timings account for worst case use for both full rate and half rate ALTMEMPHY interfaces
constant c_init_prech_delay : natural := 162; -- precharge delay (360ns = tRFC+10ns) (TXPR for DDR3)
constant c_trp_in_clks : natural := 8; -- set equal to trp / tck (trp = 15ns)
constant c_tmrd_in_clks : natural := 4; -- maximum 4 clock cycles (DDR3)
constant c_tmod_in_clks : natural := 8; -- ODT update from MRS command (tmod = 12ns (DDR2))
constant c_trrd_min_in_clks : natural := 4; -- minimum clk cycles between bank activate cmds (10ns)
constant c_trcd_min_in_clks : natural := 8; -- minimum bank activate to read/write cmd (15ns)
-- the 2 constants below are parameterised to MEM_IF_CLK_PS due to the large range of possible clock frequency
constant c_trfc_min_in_clks : natural := (350000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) + 2; -- refresh-refresh timing (worst case trfc = 350 ns (DDR3))
constant c_trefi_min_in_clks : natural := (3900000/MEM_IF_CLK_PS)/(DWIDTH_RATIO/2) - 2; -- average refresh interval worst case trefi = 3.9 us (industrial grade devices)
constant c_max_num_stacked_refreshes : natural := 8; -- max no. of stacked refreshes allowed
constant c_max_wait_value : natural := 4; -- delay before moving from s_idle to s_refresh_state
-- DDR3 specific:
constant c_zq_init_duration_clks : natural := 514; -- full rate (worst case) cycle count for tZQCL init
constant c_tzqcs : natural := 66; -- number of full rate clock cycles
-- below is a record which is used to parameterise the address and command signals (addr_cmd) used in this block
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant admin_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (admin) : ";
-- state type for admin_state (main state machine of admin block)
type t_admin_state is
(
s_reset, -- reset state
s_run_init_seq, -- run the initialisation sequence (up to but not including MR setting)
s_program_cal_mrs, -- program the mode registers ready for calibration (this is the user settings
-- with some overloads and extra init functionality)
s_idle, -- idle (i.e. maintaining refresh to max)
s_topup_refresh, -- make sure refreshes are maxed out before going on.
s_topup_refresh_done, -- wait for tRFC after refresh command
s_zq_cal_short, -- ZQCAL short command (issued prior to activate) - DDR3 only
s_access_act, -- activate
s_access, -- dgrb, dgwb accesses,
s_access_precharge, -- precharge all memory banks
s_prog_user_mrs, -- program user mode register settings
s_dummy_wait, -- wait before going to s_refresh state
s_refresh, -- issue a memory refresh command
s_refresh_done, -- wait for trfc after refresh command
s_non_operational -- special debug state to toggle interface if calibration fails
);
signal state : t_admin_state; -- admin block state machine
-- state type for ac_state
type t_ac_state is
( s_0 ,
s_1 ,
s_2 ,
s_3 ,
s_4 ,
s_5 ,
s_6 ,
s_7 ,
s_8 ,
s_9 ,
s_10,
s_11,
s_12,
s_13,
s_14);
-- enforce one-hot fsm encoding
attribute syn_encoding : string;
attribute syn_encoding of t_ac_state : TYPE is "one-hot";
signal ac_state : t_ac_state; -- state machine for sub-states of t_admin_state states
signal stage_counter : natural range 0 to 2**18 - 1; -- counter to support memory timing delays
signal stage_counter_zero : std_logic;
signal addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1); -- internal copy of output DRAM addr/cmd signals
signal mem_init_complete : std_logic; -- signifies memory initialisation is complete
signal cal_complete : std_logic; -- calibration complete (equals: cal_success OR cal_fail)
signal int_mr0 : std_logic_vector(regs_admin_ctrl_rec.mr0'range); -- an internal copy of mode register settings
signal int_mr1 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr2 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal int_mr3 : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
signal refresh_count : natural range c_trefi_min_in_clks downto 0; -- determine when refresh is due
signal refresh_due : std_logic; -- need to do a refresh now
signal refresh_done : std_logic; -- pulse when refresh complete
signal num_stacked_refreshes : natural range 0 to c_max_num_stacked_refreshes - 1; -- can stack upto 8 refreshes (for DDR2)
signal refreshes_maxed : std_logic; -- signal refreshes are maxed out
signal initial_refresh_issued : std_logic; -- to start the refresh counter off
signal ctrl_rec : t_ctrl_command;
-- last state logic
signal command_started : std_logic; -- provides a pulse when admin starts processing a command
signal command_done : std_logic; -- provides a pulse when admin completes processing a command is completed
signal finished_state : std_logic; -- finished current t_admin_state state
signal admin_req_extended : std_logic; -- keep requests for this block asserted until it is an ack is asserted
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1; -- which chip select being programmed at this instance
signal per_cs_init_seen : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- some signals to enable non_operational debug (optimised away if GENERATE_ADDITIONAL_DBG_RTL = 0)
signal nop_toggle_signal : t_addr_cmd_signals;
signal nop_toggle_pin : natural range 0 to MEM_IF_ADDR_WIDTH - 1; -- track which pin in a signal to toggle
signal nop_toggle_value : std_logic;
begin -- architecture struct
-- concurrent assignment of internal addr_cmd to output port seq_ac
process (addr_cmd)
begin
seq_ac <= addr_cmd;
end process;
-- generate calibration complete signal
process (cal_success, cal_fail)
begin
cal_complete <= cal_success or cal_fail;
end process;
-- register the control command record
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_rec <= defaults;
elsif rising_edge(clk) then
ctrl_rec <= ctrl_admin;
end if;
end process;
-- extend the admin block request until ack is asserted
process (clk, rst_n)
begin
if rst_n = '0' then
admin_req_extended <= '0';
elsif rising_edge(clk) then
if ( (ctrl_rec.command_req = '1') and ( curr_active_block(ctrl_rec.command) = admin) ) then
admin_req_extended <= '1';
elsif command_started = '1' then -- this is effectively a copy of command_ack generation
admin_req_extended <= '0';
end if;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if ctrl_rec.command_req = '1' then
current_cs <= ctrl_rec.command_op.current_cs;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- refresh logic: DDR/DDR2/DDR3 allows upto 8 refreshes to be "stacked" or queued up.
-- In the idle state, will ensure refreshes are issued when necessary. Then,
-- when an access_request is received, 7 topup refreshes will be done to max out
-- the number of queued refreshes. That way, we know we have the maximum time
-- available before another refresh is due.
-- -----------------------------------------------------------------------------
-- initial_refresh_issued flag: used to sync refresh_count
process (clk, rst_n)
begin
if rst_n = '0' then
initial_refresh_issued <= '0';
elsif rising_edge(clk) then
if cal_complete = '1' then
initial_refresh_issued <= '0';
else
if state = s_refresh_done or
state = s_topup_refresh_done then
initial_refresh_issued <= '1';
end if;
end if;
end if;
end process;
-- refresh timer: used to work out when a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_count <= c_trefi_min_in_clks;
elsif rising_edge(clk) then
if cal_complete = '1' then
refresh_count <= c_trefi_min_in_clks;
else
if refresh_count = 0 or
initial_refresh_issued = '0' or
(refreshes_maxed = '1' and refresh_done = '1') then -- if refresh issued when already maxed
refresh_count <= c_trefi_min_in_clks;
else
refresh_count <= refresh_count - 1;
end if;
end if;
end if;
end process;
-- refresh_due generation: 1 cycle pulse to indicate that c_trefi_min_in_clks has elapsed, and
-- therefore a refresh is due
process (clk, rst_n)
begin
if rst_n = '0' then
refresh_due <= '0';
elsif rising_edge(clk) then
if refresh_count = 0 and cal_complete = '0' then
refresh_due <= '1';
else
refresh_due <= '0';
end if;
end if;
end process;
-- counter to keep track of number of refreshes "stacked". NB: Up to 8
-- refreshes can be stacked.
process (clk, rst_n)
begin
if rst_n = '0' then
num_stacked_refreshes <= 0;
trefi_failure <= '0'; -- default no trefi failure
elsif rising_edge (clk) then
if state = s_reset then
trefi_failure <= '0'; -- default no trefi failure (in restart)
end if;
if cal_complete = '1' then
num_stacked_refreshes <= 0;
else
if refresh_due = '1' and num_stacked_refreshes /= 0 then
num_stacked_refreshes <= num_stacked_refreshes - 1;
elsif refresh_done = '1' and num_stacked_refreshes /= c_max_num_stacked_refreshes - 1 then
num_stacked_refreshes <= num_stacked_refreshes + 1;
end if;
-- debug message if stacked refreshes are depleted and refresh is due
if refresh_due = '1' and num_stacked_refreshes = 0 and initial_refresh_issued = '1' then
report admin_report_prefix & "error refresh is due and num_stacked_refreshes is zero" severity error;
trefi_failure <= '1'; -- persist
end if;
end if;
end if;
end process;
-- generate signal to state if refreshes are maxed out
process (clk, rst_n)
begin
if rst_n = '0' then
refreshes_maxed <= '0';
elsif rising_edge (clk) then
if num_stacked_refreshes < c_max_num_stacked_refreshes - 1 then
refreshes_maxed <= '0';
else
refreshes_maxed <= '1';
end if;
end if;
end process;
-- ----------------------------------------------------
-- Mode register selection
-- -----------------------------------------------------
int_mr0(regs_admin_ctrl_rec.mr0'range) <= regs_admin_ctrl_rec.mr0;
int_mr1(regs_admin_ctrl_rec.mr1'range) <= regs_admin_ctrl_rec.mr1;
int_mr2(regs_admin_ctrl_rec.mr2'range) <= regs_admin_ctrl_rec.mr2;
int_mr3(regs_admin_ctrl_rec.mr3'range) <= regs_admin_ctrl_rec.mr3;
-- -------------------------------------------------------
-- State machine
-- -------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
state <= s_reset;
command_done <= '0';
command_started <= '0';
elsif rising_edge(clk) then
-- Last state logic
command_done <= '0';
command_started <= '0';
case state is
when s_reset |
s_non_operational =>
if ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then
state <= s_run_init_seq;
command_started <= '1';
end if;
when s_run_init_seq =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_program_cal_mrs =>
if finished_state = '1' then
if refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh if all ranks initialised
state <= s_topup_refresh;
else
state <= s_idle;
end if;
command_done <= '1';
end if;
when s_idle =>
if ac_access_req = '1' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_init_dram and admin_req_extended = '1' then -- start initialisation sequence
state <= s_run_init_seq;
command_started <= '1';
elsif ctrl_rec.command = cmd_prog_cal_mr and admin_req_extended = '1' then -- program mode registers (used for >1 chip select)
state <= s_program_cal_mrs;
command_started <= '1';
-- always enter s_prog_user_mrs via topup refresh
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_topup_refresh;
elsif refreshes_maxed = '0' and mem_init_complete = '1' then -- only refresh once all ranks initialised
state <= s_dummy_wait;
end if;
when s_dummy_wait =>
if finished_state = '1' then
state <= s_refresh;
end if;
when s_topup_refresh =>
if finished_state = '1' then
state <= s_topup_refresh_done;
end if;
when s_topup_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_topup_refresh;
elsif ctrl_rec.command = cmd_prep_customer_mr_setup and admin_req_extended = '1' then
state <= s_prog_user_mrs;
command_started <= '1';
elsif ac_access_req = '1' then
if MEM_IF_MEMTYPE = "DDR3" then
state <= s_zq_cal_short;
else
state <= s_access_act;
end if;
else
state <= s_idle;
end if;
end if;
when s_zq_cal_short => -- DDR3 only
if finished_state = '1' then
state <= s_access_act;
end if;
when s_access_act =>
if finished_state = '1' then
state <= s_access;
end if;
when s_access =>
if ac_access_req = '0' then
state <= s_access_precharge;
end if;
when s_access_precharge =>
-- ensure precharge all timer has elapsed.
if finished_state = '1' then
state <= s_idle;
end if;
when s_prog_user_mrs =>
if finished_state = '1' then
state <= s_idle;
command_done <= '1';
end if;
when s_refresh =>
if finished_state = '1' then
state <= s_refresh_done;
end if;
when s_refresh_done =>
if finished_state = '1' then -- to ensure trfc is not violated
if refreshes_maxed = '0' then
state <= s_refresh;
else
state <= s_idle;
end if;
end if;
when others =>
state <= s_reset;
end case;
if cal_complete = '1' then
state <= s_idle;
if GENERATE_ADDITIONAL_DBG_RTL = 1 and cal_success = '0' then
state <= s_non_operational; -- if calibration failed and debug enabled then toggle pins in pre-defined pattern
end if;
end if;
-- if recalibrating then put admin in reset state to
-- avoid issuing refresh commands when not needed
if ctl_recalibrate_req = '1' then
state <= s_reset;
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate initialisation complete
-- --------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
mem_init_complete <= '0';
elsif rising_edge(clk) then
if to_integer(unsigned(per_cs_init_seen)) = 2**MEM_IF_NUM_RANKS - 1 then
mem_init_complete <= '1';
else
mem_init_complete <= '0';
end if;
end if;
end process;
-- --------------------------------------------------
-- process to generate addr/cmd.
-- --------------------------------------------------
process(rst_n, clk)
variable v_mr_overload : std_logic_vector(regs_admin_ctrl_rec.mr0'range);
-- required for non_operational state only
variable v_nop_ac_0 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
variable v_nop_ac_1 : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
ac_state <= s_0;
stage_counter <= 0;
stage_counter_zero <= '1';
finished_state <= '0';
seq_ac_sel <= '1';
refresh_done <= '0';
per_cs_init_seen <= (others => '0');
addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
elsif rising_edge(clk) then
finished_state <= '0';
refresh_done <= '0';
-- address / command path control
-- if seq_ac_sel = 1 then sequencer has control of a/c
-- if seq_ac_sel = 0 then memory controller has control of a/c
seq_ac_sel <= '1';
if cal_complete = '1' then
if cal_success = '1' or
GENERATE_ADDITIONAL_DBG_RTL = 0 then -- hand over interface if cal successful or no debug enabled
seq_ac_sel <= '0';
end if;
end if;
-- if recalibration request then take control of a/c path
if ctl_recalibrate_req = '1' then
seq_ac_sel <= '1';
end if;
if state = s_reset then
addr_cmd <= reset(c_seq_addr_cmd_config);
stage_counter <= 0;
elsif state /= s_run_init_seq and
state /= s_non_operational then
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
end if;
if (stage_counter = 1 or stage_counter = 0) then
stage_counter_zero <= '1';
else
stage_counter_zero <= '0';
end if;
if stage_counter_zero /= '1' and state /= s_reset then
stage_counter <= stage_counter -1;
else
stage_counter_zero <= '0';
case state is
when s_run_init_seq =>
per_cs_init_seen <= (others => '0'); -- per cs test
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
case ac_state is
-- JEDEC (JESD79-2E) stage c
when s_0 to s_9 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10)+1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
-- JEDEC (JESD79-2E) stage d
when s_10 =>
ac_state <= s_11;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_11 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then -- DDR3 specific initialisation sequence
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= TINIT_RST + 1;
addr_cmd <= reset(c_seq_addr_cmd_config);
when s_1 to s_10 =>
ac_state <= t_ac_state'succ(ac_state);
stage_counter <= (TINIT_TCK/10) + 1;
addr_cmd <= maintain_pd_or_sr(c_seq_addr_cmd_config,
deselect(c_seq_addr_cmd_config, addr_cmd),
2**MEM_IF_NUM_RANKS -1);
when s_11 =>
ac_state <= s_12;
stage_counter <= c_init_prech_delay;
addr_cmd <= deselect(c_seq_addr_cmd_config, addr_cmd);
when s_12 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
-- finish sequence by going into s_program_cal_mrs state
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of initialisation sequence
when s_program_cal_mrs =>
if MEM_IF_MEMTYPE = "DDR2" then -- DDR2 style mode register settings
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage d
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage e
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage f
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage g
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
v_mr_overload(9 downto 7) := "000"; -- required in JESD79-2E (but not in JESD79-2B)
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage h
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage i
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
-- JEDEC (JESD79-2E) stage j
when s_7 =>
ac_state <= s_8;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage j - second refresh
when s_8 =>
ac_state <= s_9;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
-- JEDEC (JESD79-2E) stage k
when s_9 =>
ac_state <= s_10;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
v_mr_overload(8) := '0'; -- required in JESD79-2E
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - wait 200 cycles
when s_10 =>
ac_state <= s_11;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
-- JEDEC (JESD79-2E) stage l - OCD default
when s_11 =>
ac_state <= s_12;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "111"; -- OCD calibration default (i.e. OCD unused)
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
-- JEDEC (JESD79-2E) stage l - OCD cal exit
when s_12 =>
ac_state <= s_13;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(9 downto 7) := "000"; -- OCD calibration exit
v_mr_overload(0) := '0'; -- override for DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
per_cs_init_seen(current_cs) <= '1';
-- JEDEC (JESD79-2E) stage m - cal finished
when s_13 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR" then -- DDR style mode register setting following JEDEC (JESD79E)
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- override DLL enable
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload , -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmod_in_clks;
addr_cmd <= dll_reset(c_seq_addr_cmd_config, -- configuration
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_5 =>
ac_state <= s_6;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_6 =>
ac_state <= s_7;
stage_counter <= c_trfc_min_in_clks;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**current_cs); -- rank
when s_7 =>
ac_state <= s_8;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 3) & "010"; -- override to burst length 4
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_8 =>
ac_state <= s_9;
stage_counter <= 200;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
per_cs_init_seen(current_cs) <= '1';
when s_9 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
null;
end case;
elsif MEM_IF_MEMTYPE = "DDR3" then
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trp_in_clks;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
v_mr_overload := int_mr1(c_max_mode_reg_index downto 0);
v_mr_overload(0) := '0'; -- Override for DLL enable
v_mr_overload(12) := '0'; -- output buffer enable.
v_mr_overload(7) := '0'; -- Disable Write levelling
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmod_in_clks;
v_mr_overload := int_mr0(c_max_mode_reg_index downto 0);
v_mr_overload(1 downto 0) := "01"; -- override to on the fly burst length choice
v_mr_overload(7) := '0'; -- test mode not enabled
v_mr_overload(8) := '1'; -- DLL reset
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
v_mr_overload, -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_5 =>
ac_state <= s_6;
stage_counter <= c_zq_init_duration_clks;
addr_cmd <= ZQCL(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- rank
per_cs_init_seen(current_cs) <= '1';
when s_6 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
else
report admin_report_prefix & "unsupported memory type specified" severity error;
end if;
-- end of s_program_cal_mrs case
when s_prog_user_mrs =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
if MEM_IF_MEMTYPE = "DDR" then -- for DDR memory skip MR2/3 because not present
ac_state <= s_4;
else -- for DDR2/DDR3 all MRs programmed
ac_state <= s_2;
end if;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_3;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
2, -- mode register number
int_mr2(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_3 =>
ac_state <= s_4;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
3, -- mode register number
int_mr3(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if to_integer(unsigned(int_mr3)) /= 0 then
report admin_report_prefix & " mode register 3 is expected to have a value of 0 but has a value of : " &
integer'image(to_integer(unsigned(int_mr3))) severity warning;
end if;
when s_4 =>
ac_state <= s_5;
stage_counter <= c_tmrd_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
1, -- mode register number
int_mr1(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
if (MEM_IF_DQSN_EN = 0) and (int_mr1(10) = '0') and (MEM_IF_MEMTYPE = "DDR2") then
report admin_report_prefix & "mode register and generic conflict:" & LF &
"* generic MEM_IF_DQSN_EN is set to 'disable' DQSN" & LF &
"* user mode register MEM_IF_MR1 bit 10 is set to 'enable' DQSN" severity warning;
end if;
when s_5 =>
ac_state <= s_6;
stage_counter <= c_tmod_in_clks;
addr_cmd <= load_mode(c_seq_addr_cmd_config, -- configuration
0, -- mode register number
int_mr0(c_max_mode_reg_index downto 0), -- mode register value
2**current_cs, -- rank
false); -- remap address and bank address
when s_6 =>
ac_state <= s_7;
stage_counter <= 1;
when s_7 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- end of s_prog_user_mr case
when s_access_precharge =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 8;
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trp_in_clks;
addr_cmd <= precharge_all(c_seq_addr_cmd_config, -- configuration
2**MEM_IF_NUM_RANKS - 1); -- rank(s)
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh | s_refresh =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= 1;
addr_cmd <= refresh(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
2**MEM_IF_NUM_RANKS - 1); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_topup_refresh_done | s_refresh_done =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trfc_min_in_clks;
refresh_done <= '1'; -- ensure trfc not violated
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_zq_cal_short =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= 1;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_tzqcs;
addr_cmd <= ZQCS(c_seq_addr_cmd_config, -- configuration
2**current_cs); -- all ranks
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_access_act =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_trrd_min_in_clks;
when s_1 =>
ac_state <= s_2;
stage_counter <= c_trcd_min_in_clks;
addr_cmd <= activate(c_seq_addr_cmd_config, -- configuration
addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_ROW, -- row address
2**current_cs); -- rank
when s_2 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
-- counter to delay transition from s_idle to s_refresh - this is to ensure a refresh command is not sent
-- just as we enter operational state (could cause a trfc violation)
when s_dummy_wait =>
case ac_state is
when s_0 =>
ac_state <= s_1;
stage_counter <= c_max_wait_value;
when s_1 =>
ac_state <= s_0;
stage_counter <= 1;
finished_state <= '1';
when others =>
ac_state <= s_0;
end case;
when s_reset =>
stage_counter <= 1;
-- default some s_non_operational signals
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
nop_toggle_signal <= addr;
nop_toggle_pin <= 0;
nop_toggle_value <= '0';
end if;
when s_non_operational => -- if failed then output a recognised pattern to the memory (Only executes if GENERATE_ADDITIONAL_DBG_RTL set)
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
if NON_OP_EVAL_MD = "PIN_FINDER" then -- toggle pins in turn for 200 memory clk cycles
stage_counter <= 200/(DWIDTH_RATIO/2); -- 200 mem_clk cycles
case nop_toggle_signal is
when addr =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_ADDR_WIDTH-1 then
nop_toggle_signal <= ba;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when ba =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, '0');
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ba, nop_toggle_value, nop_toggle_pin);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
if nop_toggle_pin = MEM_IF_BANKADDR_WIDTH-1 then
nop_toggle_signal <= cas_n;
nop_toggle_pin <= 0;
else
nop_toggle_pin <= nop_toggle_pin + 1;
end if;
end if;
when cas_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, cas_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= ras_n;
end if;
when ras_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, ras_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= we_n;
end if;
when we_n =>
addr_cmd <= mask (c_seq_addr_cmd_config, addr_cmd, we_n, nop_toggle_value);
nop_toggle_value <= not nop_toggle_value;
if nop_toggle_value = '1' then
nop_toggle_signal <= addr;
end if;
when others =>
report admin_report_prefix & " an attempt to toggle a non addr/cmd pin detected" severity failure;
end case;
elsif NON_OP_EVAL_MD = "SI_EVALUATOR" then -- toggle all addr/cmd pins at fmax
stage_counter <= 0; -- every mem_clk cycle
stage_counter_zero <= '1';
v_nop_ac_0 := mask (c_seq_addr_cmd_config, addr_cmd, addr, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ba, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, we_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, ras_n, nop_toggle_value);
v_nop_ac_0 := mask (c_seq_addr_cmd_config, v_nop_ac_0, cas_n, nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, addr_cmd, addr, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ba, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, we_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, ras_n, not nop_toggle_value);
v_nop_ac_1 := mask (c_seq_addr_cmd_config, v_nop_ac_1, cas_n, not nop_toggle_value);
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if i mod 2 = 0 then
addr_cmd(i) <= v_nop_ac_0(i);
else
addr_cmd(i) <= v_nop_ac_1(i);
end if;
end loop;
if DWIDTH_RATIO = 2 then
nop_toggle_value <= not nop_toggle_value;
end if;
else
report admin_report_prefix & "unknown non-operational evaluation mode " & NON_OP_EVAL_MD severity failure;
end if;
when others =>
addr_cmd <= deselect(c_seq_addr_cmd_config, -- configuration
addr_cmd); -- previous value
stage_counter <= 1;
end case;
end if;
end if;
end process;
-- -------------------------------------------------------------------
-- output packing of mode register settings and enabling of ODT
-- -------------------------------------------------------------------
process (int_mr0, int_mr1, int_mr2, int_mr3, mem_init_complete)
begin
admin_regs_status_rec.mr0 <= int_mr0;
admin_regs_status_rec.mr1 <= int_mr1;
admin_regs_status_rec.mr2 <= int_mr2;
admin_regs_status_rec.mr3 <= int_mr3;
admin_regs_status_rec.init_done <= mem_init_complete;
enable_odt <= int_mr1(2) or int_mr1(6); -- if ODT enabled in MR settings (i.e. MR1 bits 2 or 6 /= 0)
end process;
-- --------------------------------------------------------------------------------
-- generation of handshake signals with ctrl, dgrb and dgwb blocks (this includes
-- command ack, command done for ctrl and access grant for dgrb/dgwb)
-- --------------------------------------------------------------------------------
process (rst_n, clk)
begin
if rst_n = '0' then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
elsif rising_edge(clk) then
admin_ctrl <= defaults;
ac_access_gnt <= '0';
admin_ctrl.command_ack <= command_started;
admin_ctrl.command_done <= command_done;
if state = s_access then
ac_access_gnt <= '1';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : inferred ram for the non-levelling AFI PHY sequencer
-- The inferred ram is used in the iram block to store
-- debug information about the sequencer. It is variable in
-- size based on the IRAM_AWIDTH generic and is of size
-- 32 * (2 ** IRAM_ADDR_WIDTH) bits
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
--
entity ddr2_phy_alt_mem_phy_iram_ram IS
generic (
IRAM_AWIDTH : natural
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- ram ports
addr : in unsigned(IRAM_AWIDTH-1 downto 0);
wdata : in std_logic_vector(31 downto 0);
write : in std_logic;
rdata : out std_logic_vector(31 downto 0)
);
end entity;
--
architecture struct of ddr2_phy_alt_mem_phy_iram_ram is
-- infer ram
constant c_max_ram_address : natural := 2**IRAM_AWIDTH -1;
-- registered ram signals
signal addr_r : unsigned(IRAM_AWIDTH-1 downto 0);
signal wdata_r : std_logic_vector(31 downto 0);
signal write_r : std_logic;
signal rdata_r : std_logic_vector(31 downto 0);
-- ram storage array
type t_iram is array (0 to c_max_ram_address) of std_logic_vector(31 downto 0);
signal iram_ram : t_iram;
attribute altera_attribute : string;
attribute altera_attribute of iram_ram : signal is "-name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ""OFF""";
begin -- architecture struct
-- inferred ram instance - standard ram logic
process (clk, rst_n)
begin
if rst_n = '0' then
rdata_r <= (others => '0');
elsif rising_edge(clk) then
if write_r = '1' then
iram_ram(to_integer(addr_r)) <= wdata_r;
end if;
rdata_r <= iram_ram(to_integer(addr_r));
end if;
end process;
-- register i/o for speed
process (clk, rst_n)
begin
if rst_n = '0' then
rdata <= (others => '0');
write_r <= '0';
addr_r <= (others => '0');
wdata_r <= (others => '0');
elsif rising_edge(clk) then
rdata <= rdata_r;
write_r <= write;
addr_r <= addr;
wdata_r <= wdata;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : iram block for the non-levelling AFI PHY sequencer
-- This block is an optional storage of debug information for
-- the sequencer. In the current form the iram stores header
-- information about the arrangement of the sequencer and pass/
-- fail information for per-delay/phase/pin sweeps for the
-- read resynch phase calibration stage. Support for debug of
-- additional commands can be added at a later date
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The altmemphy iram ram (alt_mem_phy_iram_ram) is an inferred ram memory to implement the debug
-- iram ram block
--
use work.ddr2_phy_alt_mem_phy_iram_ram;
--
entity ddr2_phy_alt_mem_phy_iram is
generic (
-- physical interface width definitions
MEM_IF_MEMTYPE : string;
FAMILYGROUP_ID : natural;
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
IRAM_AWIDTH : natural;
REFRESH_COUNT_INIT : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural;
CAPABILITIES : natural;
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- read interface from mmi block:
mmi_iram : in t_iram_ctrl;
mmi_iram_enable_writes : in std_logic;
--iram status signal (includes read data from iram)
iram_status : out t_iram_stat;
iram_push_done : out std_logic;
-- from ctrl block
ctrl_iram : in t_ctrl_command;
-- from dgrb block
dgrb_iram : in t_iram_push;
-- from admin block
admin_regs_status_rec : in t_admin_stat;
-- current write position in the iram
ctrl_idib_top : in natural range 0 to 2 ** IRAM_AWIDTH - 1;
ctrl_iram_push : in t_ctrl_iram;
-- the following signals are unused and reserved for future use
dgwb_iram : in t_iram_push
);
end entity;
library work;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr2_phy_alt_mem_phy_regs_pkg.all;
--
architecture struct of ddr2_phy_alt_mem_phy_iram is
-- -------------------------------------------
-- IHI fields
-- -------------------------------------------
-- memory type , Quartus Build No., Quartus release, sequencer architecture version :
signal memtype : std_logic_vector(7 downto 0);
signal ihi_self_description : std_logic_vector(31 downto 0);
signal ihi_self_description_extra : std_logic_vector(31 downto 0);
-- for iram address generation:
signal curr_iram_offset : natural range 0 to 2 ** IRAM_AWIDTH - 1;
-- set read latency for iram_rdata_valid signal control:
constant c_iram_rlat : natural := 3; -- iram read latency (increment if read pipelining added
-- for rdata valid generation:
signal read_valid_ctr : natural range 0 to c_iram_rlat;
signal iram_addr_r : unsigned(IRAM_AWIDTH downto 0);
constant c_ihi_phys_if_desc : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(MEM_IF_NUM_RANKS,8) & to_unsigned(MEM_IF_DM_WIDTH,8) & to_unsigned(MEM_IF_DQS_WIDTH,8) & to_unsigned(MEM_IF_DWIDTH,8));
constant c_ihi_timing_info : std_logic_vector(31 downto 0) := X"DEADDEAD";
constant c_ihi_ctrl_ss_word2 : std_logic_vector(31 downto 0) := std_logic_vector (to_unsigned(PRESET_RLAT,16) & X"0000");
-- IDIB header codes
constant c_idib_header_code0 : std_logic_vector(7 downto 0) := X"4A";
constant c_idib_footer_code : std_logic_vector(7 downto 0) := X"5A";
-- encoded Quartus version
-- constant c_quartus_version : natural := 0; -- Quartus 7.2
-- constant c_quartus_version : natural := 1; -- Quartus 8.0
--constant c_quartus_version : natural := 2; -- Quartus 8.1
--constant c_quartus_version : natural := 3; -- Quartus 9.0
--constant c_quartus_version : natural := 4; -- Quartus 9.0sp2
--constant c_quartus_version : natural := 5; -- Quartus 9.1
--constant c_quartus_version : natural := 6; -- Quartus 9.1sp1?
--constant c_quartus_version : natural := 7; -- Quartus 9.1sp2?
constant c_quartus_version : natural := 8; -- Quartus 10.0
-- constant c_quartus_version : natural := 114; -- reserved
-- allow for different variants for debug i/f
constant c_dbg_if_version : natural := 2;
-- sequencer type 1 for levelling, 2 for non-levelling
constant c_sequencer_type : natural := 2;
-- a prefix for all report signals to identify phy and sequencer block
--
constant iram_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (iram) : ";
-- -------------------------------------------
-- signal and type declarations
-- -------------------------------------------
type t_iram_state is ( s_reset, -- system reset
s_pre_init_ram, -- identify pre-initialisation
s_init_ram, -- zero all locations
s_idle, -- default state
s_word_access_ram, -- mmi access to the iram (post-calibration)
s_word_fetch_ram_rdata, -- sample read data from RAM
s_word_fetch_ram_rdata_r,-- register the sampling of data from RAM (to improve timing)
s_word_complete, -- finalise iram ram write
s_idib_header_write, -- when starting a command
s_idib_header_inc_addr, -- address increment
s_idib_footer_write, -- unique footer to indicate end of data
s_cal_data_read, -- read RAM location (read occurs continuously from idle state)
s_cal_data_read_r,
s_cal_data_modify, -- modify RAM location (read occurs continuously)
s_cal_data_write, -- write modified value back to RAM
s_ihi_header_word0_wr, -- from 0 to 6 writing iram header info
s_ihi_header_word1_wr,
s_ihi_header_word2_wr,
s_ihi_header_word3_wr,
s_ihi_header_word4_wr,
s_ihi_header_word5_wr,
s_ihi_header_word6_wr,
s_ihi_header_word7_wr-- end writing iram header info
);
signal state : t_iram_state;
signal contested_access : std_logic;
signal idib_header_count : std_logic_vector(7 downto 0);
-- register a new cmd request
signal new_cmd : std_logic;
signal cmd_processed : std_logic;
-- signals to control dgrb writes
signal iram_modified_data : std_logic_vector(31 downto 0); -- scratchpad memory for read-modify-write
-- -------------------------------------------
-- physical ram connections
-- -------------------------------------------
-- Note that the iram_addr here is created IRAM_AWIDTH downto 0, and not
-- IRAM_AWIDTH-1 downto 0. This means that the MSB is outside the addressable
-- area of the RAM. The purpose of this is that this shall be our memory
-- overflow bit. It shall be directly connected to the iram_out_of_memory flag
-- 32-bit interface port (read and write)
signal iram_addr : unsigned(IRAM_AWIDTH downto 0);
signal iram_wdata : std_logic_vector(31 downto 0);
signal iram_rdata : std_logic_vector(31 downto 0);
signal iram_write : std_logic;
-- signal generated external to the iram to say when read data is valid
signal iram_rdata_valid : std_logic;
-- The FSM owns local storage that is loaded with the wdata/addr from the
-- requesting sub-block, which is then fed to the iram's wdata/addr in turn
-- until all data has gone across
signal fsm_read : std_logic;
-- -------------------------------------------
-- multiplexed push data
-- -------------------------------------------
signal iram_done : std_logic; -- unused
signal iram_pushdata : std_logic_vector(31 downto 0);
signal pending_push : std_logic; -- push data to RAM
signal iram_wordnum : natural range 0 to 511;
signal iram_bitnum : natural range 0 to 31;
begin -- architecture struct
-- -------------------------------------------
-- iram ram instantiation
-- -------------------------------------------
-- Note that the IRAM_AWIDTH is the physical number of address bits that the RAM has.
-- However, for out of range access detection purposes, an additional bit is added to
-- the various address signals. The iRAM does not register any of its inputs as the addr,
-- wdata etc are registered directly before being driven to it.
-- The dgrb accesses are of format read-modify-write to a single bit of a 32-bit word, the
-- mmi reads and header writes are in 32-bit words
--
ram : entity ddr2_phy_alt_mem_phy_iram_ram
generic map (
IRAM_AWIDTH => IRAM_AWIDTH
)
port map (
clk => clk,
rst_n => rst_n,
addr => iram_addr(IRAM_AWIDTH-1 downto 0),
wdata => iram_wdata,
write => iram_write,
rdata => iram_rdata
);
-- -------------------------------------------
-- IHI fields
-- asynchronously
-- -------------------------------------------
-- this field identifies the type of memory
memtype <= X"03" when (MEM_IF_MEMTYPE = "DDR3") else
X"02" when (MEM_IF_MEMTYPE = "DDR2") else
X"01" when (MEM_IF_MEMTYPE = "DDR") else
X"10" when (MEM_IF_MEMTYPE = "QDRII") else
X"00" ;
-- this field indentifies the gross level description of the sequencer
ihi_self_description <= memtype
& std_logic_vector(to_unsigned(IP_BUILDNUM,8))
& std_logic_vector(to_unsigned(c_quartus_version,8))
& std_logic_vector(to_unsigned(c_dbg_if_version,8));
-- some extra information for the debug gui - sequencer type and familygroup
ihi_self_description_extra <= std_logic_vector(to_unsigned(FAMILYGROUP_ID,4))
& std_logic_vector(to_unsigned(c_sequencer_type,4))
& x"000000";
-- -------------------------------------------
-- check for contested memory accesses
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
contested_access <= '0';
elsif rising_edge(clk) then
contested_access <= '0';
if mmi_iram.read = '1' and pending_push = '1' then
report iram_report_prefix & "contested memory accesses to the iram" severity failure;
contested_access <= '1';
end if;
-- sanity checks
if mmi_iram.write = '1' then
report iram_report_prefix & "mmi writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
if dgwb_iram.iram_write = '1' then
report iram_report_prefix & "dgwb writes to the iram unsupported for non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end process;
-- -------------------------------------------
-- mux push data and associated signals
-- note: single bit taken for iram_pushdata because 1-bit read-modify-write to
-- a 32-bit word in the ram. This interface style is maintained for future
-- scalability / wider application of the iram block.
-- -------------------------------------------
process(clk,rst_n)
begin
if rst_n = '0' then
iram_done <= '0';
iram_pushdata <= (others => '0');
pending_push <= '0';
iram_wordnum <= 0;
iram_bitnum <= 0;
elsif rising_edge(clk) then
case curr_active_block(ctrl_iram.command) is
when dgrb =>
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
when others => -- default dgrb
iram_done <= dgrb_iram.iram_done;
iram_pushdata <= dgrb_iram.iram_pushdata;
pending_push <= dgrb_iram.iram_write;
iram_wordnum <= dgrb_iram.iram_wordnum;
iram_bitnum <= dgrb_iram.iram_bitnum;
end case;
end if;
end process;
-- -------------------------------------------
-- generate write signal for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_write <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
iram_write <= '0';
when s_pre_init_ram |
s_init_ram =>
iram_write <= '1';
when s_ihi_header_word0_wr |
s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_write <= '1';
when s_idib_header_write =>
iram_write <= '1';
when s_idib_footer_write =>
iram_write <= '1';
when s_cal_data_write =>
iram_write <= '1';
when others =>
iram_write <= '0'; -- default
end case;
end if;
end process;
-- -------------------------------------------
-- generate wdata for the ram
-- -------------------------------------------
process(clk, rst_n)
variable v_current_cs : std_logic_vector(3 downto 0);
variable v_mtp_alignment : std_logic_vector(0 downto 0);
variable v_single_bit : std_logic;
begin
if rst_n = '0' then
iram_wdata <= (others => '0');
elsif rising_edge(clk) then
case state is
when s_pre_init_ram |
s_init_ram =>
iram_wdata <= (others => '0');
when s_ihi_header_word0_wr =>
iram_wdata <= ihi_self_description;
when s_ihi_header_word1_wr =>
iram_wdata <= c_ihi_phys_if_desc;
when s_ihi_header_word2_wr =>
iram_wdata <= c_ihi_timing_info;
when s_ihi_header_word3_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr0'range) <= admin_regs_status_rec.mr0;
iram_wdata(admin_regs_status_rec.mr1'high + 16 downto 16) <= admin_regs_status_rec.mr1;
when s_ihi_header_word4_wr =>
iram_wdata <= ( others => '0');
iram_wdata(admin_regs_status_rec.mr2'range) <= admin_regs_status_rec.mr2;
iram_wdata(admin_regs_status_rec.mr3'high + 16 downto 16) <= admin_regs_status_rec.mr3;
when s_ihi_header_word5_wr =>
iram_wdata <= c_ihi_ctrl_ss_word2;
when s_ihi_header_word6_wr =>
iram_wdata <= std_logic_vector(to_unsigned(IRAM_AWIDTH,32)); -- tbd write the occupancy at end of cal
when s_ihi_header_word7_wr =>
iram_wdata <= ihi_self_description_extra;
when s_idib_header_write =>
-- encode command_op for current operation
v_current_cs := std_logic_vector(to_unsigned(ctrl_iram.command_op.current_cs, 4));
v_mtp_alignment := std_logic_vector(to_unsigned(ctrl_iram.command_op.mtp_almt, 1));
v_single_bit := ctrl_iram.command_op.single_bit;
iram_wdata <= encode_current_stage(ctrl_iram.command) & -- which command being executed (currently this should only be cmd_rrp_sweep (8 bits)
v_current_cs & -- which chip select being processed (4 bits)
v_mtp_alignment & -- currently used MTP alignment (1 bit)
v_single_bit & -- is single bit calibration selected (1 bit) - used during MTP alignment
"00" & -- RFU
idib_header_count & -- unique ID to how many headers have been written (8 bits)
c_idib_header_code0; -- unique ID for headers (8 bits)
when s_idib_footer_write =>
iram_wdata <= c_idib_footer_code & c_idib_footer_code & c_idib_footer_code & c_idib_footer_code;
when s_cal_data_modify =>
-- default don't overwrite
iram_modified_data <= iram_rdata;
-- update iram data based on packing and write modes
if ctrl_iram_push.packing_mode = dq_bitwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0);
when or_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) or iram_rdata(0);
when and_into_ram =>
iram_modified_data(iram_bitnum) <= iram_pushdata(0) and iram_rdata(0);
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
elsif ctrl_iram_push.packing_mode = dq_wordwise then
case ctrl_iram_push.write_mode is
when overwrite_ram =>
iram_modified_data <= iram_pushdata;
when or_into_ram =>
iram_modified_data <= iram_pushdata or iram_rdata;
when and_into_ram =>
iram_modified_data <= iram_pushdata and iram_rdata;
when others =>
report iram_report_prefix & "unidentified write mode of " & t_iram_write_mode'image(ctrl_iram_push.write_mode) &
" specified when generating iram write data" severity failure;
end case;
else
report iram_report_prefix & "unidentified packing mode of " & t_iram_packing_mode'image(ctrl_iram_push.packing_mode) &
" specified when generating iram write data" severity failure;
end if;
when s_cal_data_write =>
iram_wdata <= iram_modified_data;
when others =>
iram_wdata <= (others => '0');
end case;
end if;
end process;
-- -------------------------------------------
-- generate addr for the ram
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_addr <= (others => '0');
curr_iram_offset <= 0;
elsif rising_edge(clk) then
case (state) is
when s_idle =>
if mmi_iram.read = '1' then -- pre-set mmi read location address
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
else -- default get next push data location from iram
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1);
end if;
when s_word_access_ram =>
-- calculate the address
if mmi_iram.read = '1' then -- mmi access
iram_addr <= ('0' & to_unsigned(mmi_iram.addr,IRAM_AWIDTH)); -- Pad MSB
end if;
when s_ihi_header_word0_wr =>
iram_addr <= (others => '0');
-- increment address for IHI word writes :
when s_ihi_header_word1_wr |
s_ihi_header_word2_wr |
s_ihi_header_word3_wr |
s_ihi_header_word4_wr |
s_ihi_header_word5_wr |
s_ihi_header_word6_wr |
s_ihi_header_word7_wr =>
iram_addr <= iram_addr + 1;
when s_idib_header_write =>
iram_addr <= '0' & to_unsigned(ctrl_idib_top, IRAM_AWIDTH); -- Always write header at idib_top location
when s_idib_footer_write =>
iram_addr <= to_unsigned(curr_iram_offset + iram_wordnum, IRAM_AWIDTH+1); -- active block communicates where to put the footer with done signal
when s_idib_header_inc_addr =>
iram_addr <= iram_addr + 1;
curr_iram_offset <= to_integer('0' & iram_addr) + 1;
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
iram_addr <= (others => '0'); -- this prevents erroneous out-of-mem flag after initialisation
else
iram_addr <= iram_addr + 1;
end if;
when others =>
iram_addr <= iram_addr;
end case;
end if;
end process;
-- -------------------------------------------
-- generate new cmd signal to register the command_req signal
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
new_cmd <= '0';
elsif rising_edge(clk) then
if ctrl_iram.command_req = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep | -- only prompt new_cmd for commands we wish to write headers for
cmd_rrp_seek |
cmd_read_mtp |
cmd_write_ihi =>
new_cmd <= '1';
when others =>
new_cmd <= '0';
end case;
end if;
if cmd_processed = '1' then
new_cmd <= '0';
end if;
end if;
end process;
-- -------------------------------------------
-- generate read valid signal which takes account of pipelining of reads
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_rdata_valid <= '0';
read_valid_ctr <= 0;
iram_addr_r <= (others => '0');
elsif rising_edge(clk) then
if read_valid_ctr < c_iram_rlat then
iram_rdata_valid <= '0';
read_valid_ctr <= read_valid_ctr + 1;
else
iram_rdata_valid <= '1';
end if;
if to_integer(iram_addr) /= to_integer(iram_addr_r) or
iram_write = '1' then
read_valid_ctr <= 0;
iram_rdata_valid <= '0';
end if;
-- register iram address
iram_addr_r <= iram_addr;
end if;
end process;
-- -------------------------------------------
-- state machine
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
state <= s_reset;
cmd_processed <= '0';
elsif rising_edge(clk) then
cmd_processed <= '0';
case state is
when s_reset =>
state <= s_pre_init_ram;
when s_pre_init_ram =>
state <= s_init_ram;
-- remain in the init_ram state until all the ram locations have been zero'ed
when s_init_ram =>
if iram_addr(IRAM_AWIDTH) = '1' then
state <= s_idle;
end if;
-- default state after reset
when s_idle =>
if pending_push = '1' then
state <= s_cal_data_read;
elsif iram_done = '1' then
state <= s_idib_footer_write;
elsif new_cmd = '1' then
case ctrl_iram.command is
when cmd_rrp_sweep |
cmd_rrp_seek |
cmd_read_mtp => state <= s_idib_header_write;
when cmd_write_ihi => state <= s_ihi_header_word0_wr;
when others => state <= state;
end case;
cmd_processed <= '1';
elsif mmi_iram.read = '1' then
state <= s_word_access_ram;
end if;
-- mmi read accesses
when s_word_access_ram => state <= s_word_fetch_ram_rdata;
when s_word_fetch_ram_rdata => state <= s_word_fetch_ram_rdata_r;
when s_word_fetch_ram_rdata_r => if iram_rdata_valid = '1' then
state <= s_word_complete;
end if;
when s_word_complete => if iram_rdata_valid = '1' then -- return to idle when iram_rdata stable
state <= s_idle;
end if;
-- header write (currently only for cmp_rrp stage)
when s_idib_header_write => state <= s_idib_header_inc_addr;
when s_idib_header_inc_addr => state <= s_idle; -- return to idle to wait for push
when s_idib_footer_write => state <= s_word_complete;
-- push data accesses (only used by the dgrb block at present)
when s_cal_data_read => state <= s_cal_data_read_r;
when s_cal_data_read_r => if iram_rdata_valid = '1' then
state <= s_cal_data_modify;
end if;
when s_cal_data_modify => state <= s_cal_data_write;
when s_cal_data_write => state <= s_word_complete;
-- IHI Header write accesses
when s_ihi_header_word0_wr => state <= s_ihi_header_word1_wr;
when s_ihi_header_word1_wr => state <= s_ihi_header_word2_wr;
when s_ihi_header_word2_wr => state <= s_ihi_header_word3_wr;
when s_ihi_header_word3_wr => state <= s_ihi_header_word4_wr;
when s_ihi_header_word4_wr => state <= s_ihi_header_word5_wr;
when s_ihi_header_word5_wr => state <= s_ihi_header_word6_wr;
when s_ihi_header_word6_wr => state <= s_ihi_header_word7_wr;
when s_ihi_header_word7_wr => state <= s_idle;
when others => state <= state;
end case;
end if;
end process;
-- -------------------------------------------
-- drive read data and responses back.
-- -------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
iram_status <= defaults;
iram_push_done <= '0';
idib_header_count <= (others => '0');
fsm_read <= '0';
elsif rising_edge(clk) then
-- defaults
iram_status <= defaults;
iram_status.done <= '0';
iram_status.rdata <= (others => '0');
iram_push_done <= '0';
if state = s_init_ram then
iram_status.out_of_mem <= '0';
else
iram_status.out_of_mem <= iram_addr(IRAM_AWIDTH);
end if;
-- register read flag for 32 bit accesses
if state = s_idle then
fsm_read <= mmi_iram.read;
end if;
if state = s_word_complete then
iram_status.done <= '1';
if fsm_read = '1' then
iram_status.rdata <= iram_rdata;
else
iram_status.rdata <= (others => '0');
end if;
end if;
-- if another access is ever presented while the FSM is busy, set the contested flag
if contested_access = '1' then
iram_status.contested_access <= '1';
end if;
-- set (and keep set) the iram_init_done output once initialisation of the RAM is complete
if (state /= s_init_ram) and (state /= s_pre_init_ram) and (state /= s_reset) then
iram_status.init_done <= '1';
end if;
if state = s_ihi_header_word7_wr then
iram_push_done <= '1';
end if;
-- if completing push or footer write then acknowledge
if state = s_cal_data_modify or state = s_idib_footer_write then
iram_push_done <= '1';
end if;
-- increment IDIB header count each time a header is written
if state = s_idib_header_write then
idib_header_count <= std_logic_vector(unsigned(idib_header_count) + to_unsigned(1,idib_header_count'high +1));
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (read bias) [dgrb] block for the non-levelling
-- AFI PHY sequencer
-- This block handles all calibration commands which require
-- memory read operations.
--
-- These include:
-- Resync phase calibration - sweep of phases, calculation of
-- result and optional storage to iram
-- Postamble calibration - clock cycle calibration of the postamble
-- enable signal
-- Read data valid signal alignment
-- Calculation of advertised read and write latencies
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr2_phy_alt_mem_phy_addr_cmd_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr2_phy_alt_mem_phy_iram_addr_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
--
entity ddr2_phy_alt_mem_phy_dgrb is
generic (
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQS_CAPTURE : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
CLOCK_INDEX_WIDTH : natural;
DWIDTH_RATIO : natural;
PRESET_RLAT : natural;
PLL_STEPS_PER_CYCLE : natural; -- number of PLL phase steps per PHY clock cycle
SIM_TIME_REDUCTIONS : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
PRESET_CODVW_PHASE : natural;
PRESET_CODVW_SIZE : natural;
-- base column address to which calibration data is written
-- memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data
MEM_IF_CAL_BANK : natural; -- bank to which calibration data is written
MEM_IF_CAL_BASE_COL : natural;
EN_OCT : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- control interface
dgrb_ctrl : out t_ctrl_stat;
ctrl_dgrb : in t_ctrl_command;
parameterisation_rec : in t_algm_paramaterisation;
-- PLL reconfig interface
phs_shft_busy : in std_logic;
seq_pll_inc_dec_n : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
seq_pll_start_reconfig : out std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic / aka measure clock
-- iram 'push' interface
dgrb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- addr/cmd output for write commands
dgrb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- admin block req/gnt interface
dgrb_ac_access_req : out std_logic;
dgrb_ac_access_gnt : in std_logic;
-- RDV latency controls
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
-- POA latency controls
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
-- read datapath interface
rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0);
rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- advertised write latency
wd_lat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- OCT control
seq_oct_value : out std_logic;
dgrb_wdp_ovride : out std_logic;
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- calibration byte lane select (reserved for future use - RFU)
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1);
-- signal to identify if a/c nt setting is correct (set after wr_lat calculation)
-- NOTE: labelled nt for future scalability to quarter rate interfaces
dgrb_ctrl_ac_nt_good : out std_logic;
-- status signals on calibrated cdvw
dgrb_mmi : out t_dgrb_mmi
);
end entity;
--
architecture struct of ddr2_phy_alt_mem_phy_dgrb is
-- ------------------------------------------------------------------
-- constant declarations
-- ------------------------------------------------------------------
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- command/result length
constant c_command_result_len : natural := 8;
-- burst characteristics and latency characteristics
constant c_max_read_lat : natural := 2**rd_lat'length - 1; -- maximum read latency in phy clock-cycles
-- training pattern characteristics
constant c_cal_mtp_len : natural := 16;
constant c_cal_mtp : std_logic_vector(c_cal_mtp_len - 1 downto 0) := x"30F5";
constant c_cal_mtp_t : natural := c_cal_mtp_len / DWIDTH_RATIO; -- number of phy-clk cycles required to read BTP
-- read/write latency defaults
constant c_default_rd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_rd_lat, ADV_LAT_WIDTH));
constant c_default_wd_lat_slv : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0) := std_logic_vector(to_unsigned(c_default_wr_lat, ADV_LAT_WIDTH));
-- tracking reporting parameters
constant c_max_rsc_drift_in_phases : natural := 127; -- this must be a value of < 2^10 - 1 because of the range of signal codvw_trk_shift
-- Returns '1' when boolean b is True; '0' otherwise.
function active_high(b : in boolean) return std_logic is
variable r : std_logic;
begin
if b then
r := '1';
else
r := '0';
end if;
return r;
end function;
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgrb_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (dgrb) : ";
-- Return the number of clock periods the resync clock should sweep.
--
-- On half-rate systems and in DQS-capture based systems a 720
-- to guarantee the resync window can be properly observed.
function rsc_sweep_clk_periods return natural is
variable v_num_periods : natural;
begin
if DWIDTH_RATIO = 2 then
if MEM_IF_DQS_CAPTURE = 1 then -- families which use DQS capture require a 720 degree sweep for FR to show a window
v_num_periods := 2;
else
v_num_periods := 1;
end if;
elsif DWIDTH_RATIO = 4 then
v_num_periods := 2;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO." severity failure;
end if;
return v_num_periods;
end function;
-- window for PLL sweep
constant c_max_phase_shifts : natural := rsc_sweep_clk_periods*PLL_STEPS_PER_CYCLE;
constant c_pll_phs_inc : std_logic := '1';
constant c_pll_phs_dec : std_logic := not c_pll_phs_inc;
-- ------------------------------------------------------------------
-- type declarations
-- ------------------------------------------------------------------
-- dgrb main state machine
type t_dgrb_state is (
-- idle state
s_idle,
-- request access to memory address/command bus from the admin block
s_wait_admin,
-- relinquish address/command bus access
s_release_admin,
-- wind back resync phase to a 'zero' point
s_reset_cdvw,
-- perform resync phase sweep (used for MTP alignment checking and actual RRP sweep)
s_test_phases,
-- processing to when checking MTP alignment
s_read_mtp,
-- processing for RRP (read resync phase) sweep
s_seek_cdvw,
-- clock cycle alignment of read data valid signal
s_rdata_valid_align,
-- calculate advertised read latency
s_adv_rd_lat_setup,
s_adv_rd_lat,
-- calculate advertised write latency
s_adv_wd_lat,
-- postamble clock cycle calibration
s_poa_cal,
-- tracking - setup and periodic update
s_track
);
-- dgrb slave state machine for addr/cmd signals
type t_ac_state is (
-- idle state
s_ac_idle,
-- wait X cycles (issuing NOP command) to flush address/command and DQ buses
s_ac_relax,
-- read MTP pattern
s_ac_read_mtp,
-- read pattern for read data valid alignment
s_ac_read_rdv,
-- read pattern for POA calibration
s_ac_read_poa_mtp,
-- read pattern to calculate advertised write latency
s_ac_read_wd_lat
);
-- dgrb slave state machine for read resync phase calibration
type t_resync_state is (
-- idle state
s_rsc_idle,
-- shift resync phase by one
s_rsc_next_phase,
-- start test sequence for current pin and current phase
s_rsc_test_phase,
-- flush the read datapath
s_rsc_wait_for_idle_dimm, -- wait until no longer driving
s_rsc_flush_datapath, -- flush a/c path
-- sample DQ data to test phase
s_rsc_test_dq,
-- reset rsc phase to a zero position
s_rsc_reset_cdvw,
s_rsc_rewind_phase,
-- calculate the centre of resync window
s_rsc_cdvw_calc,
s_rsc_cdvw_wait, -- wait for calc result
-- set rsc clock phase to centre of data valid window
s_rsc_seek_cdvw,
-- wait until all results written to iram
s_rsc_wait_iram -- only entered if GENERATE_ADDITIONAL_DBG_RTL = 1
);
-- record definitions for window processing
type t_win_processing_status is ( calculating,
valid_result,
no_invalid_phases,
multiple_equal_windows,
no_valid_phases
);
type t_window_processing is record
working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
first_good_edge : natural range 0 to c_max_phase_shifts - 1; -- pointer to first detected good edge
current_window_start : natural range 0 to c_max_phase_shifts - 1;
current_window_size : natural range 0 to c_max_phase_shifts - 1;
current_window_centre : natural range 0 to c_max_phase_shifts - 1;
largest_window_start : natural range 0 to c_max_phase_shifts - 1;
largest_window_size : natural range 0 to c_max_phase_shifts - 1;
largest_window_centre : natural range 0 to c_max_phase_shifts - 1;
current_bit : natural range 0 to c_max_phase_shifts - 1;
window_centre_update : std_logic;
last_bit_value : std_logic;
valid_phase_seen : boolean;
invalid_phase_seen : boolean;
first_cycle : boolean;
multiple_eq_windows : boolean;
found_a_good_edge : boolean;
status : t_win_processing_status;
windows_seen : natural range 0 to c_max_phase_shifts/2 - 1;
end record;
-- ------------------------------------------------------------------
-- function and procedure definitions
-- ------------------------------------------------------------------
-- Returns a string representation of a std_logic_vector.
-- Not synthesizable.
function str(v: std_logic_vector) return string is
variable str_value : string (1 to v'length);
variable str_len : integer;
variable c : character;
begin
str_len := 1;
for i in v'range loop
case v(i) is
when '0' => c := '0';
when '1' => c := '1';
when others => c := '?';
end case;
str_value(str_len) := c;
str_len := str_len + 1;
end loop;
return str_value;
end str;
-- functions and procedures for window processing
function defaults return t_window_processing is
variable output : t_window_processing;
begin
output.working_window := (others => '1');
output.last_bit_value := '1';
output.first_good_edge := 0;
output.current_window_start := 0;
output.current_window_size := 0;
output.current_window_centre := 0;
output.largest_window_start := 0;
output.largest_window_size := 0;
output.largest_window_centre := 0;
output.window_centre_update := '1';
output.current_bit := 0;
output.multiple_eq_windows := false;
output.valid_phase_seen := false;
output.invalid_phase_seen := false;
output.found_a_good_edge := false;
output.status := no_valid_phases;
output.first_cycle := false;
output.windows_seen := 0;
return output;
end function defaults;
procedure initialise_window_for_proc ( working : inout t_window_processing ) is
variable v_working_window : std_logic_vector( c_max_phase_shifts - 1 downto 0);
begin
v_working_window := working.working_window;
working := defaults;
working.working_window := v_working_window;
working.status := calculating;
working.first_cycle := true;
working.window_centre_update := '1';
working.windows_seen := 0;
end procedure initialise_window_for_proc;
procedure shift_window (working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
)
is
begin
if working.working_window(0) = '0' then
working.invalid_phase_seen := true;
else
working.valid_phase_seen := true;
end if;
-- general bit serial shifting of window and incrementing of current bit counter.
if working.current_bit < num_phases - 1 then
working.current_bit := working.current_bit + 1;
else
working.current_bit := 0;
end if;
working.last_bit_value := working.working_window(0);
working.working_window := working.working_window(0) & working.working_window(working.working_window'high downto 1);
--synopsis translate_off
-- for simulation to make it simpler to see IF we are not using all the bits in the window
working.working_window(working.working_window'high) := 'H'; -- for visual debug
--synopsis translate_on
working.working_window(num_phases -1) := working.last_bit_value;
working.first_cycle := false;
end procedure shift_window;
procedure find_centre_of_largest_data_valid_window
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure, then handle end conditions
if working.current_bit = 0 and working.found_a_good_edge = false then -- have been all way arround window (circular)
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
end if;
elsif working.current_bit = working.first_good_edge then -- if have found a good edge then complete a circular sweep to that edge
if working.multiple_eq_windows = true then
working.status := multiple_equal_windows;
else
working.status := valid_result;
end if;
end if;
end if;
-- start of a window condition
if working.last_bit_value = '0' and working.working_window(0) = '1' then
working.current_window_start := working.current_bit;
working.current_window_size := working.current_window_size + 1; -- equivalent to assigning to one because if not in a window then it is set to 0
working.window_centre_update := not working.window_centre_update;
working.current_window_centre := working.current_bit;
if working.found_a_good_edge /= true then -- if have not yet found a good edge then store this value
working.first_good_edge := working.current_bit;
working.found_a_good_edge := true;
end if;
-- end of window conditions
elsif working.last_bit_value = '1' and working.working_window(0) = '0' then
if working.current_window_size > working.largest_window_size then
working.largest_window_size := working.current_window_size;
working.largest_window_start := working.current_window_start;
working.largest_window_centre := working.current_window_centre;
working.multiple_eq_windows := false;
elsif working.current_window_size = working.largest_window_size then
working.multiple_eq_windows := true;
end if;
-- put counter in here because start of window 1 is observed twice
if working.found_a_good_edge = true then
working.windows_seen := working.windows_seen + 1;
end if;
working.current_window_size := 0;
elsif working.last_bit_value = '1' and working.working_window(0) = '1' and (working.found_a_good_edge = true) then --note operand in brackets is excessive but for may provide power savings and makes visual inspection of simulatuion easier
if working.window_centre_update = '1' then
if working.current_window_centre < num_phases -1 then
working.current_window_centre := working.current_window_centre + 1;
else
working.current_window_centre := 0;
end if;
end if;
working.window_centre_update := not working.window_centre_update;
working.current_window_size := working.current_window_size + 1;
end if;
shift_window(working,num_phases);
end procedure find_centre_of_largest_data_valid_window;
procedure find_last_failing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts + 1
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(1) = '1' and working.working_window(0) = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_last_failing_phase;
procedure find_first_passing_phase
( working : inout t_window_processing;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
if working.first_cycle = false then -- not first call to procedure
if working.current_bit = 0 then -- and working.found_a_good_edge = false then
if working.valid_phase_seen = false then
working.status := no_valid_phases;
elsif working.invalid_phase_seen = false then
working.status := no_invalid_phases;
else
working.status := valid_result;
end if;
end if;
end if;
if working.working_window(0) = '1' and working.last_bit_value = '0' and working.status = calculating then
working.current_window_start := working.current_bit;
end if;
shift_window(working, num_phases); -- shifts window and sets first_cycle = false
end procedure find_first_passing_phase;
-- shift in current pass/fail result to the working window
procedure shift_in(
working : inout t_window_processing;
status : in std_logic;
num_phases : in natural range 1 to c_max_phase_shifts
) is
begin
working.last_bit_value := working.working_window(0);
working.working_window(num_phases-1 downto 0) := (working.working_window(0) and status) & working.working_window(num_phases-1 downto 1);
end procedure;
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgrb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
-- extract PHY 'addr/cmd' to 'wdata_valid' write latency from current read data
function wd_lat_from_rdata(signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0))
return std_logic_vector is
variable v_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
v_wd_lat := (others => '0');
if set_wlat_dq_rep_width >= ADV_LAT_WIDTH then
v_wd_lat := rdata(v_wd_lat'high downto 0);
else
v_wd_lat := (others => '0');
v_wd_lat(set_wlat_dq_rep_width - 1 downto 0) := rdata(set_wlat_dq_rep_width - 1 downto 0);
end if;
return v_wd_lat;
end function;
-- check if rdata_valid is correctly aligned
function rdata_valid_aligned(
signal rdata : in std_logic_vector(DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
signal rdata_valid : in std_logic_vector(DWIDTH_RATIO/2 - 1 downto 0)
) return std_logic is
variable v_dq_rdata : std_logic_vector(DWIDTH_RATIO - 1 downto 0);
variable v_aligned : std_logic;
begin
-- Look at data from a single DQ pin 0 (DWIDTH_RATIO data bits)
for i in 0 to DWIDTH_RATIO - 1 loop
v_dq_rdata(i) := rdata(i*MEM_IF_DWIDTH);
end loop;
-- Check each alignment (necessary because in the HR case rdata can be in any alignment)
v_aligned := '0';
for i in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata_valid(i) = '1' then
if v_dq_rdata(2*i + 1 downto 2*i) = "00" then
v_aligned := '1';
end if;
end if;
end loop;
return v_aligned;
end function;
-- set severity level for calibration failures
function set_cal_fail_sev_level (
generate_additional_debug_rtl : natural
) return severity_level is
begin
if generate_additional_debug_rtl = 1 then
return warning;
else
return failure;
end if;
end function;
constant cal_fail_sev_level : severity_level := set_cal_fail_sev_level(GENERATE_ADDITIONAL_DBG_RTL);
-- ------------------------------------------------------------------
-- signal declarations
-- rsc = resync - the mechanism of capturing DQ pin data onto a local clock domain
-- trk = tracking - a mechanism to track rsc clock phase with PVT variations
-- poa = postamble - protection circuitry from postamble glitched on DQS
-- ac = memory address / command signals
-- ------------------------------------------------------------------
-- main state machine
signal sig_dgrb_state : t_dgrb_state;
signal sig_dgrb_last_state : t_dgrb_state;
signal sig_rsc_req : t_resync_state; -- tells resync block which state to transition to.
-- centre of data-valid window process
signal sig_cdvw_state : t_window_processing;
-- control signals for the address/command process
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_ac_req : t_ac_state;
signal sig_dimm_driving_dq : std_logic;
signal sig_doing_rd : std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
signal sig_ac_even : std_logic; -- odd/even count of PHY clock cycles.
--
-- sig_ac_even behaviour
--
-- sig_ac_even is always '1' on the cycle a command is issued. It will
-- be '1' on even clock cycles thereafter and '0' otherwise.
--
-- ; ; ; ; ; ;
-- ; _______ ; ; ; ; ;
-- XXXXX / \ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- addr/cmd XXXXXX CMD XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- sig_ac_even ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- phy clk
-- count (0) (1) (2) (3) (4)
--
--
-- resync related signals
signal sig_rsc_ack : std_logic;
signal sig_rsc_err : std_logic;
signal sig_rsc_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_rsc_cdvw_phase : std_logic;
signal sig_rsc_cdvw_shift_in : std_logic;
signal sig_rsc_cdvw_calc : std_logic;
signal sig_rsc_pll_start_reconfig : std_logic;
signal sig_rsc_pll_inc_dec_n : std_logic;
signal sig_rsc_ac_access_req : std_logic; -- High when the resync block requires a training pattern to be read.
-- tracking related signals
signal sig_trk_ack : std_logic;
signal sig_trk_err : std_logic;
signal sig_trk_result : std_logic_vector(c_command_result_len - 1 downto 0 );
signal sig_trk_cdvw_phase : std_logic;
signal sig_trk_cdvw_shift_in : std_logic;
signal sig_trk_cdvw_calc : std_logic;
signal sig_trk_pll_start_reconfig : std_logic;
signal sig_trk_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 DOWNTO 0);
signal sig_trk_pll_inc_dec_n : std_logic;
signal sig_trk_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
-- phs_shft_busy could (potentially) be asynchronous
-- triple register it for metastability hardening
-- these signals are the taps on the shift register
signal sig_phs_shft_busy : std_logic;
signal sig_phs_shft_busy_1t : std_logic;
signal sig_phs_shft_start : std_logic;
signal sig_phs_shft_end : std_logic;
-- locally register crl_dgrb to minimise fan out
signal ctrl_dgrb_r : t_ctrl_command;
-- command_op signals
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal current_mtp_almt : natural range 0 to 1;
signal single_bit_cal : std_logic;
-- codvw status signals (packed into record and sent to mmi block)
signal cal_codvw_phase : std_logic_vector(7 downto 0);
signal codvw_trk_shift : std_logic_vector(11 downto 0);
signal cal_codvw_size : std_logic_vector(7 downto 0);
-- error signal and result from main state machine (operations other than rsc or tracking)
signal sig_cmd_err : std_logic;
signal sig_cmd_result : std_logic_vector(c_command_result_len - 1 downto 0 );
-- signals that the training pattern matched correctly on the last clock
-- cycle.
signal sig_dq_pin_ctr : natural range 0 to MEM_IF_DWIDTH - 1;
signal sig_mtp_match : std_logic;
-- controls postamble match and timing.
signal sig_poa_match_en : std_logic;
signal sig_poa_match : std_logic;
-- postamble signals
signal sig_poa_ack : std_logic; -- '1' for postamble block to acknowledge.
-- calibration byte lane select
signal cal_byte_lanes : std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
signal codvw_grt_one_dvw : std_logic;
begin
doing_rd <= sig_doing_rd;
-- pack record of codvw status signals
dgrb_mmi.cal_codvw_phase <= cal_codvw_phase;
dgrb_mmi.codvw_trk_shift <= codvw_trk_shift;
dgrb_mmi.cal_codvw_size <= cal_codvw_size;
dgrb_mmi.codvw_grt_one_dvw <= codvw_grt_one_dvw;
-- map some internal signals to outputs
dgrb_ac <= sig_addr_cmd;
-- locally register crl_dgrb to minimise fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_dgrb_r <= defaults;
elsif rising_edge(clk) then
ctrl_dgrb_r <= ctrl_dgrb;
end if;
end process;
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
current_mtp_almt <= 0;
single_bit_cal <= '0';
cal_byte_lanes <= (others => '0');
elsif rising_edge(clk) then
if ctrl_dgrb_r.command_req = '1' then
current_cs <= ctrl_dgrb_r.command_op.current_cs;
current_mtp_almt <= ctrl_dgrb_r.command_op.mtp_almt;
single_bit_cal <= ctrl_dgrb_r.command_op.single_bit;
end if;
-- mux byte lane select for given chip select
for i in 0 to MEM_IF_DQS_WIDTH - 1 loop
cal_byte_lanes(i) <= ctl_cal_byte_lanes((current_cs * MEM_IF_DQS_WIDTH) + i);
end loop;
assert ctl_cal_byte_lanes(0) = '1' report dgrb_report_prefix & " Byte lane 0 (chip select 0) disable is not supported - ending simulation" severity failure;
end if;
end process;
-- ------------------------------------------------------------------
-- main state machine for dgrb architecture
--
-- process of commands from control (ctrl) block and overall control of
-- the subsequent calibration processing functions
-- also communicates completion and any errors back to the ctrl block
-- read data valid alignment and advertised latency calculations are
-- included in this block
-- ------------------------------------------------------------------
dgrb_main_block : block
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_wd_lat : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
begin
dgrb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
-- initialise state
sig_dgrb_state <= s_idle;
sig_dgrb_last_state <= s_idle;
sig_ac_req <= s_ac_idle;
sig_rsc_req <= s_rsc_idle;
-- set up rd_lat defaults
rd_lat <= c_default_rd_lat_slv;
wd_lat <= c_default_wd_lat_slv;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- reset counter
sig_count <= 0;
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- sig_wd_lat
sig_wd_lat <= (others => '0');
-- status of the ac_nt alignment
dgrb_ctrl_ac_nt_good <= '1';
elsif rising_edge(clk) then
sig_dgrb_last_state <= sig_dgrb_state;
sig_rsc_req <= s_rsc_idle;
-- set up rdata_valid latency control defaults
seq_rdata_valid_lat_inc <= '0';
seq_rdata_valid_lat_dec <= '0';
-- error signals
sig_cmd_err <= '0';
sig_cmd_result <= (others => '0');
-- register wd_lat output.
wd_lat <= sig_wd_lat;
case sig_dgrb_state is
when s_idle =>
sig_count <= 0;
if ctrl_dgrb_r.command_req = '1' then
if curr_active_block(ctrl_dgrb_r.command) = dgrb then
sig_dgrb_state <= s_wait_admin;
end if;
end if;
sig_ac_req <= s_ac_idle;
when s_wait_admin =>
sig_dgrb_state <= s_wait_admin;
case ctrl_dgrb_r.command is
when cmd_read_mtp => sig_dgrb_state <= s_read_mtp;
when cmd_rrp_reset => sig_dgrb_state <= s_reset_cdvw;
when cmd_rrp_sweep => sig_dgrb_state <= s_test_phases;
when cmd_rrp_seek => sig_dgrb_state <= s_seek_cdvw;
when cmd_rdv => sig_dgrb_state <= s_rdata_valid_align;
when cmd_prep_adv_rd_lat => sig_dgrb_state <= s_adv_rd_lat_setup;
when cmd_prep_adv_wr_lat => sig_dgrb_state <= s_adv_wd_lat;
when cmd_tr_due => sig_dgrb_state <= s_track;
when cmd_poa => sig_dgrb_state <= s_poa_cal;
when others =>
report dgrb_report_prefix & "unknown command" severity failure;
sig_dgrb_state <= s_idle;
end case;
when s_reset_cdvw =>
-- the cdvw proc watches for this state and resets the cdvw
-- state block.
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_reset_cdvw;
end if;
when s_test_phases =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_test_phase;
if sig_rsc_ac_access_req = '1' then
sig_ac_req <= s_ac_read_mtp;
else
sig_ac_req <= s_ac_idle;
end if;
end if;
when s_seek_cdvw | s_read_mtp =>
if sig_rsc_ack = '1' then
sig_dgrb_state <= s_release_admin;
else
sig_rsc_req <= s_rsc_cdvw_calc;
end if;
when s_release_admin =>
sig_ac_req <= s_ac_idle;
if dgrb_ac_access_gnt = '0' and sig_dimm_driving_dq = '0' then
sig_dgrb_state <= s_idle;
end if;
when s_rdata_valid_align =>
sig_ac_req <= s_ac_read_rdv;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
if sig_dimm_driving_dq = '1' then
-- only do comparison if rdata_valid is all 'ones'
if rdata_valid /= std_logic_vector(to_unsigned(0, DWIDTH_RATIO/2)) then
-- rdata_valid is all ones
if rdata_valid_aligned(rdata, rdata_valid) = '1' then
-- success: rdata_valid and rdata are properly aligned
sig_dgrb_state <= s_release_admin;
else
-- misaligned: bring in rdata_valid by a clock cycle
seq_rdata_valid_lat_dec <= '1';
end if;
end if;
end if;
when s_adv_rd_lat_setup =>
-- wait for sig_doing_rd to go high
sig_ac_req <= s_ac_read_rdv;
if sig_dgrb_state /= sig_dgrb_last_state then
rd_lat <= (others => '0');
sig_count <= 0;
elsif sig_dimm_driving_dq = '1' and sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) = '1' then
-- a read has started: start counter
sig_dgrb_state <= s_adv_rd_lat;
end if;
when s_adv_rd_lat =>
sig_ac_req <= s_ac_read_rdv;
if sig_dimm_driving_dq = '1' then
if sig_count >= 2**rd_lat'length then
report dgrb_report_prefix & "maximum read latency exceeded while waiting for rdata_valid" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_MAX_RD_LAT_EXCEEDED,sig_cmd_result'length));
end if;
if rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- have found the read latency
sig_dgrb_state <= s_release_admin;
else
sig_count <= sig_count + 1;
end if;
rd_lat <= std_logic_vector(to_unsigned(sig_count, rd_lat'length));
end if;
when s_adv_wd_lat =>
sig_ac_req <= s_ac_read_wd_lat;
if sig_dgrb_state /= sig_dgrb_last_state then
sig_wd_lat <= (others => '0');
else
if sig_dimm_driving_dq = '1' and rdata_valid /= std_logic_vector(to_unsigned(0, rdata_valid'length)) then
-- construct wd_lat using data from the lowest addresses
-- wd_lat <= rdata(MEM_IF_DQ_PER_DQS - 1 downto 0);
sig_wd_lat <= wd_lat_from_rdata(rdata);
sig_dgrb_state <= s_release_admin;
-- check data integrity
for i in 1 to MEM_IF_DWIDTH/set_wlat_dq_rep_width - 1 loop
-- wd_lat is copied across MEM_IF_DWIDTH bits in fields of width MEM_IF_DQ_PER_DQS.
-- All of these fields must have the same value or it is an error.
-- only check if byte lane not disabled
if cal_byte_lanes((i*set_wlat_dq_rep_width)/MEM_IF_DQ_PER_DQS) = '1' then
if rdata(set_wlat_dq_rep_width - 1 downto 0) /= rdata((i+1)*set_wlat_dq_rep_width - 1 downto i*set_wlat_dq_rep_width) then
-- signal write latency different between DQS groups
report dgrb_report_prefix & "the write latency read from memory is different accross dqs groups" severity cal_fail_sev_level;
sig_cmd_err <= '1';
sig_cmd_result <= std_logic_vector(to_unsigned(C_ERR_WD_LAT_DISAGREEMENT, sig_cmd_result'length));
end if;
end if;
end loop;
-- check if ac_nt alignment is ok
-- in this condition all DWIDTH_RATIO copies of rdata should be identical
dgrb_ctrl_ac_nt_good <= '1';
if DWIDTH_RATIO /= 2 then
for j in 0 to DWIDTH_RATIO/2 - 1 loop
if rdata(j*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto j*MEM_IF_DWIDTH) /= rdata((j+2)*MEM_IF_DWIDTH + MEM_IF_DQ_PER_DQS - 1 downto (j+2)*MEM_IF_DWIDTH) then
dgrb_ctrl_ac_nt_good <= '0';
end if;
end loop;
end if;
end if;
end if;
when s_poa_cal =>
-- Request the address/command block begins reading the "M"
-- training pattern here. There is no provision for doing
-- refreshes so this limits the time spent in this state
-- to 9 x tREFI (by the DDR2 JEDEC spec). Instead of the
-- maximum value, a maximum "safe" time in this postamble
-- state is chosen to be tpoamax = 5 x tREFI = 5 x 3.9us.
-- When entering this s_poa_cal state it must be guaranteed
-- that the number of stacked refreshes is at maximum.
--
-- Minimum clock freq supported by DRAM is fck,min=125MHz.
-- Each adjustment to postamble latency requires 16*clock
-- cycles (time to read "M" training pattern twice) so
-- maximum number of adjustments to POA latency (n) is:
--
-- n = (5 x trefi x fck,min) / 16
-- = (5 x 3.9us x 125MHz) / 16
-- ~ 152
--
-- Postamble latency must be adjusted less than 152 cycles
-- to meet this requirement.
--
sig_ac_req <= s_ac_read_poa_mtp;
if sig_poa_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when s_track =>
if sig_trk_ack = '1' then
sig_dgrb_state <= s_release_admin;
end if;
when others => null;
report dgrb_report_prefix & "undefined state" severity failure;
sig_dgrb_state <= s_idle;
end case;
-- default if not calibrating go to idle state via s_release_admin
if ctrl_dgrb_r.command = cmd_idle and
sig_dgrb_state /= s_idle and
sig_dgrb_state /= s_release_admin then
sig_dgrb_state <= s_release_admin;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- metastability hardening of potentially async phs_shift_busy signal
--
-- Triple register it for metastability hardening. This process
-- creates the shift register. Also add a sig_phs_shft_busy and
-- an sig_phs_shft_busy_1t echo because various other processes find
-- this useful.
-- ------------------------------------------------------------------
phs_shft_busy_reg: block
signal phs_shft_busy_1r : std_logic;
signal phs_shft_busy_2r : std_logic;
signal phs_shft_busy_3r : std_logic;
begin
phs_shift_busy_sync : process (clk, rst_n)
begin
if rst_n = '0' then
sig_phs_shft_busy <= '0';
sig_phs_shft_busy_1t <= '0';
phs_shft_busy_1r <= '0';
phs_shft_busy_2r <= '0';
phs_shft_busy_3r <= '0';
sig_phs_shft_start <= '0';
sig_phs_shft_end <= '0';
elsif rising_edge(clk) then
sig_phs_shft_busy_1t <= phs_shft_busy_3r;
sig_phs_shft_busy <= phs_shft_busy_2r;
-- register the below to reduce fan out on sig_phs_shft_busy and sig_phs_shft_busy_1t
sig_phs_shft_start <= phs_shft_busy_3r or phs_shft_busy_2r;
sig_phs_shft_end <= phs_shft_busy_3r and not(phs_shft_busy_2r);
phs_shft_busy_3r <= phs_shft_busy_2r;
phs_shft_busy_2r <= phs_shft_busy_1r;
phs_shft_busy_1r <= phs_shft_busy;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- PLL reconfig MUX
--
-- switches PLL Reconfig input between tracking and resync blocks
-- ------------------------------------------------------------------
pll_reconf_mux : process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_select <= (others => '0');
seq_pll_start_reconfig <= '0';
elsif rising_edge(clk) then
if sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_reset_cdvw then
seq_pll_select <= pll_resync_clk_index;
seq_pll_inc_dec_n <= sig_rsc_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_rsc_pll_start_reconfig;
elsif sig_dgrb_state = s_track then
seq_pll_select <= sig_trk_pll_select;
seq_pll_inc_dec_n <= sig_trk_pll_inc_dec_n;
seq_pll_start_reconfig <= sig_trk_pll_start_reconfig;
else
seq_pll_select <= pll_measure_clk_index;
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- Centre of data valid window calculation block
--
-- This block handles the sharing of the centre of window calculation
-- logic between the rsc and trk operations. Functions defined in the
-- header of this entity are called to do this.
-- ------------------------------------------------------------------
cdvw_block : block
signal sig_cdvw_calc_1t : std_logic;
begin
-- purpose: manages centre of data valid window calculations
-- type : sequential
-- inputs : clk, rst_n
-- outputs: sig_cdvw_state
cdvw_proc: process (clk, rst_n)
variable v_cdvw_state : t_window_processing;
variable v_start_calc : std_logic;
variable v_shift_in : std_logic;
variable v_phase : std_logic;
begin -- process cdvw_proc
if rst_n = '0' then -- asynchronous reset (active low)
sig_cdvw_state <= defaults;
sig_cdvw_calc_1t <= '0';
elsif rising_edge(clk) then -- rising clock edge
v_cdvw_state := sig_cdvw_state;
case sig_dgrb_state is
when s_track =>
v_start_calc := sig_trk_cdvw_calc;
v_phase := sig_trk_cdvw_phase;
v_shift_in := sig_trk_cdvw_shift_in;
when s_read_mtp | s_seek_cdvw | s_test_phases =>
v_start_calc := sig_rsc_cdvw_calc;
v_phase := sig_rsc_cdvw_phase;
v_shift_in := sig_rsc_cdvw_shift_in;
when others =>
v_start_calc := '0';
v_phase := '0';
v_shift_in := '0';
end case;
if sig_dgrb_state = s_reset_cdvw or (sig_dgrb_state = s_track and sig_dgrb_last_state /= s_track) then
-- reset *C*entre of *D*ata *V*alid *W*indow
v_cdvw_state := defaults;
elsif sig_cdvw_calc_1t /= '1' and v_start_calc = '1' then
initialise_window_for_proc(v_cdvw_state);
elsif v_cdvw_state.status = calculating then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, PLL_STEPS_PER_CYCLE);
else -- can be a 720 degrees sweep
find_centre_of_largest_data_valid_window(v_cdvw_state, c_max_phase_shifts);
end if;
elsif v_shift_in = '1' then
if sig_dgrb_state = s_track then -- ensure 360 degrees sweep
shift_in(v_cdvw_state, v_phase, PLL_STEPS_PER_CYCLE);
else
shift_in(v_cdvw_state, v_phase, c_max_phase_shifts);
end if;
end if;
sig_cdvw_calc_1t <= v_start_calc;
sig_cdvw_state <= v_cdvw_state;
end if;
end process cdvw_proc;
end block;
-- ------------------------------------------------------------------
-- block for resync calculation.
--
-- This block implements the following:
-- 1) Control logic for the rsc slave state machine
-- 2) Processing of resync operations - through reports form cdvw block and
-- test pattern match blocks
-- 3) Shifting of the resync phase for rsc sweeps
-- 4) Writing of results to iram (optional)
-- ------------------------------------------------------------------
rsc_block : block
signal sig_rsc_state : t_resync_state;
signal sig_rsc_last_state : t_resync_state;
signal sig_num_phase_shifts : natural range c_max_phase_shifts - 1 downto 0;
signal sig_rewind_direction : std_logic;
signal sig_count : natural range 0 to 2**8 - 1;
signal sig_test_dq_expired : std_logic;
signal sig_chkd_all_dq_pins : std_logic;
-- prompts to write data to iram
signal sig_dgrb_iram : t_iram_push; -- internal copy of dgrb to iram control signals
signal sig_rsc_push_rrp_sweep : std_logic; -- push result of a rrp sweep pass (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_pass : std_logic; -- result of a rrp sweep result (for cmd_rrp_sweep)
signal sig_rsc_push_rrp_seek : std_logic; -- write seek results (for cmd_rrp_seek / cmd_read_mtp states)
signal sig_rsc_push_footer : std_logic; -- write a footer
signal sig_dq_pin_ctr_r : natural range 0 to MEM_IF_DWIDTH - 1; -- registered version of dq_pin_ctr
signal sig_rsc_curr_phase : natural range 0 to c_max_phase_shifts - 1; -- which phase is being processed
signal sig_iram_idle : std_logic; -- track if iram currently writing data
signal sig_mtp_match_en : std_logic;
-- current byte lane disabled?
signal sig_curr_byte_ln_dis : std_logic;
signal sig_iram_wds_req : integer; -- words required for a given iram dump (used to locate where to write footer)
begin
-- When using DQS capture or not at full-rate only match on "even" clock cycles.
sig_mtp_match_en <= active_high(sig_ac_even = '1' or MEM_IF_DQS_CAPTURE = 0 or DWIDTH_RATIO /= 2);
-- register current byte lane disable mux for speed
byte_lane_dis: process (clk, rst_n)
begin
if rst_n = '0' then
sig_curr_byte_ln_dis <= '0';
elsif rising_edge(clk) then
sig_curr_byte_ln_dis <= cal_byte_lanes(sig_dq_pin_ctr/MEM_IF_DQ_PER_DQS);
end if;
end process;
-- check if all dq pins checked in rsc sweep
chkd_dq : process (clk, rst_n)
begin
if rst_n = '0' then
sig_chkd_all_dq_pins <= '0';
elsif rising_edge(clk) then
if sig_dq_pin_ctr = 0 then
sig_chkd_all_dq_pins <= '1';
else
sig_chkd_all_dq_pins <= '0';
end if;
end if;
end process;
-- main rsc process
rsc_proc : process (clk, rst_n)
-- these are temporary variables which should not infer FFs and
-- are not guaranteed to be initialized by s_rsc_idle.
variable v_rdata_correct : std_logic;
variable v_phase_works : std_logic;
begin
if rst_n = '0' then
-- initialise signals
sig_rsc_state <= s_rsc_idle;
sig_rsc_last_state <= s_rsc_idle;
sig_dq_pin_ctr <= 0;
sig_num_phase_shifts <= c_max_phase_shifts - 1; -- want c_max_phase_shifts-1 inc / decs of phase
sig_count <= 0;
sig_test_dq_expired <= '0';
v_phase_works := '0';
-- interface to other processes to tell them when we are done.
sig_rsc_ack <= '0';
sig_rsc_err <= '0';
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, c_command_result_len));
-- centre of data valid window functions
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
-- set up PLL reconfig interface controls
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- True when access to the ac_block is required.
sig_rsc_ac_access_req <= '0';
-- default values on centre and size of data valid window
if SIM_TIME_REDUCTIONS = 1 then
cal_codvw_phase <= std_logic_vector(to_unsigned(PRESET_CODVW_PHASE, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(PRESET_CODVW_SIZE, 8));
else
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
end if;
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
codvw_grt_one_dvw <= '0';
elsif rising_edge(clk) then
-- default values assigned to some signals
sig_rsc_ack <= '0';
sig_rsc_cdvw_phase <= '0';
sig_rsc_cdvw_shift_in <= '0';
sig_rsc_cdvw_calc <= '0';
sig_rsc_pll_start_reconfig <= '0';
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rewind_direction <= c_pll_phs_dec;
-- by default don't ask the resync block to read anything
sig_rsc_ac_access_req <= '0';
sig_rsc_push_rrp_sweep <= '0';
sig_rsc_push_rrp_seek <= '0';
sig_rsc_push_rrp_pass <= '0';
sig_rsc_push_footer <= '0';
sig_test_dq_expired <= '0';
-- resync state machine
case sig_rsc_state is
when s_rsc_idle =>
-- initialize those signals we are ready to use.
sig_dq_pin_ctr <= 0;
sig_count <= 0;
if sig_rsc_state = sig_rsc_last_state then -- avoid transition when acknowledging a command has finished
if sig_rsc_req = s_rsc_test_phase then
sig_rsc_state <= s_rsc_test_phase;
elsif sig_rsc_req = s_rsc_cdvw_calc then
sig_rsc_state <= s_rsc_cdvw_calc;
elsif sig_rsc_req = s_rsc_seek_cdvw then
sig_rsc_state <= s_rsc_seek_cdvw;
elsif sig_rsc_req = s_rsc_reset_cdvw then
sig_rsc_state <= s_rsc_reset_cdvw;
else
sig_rsc_state <= s_rsc_idle;
end if;
end if;
when s_rsc_next_phase =>
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- PLL phase shift started - so stop requesting a shift
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_state <= s_rsc_test_phase;
end if;
when s_rsc_test_phase =>
v_phase_works := '1';
-- Note: For single pin single CS calibration set sig_dq_pin_ctr to 0 to
-- ensure that only 1 pin calibrated
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
if single_bit_cal = '1' then
sig_dq_pin_ctr <= 0;
else
sig_dq_pin_ctr <= MEM_IF_DWIDTH-1;
end if;
when s_rsc_wait_for_idle_dimm =>
if sig_dimm_driving_dq = '0' then
sig_rsc_state <= s_rsc_flush_datapath;
end if;
when s_rsc_flush_datapath =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= c_max_read_lat - 1;
else
if sig_dimm_driving_dq = '1' then
if sig_count = 0 then
sig_rsc_state <= s_rsc_test_dq;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_test_dq =>
sig_rsc_ac_access_req <= '1';
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state.
sig_count <= 2*c_cal_mtp_t;
else
if sig_dimm_driving_dq = '1' then
if (
(sig_mtp_match = '1' and sig_mtp_match_en = '1') or -- have a pattern match
(sig_test_dq_expired = '1') or -- time in this phase has expired.
sig_curr_byte_ln_dis = '0' -- byte lane disabled
) then
v_phase_works := v_phase_works and ((sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis));
sig_rsc_push_rrp_sweep <= '1';
sig_rsc_push_rrp_pass <= (sig_mtp_match and sig_mtp_match_en) or (not sig_curr_byte_ln_dis);
if sig_chkd_all_dq_pins = '1' then
-- finished checking all dq pins.
-- done checking this phase.
-- shift phase status into
sig_rsc_cdvw_phase <= v_phase_works;
sig_rsc_cdvw_shift_in <= '1';
if sig_num_phase_shifts /= 0 then
-- there are more phases to test so shift to next phase
sig_rsc_state <= s_rsc_next_phase;
else
-- no more phases to check.
-- clean up after ourselves by
-- going into s_rsc_rewind_phase
sig_rsc_state <= s_rsc_rewind_phase;
sig_rewind_direction <= c_pll_phs_dec;
sig_num_phase_shifts <= c_max_phase_shifts - 1;
end if;
else
-- shift to next dq pin
if MEM_IF_DWIDTH > 71 and -- if >= 72 pins then:
(sig_dq_pin_ctr mod 64) = 0 then -- ensure refreshes at least once every 64 pins
sig_rsc_state <= s_rsc_wait_for_idle_dimm;
else -- otherwise continue sweep
sig_rsc_state <= s_rsc_flush_datapath;
end if;
sig_dq_pin_ctr <= sig_dq_pin_ctr - 1;
end if;
else
sig_count <= sig_count - 1;
if sig_count = 1 then
sig_test_dq_expired <= '1';
end if;
end if;
end if;
end if;
when s_rsc_reset_cdvw =>
sig_rsc_state <= s_rsc_rewind_phase;
-- determine the amount to rewind by (may be wind forward depending on tracking behaviour)
if to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift < 0 then
sig_num_phase_shifts <= - (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_inc;
else
sig_num_phase_shifts <= (to_integer(unsigned(cal_codvw_phase)) + sig_trk_rsc_drift);
sig_rewind_direction <= c_pll_phs_dec;
end if;
-- reset the calibrated phase and size to zero (because un-doing prior calibration here)
cal_codvw_phase <= (others => '0');
cal_codvw_size <= (others => '0');
when s_rsc_rewind_phase =>
-- rewinds the resync PLL by sig_num_phase_shifts steps and returns to idle state
if sig_num_phase_shifts = 0 then
-- no more steps to take off, go to next state
sig_num_phase_shifts <= c_max_phase_shifts - 1;
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
sig_rsc_pll_inc_dec_n <= sig_rewind_direction;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_busy = '1' then
-- inhibit a phase shift if phase shift is busy.
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_busy_1t = '1' and sig_phs_shft_busy /= '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_num_phase_shifts <= sig_num_phase_shifts - 1;
sig_rsc_pll_start_reconfig <= '0';
end if;
end if;
when s_rsc_cdvw_calc =>
if sig_rsc_state /= sig_rsc_last_state then
if sig_dgrb_state = s_read_mtp then
report dgrb_report_prefix & "gathered resync phase samples (for mtp alignment " & natural'image(current_mtp_almt) & ") is DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
else
report dgrb_report_prefix & "gathered resync phase samples DGRB_PHASE_SAMPLES: " & str(sig_cdvw_state.working_window) severity note;
end if;
sig_rsc_cdvw_calc <= '1'; -- begin calculating result
else
sig_rsc_state <= s_rsc_cdvw_wait;
end if;
when s_rsc_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
-- a result has been reached.
if sig_dgrb_state = s_read_mtp then -- if doing mtp alignment then skip setting phase
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
else
if sig_cdvw_state.status = valid_result then
-- calculation successfully found a
-- data-valid window to seek to.
sig_rsc_state <= s_rsc_seek_cdvw;
sig_rsc_result <= std_logic_vector(to_unsigned(C_SUCCESS, sig_rsc_result'length));
-- If more than one data valid window was seen, then set the result code :
if (sig_cdvw_state.windows_seen > 1) then
report dgrb_report_prefix & "Warning : multiple data-valid windows found, largest chosen." severity note;
codvw_grt_one_dvw <= '1';
else
report dgrb_report_prefix & "data-valid window found successfully." severity note;
end if;
else
-- calculation failed to find a data-valid window.
report dgrb_report_prefix & "couldn't find a data-valid window in resync." severity warning;
sig_rsc_ack <= '1';
sig_rsc_err <= '1';
sig_rsc_state <= s_rsc_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when multiple_equal_windows =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_rsc_result'length));
when no_valid_phases =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_rsc_result'length));
when others =>
sig_rsc_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_rsc_result'length));
end case;
end if;
end if;
-- signal to write a rrp_sweep result to iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
sig_rsc_push_rrp_seek <= '1';
end if;
end if;
when s_rsc_seek_cdvw =>
if sig_rsc_state /= sig_rsc_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_count <= sig_cdvw_state.largest_window_centre;
else
if sig_count = 0 or
((MEM_IF_DQS_CAPTURE = 1 and DWIDTH_RATIO = 2) and
sig_count = PLL_STEPS_PER_CYCLE) -- if FR and DQS capture ensure within 0-360 degrees phase
then
-- ready to transition to next state
if GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if iram present hold off until access finished
sig_rsc_state <= s_rsc_wait_iram;
else
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
end if;
-- return largest window centre and size in the result
-- perform cal_codvw phase / size update only if a valid result is found
if sig_cdvw_state.status = valid_result then
cal_codvw_phase <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8));
cal_codvw_size <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
end if;
-- leaving sig_rsc_err or sig_rsc_result at
-- their default values (of success)
else
sig_rsc_pll_inc_dec_n <= c_pll_phs_inc;
-- request a phase shift
sig_rsc_pll_start_reconfig <= '1';
if sig_phs_shft_start = '1' then
-- inhibit a phase shift if phase shift is busy
sig_rsc_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
-- we've just successfully removed a phase step
-- decrement counter
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_rsc_wait_iram =>
-- hold off check 1 clock cycle to enable last rsc push operations to start
if sig_rsc_state = sig_rsc_last_state then
if sig_iram_idle = '1' then
sig_rsc_ack <= '1';
sig_rsc_state <= s_rsc_idle;
if sig_dgrb_state = s_test_phases or
sig_dgrb_state = s_seek_cdvw or
sig_dgrb_state = s_read_mtp then
sig_rsc_push_footer <= '1';
end if;
end if;
end if;
when others =>
null;
end case;
sig_rsc_last_state <= sig_rsc_state;
end if;
end process;
-- write results to the iram
iram_push: process (clk, rst_n)
begin
if rst_n = '0' then
sig_dgrb_iram <= defaults;
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_iram_wds_req <= 0;
elsif rising_edge(clk) then
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
if sig_dgrb_iram.iram_write = '1' and sig_dgrb_iram.iram_done = '1' then
report dgrb_report_prefix & "iram_done and iram_write signals concurrently set - iram contents may be corrupted" severity failure;
end if;
if sig_dgrb_iram.iram_write = '0' and sig_dgrb_iram.iram_done = '0' then
sig_iram_idle <= '1';
else
sig_iram_idle <= '0';
end if;
-- registered sig_dq_pin_ctr to align with rrp_sweep result
sig_dq_pin_ctr_r <= sig_dq_pin_ctr;
-- calculate current phase (registered to align with rrp_sweep result)
sig_rsc_curr_phase <= (c_max_phase_shifts - 1) - sig_num_phase_shifts;
-- serial push of rrp_sweep results into memory
if sig_rsc_push_rrp_sweep = '1' then
-- signal an iram write and track a write pending
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
-- if not single_bit_cal then pack pin phase results in MEM_IF_DWIDTH word blocks
if single_bit_cal = '1' then
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32);
sig_iram_wds_req <= iram_wd_for_one_pin_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
else
sig_dgrb_iram.iram_wordnum <= sig_dq_pin_ctr_r + (sig_rsc_curr_phase/32) * MEM_IF_DWIDTH;
sig_iram_wds_req <= iram_wd_for_full_rrp( DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE); -- note total word requirement
end if;
-- check if current pin and phase passed:
sig_dgrb_iram.iram_pushdata(0) <= sig_rsc_push_rrp_pass;
-- bit offset is modulo phase
sig_dgrb_iram.iram_bitnum <= sig_rsc_curr_phase mod 32;
end if;
-- write result of rrp_calc to iram when completed
if sig_rsc_push_rrp_seek = '1' then -- a result found
sig_dgrb_iram.iram_write <= '1';
sig_iram_idle <= '0';
sig_dgrb_iram.iram_wordnum <= 0;
sig_iram_wds_req <= 1; -- note total word requirement
if sig_cdvw_state.status = valid_result then -- result is valid
sig_dgrb_iram.iram_pushdata <= x"0000" &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_centre, 8)) &
std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size, 8));
else -- invalid result (error code communicated elsewhere)
sig_dgrb_iram.iram_pushdata <= x"FFFF" & -- signals an error condition
x"0000";
end if;
end if;
-- when stage finished write footer
if sig_rsc_push_footer = '1' then
sig_dgrb_iram.iram_done <= '1';
sig_iram_idle <= '0';
-- set address location of footer
sig_dgrb_iram.iram_wordnum <= sig_iram_wds_req;
end if;
-- if write completed deassert iram_write and done signals
if iram_push_done = '1' then
sig_dgrb_iram.iram_write <= '0';
sig_dgrb_iram.iram_done <= '0';
end if;
else
sig_iram_idle <= '0';
sig_dq_pin_ctr_r <= 0;
sig_rsc_curr_phase <= 0;
sig_dgrb_iram <= defaults;
end if;
end if;
end process;
-- concurrently assign sig_dgrb_iram to dgrb_iram
dgrb_iram <= sig_dgrb_iram;
end block; -- resync calculation
-- ------------------------------------------------------------------
-- test pattern match block
--
-- This block handles the sharing of logic for test pattern matching
-- which is used in resync and postamble calibration / code blocks
-- ------------------------------------------------------------------
tp_match_block : block
--
-- Ascii Waveforms:
--
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- delayed_dqs |____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ ; _______ ; _______ ; _______ ; _______ _______
-- XXXXX / \ / \ / \ / \ / \ / \
-- c0,c1 XXXXXX A B X C D X E F X G H X I J X L M X captured data
-- XXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____; ____; ____ ____ ____ ____ ____
-- 180-resync_clk |____| |____| |____| |____| |____| |____| | 180deg shift from delayed dqs
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; _______ _______ _______ _______ _______ ____
-- XXXXXXXXXX / \ / \ / \ / \ / \ /
-- 180-r0,r1 XXXXXXXXXXX A B X C D X E F X G H X I J X L resync data
-- XXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____
-- 360-resync_clk ____| |____| |____| |____| |____| |____| |____|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ ; _______ ; _______ ; _______ ; _______
-- XXXXXXXXXXXXXXX / \ / \ / \ / \ / \
-- 360-r0,r1 XXXXXXXXXXXXXXXX A B X C D X E F X G H X I J X resync data
-- XXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ____ ____ ____ ____ ____ ____ ____
-- 540-resync_clk |____| |____| |____| |____| |____| |____| |
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; _______ _______ _______ _______ ____
-- XXXXXXXXXXXXXXXXXXX / \ / \ / \ / \ /
-- 540-r0,r1 XXXXXXXXXXXXXXXXXXXX A B X C D X E F X G H X I resync data
-- XXXXXXXXXXXXXXXXXXX \_______/ \_______/ \_______/ \_______/ \____
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ;____ ____ ____ ____ ____ ____
-- phy_clk |____| |____| |____| |____| |____| |____| |____|
--
-- 0 1 2 3 4 5 6
--
--
-- |<- Aligned Data ->|
-- phy_clk 180-r0,r1 540-r0,r1 sig_mtp_match_en (generated from sig_ac_even)
-- 0 XXXXXXXX XXXXXXXX '1'
-- 1 XXXXXXAB XXXXXXXX '0'
-- 2 XXXXABCD XXXXXXAB '1'
-- 3 XXABCDEF XXXXABCD '0'
-- 4 ABCDEFGH XXABCDEF '1'
-- 5 CDEFGHAB ABCDEFGH '0'
--
-- In DQS-based capture, sweeping resync_clk from 180 degrees to 360
-- does not necessarily result in a failure because the setup/hold
-- requirements are so small. The data comparison needs to fail when
-- the resync_clk is shifted more than 360 degrees. The
-- sig_mtp_match_en signal allows the sequencer to blind itself
-- training pattern matches that occur above 360 degrees.
--
--
--
--
--
-- Asserts sig_mtp_match.
--
-- Data comes in from rdata and is pushed into a two-bit wide shift register.
-- It is a critical assumption that the rdata comes back byte aligned.
--
--
--sig_mtp_match_valid
-- rdata_valid (shift-enable)
-- |
-- |
-- +-----------------------+-----------+------------------+
-- ___ | | |
-- dq(0) >---| \ | Shift Register |
-- dq(1) >---| \ +------+ +------+ +------------------+
-- dq(2) >---| )--->| D(0) |-+->| D(1) |-+->...-+->| D(c_cal_mtp_len - 1) |
-- ... | / +------+ | +------+ | | +------------------+
-- dq(n-1) >---|___/ +-----------++-...-+
-- | || +---+
-- | (==)--------> sig_mtp_match_0t ---->| |-->sig_mtp_match_1t-->sig_mtp_match
-- | || +---+
-- | +-----------++...-+
-- sig_dq_pin_ctr >-+ +------+ | +------+ | | +------------------+
-- | P(0) |-+ | P(1) |-+ ...-+->| P(c_cal_mtp_len - 1) |
-- +------+ +------+ +------------------+
--
--
--
--
signal sig_rdata_current_pin : std_logic_vector(c_cal_mtp_len - 1 downto 0);
-- A fundamental assumption here is that rdata_valid is all
-- ones or all zeros - not both.
signal sig_rdata_valid_1t : std_logic; -- rdata_valid delayed by 1 clock period.
signal sig_rdata_valid_2t : std_logic; -- rdata_valid delayed by 2 clock periods.
begin
rdata_valid_1t_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_valid_1t <= '0';
sig_rdata_valid_2t <= '0';
elsif rising_edge(clk) then
sig_rdata_valid_2t <= sig_rdata_valid_1t;
sig_rdata_valid_1t <= rdata_valid(0);
end if;
end process;
-- MUX data into sig_rdata_current_pin shift register.
rdata_current_pin_proc: process (clk, rst_n)
begin
if rst_n = '0' then
sig_rdata_current_pin <= (others => '0');
elsif rising_edge(clk) then
-- shift old data down the shift register
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO downto 0) <=
sig_rdata_current_pin(sig_rdata_current_pin'high downto DWIDTH_RATIO);
-- shift new data into the bottom of the shift register.
for i in 0 to DWIDTH_RATIO - 1 loop
sig_rdata_current_pin(sig_rdata_current_pin'high - DWIDTH_RATIO + 1 + i) <= rdata(i*MEM_IF_DWIDTH + sig_dq_pin_ctr);
end loop;
end if;
end process;
mtp_match_proc : process (clk, rst_n)
begin
if rst_n = '0' then -- * when at least c_max_read_lat clock cycles have passed
sig_mtp_match <= '0';
elsif rising_edge(clk) then
sig_mtp_match <= '0';
if sig_rdata_current_pin = c_cal_mtp then
sig_mtp_match <= '1';
end if;
end if;
end process;
poa_match_proc : process (clk, rst_n)
-- poa_match_Calibration Strategy
--
-- Ascii Waveforms:
--
-- __ __ __ __ __ __ __ __ __
-- clk __| |__| |__| |__| |__| |__| |__| |__| |__| |
--
-- ; ; ; ;
-- _________________
-- rdata_valid ________| |___________________________
--
-- ; ; ; ;
-- _____
-- poa_match_en ______________________________________| |_______________
--
-- ; ; ; ;
-- _____
-- poa_match XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
--
--
-- Notes:
-- -poa_match is only valid while poa_match_en is asserted.
--
--
--
--
--
--
begin
if rst_n = '0' then
sig_poa_match_en <= '0';
sig_poa_match <= '0';
elsif rising_edge(clk) then
sig_poa_match <= '0';
sig_poa_match_en <= '0';
if sig_rdata_valid_2t = '1' and sig_rdata_valid_1t = '0' then
sig_poa_match_en <= '1';
end if;
if DWIDTH_RATIO = 2 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 6) = "111100" then
sig_poa_match <= '1';
end if;
elsif DWIDTH_RATIO = 4 then
if sig_rdata_current_pin(sig_rdata_current_pin'high downto sig_rdata_current_pin'length - 8) = "11111100" then
sig_poa_match <= '1';
end if;
else
report dgrb_report_prefix & "unsupported DWIDTH_RATIO" severity failure;
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- Postamble calibration
--
-- Implements the postamble slave state machine and collates the
-- processing data from the test pattern match block.
-- ------------------------------------------------------------------
poa_block : block
-- Postamble Calibration Strategy
--
-- Ascii Waveforms:
--
-- c_read_burst_t c_read_burst_t
-- ;<------->; ;<------->;
-- ; ; ; ;
-- __ / / __
-- mem_dq[0] ___________| |_____\ \________| |___
--
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- poa_enable ______| |___\ \_| |___
-- ; ; ; ;
-- ; ; ; ;
-- __ / / ______
-- rdata[0] ___________| |______\ \_______|
-- ; ; ; ;
-- ; ; ; ;
-- ; ; ; ;
-- _ / / _
-- poa_match_en _____________| |___\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / / _
-- poa_match ___________________\ \___________| |_
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _ / /
-- seq_poa_lat_dec _______________| |_\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- / /
-- seq_poa_lat_inc ___________________\ \_______________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
--
-- (1) (2)
--
--
-- (1) poa_enable signal is late, and the zeros on mem_dq after (1)
-- are captured.
-- (2) poa_enable signal is aligned. Zeros following (2) are not
-- captured rdata remains at '1'.
--
-- The DQS capture circuit wth the dqs enable asynchronous set.
--
--
--
-- dqs_en_async_preset ----------+
-- |
-- v
-- +---------+
-- +--|Q SET D|----------- gnd
-- | | <O---+
-- | +---------+ |
-- | |
-- | |
-- +--+---. |
-- |AND )--------+------- dqs_bus
-- delayed_dqs -----+---^
--
--
--
-- _____ _____ _____ _____
-- dqs ____| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- ; ; ; ; ;
-- ; ; ; ;
-- _____ _____ _____ _____
-- delayed_dqs _______| |_____| |_____| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ; ; ; ;
-- ; ______________________________________________________________
-- dqs_en_async_ _____________________________| |_____
-- preset
-- ; ; ; ; ;
-- ; ; ; ; ;
-- _____ _____ _____
-- dqs_bus _______| |_________________| |_____| |_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
--
-- ; ;
-- (1) (2)
--
--
-- Notes:
-- (1) The dqs_bus pulse here comes because the last value of Q
-- is '1' until the first DQS pulse clocks gnd into the FF,
-- brings low the AND gate, and disables dqs_bus. A training
-- pattern could potentially match at this point even though
-- between (1) and (2) there are no dqs_bus triggers. Data
-- is frozen on rdata while awaiting the dqs_bus pulses at
-- (2). For this reason, wait until the first match of the
-- training pattern, and continue reducing latency until it
-- TP no longer matches, then increase latency by one. In
-- this case, dqs_en_async_preset will have its latency
-- reduced by three until the training pattern is not matched,
-- then latency is increased by one.
--
--
--
--
-- Postamble calibration state
type t_poa_state is (
-- decrease poa enable latency by 1 cycle iteratively until 'correct' position found
s_poa_rewind_to_pass,
-- poa cal complete
s_poa_done
);
constant c_poa_lat_cmd_wait : natural := 10; -- Number of clock cycles to wait for lat_inc/lat_dec signal to take effect.
constant c_poa_max_lat : natural := 100; -- Maximum number of allowable latency changes.
signal sig_poa_adjust_count : integer range 0 to 2**8 - 1;
signal sig_poa_state : t_poa_state;
begin
poa_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_poa_ack <= '0';
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
sig_poa_adjust_count <= 0;
sig_poa_state <= s_poa_rewind_to_pass;
elsif rising_edge(clk) then
sig_poa_ack <= '0';
seq_poa_lat_inc_1x <= (others => '0');
seq_poa_lat_dec_1x <= (others => '0');
if sig_dgrb_state = s_poa_cal then
case sig_poa_state is
when s_poa_rewind_to_pass =>
-- In postamble calibration
--
-- Normally, must wait for sig_dimm_driving_dq to be '1'
-- before reading, but by this point in calibration
-- rdata_valid is assumed to be set up properly. The
-- sig_poa_match_en (derived from rdata_valid) is used
-- here rather than sig_dimm_driving_dq.
if sig_poa_match_en = '1' then
if sig_poa_match = '1' then
sig_poa_state <= s_poa_done;
else
seq_poa_lat_dec_1x <= (others => '1');
end if;
sig_poa_adjust_count <= sig_poa_adjust_count + 1;
end if;
when s_poa_done =>
sig_poa_ack <= '1';
end case;
else
sig_poa_state <= s_poa_rewind_to_pass;
sig_poa_adjust_count <= 0;
end if;
assert sig_poa_adjust_count <= c_poa_max_lat
report dgrb_report_prefix & "Maximum number of postamble latency adjustments exceeded."
severity failure;
end if;
end process;
end block;
-- ------------------------------------------------------------------
-- code block for tracking signal generation
--
-- this is used for initial tracking setup (finding a reference window)
-- and periodic tracking operations (PVT compensation on rsc phase)
--
-- A slave trk state machine is described and implemented within the block
-- The mimic path is controlled within this block
-- ------------------------------------------------------------------
trk_block : block
type t_tracking_state is (
-- initialise variables out of reset
s_trk_init,
-- idle state
s_trk_idle,
-- sample data from the mimic path (build window)
s_trk_mimic_sample,
-- 'shift' mimic path phase
s_trk_next_phase,
-- calculate mimic window
s_trk_cdvw_calc,
s_trk_cdvw_wait, -- for results
-- calculate how much mimic window has moved (only entered in periodic tracking)
s_trk_cdvw_drift,
-- track rsc phase (only entered in periodic tracking)
s_trk_adjust_resync,
-- communicate command complete to the master state machine
s_trk_complete
);
signal sig_mmc_seq_done : std_logic;
signal sig_mmc_seq_done_1t : std_logic;
signal mmc_seq_value_r : std_logic;
signal sig_mmc_start : std_logic;
signal sig_trk_state : t_tracking_state;
signal sig_trk_last_state : t_tracking_state;
signal sig_rsc_drift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores total change in rsc phase from first calibration
signal sig_req_rsc_shift : integer range -c_max_rsc_drift_in_phases to c_max_rsc_drift_in_phases; -- stores required shift in rsc phase instantaneously
signal sig_mimic_cdv_found : std_logic;
signal sig_mimic_cdv : integer range 0 to PLL_STEPS_PER_CYCLE; -- centre of data valid window calculated from first mimic-cycle
signal sig_mimic_delta : integer range -PLL_STEPS_PER_CYCLE to PLL_STEPS_PER_CYCLE;
signal sig_large_drift_seen : std_logic;
signal sig_remaining_samples : natural range 0 to 2**8 - 1;
begin
-- advertise the codvw phase shift
process (clk, rst_n)
variable v_length : integer;
begin
if rst_n = '0' then
codvw_trk_shift <= (others => '0');
elsif rising_edge(clk) then
if sig_mimic_cdv_found = '1' then
-- check range
v_length := codvw_trk_shift'length;
codvw_trk_shift <= std_logic_vector(to_signed(sig_rsc_drift, v_length));
else
codvw_trk_shift <= (others => '0');
end if;
end if;
end process;
-- request a mimic sample
mimic_sample_req : process (clk, rst_n)
variable seq_mmc_start_r : std_logic_vector(3 downto 0);
begin
if rst_n = '0' then
seq_mmc_start <= '0';
seq_mmc_start_r := "0000";
elsif rising_edge(clk) then
seq_mmc_start_r(3) := seq_mmc_start_r(2);
seq_mmc_start_r(2) := seq_mmc_start_r(1);
seq_mmc_start_r(1) := seq_mmc_start_r(0);
-- extend sig_mmc_start by one clock cycle
if sig_mmc_start = '1' then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '1';
elsif ( (seq_mmc_start_r(3) = '1') or (seq_mmc_start_r(2) = '1') or (seq_mmc_start_r(1) = '1') or (seq_mmc_start_r(0) = '1') ) then
seq_mmc_start <= '1';
seq_mmc_start_r(0) := '0';
else
seq_mmc_start <= '0';
end if;
end if;
end process;
-- metastability hardening of async mmc_seq_done signal
mmc_seq_req_sync : process (clk, rst_n)
variable v_mmc_seq_done_1r : std_logic;
variable v_mmc_seq_done_2r : std_logic;
variable v_mmc_seq_done_3r : std_logic;
begin
if rst_n = '0' then
sig_mmc_seq_done <= '0';
sig_mmc_seq_done_1t <= '0';
v_mmc_seq_done_1r := '0';
v_mmc_seq_done_2r := '0';
v_mmc_seq_done_3r := '0';
elsif rising_edge(clk) then
sig_mmc_seq_done_1t <= v_mmc_seq_done_3r;
sig_mmc_seq_done <= v_mmc_seq_done_2r;
mmc_seq_value_r <= mmc_seq_value;
v_mmc_seq_done_3r := v_mmc_seq_done_2r;
v_mmc_seq_done_2r := v_mmc_seq_done_1r;
v_mmc_seq_done_1r := mmc_seq_done;
end if;
end process;
-- collect mimic samples as they arrive
shift_in_mmc_seq_value : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
elsif rising_edge(clk) then
sig_trk_cdvw_shift_in <= '0';
sig_trk_cdvw_phase <= '0';
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
sig_trk_cdvw_shift_in <= '1';
sig_trk_cdvw_phase <= mmc_seq_value_r;
end if;
end if;
end process;
-- main tracking state machine
trk_proc : process (clk, rst_n)
begin
if rst_n = '0' then
sig_trk_state <= s_trk_init;
sig_trk_last_state <= s_trk_init;
sig_trk_result <= (others => '0');
sig_trk_err <= '0';
sig_mmc_start <= '0';
sig_trk_pll_select <= (others => '0');
sig_req_rsc_shift <= -c_max_rsc_drift_in_phases;
sig_rsc_drift <= -c_max_rsc_drift_in_phases;
sig_mimic_delta <= -PLL_STEPS_PER_CYCLE;
sig_mimic_cdv_found <= '0';
sig_mimic_cdv <= 0;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_remaining_samples <= 0;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_trk_ack <= '0';
elsif rising_edge(clk) then
sig_trk_pll_select <= pll_measure_clk_index;
sig_trk_pll_start_reconfig <= '0';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_large_drift_seen <= '0';
sig_trk_cdvw_calc <= '0';
sig_trk_ack <= '0';
sig_trk_err <= '0';
sig_trk_result <= (others => '0');
sig_mmc_start <= '0';
-- if no cdv found then reset tracking results
if sig_mimic_cdv_found = '0' then
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
end if;
if sig_dgrb_state = s_track then
-- resync state machine
case sig_trk_state is
when s_trk_init =>
sig_trk_state <= s_trk_idle;
sig_mimic_cdv_found <= '0';
sig_rsc_drift <= 0;
sig_req_rsc_shift <= 0;
sig_mimic_delta <= 0;
when s_trk_idle =>
sig_remaining_samples <= PLL_STEPS_PER_CYCLE; -- ensure a 360 degrees sweep
sig_trk_state <= s_trk_mimic_sample;
when s_trk_mimic_sample =>
if sig_remaining_samples = 0 then
sig_trk_state <= s_trk_cdvw_calc;
else
if sig_trk_state /= sig_trk_last_state then
-- request a sample as soon as we arrive in this state.
-- the default value of sig_mmc_start is zero!
sig_mmc_start <= '1';
end if;
if sig_mmc_seq_done_1t = '1' and sig_mmc_seq_done = '0' then
-- a sample has been collected, go to next PLL phase
sig_remaining_samples <= sig_remaining_samples - 1;
sig_trk_state <= s_trk_next_phase;
end if;
end if;
when s_trk_next_phase =>
sig_trk_pll_start_reconfig <= '1';
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_mimic_sample;
end if;
when s_trk_cdvw_calc =>
if sig_trk_state /= sig_trk_last_state then
-- reset variables we are interested in when we first arrive in this state
sig_trk_cdvw_calc <= '1';
report dgrb_report_prefix & "gathered mimic phase samples DGRB_MIMIC_SAMPLES: " & str(sig_cdvw_state.working_window(sig_cdvw_state.working_window'high downto sig_cdvw_state.working_window'length - PLL_STEPS_PER_CYCLE)) severity note;
else
sig_trk_state <= s_trk_cdvw_wait;
end if;
when s_trk_cdvw_wait =>
if sig_cdvw_state.status /= calculating then
if sig_cdvw_state.status = valid_result then
report dgrb_report_prefix & "mimic window successfully found." severity note;
if sig_mimic_cdv_found = '0' then -- first run of tracking operation
sig_mimic_cdv_found <= '1';
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_complete;
else -- subsequent tracking operation runs
sig_mimic_delta <= sig_mimic_cdv - sig_cdvw_state.largest_window_centre;
sig_mimic_cdv <= sig_cdvw_state.largest_window_centre;
sig_trk_state <= s_trk_cdvw_drift;
end if;
else
report dgrb_report_prefix & "couldn't find a data-valid window for tracking." severity cal_fail_sev_level;
sig_trk_ack <= '1';
sig_trk_err <= '1';
sig_trk_state <= s_trk_idle;
-- set resync result code
case sig_cdvw_state.status is
when no_invalid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_INVALID_PHASES, sig_trk_result'length));
when multiple_equal_windows =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS, sig_trk_result'length));
when no_valid_phases =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_RESYNC_NO_VALID_PHASES, sig_trk_result'length));
when others =>
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_CRITICAL, sig_trk_result'length));
end case;
end if;
end if;
when s_trk_cdvw_drift => -- calculate the drift in rsc phase
-- pipeline stage 1
if abs(sig_mimic_delta) > PLL_STEPS_PER_CYCLE/2 then
sig_large_drift_seen <= '1';
else
sig_large_drift_seen <= '0';
end if;
--pipeline stage 2
if sig_trk_state = sig_trk_last_state then
if sig_large_drift_seen = '1' then
if sig_mimic_delta < 0 then -- anti-clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta + PLL_STEPS_PER_CYCLE;
else -- clockwise movement
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta - PLL_STEPS_PER_CYCLE;
end if;
else
sig_req_rsc_shift <= sig_req_rsc_shift + sig_mimic_delta;
end if;
sig_trk_state <= s_trk_adjust_resync;
end if;
when s_trk_adjust_resync =>
sig_trk_pll_select <= pll_resync_clk_index;
sig_trk_pll_start_reconfig <= '1';
if sig_trk_state /= sig_trk_last_state then
if sig_req_rsc_shift < 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_inc;
sig_req_rsc_shift <= sig_req_rsc_shift + 1;
sig_rsc_drift <= sig_rsc_drift + 1;
elsif sig_req_rsc_shift > 0 then
sig_trk_pll_inc_dec_n <= c_pll_phs_dec;
sig_req_rsc_shift <= sig_req_rsc_shift - 1;
sig_rsc_drift <= sig_rsc_drift - 1;
else
sig_trk_state <= s_trk_complete;
sig_trk_pll_start_reconfig <= '0';
end if;
else
sig_trk_pll_inc_dec_n <= sig_trk_pll_inc_dec_n; -- maintain current value
end if;
if abs(sig_rsc_drift) = c_max_rsc_drift_in_phases then
report dgrb_report_prefix & " a maximum absolute change in resync_clk of " & integer'image(sig_rsc_drift) & " phases has " & LF &
" occurred (since read resynch phase calibration) during tracking" severity cal_fail_sev_level;
sig_trk_err <= '1';
sig_trk_result <= std_logic_vector(to_unsigned(C_ERR_MAX_TRK_SHFT_EXCEEDED, sig_trk_result'length));
end if;
if sig_phs_shft_start = '1' then
sig_trk_pll_start_reconfig <= '0';
end if;
if sig_phs_shft_end = '1' then
sig_trk_state <= s_trk_complete;
end if;
when s_trk_complete =>
sig_trk_ack <= '1';
end case;
sig_trk_last_state <= sig_trk_state;
else
sig_trk_state <= s_trk_idle;
sig_trk_last_state <= s_trk_idle;
end if;
end if;
end process;
rsc_drift: process (sig_rsc_drift)
begin
sig_trk_rsc_drift <= sig_rsc_drift; -- communicate tracking shift to rsc process
end process;
end block; -- tracking signals
-- ------------------------------------------------------------------
-- write-datapath (WDP) ` and on-chip-termination (OCT) signal
-- ------------------------------------------------------------------
wdp_oct : process(clk,rst_n)
begin
if rst_n = '0' then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
elsif rising_edge(clk) then
if ((sig_dgrb_state = s_idle) or (EN_OCT = 0)) then
seq_oct_value <= c_set_oct_to_rs;
dgrb_wdp_ovride <= '0';
else
seq_oct_value <= c_set_oct_to_rt;
dgrb_wdp_ovride <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- handles muxing of error codes to the control block
-- ------------------------------------------------------------------
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgrb_ctrl <= defaults;
elsif rising_edge(clk) then
dgrb_ctrl <= defaults;
if sig_dgrb_state = s_wait_admin and sig_dgrb_last_state = s_idle then
dgrb_ctrl.command_ack <= '1';
end if;
case sig_dgrb_state is
when s_seek_cdvw =>
dgrb_ctrl.command_err <= sig_rsc_err;
dgrb_ctrl.command_result <= sig_rsc_result;
when s_track =>
dgrb_ctrl.command_err <= sig_trk_err;
dgrb_ctrl.command_result <= sig_trk_result;
when others => -- from main state machine
dgrb_ctrl.command_err <= sig_cmd_err;
dgrb_ctrl.command_result <= sig_cmd_result;
end case;
if ctrl_dgrb_r.command = cmd_read_mtp then -- check against command because aligned with command done not command_err
dgrb_ctrl.command_err <= '0';
dgrb_ctrl.command_result <= std_logic_vector(to_unsigned(sig_cdvw_state.largest_window_size,dgrb_ctrl.command_result'length));
end if;
if sig_dgrb_state = s_idle and sig_dgrb_last_state = s_release_admin then
dgrb_ctrl.command_done <= '1';
end if;
end if;
end process;
-- ------------------------------------------------------------------
-- address/command state machine
-- process is commanded to begin reading training patterns.
--
-- implements the address/command slave state machine
-- issues read commands to the memory relative to given calibration
-- stage being implemented
-- burst length is dependent on memory type
-- ------------------------------------------------------------------
ac_block : block
-- override the calibration burst length for DDR3 device support
-- (requires BL8 / on the fly setting in MR in admin block)
function set_read_bl ( memtype: in string ) return natural is
begin
if memtype = "DDR3" then
return 8;
elsif memtype = "DDR" or memtype = "DDR2" then
return c_cal_burst_len;
else
report dgrb_report_prefix & " a calibration burst length choice has not been set for memory type " & memtype severity failure;
end if;
return 0;
end function;
-- parameterisation of the read algorithm by burst length
constant c_poa_addr_width : natural := 6;
constant c_cal_read_burst_len : natural := set_read_bl(MEM_IF_MEMTYPE);
constant c_bursts_per_btp : natural := c_cal_mtp_len / c_cal_read_burst_len;
constant c_read_burst_t : natural := c_cal_read_burst_len / DWIDTH_RATIO;
constant c_max_rdata_valid_lat : natural := 50*(c_cal_read_burst_len / DWIDTH_RATIO); -- maximum latency that rdata_valid can ever have with respect to doing_rd
constant c_rdv_ones_rd_clks : natural := (c_max_rdata_valid_lat + c_read_burst_t) / c_read_burst_t; -- number of cycles to read ones for before a pulse of zeros
-- array of burst training pattern addresses
-- here the MTP is used in this addressing
subtype t_btp_addr is natural range 0 to 2 ** MEM_IF_ADDR_WIDTH - 1;
type t_btp_addr_array is array (0 to c_bursts_per_btp - 1) of t_btp_addr;
-- default values
function defaults return t_btp_addr_array is
variable v_btp_array : t_btp_addr_array;
begin
for i in 0 to c_bursts_per_btp - 1 loop
v_btp_array(i) := 0;
end loop;
return v_btp_array;
end function;
-- load btp array addresses
-- Note: this scales to burst lengths of 2, 4 and 8
-- the settings here are specific to the choice of training pattern and need updating if the pattern changes
function set_btp_addr (mtp_almt : natural ) return t_btp_addr_array is
variable v_addr_array : t_btp_addr_array;
begin
for i in 0 to 8/c_cal_read_burst_len - 1 loop
-- set addresses for xF5 data
v_addr_array((c_bursts_per_btp - 1) - i) := MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + i*c_cal_read_burst_len;
-- set addresses for x30 data (based on mtp alignment)
if mtp_almt = 0 then
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + i*c_cal_read_burst_len;
else
v_addr_array((c_bursts_per_btp - 1) - (8/c_cal_read_burst_len + i)) := MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + i*c_cal_read_burst_len;
end if;
end loop;
return v_addr_array;
end function;
function find_poa_cycle_period return natural is
-- Returns the period over which the postamble reads
-- repeat in c_read_burst_t units.
variable v_num_bursts : natural;
begin
v_num_bursts := 2 ** c_poa_addr_width / c_read_burst_t;
if v_num_bursts * c_read_burst_t < 2**c_poa_addr_width then
v_num_bursts := v_num_bursts + 1;
end if;
v_num_bursts := v_num_bursts + c_bursts_per_btp + 1;
return v_num_bursts;
end function;
function get_poa_burst_addr(burst_count : in natural; mtp_almt : in natural) return t_btp_addr is
variable v_addr : t_btp_addr;
begin
if burst_count = 0 then
if mtp_almt = 0 then
v_addr := c_cal_ofs_x30_almt_1;
elsif mtp_almt = 1 then
v_addr := c_cal_ofs_x30_almt_0;
else
report "Unsupported mtp_almt " & natural'image(mtp_almt) severity failure;
end if;
-- address gets incremented by four if in burst-length four.
v_addr := v_addr + (8 - c_cal_read_burst_len);
else
v_addr := c_cal_ofs_zeros;
end if;
return v_addr;
end function;
signal btp_addr_array : t_btp_addr_array; -- burst training pattern addresses
signal sig_addr_cmd_state : t_ac_state;
signal sig_addr_cmd_last_state : t_ac_state;
signal sig_doing_rd_count : integer range 0 to c_read_burst_t - 1;
signal sig_count : integer range 0 to 2**8 - 1;
signal sig_setup : integer range c_max_read_lat downto 0;
signal sig_burst_count : integer range 0 to c_read_burst_t;
begin
-- handles counts for when to begin burst-reads (sig_burst_count)
-- sets sig_dimm_driving_dq
-- sets dgrb_ac_access_req
dimm_driving_dq_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dimm_driving_dq <= '1';
sig_setup <= c_max_read_lat;
sig_burst_count <= 0;
dgrb_ac_access_req <= '0';
sig_ac_even <= '0';
elsif rising_edge(clk) then
sig_dimm_driving_dq <= '0';
if sig_addr_cmd_state /= s_ac_idle and sig_addr_cmd_state /= s_ac_relax then
dgrb_ac_access_req <= '1';
else
dgrb_ac_access_req <= '0';
end if;
case sig_addr_cmd_state is
when s_ac_read_mtp | s_ac_read_rdv | s_ac_read_wd_lat | s_ac_read_poa_mtp =>
sig_ac_even <= not sig_ac_even;
-- a counter that keeps track of when we are ready
-- to issue a burst read. Issue burst read eigvery
-- time we are at zero.
if sig_burst_count = 0 then
sig_burst_count <= c_read_burst_t - 1;
else
sig_burst_count <= sig_burst_count - 1;
end if;
if dgrb_ac_access_gnt /= '1' then
sig_setup <= c_max_read_lat;
else
-- primes reads
-- signal that dimms are driving dq pins after
-- at least c_max_read_lat clock cycles have passed.
--
if sig_setup = 0 then
sig_dimm_driving_dq <= '1';
elsif dgrb_ac_access_gnt = '1' then
sig_setup <= sig_setup - 1;
end if;
end if;
when s_ac_relax =>
sig_dimm_driving_dq <= '1';
sig_burst_count <= 0;
sig_ac_even <= '0';
when others =>
sig_burst_count <= 0;
sig_ac_even <= '0';
end case;
end if;
end process;
ac_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_count <= 0;
sig_addr_cmd_state <= s_ac_idle;
sig_addr_cmd_last_state <= s_ac_idle;
sig_doing_rd_count <= 0;
sig_addr_cmd <= reset(c_seq_addr_cmd_config);
btp_addr_array <= defaults;
sig_doing_rd <= (others => '0');
elsif rising_edge(clk) then
assert c_cal_mtp_len mod c_cal_read_burst_len = 0 report dgrb_report_prefix & "burst-training pattern length must be a multiple of burst-length." severity failure;
assert MEM_IF_CAL_BANK < 2**MEM_IF_BANKADDR_WIDTH report dgrb_report_prefix & "MEM_IF_CAL_BANK out of range." severity failure;
assert MEM_IF_CAL_BASE_COL < 2**MEM_IF_ADDR_WIDTH - 1 - C_CAL_DATA_LEN report dgrb_report_prefix & "MEM_IF_CAL_BASE_COL out of range." severity failure;
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
if sig_ac_req /= sig_addr_cmd_state and sig_addr_cmd_state /= s_ac_idle then
-- and dgrb_ac_access_gnt = '1'
sig_addr_cmd_state <= s_ac_relax;
else
sig_addr_cmd_state <= sig_ac_req;
end if;
if sig_doing_rd_count /= 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= sig_doing_rd_count - 1;
else
sig_doing_rd <= (others => '0');
end if;
case sig_addr_cmd_state is
when s_ac_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
when s_ac_relax =>
-- waits at least c_max_read_lat before returning to s_ac_idle state
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_max_read_lat;
else
if sig_count = 0 then
sig_addr_cmd_state <= s_ac_idle;
else
sig_count <= sig_count - 1;
end if;
end if;
when s_ac_read_mtp =>
-- reads 'more'-training pattern
-- issue read commands for proper addresses
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_bursts_per_btp - 1; -- counts number of bursts in a training pattern
else
sig_doing_rd <= (others => '1');
-- issue a read command every c_read_burst_t clock cycles
if sig_burst_count = 0 then
-- decide which read command to issue
for i in 0 to c_bursts_per_btp - 1 loop
if sig_count = i then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
btp_addr_array(i), -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
end if;
end loop;
-- Set next value of count
if sig_count = 0 then
sig_count <= c_bursts_per_btp - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_poa_mtp =>
-- Postamble rdata/rdata_valid Activity:
--
--
-- (0) (1) (2)
-- ; ; ; ;
-- _________ __ ____________ _____________ _______ _________
-- \ / \ / \ \ \ / \ /
-- (a) rdata[0] 00000000 X 11 X 0000000000 / / 0000000000 X MTP X 00000000
-- _________/ \__/ \____________\ \____________/ \_______/ \_________
-- ; ; ; ;
-- ; ; ; ;
-- _________ / / _________
-- rdata_valid ____| |_____________\ \_____________| |__________
--
-- ;<- (b) ->;<------------(c)------------>; ;
-- ; ; ; ;
--
--
-- This block must issue reads and drive doing_rd to place the above pattern on
-- the rdata and rdata_valid ports. MTP will most likely come back corrupted but
-- the postamble block (poa_block) will make the necessary adjustments to improve
-- matters.
--
-- (a) Read zeros followed by two ones. The two will be at the end of a burst.
-- Assert rdata_valid only during the burst containing the ones.
-- (b) c_read_burst_t clock cycles.
-- (c) Must be greater than but NOT equal to maximum postamble latency clock
-- cycles. Another way: c_min = (max_poa_lat + 1) phy clock cycles. This
-- must also be long enough to allow the postamble block to respond to a
-- the seq_poa_lat_dec_1x signal, but this requirement is less stringent
-- than the first so that we can ignore it.
--
-- The find_poa_cycle_period function should return (b+c)/c_read_burst_t
-- rounded up to the next largest integer.
--
--
-- set burst training pattern (mtp in this case) addresses
btp_addr_array <= set_btp_addr(current_mtp_almt);
-- issue read commands for proper addresses
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= find_poa_cycle_period - 1; -- length of read patter in bursts.
elsif dgrb_ac_access_gnt = '1' then
-- only begin operation once dgrb_ac_access_gnt has been issued
-- otherwise rdata_valid may be asserted when rdasta is not
-- valid.
--
-- *** WARNING: BE SAFE. DON'T LET THIS HAPPEN TO YOU: ***
--
-- ; ; ; ; ; ;
-- ; _______ ; ; _______ ; ; _______
-- XXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX
-- addr/cmd XXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX READ XXXXXXXXXXX
-- XXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- ; ; ; ; ; ; _______
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX / \
-- rdata XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX MTP X
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX \_______/
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________ _________
-- doing_rd ____| |_________| |_________| |__________
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- __________________________________________________
-- ac_accesss_gnt ______________|
-- ; ; ; ; ; ;
-- ; ; ; ; ; ;
-- _________ _________
-- rdata_valid __________________________________| |_________| |
-- ; ; ; ; ; ;
--
-- (0) (1) (2)
--
--
-- Cmmand and doing_rd issued at (0). The doing_rd signal enters the
-- rdata_valid pipe here so that it will return on rdata_valid with the
-- expected latency (at this point in calibration, rdata_valid and adv_rd_lat
-- should be properly calibrated). Unlike doing_rd, since ac_access_gnt is not
-- asserted the READ command at (0) is never actually issued. This results
-- in the situation at (2) where rdata is undefined yet rdata_valid indicates
-- valid data. The moral of this story is to wait for ac_access_gnt = '1'
-- before issuing commands when it is important that rdata_valid be accurate.
--
--
--
--
if sig_burst_count = 0 then
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
get_poa_burst_addr(sig_count, current_mtp_almt),-- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
-- Set doing_rd
if sig_count = 0 then
sig_doing_rd <= (others => '1');
sig_doing_rd_count <= c_read_burst_t - 1; -- Extend doing_rd pulse by this many phy_clk cycles.
end if;
-- Set next value of count
if sig_count = 0 then
sig_count <= find_poa_cycle_period - 1; -- read for one period then relax (no read) for same time period
else
sig_count <= sig_count - 1;
end if;
end if;
end if;
when s_ac_read_rdv =>
assert c_max_rdata_valid_lat mod c_read_burst_t = 0 report dgrb_report_prefix & "c_max_rdata_valid_lat must be a multiple of c_read_burst_t." severity failure;
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
sig_count <= c_rdv_ones_rd_clks - 1;
else
if sig_burst_count = 0 then
if sig_count = 0 then
-- expecting to read ZEROS
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous valid
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ZEROS, -- column
2**current_cs, -- rank
c_cal_read_burst_len, -- burst length
false);
else
-- expecting to read ONES
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + C_CAL_OFS_ONES, -- column address
2**current_cs, -- rank
c_cal_read_burst_len, -- op length
false);
end if;
if sig_count = 0 then
sig_count <= c_rdv_ones_rd_clks - 1;
else
sig_count <= sig_count - 1;
end if;
end if;
if (sig_count = c_rdv_ones_rd_clks - 1 and sig_burst_count = 1) or
(sig_count = 0 and c_read_burst_t = 1) then
-- the last burst read- that was issued was supposed to read only zeros
-- a burst read command will be issued on the next clock cycle
--
-- A long (>= maximim rdata_valid latency) series of burst reads are
-- issued for ONES.
-- Into this stream a single burst read for ZEROs is issued. After
-- the ZERO read command is issued, rdata_valid needs to come back
-- high one clock cycle before the next read command (reading ONES
-- again) is issued. Since the rdata_valid is just a delayed
-- version of doing_rd, doing_rd needs to exhibit the same behaviour.
--
-- for FR (burst length 4): require that doing_rd high 1 clock cycle after cs_n is low
-- ____ ____ ____ ____ ____ ____ ____ ____ ____
-- clk ____| |____| |____| |____| |____| |____| |____| |____| |____|
--
-- ___ _______ _______ _______ _______
-- \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXXXXXXX / \ XXXX
-- addr XXXXXXXXXXX ONES XXXXXXXXXXX ONES XXXXXXXXXXX ZEROS XXXXXXXXXXX ONES XXXXX--> Repeat
-- ___/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXXXXXXX \_______/ XXXX
--
-- _________ _________ _________ _________ ____
-- cs_n ____| |_________| |_________| |_________| |_________|
--
-- _________
-- doing_rd ________________________________________________________________| |______________
--
--
-- for HR: require that doing_rd high in the same clock cycle as cs_n is low
--
sig_doing_rd(MEM_IF_DQS_WIDTH*(DWIDTH_RATIO/2-1)) <= '1';
end if;
end if;
when s_ac_read_wd_lat =>
-- continuously issues reads on the memory locations
-- containing write latency addr=[2*c_cal_burst_len - (3*c_cal_burst_len - 1)]
if sig_addr_cmd_state /= sig_addr_cmd_last_state then
-- no initialization required here. Must still wait
-- a clock cycle before beginning operations so that
-- we are properly synchronized with
-- dimm_driving_dq_proc.
else
if sig_burst_count = 0 then
if sig_dimm_driving_dq = '1' then
sig_doing_rd <= (others => '1');
end if;
sig_addr_cmd <= read(c_seq_addr_cmd_config, -- configuration
sig_addr_cmd, -- previous value
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- column
2**current_cs, -- rank
c_cal_read_burst_len,
false);
end if;
end if;
when others =>
report dgrb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_addr_cmd_state <= s_ac_idle;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).read;
end loop;
sig_addr_cmd_last_state <= sig_addr_cmd_state;
end if;
end process;
end block ac_block;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : data gatherer (write bias) [dgwb] block for the non-levelling
-- AFI PHY sequencer
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr2_phy_alt_mem_phy_addr_cmd_pkg.all;
--
entity ddr2_phy_alt_mem_phy_dgwb is
generic (
-- Physical IF width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
DWIDTH_RATIO : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_NUM_RANKS : natural; -- The sequencer outputs memory control signals of width num_ranks
MEM_IF_MEMTYPE : string;
ADV_LAT_WIDTH : natural;
MEM_IF_CAL_BANK : natural; -- Bank to which calibration data is written
-- Base column address to which calibration data is written.
-- Memory at MEM_IF_CAL_BASE_COL - MEM_IF_CAL_BASE_COL + C_CAL_DATA_LEN - 1
-- is assumed to contain the proper data.
MEM_IF_CAL_BASE_COL : natural
);
port (
-- CLK Reset
clk : in std_logic;
rst_n : in std_logic;
parameterisation_rec : in t_algm_paramaterisation;
-- Control interface :
dgwb_ctrl : out t_ctrl_stat;
ctrl_dgwb : in t_ctrl_command;
-- iRAM 'push' interface :
dgwb_iram : out t_iram_push;
iram_push_done : in std_logic;
-- Admin block req/gnt interface.
dgwb_ac_access_req : out std_logic;
dgwb_ac_access_gnt : in std_logic;
-- WDP interface
dgwb_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
dgwb_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
dgwb_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
dgwb_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
dgwb_wdp_ovride : out std_logic;
-- addr/cmd output for write commands.
dgwb_ac : out t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
bypassed_rdata : in std_logic_vector(MEM_IF_DWIDTH-1 downto 0);
-- odt settings per chip select
odt_settings : in t_odt_array(0 to MEM_IF_NUM_RANKS-1)
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
--
architecture rtl of ddr2_phy_alt_mem_phy_dgwb is
type t_dgwb_state is (
s_idle,
s_wait_admin,
s_write_btp, -- Writes bit-training pattern
s_write_ones, -- Writes ones
s_write_zeros, -- Writes zeros
s_write_mtp, -- Write more training patterns (requires read to check allignment)
s_write_01_pairs, -- Writes 01 pairs
s_write_1100_step,-- Write step function (half zeros, half ones)
s_write_0011_step,-- Write reversed step function (half ones, half zeros)
s_write_wlat, -- Writes the write latency into a memory address.
s_release_admin
);
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant dgwb_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (dgwb) : ";
function dqs_pattern return std_logic_vector is
variable dqs : std_logic_vector( DWIDTH_RATIO - 1 downto 0);
begin
if DWIDTH_RATIO = 2 then
dqs := "10";
elsif DWIDTH_RATIO = 4 then
dqs := "1100";
else
report dgwb_report_prefix & "unsupported DWIDTH_RATIO in function dqs_pattern." severity failure;
end if;
return dqs;
end;
signal sig_addr_cmd : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal sig_dgwb_state : t_dgwb_state;
signal sig_dgwb_last_state : t_dgwb_state;
signal access_complete : std_logic;
signal generate_wdata : std_logic; -- for s_write_wlat only
-- current chip select being processed
signal current_cs : natural range 0 to MEM_IF_NUM_RANKS-1;
begin
dgwb_ac <= sig_addr_cmd;
-- Set IRAM interface to defaults
dgwb_iram <= defaults;
-- Master state machine. Generates state transitions.
master_dgwb_state_block : if True generate
signal sig_ctrl_dgwb : t_ctrl_command; -- registers ctrl_dgwb input.
begin
-- generate the current_cs signal to track which cs accessed by PHY at any instance
current_cs_proc : process (clk, rst_n)
begin
if rst_n = '0' then
current_cs <= 0;
elsif rising_edge(clk) then
if sig_ctrl_dgwb.command_req = '1' then
current_cs <= sig_ctrl_dgwb.command_op.current_cs;
end if;
end if;
end process;
master_dgwb_state_proc : process(rst_n, clk)
begin
if rst_n = '0' then
sig_dgwb_state <= s_idle;
sig_dgwb_last_state <= s_idle;
sig_ctrl_dgwb <= defaults;
elsif rising_edge(clk) then
case sig_dgwb_state is
when s_idle =>
if sig_ctrl_dgwb.command_req = '1' then
if (curr_active_block(sig_ctrl_dgwb.command) = dgwb) then
sig_dgwb_state <= s_wait_admin;
end if;
end if;
when s_wait_admin =>
case sig_ctrl_dgwb.command is
when cmd_write_btp => sig_dgwb_state <= s_write_btp;
when cmd_write_mtp => sig_dgwb_state <= s_write_mtp;
when cmd_was => sig_dgwb_state <= s_write_wlat;
when others =>
report dgwb_report_prefix & "unknown command" severity error;
end case;
if dgwb_ac_access_gnt /= '1' then
sig_dgwb_state <= s_wait_admin;
end if;
when s_write_btp =>
sig_dgwb_state <= s_write_zeros;
when s_write_zeros =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_ones;
end if;
when s_write_ones =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_mtp =>
sig_dgwb_state <= s_write_01_pairs;
when s_write_01_pairs =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_1100_step;
end if;
when s_write_1100_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_write_0011_step;
end if;
when s_write_0011_step =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_write_wlat =>
if sig_dgwb_state = sig_dgwb_last_state and access_complete = '1' then
sig_dgwb_state <= s_release_admin;
end if;
when s_release_admin =>
if dgwb_ac_access_gnt = '0' then
sig_dgwb_state <= s_idle;
end if;
when others =>
report dgwb_report_prefix & "undefined state in addr_cmd_proc" severity error;
sig_dgwb_state <= s_idle;
end case;
sig_dgwb_last_state <= sig_dgwb_state;
sig_ctrl_dgwb <= ctrl_dgwb;
end if;
end process;
end generate;
-- Generates writes
ac_write_block : if True generate
constant C_BURST_T : natural := C_CAL_BURST_LEN / DWIDTH_RATIO; -- Number of phy-clock cycles per burst
constant C_MAX_WLAT : natural := 2**ADV_LAT_WIDTH-1; -- Maximum latency in clock cycles
constant C_MAX_COUNT : natural := C_MAX_WLAT + C_BURST_T + 4*12 - 1; -- up to 12 consecutive writes at 4 cycle intervals
-- The following function sets the width over which
-- write latency should be repeated on the dq bus
-- the default value is MEM_IF_DQ_PER_DQS
function set_wlat_dq_rep_width return natural is
begin
for i in 1 to MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS loop
if (i*MEM_IF_DQ_PER_DQS) >= ADV_LAT_WIDTH then
return i*MEM_IF_DQ_PER_DQS;
end if;
end loop;
report dgwb_report_prefix & "the specified maximum write latency cannot be fully represented in the given number of DQ pins" & LF &
"** NOTE: This may cause overflow when setting ctl_wlat signal" severity warning;
return MEM_IF_DQ_PER_DQS;
end function;
constant C_WLAT_DQ_REP_WIDTH : natural := set_wlat_dq_rep_width;
signal sig_count : natural range 0 to 2**8 - 1;
begin
ac_write_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
generate_wdata <= '0'; -- for s_write_wlat only
sig_count <= 0;
sig_addr_cmd <= int_pup_reset(c_seq_addr_cmd_config);
access_complete <= '0';
elsif rising_edge(clk) then
dgwb_wdp_ovride <= '0';
dgwb_dqs <= (others => '0');
dgwb_dm <= (others => '1');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '0');
dgwb_wdata_valid <= (others => '0');
sig_addr_cmd <= deselect(c_seq_addr_cmd_config, sig_addr_cmd);
access_complete <= '0';
generate_wdata <= '0'; -- for s_write_wlat only
case sig_dgwb_state is
when s_idle =>
sig_addr_cmd <= defaults(c_seq_addr_cmd_config);
-- require ones in locations:
-- 1. c_cal_ofs_ones (8 locations)
-- 2. 2nd half of location c_cal_ofs_xF5 (4 locations)
when s_write_ones =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ONES to DQ pins
dgwb_wdata <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
-- ensure safe intervals for DDRx memory writes (min 4 mem clk cycles between writes for BC4 DDR3)
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_ones + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5 + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require zeros in locations:
-- 1. c_cal_ofs_zeros (8 locations)
-- 2. 1st half of c_cal_ofs_x30_almt_0 (4 locations)
-- 3. 1st half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_zeros =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
-- Write ZEROS to DQ pins
dgwb_wdata <= (others => '0');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 4 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_zeros + 4, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 8 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
elsif sig_count = 12 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1, -- address
2**current_cs, -- rank
4, -- burst length (fixed at BC4)
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- require 0101 pattern in locations:
-- 1. 1st half of location c_cal_ofs_xF5 (4 locations)
when s_write_01_pairs =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_count <= 0;
else
if sig_count = 0 then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_xF5, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
end if;
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 01 to pairs of memory addresses
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if i mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
-- require pattern "0011" (or "1100") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_0 (4 locations)
when s_write_0011_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_0 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 0011 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
-- this calculation has 2 parts:
-- a) sig_count mod C_BURST_T is a timewise iterator of repetition of the pattern
-- b) i represents the temporal iterator of the pattern
-- it is required to sum a and b and switch the pattern between 0 and 1 every 2 locations in each dimension
-- Note: the same formulae is used below for the 1100 pattern
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
end if;
end loop;
-- require pattern "1100" (or "0011") in locations:
-- 1. 2nd half of c_cal_ofs_x30_almt_1 (4 locations)
when s_write_1100_step =>
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
-- Issue write command
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config,
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_x30_almt_1 + 4, -- address
2**current_cs, -- rank
4, -- burst length
false); -- auto-precharge
sig_count <= 0;
else
sig_count <= sig_count + 1;
end if;
if sig_count = C_MAX_COUNT - 1 then
access_complete <= '1';
end if;
-- Write 1100 step to column addresses. Note that
-- it cannot be determined which at this point. The
-- strategy is to write both alignments and see which
-- one is correct later on.
for i in 0 to dgwb_wdata'length / MEM_IF_DWIDTH - 1 loop
if ((sig_count mod C_BURST_T) + (i/2)) mod 2 = 0 then
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '1');
else
dgwb_wdata((i+1)*MEM_IF_DWIDTH - 1 downto i*MEM_IF_DWIDTH) <= (others => '0');
end if;
end loop;
when s_write_wlat =>
-- Effect:
-- *Writes the memory latency to an array formed
-- from memory addr=[2*C_CAL_BURST_LEN-(3*C_CAL_BURST_LEN-1)].
-- The write latency is written to pairs of addresses
-- across the given range.
--
-- Example
-- C_CAL_BURST_LEN = 4
-- addr 8 - 9 [WLAT] size = 2*MEM_IF_DWIDTH bits
-- addr 10 - 11 [WLAT] size = 2*MEM_IF_DWIDTH bits
--
dgwb_wdp_ovride <= '1';
dgwb_dqs <= dqs_pattern;
dgwb_dm <= (others => '0');
dgwb_wdata <= (others => '0');
dgwb_dqs_burst <= (others => '1');
dgwb_wdata_valid <= (others => '1');
if sig_dgwb_state /= sig_dgwb_last_state then
sig_addr_cmd <= write(c_seq_addr_cmd_config, -- A/C configuration
sig_addr_cmd,
MEM_IF_CAL_BANK, -- bank
MEM_IF_CAL_BASE_COL + c_cal_ofs_wd_lat, -- address
2**current_cs, -- rank
8, -- burst length (8 for DDR3 and 4 for DDR/DDR2)
false); -- auto-precharge
sig_count <= 0;
else
-- hold wdata_valid and wdata 2 clock cycles
-- 1 - because ac signal registered at top level of sequencer
-- 2 - because want time to dqs_burst edge which occurs 1 cycle earlier
-- than wdata_valid in an AFI compliant controller
generate_wdata <= '1';
end if;
if generate_wdata = '1' then
for i in 0 to dgwb_wdata'length/C_WLAT_DQ_REP_WIDTH - 1 loop
dgwb_wdata((i+1)*C_WLAT_DQ_REP_WIDTH - 1 downto i*C_WLAT_DQ_REP_WIDTH) <= std_logic_vector(to_unsigned(sig_count, C_WLAT_DQ_REP_WIDTH));
end loop;
-- delay by 1 clock cycle to account for 1 cycle discrepancy
-- between dqs_burst and wdata_valid
if sig_count = C_MAX_COUNT then
access_complete <= '1';
end if;
sig_count <= sig_count + 1;
end if;
when others =>
null;
end case;
-- mask odt signal
for i in 0 to (DWIDTH_RATIO/2)-1 loop
sig_addr_cmd(i).odt <= odt_settings(current_cs).write;
end loop;
end if;
end process;
end generate;
-- Handles handshaking for access to address/command
ac_handshake_proc : process(rst_n, clk)
begin
if rst_n = '0' then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
elsif rising_edge(clk) then
dgwb_ctrl <= defaults;
dgwb_ac_access_req <= '0';
if sig_dgwb_state /= s_idle and sig_dgwb_state /= s_release_admin then
dgwb_ac_access_req <= '1';
elsif sig_dgwb_state = s_idle or sig_dgwb_state = s_release_admin then
dgwb_ac_access_req <= '0';
else
report dgwb_report_prefix & "unexpected state in ac_handshake_proc so haven't requested access to address/command." severity warning;
end if;
if sig_dgwb_state = s_wait_admin and sig_dgwb_last_state = s_idle then
dgwb_ctrl.command_ack <= '1';
end if;
if sig_dgwb_state = s_idle and sig_dgwb_last_state = s_release_admin then
dgwb_ctrl.command_done <= '1';
end if;
end if;
end process;
end architecture rtl;
--
-- -----------------------------------------------------------------------------
-- Abstract : ctrl block for the non-levelling AFI PHY sequencer
-- This block is the central control unit for the sequencer. The method
-- of control is to issue commands (prefixed cmd_) to each of the other
-- sequencer blocks to execute. Each command corresponds to a stage of
-- the AFI PHY calibaration stage, and in turn each state represents a
-- command or a supplimentary flow control operation. In addition to
-- controlling the sequencer this block also checks for time out
-- conditions which occur when a different system block is faulty.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr2_phy_alt_mem_phy_iram_addr_pkg.all;
--
entity ddr2_phy_alt_mem_phy_ctrl is
generic (
FAMILYGROUP_ID : natural;
MEM_IF_DLL_LOCK_COUNT : natural;
MEM_IF_MEMTYPE : string;
DWIDTH_RATIO : natural;
IRAM_ADDRESSING : t_base_hdr_addresses;
MEM_IF_CLK_PS : natural;
TRACKING_INTERVAL_IN_MS : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_DQS_WIDTH : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 1 skip rrp, if 2 rrp for 1 dqs group and 1 cs
ACK_SEVERITY : severity_level
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and redo request
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_recalibrate_req : in std_logic; -- acts as a synchronous reset
-- status signals from iram
iram_status : in t_iram_stat;
iram_push_done : in std_logic;
-- standard control signal to all blocks
ctrl_op_rec : out t_ctrl_command;
-- standardised response from all system blocks
admin_ctrl : in t_ctrl_stat;
dgrb_ctrl : in t_ctrl_stat;
dgwb_ctrl : in t_ctrl_stat;
-- mmi to ctrl interface
mmi_ctrl : in t_mmi_ctrl;
ctrl_mmi : out t_ctrl_mmi;
-- byte lane select
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- signals to control the ac_nt setting
dgrb_ctrl_ac_nt_good : in std_logic;
int_ac_nt : out std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0); -- width of 1 for DWIDTH_RATIO =2,4 and 2 for DWIDTH_RATIO = 8
-- the following signals are reserved for future use
ctrl_iram_push : out t_ctrl_iram
);
end entity;
library work;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
--
architecture struct of ddr2_phy_alt_mem_phy_ctrl is
-- a prefix for all report signals to identify phy and sequencer block
--
constant ctrl_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (ctrl) : ";
-- decoder to find the relevant disable bit (from mmi registers) for a given state
function find_dis_bit
(
state : t_master_sm_state;
mmi_ctrl : t_mmi_ctrl
) return std_logic is
variable v_dis : std_logic;
begin
case state is
when s_phy_initialise => v_dis := mmi_ctrl.hl_css.phy_initialise_dis;
when s_init_dram |
s_prog_cal_mr => v_dis := mmi_ctrl.hl_css.init_dram_dis;
when s_write_ihi => v_dis := mmi_ctrl.hl_css.write_ihi_dis;
when s_cal => v_dis := mmi_ctrl.hl_css.cal_dis;
when s_write_btp => v_dis := mmi_ctrl.hl_css.write_btp_dis;
when s_write_mtp => v_dis := mmi_ctrl.hl_css.write_mtp_dis;
when s_read_mtp => v_dis := mmi_ctrl.hl_css.read_mtp_dis;
when s_rrp_reset => v_dis := mmi_ctrl.hl_css.rrp_reset_dis;
when s_rrp_sweep => v_dis := mmi_ctrl.hl_css.rrp_sweep_dis;
when s_rrp_seek => v_dis := mmi_ctrl.hl_css.rrp_seek_dis;
when s_rdv => v_dis := mmi_ctrl.hl_css.rdv_dis;
when s_poa => v_dis := mmi_ctrl.hl_css.poa_dis;
when s_was => v_dis := mmi_ctrl.hl_css.was_dis;
when s_adv_rd_lat => v_dis := mmi_ctrl.hl_css.adv_rd_lat_dis;
when s_adv_wr_lat => v_dis := mmi_ctrl.hl_css.adv_wr_lat_dis;
when s_prep_customer_mr_setup => v_dis := mmi_ctrl.hl_css.prep_customer_mr_setup_dis;
when s_tracking_setup |
s_tracking => v_dis := mmi_ctrl.hl_css.tracking_dis;
when others => v_dis := '1'; -- default change stage
end case;
return v_dis;
end function;
-- decoder to find the relevant command for a given state
function find_cmd
(
state : t_master_sm_state
) return t_ctrl_cmd_id is
begin
case state is
when s_phy_initialise => return cmd_phy_initialise;
when s_init_dram => return cmd_init_dram;
when s_prog_cal_mr => return cmd_prog_cal_mr;
when s_write_ihi => return cmd_write_ihi;
when s_cal => return cmd_idle;
when s_write_btp => return cmd_write_btp;
when s_write_mtp => return cmd_write_mtp;
when s_read_mtp => return cmd_read_mtp;
when s_rrp_reset => return cmd_rrp_reset;
when s_rrp_sweep => return cmd_rrp_sweep;
when s_rrp_seek => return cmd_rrp_seek;
when s_rdv => return cmd_rdv;
when s_poa => return cmd_poa;
when s_was => return cmd_was;
when s_adv_rd_lat => return cmd_prep_adv_rd_lat;
when s_adv_wr_lat => return cmd_prep_adv_wr_lat;
when s_prep_customer_mr_setup => return cmd_prep_customer_mr_setup;
when s_tracking_setup |
s_tracking => return cmd_tr_due;
when others => return cmd_idle;
end case;
end function;
function mcs_rw_state -- returns true for multiple cs read/write states
(
state : t_master_sm_state
) return boolean is
begin
case state is
when s_write_btp | s_write_mtp | s_rrp_sweep =>
return true;
when s_reset | s_phy_initialise | s_init_dram | s_prog_cal_mr | s_write_ihi | s_cal |
s_read_mtp | s_rrp_reset | s_rrp_seek | s_rdv | s_poa |
s_was | s_adv_rd_lat | s_adv_wr_lat | s_prep_customer_mr_setup |
s_tracking_setup | s_tracking | s_operational | s_non_operational =>
return false;
when others =>
--
return false;
end case;
end function;
-- timing parameters
constant c_done_timeout_count : natural := 32768;
constant c_ack_timeout_count : natural := 1000;
constant c_ticks_per_ms : natural := 1000000000/(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
constant c_ticks_per_10us : natural := 10000000 /(MEM_IF_CLK_PS*(DWIDTH_RATIO/2));
-- local copy of calibration fail/success signals
signal int_ctl_init_fail : std_logic;
signal int_ctl_init_success : std_logic;
-- state machine (master for sequencer)
signal state : t_master_sm_state;
signal last_state : t_master_sm_state;
-- flow control signals for state machine
signal dis_state : std_logic; -- disable state
signal hold_state : std_logic; -- hold in state for 1 clock cycle
signal master_ctrl_op_rec : t_ctrl_command; -- master command record to all sequencer blocks
signal master_ctrl_iram_push : t_ctrl_iram; -- record indicating control details for pushes
signal dll_lock_counter : natural range MEM_IF_DLL_LOCK_COUNT - 1 downto 0; -- to wait for dll to lock
signal iram_init_complete : std_logic;
-- timeout signals to check if a block has 'hung'
signal timeout_counter : natural range c_done_timeout_count - 1 downto 0;
signal timeout_counter_stop : std_logic;
signal timeout_counter_enable : std_logic;
signal timeout_counter_clear : std_logic;
signal cmd_req_asserted : std_logic; -- a command has been issued
signal flag_ack_timeout : std_logic; -- req -> ack timed out
signal flag_done_timeout : std_logic; -- reg -> done timed out
signal waiting_for_ack : std_logic; -- command issued
signal cmd_ack_seen : std_logic; -- command completed
signal curr_ctrl : t_ctrl_stat; -- response for current active block
signal curr_cmd : t_ctrl_cmd_id;
-- store state information based on issued command
signal int_ctrl_prev_stage : t_ctrl_cmd_id;
signal int_ctrl_current_stage : t_ctrl_cmd_id;
-- multiple chip select counter
signal cs_counter : natural range 0 to MEM_IF_NUM_RANKS - 1;
signal reissue_cmd_req : std_logic; -- reissue command request for multiple cs
signal cal_cs_enabled : std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
-- signals to check the ac_nt setting
signal ac_nt_almts_checked : natural range 0 to DWIDTH_RATIO/2-1;
signal ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
-- track the mtp alignment setting
signal mtp_almts_checked : natural range 0 to 2;
signal mtp_correct_almt : natural range 0 to 1;
signal mtp_no_valid_almt : std_logic;
signal mtp_both_valid_almt : std_logic;
signal mtp_err : std_logic;
-- tracking timing
signal milisecond_tick_gen_count : natural range 0 to c_ticks_per_ms -1 := c_ticks_per_ms -1;
signal tracking_ms_counter : natural range 0 to 255;
signal tracking_update_due : std_logic;
begin -- architecture struct
-------------------------------------------------------------------------------
-- check if chip selects are enabled
-- this only effects reactive stages (i,e, those requiring memory reads)
-------------------------------------------------------------------------------
process(ctl_cal_byte_lanes)
variable v_cs_enabled : std_logic;
begin
for i in 0 to MEM_IF_NUM_RANKS - 1 loop
-- check if any bytes enabled
v_cs_enabled := '0';
for j in 0 to MEM_IF_DQS_WIDTH - 1 loop
v_cs_enabled := v_cs_enabled or ctl_cal_byte_lanes(i*MEM_IF_DQS_WIDTH + j);
end loop;
-- if any byte enabled set cs as enabled else not
cal_cs_enabled(i) <= v_cs_enabled;
-- sanity checking:
if i = 0 and v_cs_enabled = '0' then
report ctrl_report_prefix & " disabling of chip select 0 is unsupported by the sequencer," & LF &
"-> if this is your intention then please remap CS pins such that CS 0 is not disabled" severity failure;
end if;
end loop;
end process;
-- -----------------------------------------------------------------------------
-- dll lock counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif rising_edge(clk) then
if ctl_recalibrate_req = '1' then
dll_lock_counter <= MEM_IF_DLL_LOCK_COUNT -1;
elsif dll_lock_counter /= 0 then
dll_lock_counter <= dll_lock_counter - 1;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- timeout counter : this counter is used to determine if an ack, or done has
-- not been received within the expected number of clock cycles of a req being
-- asserted.
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter <= c_done_timeout_count - 1;
elsif rising_edge(clk) then
if timeout_counter_clear = '1' then
timeout_counter <= c_done_timeout_count - 1;
elsif timeout_counter_enable = '1' and state /= s_init_dram then
if timeout_counter /= 0 then
timeout_counter <= timeout_counter - 1;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- register current ctrl signal based on current command
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
curr_ctrl <= defaults;
curr_cmd <= cmd_idle;
elsif rising_edge(clk) then
case curr_active_block(curr_cmd) is
when admin => curr_ctrl <= admin_ctrl;
when dgrb => curr_ctrl <= dgrb_ctrl;
when dgwb => curr_ctrl <= dgwb_ctrl;
when others => curr_ctrl <= defaults;
end case;
curr_cmd <= master_ctrl_op_rec.command;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of cmd_ack_seen
-- -----------------------------------------------------------------------------
process (curr_ctrl)
begin
cmd_ack_seen <= curr_ctrl.command_ack;
end process;
-------------------------------------------------------------------------------
-- generation of waiting_for_ack flag (to determine whether ack has timed out)
-------------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
waiting_for_ack <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
waiting_for_ack <= '1';
elsif cmd_ack_seen = '1' then
waiting_for_ack <= '0';
end if;
end if;
end process;
-- -----------------------------------------------------------------------------
-- generation of timeout flags
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
flag_ack_timeout <= '0';
flag_done_timeout <= '0';
elsif rising_edge(clk) then
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_ack_timeout <= '0';
elsif timeout_counter = 0 and waiting_for_ack = '1' then
flag_ack_timeout <= '1';
end if;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
flag_done_timeout <= '0';
elsif timeout_counter = 0 and
state /= s_rrp_sweep and -- rrp can take enough cycles to overflow counter so don't timeout
state /= s_init_dram and -- init_dram takes about 200 us, so don't timeout
timeout_counter_clear /= '1' then -- check if currently clearing the timeout (i.e. command_done asserted for s_init_dram or s_rrp_sweep)
flag_done_timeout <= '1';
end if;
end if;
end process;
-- generation of timeout_counter_stop
timeout_counter_stop <= curr_ctrl.command_done;
-- -----------------------------------------------------------------------------
-- generation of timeout_counter_enable and timeout_counter_clear
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
timeout_counter_enable <= '0';
timeout_counter_clear <= '0';
elsif rising_edge(clk) then
if cmd_req_asserted = '1' then
timeout_counter_enable <= '1';
timeout_counter_clear <= '0';
elsif timeout_counter_stop = '1'
or state = s_operational
or state = s_non_operational
or state = s_reset then
timeout_counter_enable <= '0';
timeout_counter_clear <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- assignment to ctrl_mmi record
-------------------------------------------------------------------------------
process (clk, rst_n)
variable v_ctrl_mmi : t_ctrl_mmi;
begin
if rst_n = '0' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
int_ctrl_prev_stage <= cmd_idle;
int_ctrl_current_stage <= cmd_idle;
elsif rising_edge(clk) then
ctrl_mmi <= v_ctrl_mmi;
v_ctrl_mmi.ctrl_calibration_success := '0';
v_ctrl_mmi.ctrl_calibration_fail := '0';
if (curr_ctrl.command_ack = '1') then
case state is
when s_init_dram => v_ctrl_mmi.ctrl_cal_stage_ack_seen.init_dram := '1';
when s_write_btp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_btp := '1';
when s_write_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_mtp := '1';
when s_read_mtp => v_ctrl_mmi.ctrl_cal_stage_ack_seen.read_mtp := '1';
when s_rrp_reset => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_reset := '1';
when s_rrp_sweep => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_sweep := '1';
when s_rrp_seek => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rrp_seek := '1';
when s_rdv => v_ctrl_mmi.ctrl_cal_stage_ack_seen.rdv := '1';
when s_poa => v_ctrl_mmi.ctrl_cal_stage_ack_seen.poa := '1';
when s_was => v_ctrl_mmi.ctrl_cal_stage_ack_seen.was := '1';
when s_adv_rd_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_rd_lat := '1';
when s_adv_wr_lat => v_ctrl_mmi.ctrl_cal_stage_ack_seen.adv_wr_lat := '1';
when s_prep_customer_mr_setup => v_ctrl_mmi.ctrl_cal_stage_ack_seen.prep_customer_mr_setup := '1';
when s_tracking_setup |
s_tracking => v_ctrl_mmi.ctrl_cal_stage_ack_seen.tracking_setup := '1';
when others => null;
end case;
end if;
-- special 'ack' (actually finished) triggers for phy_initialise, writing iram header info and s_cal
if state = s_phy_initialise then
if iram_status.init_done = '1' and dll_lock_counter = 0 then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.phy_initialise := '1';
end if;
end if;
if state = s_write_ihi then
if iram_push_done = '1' then
v_ctrl_mmi.ctrl_cal_stage_ack_seen.write_ihi := '1';
end if;
end if;
if state = s_cal and find_dis_bit(state, mmi_ctrl) = '0' then -- if cal state and calibration not disabled acknowledge
v_ctrl_mmi.ctrl_cal_stage_ack_seen.cal := '1';
end if;
if state = s_operational then
v_ctrl_mmi.ctrl_calibration_success := '1';
end if;
if state = s_non_operational then
v_ctrl_mmi.ctrl_calibration_fail := '1';
end if;
if state /= s_non_operational then
v_ctrl_mmi.ctrl_current_active_block := master_ctrl_iram_push.active_block;
v_ctrl_mmi.ctrl_current_stage := master_ctrl_op_rec.command;
else
v_ctrl_mmi.ctrl_current_active_block := v_ctrl_mmi.ctrl_current_active_block;
v_ctrl_mmi.ctrl_current_stage := v_ctrl_mmi.ctrl_current_stage;
end if;
int_ctrl_prev_stage <= int_ctrl_current_stage;
int_ctrl_current_stage <= v_ctrl_mmi.ctrl_current_stage;
if int_ctrl_prev_stage /= int_ctrl_current_stage then
v_ctrl_mmi.ctrl_current_stage_done := '0';
else
if curr_ctrl.command_done = '1' then
v_ctrl_mmi.ctrl_current_stage_done := '1';
end if;
end if;
v_ctrl_mmi.master_state_r := last_state;
if mmi_ctrl.calibration_start = '1' or ctl_recalibrate_req = '1' then
v_ctrl_mmi := defaults;
ctrl_mmi <= defaults;
end if;
-- assert error codes here
if curr_ctrl.command_err = '1' then
v_ctrl_mmi.ctrl_err_code := curr_ctrl.command_result;
elsif flag_ack_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_ack_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif flag_done_timeout = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(c_err_ctrl_done_timeout, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_err = '1' then
if mtp_no_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_NO_VALID_ALMT, v_ctrl_mmi.ctrl_err_code'length));
elsif mtp_both_valid_almt = '1' then
v_ctrl_mmi.ctrl_err_code := std_logic_vector(to_unsigned(C_ERR_READ_MTP_BOTH_ALMT_PASS, v_ctrl_mmi.ctrl_err_code'length));
end if;
end if;
end if;
end process;
-- check if iram finished init
process(iram_status)
begin
if GENERATE_ADDITIONAL_DBG_RTL = 0 then
iram_init_complete <= '1';
else
iram_init_complete <= iram_status.init_done;
end if;
end process;
-- -----------------------------------------------------------------------------
-- master state machine
-- (this controls the operation of the entire sequencer)
-- the states are summarised as follows:
-- s_reset
-- s_phy_initialise - wait for dll lock and init done flag from iram
-- s_init_dram, -- dram initialisation - reset sequence
-- s_prog_cal_mr, -- dram initialisation - programming mode registers (once per chip select)
-- s_write_ihi - write header information in iRAM
-- s_cal - check if calibration to be executed
-- s_write_btp - write burst training pattern
-- s_write_mtp - write more training pattern
-- s_rrp_reset - read resync phase setup - reset initial conditions
-- s_rrp_sweep - read resync phase setup - sweep phases per chip select
-- s_read_mtp - read training patterns to find correct alignment for 1100 burst
-- (this is a special case of s_rrp_seek with no resych phase setting)
-- s_rrp_seek - read resync phase setup - seek correct alignment
-- s_rdv - read data valid setup
-- s_poa - calibrate the postamble
-- s_was - write datapath setup (ac to write data timing)
-- s_adv_rd_lat - advertise read latency
-- s_adv_wr_lat - advertise write latency
-- s_tracking_setup - perform tracking (1st pass to setup mimic window)
-- s_prep_customer_mr_setup - apply user mode register settings (in admin block)
-- s_tracking - perform tracking (subsequent passes in user mode)
-- s_operational - calibration successful and in user mode
-- s_non_operational - calibration unsuccessful and in user mode
-- -----------------------------------------------------------------------------
process(clk, rst_n)
variable v_seen_ack : boolean;
variable v_dis : std_logic; -- disable bit
begin
if rst_n = '0' then
state <= s_reset;
last_state <= s_reset;
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
v_seen_ack := false;
hold_state <= '0';
cs_counter <= 0;
mtp_almts_checked <= 0;
ac_nt <= (others => '1');
ac_nt_almts_checked <= 0;
reissue_cmd_req <= '0';
dis_state <= '0';
elsif rising_edge(clk) then
last_state <= state;
-- check if state_tx required
if curr_ctrl.command_ack = '1' then
v_seen_ack := true;
end if;
-- find disable bit for current state (do once to avoid exit mid-state)
if state /= last_state then
dis_state <= find_dis_bit(state, mmi_ctrl);
end if;
-- Set special conditions:
if state = s_reset or
state = s_operational or
state = s_non_operational then
dis_state <= '1';
end if;
-- override to ensure execution of next state logic
if (state = s_cal) then
dis_state <= '1';
end if;
-- if header writing in iram check finished
if (state = s_write_ihi) then
if iram_push_done = '1' or mmi_ctrl.hl_css.write_ihi_dis = '1' then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
-- Special condition for initialisation
if (state = s_phy_initialise) then
if ((dll_lock_counter = 0) and (iram_init_complete = '1')) or
(mmi_ctrl.hl_css.phy_initialise_dis = '1') then
dis_state <= '1';
else
dis_state <= '0';
end if;
end if;
if dis_state = '1' then
v_seen_ack := false;
elsif curr_ctrl.command_done = '1' then
if v_seen_ack = false then
report ctrl_report_prefix & "have not seen ack but have seen command done from " & t_ctrl_active_block'image(curr_active_block(master_ctrl_op_rec.command)) & "_block in state " & t_master_sm_state'image(state) severity warning;
end if;
v_seen_ack := false;
end if;
-- default do not reissue command request
reissue_cmd_req <= '0';
if (hold_state = '1') then
hold_state <= '0';
else
if ((dis_state = '1') or
(curr_ctrl.command_done = '1') or
((cal_cs_enabled(cs_counter) = '0') and (mcs_rw_state(state) = True))) then -- current chip select is disabled and read/write
hold_state <= '1';
-- Only reset the below if making state change
int_ctl_init_success <= '0';
int_ctl_init_fail <= '0';
-- default chip select counter gets reset to zero
cs_counter <= 0;
case state is
when s_reset => state <= s_phy_initialise;
ac_nt <= (others => '1');
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_phy_initialise => state <= s_init_dram;
when s_init_dram => state <= s_prog_cal_mr;
when s_prog_cal_mr => if cs_counter = MEM_IF_NUM_RANKS - 1 then
-- if no debug interface don't write iram header
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
state <= s_write_ihi;
else
state <= s_cal;
end if;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_write_ihi => state <= s_cal;
when s_cal => if mmi_ctrl.hl_css.cal_dis = '0' then
state <= s_write_btp;
else
state <= s_tracking_setup;
end if;
-- always enter s_cal before calibration so reset some variables here
mtp_almts_checked <= 0;
ac_nt_almts_checked <= 0;
when s_write_btp => if cs_counter = MEM_IF_NUM_RANKS-1 or
SIM_TIME_REDUCTIONS = 2 then
state <= s_write_mtp;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_write_mtp => if cs_counter = MEM_IF_NUM_RANKS - 1 or
SIM_TIME_REDUCTIONS = 2 then
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_rrp_reset => state <= s_rrp_sweep;
when s_rrp_sweep => if cs_counter = MEM_IF_NUM_RANKS - 1 or
mtp_almts_checked /= 2 or
SIM_TIME_REDUCTIONS = 2 then
if mtp_almts_checked /= 2 then
state <= s_read_mtp;
else
state <= s_rrp_seek;
end if;
else
cs_counter <= cs_counter + 1;
-- only reissue command if current chip select enabled
if cal_cs_enabled(cs_counter + 1) = '1' then
reissue_cmd_req <= '1';
end if;
end if;
when s_read_mtp => if mtp_almts_checked /= 2 then
mtp_almts_checked <= mtp_almts_checked + 1;
end if;
state <= s_rrp_reset;
when s_rrp_seek => state <= s_rdv;
when s_rdv => state <= s_was;
when s_was => state <= s_adv_rd_lat;
when s_adv_rd_lat => state <= s_adv_wr_lat;
when s_adv_wr_lat => if dgrb_ctrl_ac_nt_good = '1' then
state <= s_poa;
else
if ac_nt_almts_checked = (DWIDTH_RATIO/2 - 1) then
state <= s_non_operational;
else
-- switch alignment and restart calibration
ac_nt <= std_logic_vector(unsigned(ac_nt) + 1);
ac_nt_almts_checked <= ac_nt_almts_checked + 1;
if SIM_TIME_REDUCTIONS = 1 then
state <= s_rdv;
else
state <= s_rrp_reset;
end if;
mtp_almts_checked <= 0;
end if;
end if;
when s_poa => state <= s_tracking_setup;
when s_tracking_setup => state <= s_prep_customer_mr_setup;
when s_prep_customer_mr_setup => if cs_counter = MEM_IF_NUM_RANKS - 1 then -- s_prep_customer_mr_setup is always performed over all cs
state <= s_operational;
else
cs_counter <= cs_counter + 1;
reissue_cmd_req <= '1';
end if;
when s_tracking => state <= s_operational;
int_ctl_init_success <= int_ctl_init_success;
int_ctl_init_fail <= int_ctl_init_fail;
when s_operational => int_ctl_init_success <= '1';
int_ctl_init_fail <= '0';
hold_state <= '0';
if tracking_update_due = '1' and mmi_ctrl.hl_css.tracking_dis = '0' then
state <= s_tracking;
hold_state <= '1';
end if;
when s_non_operational => int_ctl_init_success <= '0';
int_ctl_init_fail <= '1';
hold_state <= '0';
if last_state /= s_non_operational then -- print a warning on entering this state
report ctrl_report_prefix & "memory calibration has failed (output from ctrl block)" severity WARNING;
end if;
when others => state <= t_master_sm_state'succ(state);
end case;
end if;
end if;
if flag_done_timeout = '1' -- no done signal from current active block
or flag_ack_timeout = '1' -- or no ack signal from current active block
or curr_ctrl.command_err = '1' -- or an error from current active block
or mtp_err = '1' then -- or an error due to mtp alignment
state <= s_non_operational;
end if;
if mmi_ctrl.calibration_start = '1' then -- restart calibration process
state <= s_cal;
end if;
if ctl_recalibrate_req = '1' then -- restart all incl. initialisation
state <= s_reset;
end if;
end if;
end process;
-- generate output calibration fail/success signals
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= int_ctl_init_fail;
ctl_init_success <= int_ctl_init_success;
end if;
end process;
-- assign ac_nt to the output int_ac_nt
process(ac_nt)
begin
int_ac_nt <= ac_nt;
end process;
-- ------------------------------------------------------------------------------
-- find correct mtp_almt from returned data
-- ------------------------------------------------------------------------------
mtp_almt: block
signal dvw_size_a0 : natural range 0 to 255; -- maximum size of command result
signal dvw_size_a1 : natural range 0 to 255;
begin
process (clk, rst_n)
variable v_dvw_a0_small : boolean;
variable v_dvw_a1_small : boolean;
begin
if rst_n = '0' then
mtp_correct_almt <= 0;
dvw_size_a0 <= 0;
dvw_size_a1 <= 0;
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
elsif rising_edge(clk) then
-- update the dvw sizes
if state = s_read_mtp then
if curr_ctrl.command_done = '1' then
if mtp_almts_checked = 0 then
dvw_size_a0 <= to_integer(unsigned(curr_ctrl.command_result));
else
dvw_size_a1 <= to_integer(unsigned(curr_ctrl.command_result));
end if;
end if;
end if;
-- check dvw size and set mtp almt
if dvw_size_a0 < dvw_size_a1 then
mtp_correct_almt <= 1;
else
mtp_correct_almt <= 0;
end if;
-- error conditions
if mtp_almts_checked = 2 and GENERATE_ADDITIONAL_DBG_RTL = 1 then -- if finished alignment checking (and GENERATE_ADDITIONAL_DBG_RTL set)
-- perform size checks once per dvw
if dvw_size_a0 < 3 then
v_dvw_a0_small := true;
else
v_dvw_a0_small := false;
end if;
if dvw_size_a1 < 3 then
v_dvw_a1_small := true;
else
v_dvw_a1_small := false;
end if;
if v_dvw_a0_small = true and v_dvw_a1_small = true then
mtp_no_valid_almt <= '1';
mtp_err <= '1';
end if;
if v_dvw_a0_small = false and v_dvw_a1_small = false then
mtp_both_valid_almt <= '1';
mtp_err <= '1';
end if;
else
mtp_no_valid_almt <= '0';
mtp_both_valid_almt <= '0';
mtp_err <= '0';
end if;
end if;
end process;
end block;
-- ------------------------------------------------------------------------------
-- process to generate command outputs, based on state, last_state and mmi_ctrl.
-- asynchronously
-- ------------------------------------------------------------------------------
process (state, last_state, mmi_ctrl, reissue_cmd_req, cs_counter, mtp_almts_checked, mtp_correct_almt)
begin
master_ctrl_op_rec <= defaults;
master_ctrl_iram_push <= defaults;
case state is
-- special condition states
when s_reset | s_phy_initialise | s_cal =>
null;
when s_write_ihi =>
if mmi_ctrl.hl_css.write_ihi_dis = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state then
master_ctrl_op_rec.command_req <= '1';
end if;
end if;
when s_operational | s_non_operational =>
master_ctrl_op_rec.command <= find_cmd(state);
when others => -- default condition for most states
if find_dis_bit(state, mmi_ctrl) = '0' then
master_ctrl_op_rec.command <= find_cmd(state);
if state /= last_state or reissue_cmd_req = '1' then
master_ctrl_op_rec.command_req <= '1';
end if;
else
if state = last_state then -- safe state exit if state disabled mid-calibration
master_ctrl_op_rec.command <= find_cmd(state);
end if;
end if;
end case;
-- for multiple chip select commands assign operand to cs_counter
master_ctrl_op_rec.command_op <= defaults;
master_ctrl_op_rec.command_op.current_cs <= cs_counter;
if state = s_rrp_sweep or state = s_read_mtp or state = s_poa then
if mtp_almts_checked /= 2 or SIM_TIME_REDUCTIONS = 2 then
master_ctrl_op_rec.command_op.single_bit <= '1';
end if;
if mtp_almts_checked /= 2 then
master_ctrl_op_rec.command_op.mtp_almt <= mtp_almts_checked;
else
master_ctrl_op_rec.command_op.mtp_almt <= mtp_correct_almt;
end if;
end if;
-- set write mode and packing mode for iram
if GENERATE_ADDITIONAL_DBG_RTL = 1 then
case state is
when s_rrp_sweep =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_bitwise;
when s_rrp_seek |
s_read_mtp =>
master_ctrl_iram_push.write_mode <= overwrite_ram;
master_ctrl_iram_push.packing_mode <= dq_wordwise;
when others =>
null;
end case;
end if;
-- set current active block
master_ctrl_iram_push.active_block <= curr_active_block(find_cmd(state));
end process;
-- some concurc_read_burst_trent assignments to outputs
process (master_ctrl_iram_push, master_ctrl_op_rec)
begin
ctrl_iram_push <= master_ctrl_iram_push;
ctrl_op_rec <= master_ctrl_op_rec;
cmd_req_asserted <= master_ctrl_op_rec.command_req;
end process;
-- -----------------------------------------------------------------------------
-- tracking interval counter
-- -----------------------------------------------------------------------------
process(clk, rst_n)
begin
if rst_n = '0' then
milisecond_tick_gen_count <= c_ticks_per_ms -1;
tracking_ms_counter <= 0;
tracking_update_due <= '0';
elsif rising_edge(clk) then
if state = s_operational and last_state/= s_operational then
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
tracking_ms_counter <= mmi_ctrl.tracking_period_ms;
elsif state = s_operational then
if milisecond_tick_gen_count = 0 and tracking_update_due /= '1' then
if tracking_ms_counter = 0 then
tracking_update_due <= '1';
else
tracking_ms_counter <= tracking_ms_counter -1;
end if;
if mmi_ctrl.tracking_orvd_to_10ms = '1' then
milisecond_tick_gen_count <= c_ticks_per_10us -1;
else
milisecond_tick_gen_count <= c_ticks_per_ms -1;
end if;
elsif milisecond_tick_gen_count /= 0 then
milisecond_tick_gen_count <= milisecond_tick_gen_count -1;
end if;
else
tracking_update_due <= '0';
end if;
end if;
end process;
end architecture struct;
--
-- -----------------------------------------------------------------------------
-- Abstract : top level for the non-levelling AFI PHY sequencer
-- The top level instances the sub-blocks of the AFI PHY
-- sequencer. In addition a number of multiplexing and high-
-- level control operations are performed. This includes the
-- multiplexing and generation of control signals for: the
-- address and command DRAM interface and pll, oct and datapath
-- latency control signals.
-- -----------------------------------------------------------------------------
--altera message_off 10036
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity ddr2_phy_alt_mem_phy_seq IS
generic (
-- choice of FPGA device family and DRAM type
FAMILY : string;
MEM_IF_MEMTYPE : string;
SPEED_GRADE : string;
FAMILYGROUP_ID : natural;
-- physical interface width definitions
MEM_IF_DQS_WIDTH : natural;
MEM_IF_DWIDTH : natural;
MEM_IF_DM_WIDTH : natural;
MEM_IF_DQ_PER_DQS : natural;
DWIDTH_RATIO : natural;
CLOCK_INDEX_WIDTH : natural;
MEM_IF_CLK_PAIR_COUNT : natural;
MEM_IF_ADDR_WIDTH : natural;
MEM_IF_BANKADDR_WIDTH : natural;
MEM_IF_CS_WIDTH : natural;
MEM_IF_NUM_RANKS : natural;
MEM_IF_RANKS_PER_SLOT : natural;
ADV_LAT_WIDTH : natural;
RESYNCHRONISE_AVALON_DBG : natural; -- 0 = false, 1 = true
AV_IF_ADDR_WIDTH : natural;
-- Not used for non-levelled seq
CHIP_OR_DIMM : string;
RDIMM_CONFIG_BITS : string;
-- setup / algorithm information
NOM_DQS_PHASE_SETTING : natural;
SCAN_CLK_DIVIDE_BY : natural;
RDP_ADDR_WIDTH : natural;
PLL_STEPS_PER_CYCLE : natural;
IOE_PHASES_PER_TCK : natural;
IOE_DELAYS_PER_PHS : natural;
MEM_IF_CLK_PS : natural;
WRITE_DESKEW_T10 : natural;
WRITE_DESKEW_HC_T10 : natural;
WRITE_DESKEW_T9NI : natural;
WRITE_DESKEW_HC_T9NI : natural;
WRITE_DESKEW_T9I : natural;
WRITE_DESKEW_HC_T9I : natural;
WRITE_DESKEW_RANGE : natural;
-- initial mode register settings
PHY_DEF_MR_1ST : natural;
PHY_DEF_MR_2ND : natural;
PHY_DEF_MR_3RD : natural;
PHY_DEF_MR_4TH : natural;
MEM_IF_DQSN_EN : natural; -- default off for Cyclone-III
MEM_IF_DQS_CAPTURE_EN : natural;
GENERATE_ADDITIONAL_DBG_RTL : natural; -- 1 signals to include iram and mmi blocks and 0 not to include
SINGLE_DQS_DELAY_CONTROL_CODE : natural; -- reserved for future use
PRESET_RLAT : natural; -- reserved for future use
EN_OCT : natural; -- Does the sequencer use OCT during calibration.
OCT_LAT_WIDTH : natural;
SIM_TIME_REDUCTIONS : natural; -- if 0 null, if 2 rrp for 1 dqs group and 1 cs
FORCE_HC : natural; -- Use to force HardCopy in simulation.
CAPABILITIES : natural; -- advertise capabilities i.e. which ctrl block states to execute (default all on)
TINIT_TCK : natural;
TINIT_RST : natural;
GENERATE_TRACKING_PHASE_STORE : natural; -- reserved for future use
IP_BUILDNUM : natural
);
port (
-- clk / reset
clk : in std_logic;
rst_n : in std_logic;
-- calibration status and prompt
ctl_init_success : out std_logic;
ctl_init_fail : out std_logic;
ctl_init_warning : out std_logic; -- unused
ctl_recalibrate_req : in std_logic;
-- the following two signals are reserved for future use
mem_ac_swapped_ranks : in std_logic_vector(MEM_IF_NUM_RANKS - 1 downto 0);
ctl_cal_byte_lanes : in std_logic_vector(MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 downto 0);
-- pll reconfiguration
seq_pll_inc_dec_n : out std_logic;
seq_pll_start_reconfig : out std_logic;
seq_pll_select : out std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
seq_pll_phs_shift_busy : in std_logic;
pll_resync_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select resync clock
pll_measure_clk_index : in std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0); -- PLL phase used to select mimic/measure clock
-- scanchain associated signals (reserved for future use)
seq_scan_clk : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqs_config : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_update : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_din : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_ck : out std_logic_vector(MEM_IF_CLK_PAIR_COUNT - 1 downto 0);
seq_scan_enable_dqs : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dqsn : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_scan_enable_dq : out std_logic_vector(MEM_IF_DWIDTH - 1 downto 0);
seq_scan_enable_dm : out std_logic_vector(MEM_IF_DM_WIDTH - 1 downto 0);
hr_rsc_clk : in std_logic;
-- address / command interface (note these are mapped internally to the seq_ac record)
seq_ac_addr : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 downto 0);
seq_ac_ba : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 downto 0);
seq_ac_cas_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_ras_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_we_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_cke : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_cs_n : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_odt : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 downto 0);
seq_ac_rst_n : out std_logic_vector((DWIDTH_RATIO/2) - 1 downto 0);
seq_ac_sel : out std_logic;
seq_mem_clk_disable : out std_logic;
-- additional datapath latency (reserved for future use)
seq_ac_add_1t_ac_lat_internal : out std_logic;
seq_ac_add_1t_odt_lat_internal : out std_logic;
seq_ac_add_2t : out std_logic;
-- read datapath interface
seq_rdp_reset_req_n : out std_logic;
seq_rdp_inc_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_rdp_dec_read_lat_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
rdata : in std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
-- read data valid (associated signals) interface
seq_rdv_doing_rd : out std_logic_vector(MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 downto 0);
rdata_valid : in std_logic_vector( DWIDTH_RATIO/2 - 1 downto 0);
seq_rdata_valid_lat_inc : out std_logic;
seq_rdata_valid_lat_dec : out std_logic;
seq_ctl_rlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- postamble interface (unused for Cyclone-III)
seq_poa_lat_dec_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_lat_inc_1x : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_poa_protection_override_1x : out std_logic;
-- OCT path control
seq_oct_oct_delay : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_oct_extend : out std_logic_vector(OCT_LAT_WIDTH - 1 downto 0);
seq_oct_value : out std_logic;
-- write data path interface
seq_wdp_dqs_burst : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata_valid : out std_logic_vector((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 downto 0);
seq_wdp_wdata : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DWIDTH - 1 downto 0);
seq_wdp_dm : out std_logic_vector( DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 downto 0);
seq_wdp_dqs : out std_logic_vector( DWIDTH_RATIO - 1 downto 0);
seq_wdp_ovride : out std_logic;
seq_dqs_add_2t_delay : out std_logic_vector(MEM_IF_DQS_WIDTH - 1 downto 0);
seq_ctl_wlat : out std_logic_vector(ADV_LAT_WIDTH - 1 downto 0);
-- mimic path interface
seq_mmc_start : out std_logic;
mmc_seq_done : in std_logic;
mmc_seq_value : in std_logic;
-- parity signals (not used for non-levelled PHY)
mem_err_out_n : in std_logic;
parity_error_n : out std_logic;
--synchronous Avalon debug interface (internally re-synchronised to input clock (a generic option))
dbg_seq_clk : in std_logic;
dbg_seq_rst_n : in std_logic;
dbg_seq_addr : in std_logic_vector(AV_IF_ADDR_WIDTH - 1 downto 0);
dbg_seq_wr : in std_logic;
dbg_seq_rd : in std_logic;
dbg_seq_cs : in std_logic;
dbg_seq_wr_data : in std_logic_vector(31 downto 0);
seq_dbg_rd_data : out std_logic_vector(31 downto 0);
seq_dbg_waitrequest : out std_logic
);
end entity;
library work;
-- The record package (alt_mem_phy_record_pkg) is used to combine command and status signals
-- (into records) to be passed between sequencer blocks. It also contains type and record definitions
-- for the stages of DRAM memory calibration.
--
use work.ddr2_phy_alt_mem_phy_record_pkg.all;
-- The registers package (alt_mem_phy_regs_pkg) is used to combine the definition of the
-- registers for the mmi status registers and functions/procedures applied to the registers
--
use work.ddr2_phy_alt_mem_phy_regs_pkg.all;
-- The constant package (alt_mem_phy_constants_pkg) contains global 'constants' which are fixed
-- thoughout the sequencer and will not change (for constants which may change between sequencer
-- instances generics are used)
--
use work.ddr2_phy_alt_mem_phy_constants_pkg.all;
-- The iram address package (alt_mem_phy_iram_addr_pkg) is used to define the base addresses used
-- for iram writes during calibration
--
use work.ddr2_phy_alt_mem_phy_iram_addr_pkg.all;
-- The address and command package (alt_mem_phy_addr_cmd_pkg) is used to combine DRAM address
-- and command signals in one record and unify the functions operating on this record.
--
use work.ddr2_phy_alt_mem_phy_addr_cmd_pkg.all;
-- Individually include each of library files for the sub-blocks of the sequencer:
--
use work.ddr2_phy_alt_mem_phy_admin;
--
use work.ddr2_phy_alt_mem_phy_mmi;
--
use work.ddr2_phy_alt_mem_phy_iram;
--
use work.ddr2_phy_alt_mem_phy_dgrb;
--
use work.ddr2_phy_alt_mem_phy_dgwb;
--
use work.ddr2_phy_alt_mem_phy_ctrl;
--
architecture struct of ddr2_phy_alt_mem_phy_seq IS
attribute altera_attribute : string;
attribute altera_attribute of struct : architecture is "-name MESSAGE_DISABLE 18010";
-- debug signals (similar to those seen in the Quartus v8.0 DDR/DDR2 sequencer)
signal rsu_multiple_valid_latencies_err : std_logic; -- true if >2 valid latency values are detected
signal rsu_grt_one_dvw_err : std_logic; -- true if >1 data valid window is detected
signal rsu_no_dvw_err : std_logic; -- true if no data valid window is detected
signal rsu_codvw_phase : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_codvw_size : std_logic_vector(11 downto 0); -- set to the phase of the DVW detected if calibration is successful
signal rsu_read_latency : std_logic_vector(ADV_LAT_WIDTH - 1 downto 0); -- set to the correct read latency if calibration is successful
-- outputs from the dgrb to generate the above rsu_codvw_* signals and report status to the mmi
signal dgrb_mmi : t_dgrb_mmi;
-- admin to mmi interface
signal regs_admin_ctrl_rec : t_admin_ctrl; -- mmi register settings information
signal admin_regs_status_rec : t_admin_stat; -- admin status information
-- odt enable from the admin block based on mr settings
signal enable_odt : std_logic;
-- iram status information (sent to the ctrl block)
signal iram_status : t_iram_stat;
-- dgrb iram write interface
signal dgrb_iram : t_iram_push;
-- ctrl to iram interface
signal ctrl_idib_top : natural; -- current write location in the iram
signal ctrl_active_block : t_ctrl_active_block;
signal ctrl_iram_push : t_ctrl_iram;
signal iram_push_done : std_logic;
signal ctrl_iram_ihi_write : std_logic;
-- local copies of calibration status
signal ctl_init_success_int : std_logic;
signal ctl_init_fail_int : std_logic;
-- refresh period failure flag
signal trefi_failure : std_logic;
-- unified ctrl signal broadcast to all blocks from the ctrl block
signal ctrl_broadcast : t_ctrl_command;
-- standardised status report per block to control block
signal admin_ctrl : t_ctrl_stat;
signal dgwb_ctrl : t_ctrl_stat;
signal dgrb_ctrl : t_ctrl_stat;
-- mmi and ctrl block interface
signal mmi_ctrl : t_mmi_ctrl;
signal ctrl_mmi : t_ctrl_mmi;
-- write datapath override signals
signal dgwb_wdp_override : std_logic;
signal dgrb_wdp_override : std_logic;
-- address/command access request and grant between the dgrb/dgwb blocks and the admin block
signal dgb_ac_access_gnt : std_logic;
signal dgb_ac_access_gnt_r : std_logic;
signal dgb_ac_access_req : std_logic;
signal dgwb_ac_access_req : std_logic;
signal dgrb_ac_access_req : std_logic;
-- per block address/command record (multiplexed in this entity)
signal admin_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgwb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
signal dgrb_ac : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
-- doing read signal
signal seq_rdv_doing_rd_int : std_logic_vector(seq_rdv_doing_rd'range);
-- local copy of interface to inc/dec latency on rdata_valid and postamble
signal seq_rdata_valid_lat_dec_int : std_logic;
signal seq_rdata_valid_lat_inc_int : std_logic;
signal seq_poa_lat_inc_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
signal seq_poa_lat_dec_1x_int : std_logic_vector(MEM_IF_DQS_WIDTH -1 downto 0);
-- local copy of write/read latency
signal seq_ctl_wlat_int : std_logic_vector(seq_ctl_wlat'range);
signal seq_ctl_rlat_int : std_logic_vector(seq_ctl_rlat'range);
-- parameterisation of dgrb / dgwb / admin blocks from mmi register settings
signal parameterisation_rec : t_algm_paramaterisation;
-- PLL reconfig
signal seq_pll_phs_shift_busy_r : std_logic;
signal seq_pll_phs_shift_busy_ccd : std_logic;
signal dgrb_pll_inc_dec_n : std_logic;
signal dgrb_pll_start_reconfig : std_logic;
signal dgrb_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal dgrb_phs_shft_busy : std_logic;
signal mmi_pll_inc_dec_n : std_logic;
signal mmi_pll_start_reconfig : std_logic;
signal mmi_pll_select : std_logic_vector(CLOCK_INDEX_WIDTH - 1 downto 0);
signal pll_mmi : t_pll_mmi;
signal mmi_pll : t_mmi_pll_reconfig;
-- address and command 1t setting (unused for Full Rate)
signal int_ac_nt : std_logic_vector(((DWIDTH_RATIO+2)/4) - 1 downto 0);
signal dgrb_ctrl_ac_nt_good : std_logic;
-- the following signals are reserved for future use
signal ctl_cal_byte_lanes_r : std_logic_vector(ctl_cal_byte_lanes'range);
signal mmi_setup : t_ctrl_cmd_id;
signal dgwb_iram : t_iram_push;
-- track number of poa / rdv adjustments (reporting only)
signal poa_adjustments : natural;
signal rdv_adjustments : natural;
-- convert input generics from natural to std_logic_vector
constant c_phy_def_mr_1st_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_1ST, 16));
constant c_phy_def_mr_2nd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_2ND, 16));
constant c_phy_def_mr_3rd_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_3RD, 16));
constant c_phy_def_mr_4th_sl_vector : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(PHY_DEF_MR_4TH, 16));
-- overrride on capabilities to speed up simulation time
function capabilities_override(capabilities : natural;
sim_time_reductions : natural) return natural is
begin
if sim_time_reductions = 1 then
return 2**c_hl_css_reg_cal_dis_bit; -- disable calibration completely
else
return capabilities;
end if;
end function;
-- set sequencer capabilities
constant c_capabilities_override : natural := capabilities_override(CAPABILITIES, SIM_TIME_REDUCTIONS);
constant c_capabilities : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override,32));
-- setup for address/command interface
constant c_seq_addr_cmd_config : t_addr_cmd_config_rec := set_config_rec(MEM_IF_ADDR_WIDTH, MEM_IF_BANKADDR_WIDTH, MEM_IF_NUM_RANKS, DWIDTH_RATIO, MEM_IF_MEMTYPE);
-- setup for odt signals
-- odt setting as implemented in the altera high-performance controller for ddrx memories
constant c_odt_settings : t_odt_array(0 to MEM_IF_NUM_RANKS-1) := set_odt_values(MEM_IF_NUM_RANKS, MEM_IF_RANKS_PER_SLOT, MEM_IF_MEMTYPE);
-- a prefix for all report signals to identify phy and sequencer block
--
constant seq_report_prefix : string := "ddr2_phy_alt_mem_phy_seq (top) : ";
-- setup iram configuration
constant c_iram_addresses : t_base_hdr_addresses := calc_iram_addresses(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_NUM_RANKS, MEM_IF_DQS_CAPTURE_EN);
constant c_int_iram_awidth : natural := c_iram_addresses.required_addr_bits;
constant c_preset_cal_setup : t_preset_cal := setup_instant_on(SIM_TIME_REDUCTIONS, FAMILYGROUP_ID, MEM_IF_MEMTYPE, DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, c_phy_def_mr_1st_sl_vector, c_phy_def_mr_2nd_sl_vector, c_phy_def_mr_3rd_sl_vector);
constant c_preset_codvw_phase : natural := c_preset_cal_setup.codvw_phase;
constant c_preset_codvw_size : natural := c_preset_cal_setup.codvw_size;
constant c_tracking_interval_in_ms : natural := 128;
constant c_mem_if_cal_bank : natural := 0; -- location to calibrate to
constant c_mem_if_cal_base_col : natural := 0; -- default all zeros
constant c_mem_if_cal_base_row : natural := 0;
constant c_non_op_eval_md : string := "PIN_FINDER"; -- non_operational evaluation mode (used when GENERATE_ADDITIONAL_DBG_RTL = 1)
begin -- architecture struct
-- ---------------------------------------------------------------
-- tie off unused signals to default values
-- ---------------------------------------------------------------
-- scan chain associated signals
seq_scan_clk <= (others => '0');
seq_scan_enable_dqs_config <= (others => '0');
seq_scan_update <= (others => '0');
seq_scan_din <= (others => '0');
seq_scan_enable_ck <= (others => '0');
seq_scan_enable_dqs <= (others => '0');
seq_scan_enable_dqsn <= (others => '0');
seq_scan_enable_dq <= (others => '0');
seq_scan_enable_dm <= (others => '0');
seq_dqs_add_2t_delay <= (others => '0');
seq_rdp_inc_read_lat_1x <= (others => '0');
seq_rdp_dec_read_lat_1x <= (others => '0');
-- warning flag (not used in non-levelled sequencer)
ctl_init_warning <= '0';
-- parity error flag (not used in non-levelled sequencer)
parity_error_n <= '1';
--
admin: entity ddr2_phy_alt_mem_phy_admin
generic map
(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_DQSN_EN => MEM_IF_DQSN_EN,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_ROW => c_mem_if_cal_base_row,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
NON_OP_EVAL_MD => c_non_op_eval_md,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TINIT_TCK => TINIT_TCK,
TINIT_RST => TINIT_RST
)
port map
(
clk => clk,
rst_n => rst_n,
mem_ac_swapped_ranks => mem_ac_swapped_ranks,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
seq_ac => admin_ac,
seq_ac_sel => seq_ac_sel,
enable_odt => enable_odt,
regs_admin_ctrl_rec => regs_admin_ctrl_rec,
admin_regs_status_rec => admin_regs_status_rec,
trefi_failure => trefi_failure,
ctrl_admin => ctrl_broadcast,
admin_ctrl => admin_ctrl,
ac_access_req => dgb_ac_access_req,
ac_access_gnt => dgb_ac_access_gnt,
cal_fail => ctl_init_fail_int,
cal_success => ctl_init_success_int,
ctl_recalibrate_req => ctl_recalibrate_req
);
-- selectively include the debug i/f (iram and mmi blocks)
with_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 1 generate
signal mmi_iram : t_iram_ctrl;
signal mmi_iram_enable_writes : std_logic;
signal rrp_mem_loc : natural range 0 to 2 ** c_int_iram_awidth - 1;
signal command_req_r : std_logic;
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
--
mmi : entity ddr2_phy_alt_mem_phy_mmi
generic map (
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_CLK_PAIR_COUNT => MEM_IF_CLK_PAIR_COUNT,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
RESYNCHRONISE_AVALON_DBG => RESYNCHRONISE_AVALON_DBG,
AV_IF_ADDR_WIDTH => AV_IF_ADDR_WIDTH,
NOM_DQS_PHASE_SETTING => NOM_DQS_PHASE_SETTING,
SCAN_CLK_DIVIDE_BY => SCAN_CLK_DIVIDE_BY,
RDP_ADDR_WIDTH => RDP_ADDR_WIDTH,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
IOE_PHASES_PER_TCK => IOE_PHASES_PER_TCK,
IOE_DELAYS_PER_PHS => IOE_DELAYS_PER_PHS,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
PHY_DEF_MR_1ST => c_phy_def_mr_1st_sl_vector,
PHY_DEF_MR_2ND => c_phy_def_mr_2nd_sl_vector,
PHY_DEF_MR_3RD => c_phy_def_mr_3rd_sl_vector,
PHY_DEF_MR_4TH => c_phy_def_mr_4th_sl_vector,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
PRESET_RLAT => PRESET_RLAT,
CAPABILITIES => c_capabilities_override,
USE_IRAM => '1', -- always use iram (generic is rfu)
IRAM_AWIDTH => c_int_iram_awidth,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
READ_LAT_WIDTH => ADV_LAT_WIDTH
)
port map(
clk => clk,
rst_n => rst_n,
dbg_seq_clk => dbg_seq_clk,
dbg_seq_rst_n => dbg_seq_rst_n,
dbg_seq_addr => dbg_seq_addr,
dbg_seq_wr => dbg_seq_wr,
dbg_seq_rd => dbg_seq_rd,
dbg_seq_cs => dbg_seq_cs,
dbg_seq_wr_data => dbg_seq_wr_data,
seq_dbg_rd_data => seq_dbg_rd_data,
seq_dbg_waitrequest => seq_dbg_waitrequest,
regs_admin_ctrl => regs_admin_ctrl_rec,
admin_regs_status => admin_regs_status_rec,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi,
int_ac_1t => int_ac_nt(0),
invert_ac_1t => open,
trefi_failure => trefi_failure,
parameterisation_rec => parameterisation_rec,
pll_mmi => pll_mmi,
mmi_pll => mmi_pll,
dgrb_mmi => dgrb_mmi
);
--
iram : entity ddr2_phy_alt_mem_phy_iram
generic map(
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
IRAM_AWIDTH => c_int_iram_awidth,
REFRESH_COUNT_INIT => 12,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
CAPABILITIES => c_capabilities_override,
IP_BUILDNUM => IP_BUILDNUM
)
port map(
clk => clk,
rst_n => rst_n,
mmi_iram => mmi_iram,
mmi_iram_enable_writes => mmi_iram_enable_writes,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_iram => ctrl_broadcast_r,
dgrb_iram => dgrb_iram,
admin_regs_status_rec => admin_regs_status_rec,
ctrl_idib_top => ctrl_idib_top,
ctrl_iram_push => ctrl_iram_push,
dgwb_iram => dgwb_iram
);
-- calculate where current data should go in the iram
process (clk, rst_n)
variable v_words_req : natural range 0 to 2 * MEM_IF_DWIDTH * PLL_STEPS_PER_CYCLE * DWIDTH_RATIO - 1; -- how many words are required
begin
if rst_n = '0' then
ctrl_idib_top <= 0;
command_req_r <= '0';
rrp_mem_loc <= 0;
elsif rising_edge(clk) then
if command_req_r = '0' and ctrl_broadcast_r.command_req = '1' then -- execute once on each command_req assertion
-- default a 'safe location'
ctrl_idib_top <= c_iram_addresses.safe_dummy;
case ctrl_broadcast_r.command is
when cmd_write_ihi => -- reset pointers
rrp_mem_loc <= c_iram_addresses.rrp;
ctrl_idib_top <= 0; -- write header to zero location always
when cmd_rrp_sweep =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- add the current space requirement to v_rrp_mem_loc
-- there are (DWIDTH_RATIO/2) * PLL_STEPS_PER_CYCLE phases swept packed into 32 bit words per pin
-- note: special case for single_bit calibration stages (e.g. read_mtp alignment)
if ctrl_broadcast_r.command_op.single_bit = '1' then
v_words_req := iram_wd_for_one_pin_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
else
v_words_req := iram_wd_for_full_rrp(DWIDTH_RATIO, PLL_STEPS_PER_CYCLE, MEM_IF_DWIDTH, MEM_IF_DQS_CAPTURE_EN);
end if;
v_words_req := v_words_req + 2; -- add 1 word location for header / footer information
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when cmd_rrp_seek |
cmd_read_mtp =>
-- add previous space requirement onto the current address
ctrl_idib_top <= rrp_mem_loc;
-- require 3 words - header, result and footer
v_words_req := 3;
rrp_mem_loc <= rrp_mem_loc + v_words_req;
when others =>
null;
end case;
end if;
command_req_r <= ctrl_broadcast_r.command_req;
-- if recalibration request then reset iram address
if ctl_recalibrate_req = '1' or mmi_ctrl.calibration_start = '1' then
rrp_mem_loc <= c_iram_addresses.rrp;
end if;
end if;
end process;
end generate; -- with debug interface
-- if no debug interface (iram/mmi block) tie off relevant signals
without_debug_if : if GENERATE_ADDITIONAL_DBG_RTL = 0 generate
constant c_slv_hl_stage_enable : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(c_capabilities_override, 32));
constant c_hl_stage_enable : std_logic_vector(c_hl_ccs_num_stages-1 downto 0) := c_slv_hl_stage_enable(c_hl_ccs_num_stages-1 downto 0);
constant c_pll_360_sweeps : natural := rrp_pll_phase_mult(DWIDTH_RATIO, MEM_IF_DQS_CAPTURE_EN);
signal mmi_regs : t_mmi_regs := defaults;
begin
-- avalon interface signals
seq_dbg_rd_data <= (others => '0');
seq_dbg_waitrequest <= '0';
-- The following registers are generated to simplify the assignments which follow
-- but will be optimised away in synthesis
mmi_regs.rw_regs <= defaults(c_phy_def_mr_1st_sl_vector,
c_phy_def_mr_2nd_sl_vector,
c_phy_def_mr_3rd_sl_vector,
c_phy_def_mr_4th_sl_vector,
NOM_DQS_PHASE_SETTING,
PLL_STEPS_PER_CYCLE,
c_pll_360_sweeps,
c_tracking_interval_in_ms,
c_hl_stage_enable);
mmi_regs.ro_regs <= defaults(dgrb_mmi,
ctrl_mmi,
pll_mmi,
mmi_regs.rw_regs.rw_if_test,
'0', -- do not use iram
MEM_IF_DQS_CAPTURE_EN,
int_ac_nt(0),
trefi_failure,
iram_status,
c_int_iram_awidth);
process(mmi_regs)
begin
-- debug parameterisation signals
regs_admin_ctrl_rec <= pack_record(mmi_regs.rw_regs);
parameterisation_rec <= pack_record(mmi_regs.rw_regs);
mmi_pll <= pack_record(mmi_regs.rw_regs);
mmi_ctrl <= pack_record(mmi_regs.rw_regs);
end process;
-- from the iram
iram_status <= defaults;
iram_push_done <= '0';
end generate; -- without debug interface
--
dgrb : entity ddr2_phy_alt_mem_phy_dgrb
generic map(
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
MEM_IF_DQS_CAPTURE => MEM_IF_DQS_CAPTURE_EN,
DWIDTH_RATIO => DWIDTH_RATIO,
CLOCK_INDEX_WIDTH => CLOCK_INDEX_WIDTH,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
PRESET_RLAT => PRESET_RLAT,
PLL_STEPS_PER_CYCLE => PLL_STEPS_PER_CYCLE,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
PRESET_CODVW_PHASE => c_preset_codvw_phase,
PRESET_CODVW_SIZE => c_preset_codvw_size,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col,
EN_OCT => EN_OCT
)
port map(
clk => clk,
rst_n => rst_n,
dgrb_ctrl => dgrb_ctrl,
ctrl_dgrb => ctrl_broadcast,
parameterisation_rec => parameterisation_rec,
phs_shft_busy => dgrb_phs_shft_busy,
seq_pll_inc_dec_n => dgrb_pll_inc_dec_n,
seq_pll_select => dgrb_pll_select,
seq_pll_start_reconfig => dgrb_pll_start_reconfig,
pll_resync_clk_index => pll_resync_clk_index,
pll_measure_clk_index => pll_measure_clk_index,
dgrb_iram => dgrb_iram,
iram_push_done => iram_push_done,
dgrb_ac => dgrb_ac,
dgrb_ac_access_req => dgrb_ac_access_req,
dgrb_ac_access_gnt => dgb_ac_access_gnt_r,
seq_rdata_valid_lat_inc => seq_rdata_valid_lat_inc_int,
seq_rdata_valid_lat_dec => seq_rdata_valid_lat_dec_int,
seq_poa_lat_dec_1x => seq_poa_lat_dec_1x_int,
seq_poa_lat_inc_1x => seq_poa_lat_inc_1x_int,
rdata_valid => rdata_valid,
rdata => rdata,
doing_rd => seq_rdv_doing_rd_int,
rd_lat => seq_ctl_rlat_int,
wd_lat => seq_ctl_wlat_int,
dgrb_wdp_ovride => dgrb_wdp_override,
seq_oct_value => seq_oct_value,
seq_mmc_start => seq_mmc_start,
mmc_seq_done => mmc_seq_done,
mmc_seq_value => mmc_seq_value,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
odt_settings => c_odt_settings,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
dgrb_mmi => dgrb_mmi
);
--
dgwb : entity ddr2_phy_alt_mem_phy_dgwb
generic map(
-- Physical IF width definitions
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
MEM_IF_DQ_PER_DQS => MEM_IF_DQ_PER_DQS,
MEM_IF_DWIDTH => MEM_IF_DWIDTH,
MEM_IF_DM_WIDTH => MEM_IF_DM_WIDTH,
DWIDTH_RATIO => DWIDTH_RATIO,
MEM_IF_ADDR_WIDTH => MEM_IF_ADDR_WIDTH,
MEM_IF_BANKADDR_WIDTH => MEM_IF_BANKADDR_WIDTH,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
ADV_LAT_WIDTH => ADV_LAT_WIDTH,
MEM_IF_CAL_BANK => c_mem_if_cal_bank,
MEM_IF_CAL_BASE_COL => c_mem_if_cal_base_col
)
port map(
clk => clk,
rst_n => rst_n,
parameterisation_rec => parameterisation_rec,
dgwb_ctrl => dgwb_ctrl,
ctrl_dgwb => ctrl_broadcast,
dgwb_iram => dgwb_iram,
iram_push_done => iram_push_done,
dgwb_ac_access_req => dgwb_ac_access_req,
dgwb_ac_access_gnt => dgb_ac_access_gnt_r,
dgwb_dqs_burst => seq_wdp_dqs_burst,
dgwb_wdata_valid => seq_wdp_wdata_valid,
dgwb_wdata => seq_wdp_wdata,
dgwb_dm => seq_wdp_dm,
dgwb_dqs => seq_wdp_dqs,
dgwb_wdp_ovride => dgwb_wdp_override,
dgwb_ac => dgwb_ac,
bypassed_rdata => rdata(DWIDTH_RATIO * MEM_IF_DWIDTH -1 downto (DWIDTH_RATIO-1) * MEM_IF_DWIDTH),
odt_settings => c_odt_settings
);
--
ctrl: entity ddr2_phy_alt_mem_phy_ctrl
generic map(
FAMILYGROUP_ID => FAMILYGROUP_ID,
MEM_IF_DLL_LOCK_COUNT => 1280/(DWIDTH_RATIO/2),
MEM_IF_MEMTYPE => MEM_IF_MEMTYPE,
DWIDTH_RATIO => DWIDTH_RATIO,
IRAM_ADDRESSING => c_iram_addresses,
MEM_IF_CLK_PS => MEM_IF_CLK_PS,
TRACKING_INTERVAL_IN_MS => c_tracking_interval_in_ms,
GENERATE_ADDITIONAL_DBG_RTL => GENERATE_ADDITIONAL_DBG_RTL,
MEM_IF_NUM_RANKS => MEM_IF_NUM_RANKS,
MEM_IF_DQS_WIDTH => MEM_IF_DQS_WIDTH,
SIM_TIME_REDUCTIONS => SIM_TIME_REDUCTIONS,
ACK_SEVERITY => warning
)
port map(
clk => clk,
rst_n => rst_n,
ctl_init_success => ctl_init_success_int,
ctl_init_fail => ctl_init_fail_int,
ctl_recalibrate_req => ctl_recalibrate_req,
iram_status => iram_status,
iram_push_done => iram_push_done,
ctrl_op_rec => ctrl_broadcast,
admin_ctrl => admin_ctrl,
dgrb_ctrl => dgrb_ctrl,
dgwb_ctrl => dgwb_ctrl,
ctrl_iram_push => ctrl_iram_push,
ctl_cal_byte_lanes => ctl_cal_byte_lanes_r,
dgrb_ctrl_ac_nt_good => dgrb_ctrl_ac_nt_good,
int_ac_nt => int_ac_nt,
mmi_ctrl => mmi_ctrl,
ctrl_mmi => ctrl_mmi
);
-- ------------------------------------------------------------------
-- generate legacy rsu signals
-- ------------------------------------------------------------------
process(rst_n, clk)
begin
if rst_n = '0' then
rsu_multiple_valid_latencies_err <= '0';
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_codvw_phase <= (others => '0');
rsu_codvw_size <= (others => '0');
rsu_read_latency <= (others => '0');
elsif rising_edge(clk) then
if dgrb_ctrl.command_err = '1' then
case to_integer(unsigned(dgrb_ctrl.command_result)) is
when C_ERR_RESYNC_NO_VALID_PHASES =>
rsu_no_dvw_err <= '1';
when C_ERR_RESYNC_MULTIPLE_EQUAL_WINDOWS =>
rsu_multiple_valid_latencies_err <= '1';
when others => null;
end case;
end if;
rsu_codvw_phase(dgrb_mmi.cal_codvw_phase'range) <= dgrb_mmi.cal_codvw_phase;
rsu_codvw_size(dgrb_mmi.cal_codvw_size'range) <= dgrb_mmi.cal_codvw_size;
rsu_read_latency <= seq_ctl_rlat_int;
rsu_grt_one_dvw_err <= dgrb_mmi.codvw_grt_one_dvw;
-- Reset the flag on a recal request :
if ( ctl_recalibrate_req = '1') then
rsu_grt_one_dvw_err <= '0';
rsu_no_dvw_err <= '0';
rsu_multiple_valid_latencies_err <= '0';
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- top level multiplexing and ctrl functionality
-- ---------------------------------------------------------------
oct_delay_block : block
constant DEFAULT_OCT_DELAY_CONST : integer := - 2; -- higher increases delay by one mem_clk cycle, lower decreases delay by one mem_clk cycle.
constant DEFAULT_OCT_EXTEND : natural := 3;
-- Returns additive latency extracted from mr0 as a natural number.
function decode_cl(mr0 : in std_logic_vector(12 downto 0))
return natural is
variable v_cl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_cl := to_integer(unsigned(mr0(6 downto 4)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cl := to_integer(unsigned(mr0(6 downto 4))) + 4;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cl;
end function;
-- Returns additive latency extracted from mr1 as a natural number.
function decode_al(mr1 : in std_logic_vector(12 downto 0))
return natural is
variable v_al : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" or MEM_IF_MEMTYPE = "DDR2" then
v_al := to_integer(unsigned(mr1(5 downto 3)));
elsif MEM_IF_MEMTYPE = "DDR3" then
v_al := to_integer(unsigned(mr1(4 downto 3)));
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_al;
end function;
-- Returns cas write latency extracted from mr2 as a natural number.
function decode_cwl(
mr0 : in std_logic_vector(12 downto 0);
mr2 : in std_logic_vector(12 downto 0)
)
return natural is
variable v_cwl : natural range 0 to 2**4 - 1;
begin
if MEM_IF_MEMTYPE = "DDR" then
v_cwl := 1;
elsif MEM_IF_MEMTYPE = "DDR2" then
v_cwl := decode_cl(mr0) - 1;
elsif MEM_IF_MEMTYPE = "DDR3" then
v_cwl := to_integer(unsigned(mr2(4 downto 3))) + 5;
else
report "Unsupported memory type " & MEM_IF_MEMTYPE severity failure;
end if;
return v_cwl;
end function;
begin
-- Process to work out timings for OCT extension and delay with respect to doing_read. NOTE that it is calculated on the basis of CL, CWL, ctl_wlat
oct_delay_proc : process(clk, rst_n)
variable v_cl : natural range 0 to 2**4 - 1; -- Total read latency.
variable v_cwl : natural range 0 to 2**4 - 1; -- Total write latency
variable oct_delay : natural range 0 to 2**OCT_LAT_WIDTH - 1;
variable v_wlat : natural range 0 to 2**ADV_LAT_WIDTH - 1;
begin
if rst_n = '0' then
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
elsif rising_edge(clk) then
if ctl_init_success_int = '1' then
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
v_cl := decode_cl(admin_regs_status_rec.mr0);
v_cwl := decode_cwl(admin_regs_status_rec.mr0, admin_regs_status_rec.mr2);
if SIM_TIME_REDUCTIONS = 1 then
v_wlat := c_preset_cal_setup.wlat;
else
v_wlat := to_integer(unsigned(seq_ctl_wlat_int));
end if;
oct_delay := DWIDTH_RATIO * v_wlat / 2 + (v_cl - v_cwl) + DEFAULT_OCT_DELAY_CONST;
if not (FAMILYGROUP_ID = 2) then -- CIII doesn't support OCT
seq_oct_oct_delay <= std_logic_vector(to_unsigned(oct_delay, OCT_LAT_WIDTH));
end if;
else
seq_oct_oct_delay <= (others => '0');
seq_oct_oct_extend <= std_logic_vector(to_unsigned(DEFAULT_OCT_EXTEND, OCT_LAT_WIDTH));
end if;
end if;
end process;
end block;
-- control postamble protection override signal (seq_poa_protection_override_1x)
process(clk, rst_n)
variable v_warning_given : std_logic;
begin
if rst_n = '0' then
seq_poa_protection_override_1x <= '0';
v_warning_given := '0';
elsif rising_edge(clk) then
case ctrl_broadcast.command is
when cmd_rdv |
cmd_rrp_sweep |
cmd_rrp_seek |
cmd_prep_adv_rd_lat |
cmd_prep_adv_wr_lat => seq_poa_protection_override_1x <= '1';
when others => seq_poa_protection_override_1x <= '0';
end case;
end if;
end process;
ac_mux : block
constant c_mem_clk_disable_pipe_len : natural := 3;
signal seen_phy_init_complete : std_logic;
signal mem_clk_disable : std_logic_vector(c_mem_clk_disable_pipe_len - 1 downto 0);
signal ctrl_broadcast_r : t_ctrl_command;
begin
-- register ctrl_broadcast locally
-- #for speed and to reduce fan out
process (clk, rst_n)
begin
if rst_n = '0' then
ctrl_broadcast_r <= defaults;
elsif rising_edge(clk) then
ctrl_broadcast_r <= ctrl_broadcast;
end if;
end process;
-- multiplex mem interface control between admin, dgrb and dgwb
process(clk, rst_n)
variable v_seq_ac_mux : t_addr_cmd_vector(0 to (DWIDTH_RATIO/2)-1);
begin
if rst_n = '0' then
seq_rdv_doing_rd <= (others => '0');
seq_mem_clk_disable <= '1';
mem_clk_disable <= (others => '1');
seen_phy_init_complete <= '0';
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
elsif rising_edge(clk) then
seq_rdv_doing_rd <= seq_rdv_doing_rd_int;
seq_mem_clk_disable <= mem_clk_disable(c_mem_clk_disable_pipe_len-1);
mem_clk_disable(c_mem_clk_disable_pipe_len-1 downto 1) <= mem_clk_disable(c_mem_clk_disable_pipe_len-2 downto 0);
if dgwb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgwb_ac;
elsif dgrb_ac_access_req = '1' and dgb_ac_access_gnt = '1' then
v_seq_ac_mux := dgrb_ac;
else
v_seq_ac_mux := admin_ac;
end if;
if ctl_recalibrate_req = '1' then
mem_clk_disable(0) <= '1';
seen_phy_init_complete <= '0';
elsif ctrl_broadcast_r.command = cmd_init_dram and ctrl_broadcast_r.command_req = '1' then
mem_clk_disable(0) <= '0';
seen_phy_init_complete <= '1';
end if;
if seen_phy_init_complete /= '1' then -- if not initialised the phy hold in reset
seq_ac_addr <= (others => '0');
seq_ac_ba <= (others => '0');
seq_ac_cas_n <= (others => '1');
seq_ac_ras_n <= (others => '1');
seq_ac_we_n <= (others => '1');
seq_ac_cke <= (others => '0');
seq_ac_cs_n <= (others => '1');
seq_ac_odt <= (others => '0');
seq_ac_rst_n <= (others => '0');
else
if enable_odt = '0' then
v_seq_ac_mux := mask(c_seq_addr_cmd_config, v_seq_ac_mux, odt, '0');
end if;
unpack_addr_cmd_vector (
c_seq_addr_cmd_config,
v_seq_ac_mux,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n);
end if;
end if;
end process;
end block;
-- register dgb_ac_access_gnt signal to ensure ODT set correctly in dgrb and dgwb prior to a read or write operation
process(clk, rst_n)
begin
if rst_n = '0' then
dgb_ac_access_gnt_r <= '0';
elsif rising_edge(clk) then
dgb_ac_access_gnt_r <= dgb_ac_access_gnt;
end if;
end process;
-- multiplex access request from dgrb/dgwb to admin block with checking for multiple accesses
process (dgrb_ac_access_req, dgwb_ac_access_req)
begin
dgb_ac_access_req <= '0';
if dgwb_ac_access_req = '1' and dgrb_ac_access_req = '1' then
report seq_report_prefix & "multiple accesses attempted from DGRB and DGWB to admin block via signals dg.b_ac_access_reg " severity failure;
elsif dgwb_ac_access_req = '1' or dgrb_ac_access_req = '1' then
dgb_ac_access_req <= '1';
end if;
end process;
rdv_poa_blk : block
-- signals to control static setup of ctl_rdata_valid signal for instant on mode:
constant c_static_rdv_offset : integer := c_preset_cal_setup.rdv_lat; -- required change in RDV latency (should always be > 0)
signal static_rdv_offset : natural range 0 to abs(c_static_rdv_offset); -- signal to count # RDV shifts
constant c_dly_rdv_set : natural := 7; -- delay between RDV shifts
signal dly_rdv_inc_dec : std_logic; -- 1 = inc, 0 = dec
signal rdv_set_delay : natural range 0 to c_dly_rdv_set; -- signal to delay RDV shifts
-- same for poa protection
constant c_static_poa_offset : integer := c_preset_cal_setup.poa_lat;
signal static_poa_offset : natural range 0 to abs(c_static_poa_offset);
constant c_dly_poa_set : natural := 7;
signal dly_poa_inc_dec : std_logic;
signal poa_set_delay : natural range 0 to c_dly_poa_set;
-- function to abstract increment or decrement checking
function set_inc_dec(offset : integer) return std_logic is
begin
if offset < 0 then
return '1';
else
return '0';
end if;
end function;
begin
-- register postamble and rdata_valid latencies
-- note: postamble unused for Cyclone-III
-- RDV
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
end if;
seq_rdata_valid_lat_dec <= '0';
seq_rdata_valid_lat_inc <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- perform static setup of RDV signal
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_rdv_offset <= abs(c_static_rdv_offset);
dly_rdv_inc_dec <= set_inc_dec(c_static_rdv_offset);
rdv_set_delay <= c_dly_rdv_set;
else
if static_rdv_offset /= 0 and
rdv_set_delay = 0 then
seq_rdata_valid_lat_dec <= not dly_rdv_inc_dec;
seq_rdata_valid_lat_inc <= dly_rdv_inc_dec;
static_rdv_offset <= static_rdv_offset - 1;
rdv_set_delay <= c_dly_rdv_set;
else -- once conplete pass through internal signals
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
if rdv_set_delay /= 0 then
rdv_set_delay <= rdv_set_delay - 1;
end if;
end if;
else -- no static setup
seq_rdata_valid_lat_dec <= seq_rdata_valid_lat_dec_int;
seq_rdata_valid_lat_inc <= seq_rdata_valid_lat_inc_int;
end if;
end if;
end process;
-- count number of RDV adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
rdv_adjustments <= 0;
elsif rising_edge(clk) then
if seq_rdata_valid_lat_dec_int = '1' then
rdv_adjustments <= rdv_adjustments + 1;
end if;
if seq_rdata_valid_lat_inc_int = '1' then
if rdv_adjustments = 0 then
report seq_report_prefix & " read data valid adjustment wrap around detected - more increments than decrements" severity failure;
else
rdv_adjustments <= rdv_adjustments - 1;
end if;
end if;
end if;
end process;
-- POA protection
process(clk, rst_n)
begin
if rst_n = '0' then
if SIM_TIME_REDUCTIONS = 1 then
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
end if;
seq_poa_lat_dec_1x <= (others => '0');
seq_poa_lat_inc_1x <= (others => '0');
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then -- static setup
if ctl_recalibrate_req = '1' then -- second reset condition
-- setup offset calc
static_poa_offset <= abs(c_static_poa_offset);
dly_poa_inc_dec <= set_inc_dec(c_static_poa_offset);
poa_set_delay <= c_dly_poa_set;
else
if static_poa_offset /= 0 and
poa_set_delay = 0 then
seq_poa_lat_dec_1x <= (others => not(dly_poa_inc_dec));
seq_poa_lat_inc_1x <= (others => dly_poa_inc_dec);
static_poa_offset <= static_poa_offset - 1;
poa_set_delay <= c_dly_poa_set;
else
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
if poa_set_delay /= 0 then
poa_set_delay <= poa_set_delay - 1;
end if;
end if;
else -- no static setup
seq_poa_lat_inc_1x <= seq_poa_lat_inc_1x_int;
seq_poa_lat_dec_1x <= seq_poa_lat_dec_1x_int;
end if;
end if;
end process;
-- count POA protection adjustments for debug
process(clk, rst_n)
begin
if rst_n = '0' then
poa_adjustments <= 0;
elsif rising_edge(clk) then
if seq_poa_lat_dec_1x_int(0) = '1' then
poa_adjustments <= poa_adjustments + 1;
end if;
if seq_poa_lat_inc_1x_int(0) = '1' then
if poa_adjustments = 0 then
report seq_report_prefix & " postamble adjustment wrap around detected - more increments than decrements" severity failure;
else
poa_adjustments <= poa_adjustments - 1;
end if;
end if;
end if;
end process;
end block;
-- register output fail/success signals - avoiding optimisation out
process(clk, rst_n)
begin
if rst_n = '0' then
ctl_init_fail <= '0';
ctl_init_success <= '0';
elsif rising_edge(clk) then
ctl_init_fail <= ctl_init_fail_int;
ctl_init_success <= ctl_init_success_int;
end if;
end process;
-- ctl_cal_byte_lanes register
-- seq_rdp_reset_req_n - when ctl_recalibrate_req issued
process(clk,rst_n)
begin
if rst_n = '0' then
seq_rdp_reset_req_n <= '0';
ctl_cal_byte_lanes_r <= (others => '1');
elsif rising_edge(clk) then
ctl_cal_byte_lanes_r <= not ctl_cal_byte_lanes;
if ctl_recalibrate_req = '1' then
seq_rdp_reset_req_n <= '0';
else
if ctrl_broadcast.command = cmd_rrp_sweep or
SIM_TIME_REDUCTIONS = 1 then
seq_rdp_reset_req_n <= '1';
end if;
end if;
end if;
end process;
-- register 1t addr/cmd and odt latency outputs
process(clk, rst_n)
begin
if rst_n = '0' then
seq_ac_add_1t_ac_lat_internal <= '0';
seq_ac_add_1t_odt_lat_internal <= '0';
seq_ac_add_2t <= '0';
elsif rising_edge(clk) then
if SIM_TIME_REDUCTIONS = 1 then
seq_ac_add_1t_ac_lat_internal <= c_preset_cal_setup.ac_1t;
seq_ac_add_1t_odt_lat_internal <= c_preset_cal_setup.ac_1t;
else
seq_ac_add_1t_ac_lat_internal <= int_ac_nt(0);
seq_ac_add_1t_odt_lat_internal <= int_ac_nt(0);
end if;
seq_ac_add_2t <= '0';
end if;
end process;
-- override write datapath signal generation
process(dgwb_wdp_override, dgrb_wdp_override, ctl_init_success_int, ctl_init_fail_int)
begin
if ctl_init_success_int = '0' and ctl_init_fail_int = '0' then -- if calibrating
seq_wdp_ovride <= dgwb_wdp_override or dgrb_wdp_override;
else
seq_wdp_ovride <= '0';
end if;
end process;
-- output write/read latency (override with preset values when sim time reductions equals 1
seq_ctl_wlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.wlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_wlat_int;
seq_ctl_rlat <= std_logic_vector(to_unsigned(c_preset_cal_setup.rlat,ADV_LAT_WIDTH)) when SIM_TIME_REDUCTIONS = 1 else seq_ctl_rlat_int;
process (clk, rst_n)
begin
if rst_n = '0' then
seq_pll_phs_shift_busy_r <= '0';
seq_pll_phs_shift_busy_ccd <= '0';
elsif rising_edge(clk) then
seq_pll_phs_shift_busy_r <= seq_pll_phs_shift_busy;
seq_pll_phs_shift_busy_ccd <= seq_pll_phs_shift_busy_r;
end if;
end process;
pll_ctrl: block
-- static resync setup variables for sim time reductions
signal static_rst_offset : natural range 0 to 2*PLL_STEPS_PER_CYCLE;
signal phs_shft_busy_1r : std_logic;
signal pll_set_delay : natural range 100 downto 0; -- wait 100 clock cycles for clk to be stable before setting resync phase
-- pll signal generation
signal mmi_pll_active : boolean;
signal seq_pll_phs_shift_busy_ccd_1t : std_logic;
begin
-- multiplex ppl interface between dgrb and mmi blocks
-- plus static setup of rsc phase to a known 'good' condition
process(clk,rst_n)
begin
if rst_n = '0' then
seq_pll_inc_dec_n <= '0';
seq_pll_start_reconfig <= '0';
seq_pll_select <= (others => '0');
dgrb_phs_shft_busy <= '0';
-- static resync setup variables for sim time reductions
if SIM_TIME_REDUCTIONS = 1 then
static_rst_offset <= c_preset_codvw_phase;
else
static_rst_offset <= 0;
end if;
phs_shft_busy_1r <= '0';
pll_set_delay <= 100;
elsif rising_edge(clk) then
dgrb_phs_shft_busy <= '0';
if static_rst_offset /= 0 and -- not finished decrementing
pll_set_delay = 0 and -- initial reset period over
SIM_TIME_REDUCTIONS = 1 then -- in reduce sim time mode (optimse logic away when not in this mode)
seq_pll_inc_dec_n <= '1';
seq_pll_start_reconfig <= '1';
seq_pll_select <= pll_resync_clk_index;
if seq_pll_phs_shift_busy_ccd = '1' then -- no metastability hardening needed in simulation
-- PLL phase shift started - so stop requesting a shift
seq_pll_start_reconfig <= '0';
end if;
if seq_pll_phs_shift_busy_ccd = '0' and phs_shft_busy_1r = '1' then
-- PLL phase shift finished - so proceed to flush the datapath
static_rst_offset <= static_rst_offset - 1;
seq_pll_start_reconfig <= '0';
end if;
phs_shft_busy_1r <= seq_pll_phs_shift_busy_ccd;
else
if ctrl_iram_push.active_block = ret_dgrb then
seq_pll_inc_dec_n <= dgrb_pll_inc_dec_n;
seq_pll_start_reconfig <= dgrb_pll_start_reconfig;
seq_pll_select <= dgrb_pll_select;
dgrb_phs_shft_busy <= seq_pll_phs_shift_busy_ccd;
else
seq_pll_inc_dec_n <= mmi_pll_inc_dec_n;
seq_pll_start_reconfig <= mmi_pll_start_reconfig;
seq_pll_select <= mmi_pll_select;
end if;
end if;
if pll_set_delay /= 0 then
pll_set_delay <= pll_set_delay - 1;
end if;
if ctl_recalibrate_req = '1' then
pll_set_delay <= 100;
end if;
end if;
end process;
-- generate mmi pll signals
process (clk, rst_n)
begin
if rst_n = '0' then
pll_mmi.pll_busy <= '0';
pll_mmi.err <= (others => '0');
mmi_pll_inc_dec_n <= '0';
mmi_pll_start_reconfig <= '0';
mmi_pll_select <= (others => '0');
mmi_pll_active <= false;
seq_pll_phs_shift_busy_ccd_1t <= '0';
elsif rising_edge(clk) then
if mmi_pll_active = true then
pll_mmi.pll_busy <= '1';
else
pll_mmi.pll_busy <= mmi_pll.pll_phs_shft_up_wc or mmi_pll.pll_phs_shft_dn_wc;
end if;
if pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' then
pll_mmi.err <= "01";
elsif pll_mmi.err = "00" and mmi_pll_active = true then
pll_mmi.err <= "10";
elsif pll_mmi.err = "00" and dgrb_pll_start_reconfig = '1' and mmi_pll_active = true then
pll_mmi.err <= "11";
end if;
if mmi_pll.pll_phs_shft_up_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '1';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif mmi_pll.pll_phs_shft_dn_wc = '1' and mmi_pll_active = false then
mmi_pll_inc_dec_n <= '0';
mmi_pll_select <= std_logic_vector(to_unsigned(mmi_pll.pll_phs_shft_phase_sel,mmi_pll_select'length));
mmi_pll_active <= true;
elsif seq_pll_phs_shift_busy_ccd_1t = '1' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '0';
mmi_pll_active <= false;
elsif mmi_pll_active = true and mmi_pll_start_reconfig = '0' and seq_pll_phs_shift_busy_ccd = '0' then
mmi_pll_start_reconfig <= '1';
elsif seq_pll_phs_shift_busy_ccd_1t = '0' and seq_pll_phs_shift_busy_ccd = '1' then
mmi_pll_start_reconfig <= '0';
end if;
seq_pll_phs_shift_busy_ccd_1t <= seq_pll_phs_shift_busy_ccd;
end if;
end process;
end block; -- pll_ctrl
--synopsys synthesis_off
reporting : block
function pass_or_fail_report( cal_success : in std_logic;
cal_fail : in std_logic
) return string is
begin
if cal_success = '1' and cal_fail = '1' then
return "unknown state cal_fail and cal_success both high";
end if;
if cal_success = '1' then
return "PASSED";
end if;
if cal_fail = '1' then
return "FAILED";
end if;
return "calibration report run whilst sequencer is still calibrating";
end function;
function is_stage_disabled ( stage_name : in string;
stage_dis : in std_logic
) return string is
begin
if stage_dis = '0' then
return "";
else
return stage_name & " stage is disabled" & LF;
end if;
end function;
function disabled_stages ( capabilities : in std_logic_vector
) return string is
begin
return is_stage_disabled("all calibration", c_capabilities(c_hl_css_reg_cal_dis_bit)) &
is_stage_disabled("initialisation", c_capabilities(c_hl_css_reg_phy_initialise_dis_bit)) &
is_stage_disabled("DRAM initialisation", c_capabilities(c_hl_css_reg_init_dram_dis_bit)) &
is_stage_disabled("iram header write", c_capabilities(c_hl_css_reg_write_ihi_dis_bit)) &
is_stage_disabled("burst training pattern write", c_capabilities(c_hl_css_reg_write_btp_dis_bit)) &
is_stage_disabled("more training pattern (MTP) write", c_capabilities(c_hl_css_reg_write_mtp_dis_bit)) &
is_stage_disabled("check MTP pattern alignment calculation", c_capabilities(c_hl_css_reg_read_mtp_dis_bit)) &
is_stage_disabled("read resynch phase reset stage", c_capabilities(c_hl_css_reg_rrp_reset_dis_bit)) &
is_stage_disabled("read resynch phase sweep stage", c_capabilities(c_hl_css_reg_rrp_sweep_dis_bit)) &
is_stage_disabled("read resynch phase seek stage (set phase)", c_capabilities(c_hl_css_reg_rrp_seek_dis_bit)) &
is_stage_disabled("read data valid window setup", c_capabilities(c_hl_css_reg_rdv_dis_bit)) &
is_stage_disabled("postamble calibration", c_capabilities(c_hl_css_reg_poa_dis_bit)) &
is_stage_disabled("write latency timing calc", c_capabilities(c_hl_css_reg_was_dis_bit)) &
is_stage_disabled("advertise read latency", c_capabilities(c_hl_css_reg_adv_rd_lat_dis_bit)) &
is_stage_disabled("advertise write latency", c_capabilities(c_hl_css_reg_adv_wr_lat_dis_bit)) &
is_stage_disabled("write customer mode register settings", c_capabilities(c_hl_css_reg_prep_customer_mr_setup_dis_bit)) &
is_stage_disabled("tracking", c_capabilities(c_hl_css_reg_tracking_dis_bit));
end function;
function ac_nt_report( ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal) return string
is
variable v_ac_nt : std_logic_vector(0 downto 0);
begin
if SIM_TIME_REDUCTIONS = 1 then
v_ac_nt(0) := preset_cal_setup.ac_1t;
if v_ac_nt(0) = '1' then
return "-- statically set address and command 1T delay: add 1T delay" & LF;
else
return "-- statically set address and command 1T delay: no 1T delay" & LF;
end if;
else
v_ac_nt(0) := ac_nt(0);
if dgrb_ctrl_ac_nt_good = '1' then
if v_ac_nt(0) = '1' then
return "-- chosen address and command 1T delay: add 1T delay" & LF;
else
return "-- chosen address and command 1T delay: no 1T delay" & LF;
end if;
else
return "-- no valid address and command phase chosen (calibration FAILED)" & LF;
end if;
end if;
end function;
function read_resync_report ( codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "-- read resynch phase static setup (no calibration run) report:" & LF &
" -- statically set centre of data valid window phase : " & natural'image(preset_cal_setup.codvw_phase) & LF &
" -- statically set centre of data valid window size : " & natural'image(preset_cal_setup.codvw_size) & LF &
" -- statically set read latency (ctl_rlat) : " & natural'image(preset_cal_setup.rlat) & LF &
" -- statically set write latency (ctl_wlat) : " & natural'image(preset_cal_setup.wlat) & LF &
" -- note: this mode only works for simulation and sets resync phase" & LF &
" to a known good operating condition for no test bench" & LF &
" delays on mem_dq signal" & LF;
else
return "-- PHY read latency (ctl_rlat) is : " & natural'image(to_integer(unsigned(ctl_rlat))) & LF &
"-- address/command to PHY write latency (ctl_wlat) is : " & natural'image(to_integer(unsigned(ctl_wlat))) & LF &
"-- read resynch phase calibration report:" & LF &
" -- calibrated centre of data valid window phase : " & natural'image(to_integer(unsigned(codvw_phase))) & LF &
" -- calibrated centre of data valid window size : " & natural'image(to_integer(unsigned(codvw_size))) & LF;
end if;
end function;
function poa_rdv_adjust_report( poa_adjust : in natural;
rdv_adjust : in natural;
preset_cal_setup : in t_preset_cal) return string
is
begin
if SIM_TIME_REDUCTIONS = 1 then
return "Statically set poa and rdv (adjustments from reset value):" & LF &
"poa 'dec' adjustments = " & natural'image(preset_cal_setup.poa_lat) & LF &
"rdv 'dec' adjustments = " & natural'image(preset_cal_setup.rdv_lat) & LF;
else
return "poa 'dec' adjustments = " & natural'image(poa_adjust) & LF &
"rdv 'dec' adjustments = " & natural'image(rdv_adjust) & LF;
end if;
end function;
function calibration_report ( capabilities : in std_logic_vector;
cal_success : in std_logic;
cal_fail : in std_logic;
ctl_rlat : in std_logic_vector;
ctl_wlat : in std_logic_vector;
codvw_phase : in std_logic_vector;
codvw_size : in std_logic_vector;
ac_nt : in std_logic_vector;
dgrb_ctrl_ac_nt_good : in std_logic;
preset_cal_setup : in t_preset_cal;
poa_adjust : in natural;
rdv_adjust : in natural) return string
is
begin
return seq_report_prefix & " report..." & LF &
"-----------------------------------------------------------------------" & LF &
"-- **** ALTMEMPHY CALIBRATION has completed ****" & LF &
"-- Status:" & LF &
"-- calibration has : " & pass_or_fail_report(cal_success, cal_fail) & LF &
read_resync_report(codvw_phase, codvw_size, ctl_rlat, ctl_wlat, preset_cal_setup) &
ac_nt_report(ac_nt, dgrb_ctrl_ac_nt_good, preset_cal_setup) &
poa_rdv_adjust_report(poa_adjust, rdv_adjust, preset_cal_setup) &
disabled_stages(capabilities) &
"-----------------------------------------------------------------------";
end function;
begin
-- -------------------------------------------------------
-- calibration result reporting
-- -------------------------------------------------------
process(rst_n, clk)
variable v_reports_written : std_logic;
variable v_cal_request_r : std_logic;
variable v_rewrite_report : std_logic;
begin
if rst_n = '0' then
v_reports_written := '0';
v_cal_request_r := '0';
v_rewrite_report := '0';
elsif Rising_Edge(clk) then
if v_reports_written = '0' then
if ctl_init_success_int = '1' or ctl_init_fail_int = '1' then
v_reports_written := '1';
report calibration_report(c_capabilities,
ctl_init_success_int,
ctl_init_fail_int,
seq_ctl_rlat_int,
seq_ctl_wlat_int,
dgrb_mmi.cal_codvw_phase,
dgrb_mmi.cal_codvw_size,
int_ac_nt,
dgrb_ctrl_ac_nt_good,
c_preset_cal_setup,
poa_adjustments,
rdv_adjustments
) severity note;
end if;
end if;
-- if recalibrate request triggered watch for cal success / fail going low and re-trigger report writing
if ctl_recalibrate_req = '1' and v_cal_request_r = '0' then
v_rewrite_report := '1';
end if;
if v_rewrite_report = '1' and ctl_init_success_int = '0' and ctl_init_fail_int = '0' then
v_reports_written := '0';
v_rewrite_report := '0';
end if;
v_cal_request_r := ctl_recalibrate_req;
end if;
end process;
-- -------------------------------------------------------
-- capabilities vector reporting and coarse PHY setup sanity checks
-- -------------------------------------------------------
process(rst_n, clk)
variable reports_written : std_logic;
begin
if rst_n = '0' then
reports_written := '0';
elsif Rising_Edge(clk) then
if reports_written = '0' then
reports_written := '1';
if MEM_IF_MEMTYPE="DDR" or MEM_IF_MEMTYPE="DDR2" or MEM_IF_MEMTYPE="DDR3" then
if DWIDTH_RATIO = 2 or DWIDTH_RATIO = 4 then
report disabled_stages(c_capabilities) severity note;
else
report seq_report_prefix & "unsupported rate for non-levelling AFI PHY sequencer - only full- or half-rate supported" severity warning;
end if;
else
report seq_report_prefix & "memory type " & MEM_IF_MEMTYPE & " is not supported in non-levelling AFI PHY sequencer" severity failure;
end if;
end if;
end if;
end process;
end block; -- reporting
--synopsys synthesis_on
end architecture struct;
| apache-2.0 | e9b88276405be21a4a107f1fccd4e978 | 0.441486 | 4.428363 | false | false | false | false |
Nibble-Knowledge/cpu-vhdl | Nibble_Knowledge_CPU/alu_complete.vhd | 1 | 5,283 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:22:26 10/22/2015
-- Design Name:
-- Module Name: alu_complete - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu_complete is
Port ( exe : in STD_LOGIC;
OP_EN : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (3 downto 0);
WE : out STD_LOGIC;
JMP : out STD_LOGIC;
STR : out STD_LOGIC;
HLT : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
clk_fast : in std_logic;
rst : in STD_LOGIC);
end alu_complete;
architecture Behavioral of alu_complete is
--COMPONENTS
component four_bit_full_adder is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
msb_cin: out STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
component four_bit_nand is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
nnd : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Reg is
Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0);
data_out : out STD_LOGIC_VECTOR (3 downto 0);
enable : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC);
end component;
component alu_decode is
Port ( exe : in STD_LOGIC;
OP_EN : in STD_LOGIC;
clk : in STD_LOGIC;
clk_fast : in std_logic;
rst : in STD_LOGIC;
OP_Code : in STD_LOGIC_VECTOR(3 downto 0);
WE : out STD_LOGIC;
A_EN : out STD_LOGIC;
STAT_EN : out STD_LOGIC;
HLT : out STD_LOGIC;
JMP : out STD_LOGIC;
Arith_S : out STD_LOGIC;
Stat_S : out STD_LOGIC;
LOD_S : out STD_LOGIC;
STR : out STD_LOGIC);
end component;
--Decode
signal i_A_EN : STD_LOGIC;
signal i_STAT_EN : STD_LOGIC;
signal i_HLT : STD_LOGIC;
signal i_JMP : STD_LOGIC;
signal i_LOD_S : STD_LOGIC;
signal i_stat_S : STD_LOGIC;
signal i_arith_S : STD_LOGIC;
--STAT
signal i_XORb_in : STD_LOGIC;
signal i_XORb_new : STD_LOGIC;
signal i_XORb_old : STD_LOGIC;
signal i_carry_in : STD_LOGIC;
signal i_carry_new : STD_LOGIC;
signal i_carry_old : STD_LOGIC;
signal i_stat : STD_LOGIC_VECTOR(3 downto 0);
signal i_stat_in : STD_LOGIC_VECTOR(3 downto 0);
--Arithmetic
signal i_data_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_arith_result : STD_LOGIC_VECTOR(3 downto 0);
signal i_data_out : STD_LOGIC_VECTOR(3 downto 0);
signal i_NAND_result : STD_LOGIC_VECTOR(3 downto 0);
signal i_add_result : STD_LOGIC_VECTOR(3 downto 0);
signal i_arith_stat : STD_LOGIC_VECTOR(3 downto 0);
signal i_A_in : STD_LOGIC_VECTOR(3 downto 0);
signal i_MSB_cin : STD_LOGIC;
begin
ADDER: four_bit_full_adder
port map( x => i_data_out,
y => i_data_in,
cin => '0',
msb_cin => i_MSB_cin,
sum => i_add_result,
cout => i_carry_new
);
NANDER: four_bit_nand
port map( x => i_data_out,
y => i_data_in,
nnd => i_NAND_result
);
STAT: Reg
port map( data_in => i_stat_in,
data_out => i_stat,
enable => i_STAT_EN,
clk => clk,
rst => rst
);
A: Reg
port map( data_in => i_A_in,
data_out => i_data_out,
enable => i_A_EN,
clk => clk,
rst => rst
);
DECODER: alu_decode
port map( exe => exe,
OP_EN => OP_EN,
clk => clk,
clk_fast => clk_fast,
rst => rst,
OP_Code => i_data_in,
WE => WE,
A_EN => i_A_EN,
STAT_EN => i_STAT_EN,
HLT => i_HLT,
JMP => i_JMP,
Arith_S => i_arith_S,
Stat_S => i_stat_S,
LOD_S => i_LOD_S,
STR => STR
);
i_stat_in <= i_XORb_in & '0' & i_HLT & i_carry_in;
i_data_in <= data_in;
data_out <= i_data_out;
JMP <= i_JMP and (not (i_data_out(0) or i_data_out(1) or i_data_out(2) or i_data_out(3)));
i_XORb_new <= (i_carry_new XOR i_MSB_cin) XOR i_add_result(3);
i_XORb_old <= i_stat(3);
i_carry_old <= i_stat(0);
--Input to A (A_M0)
i_A_in <= i_data_in when (i_LOD_S = '1') else i_arith_stat;
--A_M1
i_arith_stat <= i_stat when (i_stat_S = '1') else i_arith_result;
--A_M4
i_arith_result <= i_NAND_result when (i_arith_S = '1') else i_add_result;
--A_M2 and A_M3
i_XORb_in <= i_XORb_old when (i_HLT = '1') else i_XORb_new;
i_carry_in <= i_carry_old when (i_HLT = '1') else i_carry_new;
--HALT
HLT <= i_HLT;
end Behavioral;
| unlicense | ca28b3c98ec11613e1ed4db2d4e9ea49 | 0.548173 | 2.964646 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9649_v1_00_a/hdl/vhdl/axi_ad9649.vhd | 1 | 11,005 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_ad9649 is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
adc_clk_in : in std_logic;
adc_data_in : in std_logic_vector(13 downto 0);
adc_or_in : in std_logic;
delay_clk : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(15 downto 0);
S_AXIS_S2MM_CLK : in std_logic;
S_AXIS_S2MM_TVALID : out std_logic;
S_AXIS_S2MM_TDATA : out std_logic_vector(63 downto 0);
S_AXIS_S2MM_TKEEP : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TLAST : out std_logic;
S_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_ad9649;
architecture IMP of axi_ad9649 is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
adc_clk_in : in std_logic;
adc_data_in : in std_logic_vector(13 downto 0);
adc_or_in : in std_logic;
dma_clk : in std_logic;
dma_valid : out std_logic;
dma_data : out std_logic_vector(63 downto 0);
dma_be : out std_logic_vector(7 downto 0);
dma_last : out std_logic;
dma_ready : in std_logic;
delay_clk : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(15 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_CF_BUFTYPE => C_CF_BUFTYPE
)
port map
(
adc_clk_in => adc_clk_in,
adc_data_in => adc_data_in,
adc_or_in => adc_or_in,
dma_clk => S_AXIS_S2MM_CLK,
dma_valid => S_AXIS_S2MM_TVALID,
dma_data => S_AXIS_S2MM_TDATA,
dma_be => S_AXIS_S2MM_TKEEP,
dma_last => S_AXIS_S2MM_TLAST,
dma_ready => S_AXIS_S2MM_TREADY,
delay_clk => delay_clk,
dma_dbg_data => dma_dbg_data,
dma_dbg_trigger => dma_dbg_trigger,
adc_clk => adc_clk,
adc_dbg_data => adc_dbg_data,
adc_dbg_trigger => adc_dbg_trigger,
adc_mon_valid => adc_mon_valid,
adc_mon_data => adc_mon_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 8ae3104c53e185d6a9b21c11fb34f0d9 | 0.547115 | 3.061196 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/noise/noise.vhd | 1 | 2,819 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - noise
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Basic component that generates noise (white, pink,...)
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity noise is
generic(
NOISE : NOISE_TYPE := WHITE
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
data : out signed(31 downto 0)
);
end noise;
architecture Behavioral of noise is
--------------------------------------------------------------------------------
-- Cordic related components and signals
--------------------------------------------------------------------------------
component PRBS -- white noise
Generic ( constant levels : integer := 16);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ce : in STD_LOGIC;
rand : out signed (levels - 1 downto 0));
end component PRBS;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
constant prbs_levels : integer := 32;
--------------------------------------------------------------------------------
-- FOO related components and signals
--------------------------------------------------------------------------------
begin
WHITE_NOISE : if NOISE = WHITE generate
PRBS_INSTA : PRBS
generic map ( levels => prbs_levels)
port map ( clk => clk,
rst => rst,
ce => ce,
rand => data);
end generate;
--------------------------------------------------------------------------------
end Behavioral;
| mit | e583f1531bd5a0742e0d62ea75f289e1 | 0.345867 | 5.125455 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Ext_Mem_Buffer.vhd | 1 | 4,603 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Ext_Mem_Buffer is
port(
Clk : in std_logic;
Rst : in std_logic;
enable : in std_logic;
pc_mux_input : in std_logic_vector(1 downto 0);
op_code_input: in std_logic_vector(4 downto 0);
mem_mux_input : in std_logic; --mickey mux
R1_regfile_input: in std_logic_vector(15 downto 0);
--ALU_address_input : in std_logic_vector(9 downto 0);
--stack_address_input : in std_logic_vector(9 downto 0);
--ALU_address_input,stack_address_input : in std_logic_vector(9 downto 0);
ALU_out_input : in std_logic_vector(15 downto 0);
Z_input: in std_logic;
NF_input: in std_logic;
V_input: in std_logic;
C_input: in std_logic;
outport_en_input : in std_logic;
reg_write_input : in std_logic;
mem_write_input : in std_logic;
write_data_reg_mux_input : in std_logic;
write_back_mux_input : in std_logic_vector(1 downto 0);
LDM_immediate_input : in std_logic_vector(15 downto 0);
load_store_address_input : in std_logic_vector(9 downto 0); --LDD
--------------------------------------------------------------------------------------------------------------------
pc_mux_output : out std_logic_vector(1 downto 0);
op_code_output: out std_logic_vector(4 downto 0);
mem_mux_output : out std_logic; --mickey mux
R1_regfile_output: out std_logic_vector(15 downto 0);
--ALU_address_output,stack_address_output : out std_logic_vector(9 downto 0);
ALU_out_output : out std_logic_vector(15 downto 0);
Z_output: out std_logic;
NF_output: out std_logic;
V_output: out std_logic;
C_output: out std_logic;
outport_en_output : out std_logic;
reg_write_output : out std_logic;
mem_write_output : out std_logic;
write_data_reg_mux_output : out std_logic;
write_back_mux_output: out std_logic_vector(1 downto 0);
LDM_immediate_output : out std_logic_vector(15 downto 0);
load_store_address_output : out std_logic_vector(9 downto 0);
Stack_WriteEnable_input1, StackPushPop_signal_input1 : in std_logic;
Stack_WriteEnable_output1, StackPushPop_output1 : out std_logic;
R1_address_in2,R2_address_in2: in std_logic_vector(2 downto 0 );
R1_address_out2,R2_address_out2: out std_logic_vector(2 downto 0 );
Rout_in1: out std_logic_vector(2 downto 0 );
Rout_out1: out std_logic_vector(2 downto 0 )
);
end Ext_Mem_Buffer;
architecture arch_Ext_Mem_Buffer of Ext_Mem_Buffer is
component Regis is
port(
Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component nreg is
Generic ( n : integer := 16);
port(
Clk,Rst,enable : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0)
);
end component;
begin
pc_mux_map : nreg generic map (n=>2)port map(Clk,Rst,enable,pc_mux_input,pc_mux_output);
op_code_map : nreg generic map (n=>5)port map(Clk,Rst,enable,op_code_input,op_code_output);
mem_mux_map : Regis port map(Clk,Rst,enable,mem_mux_input,mem_mux_output);
R1_regfile_map : nreg generic map (n=>16)port map(Clk,Rst,enable,R1_regfile_input,R1_regfile_output);
--ALU_address_map : nreg generic map (n=>10)port map(Clk,Rst,enable,ALU_address_input,ALU_address_output);
ALU_out_map : nreg generic map (n=>16)port map(Clk,Rst,enable,ALU_out_input,ALU_out_output);
Z_map : Regis port map(Clk,Rst,enable,Z_input,Z_output);
NF_map : Regis port map(Clk,Rst,enable,NF_input,NF_output);
V_map : Regis port map(Clk,Rst,enable,V_input,V_output);
C_map : Regis port map(Clk,Rst,enable,C_input,C_output);
outport_en_map : Regis port map(Clk,Rst,enable,outport_en_input,outport_en_output);
reg_write_map : Regis port map(Clk,Rst,enable,reg_write_input,reg_write_output);
mem_write_map : Regis port map(Clk,Rst,enable,mem_write_input,mem_write_output);
write_data_reg_mux_map : Regis port map(Clk,Rst,enable,write_data_reg_mux_input,write_data_reg_mux_output);
write_back_mux_map : nreg generic map (n=>16)port map(Clk,Rst,enable,write_back_mux_input,write_back_mux_output);
--LDM_immediate_output <= LDM_immediate_input;
LDM_immediate_map : nreg generic map (n=>16)port map(Clk,Rst,enable,LDM_immediate_input,LDM_immediate_output);
load_store_address_map : nreg generic map (n=>10)port map(Clk,Rst,enable,load_store_address_input,load_store_address_output);
end arch_Ext_Mem_Buffer;
| mit | bb8838c61ba3572475841349dc87ff61 | 0.651532 | 2.829133 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_2c_v1_00_a/hdl/vhdl/axi_adc_2c.vhd | 1 | 12,964 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_adc_2c is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0;
C_IODELAY_GROUP : string := "adc_if_delay_group"
);
port
(
pid : in std_logic_vector(7 downto 0);
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(13 downto 0);
adc_data_in_n : in std_logic_vector(13 downto 0);
adc_data_or_p : in std_logic;
adc_data_or_n : in std_logic;
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic;
delay_clk : in std_logic;
up_status : out std_logic_vector(7 downto 0);
up_adc_capture_int : out std_logic;
up_adc_capture_ext : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(31 downto 0);
S_AXIS_S2MM_CLK : in std_logic;
S_AXIS_S2MM_TVALID : out std_logic;
S_AXIS_S2MM_TDATA : out std_logic_vector(63 downto 0);
S_AXIS_S2MM_TKEEP : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TLAST : out std_logic;
S_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_adc_2c;
architecture IMP of axi_adc_2c is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0;
C_IODELAY_GROUP : string := "adc_if_delay_group"
);
port
(
pid : in std_logic_vector(7 downto 0);
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(13 downto 0);
adc_data_in_n : in std_logic_vector(13 downto 0);
adc_data_or_p : in std_logic;
adc_data_or_n : in std_logic;
spi_cs0n : out std_logic;
spi_cs1n : out std_logic;
spi_clk : out std_logic;
spi_sd_o : out std_logic;
spi_sd_i : in std_logic;
dma_clk : in std_logic;
dma_valid : out std_logic;
dma_data : out std_logic_vector(63 downto 0);
dma_be : out std_logic_vector(7 downto 0);
dma_last : out std_logic;
dma_ready : in std_logic;
delay_clk : in std_logic;
up_status : out std_logic_vector(7 downto 0);
up_adc_capture_int : out std_logic;
up_adc_capture_ext : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(31 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_CF_BUFTYPE => C_CF_BUFTYPE,
C_IODELAY_GROUP => C_IODELAY_GROUP
)
port map
(
pid => pid,
adc_clk_in_p => adc_clk_in_p,
adc_clk_in_n => adc_clk_in_n,
adc_data_in_p => adc_data_in_p,
adc_data_in_n => adc_data_in_n,
adc_data_or_p => adc_data_or_p,
adc_data_or_n => adc_data_or_n,
spi_cs0n => spi_cs0n,
spi_cs1n => spi_cs1n,
spi_clk => spi_clk,
spi_sd_o => spi_sdo,
spi_sd_i => spi_sdi,
dma_clk => S_AXIS_S2MM_CLK,
dma_valid => S_AXIS_S2MM_TVALID,
dma_data => S_AXIS_S2MM_TDATA,
dma_be => S_AXIS_S2MM_TKEEP,
dma_last => S_AXIS_S2MM_TLAST,
dma_ready => S_AXIS_S2MM_TREADY,
delay_clk => delay_clk,
up_status => up_status,
up_adc_capture_int => up_adc_capture_int,
up_adc_capture_ext => up_adc_capture_ext,
dma_dbg_data => dma_dbg_data,
dma_dbg_trigger => dma_dbg_trigger,
adc_clk => adc_clk,
adc_dbg_data => adc_dbg_data,
adc_dbg_trigger => adc_dbg_trigger,
adc_mon_valid => adc_mon_valid,
adc_mon_data => adc_mon_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 400b0a516c1a9c12917da1fd0a2de9b8 | 0.530546 | 3.080067 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_control_sub_v1_00_a/hdl/vhdl/hwt_control_sub.vhd | 1 | 14,029 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_control_sub
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for subtracting control units
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_control_sub is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_control_sub;
architecture Behavioral of hwt_control_sub is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component sub is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMaddr_sub : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_sub : std_logic_vector(0 to 31); -- sub to local ram
signal i_RAMData_sub : std_logic_vector(0 to 31); -- local ram to sub
signal o_RAMWE_sub : std_logic;
signal o_RAMaddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMaddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMaddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal sub_ce : std_logic; -- sub clock enable (like a start/stop signal)
signal refresh_state : integer;
signal process_state : integer;
signal input1 : std_logic_vector(31 downto 0);
signal input2 : std_logic_vector(31 downto 0);
signal input1_addr : std_logic_vector(31 downto 0);
signal input2_addr : std_logic_vector(31 downto 0);
signal sub_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant sub_START : std_logic_vector(31 downto 0) := x"0000000F";
constant sub_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_sub <= std_logic_vector(sub_data);
--sub_wave <= signed(i_RAMData_sub);
o_RAMaddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMaddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMaddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
sub_INST : sub
port map(
clk => clk,
rst => rst,
ce => sub_ce,
wave1 => signed(input1),
wave2 => signed(input2),
output => sub_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMaddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMaddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_sub = '1') then
local_ram(to_integer(unsigned(o_RAMaddr_sub))) := o_RAMData_sub;
else -- else needed, because sub is consuming samples
i_RAMData_sub <= local_ram(to_integer(unsigned(o_RAMaddr_sub)));
end if;
end if;
end process;
sub_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
sub_ce <= '0';
o_RAMWE_sub<= '0';
o_RAMaddr_sub <= (others => '0');
refresh_state <= 0;
process_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
input2_addr <= snd_comp_header.opt_arg_addr;
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = sub_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = sub_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, snd_comp_header.source_addr , input1, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, input2_addr , input2, done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= 0;
end case;
-- memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
-- if done then
-- refresh_state <= 0;
-- state <= STATE_PROCESS;
-- end if;
-- when others =>
-- refresh_state <= 0;
-- end case;
when STATE_PROCESS =>
--if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
sub_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_sub <= std_logic_vector(sub_data);
o_RAMWE_sub <= '1';
sub_ce <= '0';
process_state <= 2;
when 2 =>
o_RAMWE_sub <= '0';
-- o_RAMaddr_sub <= std_logic_vector(unsigned(o_RAMaddr_sub) + 1);
-- sample_count <= sample_count + 1;
process_state <= 3;
when 3 =>
--o_RAMaddr_sub <= (others => '0');
state <= STATE_WRITE_MEM;
when others =>
process_state <= 0;
end case;
-- else
-- -- Samples have been generated
-- o_RAMaddr_sub <= (others => '0');
-- sample_count <= to_unsigned(0, 16);
-- state <= STATE_WRITE_MEM;
-- end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | d76bfe29df287a5a77000d3ee6e2f26a | 0.470026 | 3.765164 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_16.vhd | 1 | 1,286 | -- File: gray_counter_16.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_16 is
port (
gray_count: out unsigned(15 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_16;
architecture MyHDL of gray_counter_16 is
signal even: std_logic;
signal gray: unsigned(15 downto 0);
begin
GRAY_COUNTER_16_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(15 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((16 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 16-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_16_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | 6b7dd8347a6285cf4e2ee49e17acf999 | 0.561431 | 3.402116 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Buffer.vhd | 1 | 382 | Library ieee;
Use ieee.std_logic_1164.all;
Entity Regis is
port( Clk,Rst,enable : in std_logic;
d : in std_logic;
q : out std_logic);
end Regis;
Architecture Regis_function of Regis is
begin
Process (Clk,Rst)
begin
if Rst = '1' then
q <= '0';
elsif clk'event and clk = '1' then
if (enable = '1') then
q <= d;
end if;
end if;
end process;
end Regis_function;
| mit | 9e3a6c2ef05d949fedde435936de75f0 | 0.646597 | 2.728571 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/soundgates_v1_00_a/hdl/vhdl/soundgates_reconos_pkg.vhd | 1 | 7,636 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
--
-- ======================================================================
--
-- title: VHDL Package - soundgates_reconos_pkg
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: ReconOS extension for the integration of sound components
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
package soundgates_reconos_pkg is
-- Constant declarations
constant MAX_HWT_ARGS : integer := 32;
constant DWORD_WIDTH : integer := 32;
constant ADDR_WIDTH : integer := 32;
-- Type declarations
type snd_comp_header_msg_t is record
base_addr : std_logic_vector(31 downto 0);
source_addr : std_logic_vector(C_FIFO_WIDTH - 1 downto 0); -- memory address of the data source buffer
src_len : std_logic_vector(C_FIFO_WIDTH - 1 downto 0); -- data length of the source buffer
dest_addr : std_logic_vector(C_FIFO_WIDTH - 1 downto 0); -- memory address destination buffer
opt_arg_addr : std_logic_vector(C_FIFO_WIDTH - 1 downto 0); -- memory address of optional arguments
opt_arg_len : std_logic_vector(C_FIFO_WIDTH - 1 downto 0); -- number of optional arguments
f_step : integer range 0 to 15;
end record;
type hwtargs_t is array (0 to MAX_HWT_ARGS - 1) of std_logic_vector(DWORD_WIDTH - 1 downto 0);
type hwtio_t is record
base_addr : std_logic_vector(DWORD_WIDTH - 1 downto 0);
f_step : integer range 0 to MAX_HWT_ARGS + 2;
argv : hwtargs_t;
end record;
------------------------------------------------------------
-- Functions and Procedure declarations
------------------------------------------------------------
------------------------------------------------------------
procedure snd_comp_get_header(
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
signal snd_comp_header : inout snd_comp_header_msg_t;
variable done : out boolean
);
procedure snd_comp_init_header ( signal snd_comp_header : out snd_comp_header_msg_t );
procedure hwtio_init( signal hwt_args : inout hwtio_t );
procedure get_hwt_args(
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
signal hwt_args : inout hwtio_t;
constant argc : in integer;
variable done : out boolean
);
-- Reverse a std_logic_vector (to <--> downto)
function reverse_vector (a: in std_logic_vector) return std_logic_vector;
------------------------------------------------------------
end soundgates_reconos_pkg;
package body soundgates_reconos_pkg is
function reverse_vector (a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'RANGE);
alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
begin
for i in aa'RANGE loop
result(i) := aa(i);
end loop;
return result;
end; -- function reverse_any_vector
procedure hwtio_init( signal hwt_args : inout hwtio_t ) is
begin
hwt_args.f_step <= 0;
hwt_args.base_addr <= (others => '0');
end procedure hwtio_init;
procedure get_hwt_args(
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
signal hwt_args : inout hwtio_t;
constant argc : in integer;
variable done : out boolean
) is
variable patially_done : boolean := False;
begin
case hwt_args.f_step is
when 0 =>
-- get header address
osif_get_init_data(i_osif, o_osif, hwt_args.base_addr, patially_done);
if (patially_done) then
hwt_args.f_step <= 1;
end if;
when 1 to (argc + 1) =>
memif_read_word(i_memif, o_memif,
std_logic_vector(unsigned(hwt_args.base_addr) + ((hwt_args.f_step-1) * 4)),
hwt_args.argv(hwt_args.f_step-1) , patially_done);
if (patially_done) then
hwt_args.f_step <= hwt_args.f_step + 1;
end if;
when others =>
done := True;
hwt_args.f_step <= 0;
end case;
end procedure get_hwt_args;
procedure snd_comp_init_header ( signal snd_comp_header : out snd_comp_header_msg_t ) is
begin
snd_comp_header.source_addr <= (others => '0');
snd_comp_header.src_len <= (others => '0');
snd_comp_header.dest_addr <= (others => '0');
snd_comp_header.opt_arg_addr <= (others => '0');
snd_comp_header.f_step <= 0;
end procedure snd_comp_init_header;
procedure snd_comp_get_header(
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
signal snd_comp_header : inout snd_comp_header_msg_t;
variable done : out boolean
) is
variable patially_done : boolean := False;
begin
case snd_comp_header.f_step is
when 0 =>
-- get header address
osif_get_init_data(i_osif, o_osif, snd_comp_header.base_addr, patially_done);
if(patially_done) then
snd_comp_header.f_step <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, snd_comp_header.base_addr, snd_comp_header.source_addr, patially_done);
if(patially_done) then
snd_comp_header.f_step <= 2;
end if;
when 2 =>
memif_read_word(i_memif, o_memif, std_logic_vector(unsigned(snd_comp_header.base_addr)+4), snd_comp_header.src_len, patially_done);
if(patially_done) then
snd_comp_header.f_step <= 3;
end if;
when 3 =>
memif_read_word(i_memif, o_memif, std_logic_vector(unsigned(snd_comp_header.base_addr)+8), snd_comp_header.dest_addr, patially_done);
if(patially_done) then
snd_comp_header.f_step <= 4;
end if;
when 4 =>
memif_read_word(i_memif, o_memif, std_logic_vector(unsigned(snd_comp_header.base_addr)+12), snd_comp_header.opt_arg_addr, patially_done);
if(patially_done) then
snd_comp_header.f_step <= 5;
end if;
when others =>
done := True;
snd_comp_header.f_step <= 0;
end case;
end procedure snd_comp_get_header;
end package body soundgates_reconos_pkg;
| mit | f7bb342141c93ab9e6508dcf15ee85bf | 0.496202 | 3.627553 | false | false | false | false |
aylons/sp601_spi_test | hdl/testbench/spi_test_top_tb.vhd | 1 | 3,133 | -------------------------------------------------------------------------------
-- Title : Testbench for design "spi_test_top"
-- Project :
-------------------------------------------------------------------------------
-- File : spi_test_top_tb.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-24
-- Last update: 2014-10-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-24 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity spi_test_top_tb is
end entity spi_test_top_tb;
-------------------------------------------------------------------------------
architecture test of spi_test_top_tb is
constant input_freq : real := 2.0e08;
constant clock_period : time := 1.0 sec /(input_freq);
constant c_width : positive := 16;
-- component ports
signal sys_clk_p_i : std_logic;
signal sys_clk_n_i : std_logic;
signal on_sw_i : std_logic;
signal rst_i : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
signal spi_miso : std_logic;
signal spi_ssel : std_logic;
signal nok_o : std_logic_vector(c_width-1 downto 0);
signal ok_o : std_logic_vector(c_width-1 downto 0);
component spi_test_top is
port (
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
on_sw_i : in std_logic;
rst_i : in std_logic;
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_ssel_o : out std_logic;
spi_sck_i : in std_logic;
spi_mosi_i : in std_logic;
spi_miso_o : out std_logic;
spi_ssel_i : in std_logic;
nok_o : out std_logic_vector(c_width-1 downto 0);
ok_o : out std_logic_vector(c_width-1 downto 0));
end component spi_test_top;
begin -- architecture test
clk_gen : process
begin
sys_clk_n_i <= '0';
sys_clk_p_i <= '1';
wait for clock_period/2.0;
sys_clk_n_i <= '1';
sys_clk_p_i <= '0';
wait for clock_period/2.0;
end process;
on_sw_i <= '1';
rst_i <= '0';
-- component instantiation
uut : spi_test_top
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
spi_sck_o => spi_sck,
spi_mosi_o => spi_mosi,
spi_miso_i => spi_miso,
spi_ssel_o => spi_ssel,
spi_sck_i => spi_sck,
spi_mosi_i => spi_mosi,
spi_miso_o => spi_miso,
spi_ssel_i => spi_ssel,
nok_o => nok_o,
ok_o => ok_o,
on_sw_i => on_sw_i,
rst_i => rst_i);
end architecture test;
| gpl-3.0 | c9622ab5c762cefd56ebda5a90b92280 | 0.44143 | 3.405435 | false | true | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/vhdl/axi_dac_4d_2c.vhd | 1 | 12,132 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_dac_4d_2c is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
pid : in std_logic_vector(7 downto 0);
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_p : out std_logic_vector(15 downto 0);
dac_data_out_n : out std_logic_vector(15 downto 0);
up_status : out std_logic_vector(7 downto 0);
up_dds_enable_int : out std_logic;
up_dds_frame_int : out std_logic;
up_dds_enable_ext : in std_logic;
up_dds_frame_ext : in std_logic;
vdma_dbg_data : out std_logic_vector(198 downto 0);
vdma_dbg_trigger : out std_logic_vector(7 downto 0);
dac_div3_clk : out std_logic;
dac_dbg_data : out std_logic_vector(195 downto 0);
dac_dbg_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
vdma_clk : in std_logic;
vdma_fs : out std_logic;
M_AXIS_MM2S_TVALID : in std_logic;
M_AXIS_MM2S_TKEEP : in std_logic_vector(7 downto 0);
M_AXIS_MM2S_TDATA : in std_logic_vector(63 downto 0);
M_AXIS_MM2S_TLAST : in std_logic;
M_AXIS_MM2S_TREADY : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_dac_4d_2c;
architecture IMP of axi_dac_4d_2c is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_CF_BUFTYPE : integer := 0
);
port
(
pid : in std_logic_vector(7 downto 0);
dac_clk_in_p : in std_logic;
dac_clk_in_n : in std_logic;
dac_clk_out_p : out std_logic;
dac_clk_out_n : out std_logic;
dac_frame_out_p : out std_logic;
dac_frame_out_n : out std_logic;
dac_data_out_p : out std_logic_vector(15 downto 0);
dac_data_out_n : out std_logic_vector(15 downto 0);
vdma_clk : in std_logic;
vdma_fs : out std_logic;
vdma_valid : in std_logic;
vdma_data : in std_logic_vector(63 downto 0);
vdma_ready : out std_logic;
up_status : out std_logic_vector(7 downto 0);
up_dds_enable_int : out std_logic;
up_dds_frame_int : out std_logic;
up_dds_enable_ext : in std_logic;
up_dds_frame_ext : in std_logic;
vdma_dbg_data : out std_logic_vector(198 downto 0);
vdma_dbg_trigger : out std_logic_vector(7 downto 0);
dac_div3_clk : out std_logic;
dac_dbg_data : out std_logic_vector(195 downto 0);
dac_dbg_trigger : out std_logic_vector(7 downto 0);
delay_clk : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_CF_BUFTYPE => C_CF_BUFTYPE
)
port map
(
pid => pid,
dac_clk_in_p => dac_clk_in_p,
dac_clk_in_n => dac_clk_in_n,
dac_clk_out_p => dac_clk_out_p,
dac_clk_out_n => dac_clk_out_n,
dac_frame_out_p => dac_frame_out_p,
dac_frame_out_n => dac_frame_out_n,
dac_data_out_p => dac_data_out_p,
dac_data_out_n => dac_data_out_n,
vdma_clk => vdma_clk,
vdma_fs => vdma_fs,
vdma_valid => M_AXIS_MM2S_TVALID,
vdma_data => M_AXIS_MM2S_TDATA,
vdma_ready => M_AXIS_MM2S_TREADY,
up_status => up_status,
up_dds_enable_int => up_dds_enable_int,
up_dds_frame_int => up_dds_frame_int,
up_dds_enable_ext => up_dds_enable_ext,
up_dds_frame_ext => up_dds_frame_ext,
vdma_dbg_data => vdma_dbg_data,
vdma_dbg_trigger => vdma_dbg_trigger,
dac_div3_clk => dac_div3_clk,
dac_dbg_data => dac_dbg_data,
dac_dbg_trigger => dac_dbg_trigger,
delay_clk => delay_clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 87f907de1fb4bfd6b242bf44b858bf39 | 0.549786 | 3 | false | false | false | false |
EPiCS/soundgates | hardware/basic/sub/sub.vhd | 1 | 1,464 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - sub.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: subtracts two samples
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity sub is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end sub;
architecture Behavioral of sub is
begin
adder : process (clk, rst, ce)
begin
if rising_edge(clk) then
if ce = '1' then
output <= wave1 - wave2;
end if;
end if;
end process;
end Behavioral;
| mit | 72d63e11c8c78a08d4a9b80d407530e1 | 0.346995 | 3.753846 | false | false | false | false |
aylons/sp601_spi_test | hdl/modules/simple_counter/simple_counter.vhd | 1 | 2,019 | -------------------------------------------------------------------------------
-- Title : Simple Counter for SPI test
-- Project :
-------------------------------------------------------------------------------
-- File : simple_counter.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-23
-- Last update: 2014-10-30
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simples counter possible
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-23 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity simple_counter is
generic (
g_width : natural := 16
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
data_o : out std_logic_vector(g_width-1 downto 0)
);
end entity simple_counter;
-------------------------------------------------------------------------------
architecture behavioural of simple_counter is
signal cur_value : unsigned(g_width-1 downto 0);
begin -- architecture str
count : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
cur_value <= (others => '0');
else
if ce_i = '1' then
cur_value <= cur_value+to_unsigned(1, g_width);
end if;
end if;
end if;
end process;
data_o <= std_logic_vector(cur_value);
end architecture behavioural;
-------------------------------------------------------------------------------
| gpl-3.0 | 2e1688f88d90ddd10ac792de10a3f313 | 0.392273 | 4.739437 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/arithmetic/arithmetic.vhd | 1 | 3,179 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - arithmetic.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: arithmetic component,
-- adds, subtracts or multiplies to samples
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity arithmetic is
generic(
ARITH : ARITHMETIC_TYPE := ADD
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave1 : in signed (31 downto 0);
wave2 : in signed (31 downto 0);
output : out signed (31 downto 0)
);
end arithmetic;
architecture Behavioral of arithmetic is
component signal_add
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component signal_add;
component signal_sub
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component signal_sub;
component signal_mul
port(
clk : in std_logic;
ce : in std_logic;
rst : in std_logic;
wave1 : in signed(31 downto 0);
wave2 : in signed(31 downto 0);
output : out signed(31 downto 0)
);
end component signal_mul;
begin
ADD_ARITHMETIC : if ARITH = ADD generate
S_ADD : signal_add
port map(
clk => clk,
rst => rst,
ce => ce,
wave1 => wave1,
wave2 => wave2,
output => output );
end generate;
SUB_ARITHMETIC : if ARITH = SUB generate
S_SUB : signal_sub
port map(
clk => clk,
rst => rst,
ce => ce,
wave1 => wave1,
wave2 => wave2,
output => output );
end generate;
MUL_ARITHMETIC : if ARITH = MUL generate
S_MUL : signal_mul
port map(
clk => clk,
rst => rst,
ce => ce,
wave1 => wave1,
wave2 => wave2,
output => output );
end generate;
end Behavioral;
| mit | 9b8759337f7e2e1cfcb562917afc38bd | 0.404844 | 3.853333 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/pck_myhdl_08.vhd | 1 | 3,359 | -- File: pck_myhdl_08.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:42 2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pck_myhdl_08 is
attribute enum_encoding: string;
function stdl (arg: boolean) return std_logic;
function stdl (arg: integer) return std_logic;
function to_unsigned (arg: boolean; size: natural) return unsigned;
function to_signed (arg: boolean; size: natural) return signed;
function to_integer(arg: boolean) return integer;
function to_integer(arg: std_logic) return integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned;
function to_signed (arg: std_logic; size: natural) return signed;
function bool (arg: std_logic) return boolean;
function bool (arg: unsigned) return boolean;
function bool (arg: signed) return boolean;
function bool (arg: integer) return boolean;
function "-" (arg: unsigned) return signed;
end pck_myhdl_08;
package body pck_myhdl_08 is
function stdl (arg: boolean) return std_logic is
begin
if arg then
return '1';
else
return '0';
end if;
end function stdl;
function stdl (arg: integer) return std_logic is
begin
if arg /= 0 then
return '1';
else
return '0';
end if;
end function stdl;
function to_unsigned (arg: boolean; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
if arg then
res(0):= '1';
end if;
return res;
end function to_unsigned;
function to_signed (arg: boolean; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
if arg then
res(0) := '1';
end if;
return res;
end function to_signed;
function to_integer(arg: boolean) return integer is
begin
if arg then
return 1;
else
return 0;
end if;
end function to_integer;
function to_integer(arg: std_logic) return integer is
begin
if arg = '1' then
return 1;
else
return 0;
end if;
end function to_integer;
function to_unsigned (arg: std_logic; size: natural) return unsigned is
variable res: unsigned(size-1 downto 0) := (others => '0');
begin
res(0):= arg;
return res;
end function to_unsigned;
function to_signed (arg: std_logic; size: natural) return signed is
variable res: signed(size-1 downto 0) := (others => '0');
begin
res(0) := arg;
return res;
end function to_signed;
function bool (arg: std_logic) return boolean is
begin
return arg = '1';
end function bool;
function bool (arg: unsigned) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: signed) return boolean is
begin
return arg /= 0;
end function bool;
function bool (arg: integer) return boolean is
begin
return arg /= 0;
end function bool;
function "-" (arg: unsigned) return signed is
begin
return - signed(resize(arg, arg'length+1));
end function "-";
end pck_myhdl_08;
| mit | ddafc159ee7cc2e9abaa24c0d7aafbca | 0.600774 | 4.017943 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_sawtooth_v1_00_a/hdl/vhdl/hwt_sawtooth.vhd | 1 | 13,365 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sawtooth
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for a sawtooth wave
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sawtooth is
generic(
SND_COMP_CLK_FREQ : integer := 100_000_000
);
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sawtooth;
architecture Behavioral of hwt_sawtooth is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component sawtooth is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
saw : out signed(31 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT_PHASE_OFFSET, STATE_REFRESH_INPUT_PHASE_INCR, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_saw : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_saw : std_logic_vector(0 to 31); -- saw to local ram
signal i_RAMData_saw : std_logic_vector(0 to 31); -- local ram to saw
signal o_RAMWE_saw : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(C_MAX_SAMPLE_COUNT, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal saw_ce : std_logic; -- saw clock enable (like a start/stop signal)
signal phase_offset_addr : std_logic_vector(31 downto 0);
signal phase_incr_addr : std_logic_vector(31 downto 0);
signal phase_offset : std_logic_vector(31 downto 0);
signal phase_incr : std_logic_vector(31 downto 0);
signal saw_data : signed(31 downto 0);
signal state_inner_process : std_logic;
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant saw_START : std_logic_vector(31 downto 0) := x"0000000F";
constant saw_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
o_RAMData_saw <= std_logic_vector(saw_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
saw_inst : sawtooth
port map(
clk => clk,
rst => rst,
ce => saw_ce,
incr => signed(phase_incr),
offset => signed(phase_offset),
saw => saw_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_saw = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_saw))) := o_RAMData_saw;
--else -- else not needed, because saw is not consuming any samples
-- i_RAMData_saw <= local_ram(conv_integer(unsigned(o_RAMAddr_saw)));
end if;
end if;
end process;
saw_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
osif_ctrl_signal <= (others => '0');
saw_ce <= '0';
o_RAMWE_saw <= '0';
state_inner_process <= '0';
done := False;
elsif rising_edge(clk) then
saw_ce <= '0';
o_RAMWE_saw <= '0';
osif_ctrl_signal <= ( others => '0');
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
-- Initialize your signals
phase_offset_addr <= snd_comp_header.opt_arg_addr;
phase_incr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = saw_START then
sample_count <= to_unsigned(C_MAX_SAMPLE_COUNT, 16);
state <= STATE_REFRESH_INPUT_PHASE_OFFSET;
elsif osif_ctrl_signal = saw_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT_PHASE_OFFSET =>
memif_read_word(i_memif, o_memif, phase_offset_addr, phase_offset, done);
if done then
state <= STATE_REFRESH_INPUT_PHASE_INCR;
end if;
when STATE_REFRESH_INPUT_PHASE_INCR =>
memif_read_word(i_memif, o_memif, phase_incr_addr, phase_incr, done);
if done then
state <= STATE_PROCESS;
end if;
when STATE_PROCESS =>
if sample_count > 0 then
case state_inner_process is
when '0' =>
o_RAMWE_saw <= '1';
saw_ce <= '1'; -- ein takt früher
state_inner_process <= '1';
when '1' =>
o_RAMAddr_saw <= std_logic_vector(unsigned(o_RAMAddr_saw) + 1);
sample_count <= sample_count - 1;
state_inner_process <= '0';
when others =>
state_inner_process <= '0';
end case;
else
-- Samples have been generated
o_RAMAddr_saw <= (others => '0');
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 0a632dc60e024a1bd073d12c0a18a064 | 0.487429 | 3.721526 | false | false | false | false |
EPiCS/soundgates | hardware/basic/white_noise/PRBS_tb.vhd | 1 | 1,125 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PRBS_tb IS
END PRBS_tb;
ARCHITECTURE behavior OF PRBS_tb IS
COMPONENT PRBS
PORT(
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
rand : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
--Outputs
signal rand : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PRBS PORT MAP (
clk => clk,
rst => rst,
ce => ce,
rand => rand
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | 449453affcf3552797715c7c4e1f75ac | 0.552 | 3.640777 | false | false | false | false |
spiersad/ECGR4146-FIFO | ROUTER.vhd | 1 | 6,265 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use work.pkg.all;
entity ROUTER is
generic (N: integer := 8; -- number of address bits for 2**N address locations
ADDSKEW: std_logic_vector(7 downto 0) := "00010000";
M: integer := 64); -- number of data bits to/from FIFO
port (CLK,RESET: in std_logic;
DIN: in DataInArray;
EXPUSH: in PushArray;
EXPOP: in PopArray;
DOUT: out DataOutArray);
end entity ROUTER;
architecture behav of router is
type state is (state0, state1, state2, state3,state4 ,state5 ,state6);
signal current_state, next_state : state := state0;
signal INPUSH: PushArray;
signal INPOP: PopArray;
signal NOPOP: NoPopArray;
signal h: std_logic_vector(N-1 downto 0);
signal WE, f,INIT: std_logic;
signal BUFF: BufferArray;
signal TMP: std_logic_vector(63 downto 0);
signal a, d: IOArray;
signal b, c: std_logic_vector(63 downto 0);
signal g: AddrArray;
signal e: WRArray;
signal IOSelect: std_logic_vector(1 downto 0);
signal AddrBit: std_logic;
component FIFO_LOGIC_MODIFIED is
generic (N: integer); -- number of address bits
port (CLK, PUSH, POP, INIT: in std_logic;
BUFF: out std_logic_vector(3 downto 0);
ADD: out std_logic_vector(N-1 downto 0);
FULL, EMPTY, WE, NOPUSH, NOPOP: out std_logic);
end component FIFO_LOGIC_MODIFIED;
component RAM is
generic (K, W: integer); -- number of address and data bits
port (WR: in std_logic; -- active high write enable
ADDR: in std_logic_vector (W-1 downto 0); -- RAM address
DIN: in std_logic_vector (K-1 downto 0); -- write data
DOUT: out std_logic_vector (K-1 downto 0)); -- read data
end component RAM;
begin
OUTFIFO_GEN:
for I in 3 downto 0 generate
OUTFIFO: FIFO_LOGIC_MODIFIED generic map (N => N)
port map(CLK => CLK, PUSH => INPUSH(I), POP => EXPOP(I), INIT => INIT,
ADD => g(I+4), BUFF => BUFF(I), WE => e(I+4), NOPOP => NOPOP(I));
end generate;
INFIFO_GEN:
for I in 3 downto 0 generate
INFIFO: FIFO_LOGIC_MODIFIED generic map (N => N)
port map(CLK => CLK, PUSH => EXPUSH(I), POP => INPOP(I), INIT => INIT,
ADD => g(I), WE => e(I));
end generate;
R: RAM generic map (W => N, K => M)
port map (DIN => b, ADDR => h, WR => f, DOUT => c);
b <= a(0) when (IOSelect = "00");
d(0) <= c when (IOSelect = "00");
b <= a(1) when (IOSelect = "01");
d(1) <= c when (IOSelect = "01");
b <= a(2) when (IOSelect = "10");
d(2) <= c when (IOSelect = "10");
b <= a(3) when (IOSelect = "11");
d(3) <= c when (IOSelect = "11");
f <= e(0) when (IOSelect = "00" and AddrBit = '0');
h <= g(0) + std_logic_vector(unsigned(ADDSKEW) * 0) when (IOSelect = "00" and AddrBit = '0');
f <= e(1) when (IOSelect = "01" and AddrBit = '0');
h <= g(1) + std_logic_vector(unsigned(ADDSKEW) * 1)when (IOSelect = "01" and AddrBit = '0');
f <= e(2) when (IOSelect = "10" and AddrBit = '0');
h <= g(2) + std_logic_vector(unsigned(ADDSKEW) * 2)when (IOSelect = "10" and AddrBit = '0');
f <= e(3) when (IOSelect = "11" and AddrBit = '0');
h <= g(3) + std_logic_vector(unsigned(ADDSKEW) * 3)when (IOSelect = "11" and AddrBit = '0');
f <= e(4) when (IOSelect = "00" and AddrBit = '1');
h <= g(4) + std_logic_vector(unsigned(ADDSKEW) * 4)when (IOSelect = "00" and AddrBit = '1');
f <= e(5) when (IOSelect = "01" and AddrBit = '1');
h <= g(5) + std_logic_vector(unsigned(ADDSKEW) * 5)when (IOSelect = "01" and AddrBit = '1');
f <= e(6) when (IOSelect = "10" and AddrBit = '1');
h <= g(6) + std_logic_vector(unsigned(ADDSKEW) * 6)when (IOSelect = "10" and AddrBit = '1');
f <= e(7) when (IOSelect = "11" and AddrBit = '1');
h <= g(7) + std_logic_vector(unsigned(ADDSKEW) * 7)when (IOSelect = "11" and AddrBit = '1');
process(Clk, Reset)
variable i : std_logic_vector(1 downto 0);
begin
if (RESET = '1') then
current_state <= state0;
i := "00";
INIT<= '1';
IOSelect <= "00";
AddrBit <= '0';
INPUSH <= (others => '0');
INPOP <= (others => '0');
else
if (Clk'event and Clk='1') then
case current_state is
when state0 =>
INPOP(to_integer(unsigned(i))) <= '1';
INPUSH <= (others => '0');
if(NOPOP(to_integer(unsigned(i))) = '1') then
next_state <= state1;
elsif((b(63 downto 48) >= (std_logic_vector(to_unsigned(0,64)))) and (b(63 downto 48) < (std_logic_vector(to_unsigned(21844,64))))) then
IOSelect <= "00";
AddrBit <= '1';
next_state <= state2;
elsif((b(63 downto 48) >= (std_logic_vector(to_unsigned(21845,64)))) and (b(63 downto 48) < (std_logic_vector(to_unsigned(43690,64))))) then
IOSelect <= "01";
AddrBit <= '1';
next_state <= state3;
elsif((b(63 downto 48) >= (std_logic_vector(to_unsigned(43691,64)))) and (b(63 downto 48) < (std_logic_vector(to_unsigned(65535,64))))) then
IOSelect <= "10";
AddrBit <= '1';
next_state <= state4;
--elsif()
end if;
when state1 =>
i := i + "01";
INPOP(to_integer(unsigned(i))) <= '0';
INPUSH(0) <= '1';
next_state <= state0;
AddrBit <= '0';
IOSelect <= i;
when state2 =>
i := i + "01";
INPOP(to_integer(unsigned(i))) <= '0';
INPUSH(1) <= '1';
next_state <= state0;
AddrBit <= '0';
IOSelect <= i;
when state3 =>
i := i + "01";
INPOP(to_integer(unsigned(i))) <= '0';
INPUSH(1) <= '1';
next_state <= state0;
AddrBit <= '0';
IOSelect <= i;
when others =>
next_state <= state0;
end case;
end if;
current_state <= next_state;
end if;
end process;
end behav; | gpl-2.0 | 5dafd0de16fd264dc16e861e211fd827 | 0.528492 | 3.2394 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_clkgen_v1_00_a/hdl/vhdl/axi_clkgen.vhd | 1 | 9,468 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_clkgen is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_MMCM_TYPE : integer := 0
);
port
(
ref_clk : in std_logic;
clk : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_clkgen;
architecture IMP of axi_clkgen is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_MMCM_TYPE : integer := 0
);
port
(
ref_clk : in std_logic;
clk : out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_MMCM_TYPE => C_MMCM_TYPE
)
port map
(
ref_clk => ref_clk,
clk => clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 32432c76702d30a543092ed45fc23d5a | 0.510034 | 3.311647 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_8c_v1_00_a/hdl/vhdl/axi_adc_8c.vhd | 1 | 11,345 | -- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_adc_8c is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(7 downto 0);
adc_data_in_n : in std_logic_vector(7 downto 0);
adc_frame_p : in std_logic;
adc_frame_n : in std_logic;
delay_clk : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(143 downto 0);
S_AXIS_S2MM_CLK : in std_logic;
S_AXIS_S2MM_TVALID : out std_logic;
S_AXIS_S2MM_TDATA : out std_logic_vector(63 downto 0);
S_AXIS_S2MM_TKEEP : out std_logic_vector(7 downto 0);
S_AXIS_S2MM_TLAST : out std_logic;
S_AXIS_S2MM_TREADY : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_adc_8c;
architecture IMP of axi_adc_8c is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
adc_clk_in_p : in std_logic;
adc_clk_in_n : in std_logic;
adc_data_in_p : in std_logic_vector(7 downto 0);
adc_data_in_n : in std_logic_vector(7 downto 0);
adc_frame_p : in std_logic;
adc_frame_n : in std_logic;
dma_clk : in std_logic;
dma_valid : out std_logic;
dma_data : out std_logic_vector(63 downto 0);
dma_be : out std_logic_vector(7 downto 0);
dma_last : out std_logic;
dma_ready : in std_logic;
delay_clk : in std_logic;
dma_dbg_data : out std_logic_vector(63 downto 0);
dma_dbg_trigger : out std_logic_vector(7 downto 0);
adc_dbg_data : out std_logic_vector(63 downto 0);
adc_dbg_trigger : out std_logic_vector(7 downto 0);
adc_clk : out std_logic;
adc_mon_valid : out std_logic;
adc_mon_data : out std_logic_vector(143 downto 0);
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
adc_clk_in_p => adc_clk_in_p,
adc_clk_in_n => adc_clk_in_n,
adc_data_in_p => adc_data_in_p,
adc_data_in_n => adc_data_in_n,
adc_frame_p => adc_frame_p,
adc_frame_n => adc_frame_n,
dma_clk => S_AXIS_S2MM_CLK,
dma_valid => S_AXIS_S2MM_TVALID,
dma_data => S_AXIS_S2MM_TDATA,
dma_be => S_AXIS_S2MM_TKEEP,
dma_last => S_AXIS_S2MM_TLAST,
dma_ready => S_AXIS_S2MM_TREADY,
delay_clk => delay_clk,
dma_dbg_data => dma_dbg_data,
dma_dbg_trigger => dma_dbg_trigger,
adc_dbg_data => adc_dbg_data,
adc_dbg_trigger => adc_dbg_trigger,
adc_clk => adc_clk,
adc_mon_valid => adc_mon_valid,
adc_mon_data => adc_mon_data,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 1b6f2380c566c4fb114cfb56a73843d4 | 0.544557 | 3.042371 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_spdif.vhd | 1 | 13,599 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver. Top level entity for the receiver core. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.5 2004/07/19 16:58:37 gedra
-- Fixed bug.
--
-- Revision 1.4 2004/07/12 17:06:41 gedra
-- Fixed bug with lock event generation.
--
-- Revision 1.3 2004/07/11 16:19:50 gedra
-- Bug-fix.
--
-- Revision 1.2 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.1 2004/06/26 14:13:56 gedra
-- Top level entity for receiver.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
use work.rx_package.all;
entity rx_spdif is
generic (DATA_WIDTH: integer range 16 to 32;
ADDR_WIDTH: integer range 8 to 64;
CH_ST_CAPTURE: integer range 0 to 8;
WISHBONE_FREQ: natural);
port (
-- Wishbone interface
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_sel_i: in std_logic;
wb_stb_i: in std_logic;
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_bte_i: in std_logic_vector(1 downto 0);
wb_cti_i: in std_logic_vector(2 downto 0);
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0);
wb_dat_i: in std_logic_vector(DATA_WIDTH -1 downto 0);
wb_ack_o: out std_logic;
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Interrupt line
rx_int_o: out std_logic;
-- SPDIF input signal
spdif_rx_i: in std_logic);
end rx_spdif;
architecture rtl of rx_spdif is
signal data_out, ver_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal ver_rd : std_logic;
signal conf_rxen, conf_sample, evt_en, conf_chas, conf_valid : std_logic;
signal conf_blken, conf_valen, conf_useren, conf_staten : std_logic;
signal conf_paren, config_rd, config_wr : std_logic;
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_bits, conf_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal status_rd : std_logic;
signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal imask_rd, imask_wr : std_logic;
signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal istat_rd, istat_wr, istat_lock : std_logic;
signal istat_lsbf, istat_hsbf, istat_paritya, istat_parityb: std_logic;
signal istat_cap : std_logic_vector(7 downto 0);
signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
signal cap_dout : bus_array;
signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
signal mem_rd, sample_wr : std_logic;
signal sample_din, sample_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal sbuf_wr_adr, sbuf_rd_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
signal lock, rx_frame_start: std_logic;
signal rx_data, rx_data_en, rx_block_start: std_logic;
signal rx_channel_a, rx_error, lock_evt: std_logic;
begin
-- Data bus or'ing
DB16: if DATA_WIDTH = 16 generate
data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout
when wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
end generate DB16;
DB32: if DATA_WIDTH = 32 generate
data_out <= ver_dout or conf_dout or stat_dout or imask_dout or istat_dout or
cap_dout(1) or cap_dout(2) or cap_dout(3) or cap_dout(4) or
cap_dout(5) or cap_dout(6) or cap_dout(7) or cap_dout(0) when
wb_adr_i(ADDR_WIDTH - 1) = '0' else sample_dout;
end generate DB32;
-- Wishbone bus cycle decoder
WB: rx_wb_decoder
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_cyc_i => wb_cyc_i,
wb_bte_i => wb_bte_i,
wb_cti_i => wb_cti_i,
wb_adr_i => wb_adr_i,
data_out => data_out,
wb_ack_o => wb_ack_o,
wb_dat_o => wb_dat_o,
version_rd => ver_rd,
config_rd => config_rd,
config_wr => config_wr,
status_rd => status_rd,
intmask_rd => imask_rd,
intmask_wr => imask_wr,
intstat_rd => istat_rd,
intstat_wr => istat_wr,
mem_rd => mem_rd,
mem_addr => sbuf_rd_adr,
ch_st_cap_rd => ch_st_cap_rd,
ch_st_cap_wr => ch_st_cap_wr,
ch_st_data_rd => ch_st_data_rd);
-- Version register
VER : rx_ver_reg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
CH_ST_CAPTURE => CH_ST_CAPTURE)
port map (
ver_rd => ver_rd,
ver_dout => ver_dout);
-- Configuration register
CG32: if DATA_WIDTH = 32 generate
CONF: gen_control_reg
generic map (
DATA_WIDTH => 32,
ACTIVE_BIT_MASK => "11111100000000001111111100000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => config_wr,
ctrl_rd => config_rd,
ctrl_din => wb_dat_i,
ctrl_dout => conf_dout,
ctrl_bits => conf_bits);
conf_mode(3 downto 0) <= conf_bits(23 downto 20);
conf_paren <= conf_bits(19);
conf_staten <= conf_bits(18);
conf_useren <= conf_bits(17);
conf_valen <= conf_bits(16);
end generate CG32;
CG16: if DATA_WIDTH = 16 generate
CONF: gen_control_reg
generic map (
DATA_WIDTH => 16,
ACTIVE_BIT_MASK => "1111110000000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => config_wr,
ctrl_rd => config_rd,
ctrl_din => wb_dat_i,
ctrl_dout => conf_dout,
ctrl_bits => conf_bits);
conf_mode(3 downto 0) <= "0000";
conf_paren <= '0';
conf_staten <= '0';
conf_useren <= '0';
conf_valen <= '0';
end generate CG16;
conf_blken <= conf_bits(5);
conf_valid <= conf_bits(4);
conf_chas <= conf_bits(3);
evt_en <= conf_bits(2);
conf_sample <= conf_bits(1);
conf_rxen <= conf_bits(0);
-- status register
STAT : rx_status_reg
generic map (
DATA_WIDTH => DATA_WIDTH)
port map (
wb_clk_i => wb_clk_i,
status_rd => status_rd,
lock => lock,
chas => conf_chas,
rx_block_start => rx_block_start,
ch_data => rx_data,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en,
status_dout => stat_dout);
-- interrupt mask register
IM32: if DATA_WIDTH = 32 generate
IMASK: gen_control_reg
generic map (
DATA_WIDTH => 32,
ACTIVE_BIT_MASK => "11111000000000001111111100000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => imask_wr,
ctrl_rd => imask_rd,
ctrl_din => wb_dat_i,
ctrl_dout => imask_dout,
ctrl_bits => imask_bits);
end generate IM32;
IM16: if DATA_WIDTH = 16 generate
IMASK: gen_control_reg
generic map (
DATA_WIDTH => 16,
ACTIVE_BIT_MASK => "1111100000000000")
port map (
clk => wb_clk_i,
rst => wb_rst_i,
ctrl_wr => imask_wr,
ctrl_rd => imask_rd,
ctrl_din => wb_dat_i,
ctrl_dout => imask_dout,
ctrl_bits => imask_bits);
end generate IM16;
-- interrupt status register
ISTAT: gen_event_reg
generic map (
DATA_WIDTH => DATA_WIDTH)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
evt_wr => istat_wr,
evt_rd => istat_rd,
evt_din => wb_dat_i,
evt_dout => istat_dout,
event => istat_events,
evt_mask => imask_bits,
evt_en => evt_en,
evt_irq => rx_int_o);
istat_events(0) <= lock_evt;
istat_events(1) <= istat_lsbf;
istat_events(2) <= istat_hsbf;
istat_events(3) <= istat_paritya;
istat_events(4) <= istat_parityb;
istat_events(15 downto 5) <= (others => '0');
IS32: if DATA_WIDTH = 32 generate
istat_events(23 downto 16) <= istat_cap(7 downto 0);
istat_events(31 downto 24) <= (others => '0');
end generate IS32;
-- capture registers
GCAP: if DATA_WIDTH = 32 and CH_ST_CAPTURE > 0 generate
CAPR: for k in 0 to CH_ST_CAPTURE - 1 generate
CHST: rx_cap_reg
port map (
clk => wb_clk_i,
rst => wb_rst_i,
cap_ctrl_wr => ch_st_cap_wr(k),
cap_ctrl_rd => ch_st_cap_rd(k),
cap_data_rd => ch_st_data_rd(k),
cap_din => wb_dat_i,
cap_dout => cap_dout(k),
cap_evt => istat_cap(k),
rx_block_start => rx_block_start,
ch_data => rx_data,
ud_a_en => ud_a_en,
ud_b_en => ud_b_en,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en);
end generate CAPR;
-- unused capture registers set to zero
UCAPR: if CH_ST_CAPTURE < 8 generate
UC: for k in CH_ST_CAPTURE to 7 generate
cap_dout(k) <= (others => '0');
end generate UC;
end generate UCAPR;
end generate GCAP;
-- Sample buffer memory
MEM: dpram
generic map (
DATA_WIDTH => DATA_WIDTH,
RAM_WIDTH => ADDR_WIDTH - 1)
port map (
clk => wb_clk_i,
rst => wb_rst_i,
din => sample_din,
wr_en => sample_wr,
rd_en => mem_rd,
wr_addr => sbuf_wr_adr,
rd_addr => sbuf_rd_adr,
dout => sample_dout);
-- phase decoder
PDET: rx_phase_det
generic map (
WISHBONE_FREQ => WISHBONE_FREQ) -- WishBone frequency in MHz
port map (
wb_clk_i => wb_clk_i,
rxen => conf_rxen,
spdif => spdif_rx_i,
lock => lock,
lock_evt => lock_evt,
rx_data => rx_data,
rx_data_en => rx_data_en,
rx_block_start => rx_block_start,
rx_frame_start => rx_frame_start,
rx_channel_a => rx_channel_a,
rx_error => rx_error,
ud_a_en => ud_a_en,
ud_b_en => ud_b_en,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en);
-- frame decoder
FDEC: rx_decode
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH)
port map (
wb_clk_i => wb_clk_i,
conf_rxen => conf_rxen,
conf_sample => conf_sample,
conf_valid => conf_valid,
conf_mode => conf_mode,
conf_blken => conf_blken,
conf_valen => conf_valen,
conf_useren => conf_useren,
conf_staten => conf_staten,
conf_paren => conf_paren,
lock => lock,
rx_data => rx_data,
rx_data_en => rx_data_en,
rx_block_start => rx_block_start,
rx_frame_start => rx_frame_start,
rx_channel_a => rx_channel_a,
wr_en => sample_wr,
wr_addr => sbuf_wr_adr,
wr_data => sample_din,
stat_paritya => istat_paritya,
stat_parityb => istat_parityb,
stat_lsbf => istat_lsbf,
stat_hsbf => istat_hsbf);
end rtl;
| mit | 0ffdcef4c811ab845dd4c5ba50ebef2e | 0.510993 | 3.450647 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/reconos_v3_00_c/hdl/vhdl/reconos_pkg.vhd | 1 | 41,584 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: VHDL Package - ReconOS
--
-- project: ReconOS
-- author: Enno Lübbers, University of Paderborn
-- Andreas Agne, University of Paderborn
-- Christoph Rüthing, University of Paderborn
-- description: The entire ReconOS package with type definitions and
-- hardware OS services in VHDL
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
package reconos_pkg is
constant C_FIFO_WIDTH : integer := 32;
constant C_OSIF_WIDTH : integer := C_FIFO_WIDTH;
constant C_MEMIF_WIDTH : integer := C_FIFO_WIDTH;
-- any request will be split up in multiple requests of size C_CHUNK_SIZE (in words)
constant C_CHUNK_SIZE : integer := 64;
constant C_CHUNK_SIZE_BYTES : integer := C_CHUNK_SIZE * 4;
constant C_MEMIF_LENGTH_WIDTH : integer := 24;
constant C_MEMIF_CMD_WIDTH : integer := C_MEMIF_WIDTH - C_MEMIF_LENGTH_WIDTH;
-- common constants
constant C_RECONOS_FAILURE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"00000000";
constant C_RECONOS_SUCCESS : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"00000001";
-- commands
constant OSIF_CMD_THREAD_GET_INIT_DATA : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A0";
constant OSIF_CMD_THREAD_DELAY : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A1"; -- ToDo
constant OSIF_CMD_THREAD_EXIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A2";
constant OSIF_CMD_THREAD_YIELD : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A3"; -- ToDo
constant OSIF_CMD_THREAD_RESUME : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A4"; -- ToDo
constant OSIF_CMD_THREAD_LOAD_STATE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A5"; -- ToDo
constant OSIF_CMD_THREAD_STORE_STATE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000A6"; -- ToDo
constant OSIF_CMD_SEM_POST : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000B0";
constant OSIF_CMD_SEM_WAIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000B1";
constant OSIF_CMD_MUTEX_LOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C0";
constant OSIF_CMD_MUTEX_UNLOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C1";
constant OSIF_CMD_MUTEX_TRYLOCK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000C2"; -- Not tested, yet
constant OSIF_CMD_COND_WAIT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D0"; -- Not tested, yet
constant OSIF_CMD_COND_SIGNAL : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D1"; -- Not tested, yet
constant OSIF_CMD_COND_BROADCAST : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000D2"; -- Not tested, yet
constant OSIF_CMD_RQ_RECEIVE : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000E0"; -- ToDo
constant OSIF_CMD_RQ_SEND : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000E1"; -- ToDo
constant OSIF_CMD_MBOX_GET : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F0";
constant OSIF_CMD_MBOX_PUT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F1";
constant OSIF_CMD_MBOX_TRYGET : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F2"; -- ToDo
constant OSIF_CMD_MBOX_TRYPUT : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"000000F3"; -- ToDo
constant OSIF_CMD_YIELD_MASK : std_logic_vector(C_OSIF_WIDTH - 1 downto 0) := X"80000000";
constant MEMIF_CMD_READ : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0) := X"00";
constant MEMIF_CMD_WRITE : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0) := X"F0";
-- type definitions for easier handling of signals
type i_fifo_t is record
s_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
s_fill : std_logic_vector(15 downto 0);
s_empty : std_logic;
m_rem : std_logic_vector(15 downto 0);
m_full : std_logic;
s_re : std_logic;
m_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
type o_fifo_t is record
s_re : std_logic;
m_data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
m_we : std_logic;
step : integer range 0 to 15;
void : std_logic;
end record;
alias i_osif_t is i_fifo_t;
alias o_osif_t is o_fifo_t;
alias i_memif_t is i_fifo_t;
alias o_memif_t is o_fifo_t;
type i_ram_t is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
remote_addr : std_logic_vector(31 downto 0);
remainder : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
step : integer range 0 to 15;
end record;
type o_ram_t is record
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
we : std_logic;
count : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
remote_addr : std_logic_vector(31 downto 0);
remainder : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
step : integer range 0 to 15;
end record;
-- setup functions
procedure fifo_setup (
signal i_fifo : out i_fifo_t;
signal o_fifo : in o_fifo_t;
signal s_data : in std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : in std_logic_vector(15 downto 0);
signal s_empty : in std_logic;
signal m_rem : in std_logic_vector(15 downto 0);
signal m_full : in std_logic;
signal s_re : out std_logic;
signal m_data : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_we : out std_logic
);
procedure fifo_reset (
signal o_fifo : out o_fifo_t
);
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal sw2hw_fill : in std_logic_vector(15 downto 0);
signal sw2hw_empty : in std_logic;
signal hw2sw_rem : in std_logic_vector(15 downto 0);
signal hw2sw_full : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal hw2sw_we : out std_logic
);
procedure osif_reset (
signal o_osif : out o_osif_t
);
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal mem2hwt_fill : in std_logic_vector(15 downto 0);
signal mem2hwt_empty : in std_logic;
signal hwt2mem_rem : in std_logic_vector(15 downto 0);
signal hwt2mem_full : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal hwt2mem_we : out std_logic
);
procedure memif_reset (
signal o_memif : out o_memif_t
);
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal addr : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal we : out std_logic;
signal o_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal i_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0)
);
procedure ram_reset (
signal o_ram : out o_ram_t
);
-- fifo access functions
procedure fifo_default (
signal o_fifo : out o_fifo_t
);
procedure fifo_pull_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal result : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer;
continue : boolean
);
procedure fifo_push_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer
);
procedure fifo_pull (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
);
procedure fifo_push (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
);
-- functions to access osif directly
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- generic osif functions
procedure osif_call_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_call_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_call_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
-- osif functions
procedure osif_set_yield (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_rq_receive (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_rq_send (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
);
-- memif functions
procedure memif_flush (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
variable done : out boolean
);
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
variable done : out boolean
);
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(31 downto 0);
variable done : out boolean
);
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
);
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
);
end package reconos_pkg;
package body reconos_pkg is
procedure fifo_setup (
signal i_fifo : out i_fifo_t;
signal o_fifo : in o_fifo_t;
signal s_data : in std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal s_fill : in std_logic_vector(15 downto 0);
signal s_empty : in std_logic;
signal m_rem : in std_logic_vector(15 downto 0);
signal m_full : in std_logic;
signal s_re : out std_logic;
signal m_data : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
signal m_we : out std_logic
) is begin
i_fifo.step <= o_fifo.step;
i_fifo.s_data <= s_data;
i_fifo.s_fill <= s_fill;
i_fifo.s_empty <= s_empty;
i_fifo.m_rem <= m_rem;
i_fifo.m_full <= m_full;
s_re <= o_fifo.s_re;
m_data <= o_fifo.m_data;
m_we <= o_fifo.m_we;
i_fifo.s_re <= o_fifo.s_re;
i_fifo.m_we <= o_fifo.m_we;
i_fifo.void <= o_fifo.void;
end procedure fifo_setup;
procedure fifo_reset (
signal o_fifo : out o_fifo_t
) is begin
o_fifo.step <= 0;
o_fifo.m_we <= '0';
o_fifo.s_re <= '0';
o_fifo.m_data <= (others => '0');
o_fifo.void <= '0';
end procedure fifo_reset;
procedure osif_setup (
signal i_osif : out i_osif_t;
signal o_osif : in o_osif_t;
signal sw2hw_data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal sw2hw_fill : in std_logic_vector(15 downto 0);
signal sw2hw_empty : in std_logic;
signal hw2sw_rem : in std_logic_vector(15 downto 0);
signal hw2sw_full : in std_logic;
signal sw2hw_re : out std_logic;
signal hw2sw_data : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal hw2sw_we : out std_logic
) is begin
fifo_setup(i_osif, o_osif, sw2hw_data, sw2hw_fill, sw2hw_empty,
hw2sw_rem, hw2sw_full, sw2hw_re, hw2sw_data, hw2sw_we);
end procedure osif_setup;
procedure osif_reset (
signal o_osif : out o_osif_t
) is begin
fifo_reset(o_osif);
end procedure osif_reset;
procedure memif_setup (
signal i_memif : out i_memif_t;
signal o_memif : in o_memif_t;
signal mem2hwt_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal mem2hwt_fill : in std_logic_vector(15 downto 0);
signal mem2hwt_empty : in std_logic;
signal hwt2mem_rem : in std_logic_vector(15 downto 0);
signal hwt2mem_full : in std_logic;
signal mem2hwt_re : out std_logic;
signal hwt2mem_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal hwt2mem_we : out std_logic
) is begin
fifo_setup(i_memif, o_memif, mem2hwt_data, mem2hwt_fill, mem2hwt_empty,
hwt2mem_rem, hwt2mem_full, mem2hwt_re, hwt2mem_data, hwt2mem_we);
end procedure memif_setup;
procedure memif_reset (
signal o_memif : out o_memif_t
) is begin
fifo_reset(o_memif);
end procedure memif_reset;
procedure ram_setup (
signal i_ram : out i_ram_t;
signal o_ram : in o_ram_t;
signal addr : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal we : out std_logic;
signal o_data : out std_logic_vector(C_MEMIF_WIDTH - 1 downto 0);
signal i_data : in std_logic_vector(C_MEMIF_WIDTH - 1 downto 0)
) is begin
i_ram.data <= i_data;
addr <= o_ram.addr;
we <= o_ram.we;
o_data <= o_ram.data;
i_ram.addr <= o_ram.addr;
i_ram.count <= o_ram.count;
i_ram.step <= o_ram.step;
i_ram.remote_addr <= o_ram.remote_addr;
i_ram.remainder <= o_ram.remainder;
end procedure ram_setup;
procedure ram_reset (
signal o_ram : out o_ram_t
) is begin
o_ram.we <= '0';
o_ram.addr <= (others => '0');
o_ram.data <= (others => '0');
o_ram.count <= (others => '0');
o_ram.step <= 0;
o_ram.remote_addr <= (others => '0');
o_ram.remainder <= (others => '0');
end procedure ram_reset;
-- fifo access functions
procedure fifo_default (
signal o_fifo : out o_fifo_t
) is begin
o_fifo.s_re <= '0';
o_fifo.m_we <= '0';
end procedure fifo_default;
procedure fifo_pull_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal result : out std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer;
continue : boolean
) is begin
-- set re, if FIFO is empty this is no problem
--if i_fifo.s_empty = '0' then
o_fifo.s_re <= '1';
--end if;
-- read data one clock cycle after setting the re
-- and only if FIFO not empty
if i_fifo.s_empty = '0' and i_fifo.s_re = '1' then
result <= i_fifo.s_data;
o_fifo.step <= next_step;
-- stop reading if continue is false (last read)
if not continue then
o_fifo.s_re <= '0';
end if;
end if;
end procedure fifo_pull_word;
procedure fifo_push_word (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
data : std_logic_vector(C_FIFO_WIDTH - 1 downto 0);
next_step : integer
) is begin
o_fifo.m_data <= data;
if i_fifo.m_full = '0'
and (i_fifo.m_we = '0' or or_reduce(i_fifo.m_rem) = '1') then
-- write data into FIFO if
-- FIFO is not full
-- and no previous write or more than one word free
o_fifo.m_we <= '1';
o_fifo.step <= next_step;
end if;
end procedure fifo_push_word;
procedure fifo_pull (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
) is begin
case i_ram.step is
when 0 =>
-- because of the FIFO implementation used
-- we can keep the RE high and check the empty flag
o_fifo.s_re <= '1';
-- set address one word before actual address
--o_ram.addr <= i_ram.addr - 1;
o_ram.step <= 1;
o_ram.count <= (others => '0');
when 1 =>
o_fifo.s_re <= '1';
if i_fifo.s_empty = '0' then
o_ram.we <= '1';
o_ram.data <= i_fifo.s_data;
if or_reduce(i_ram.count) = '0' then
o_ram.addr <= i_ram.addr;
else
o_ram.addr <= i_ram.addr + 1;
end if;
o_ram.count <= i_ram.count + 1;
if i_ram.count = count - 1 then
o_ram.step <= 2;
end if;
end if;
when others =>
o_ram.we <= '0';
o_ram.step <= 0;
o_fifo.step <= next_step;
end case;
end procedure fifo_pull;
procedure fifo_push (
signal i_fifo : in i_fifo_t;
signal o_fifo : out o_fifo_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
count : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 3 downto 0);
next_step : integer
) is begin
case i_ram.step is
when 0 =>
-- waiting for FIFO to become empty enough
-- this is not so nice, but should be now major drawback
-- since the FIFOs are empty most of the time
if i_fifo.m_full = '0' and i_fifo.m_rem >= count - 1 then
o_ram.count <= (others => '0');
o_ram.addr <= i_ram.addr + 1;
o_ram.step <= 1;
end if;
when 1 =>
o_fifo.m_we <= '1';
o_fifo.m_data <= i_ram.data;
o_ram.addr <= i_ram.addr + 1;
o_ram.count <= i_ram.count + 1;
if i_ram.count = count - 1 then
o_ram.step <= 2;
end if;
when others =>
o_ram.addr <= i_ram.addr - 2;
o_fifo.m_we <= '0';
o_ram.step <= 0;
o_fifo.step <= next_step;
end case;
end procedure fifo_push;
procedure osif_read (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
fifo_pull_word(i_osif, o_osif, result, 1, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_read;
procedure osif_write (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
data : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
fifo_push_word(i_osif, o_osif, data, 1);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_write;
procedure osif_call_0 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
fifo_pull_word(i_osif, o_osif, result, 3, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_0;
procedure osif_call_1 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
fifo_pull_word(i_osif, o_osif, result, 4, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_1;
procedure osif_call_1_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
fifo_pull_word(i_osif, o_osif, result1, 4, True);
when 4 =>
fifo_pull_word(i_osif, o_osif, result2, 5, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_1_2;
procedure osif_call_2 (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
call_id : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg0 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
arg1 : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- wait for yield bit
o_osif.step <= 1;
when 1 =>
-- push call_id into FIFO
if i_osif.void = '1' then
fifo_push_word(i_osif, o_osif, call_id or OSIF_CMD_YIELD_MASK, 2);
else
fifo_push_word(i_osif, o_osif, call_id, 2);
end if;
when 2 =>
-- push arg0 into FIFO
fifo_push_word(i_osif, o_osif, arg0, 3);
when 3 =>
-- push arg1 into FIFO
fifo_push_word(i_osif, o_osif, arg1, 4);
when 4 =>
fifo_pull_word(i_osif, o_osif, result, 5, False);
when others =>
done := True;
o_osif.void <= '0';
o_osif.step <= 0;
end case;
end procedure osif_call_2;
-- osif functions
procedure osif_set_yield (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
o_osif.void <= '1';
end procedure osif_set_yield;
procedure osif_sem_post (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_SEM_POST, handle, result, done);
end procedure osif_sem_post;
procedure osif_sem_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_SEM_WAIT, handle, result, done);
end procedure osif_sem_wait;
procedure osif_mutex_lock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_LOCK, handle, result, done);
end procedure osif_mutex_lock;
procedure osif_mutex_unlock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_UNLOCK, handle, result, done);
end procedure osif_mutex_unlock;
procedure osif_mutex_trylock (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MUTEX_TRYLOCK, handle, result, done);
end procedure osif_mutex_trylock;
procedure osif_cond_wait (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
cond_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
mutex_handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_COND_WAIT, cond_handle, mutex_handle, result, done);
end procedure osif_cond_wait;
procedure osif_cond_signal (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_COND_SIGNAL, handle, result, done);
end procedure osif_cond_signal;
procedure osif_cond_broadcast (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_COND_BROADCAST, handle, result, done);
end procedure osif_cond_broadcast;
procedure osif_mbox_put (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_MBOX_PUT, handle, word, result, done);
end procedure osif_mbox_put;
procedure osif_mbox_get (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1(i_osif, o_osif, OSIF_CMD_MBOX_GET, handle, result, done);
end procedure osif_mbox_get;
procedure osif_mbox_tryput (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
word : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYPUT, handle, word, result, done);
end procedure osif_mbox_tryput;
procedure osif_mbox_tryget (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result1 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
signal result2 : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_1_2(i_osif, o_osif, OSIF_CMD_MBOX_TRYGET, handle, result1, result2, done);
end procedure osif_mbox_tryget;
procedure osif_rq_receive (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- not implemented yet
end procedure osif_rq_receive;
procedure osif_rq_send (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
handle : in std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
size : in std_logic_vector(31 downto 0);
addr : in std_logic_vector(31 downto 0);
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- not implemented yet
end procedure osif_rq_send;
procedure osif_get_init_data (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t;
signal result : out std_logic_vector(C_OSIF_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
osif_call_0(i_osif, o_osif, OSIF_CMD_THREAD_GET_INIT_DATA, result, done);
end procedure osif_get_init_data;
procedure osif_thread_exit (
signal i_osif : in i_osif_t;
signal o_osif : out o_osif_t
) is begin
fifo_default(o_osif);
case i_osif.step is
when 0 =>
-- push THREAD_EXIT
fifo_push_word(i_osif, o_osif, OSIF_CMD_THREAD_EXIT, 1);
when others =>
-- never return from this loop
o_osif.step <= 2;
end case;
end procedure osif_thread_exit;
--memif functions
procedure memif_flush (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
variable done : out boolean
) is begin
done := False;
if i_memif.m_rem = X"007F" and i_memif.m_full = '0' then
done := True;
end if;
end procedure memif_flush;
procedure memif_write_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & X"000004", 1);
when 1 =>
fifo_push_word(i_memif, o_memif, addr, 2);
when 2 =>
fifo_push_word(i_memif, o_memif, data, 3);
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write_word;
procedure memif_read_word (
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
addr : in std_logic_vector(31 downto 0);
signal data : out std_logic_vector(31 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & X"000004", 1);
when 1 =>
fifo_push_word(i_memif, o_memif, addr, 2);
when 2 =>
fifo_pull_word(i_memif, o_memif, data, 3, False);
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read_word;
procedure memif_write (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
o_ram.addr <= src_addr;
o_ram.remainder <= len(C_MEMIF_LENGTH_WIDTH - 1 downto 2);
o_ram.remote_addr <= dst_addr;
o_memif.step <= 1;
when 1 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE_BYTES, C_MEMIF_LENGTH_WIDTH), 2);
else
fifo_push_word(i_memif, o_memif, MEMIF_CMD_WRITE & i_ram.remainder & "00", 2);
end if;
when 2 =>
fifo_push_word(i_memif, o_memif, i_ram.remote_addr, 3);
when 3 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push(i_memif, o_memif, i_ram, o_ram, CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE, C_MEMIF_LENGTH_WIDTH - 2), 4);
else
fifo_push(i_memif, o_memif, i_ram, o_ram, i_ram.remainder, 4);
end if;
when 4 =>
if i_ram.remainder > C_CHUNK_SIZE then
-- o_ram.addr is incremented by fifo_push
o_ram.remainder <= i_ram.remainder - C_CHUNK_SIZE;
o_ram.remote_addr <= i_ram.remote_addr + C_CHUNK_SIZE_BYTES;
o_ram.addr <= i_ram.addr + 1;
o_memif.step <= 1;
else
o_memif.step <= 5;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_write;
procedure memif_read (
signal i_ram : in i_ram_t;
signal o_ram : out o_ram_t;
signal i_memif : in i_memif_t;
signal o_memif : out o_memif_t;
src_addr : in std_logic_vector(31 downto 0);
dst_addr : in std_logic_vector(31 downto 0);
len : in std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
variable done : out boolean
) is begin
-- set done to false, so the user does not have to care about it
done := False;
fifo_default(o_memif);
case i_memif.step is
when 0 =>
o_ram.addr <= dst_addr;
o_ram.remainder <= len(C_MEMIF_LENGTH_WIDTH - 1 downto 2);
o_ram.remote_addr <= src_addr;
o_memif.step <= 1;
when 1 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE_BYTES, C_MEMIF_LENGTH_WIDTH), 2);
else
fifo_push_word(i_memif, o_memif, MEMIF_CMD_READ & i_ram.remainder & "00", 2);
end if;
when 2 =>
fifo_push_word(i_memif, o_memif, i_ram.remote_addr, 3);
when 3 =>
if i_ram.remainder > C_CHUNK_SIZE then
fifo_pull(i_memif, o_memif, i_ram, o_ram, CONV_STD_LOGIC_VECTOR(C_CHUNK_SIZE, C_MEMIF_LENGTH_WIDTH - 2), 4);
else
fifo_pull(i_memif, o_memif, i_ram, o_ram, i_ram.remainder, 4);
end if;
when 4 =>
if i_ram.remainder > C_CHUNK_SIZE then
-- o_ram.addr is incremented by fifo_push
o_ram.remainder <= i_ram.remainder - C_CHUNK_SIZE;
o_ram.remote_addr <= i_ram.remote_addr + C_CHUNK_SIZE_BYTES;
o_ram.addr <= i_ram.addr + 1;
o_memif.step <= 1;
else
o_memif.step <= 5;
end if;
when others =>
done := True;
o_memif.step <= 0;
end case;
end procedure memif_read;
end package body reconos_pkg;
| mit | 6c45e84e12460e010defe8c57d4bcc32 | 0.611875 | 2.732602 | false | false | false | false |
EPiCS/soundgates | hardware/basic/cordic/cordic.vhd | 1 | 4,516 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - cordic.vhd
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: Cordic top level entity
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity cordic is
generic (
pipeline_stages : integer := 24
);
port (
phi : in signed(31 downto 0); -- 0 < phi < 2 * pi
sin : out signed(31 downto 0);
cos : out signed(31 downto 0);
clk : in std_logic; -- clock
rst : in std_logic; -- reset
ce : in std_logic -- enable
);
end cordic;
architecture Behavioral of cordic is
type pipeline_array is array (0 to pipeline_stages + 1) of signed(31 downto 0);
signal x_pipeline : pipeline_array;
signal y_pipeline : pipeline_array;
signal z_pipeline : pipeline_array;
constant cordic_gain : real := 0.60725293500888;
constant q1 : signed(31 downto 0) := to_signed(integer(real(MATH_PI / 2.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant q2 : signed(31 downto 0) := to_signed(integer(real(MATH_PI * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant q3 : signed(31 downto 0) := to_signed(integer(real(3.0 * MATH_PI / 2.0* 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant q4 : signed(31 downto 0) := to_signed(integer(real(2.0 * MATH_PI * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant cordic_x_init : signed(31 downto 0) := to_signed(integer(real(1.0 * cordic_gain * 2**SOUNDGATE_FIX_PT_SCALING)),32);
constant cordic_y_init : signed(31 downto 0) := to_signed(integer(real(0.0 * cordic_gain * 2**SOUNDGATE_FIX_PT_SCALING)),32);
signal sin_i : signed(47 downto 0) := (others => '0');
signal cos_i : signed(47 downto 0) := (others => '0');
signal cordic_out_x : signed(31 downto 0) := (others => '0');
signal cordic_out_y : signed(31 downto 0) := (others => '0');
signal x_i : signed(31 downto 0) := cordic_x_init;
signal y_i : signed(31 downto 0) := cordic_y_init;
signal phi_i : signed(31 downto 0) := (others => '0');
begin
-- rotates the vector (x,y) according to the quadrant in the unit circule
VEC_ROTATE_PROCESS : process(clk, rst)
begin
if rst = '1' then
x_i <= cordic_x_init;
y_i <= cordic_y_init;
phi_i <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
if phi < q1 then
x_i <= cordic_x_init;
y_i <= cordic_y_init;
phi_i <= phi;
elsif phi < q2 then
phi_i <= phi + (-q1);
x_i <= -cordic_y_init;
y_i <= cordic_x_init;
elsif phi < q3 then
x_i <= (-cordic_x_init);
y_i <= (-cordic_y_init);
phi_i <= phi + (-q2);
elsif phi < q4 then
x_i <= (-cordic_y_init);
y_i <= (-cordic_x_init);
phi_i <= phi + (-q3);
end if;
end if;
end if;
end process;
x_pipeline(0) <= x_i;
y_pipeline(0) <= y_i;
z_pipeline(0) <= phi_i;
-- instantiate cordic pipeline
CORDIC_PIPELINE : for i in 0 to pipeline_stages generate
PIPELINE_STAGE : entity work.cordic_stage
generic map(
stage => i,
alpha => real(2**(real(-i)))
)
port map(
clk => clk,
rst => rst,
ce => ce,
x => x_pipeline(i),
y => y_pipeline(i),
z => z_pipeline(i),
x_n => x_pipeline(i + 1),
y_n => y_pipeline(i + 1),
z_n => z_pipeline(i + 1)
);
end generate;
cordic_out_x <= x_pipeline(pipeline_stages + 1);
cordic_out_y <= y_pipeline(pipeline_stages + 1);
sin <= cordic_out_y(31) & cordic_out_y(29 downto 0) & "0";
cos <= cordic_out_x(31) & cordic_out_x(29 downto 0) & "0";
end Behavioral;
| mit | 5d98eb8adaf8438798d33a9afc72590c | 0.482064 | 3.164681 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_20.vhd | 1 | 1,286 | -- File: gray_counter_20.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_20 is
port (
gray_count: out unsigned(19 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_20;
architecture MyHDL of gray_counter_20 is
signal even: std_logic;
signal gray: unsigned(19 downto 0);
begin
GRAY_COUNTER_20_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(19 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((20 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 20-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_20_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | 8ff80e859dfc5bad3f6945b428013461 | 0.561431 | 3.402116 | false | false | false | false |
dfordivam/lava | Vhdl/lava.vhd | 3 | 2,065 | ---------------------------------------------------------------------
-- Lava Gates
---------------------------------------------------------------------
-- Koen Claessen, [email protected], 20000323
---------------------------------------------------------------------
-- entity declarations
entity
vdd
is
port
( clk : in bit
; outp : out bit
);
end entity vdd;
entity
gnd
is
port
( clk : in bit
; outp : out bit
);
end entity gnd;
entity
id
is
port
( clk : in bit
; inp : in bit
; outp : out bit
);
end entity id;
entity
inv
is
port
( clk : in bit
; inp : in bit
; outp : out bit
);
end entity inv;
entity
and2
is
port
( clk : in bit
; inp_1 : in bit
; inp_2 : in bit
; outp : out bit
);
end entity and2;
entity
or2
is
port
( clk : in bit
; inp_1 : in bit
; inp_2 : in bit
; outp : out bit
);
end entity or2;
entity
xor2
is
port
( clk : in bit
; inp_1 : in bit
; inp_2 : in bit
; outp : out bit
);
end entity xor2;
entity
delay
is
port
( clk : in bit
; init : in bit
; inp : in bit
; outp : out bit
);
end entity delay;
---------------------------------------------------------------------
-- behavioral descriptions
architecture
behavioral
of
vdd
is
begin
outp <= '1';
end;
architecture
behavioral
of
gnd
is
begin
outp <= '0';
end;
architecture
behavioral
of
id
is
begin
outp <= inp;
end;
architecture
behavioral
of
inv
is
begin
outp <= not inp;
end;
architecture
behavioral
of
and2
is
begin
outp <= inp_1 and inp_2;
end;
architecture
behavioral
of
or2
is
begin
outp <= inp_1 or inp_2;
end;
architecture
behavioral
of
xor2
is
begin
outp <= inp_1 xor inp_2;
end;
architecture
behavioral
of
delay
is
begin
latch : process is
variable state : bit;
begin
state := init;
loop
wait until clk = '1';
outp <= state;
state := inp;
end loop;
end process latch;
end;
---------------------------------------------------------------------
-- the end.
| bsd-3-clause | eebf005635b0304a3ac4facb612b597e | 0.491041 | 3.401977 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/nbit_register.vhd | 1 | 440 | Library ieee;
Use ieee.std_logic_1164.all;
Entity my_nDFF is
Generic ( n : integer := 16);
port( Clk,Rst : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0);
enable:in std_logic
);
end my_nDFF;
Architecture a_my_nDFF of my_nDFF is
begin
Process (Clk,Rst,enable)
begin
if Rst = '1' then
q <= (others=>'0');
elsif rising_edge(Clk)and enable='1' then
q <= d;
end if;
end process;
end a_my_nDFF;
| mit | 7514a296b9c72843f3ac267b132016ef | 0.675 | 2.5 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/rx_ver_reg.vhd | 1 | 4,286 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver RxVersion register. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/06/04 15:55:07 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1 2004/06/03 17:51:41 gedra
-- Receiver version register.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx_ver_reg is
generic (DATA_WIDTH: integer;
ADDR_WIDTH: integer;
CH_ST_CAPTURE: integer);
port (
ver_rd: in std_logic; -- version register read
ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data
end rx_ver_reg;
architecture rtl of rx_ver_reg is
signal version : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
ver_dout <= version when ver_rd = '1' else (others => '0');
-- version vector generation
version(3 downto 0) <= "0001"; -- version 1
G32: if DATA_WIDTH = 32 generate
version(4) <= '1';
version(31 downto 20) <= (others => '0');
version(19 downto 16) <=
std_logic_vector(to_unsigned(CH_ST_CAPTURE, 4));
end generate G32;
G16: if DATA_WIDTH = 16 generate
version(4) <= '0';
end generate G16;
version(11 downto 5) <= std_logic_vector(to_unsigned(ADDR_WIDTH, 7));
version(15 downto 12) <= (others => '0');
end rtl;
| mit | b11cb5048d96b05426d351672f64a8b1 | 0.39734 | 5.370927 | false | false | false | false |
EPiCS/soundgates | hardware/basic/adsr/adsr_tb.vhd | 1 | 2,655 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
--library soundgates_v1_00_a;
--use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY adsr_tb IS
END adsr_tb;
ARCHITECTURE behavior OF adsr_tb IS
COMPONENT adsr
PORT(
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
attack : IN signed(31 downto 0);
decay : IN signed(31 downto 0);
release : IN signed(31 downto 0);
sustain : IN signed(31 downto 0);
start_amp : IN signed(31 downto 0);
attack_amp : IN signed(31 downto 0);
sustain_amp : IN signed(31 downto 0);
release_amp : IN signed(31 downto 0);
wave : OUT signed(31 downto 0)
);
END COMPONENT;
type states is (s_reset, s_calc);
signal state : states := s_reset;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal ce : std_logic := '1';
signal attack : signed(31 downto 0) := to_signed(integer(real( 0.1 * 2**27)), 32);
signal decay : signed(31 downto 0) := to_signed(integer(real( 0.1 * 2**27)), 32);
signal sustain : signed(31 downto 0) := to_signed(integer(real( 2 * 2**27)), 32);
signal release : signed(31 downto 0) := to_signed(integer(real( 0.1 * 2**27)), 32);
signal start_amp : signed(31 downto 0) := to_signed(integer(real( 0.0 * 2**27)), 32);
signal attack_amp : signed(31 downto 0) := to_signed(integer(real( 1.5 * 2**27)), 32);
signal sustain_amp : signed(31 downto 0) := to_signed(integer(real( 1.0 * 2**27)), 32);
signal release_amp : signed(31 downto 0) := to_signed(integer(real( 0.0 * 2**27)), 32);
--Outputs
signal wave : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: adsr PORT MAP (
clk => clk,
rst => rst,
ce => ce,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
start_amp => start_amp,
attack_amp => attack_amp,
sustain_amp => sustain_amp,
release_amp => release_amp,
wave => wave
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
rst <= '0';
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| mit | c53e39b1b6e238bd6ac340d071a1344f | 0.570245 | 3.399488 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 23,237 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu Dec 15 12:04:13 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library axi_spdif_rx_v1_00_a;
use axi_spdif_rx_v1_00_a.rx_package.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 8;
CH_ST_CAPTURE : integer := 1;
AXI_FREQ : natural := 100;
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 8;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
rx_int_o: out std_logic;
spdif_rx_i: in std_logic;
spdif_rx_i_osc: out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
--AXI streaming interface
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
signal data_out, ver_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal ver_rd : std_logic;
signal conf_rxen, conf_sample, evt_en, conf_chas, conf_valid : std_logic;
signal conf_blken, conf_valen, conf_useren, conf_staten : std_logic;
signal conf_paren, config_rd, config_wr : std_logic;
signal conf_mode : std_logic_vector(3 downto 0);
signal conf_bits, conf_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal status_rd : std_logic;
signal stat_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal imask_bits, imask_dout: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal imask_rd, imask_wr : std_logic;
signal istat_dout, istat_events: std_logic_vector(DATA_WIDTH - 1 downto 0);
signal istat_rd, istat_wr, istat_lock : std_logic;
signal istat_lsbf, istat_hsbf, istat_paritya, istat_parityb: std_logic;
signal istat_cap : std_logic_vector(7 downto 0);
signal ch_st_cap_rd, ch_st_cap_wr, ch_st_data_rd: std_logic_vector(7 downto 0);
signal cap_dout : bus_array;
signal ch_data, ud_a_en, ud_b_en, cs_a_en, cs_b_en: std_logic;
signal mem_rd, sample_wr, sample_wr_d1 : std_logic;
signal sample_din, sample_dout : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal sbuf_wr_adr, sbuf_rd_adr : std_logic_vector(ADDR_WIDTH - 2 downto 0);
signal lock, rx_frame_start: std_logic;
signal rx_data, rx_data_en, rx_block_start: std_logic;
signal rx_channel_a, rx_error, lock_evt: std_logic;
signal version_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal control_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal cap_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal chstatus_reg : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(7 downto 0);
signal slv_reg_read_sel : std_logic_vector(7 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
type RAM_TYPE is array (0 to (2**ADDR_WIDTH - 1)) of std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal audio_fifo : RAM_TYPE;
signal audio_fifo_wr_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal audio_fifo_rd_addr : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal tvalid : std_logic := '0';
begin
-- Audio samples FIFO management
AUDIO_FIFO_PROCESS : process (M_AXIS_ACLK) is
variable data_cnt : std_logic_vector(ADDR_WIDTH - 1 downto 0);
begin
if M_AXIS_ACLK'event and M_AXIS_ACLK = '1' then
if Bus2IP_Resetn = '0' then
audio_fifo_wr_addr <= (others => '0');
audio_fifo_rd_addr <= (others => '0');
data_cnt := "00000000";
else
sample_wr_d1 <= sample_wr;
if ((sample_wr_d1 = '0')and(sample_wr = '1')) then
audio_fifo(conv_integer(audio_fifo_wr_addr)) <= sample_din;
audio_fifo_wr_addr <= audio_fifo_wr_addr + '1';
if(data_cnt < (2**ADDR_WIDTH - 1)) then
data_cnt := data_cnt + '1';
end if;
end if;
if((tvalid = '1') and (M_AXIS_TREADY = '1'))
then
audio_fifo_rd_addr <= audio_fifo_rd_addr + '1';
data_cnt := data_cnt - '1';
end if;
if(data_cnt > 0)
then
tvalid <= '1';
else
tvalid <= '0';
end if;
end if;
end if;
end process AUDIO_FIFO_PROCESS;
M_AXIS_TDATA <= audio_fifo(conv_integer(audio_fifo_rd_addr(ADDR_WIDTH-1 downto 0)));
M_AXIS_TVALID <= tvalid;
M_AXIS_TLAST <= '0';
M_AXIS_TKEEP <= "1111";
-- SPDIF registers update
version_reg <= slv_reg0;
control_reg <= slv_reg1;
slv_reg2 <= chstatus_reg;
cap_reg <= slv_reg3;
--USER logic implementation added here
-------------------------------------------------------------------------------
-- Version Register
-------------------------------------------------------------------------------
version_reg(31 downto 20) <= (others => '0');
version_reg(19 downto 16) <= std_logic_vector(to_unsigned(CH_ST_CAPTURE, 4));
version_reg(15 downto 12) <= (others => '0');
version_reg(11 downto 5) <= std_logic_vector(to_unsigned(ADDR_WIDTH,7));
version_reg(4) <= '1';
version_reg(3 downto 0) <= "0001";
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Control Register
--------------------------------------------------------------------------------
conf_mode(3 downto 0) <= control_reg(23 downto 20);
conf_paren <= control_reg(19);
conf_staten <= control_reg(18);
conf_useren <= control_reg(17);
conf_valen <= control_reg(16);
conf_blken <= control_reg(5);
conf_valid <= control_reg(4);
conf_chas <= control_reg(3);
evt_en <= control_reg(2);
conf_sample <= control_reg(1);
conf_rxen <= control_reg(0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Status Register
--------------------------------------------------------------------------------
STAT: rx_status_reg
generic map
(
DATA_WIDTH => DATA_WIDTH
)
port map
(
up_clk => Bus2IP_Clk,
status_rd => Bus2IP_RdCE(2),
lock => lock,
chas => conf_chas,
rx_block_start => rx_block_start,
ch_data => rx_data,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en,
status_dout => chstatus_reg
);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Capture Register
--------------------------------------------------------------------------------
GCAP: if DATA_WIDTH = 32 and CH_ST_CAPTURE > 0
generate
CAPR: for k in 0 to CH_ST_CAPTURE - 1
generate
CHST: rx_cap_reg
port map
(
clk => Bus2IP_Clk,
rst => Bus2IP_Resetn,
--cap_ctrl_wr => ch_st_cap_wr(k),
--cap_ctrl_rd => ch_st_cap_rd(k),
--cap_data_rd => ch_st_data_rd(k),
cap_reg => cap_reg,
cap_din => Bus2IP_Data,
cap_dout => cap_dout(k),
cap_evt => istat_cap(k),
rx_block_start => rx_block_start,
ch_data => rx_data,
ud_a_en => ud_a_en,
ud_b_en => ud_b_en,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en
);
end generate CAPR;
-- unused capture registers set to zero
UCAPR: if CH_ST_CAPTURE < 8
generate
UC: for k in CH_ST_CAPTURE to 7
generate
cap_dout(k) <= (others => '0');
end generate UC;
end generate UCAPR;
end generate GCAP;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Phase decoder
--------------------------------------------------------------------------------
PDET: rx_phase_det
generic map
(
AXI_FREQ => AXI_FREQ -- WishBone frequency in MHz
)
port map
(
up_clk => Bus2IP_Clk,
rxen => conf_rxen,
spdif => spdif_rx_i,
lock => lock,
lock_evt => lock_evt,
rx_data => rx_data,
rx_data_en => rx_data_en,
rx_block_start => rx_block_start,
rx_frame_start => rx_frame_start,
rx_channel_a => rx_channel_a,
rx_error => rx_error,
ud_a_en => ud_a_en,
ud_b_en => ud_b_en,
cs_a_en => cs_a_en,
cs_b_en => cs_b_en
);
spdif_rx_i_osc <= spdif_rx_i;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Rx Decoder
--------------------------------------------------------------------------------
FDEC: rx_decode
generic map
(
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH
)
port map
(
up_clk => Bus2IP_Clk,
conf_rxen => conf_rxen,
conf_sample => conf_sample,
conf_valid => conf_valid,
conf_mode => conf_mode,
conf_blken => conf_blken,
conf_valen => conf_valen,
conf_useren => conf_useren,
conf_staten => conf_staten,
conf_paren => conf_paren,
lock => lock,
rx_data => rx_data,
rx_data_en => rx_data_en,
rx_block_start => rx_block_start,
rx_frame_start => rx_frame_start,
rx_channel_a => rx_channel_a,
wr_en => sample_wr,
wr_addr => sbuf_wr_adr,
wr_data => sample_din,
stat_paritya => istat_paritya,
stat_parityb => istat_parityb,
stat_lsbf => istat_lsbf,
stat_hsbf => istat_hsbf
);
rx_int_o <= sample_wr;
--------------------------------------------------------------------------------
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(7 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(7 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
--slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
--when "00100000" =>
--for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
--if ( Bus2IP_BE(byte_index) = '1' ) then
--slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
--end if;
--end loop;
when "00010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7 ) is
begin
case slv_reg_read_sel is
when "10000000" => slv_ip2bus_data <= slv_reg0;
when "01000000" => slv_ip2bus_data <= slv_reg1;
when "00100000" => slv_ip2bus_data <= slv_reg2;
when "00010000" => slv_ip2bus_data <= slv_reg3;
when "00001000" => slv_ip2bus_data <= slv_reg4;
when "00000100" => slv_ip2bus_data <= slv_reg5;
when "00000010" => slv_ip2bus_data <= slv_reg6;
when "00000001" => slv_ip2bus_data <= slv_reg7;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 733d9e795f1d45336c6d880eb0b2072c | 0.468821 | 3.911953 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_12.vhd | 1 | 1,286 | -- File: gray_counter_12.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_12 is
port (
gray_count: out unsigned(11 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_12;
architecture MyHDL of gray_counter_12 is
signal even: std_logic;
signal gray: unsigned(11 downto 0);
begin
GRAY_COUNTER_12_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(11 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((12 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 12-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_12_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | d828faa6f30414ff48f1cfce852a0b38 | 0.561431 | 3.402116 | false | false | false | false |
EPiCS/soundgates | hardware/basic/fir/fir_transposed.vhd | 1 | 2,493 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - fir.vhd
--
-- project: PG-Soundgates
-- author: Lukas Funke, University of Paderborn
--
-- description: FIR filter with order FIR_ORDER
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity fir is
generic(
FIR_ORDER : integer := 8 --> 10 coefficients
);
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
coefficients : in mem16(FIR_ORDER downto 0);
x_in : in signed(23 downto 0);
y_out : out signed(23 downto 0)
);
end fir;
architecture Behavioral of fir is
signal taps : mem24(FIR_ORDER downto 0) := (others => (others => '0'));
begin
FIR_CHAIN : process (clk, rst, ce)
variable tmp : std_logic_vector(39 downto 0);
variable tmp_scale : std_logic_vector(23 downto 0);
begin
if rst = '1' then
taps <= (others => (others => '0'));
elsif rising_edge(clk) then
if ce = '1' then
for i in 0 to FIR_ORDER loop
if i = 0 then
tmp := std_logic_vector(x_in * coefficients(FIR_ORDER));
taps(0) <= signed(tmp(39) & tmp(37 downto 15));
else
tmp := std_logic_vector(x_in * coefficients(FIR_ORDER - i));
tmp_scale := tmp(39) & tmp(37 downto 15);
tmp_scale := std_logic_vector(signed(tmp_scale) + taps(i - 1)); -- possible overflow error!
taps(i) <= signed(tmp_scale);
end if;
end loop;
end if;
end if;
end process;
y_out <= taps(FIR_ORDER);
end Behavioral;
| mit | a5dcae765d0cfc37607c2589aff53024 | 0.387886 | 3.932177 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/memoryForMemoryStage.vhd | 1 | 1,385 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity syncram2 is
Generic ( n : integer := 8);
port ( clk,rst : in std_logic;
we, weStack, stackPushPop : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end entity syncram2;
architecture syncrama2 of syncram2 is
type ram_type is array (0 to (2**n)-1) of std_logic_vector(15 downto 0);
signal ram : ram_type;
signal stackAdress : std_logic_vector(9 downto 0);
begin
process(clk,datain,rst) is
begin
if rst = '1' then
stackAdress <= "1111111111";
end if;
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
--end if;
elsif weStack = '1' then
if stackPushPop = '0' then--push
ram(to_integer(unsigned(stackAdress))) <= datain;
stackAdress <= std_logic_vector(unsigned(stackAdress)-1);
else -- pop
stackAdress <= std_logic_vector(unsigned(stackAdress)+1);
ram(to_integer(unsigned(stackAdress))) <= datain;
end if;
end if;
end if;
end process;
dataout <= ram(to_integer(unsigned(stackAdress))) when weStack = '1' and stackPushPop = '1' else
ram(to_integer(unsigned(address)));
dataout0 <= ram(0);
dataout1 <= ram(1);
end architecture syncrama2; | mit | 4f4a4d7a9e48adac5f90af4d05aa053b | 0.698917 | 2.972103 | false | false | false | false |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_spdif_rx_v1_00_a/hdl/vhdl/gen_control_reg.vhd | 1 | 4,993 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Generic control register. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/06/06 15:42:19 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2 2004/06/04 15:55:07 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1 2004/06/03 17:47:17 gedra
-- Generic control register. Used in both recevier and transmitter.
--
--
library ieee;
use ieee.std_logic_1164.all;
entity gen_control_reg is
generic (DATA_WIDTH: integer;
-- note that this vector is (0 to xx), reverse order
ACTIVE_BIT_MASK: std_logic_vector);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
ctrl_wr: in std_logic; -- control register write
ctrl_rd: in std_logic; -- control register read
ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- control bits
end gen_control_reg;
architecture rtl of gen_control_reg is
signal ctrl_internal: std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');
ctrl_bits <= ctrl_internal;
-- control register generation
CTRLREG: for k in ctrl_din'range generate
-- active bits can be written to
ACTIVE: if ACTIVE_BIT_MASK(k) = '1' generate
CBIT: process (clk, rst)
begin
if rst = '1' then
ctrl_internal(k) <= '0';
else
if rising_edge(clk) then
if ctrl_wr = '1' then
ctrl_internal(k) <= ctrl_din(k);
end if;
end if;
end if;
end process CBIT;
end generate ACTIVE;
-- inactive bits are always 0
INACTIVE: if ACTIVE_BIT_MASK(k) = '0' generate
ctrl_internal(k) <= '0';
end generate INACTIVE;
end generate CTRLREG;
end rtl;
| mit | b9cb6b623a3f8353a8898d1e0a558f51 | 0.416984 | 5.179461 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Execution.vhd | 1 | 2,448 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
ENTITY Execution IS
port(
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1_Reg1,R2_Reg1,ROut_Alu1,ROut_Mem1: in std_logic_vector(2 downto 0);
R1_dec: in std_logic_vector(15 downto 0);
R2_dec: in std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Alu_Output_exe , Meomry_Output_exe: in std_logic_vector(15 downto 0);
Execution_Output: out std_logic_vector(15 downto 0);
Z_F: out std_logic;
NF_F: out std_logic;
V_F: out std_logic;
C_F: out std_logic
);
END Execution;
Architecture archi of Execution is
component ALU is
port (
Clk,Rst,enable : in std_logic;
OpCode : in std_logic_vector(4 downto 0);
R1: in std_logic_vector(15 downto 0);
R2: in std_logic_vector(15 downto 0);
Output: out std_logic_vector(15 downto 0);
n : in std_logic_vector (3 downto 0);
Z: out std_logic;
NF: out std_logic;
v: out std_logic;
C: out std_logic
);
end component;
component Forwarding IS
port(
R1_Reg,R2_Reg,ROut_Alu,ROut_Mem: in std_logic_vector(2 downto 0);
R1,R2: out std_logic_vector(15 downto 0);
R1_Mux,R2_Mux : out std_logic;
Alu_Output , Meomry_Output: in std_logic_vector(15 downto 0)
--Alu_Output1 , Meomry_Output1: out std_logic_vector(15 downto 0);
--WriteBackSignal : in std_logic
);
END component;
signal R1_Forward_out_signal,R2_Forward_out_signal : std_logic_vector(15 downto 0);
signal R1_signal,R2_signal : std_logic_vector(15 downto 0);
signal R1_Mux_signal,R2_Mux_signal : std_logic;
signal Execution_Output_signal : std_logic_vector(15 downto 0); --ALU output
signal Z_signal,NF_signal,V_signal,C_signal : std_logic; --flags
begin
forward_map: Forwarding port map(R1_Reg1,R2_Reg1,ROut_Alu1,ROut_Mem1,R1_Forward_out_signal,R2_Forward_out_signal,R1_Mux_signal,R2_Mux_signal,Alu_Output_exe , Meomry_Output_exe);
Alu_map: ALU port map(Clk,Rst,enable,OpCode,R1_signal,R2_signal,Execution_Output_signal,n, Z_signal,NF_signal,V_signal,C_signal);
R1_signal <= R1_Forward_out_signal when R1_Mux_signal = '1' else
R1_dec when R1_Mux_signal = '0';
R2_signal <= R2_Forward_out_signal when R2_Mux_signal = '1' else
R2_dec when R2_Mux_signal = '0';
Execution_Output <= Execution_Output_signal;
Z_F <= Z_signal;
NF_F <= NF_signal;
V_F <= V_signal;
C_F <= C_signal;
end archi; | mit | 647522a7480c1208a9451d028a684925 | 0.681373 | 2.576842 | false | false | false | false |
EPiCS/soundgates | hardware/basic/amplifier/amplifier.vhd | 1 | 1,510 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - amplifier.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: amplifies samples
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity amplifier is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
wave : in signed(31 downto 0);
percentage: in signed(31 downto 0);
amp : out signed(31 downto 0)
);
end amplifier;
architecture Behavioral of amplifier is
begin
ampl : process (clk, rst, ce)
begin
if rising_edge(clk) then
if ce = '1' then
amp <= resize(wave * percentage, 32);
end if;
end if;
end process;
end Behavioral;
| mit | 9c7744ec3004026fd86f9f399fb6790b | 0.356291 | 3.832487 | false | false | false | false |
aylons/sp601_spi_test | hdl/top/spi_test_top.vhd | 1 | 6,082 | -------------------------------------------------------------------------------
-- Title : Top module for SPI test
-- Project :
-------------------------------------------------------------------------------
-- File : spi_test_top.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-10-23
-- Last update: 2014-11-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top module for SPI test. Outputs may be connected directly to pins
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-23 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spi_test_top is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
on_sw_i : in std_logic;
on_led_o : out std_logic;
rst_i : in std_logic;
--master_1
spi1_sck_o : out std_logic;
spi1_mosi_o : out std_logic;
spi1_miso_i : in std_logic;
spi1_ssel_o : out std_logic;
--slave_1
spi1_sck_i : in std_logic;
spi1_mosi_i : in std_logic;
spi1_miso_o : out std_logic;
spi1_ssel_i : in std_logic;
--master_2
spi2_sck_o : out std_logic;
spi2_mosi_o : out std_logic;
spi2_miso_i : in std_logic;
spi2_ssel_o : out std_logic;
--slave_2
spi2_sck_i : in std_logic;
spi2_mosi_i : in std_logic;
spi2_miso_o : out std_logic;
spi2_ssel_i : in std_logic;
--master_3
spi3_sck_o : out std_logic;
spi3_mosi_o : out std_logic;
spi3_miso_i : in std_logic;
spi3_ssel_o : out std_logic;
--slave_3
spi3_sck_i : in std_logic;
spi3_mosi_i : in std_logic;
spi3_miso_o : out std_logic;
spi3_ssel_i : in std_logic
);
end entity spi_test_top;
architecture structural of spi_test_top is
constant c_width : positive := 16;
-- service signals
signal clk_200M, clk_80M, clk_50M : std_logic;
signal locked : std_logic;
signal reset : std_logic := '0';
signal reset_n : std_logic := '1';
-- debugging
signal control1, control2, control3 : std_logic_vector(35 downto 0);
component spi_single_test is
generic (
g_width : positive);
port (
clk_i : in std_logic;
rst_i : in std_logic;
spi_sck_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_ssel_o : out std_logic;
spi_sck_i : in std_logic;
spi_mosi_i : in std_logic;
spi_miso_o : out std_logic;
spi_ssel_i : in std_logic;
chipscope_control : out std_logic_vector(35 downto 0));
end component spi_single_test;
component clk_wiz_v3_3 is
port (
CLK_IN_P : in std_logic;
CLK_IN_N : in std_logic;
clk_200M : out std_logic;
clk_80M : out std_logic;
clk_50M : out std_logic;
reset_i : in std_logic;
locked_o : out std_logic);
end component clk_wiz_v3_3;
component reset_dcm is
generic (
cycles : positive);
port (
clk : in std_logic;
locked_i : in std_logic;
reset_o : out std_logic);
end component reset_dcm;
component chipscope_icon is
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
CONTROL1 : inout std_logic_vector(35 downto 0);
CONTROL2 : inout std_logic_vector(35 downto 0));
end component chipscope_icon;
begin
on_led_o <= on_sw_i;
cmp_dcm : clk_wiz_v3_3
port map (
CLK_IN_P => sys_clk_p_i,
CLK_IN_N => sys_clk_n_i,
CLK_200M => clk_200M,
CLK_80M => clk_80M,
CLK_50M => clk_50M,
reset_i => rst_i,
locked_o => locked);
cmp_reset_dcm : reset_dcm
generic map (
cycles => 100)
port map (
clk => clk_50M,
locked_i => locked,
reset_o => reset);
cmp_spi_single_test_1 : spi_single_test
generic map (
g_width => c_width)
port map (
clk_i => clk_200M,
rst_i => reset,
spi_sck_o => spi1_sck_o,
spi_mosi_o => spi1_mosi_o,
spi_miso_i => spi1_miso_i,
spi_ssel_o => spi1_ssel_o,
spi_sck_i => spi1_sck_i,
spi_mosi_i => spi1_mosi_i,
spi_miso_o => spi1_miso_o,
spi_ssel_i => spi1_ssel_i,
chipscope_control => control1);
cmp_spi_single_test_2 : spi_single_test
generic map (
g_width => c_width)
port map (
clk_i => clk_80M,
rst_i => reset,
spi_sck_o => spi2_sck_o,
spi_mosi_o => spi2_mosi_o,
spi_miso_i => spi2_miso_i,
spi_ssel_o => spi2_ssel_o,
spi_sck_i => spi2_sck_i,
spi_mosi_i => spi2_mosi_i,
spi_miso_o => spi2_miso_o,
spi_ssel_i => spi2_ssel_i,
chipscope_control => control2);
cmp_spi_single_test_3 : spi_single_test
generic map (
g_width => c_width)
port map (
clk_i => clk_50M,
rst_i => reset,
spi_sck_o => spi3_sck_o,
spi_mosi_o => spi3_mosi_o,
spi_miso_i => spi3_miso_i,
spi_ssel_o => spi3_ssel_o,
spi_sck_i => spi3_sck_i,
spi_mosi_i => spi3_mosi_i,
spi_miso_o => spi3_miso_o,
spi_ssel_i => spi3_ssel_i,
chipscope_control => control3);
cmp_icon : chipscope_icon
port map (
CONTROL0 => control1,
CONTROL1 => control2,
CONTROL2 => control3);
end architecture structural;
| gpl-3.0 | f41837393ebbead2b0a24fe1e0389b20 | 0.488326 | 3.197687 | false | true | false | false |
IslamKhaledH/ArchitecturePorject | Project/DMA.vhd | 1 | 1,249 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity DMA is
PORT ( Clk,Mux_Selector, Memory_WriteEnable : in std_logic;
InputAddress, LoadAdress : in std_logic_vector(9 downto 0);
DataIn : in std_logic_vector(15 downto 0);
DataOut, M0, M1 : out std_logic_vector (15 downto 0);
Flags_In : in std_logic_vector(3 downto 0);
Flags_Out : out std_logic_vector(3 downto 0)
);
END DMA;
architecture MyDMA of DMA is
Component syncram is
Generic (n : integer := 8);
port ( clk : in std_logic;
we : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0);
dataout0 : out std_logic_vector(15 downto 0);
dataout1 : out std_logic_vector(15 downto 0)
);
end Component syncram;
signal Address : std_logic_vector(9 downto 0);
signal DI :std_logic_vector(15 downto 0);
signal DO,DO0,DO1 : std_logic_vector(15 downto 0);
signal dontCare1, dontCare2 : std_logic_vector (15 downto 0);
begin
Mem : syncram generic map(n=>10) port map(Clk, Memory_WriteEnable, Address,DI,DO,DO0,DO1);
Address <= InputAddress when Mux_Selector = '0' else
LoadAdress;
Flags_Out <= Flags_In;
DataOut <= DO;
M0 <= DO0;
M1 <= DO1;
end architecture MyDMA; | mit | c4478f8d0112590087847a3bc3daceb8 | 0.710969 | 2.911422 | false | false | false | false |
jandecaluwe/myhdl-examples | crusty_UK101/FourToSeven/vhdl/FourToSeven.vhd | 1 | 1,545 | -- File: FourToSeven.vhd
-- Generated by MyHDL 0.8dev
-- Date: Mon Mar 25 09:12:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity FourToSeven is
port (
ByteIn: in unsigned(3 downto 0);
Enable: in std_logic;
Polarity: in std_logic;
SegOut: out unsigned(6 downto 0)
);
end entity FourToSeven;
architecture MyHDL of FourToSeven is
begin
FOURTOSEVEN_COMB: process (Polarity, ByteIn, Enable) is
variable SegBuf: unsigned(6 downto 0);
begin
SegBuf := to_unsigned(0, 7);
if (Enable = '1') then
case to_integer(ByteIn) is
when 0 => SegBuf := "0111111";
when 1 => SegBuf := "0000110";
when 2 => SegBuf := "1011011";
when 3 => SegBuf := "1001111";
when 4 => SegBuf := "1100110";
when 5 => SegBuf := "1101101";
when 6 => SegBuf := "1111101";
when 7 => SegBuf := "0000111";
when 8 => SegBuf := "1111111";
when 9 => SegBuf := "1101111";
when 10 => SegBuf := "1110111";
when 11 => SegBuf := "1111100";
when 12 => SegBuf := "0111001";
when 13 => SegBuf := "1011110";
when 14 => SegBuf := "1111001";
when others => SegBuf := "1110001";
end case;
end if;
if (Polarity = '0') then
SegBuf := (not SegBuf);
end if;
SegOut <= SegBuf;
end process FOURTOSEVEN_COMB;
end architecture MyHDL;
| mit | 5c136a2b44b906f41640020677dd1789 | 0.546926 | 3.661137 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_ramp_v1_00_a/hdl/vhdl/hwt_ramp.vhd | 1 | 14,136 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_ramp
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating ramp envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_ramp is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_ramp;
architecture Behavioral of hwt_ramp is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
component ramp is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
incr2 : in signed(31 downto 0);
rmp : out signed(31 downto 0)
);
end component ramp;
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_ADDRESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_ramp : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMData_ramp : std_logic_vector(0 to 31); -- ramp to local ram
signal i_RAMData_ramp : std_logic_vector(0 to 31); -- local ram to ramp
signal o_RAMWE_ramp : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal ramp_ce : std_logic; -- ramp clock enable (like a start/stop signal)
signal input_data : signed(31 downto 0);
signal ramp_data : signed(31 downto 0);
signal ramp_wave : signed(31 downto 0);
signal start : std_logic;
signal stop : std_logic;
signal refresh_state : integer range 0 to 2;
signal process_state : integer range 0 to 2;
signal incr : std_logic_vector(31 downto 0);
signal decr : std_logic_vector(31 downto 0);
signal incr_addr : std_logic_vector(31 downto 0);
signal decr_addr : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant RAMP_START : std_logic_vector(31 downto 0) := x"0000000F";
constant RAMP_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_ramp <= std_logic_vector(ramp_wave);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_ADDRESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_ADDRESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
-- /ReconOS Stuff
ramp_INST : ramp
port map(
clk => clk,
rst => rst,
ce => ramp_ce,
incr => signed(incr),
incr2 => signed(decr),
rmp => ramp_data
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_ramp = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_ramp))) := o_RAMData_ramp;
else -- else needed, because ramp is consuming samples
i_RAMData_ramp <= local_ram(to_integer(unsigned(o_RAMAddr_ramp)));
end if;
end if;
end process;
ramp_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
ramp_ce <= '0';
incr <= (others => '0');
decr <= (others => '0');
o_RAMWE_ramp<= '0';
o_RAMAddr_ramp <= (others => '0');
refresh_state <= 0;
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
incr_addr <= snd_comp_header.opt_arg_addr;
decr_addr <= std_logic_vector(unsigned(snd_comp_header.opt_arg_addr) + 4);
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = RAMP_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = RAMP_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when 0 =>
memif_read_word(i_memif, o_memif, incr_addr , incr, done);
if done then
refresh_state <= 1;
end if;
when 1 =>
memif_read_word(i_memif, o_memif, decr_addr , decr, done);
if done then
refresh_state <= 2;
end if;
when 2 =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= 0;
state <= STATE_PROCESS;
end if;
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
ramp_ce <= '1';
process_state <= 1;
when 1 =>
o_RAMData_ramp <= std_logic_vector(resize(ramp_data * signed(i_RAMData_ramp), 32));
o_RAMWE_ramp <= '1';
ramp_ce <= '0';
process_state <= 0;
when 2 =>
o_RAMWE_ramp <= '0';
o_RAMAddr_ramp <= std_logic_vector(unsigned(o_RAMAddr_ramp) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_ramp <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_ADDR std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 107715151a4f1b19125cf9c8ef089989 | 0.472199 | 3.813326 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/reg_file.vhd | 1 | 3,805 | Library ieee;
Use ieee.std_logic_1164.all;
Entity REG is
Generic ( n : integer := 16);
port(
Clock,Reset: in std_logic;
d : in std_logic_vector(n-1 downto 0);
R1_Out, R2_Out : out std_logic_vector(15 downto 0);
w_en : in std_logic ;--write enable
Rout,R1,R2 : in std_logic_vector(2 downto 0);--
input_port : in std_logic_vector(15 downto 0);
wrt_data_reg_mux : in std_logic;
--------------------------------------------------------
Shift_Mux : in std_logic;--control unit
OPcode_in: in std_logic_vector(4 downto 0 );
OPcode_out: out std_logic_vector(4 downto 0 )
);
end REG;
Architecture REG_arc of REG is
component my_nDFF is
Generic ( n : integer := 16);
port( Clk,Rst : in std_logic;
d : in std_logic_vector(n-1 downto 0);
q : out std_logic_vector(n-1 downto 0);
enable:in std_logic
);
end component;
signal d1,d2,d3,d4,d5,d6 : std_logic_vector(15 downto 0);
signal q1,q2,q3,q4,q5,q6: std_logic_vector(15 downto 0);
begin
R11: my_nDFF generic map (n=>16)port map(Clock,Reset,d1,q1,'1');
R21: my_nDFF generic map (n=>16)port map(Clock,Reset,d2,q2,'1');
R31: my_nDFF generic map (n=>16)port map(Clock,Reset,d3,q3,'1');
R41: my_nDFF generic map (n=>16)port map(Clock,Reset,d4,q4,'1');
R51: my_nDFF generic map (n=>16)port map(Clock,Reset,d5,q5,'1');
R61: my_nDFF generic map (n=>16)port map(Clock,Reset,d6,q6,'1');
--WRITE BACK CLOCK NOT HANDELED
Process(Clock,Reset,w_en,Rout,R1,R2,d,wrt_data_reg_mux,Shift_Mux,input_port,OPcode_in)
begin
if Reset = '1' then
d1 <= (others=>'0');
d2 <= (others=>'0');
d3 <= (others=>'0');
d4 <= (others=>'0');
d5 <= (others=>'0');
d6 <= (others=>'0');
elsif Reset = '0' then
if Clock='1' then
OPcode_out<=OPcode_in;
if w_en = '1' then
if wrt_data_reg_mux ='0' then
if Shift_Mux = '0' then
if Rout = "000" then
d1 <= d;
elsif Rout = "001" then
d2 <= d;
elsif Rout = "010" then
d3 <= d;
elsif Rout = "011" then
d4 <= d;
elsif Rout = "100" then
d5 <=d;
elsif Rout = "101"then
d6 <=d;
end if;
elsif Shift_Mux='1' then
if R1 = "000" then
d1 <= d;
elsif R1 = "001" then
d2 <= d;
elsif R1 = "010" then
d3 <= d;
elsif R1 = "011" then
d4 <= d;
elsif R1 = "100" then
d5 <=d;
elsif R1 = "101"then
d6 <=d;
end if;
end if;
elsif wrt_data_reg_mux ='1' then
if Rout = "000" then
d1 <= input_port;
elsif Rout = "001" then
d2 <= input_port;
elsif Rout = "010" then
d3 <= input_port;
elsif Rout = "011" then
d4 <= input_port;
elsif Rout = "100" then
d5 <= input_port;
elsif Rout = "101"then
d6 <= input_port;
end if;
end if;
end if;
elsif Clock='0' then
if R1 = "000" then R1_Out <= q1;
elsif R1 = "001" then R1_Out <= q2;
elsif R1 = "010" then R1_Out <= q3;
elsif R1 = "011" then R1_Out <= q4;
elsif R1 = "100" then R1_Out <= q5;
elsif R1 = "101" then R1_Out <= q6;
end if;
if R2 = "000" then R2_Out <= q1;
elsif R2 = "001" then R2_Out <= q2;
elsif R2 = "010" then R2_Out <= q3;
elsif R2 = "011" then R2_Out <=q4 ;
elsif R2 = "100" then R2_Out <= q5;
elsif R2 = "101" then R2_Out <= q6;
end if;
end if;
end if;
end process;
end REG_arc;
| mit | bec45f00c3b698065c9104c7c957bfa2 | 0.489882 | 2.797794 | false | false | false | false |
EPiCS/soundgates | hardware/sndcomponents/nco_sync/nco_sync_tb.vhd | 1 | 2,455 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.NUMERIC_STD.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
ENTITY nco_sync_tb IS
END nco_sync_tb;
ARCHITECTURE behavior OF nco_sync_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component nco_sync
generic(
FPGA_FREQUENCY : integer := 100_000_000;
WAVEFORM : WAVEFORM_TYPE := SAW
);
Port (
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
master_phase_offset : in signed(31 downto 0);
master_phase_incr : in signed(31 downto 0);
slave_phase_offset : in signed(31 downto 0);
slave_phase_incr : in signed(31 downto 0);
data_master : out signed(31 downto 0);
data_slave : out signed(31 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '0';
signal phase_offset : signed(31 downto 0) := (others => '0');
signal master_phase_incr : signed(31 downto 0) := to_signed(integer(real(0.07 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal slave_phase_incr : signed(31 downto 0) := to_signed(integer(real(0.05 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant C_MAX_SAMPLE_COUNT : integer := 1024;
constant FPGA_FREQUENCY : integer := 100000000;
--Outputs
signal m_data : signed(31 downto 0);
signal s_data : signed(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: nco_sync PORT MAP (
clk => clk,
rst => rst,
ce => ce,
master_phase_offset => phase_offset,
master_phase_incr => master_phase_incr,
slave_phase_offset => phase_offset,
slave_phase_incr => slave_phase_incr,
data_master => m_data,
data_slave=> s_data
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
wait;
end process;
END;
| mit | b533a25112391f5cbcc8993cf96a6782 | 0.573523 | 3.487216 | false | false | false | false |
EPiCS/soundgates | hardware/basic/square/square.vhd | 1 | 3,111 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - square.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Square wave generator
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity square is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
duty_on : in signed(31 downto 0);
duty_off: in signed(31 downto 0);
sq : out signed(31 downto 0)
);
end square;
architecture Behavioral of square is
constant last_int : integer := integer(SOUNDGATE_FIX_PT_SCALING) + 1;
constant pi : signed (31 downto 0) := to_signed(integer(real(MATH_PI * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant two_pi : signed (31 downto 0) := to_signed(integer(real(2.0 *MATH_PI* 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant upper : signed (31 downto 0) := to_signed(integer(real( 1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant lower : signed (31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--constant add : signed (31 downto 0) := to_signed(integer(real(0.01 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal square : signed (31 downto 0) := upper;
begin
sq <= square;
CALC_SQ : process (clk, rst)
begin
if rst = '1' then
x <= offset;
else
if rising_edge(clk) then
if ce = '1' then
x <= x + incr;
if x >= to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32) then
square <= upper;
elsif x >= duty_on then --to_signed(integer(real( 1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32) then
square <= lower;
elsif x >= duty_off then --to_signed(integer(real( 2.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32) then
square <= upper;
x <= to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
end if;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | fd121a2730129f15033e7dc924644e79 | 0.441659 | 3.600694 | false | false | false | false |
jandecaluwe/myhdl-examples | gray_counter/vhdl/gray_counter_24.vhd | 1 | 1,286 | -- File: gray_counter_24.vhd
-- Generated by MyHDL 0.8dev
-- Date: Sun Feb 3 17:16:41 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity gray_counter_24 is
port (
gray_count: out unsigned(23 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_counter_24;
architecture MyHDL of gray_counter_24 is
signal even: std_logic;
signal gray: unsigned(23 downto 0);
begin
GRAY_COUNTER_24_SEQ: process (clock, reset) is
variable found: std_logic;
variable word: unsigned(23 downto 0);
begin
if (reset = '1') then
even <= '1';
gray <= (others => '0');
elsif rising_edge(clock) then
word := unsigned'("1" & gray((24 - 2)-1 downto 0) & even);
if bool(enable) then
found := '0';
for i in 0 to 24-1 loop
if ((word(i) = '1') and (not bool(found))) then
gray(i) <= stdl((not bool(gray(i))));
found := '1';
end if;
end loop;
even <= stdl((not bool(even)));
end if;
end if;
end process GRAY_COUNTER_24_SEQ;
gray_count <= gray;
end architecture MyHDL;
| mit | aadb83d35728328dcb8d2bbf441b4d32 | 0.561431 | 3.402116 | false | false | false | false |
EPiCS/soundgates | hardware/hwt/pcores/hwt_sample_sub_v1_00_a/hdl/vhdl/hwt_sample_sub.vhd | 1 | 13,021 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - hwt_sample_sub
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Hardware thread for generating sub envelope
--
-- ======================================================================
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--library proc_common_v3_00_a;
--use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_00_c;
use reconos_v3_00_c.reconos_pkg.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
use soundgates_v1_00_a.soundgates_reconos_pkg.all;
entity hwt_sample_sub is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
end hwt_sample_sub;
architecture Behavioral of hwt_sample_sub is
----------------------------------------------------------------
-- Subcomponent declarations
----------------------------------------------------------------
signal clk : std_logic;
signal rst : std_logic;
-- ReconOS Stuff
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram : i_ram_t;
signal o_ram : o_ram_t;
constant MBOX_START : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_FINISH : std_logic_vector(31 downto 0) := x"00000001";
-- /ReconOS Stuff
type STATE_TYPE is (STATE_INIT, STATE_WAITING, STATE_REFRESH_INPUT, STATE_PROCESS, STATE_WRITE_MEM, STATE_NOTIFY, STATE_EXIT);
signal state : STATE_TYPE;
----------------------------------------------------------------
-- Common sound component signals, constants and types
----------------------------------------------------------------
constant C_MAX_SAMPLE_COUNT : integer := 64;
-- define size of local RAM here
constant C_LOCAL_RAM_SIZE : integer := C_MAX_SAMPLE_COUNT;
constant C_LOCAL_RAM_addrESS_WIDTH : integer := 6;--clog2(C_LOCAL_RAM_SIZE);
constant C_LOCAL_RAM_SIZE_IN_BYTES : integer := 4*C_LOCAL_RAM_SIZE;
type LOCAL_MEMORY_T is array (0 to C_LOCAL_RAM_SIZE-1) of std_logic_vector(31 downto 0);
signal o_RAMAddr_sub : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_sub2: std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMData_sub : std_logic_vector(0 to 31); -- add to local ram
signal i_RAMData_sub : std_logic_vector(0 to 31); -- local ram to add
signal i_RAMData_sub2: std_logic_vector(0 to 31);
signal o_RAMWE_sub : std_logic;
signal o_RAMAddr_reconos : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1);
signal o_RAMAddr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAMData_reconos : std_logic_vector(0 to 31);
signal o_RAMWE_reconos : std_logic;
signal i_RAMData_reconos : std_logic_vector(0 to 31);
signal osif_ctrl_signal : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
constant o_RAMAddr_max : std_logic_vector(0 to C_LOCAL_RAM_addrESS_WIDTH-1) := (others=>'1');
shared variable local_ram : LOCAL_MEMORY_T;
signal snd_comp_header : snd_comp_header_msg_t; -- common sound component header
signal sample_count : unsigned(15 downto 0) := to_unsigned(0, 16);
----------------------------------------------------------------
-- Component dependent signals
----------------------------------------------------------------
signal refresh_state : std_logic;
signal process_state : integer range 0 to 2;
signal sub_data : signed(31 downto 0);
----------------------------------------------------------------
-- OS Communication
----------------------------------------------------------------
constant add_START : std_logic_vector(31 downto 0) := x"0000000F";
constant add_EXIT : std_logic_vector(31 downto 0) := x"000000F0";
begin
-----------------------------------
-- Hard wirings
-----------------------------------
clk <= HWT_Clk;
rst <= HWT_Rst;
--o_RAMData_sub <= std_logic_vector(sub_data);
o_RAMAddr_reconos(0 to C_LOCAL_RAM_addrESS_WIDTH-1) <= o_RAMAddr_reconos_2((32-C_LOCAL_RAM_addrESS_WIDTH) to 31);
-- ReconOS Stuff
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram,
o_ram,
o_RAMAddr_reconos_2,
o_RAMWE_reconos,
o_RAMData_reconos,
i_RAMData_reconos
);
local_ram_ctrl_1 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_reconos = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_reconos))) := o_RAMData_reconos;
else
i_RAMData_reconos <= local_ram(to_integer(unsigned(o_RAMAddr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAMWE_sub = '1') then
local_ram(to_integer(unsigned(o_RAMAddr_sub))) := o_RAMData_sub;
else -- else needed, because add is consuming samples
i_RAMData_sub <= local_ram(to_integer(unsigned(o_RAMAddr_sub)));
i_RAMData_sub2<= local_ram(to_integer(unsigned(o_RAMAddr_sub2)));
end if;
end if;
end process;
add_CTRL_FSM_PROC : process (clk, rst, o_osif, o_memif) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram);
state <= STATE_INIT;
sample_count <= to_unsigned(0, 16);
osif_ctrl_signal <= (others => '0');
o_RAMWE_sub<= '0';
o_RAMAddr_sub <= (others => '0');
o_RAMAddr_sub2 <= std_logic_vector(to_signed(C_MAX_SAMPLE_COUNT,o_RAMAddr_sub2'length));
refresh_state <= '0';
done := False;
elsif rising_edge(clk) then
case state is
-- INIT State gets the address of the header struct
when STATE_INIT =>
snd_comp_get_header(i_osif, o_osif, i_memif, o_memif, snd_comp_header, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_WAITING =>
-- Software process "Synthesizer" sends the start signal via mbox_start
osif_mbox_get(i_osif, o_osif, MBOX_START, osif_ctrl_signal, done);
if done then
if osif_ctrl_signal = add_START then
sample_count <= to_unsigned(0, 16);
state <= STATE_REFRESH_INPUT;
elsif osif_ctrl_signal = add_EXIT then
state <= STATE_EXIT;
end if;
end if;
when STATE_REFRESH_INPUT =>
-- Refresh your signals
case refresh_state is
when '0' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.source_addr, X"00000000", std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '1';
end if;
when '1' =>
memif_read(i_ram, o_ram, i_memif, o_memif, snd_comp_header.opt_arg_addr, std_logic_vector(to_unsigned(C_MAX_SAMPLE_COUNT,32)), std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)) ,done);
if done then
refresh_state <= '0';
state <= STATE_PROCESS;
end if;
when others =>
refresh_state <= '0';
end case;
when STATE_PROCESS =>
if sample_count < to_unsigned(C_MAX_SAMPLE_COUNT, 16) then
case process_state is
when 0 =>
sub_data <= signed(i_RAMData_sub) - signed(i_RAMData_sub2);
process_state <= 1;
when 1 =>
o_RAMData_sub <= std_logic_vector(resize(sub_data, 32));
o_RAMWE_sub <= '1';
process_state <= 0;
when 2 =>
o_RAMWE_sub <= '0';
o_RAMAddr_sub <= std_logic_vector(unsigned(o_RAMAddr_sub) + 1);
o_RAMAddr_sub2 <= std_logic_vector(unsigned(o_RAMAddr_sub2) + 1);
sample_count <= sample_count + 1;
process_state <= 0;
end case;
else
-- Samples have been generated
o_RAMAddr_sub <= (others => '0');
o_RAMAddr_sub2 <= (others => '0');
sample_count <= to_unsigned(0, 16);
state <= STATE_WRITE_MEM;
end if;
when STATE_WRITE_MEM =>
memif_write(i_ram, o_ram, i_memif, o_memif, X"00000000", snd_comp_header.dest_addr, std_logic_vector(to_unsigned(C_LOCAL_RAM_SIZE_IN_BYTES,24)), done);
if done then
state <= STATE_NOTIFY;
end if;
when STATE_NOTIFY =>
osif_mbox_put(i_osif, o_osif, MBOX_FINISH, snd_comp_header.dest_addr, ignore, done);
if done then
state <= STATE_WAITING;
end if;
when STATE_EXIT =>
osif_thread_exit(i_osif,o_osif);
end case;
end if;
end process;
end Behavioral;
-- ====================================
-- = RECONOS Function Library - Copy and Paste!
-- ====================================
-- osif_mbox_put(i_osif, o_osif, MBOX_NAME, SOURCESIGNAL, ignore, done);
-- osif_mbox_get(i_osif, o_osif, MBOX_NAME, TARGETSIGNAL, done);
-- Read from shared memory:
-- Speicherzugriffe:
-- Wortzugriff:
-- memif_read_word(i_memif, o_memif, addr, TARGETSIGNAL, done);
-- memif_write_word(i_memif, o_memif, addr, SOURCESIGNAL, done);
-- Die Laenge ist bei Speicherzugriffen Byte adressiert!
-- memif_read(i_ram, o_ram, i_memif, o_memif, SRC_addr std_logic_vector(31 downto 0);
-- dst_addr std_logic_vector(31 downto 0);
-- BYTES std_logic_vector(23 downto 0);
-- done);
-- memif_write(i_ram, o_ram, i_memif, o_memif,
-- src_addr : in std_logic_vector(31 downto 0),
-- dst_addr : in std_logic_vector(31 downto 0);
-- len : in std_logic_vector(23 downto 0);
-- done);
| mit | 87f6fcedf17d356e3450d661b6fb5bb6 | 0.488519 | 3.674097 | false | false | false | false |
EPiCS/soundgates | hardware/basic/fir/fir_transposed/fir_transposed_tb.vhd | 1 | 3,989 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
USE std.textio.all;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
--use soundgates_v1_00_a.soundgates_reconos_pkg.all;
ENTITY fir_transposed_tb IS
generic(
stim_filename : string := "sound_conv.out";
output_filename : string := "filtered.out"
);
END fir_transposed_tb;
ARCHITECTURE behavior OF fir_transposed_tb IS
constant FIR_ORDER : integer := 28;
-- Component Declaration
COMPONENT fir
generic(
FIR_ORDER : integer := 9 --> 10 coefficients
);
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
coefficients : in mem16(FIR_ORDER downto 0);
x_in : in signed(23 downto 0);
y_out : out signed(23 downto 0)
);
END COMPONENT;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ce : std_logic := '1';
constant scaling : real := 15.0;
constant coefficients : mem16(FIR_ORDER downto 0) := (
to_signed(45, 16),
to_signed(39, 16),
to_signed(30, 16),
to_signed(-1, 16),
to_signed(-76, 16),
to_signed(-215, 16),
to_signed(-433, 16),
to_signed(-733, 16),
to_signed(-1106, 16),
to_signed(-1526, 16),
to_signed(-1959, 16),
to_signed(-2360, 16),
to_signed(-2686, 16),
to_signed(-2898, 16),
to_signed(29796, 16),
to_signed(-2898, 16),
to_signed(-2686, 16),
to_signed(-2360, 16),
to_signed(-1959, 16),
to_signed(-1526, 16),
to_signed(-1106, 16),
to_signed(-733, 16),
to_signed(-433, 16),
to_signed(-215, 16),
to_signed(-76, 16),
to_signed(-1, 16),
to_signed(30, 16),
to_signed(39, 16),
to_signed(45, 16)
);
signal x_i : signed(23 downto 0);
signal y_i : signed(23 downto 0);
signal sample_out : std_logic_vector(31 downto 0);
file stimulus : TEXT is in stim_filename;
file outputfile : TEXT is out output_filename;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
sample_out <= std_logic_vector(y_i) & X"11" when y_i(23) = '1' else
std_logic_vector(y_i) & X"00";
-- Component Instantiation
uut: fir
generic map (
FIR_ORDER => FIR_ORDER
)
PORT MAP(
clk => clk,
rst => rst,
ce => ce,
coefficients => coefficients,
x_in => x_i,
y_out => y_i
);
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_process : PROCESS
variable sound_in_l : LINE;
variable sound_out_l : LINE;
variable sample_in : integer;
variable tmp : std_logic_vector(31 downto 0);
BEGIN
rst <= '1';
wait for 100 ns; -- wait until global set/reset completes
rst <= '0';
while not endfile(stimulus) loop
-- read sound data from input file
readline(stimulus, sound_in_l);
read(sound_in_l , sample_in);
tmp := std_logic_vector(to_signed(sample_in, 32));
x_i <= signed(tmp(31 downto 8));
write(sound_out_l, to_integer(signed(y_i)));
writeline(outputfile, sound_out_l);
wait until CLK = '1';
end loop;
-- Add user defined stimulus here
wait; -- will wait forever
END PROCESS stim_process;
-- End Test Bench
END;
| mit | 974395294fd92bd347b2f0761c07488d | 0.502883 | 3.649588 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/Instruction_Memory.vhd | 1 | 731 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity syncram is
Generic ( n : integer := 16);
port ( clk : in std_logic;
we : in std_logic;
address : in std_logic_vector(n-1 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0)
);
end entity syncram;
architecture syncrama of syncram is
type ram_type is array (0 to (2**n)-1) of std_logic_vector(15 downto 0);
signal ram : ram_type;
begin
process(clk) is
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
--dataout <= ram(to_integer(unsigned(address)));
end if;
end process;
dataout <= ram(to_integer(unsigned(address)));
end architecture syncrama; | mit | 1581070481ff1bf1268a0a1a8272ac46 | 0.705882 | 3.020661 | false | false | false | false |
EPiCS/soundgates | hardware/basic/ramp/ramp.vhd | 1 | 2,597 | -- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - ramp.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Ramp filter / envelope
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity ramp is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
incr2 : in signed(31 downto 0);
rmp : out signed(31 downto 0)
);
end ramp;
architecture Behavioral of ramp is
type states is (s_increasing, s_decreasing, s_exit);
signal state : states;
signal s_one : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_zero : signed (31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
begin
rmp <= x;
CALC_RAMP : process (clk, x, incr, rst)
begin
if rst = '1' then
x <= to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
state <= s_increasing;
else
if rising_edge(clk) then
if ce = '1' then
case state is
when s_increasing =>
x <= x + incr;
if x > s_one then
state <= s_decreasing;
end if;
when s_decreasing =>
x <= x - incr2;
if x < s_zero then
state <= s_exit;
end if;
when s_exit =>
--
end case;
end if;
end if;
end if;
end process;
end Behavioral;
| mit | a609a3de729b2a374dbb8f96f41f82b6 | 0.375433 | 3.830383 | false | false | false | false |
IslamKhaledH/ArchitecturePorject | Project/AddSubIncDec.vhd | 1 | 957 | Library ieee;
Use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
ENTITY AddSubIncDec IS
port(
R1,R2: in std_logic_vector(15 downto 0);
OutPut : out std_logic_vector(15 downto 0);
OpCode :in std_logic_vector(4 downto 0);
--Z: out std_logic;
--V: out std_logic;
C: out std_logic
--N: out std_logic
);
END AddSubIncDec;
Architecture archi of AddSubIncDec is
Component my_nadder is
PORT (a, b : in std_logic_vector(15 downto 0) ;
s : out std_logic_vector(15 downto 0);
cout : out std_logic);
end component;
signal tmpR1 : std_logic_vector(15 downto 0);
signal tmpR2 : std_logic_vector(15 downto 0);
signal TempOut : std_logic_vector(15 downto 0);
begin
tmpR1 <= R1 ;
tmpR2 <= R2 when OpCode = "00010" else
-R2 when OpCode = "00011" else
"0000000000000001" when OpCode = "10010" else
(others => '1') when OpCode = "10011";
F : my_nadder port map(tmpR1,tmpR2,TempOut,C);
OutPut <= TempOut;
end archi; | mit | ebfef30b17c6f994198dca4c082c60d7 | 0.676071 | 2.831361 | false | false | false | false |
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