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jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure_call/rule_003_test_input.fixed_last_close_paren__add_new_line.vhd | 1 | 843 |
architecture rtl of fifo is
begin
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow
);
connect_ports(
port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow
);
connect_ports(port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
connect_ports(port_1 => data, port_2 => enable, port_3 => overflow, port_4 => underflow
);
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
connect_ports
(
port_1 => data
,
port_2 => enable,
port_3 => overflow
,
port_4 => underflow
);
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
end architecture;
| gpl-3.0 | 71ecc47e6bf653fde8ff31e9959e6ddd | 0.567023 | 3.318898 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/c16/Board_cpu.vhd | 1 | 3,945 | --
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, change pin assignments in this file.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_pack.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity board_cpu is
PORT ( CLK40 : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
CLK_OUT : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
ENABLE_N : out STD_LOGIC;
DEACTIVATE_N : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(14 downto 0);
XM_CE_N : out STD_LOGIC;
XM_OE_N : out STD_LOGIC;
XM_WE_N : inout STD_LOGIC;
XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0)
);
end board_cpu;
architecture behavioral of board_cpu is
COMPONENT cpu
PORT( CLK_I : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR( 7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
END COMPONENT;
signal XM_WDAT : std_logic_vector( 7 downto 0);
signal XM_RDAT : std_logic_vector( 7 downto 0);
signal MEM_T : std_logic;
signal XM_WE : std_logic;
signal WE_N : std_logic;
signal DEL_WE_N : std_logic;
signal XM_CE : std_logic;
signal LCLK : std_logic;
begin
cp: cpu
PORT MAP( CLK_I => CLK40,
SWITCH => SWITCH,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
XM_ADR(14 downto 0) => XM_ADR,
XM_ADR(15) => open,
XM_RDAT => XM_RDAT,
XM_WDAT => XM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SEG1 => SEG1,
SEG2 => SEG2,
LED => LED
);
ENABLE_N <= '0';
DEACTIVATE_N <= '1';
CLK_OUT <= LCLK;
MEM_T <= DEL_WE_N; -- active low
WE_N <= not XM_WE;
XM_OE_N <= XM_WE;
XM_CE_N <= not XM_CE;
p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7));
p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0));
p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6));
p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1));
p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5));
p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2));
p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4));
p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3));
p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N);
process(CLK40)
begin
if (rising_edge(CLK40)) then
LCLK <= not LCLK;
end if;
end process;
end behavioral;
| gpl-3.0 | 0c94671d8e6d57e7485942948ff24051 | 0.524715 | 2.707618 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/blk_mem_gen_v8_0/simulation/blk_mem_gen_v8_0.vhd | 2 | 211,841 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: BLK_MEM_GEN_v8_0.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_0 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_0;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_0 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
--######################################################################################################
--######################################################################################################
--######################################################################################################
--######################################################################################################
--######################################################################################################
--######################################################################################################
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (BLK_MEM_GEN_v8_0) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_v8_0_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_0_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF BLK_MEM_GEN_v8_0_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (BLK_MEM_GEN_v8_0_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BLK_MEM_GEN_v8_0_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_0_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF BLK_MEM_GEN_v8_0_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY BLK_MEM_GEN_v8_0_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_0";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END BLK_MEM_GEN_v8_0_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF BLK_MEM_GEN_v8_0_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT BLK_MEM_GEN_v8_0_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_0_output_stage;
COMPONENT BLK_MEM_GEN_v8_0_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_0_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 2 ns;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
reg_a : BLK_MEM_GEN_v8_0_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => ENA,
REGCE => REGCEA,
DIN => memory_out_a,
DOUT => DOUTA,
SBITERR_IN => '0',
DBITERR_IN => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN => (OTHERS => '0'),
RDADDRECC => OPEN
);
-- Port B
reg_b : BLK_MEM_GEN_v8_0_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => ENB,
REGCE => REGCEB,
DIN => memory_out_b,
DOUT => doutb_i,
SBITERR_IN => sbiterr_in,
DBITERR_IN => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN => rdaddrecc_in,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: BLK_MEM_GEN_v8_0_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_0 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_0";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_0;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF BLK_MEM_GEN_v8_0 IS
COMPONENT BLK_MEM_GEN_v8_0_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_0";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT BLK_MEM_GEN_v8_0_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_0 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_0;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: BLK_MEM_GEN_v8_0_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: BLK_MEM_GEN_v8_0_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => rsta_in,
ENA => ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB,
ENB => ENB,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_0
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: BLK_MEM_GEN_v8_0_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => C_RST_TYPE,
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| bsd-2-clause | b4eaf6f7a4d6ce697517ce1999e701ca | 0.508853 | 3.557065 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_004_test_input.fixed.vhd | 1 | 1,041 |
architecture ARCH of ENTITY is
begin
-- Passing
PROC_2 : process (a) is
begin
a <= b or -- c = '2';
c or
d = '1';
c1 <= d;
e12 <= f and g and h
or i and j;
case CASE_LOGIC is
when a = 1 =>
a <= b or
c and
d = '1';
when b = 1 =>
if a = 1 then
c12 <= d or e or
f and g;
e1 <= f and x or y;
end if;
end case;
a <=
b;
end process PROC_2;
-- Violations
PROC_2 : process (a) is
begin
a <= b or -- c = '2';
c or
d = '1';
c1 <= d;
e12 <= f and g and h
or i and j;
case CASE_LOGIC is
when a = 1 =>
a <= b or
c and
d = '1';
when b = 1 =>
if a = 1 then
c12 <= d or e or
f and g;
e1 <= f and x or y;
end if;
end case;
a <=
b;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | 2d967e8cd078fbbfd8bae3b4761702b0 | 0.354467 | 3.47 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_002_test_input.vhd | 1 | 417 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | b88933a227ab78f02127f1a28e7b4114 | 0.47482 | 3.336 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/spi_master.fixed.vhd | 1 | 43,109 | -----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI master interface, implemented in one single entity.
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
--
-- SPI CLOCK GENERATION
-- ====================
--
-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
-- SPI_2X clock, which is 2x the desired SCK frequency.
-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
-- by combinatorial clock dividers outputs.
-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
--
-- PARALLEL WRITE INTERFACE
-- ========================
-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
-- enters idle state and deasserts SSEL.
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
-- idle state, if a previously loaded data has already been transferred.
--
-- PARALLEL WRITE SEQUENCE
-- =======================
-- __ __ __ __ __ __ __
-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
-- _______
-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
--
--
-- PARALLEL READ INTERFACE
-- =======================
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ SEQUENCE
-- ======================
-- ______ ______ ______ ______
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
-- _ __ __ __ __ __ __ __ __
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
-- ____________
-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
-- -- on the 3rd 'pclk_i' rising edge.
--
--
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
-- of the interface, for full duplex operation.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
-- logic, based on generics, and do_valid_o signal.
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
entity SPI_MASTER is
generic (
N : positive := 32; -- 32bit serial word length is default
CPOL : std_logic := '0'; -- SPI mode selection (mode 0 default)
CPHA : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
PREFETCH : positive := 2; -- prefetch lookahead cycles
SPI_2X_CLK_DIV : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
port (
SCLK_I : in std_logic := 'X'; -- high-speed serial interface system clock
PCLK_I : in std_logic := 'X'; -- high-speed parallel interface system clock
RST_I : in std_logic := 'X'; -- reset core
---- serial interface ----
SPI_SSEL_O : out std_logic; -- spi bus slave select line
SPI_SCK_O : out std_logic; -- spi bus sck
SPI_MOSI_O : out std_logic; -- spi bus mosi output
SPI_MISO_I : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
DI_REQ_O : out std_logic; -- preload lookahead data request line
DI_I : in std_logic_vector(N - 1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
WREN_I : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
WR_ACK_O : out std_logic; -- write acknowledge
DO_VALID_O : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
DO_O : out std_logic_vector(N - 1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
SCK_ENA_O : out std_logic; -- debug: internal sck enable signal
SCK_ENA_CE_O : out std_logic; -- debug: internal sck clock enable signal
DO_TRANSFER_O : out std_logic; -- debug: internal transfer driver
WREN_O : out std_logic; -- debug: internal state of the wren_i pulse stretcher
RX_BIT_REG_O : out std_logic; -- debug: internal rx bit
STATE_DBG_O : out std_logic_vector(3 downto 0); -- debug: internal state register
CORE_CLK_O : out std_logic;
CORE_N_CLK_O : out std_logic;
CORE_CE_O : out std_logic;
CORE_N_CE_O : out std_logic;
SH_REG_DBG_O : out std_logic_vector(N - 1 downto 0) -- debug: internal shift register
);
end entity SPI_MASTER;
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture RTL of SPI_MASTER is
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing async RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinatorial stages
signal state_next : natural range N + 1 downto 0 := 0;
signal state_reg : natural range N + 1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector(N - 1 downto 0);
signal sh_reg : std_logic_vector(N - 1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector(N - 1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
signal ssel_ena_next : std_logic := '0';
signal ssel_ena_reg : std_logic := '0';
-- internal SCK enable control signals
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector(N - 1 downto 0);
signal do_buffer_reg : std_logic_vector(N - 1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
signal do_valid_a : std_logic := '0';
signal do_valid_b : std_logic := '0';
signal do_valid_c : std_logic := '0';
signal do_valid_d : std_logic := '0';
signal do_valid_next : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_reg -> di_req_o_reg pipeline
signal di_req_o_a : std_logic := '0';
signal di_req_o_b : std_logic := '0';
signal di_req_o_c : std_logic := '0';
signal di_req_o_d : std_logic := '0';
signal di_req_o_next : std_logic := '1';
signal di_req_o_reg : std_logic := '1';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert N >= 8
report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
severity FAILURE;
-- minimum prefetch lookahead check
assert PREFETCH >= 1
report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert PREFETCH <= N - 5
report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
severity FAILURE;
-- SPI_2X_CLK_DIV clock divider value must not be zero
assert SPI_2X_CLK_DIV > 0
report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- In order to preserve global clocking resources, the core clocking scheme is completely based
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
-- the spi clock generator and the input sampling clock.
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
SPI_2X_CE_GEN_PROC : process (SCLK_I) is
variable clk_cnt : integer range SPI_2X_CLK_DIV - 1 downto 0 := 0;
begin
if (SCLK_I'event and SCLK_I = '1') then
if (clk_cnt = SPI_2X_CLK_DIV - 1) then
spi_2x_ce <= '1';
clk_cnt := 0;
else
spi_2x_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process SPI_2X_CE_GEN_PROC;
-----------------------------------------------------------------------------------------------
-- generate the core antiphase clocks and clock enables from the 2x base CE.
CORE_CLOCK_GEN_PROC : process (SCLK_I) is
begin
if (SCLK_I'event and SCLK_I = '1') then
if (spi_2x_ce = '1') then
-- generate the 2 antiphase core clocks
core_clk <= core_n_clk;
core_n_clk <= not core_n_clk;
-- generate the 2 phase core clock enables
core_ce <= core_n_clk;
core_n_ce <= not core_n_clk;
else
core_ce <= '0';
core_n_ce <= '0';
end if;
end if;
end process CORE_CLOCK_GEN_PROC;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
SPI_SCK_CPOL_0_PROC : if CPOL = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate SPI_SCK_CPOL_0_PROC;
SPI_SCK_CPOL_1_PROC : if CPOL = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate SPI_SCK_CPOL_1_PROC;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
SAMP_CE_CPHA_0_PROC : if CPHA = '0' generate
begin
samp_ce <= core_ce;
end generate SAMP_CE_CPHA_0_PROC;
SAMP_CE_CPHA_1_PROC : if CPHA = '1' generate
begin
samp_ce <= core_n_ce;
end generate SAMP_CE_CPHA_1_PROC;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
FSM_CE_CPHA_0_PROC : if CPHA = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate FSM_CE_CPHA_0_PROC;
FSM_CE_CPHA_1_PROC : if CPHA = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate FSM_CE_CPHA_1_PROC;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
RX_BIT_PROC : process (SCLK_I, SPI_MISO_I) is
begin
if (SCLK_I'event and SCLK_I = '1') then
if (samp_ce = '1') then
rx_bit_reg <= SPI_MISO_I;
end if;
end if;
end process RX_BIT_PROC;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
OUT_TRANSFER_PROC : process (PCLK_I, do_transfer_reg, di_req_reg,
do_valid_a, do_valid_b, do_valid_d,
di_req_o_a, di_req_o_b, di_req_o_d) is
begin
if (PCLK_I'event and PCLK_I = '1') then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_a <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_b <= do_valid_a; -- feed it to a ripple chain of FFDs
do_valid_c <= do_valid_b;
do_valid_d <= do_valid_c;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_a <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_b <= di_req_o_a; -- feed it to a ripple chain of FFDs
di_req_o_c <= di_req_o_b;
di_req_o_d <= di_req_o_c;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_a and do_valid_b and not do_valid_d;
di_req_o_next <= di_req_o_a and di_req_o_b and not di_req_o_d;
end process OUT_TRANSFER_PROC;
-- parallel load input registers: data register and write enable
IN_TRANSFER_PROC : process (PCLK_I, WREN_I, wr_ack_reg) is
begin
-- registered data input, input register with clock enable
if (PCLK_I'event and PCLK_I = '1') then
if (WREN_I = '1') then
di_reg <= DI_I; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if (PCLK_I'event and PCLK_I = '1') then
if (WREN_I = '1') then -- wren_i is the sync preset for wren
wren <= '1';
elsif (wr_ack_reg = '1') then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process IN_TRANSFER_PROC;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
CORE_REG_PROC : process (SCLK_I) is
begin
-- FF registers clocked on rising edge and cleared on sync rst_i
if (SCLK_I'event and SCLK_I = '1') then
if (RST_I = '1') then -- sync reset
state_reg <= 0; -- only provide local reset for the state machine
elsif (fsm_ce = '1') then -- fsm_ce is clock enable for the fsm
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked synchronous to the fsm state
if (SCLK_I'event and SCLK_I = '1') then
if (fsm_ce = '1') then
sh_reg <= sh_next; -- shift register
ssel_ena_reg <= ssel_ena_next; -- spi select enable
do_buffer_reg <= do_buffer_next; -- registered output data buffer
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
if (SCLK_I'event and SCLK_I = '1') then
if (sck_ena_ce = '1') then
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
end if;
end if;
end process CORE_REG_PROC;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
CORE_COMBI_PROC : process (sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
SPI_MOSI_O <= sh_reg(N - 1); -- default to avoid latch inference
state_next <= state_reg; -- next state
case state_reg is
when (N + 1) => -- this state is to enable SSEL before SCK
SPI_MOSI_O <= sh_reg(N - 1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N) => -- deassert 'di_rdy' and stretch do_valid
SPI_MOSI_O <= sh_reg(N - 1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(N - 1 downto 1) <= sh_reg(N - 2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (N - 1) downto (PREFETCH + 3) => -- remove 'do_transfer' and shift bits
SPI_MOSI_O <= sh_reg(N - 1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
sh_next(N - 1 downto 1) <= sh_reg(N - 2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (PREFETCH + 2) downto 2 => -- raise prefetch 'di_req_o' signal
SPI_MOSI_O <= sh_reg(N - 1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(N - 1 downto 1) <= sh_reg(N - 2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
SPI_MOSI_O <= sh_reg(N - 1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(N - 1 downto 1) <= sh_reg(N - 2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
if (wren = '1') then -- load tx register if valid data present at di_i
state_next <= N; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
sck_ena_next <= '1'; -- SCK enabled
wr_ack_next <= '1'; -- acknowledge data in transfer
else
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 => -- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if (wren = '1') then -- load tx register if valid data present at di_i
SPI_MOSI_O <= di_reg(N - 1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= N + 1; -- start from idle: let one cycle for SSEL settling
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
SPI_MOSI_O <= sh_reg(N - 1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process CORE_COMBI_PROC;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
SPI_SSEL_O <= not ssel_ena_reg; -- active-low slave select line
DO_O <= do_buffer_reg; -- parallel data out
DO_VALID_O <= do_valid_o_reg; -- data out valid
DI_REQ_O <= di_req_o_reg; -- input data request for next cycle
WR_ACK_O <= wr_ack_reg; -- write acknowledge
-----------------------------------------------------------------------------------------------
-- SCK out logic: pipeline phase compensation for the SCK line
-----------------------------------------------------------------------------------------------
-- This is a MUX with an output register.
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
SPI_SCK_O_GEN_PROC : process (SCLK_I, sck_ena_reg, spi_clk, spi_clk_reg) is
begin
if (SCLK_I'event and SCLK_I = '1') then
if (sck_ena_reg = '1') then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= CPOL; -- when clock disabled, set to idle polarity
end if;
end if;
SPI_SCK_O <= spi_clk_reg; -- connect register to output
end process SPI_SCK_O_GEN_PROC;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
DO_TRANSFER_O <= do_transfer_reg;
STATE_DBG_O <= std_logic_vector(to_unsigned(state_reg, 4));
RX_BIT_REG_O <= rx_bit_reg;
WREN_O <= wren;
SH_REG_DBG_O <= sh_reg;
CORE_CLK_O <= core_clk;
CORE_N_CLK_O <= core_n_clk;
CORE_CE_O <= core_ce;
CORE_N_CE_O <= core_n_ce;
SCK_ENA_O <= sck_ena_reg;
SCK_ENA_CE_O <= sck_ena_ce;
end architecture RTL;
| gpl-3.0 | 717d24d96449365dea588d21bc4a71c7 | 0.489573 | 4.601238 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port_map/rule_007_test_input.fixed.vhd | 2 | 677 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map ( PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | a451a12c80a44a1c5e82bca8558b78b4 | 0.447563 | 2.654902 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_020_test_input.fixed.vhd | 1 | 421 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
CASE_LABEL : case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE ;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | 4fa7114fe54a92dc15ffcc1f91922b41 | 0.491686 | 3.289063 | false | false | false | false |
Yarr/Yarr-fw | rtl/tx-core/serial_port.vhd | 1 | 3,885 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Serial Port
-- # Outputs are synchronous to clk_i
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.board_pkg.all;
entity serial_port is
generic (
g_PORT_WIDTH : integer := 32
);
port (
-- Sys connect
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Input
enable_i : in std_logic;
data_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
idle_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
sync_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
sync_interval_i : in std_logic_vector(7 downto 0);
pulse_i : in std_logic_vector(g_PORT_WIDTH-1 downto 0);
pulse_interval_i : in std_logic_vector(15 downto 0);
data_valid_i : in std_logic;
-- Output
data_o : out std_logic;
data_read_o : out std_logic
);
end serial_port;
architecture behavioral of serial_port is
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
-- Signals
constant c_ZEROS : std_logic_vector(g_PORT_WIDTH-1 downto 0) := (others => '0');
signal bit_count : unsigned(log2_ceil(g_PORT_WIDTH) downto 0);
signal sreg : std_logic_vector(g_PORT_WIDTH-1 downto 0);
signal sync_cnt : unsigned(7 downto 0);
signal pulse_cnt : unsigned(15 downto 0);
signal bx_tick : std_logic;
begin
-- Serializer proc
serialize: process(clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
sreg <= (others => '0');
bit_count <= (others => '0');
data_read_o <= '0';
sync_cnt <= (others => '0');
pulse_cnt <= (others => '0');
data_o <= '0';
elsif rising_edge(clk_i) then
-- Output register
data_o <= sreg(g_PORT_WIDTH-1);
-- Priority encoder
-- 1. Input via data_i port (fifo/looper) [only when enabled]
-- 3. Autozero word [only when enabled]
-- 2. Sync word
-- 4. Idle
if (bit_count = g_PORT_WIDTH-1 and data_valid_i = '1' and enable_i = '1') then
sreg <= data_i;
data_read_o <= '1';
bit_count <= (others => '0');
sync_cnt <= sync_cnt + 1;
pulse_cnt <= pulse_cnt + 1;
elsif (bit_count = g_PORT_WIDTH-1 and pulse_cnt >= unsigned(pulse_interval_i) and (pulse_i /= c_ZEROS) and (enable_i = '1')) then --
sreg <= pulse_i;
bit_count <= (others => '0');
sync_cnt <= sync_cnt + 1;
pulse_cnt <= (others => '0');
elsif (bit_count = g_PORT_WIDTH-1 and sync_cnt >= unsigned(sync_interval_i) and (sync_i /= c_ZEROS)) then
sreg <= sync_i;
bit_count <= (others => '0');
sync_cnt <= (others => '0');
pulse_cnt <= pulse_cnt + 1;
--elsif (bit_count = g_PORT_WIDTH-1 and data_valid_i = '0') then
elsif (bit_count = g_PORT_WIDTH-1) then
sreg <= idle_i;
bit_count <= (others => '0');
sync_cnt <= sync_cnt + 1;
pulse_cnt <= pulse_cnt + 1;
else
sreg <= sreg(g_PORT_WIDTH-2 downto 0) & '0';
data_read_o <= '0';
bit_count <= bit_count + 1;
end if;
bx_tick <= '0';
if (bit_count mod c_TX_40_DIVIDER = 0) then
bx_tick <= '1';
end if;
end if;
end process serialize;
end behavioral;
| gpl-3.0 | bf2b0318f36ecd4f2342ea41e2bad4b2 | 0.496525 | 3.407895 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_009_smart_tabs_test_input.fixed_align_left_no_align_paren_no_align_when_no_wrap_at_when_no_align_else_yes.vhd | 1 | 2,012 |
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
| gpl-3.0 | df9c3116669c420964cc7312c54dc853 | 0.448807 | 3.678245 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_033_test_input.vhd | 1 | 569 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_ENTITY_INST : entity FIFO(rtl);
-- Violations below
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1:INST
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | da84129a99ffbd4d9939c6c4b18a1e05 | 0.490334 | 2.789216 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_016_test_input.vhd | 1 | 340 |
entity FIFO is
generic (
G_WIDTH : integer := 256; -- Comment
G_DEPTH : integer := 32 -- Comment
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(g_size: integer := 10;g_width : integer := 256;g_depth: integer := 32
);
port(
i_port1 : in std_logic;i_port2 : in std_logic
);
end entity FIFO;
| gpl-3.0 | 99b8b0f45bd9c87c1e4e26279df87ad6 | 0.6 | 3.17757 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_011_test_input.vhd | 1 | 1,579 |
architecture RTL of FIFO is
constant c_con1 : std_logic_vector(-1 to -4);
type t_typ1 is range -2 to -4;
begin
a <= b + c;
a <= b - c;
a <= b / c;
a <= b * c;
a <= b ** c;
a <= (b) + (c);
a <= (b) - (c);
a <= (b) / (c);
a <= (b) * (c);
a <= (b) ** (c);
-- violations below
a <= b+ c;
a <= b +c;
a <= b+c;
a <= b- c;
a <= b -c;
a <= b-c;
a <= b/ c;
a <= b /c;
a <= b/c;
a <= b* c;
a <= b *c;
a <= b*c;
a <= b** c;
a <= b **c;
a <= b**c;
a <= (b)+ (c);
a <= (b) +(c);
a <= (b)+(c);
a <= (b)- (c);
a <= (b) -(c);
a <= (b)-(c);
a <= (b)/ (c);
a <= (b) /(c);
a <= (b)/(c);
a <= (b)* (c);
a <= (b) *(c);
a <= (b)*(c);
a <= (b)** (c);
a <= (b) **(c);
a <= (b)**(c);
a(N-1 downto 0);
a(N+1 downto 0);
end architecture RTL;
architecture RTL of FIFO is
constant c_con2 : t_type := (
-900, -- comment 1
-901, -- comment 2
-902, -- comment 3
+903, -- comment 4
-904 -- comment 5
);
constant c_con3 : t_type := (
-12.36e-47,
45.67e+67,
58.6729e1093,
-2346.7921e90,
401e56
);
begin
end architecture RTL;
architecture RTL of FIFO is
begin
a(c + d) <= '0';
a(c - d) <= '0';
a(c / d) <= '0';
a(c * d) <= '0';
a(c ** d) <= '0';
a(c+ d) <= '0';
a(c- d) <= '0';
a(c/ d) <= '0';
a(c* d) <= '0';
a(c** d) <= '0';
a(c +d) <= '0';
a(c -d) <= '0';
a(c /d) <= '0';
a(c *d) <= '0';
a(c **d) <= '0';
a(c+d) <= '0';
a(c-d) <= '0';
a(c/d) <= '0';
a(c*d) <= '0';
a(c**d) <= '0';
end architecture RTL;
| gpl-3.0 | bd6ebe9b3e836eb0894d613a1b1efcce | 0.352755 | 2.128032 | false | false | false | false |
rjarzmik/mips_processor | Caches/cache_line_streamer.vhd | 1 | 11,685 | -------------------------------------------------------------------------------
-- Title : Cache line streaming to and from memory
-- Project : MIPS processor implementation, compatible MIPS-1
-------------------------------------------------------------------------------
-- File : cache_line_streamer.vhd
-- Author : Robert Jarzmik (Intel) <[email protected]>
-- Company :
-- Created : 2016-12-21
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Breaks a cache line into data pieces and either :
-- - refill a whole or partial cache line
-- - flush a whole or partial cache line
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-21 1.0 rjarzmik Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cache_defs.all;
entity cache_line_streamer is
generic (
ADDR_WIDTH : natural := 32;
DATA_WIDTH : natural := 32;
DATAS_PER_LINE_WIDTH : natural := 4
);
port (
clk : in std_logic;
rst : in std_logic;
i_creq : in cache_request_t;
o_cresp : out cache_response_t;
-- outer mem interface
o_memory_req : out std_logic;
o_memory_we : out std_logic;
o_memory_addr : out addr_t;
i_memory_rdata : in data_t;
o_memory_wdata : out data_t;
i_memory_done : in std_logic
);
end entity cache_line_streamer;
architecture str of cache_line_streamer is
-- Input signal aliases
alias i_req : cls_op is i_creq.req;
alias i_addr : addr_t is i_creq.addr;
alias i_flushed_cache_line : cache_line_t is i_creq.cline;
alias i_datas_select : cache_line_selector_t is i_creq.sel;
alias o_filled_cache_line : cache_line_t is o_cresp.cline;
alias o_done : std_logic is o_cresp.done;
signal o_busy : std_logic;
type state_t is (s_idle, s_refilling, s_flushing);
constant EMPTY_DATAS_IN_LINE : cache_line_selector_t := (others => '0');
function get_next_state(i_req : cls_op) return state_t is
begin
if i_req = cls_refill then
return s_refilling;
elsif i_req = cls_flush then
return s_flushing;
else
return s_idle;
end if;
end function get_next_state;
function get_memory_addr(refill_base_addr : addr_t;
refill_data_idx : natural range 0 to DATAS_PER_LINE - 1)
return addr_t is
begin
return std_logic_vector(unsigned(refill_base_addr) +
refill_data_idx * DATA_WIDTH / 8);
end function get_memory_addr;
function to_std_logic_vector(sel : cache_line_selector_t)
return std_logic_vector is
variable o : std_logic_vector(sel'length - 1 downto 0);
begin
for i in sel'range loop
o(i) := sel(i);
end loop;
return o;
end function to_std_logic_vector;
signal state : state_t := s_idle;
-- Refill signals
signal refill_datas : cache_line_selector_t;
signal refill_data_idx : natural range 0 to DATAS_PER_LINE - 1;
signal refill_done : boolean;
signal refill_base_addr : addr_t;
signal refill_cache_line : cache_line_t;
--- refill memory I/F
signal refill_memory_req : std_ulogic;
signal refill_memory_we : std_ulogic;
signal refill_memory_addr : addr_t;
signal refill_memory_wdata : data_t;
--- refill mask feeder
signal mf1_sclr : std_logic;
signal mf1_sdata : std_logic_vector(DATAS_PER_LINE - 1 downto 0);
signal mf1_data : std_logic_vector(DATAS_PER_LINE - 1 downto 0);
signal mf1_bclrena : std_logic;
signal mf1_bclr : natural range 0 to DATAS_PER_LINE - 1;
signal mf1_fbitset : natural range 0 to DATAS_PER_LINE - 1;
signal mf1_allclear : std_logic;
-- Flush signals
signal flush_datas : cache_line_selector_t;
signal flush_data_idx : natural range 0 to DATAS_PER_LINE - 1;
signal flush_done : boolean;
signal flush_base_addr : addr_t;
signal flush_cache_line : cache_line_t;
--- flush memory I/F
signal flush_memory_req : std_ulogic;
signal flush_memory_we : std_ulogic;
signal flush_memory_addr : addr_t;
signal flush_memory_wdata : data_t;
--- flush mask feeder
signal mf2_sclr : std_logic;
signal mf2_sdata : std_logic_vector(DATAS_PER_LINE - 1 downto 0);
signal mf2_data : std_logic_vector(DATAS_PER_LINE - 1 downto 0);
signal mf2_bclrena : std_logic;
signal mf2_bclr : natural range 0 to DATAS_PER_LINE - 1;
signal mf2_fbitset : natural range 0 to DATAS_PER_LINE - 1;
signal mf2_allclear : std_logic;
begin -- architecture str
o_cresp.rdy <= not o_busy;
o_cresp.sel <= (others => 'X');
mf1 : entity work.mask_feeder
generic map (
WIDTH => DATAS_PER_LINE)
port map (
clk => clk,
sclr => mf1_sclr,
sdata => mf1_sdata,
bclrena => mf1_bclrena,
bclr => mf1_bclr,
fbitset => mf1_fbitset,
allclear => mf1_allclear);
mf1_sclr <= '1' when i_req = cls_refill or rst = '1' else '0';
mf1_sdata <= to_std_logic_vector(i_datas_select) when rst = '0'
else (others => '0');
mf2 : entity work.mask_feeder
generic map (
WIDTH => DATAS_PER_LINE)
port map (
clk => clk,
sclr => mf2_sclr,
sdata => mf2_sdata,
bclrena => mf2_bclrena,
bclr => mf2_bclr,
fbitset => mf2_fbitset,
allclear => mf2_allclear);
mf2_sclr <= '1' when i_req = cls_flush or rst = '1' else '0';
mf2_sdata <= to_std_logic_vector(i_datas_select) when rst = '0'
else (others => '0');
controller : process(rst, clk, i_req, state, i_addr, i_flushed_cache_line,
refill_cache_line)
variable ns : state_t;
begin
if rst = '1' then
o_busy <= '1';
o_done <= '0';
state <= s_idle;
-- mf2_bclrena <= '0';
elsif rising_edge(clk) then
case state is
when s_idle =>
o_done <= '0';
if i_req = cls_refill then
state <= s_refilling;
refill_base_addr <= i_addr;
o_busy <= '1';
elsif i_req = cls_flush then
state <= s_flushing;
flush_base_addr <= i_addr;
flush_cache_line <= i_flushed_cache_line;
o_busy <= '1';
else
o_busy <= '0';
end if;
when s_refilling =>
if refill_done then
ns := get_next_state(i_req);
state <= ns;
o_done <= '1';
o_filled_cache_line <= refill_cache_line;
if ns = s_idle then o_busy <= '0'; else o_busy <= '1'; end if;
if ns = s_flushing then
flush_cache_line <= i_flushed_cache_line;
end if;
else
o_done <= '0';
o_busy <= '1';
end if;
when s_flushing =>
if flush_done then
ns := get_next_state(i_req);
state <= ns;
o_done <= '1';
if ns = s_idle then o_busy <= '0'; else o_busy <= '1'; end if;
if ns = s_flushing then
flush_cache_line <= i_flushed_cache_line;
end if;
else
o_done <= '0';
o_busy <= '1';
end if;
end case;
end if;
end process controller;
refiller : process(rst, clk, i_req, i_memory_done, mf1_allclear, mf1_bclr,
refill_base_addr, refill_memory_req, mf1_fbitset, state,
i_memory_rdata)
variable waiting_memory_rsp : std_logic := '0';
begin
if rst = '1'then
refill_done <= true;
refill_cache_line <= (others => (others => 'X'));
elsif rising_edge(clk) and state = s_refilling then
if (mf1_allclear = '1' and waiting_memory_rsp = '1')
or mf1_allclear = '0' then
-- True work
if waiting_memory_rsp = '1' and i_memory_done = '1' then
-- Memory response ready
refill_cache_line(refill_data_idx) <= i_memory_rdata;
end if;
if refill_memory_req = '1' then
waiting_memory_rsp := '1';
refill_data_idx <= mf1_fbitset;
elsif i_memory_done = '1' then
waiting_memory_rsp := '0';
end if;
end if;
elsif rising_edge(clk) and state /= s_refilling then
refill_cache_line <= (others => (others => 'X'));
end if;
if mf1_allclear = '1' or
(waiting_memory_rsp = '1' and i_memory_done = '0') then
refill_memory_req <= '0';
else
refill_memory_req <= '1';
end if;
mf1_bclrena <= refill_memory_req;
mf1_bclr <= mf1_fbitset;
refill_done <= mf1_allclear = '1' and i_memory_done = '1'
and waiting_memory_rsp = '0';
refill_memory_we <= '0';
refill_memory_addr <= get_memory_addr(refill_base_addr, mf1_fbitset);
refill_memory_wdata <= (others => 'X');
end process refiller;
flusher : process(rst, clk, i_req, i_memory_done, mf2_allclear, mf2_bclr, flush_base_addr,
flush_memory_req, mf2_fbitset, flush_data_idx, state,
flush_cache_line, flush_done)
variable waiting_memory_rsp : std_logic := '0';
variable ffirst_flush : std_ulogic := '1';
variable all_clear_r : std_logic;
begin
if rst = '1' then
flush_done <= true;
end if;
if flush_done then
flush_memory_req <= '0';
else
flush_memory_req <= '1';
end if;
mf2_bclrena <= flush_memory_req;
mf2_bclr <= mf2_fbitset;
flush_data_idx <= mf2_fbitset;
flush_done <= mf2_allclear = '1' and all_clear_r = '1' and i_memory_done = '1';
flush_memory_req <= not mf2_allclear and (i_memory_done or ffirst_flush);
flush_memory_we <= '1';
flush_memory_addr <= get_memory_addr(flush_base_addr, mf2_fbitset);
flush_memory_wdata <= flush_cache_line(flush_data_idx);
if rst = '1' then
elsif state = s_flushing and rising_edge(clk) then
all_clear_r := mf2_allclear;
if flush_done then
ffirst_flush := '1';
else
ffirst_flush := '0';
end if;
end if;
end process flusher;
with state select o_memory_req <=
'0' when s_idle,
refill_memory_req when s_refilling,
flush_memory_req when s_flushing;
with state select o_memory_we <=
'0' when s_idle,
refill_memory_we when s_refilling,
flush_memory_we when s_flushing;
with state select o_memory_addr <=
(others => 'X') when s_idle,
refill_memory_addr when s_refilling,
flush_memory_addr when s_flushing;
with state select o_memory_wdata <=
(others => 'X') when s_idle,
refill_memory_wdata when s_refilling,
flush_memory_wdata when s_flushing;
--o_memory_we <= std_logic;
--o_memory_addr <= std_logic_vector(ADDR_WIDTH - 1 downto 0);
--o_memory_wdata <= std_logic_vector(DATA_WIDTH - 1 downto 0);
end architecture str;
| gpl-3.0 | cce9ffb5f1f08be5fc4e61e3df882581 | 0.533504 | 3.400757 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/Debounce.vhd | 1 | 4,055 | ----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: James Ratner
--
-- Create Date: 19:42:08 11/28/2011
-- Design Name:
-- Module Name: FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This is a RET debouncer with both one-shot and pulse output.
-- The SIG is the signal to be debounced and the CLK is the system
-- clock. The level output remains asserted as long as the signal to
-- be debounced remains asserted once the signal is deemed "good" by
-- the debounce unit. The pulse output is a 2-clock wide signal
-- that is output once the input signal passes the debounce
-- qualifications.
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created: 03-12-2015
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ret_db_1shot is
Port ( CLK : in STD_LOGIC;
SIG : in STD_LOGIC;
PULSE : out STD_LOGIC;
LEVEL : out STD_LOGIC);
end ret_db_1shot;
architecture Behavioral of ret_db_1shot is
type state_type is (st_wait, st_count, st_hold);
signal PS, NS : state_type;
constant WAIT_COUNT : integer := 5; -- debounce wait counter
signal s_en : std_logic;
signal s_rco : std_logic;
signal s_one_shot_1 : std_logic;
signal s_one_shot_2 : std_logic;
begin
--------------------------------------------------
-- input FSM
--------------------------------------------------
sync_proc : process (CLK, NS)
begin
if (rising_edge(CLK)) then
PS <= NS;
end if;
end process sync_proc;
comb_proc : process (PS, s_rco, SIG)
begin
s_en <= '0';
LEVEL <= '0';
case PS is
when st_wait =>
s_en <= '0';
LEVEL <= '0';
if (SIG = '0') then
NS <= st_wait;
else
NS <= st_count;
end if;
when st_count =>
s_en <= '1';
LEVEL <= '0';
if (s_rco = '0') then
NS <= st_count;
elsif (s_RCO = '1' and SIG = '1') then
NS <= st_hold;
else
NS <= st_wait;
end if;
when st_hold =>
s_en <= '0';
LEVEL <= '1';
if (SIG = '0') then
NS <= st_wait;
else
NS <= st_hold;
end if;
when others =>
NS <= st_wait;
end case;
end process comb_proc;
--------------------------------------------------
--------------------------------------------------
-- debounce counter
--------------------------------------------------
process(CLK)
variable v_pulse_cnt : integer := 0;
begin
if (rising_edge(CLK)) then
if (s_en = '1') then
if (v_pulse_cnt = WAIT_COUNT) then
v_pulse_cnt := 0; -- reset pulse count
s_rco <= '1'; -- reset pulse flip flop
else
v_pulse_cnt := v_pulse_cnt + 1;
s_rco <= '0';
end if;
else -- reset count if s_en turns off
v_pulse_cnt := 0;
s_rco <= '0';
end if;
end if;
end process;
--------------------------------------------------
-- debounce counter
--------------------------------------------------
process(CLK, s_rco, SIG)
begin
if (rising_edge(CLK)) then
if (s_rco = '1' and SIG = '1') then
s_one_shot_1 <= '1';
s_one_shot_2 <= s_one_shot_1;
else
s_one_shot_1 <= '0';
s_one_shot_2 <= s_one_shot_1;
end if;
end if;
end process;
PULSE <= s_one_shot_2 or s_one_shot_1;
--------------------------------------------------
end Behavioral;
| mit | 1214711ef9c8e504c3f8fcba42cdbed1 | 0.415043 | 4.018831 | false | false | false | false |
kjellhar/axi_mmc | src/vhdl/mmc_cmd_if.vhd | 1 | 7,432 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 09:11:16 AM
-- Design Name:
-- Module Name: mmc_cmd_if - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use WORK.mmc_core_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mmc_cmd_if is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
mmc_cmd_i : in std_logic;
mmc_cmd_o : out std_logic;
send_cmd_trigger_i : in std_logic;
receive_cmd_trigger_i : in std_logic;
send_cmd_busy_o : out std_logic;
receive_cmd_busy_o : out std_logic;
crc7_calc_en_i : in std_logic;
response_i : in std_logic_vector (2 downto 0);
cmd_shift_outval_i : in std_logic_vector (47 downto 0);
cmd_shift_inval_o : out std_logic_vector (135 downto 0);
mmc_crc7_out_o : out std_logic_vector (6 downto 0)
);
end mmc_cmd_if;
architecture rtl of mmc_cmd_if is
component mmc_crc7 is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
enable : in std_logic;
serial_in : in std_logic;
crc7_out : out std_logic_vector (6 downto 0)
);
end component;
signal send_bit_counter : integer range 0 to 47 := 0;
signal receive_bit_counter : integer range 0 to 135 := 0;
signal cmd_shift_out : std_logic_vector (47 downto 0) := (others => '1');
signal cmd_shift_in : std_logic_vector (135 downto 0) := (others => '1');
signal send_cmd_busy : std_logic := '0';
signal receive_cmd_busy : std_logic := '0';
signal receive_wait_start : std_logic := '0';
signal send_cmd_crc : std_logic := '0';
signal receive_cmd_crc : std_logic := '0';
signal send_reset_crc : std_logic := '0';
signal receive_reset_crc : std_logic := '0';
signal reset_crc : std_logic;
signal crc7_en : std_logic := '0';
signal crc7_source : std_logic;
signal crc7_out : std_logic_vector (6 downto 0);
begin
cmd_shift_inval_o <= cmd_shift_in;
receive_cmd_busy_o <= receive_cmd_busy;
send_cmd_busy_o <= send_cmd_busy;
mmc_cmd_o <= cmd_shift_out (47);
mmc_crc7_out_o <= crc7_out;
--MMC CMD out
process
begin
wait until rising_edge(clk);
send_reset_crc <= '0';
if reset='1' then
send_bit_counter <= 0;
elsif clk_en='1' then
if send_cmd_trigger_i='1' and receive_cmd_busy='0' then
cmd_shift_out <= cmd_shift_outval_i;
send_bit_counter <= 47;
send_cmd_busy <= '1';
send_cmd_crc <= '1';
else
if send_bit_counter = 0 then
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
send_cmd_busy <= '0';
elsif send_bit_counter = 7 then
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
send_bit_counter <= send_bit_counter - 1;
send_reset_crc <= '1';
elsif send_bit_counter = 8 then
send_bit_counter <= send_bit_counter - 1;
send_cmd_crc <= '0';
if crc7_calc_en_i='1' then
cmd_shift_out (41 downto 0) <= (others => '1');
cmd_shift_out (47 downto 41) <= crc7_out;
else
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
end if;
else
cmd_shift_out <= cmd_shift_out (46 downto 0) & '1';
send_bit_counter <= send_bit_counter - 1;
send_cmd_busy <= '1';
end if;
end if;
end if;
end process;
-- MMC CMD in
process
begin
wait until rising_edge(clk);
if reset='1' then
receive_cmd_busy <= '0';
receive_bit_counter <= 0;
receive_wait_start <= '0';
elsif clk_en='1' then
if receive_cmd_trigger_i='1' and send_cmd_busy='0' then
receive_cmd_busy <= '1';
receive_wait_start <= '1';
if response_i=RESP_R2 then
receive_bit_counter <= 135;
receive_cmd_crc <='0';
else
receive_bit_counter <= 47;
receive_cmd_crc <='1';
end if;
elsif receive_wait_start='1' then
if mmc_cmd_i='0' then
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
receive_wait_start <= '0';
receive_reset_crc <= '0';
else
receive_reset_crc <= '1';
end if;
elsif receive_bit_counter=128 then
receive_cmd_crc <='1';
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
elsif receive_bit_counter=8 then
receive_cmd_crc <='0';
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
elsif receive_bit_counter=0 then
if receive_cmd_busy='1' then
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
receive_cmd_busy <= '0';
end if;
else
receive_bit_counter <= receive_bit_counter - 1;
cmd_shift_in <= cmd_shift_in (134 downto 0) & mmc_cmd_i;
end if;
end if;
end process;
crc7_source <= cmd_shift_out (47) when send_cmd_busy='1' else
mmc_cmd_i when receive_cmd_busy='1' else
'0';
crc7_en <= send_cmd_crc or receive_cmd_crc;
reset_crc <= send_reset_crc or receive_reset_crc;
u_mmc_crc7 : mmc_crc7
Port map (
clk => clk,
clk_en => clk_en,
reset => reset_crc,
enable => crc7_en,
serial_in => crc7_source,
crc7_out => crc7_out
);
end rtl;
| mit | 8b46a0e32352cd42cc9fd7227a266421 | 0.455328 | 4.006469 | false | false | false | false |
Yarr/Yarr-fw | rtl/i2c-master/i2c_master_registers.vhd | 2 | 5,668 | -- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_registers is
port (
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_wacc : in std_logic;
i2c_al : in std_logic;
i2c_busy : in std_logic;
done : in std_logic;
irxack : in std_logic;
prer : out std_logic_vector(15 downto 0); -- clock prescale register
ctr : out std_logic_vector(7 downto 0); -- control register
txr : out std_logic_vector(7 downto 0); -- transmit register
cr : out std_logic_vector(7 downto 0); -- command register
sr : out std_logic_vector(7 downto 0) -- status register
);
end;
architecture arch of i2c_master_registers is
signal ctr_int : std_logic_vector(7 downto 0);
signal cr_int : std_logic_vector(7 downto 0);
signal al : std_logic; -- status register arbitration lost bit
signal rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
begin
-- generate prescale regisres, control registers, and transmit register
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case (wb_adr_i) is
when "000" => prer(7 downto 0) <= wb_dat_i;
when "001" => prer(15 downto 8) <= wb_dat_i;
when "010" => ctr_int <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when others => NULL;
end case;
end if;
end if;
end process;
ctr <= ctr_int;
-- generate command register (special case)
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
cr_int <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
cr_int <= (others => '0');
elsif (wb_wacc = '1') then
if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
cr_int <= wb_dat_i;
end if;
else
if ((done = '1') OR (i2c_al = '1')) then
cr_int(7 downto 4) <= "0000"; -- clear command b
end if; -- or when aribitr
cr_int(2 downto 1) <= "00"; -- reserved bits
cr_int(0) <= '0'; -- clear IRQ_ACK b
end if;
end if;
end process;
cr <= cr_int;
-- generate status register block + interrupt request signal
-- each output will be assigned to corresponding sr register locations on top level
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al OR (al AND NOT(cr_int(7)));
rxack <= irxack;
tip <= (cr_int(5) OR cr_int(4));
irq_flag <= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
end if;
end if;
end process;
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= "000"; -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end arch;
| gpl-3.0 | 162dd29cf9a7042aa5578b05c0a7ec24 | 0.48024 | 3.353846 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_008_test_input.fixed_new_line_after_assign_yes.vhd | 1 | 360 |
architecture RTL of FIFO is
begin
process
begin
-- These are passing
a <=
b or
d;
a <=
'0' when c = '0' else
'1' when d = '1' else
'Z';
-- Failing variations
a <=
b or
d;
a <=
'0' when c = '0' else
'1' when d = '1' else
'Z';
end process;
end architecture RTL;
| gpl-3.0 | a7a1083545b0e004ec7bbbf4facd9379 | 0.438889 | 3.302752 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/IMask.vhd | 1 | 1,126 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:02:48 11/30/2015
-- Design Name:
-- Module Name: IMask - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IMask is
Port ( i_SET : in STD_LOGIC;
I_CLR : in STD_LOGIC;
clk : in STD_LOGIC;
oot : out STD_LOGIC);
end IMask;
architecture Behavioral of IMask is
signal s_oot: std_logic;
begin
---------------------------------------------
process(i_set, I_CLR, CLK, s_oot)
begin
if (rising_edge(clk)) then
if (I_CLR = '1') then
s_oot <= '0';
elsif (I_SET = '1') then
s_oot <= '1';
end if;
end if;
end process;
---------------------------------------------
oot <= s_oot;
end Behavioral;
| mit | b6fe8ac600c7f460d9fe9a4cdd15715e | 0.416519 | 3.608974 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_009_test_input.vhd | 1 | 407 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : inst1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | fe1644188374c7dee3b51fe51f1aeb0d | 0.481572 | 2.787671 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_016_test_input.fixed_first_paren_new_line_false.vhd | 1 | 2,595 |
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array := (
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array := (
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"); -- Comment
begin
end architecture rtl;
| gpl-3.0 | b398bf996af055808e6e7aef58977d99 | 0.47553 | 2.86108 | false | false | false | false |
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| mit | 694a9584be842415904c13b336e2b09a | 0.923881 | 1.878695 | false | false | false | false |
Logistic1994/CPU | module_PC.vhd | 1 | 2,283 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:11:18 05/11/2015
-- Design Name:
-- Module Name: module_PC - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_STD.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_PC is
port (
clk_PC: in std_logic; -- ʱÖÓ
nreset: in std_logic; -- È«¾Ö¸´Î»ÐźÅ
nLD_PC: in std_logic; -- µØÖ·¸üÐÂ
M_PC: in std_logic; -- PC¼ÓÒ»
nPCH: in std_logic; -- PCÊä³öµ½×ÜÏߵĿØÖÆÐźÅ
nPCL: in std_logic; -- PCÊä³öµ½×ÜÏߵĿØÖÆÐźÅ
PC: in std_logic_vector(11 downto 0); -- 12λµÄPC
ADDR: out std_logic_vector(11 downto 0); -- ROM¶ÁµØÖ·Êä³ö
datao: out std_logic_vector(7 downto 0);
do: out std_logic); -- PCÊýÖµÊä³öµ½Êý¾Ý×ÜÏß
end module_PC;
architecture Behavioral of module_PC is
signal thePC: std_logic_vector(11 downto 0);
begin
ADDR <= thePC; -- ·ÅÔÚÕâ¸öµØ·½ÊÇ׼ȷµÄ£¬ÒòΪֻҪthePCÒ»±ä»¯£¬ÄÇôADDR¾Í»áÁ¢¼´·¢Éú±ä»¯
process(clk_PC, nreset)
begin
if nreset = '0' then
thePC <= X"000";
elsif rising_edge(clk_PC) then
-- ¼ÓÒ»²¢ÇÒË͵½µØÖ·×ÜÏßÉÏ
if M_PC = '1' then
if thePC = X"FFF" then
thePC <= X"000";
else
thePC <= std_logic_vector(unsigned(thePC) + 1);
end if;
datao <= (others => 'Z');
do <= '0';
-- ÔØÈëеØÖ·²¢ÇÒË͵½µØÖ·×ÜÏßÉÏÈ¥
elsif nLD_PC = '0' then
thePC <= PC;
datao <= (others => 'Z');
do <= '0';
-- Êä³öµ½Êý¾Ý×ÜÏßÉÏÈ¥
elsif nPCH = '0' then
datao(7 downto 4) <= X"0";
datao(3 downto 0) <= thePC(11 downto 8);
do <= '1';
elsif nPCL = '0' then
datao <= thePC(7 downto 0);
do <= '1';
else
datao <= (others => 'Z');
do <= '0';
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | fe9ab40565e4cd2543c460fe7d1e88e1 | 0.574682 | 2.663944 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port/rule_012_test_input.vhd | 1 | 747 |
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic := '0';
I_DATA : out std_logic_vector(31 downto 0):=(others=>'0');
I_RD_EN : in std_logic := '1';
O_DATA : out std_logic_vector(31 downto 0):=(others => '1')
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic := '0';-- COmment
I_DATA : out std_logic_vector(31 downto 0):=(others=>'0'); -- Comment
I_RD_EN : in std_logic := '1'; -- Comment
O_DATA : out std_logic_vector(31 downto 0):=(others => '1') -- Comment
);
end entity FIFO;
| gpl-3.0 | 806f1814a0423834abad617593c0d941 | 0.566265 | 2.808271 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port_map/rule_002_test_input.fixed_upper.vhd | 1 | 585 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
end architecture ARCH;
| gpl-3.0 | debc1c3e00acd387ca04b6d8ae35f6c1 | 0.492308 | 2.683486 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/code_examples/PIC.vhd | 1 | 9,940 | ----------------------------------------------------------------------------
---- Create Date: 00:12:45 10/23/2010
---- Design Name: pic
---- Project Name: PIC
---- Description:
---- A Programmable Interrupt Controller which can handle upto 8 ----
---- level triggered interrupts.The operating modes available are ----
---- polling fixed priority modes. ---- ----
----------------------------------------------------------------------------
---- ----
---- This file is a part of the pic project at ----
---- http://www.opencores.org/ ----
---- ----
---- Author(s): ----
---- Vipin Lal, [email protected] ----
---- ----
----------------------------------------------------------------------------
---- ----
---- Copyright (C) 2010 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PIC is
port( CLK_I : in std_logic; --Clock.
RST_I : in std_logic; --Reset
IR : in unsigned(7 downto 0); --Interrupt requests from peripherals.
DataBus : inout unsigned(7 downto 0); --Data bus between processor PIC.
INTR_O : out std_logic; --Interrupt Request pin of processor.
INTA_I : in std_logic --Interrupt ack.
);
end PIC;
architecture Behavioral of PIC is
type state_type is (reset_s,get_commands,jump_int_method,start_polling,tx_int_info_polling,ack_ISR_done,
ack_txinfo_rxd,start_priority_check,tx_int_info_priority,ack_txinfo_rxd_priority,ack_ISR_done_pt);
signal next_s : state_type :=reset_s;
signal int_type : unsigned(1 downto 0):="01";
signal int_index,count_cmd : integer := 0;
type prior_table is array (0 to 7) of unsigned(2 downto 0);
signal pt : prior_table := (others => (others => '0'));
signal int_pt : unsigned(2 downto 0):="000";
signal flag,flag1 : std_logic := '0'; --These flags are used for timing purposes.
begin
process(CLK_I,RST_I)
begin
if( RST_I = '1') then
next_s <= reset_s;
elsif( rising_edge(CLK_I) ) then
flag <= INTA_I;
case next_s is
when reset_s =>
--initialze signals to zero.
flag <= '0';
flag1 <= '0';
int_type <= "00";
int_index <= 0;
count_cmd <= 0;
int_pt <= "000";
pt <= (others => (others => '0'));
if( RST_I = '0' ) then
next_s <= get_commands;
else
next_s <= reset_s;
end if;
DataBus <= (others => 'Z');
when get_commands => --Get commands and operating mode from the processor.
if( DataBus(1 downto 0) = "01" ) then
int_type <= "01";
next_s <= jump_int_method;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 0) then
pt(0) <= DataBus(7 downto 5);
pt(1) <= DataBus(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 1) then
pt(2) <= DataBus(7 downto 5);
pt(3) <= DataBus(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 2) then
pt(4) <= DataBus(7 downto 5);
pt(5) <= DataBus(4 downto 2);
count_cmd <= count_cmd + 1;
next_s <= get_commands;
elsif( DataBus(1 downto 0) = "10" and count_cmd = 3) then
pt(6) <= DataBus(7 downto 5);
pt(7) <= DataBus(4 downto 2);
count_cmd <= 0;
int_type <= "10";
next_s <= jump_int_method;
else
next_s <= get_commands;
end if;
when jump_int_method => --Check which method is used to determine the interrupts.
flag <= '0';
flag1 <= '0';
int_index <= 0;
count_cmd <= 0;
int_pt <= "000";
if( int_type = "01" ) then
next_s <= start_polling; --Polling method for checking the interrupts.
elsif( int_type = "10" ) then
next_s <= start_priority_check; --Fixed priority scheme.
else
next_s <= reset_s; --Error if no method is specified.
end if;
DataBus <= (others => 'Z');
when start_polling => --Check for interrupts(one by one) using polling method.
if( IR(int_index) = '1' ) then
INTR_O <= '1';
next_s <= tx_int_info_polling;
else
INTR_O <= '0';
end if;
if( int_index = 7 ) then
int_index <= 0;
else
int_index <= int_index+1;
end if;
DataBus <= (others => 'Z');
when tx_int_info_polling => --Transmit interrupt information if an interrupt is found.
if( INTA_I = '0' ) then
INTR_O <= '0';
end if;
if( flag = '0' ) then
DataBus <= "01011" & to_unsigned( (int_index-1),3); --MSB "01011" is for matching purpose.
flag1 <= '1';
else
flag1 <= '0';
end if;
if ( flag1 = '1' ) then
next_s <= ack_txinfo_rxd;
if( INTA_I = '0' ) then
DataBus <= (others => 'Z');
end if;
end if;
when ack_txinfo_rxd => --ACK send by processor to tell PIC that interrupt info is received correctly.
if( INTA_I <= '0' ) then
next_s <= ack_ISR_done;
DataBus <= (others => 'Z');
end if;
when ack_ISR_done => --Wait for the ISR for the particular interrupt to get over.
if( INTA_I = '0' and DataBus(7 downto 3) = "10100" and DataBus(2 downto 0) = to_unsigned(int_index-1,3) ) then
next_s <= start_polling;
else
next_s <= ack_ISR_done;
end if;
when start_priority_check => --Fixed priority method for interrupt handling.
--Interrupts are checked based on their priority.
if( IR(to_integer(pt(0))) = '1' ) then
int_pt <= pt(0);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(1))) = '1' ) then
int_pt <= pt(1);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(2))) = '1' ) then
int_pt <= pt(2);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(3))) = '1' ) then
int_pt <= pt(3);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(4))) = '1' ) then
int_pt <= pt(4);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(5))) = '1' ) then
int_pt <= pt(5);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(6))) = '1' ) then
int_pt <= pt(6);
INTR_O <= '1';
next_s <= tx_int_info_priority;
elsif( IR(to_integer(pt(7))) = '1' ) then
int_pt <= pt(7);
INTR_O <= '1';
next_s <= tx_int_info_priority;
else
next_s <= start_priority_check;
end if;
DataBus <= (others => 'Z');
when tx_int_info_priority => --Transmit interrupt information if an interrupt is found.
if( INTA_I = '0' ) then
INTR_O <= '0';
end if;
if( flag = '0' ) then
DataBus <= "10011" & int_pt; --MSB "10011" is for matching purpose.
flag1 <= '1';
else
flag1 <= '0';
end if;
if ( flag1 = '1' ) then
next_s <= ack_txinfo_rxd_priority;
if( INTA_I = '0' ) then
DataBus <= (others => 'Z');
end if;
end if;
when ack_txinfo_rxd_priority => --ACK send by processor to tell PIC that interrupt info is received correctly.
if( INTA_I <= '0' ) then
next_s <= ack_ISR_done_pt;
DataBus <= (others => 'Z');
end if;
when ack_ISR_done_pt => --Wait for the ISR for the particular interrupt to get over.
if( INTA_I = '0' and DataBus(7 downto 3) = "01100" and DataBus(2 downto 0) = int_pt ) then
next_s <= start_priority_check;
elsif( DataBus(7 downto 3) /= "01100" or DataBus(2 downto 0) /= int_pt ) then
next_s <= reset_s; --Error.
else
next_s <= ack_ISR_done_pt;
end if;
when others =>
DataBus <= (others => 'Z');
end case;
end if;
end process;
end Behavioral;
| gpl-3.0 | 9ed74bac3c18aadffc8586d50e22fa78 | 0.491348 | 3.433506 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cntrl_strm.vhd | 1 | 21,786 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.proc_common_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity proc_common_v4_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => CNTRL_FIFO_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty
and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => m_axi_sg_aclk ,
ARST => skid_rst ,
skid_stop => mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1 : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
-- C_DEPTH => CNTRL_FIFO_DEPTH ,
-- C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
p_mm2s_stop_d1 <= '0';
p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1 <= mm2s_stop;
p_mm2s_stop_d1 <= mm2s_stop_reg;
p_mm2s_stop_d2 <= p_mm2s_stop_d1;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
CNTRL_SKID_BUF_I : entity axi_dma_v7_1.axi_dma_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
| bsd-2-clause | 7fc73bae311bf99e88157e8faa7a5e05 | 0.439273 | 4.372943 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/wrap_buff.vhd | 2 | 50,940 | `protect begin_protected
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35968)
`protect data_block
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`protect end_protected
| mit | 79cbb20162ce9b57f3edf4fb787f18e2 | 0.949804 | 1.820846 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_007_test_input.fixed_upper_with_lower_prefix_and_suffix.vhd | 1 | 1,897 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_suffix : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
| gpl-3.0 | 5b9b99f5e5784ea564553579962de525 | 0.573537 | 3.120066 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma.vhd | 1 | 126,821 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma.vhd
-- Description: This entity is the top level entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_dma.vhd
-- |- axi_dma_pkg.vhd
-- |- axi_dma_rst_module.vhd
-- |- axi_dma_reg_module.vhd
-- | |- axi_dma_lite_if.vhd
-- | |- axi_dma_register.vhd (mm2s)
-- | |- axi_dma_register.vhd (s2mm)
-- |- axi_dma_mm2s_mngr.vhd
-- | |- axi_dma_mm2s_sg_if.vhd
-- | |- axi_dma_mm2s_sm.vhd
-- | |- axi_dma_mm2s_cmdsts_if.vhd
-- | |- axi_dma_mm2s_cntrl_strm.vhd
-- | |- axi_dma_skid_buf.vhd
-- | |- axi_dma_strm_rst.vhd
-- |- axi_dma_s2mm_mngr.vhd
-- | |- axi_dma_s2mm_sg_if.vhd
-- | |- axi_dma_s2mm_sm.vhd
-- | |- axi_dma_s2mm_cmdsts_if.vhd
-- | |- axi_dma_s2mm_sts_strm.vhd
-- | |- axi_dma_skid_buf.vhd
-- |- axi_datamover_v3_00_a.axi_data_mover.vhd (FULL)
-- |- axi_dma_strm_rst.vhd
-- |- axi_dma_skid_buf.vhd
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library axi_sg_v4_1;
use axi_sg_v4_1.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.max2;
-------------------------------------------------------------------------------
entity axi_dma is
generic(
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 10;
-- Address width of the AXI Lite Interface
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
-- C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
-- Include or exclude MM2S data realignment engine (DRE)
-- 0 = Exclude MM2S DRE
-- 1 = Include MM2S DRE
C_MM2S_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on MM2S Read Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXI_MM2S_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2S Read Port
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Master AXI Stream Data Width for MM2S Channel
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_S2MM_SF : integer range 0 to 1 := 1;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_INCLUDE_S2MM_DRE : integer range 0 to 1 := 0;
-- Include or exclude S2MM data realignment engine (DRE)
-- 0 = Exclude S2MM DRE
-- 1 = Include S2MM DRE
C_S2MM_BURST_SIZE : integer range 2 to 256 := 16;
-- Maximum burst size per burst request on S2MM Write Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_M_AXI_S2MM_DATA_WIDTH : integer range 32 to 1024 := 32;
-- Master AXI Memory Map Data Width for MM2SS2MMWrite Port
C_S_AXIS_S2MM_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Slave AXI Stream Data Width for S2MM Channel
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
-- Enable CACHE support, primarily for MCDMA
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
-- Number of S2MM channels, primarily for MCDMA
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
-- Number of MM2S channels, primarily for MCDMA
C_FAMILY : string := "virtex7";
C_MICRO_DMA : integer range 0 to 1 := 0;
-- Target FPGA Device Family
C_INSTANCE : string := "axi_dma"
);
port (
s_axi_lite_aclk : in std_logic := '0' ; --
m_axi_sg_aclk : in std_logic := '0' ; --
m_axi_mm2s_aclk : in std_logic := '0' ; --
m_axi_s2mm_aclk : in std_logic := '0' ; --
-----------------------------------------------------------------------
-- Primary Clock CDMA
-----------------------------------------------------------------------
axi_resetn : in std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- AXI Lite Control Interface --
----------------------------------------------------------------------- --
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic := '0' ; --
s_axi_lite_awready : out std_logic ; --
-- s_axi_lite_awaddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_awaddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic := '0' ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic := '0' ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic := '0' ; --
s_axi_lite_arready : out std_logic ; --
-- s_axi_lite_araddr : in std_logic_vector --
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); --
s_axi_lite_araddr : in std_logic_vector --
(9 downto 0) := (others => '0'); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic := '0' ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
----------------------------------------------------------------------- --
-- AXI Scatter Gather Interface --
----------------------------------------------------------------------- --
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic := '0' ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic := '0' ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := "00" ; --
m_axi_sg_bvalid : in std_logic := '0' ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic := '0' ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_sg_rlast : in std_logic := '0'; --
m_axi_sg_rvalid : in std_logic := '0'; --
m_axi_sg_rready : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI MM2S Channel --
----------------------------------------------------------------------- --
-- Memory Map To Stream Read Address Channel --
m_axi_mm2s_araddr : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_mm2s_arvalid : out std_logic ; --
m_axi_mm2s_arready : in std_logic := '0'; --
--
-- Memory Map to Stream Read Data Channel --
m_axi_mm2s_rdata : in std_logic_vector --
(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0) := (others => '0'); --
m_axi_mm2s_rresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_mm2s_rlast : in std_logic := '0'; --
m_axi_mm2s_rvalid : in std_logic := '0'; --
m_axi_mm2s_rready : out std_logic ; --
--
-- Memory Map to Stream Stream Interface --
mm2s_prmry_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tvalid : out std_logic ; --
m_axis_mm2s_tready : in std_logic := '0'; --
m_axis_mm2s_tlast : out std_logic ; --
m_axis_mm2s_tuser : out std_logic_vector (3 downto 0) ; --
m_axis_mm2s_tid : out std_logic_vector (4 downto 0) ; --
m_axis_mm2s_tdest : out std_logic_vector (4 downto 0) ; --
--
-- Memory Map to Stream Control Stream Interface --
mm2s_cntrl_reset_out_n : out std_logic ; -- CR573702
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ; --
--
--
----------------------------------------------------------------------- --
-- AXI S2MM Channel --
----------------------------------------------------------------------- --
-- Stream to Memory Map Write Address Channel --
m_axi_s2mm_awaddr : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_s2mm_awvalid : out std_logic ; --
m_axi_s2mm_awready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Data Channel --
m_axi_s2mm_wdata : out std_logic_vector --
(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : out std_logic_vector --
((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : out std_logic ; --
m_axi_s2mm_wvalid : out std_logic ; --
m_axi_s2mm_wready : in std_logic := '0'; --
--
-- Stream to Memory Map Write Response Channel --
m_axi_s2mm_bresp : in std_logic_vector(1 downto 0) := "00"; --
m_axi_s2mm_bvalid : in std_logic := '0'; --
m_axi_s2mm_bready : out std_logic ; --
--
-- Stream to Memory Map Steam Interface --
s2mm_prmry_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_tvalid : in std_logic := '0'; --
s_axis_s2mm_tready : out std_logic ; --
s_axis_s2mm_tlast : in std_logic := '0'; --
s_axis_s2mm_tuser : in std_logic_vector (3 downto 0) := "0000" ; --
s_axis_s2mm_tid : in std_logic_vector (4 downto 0) := "00000" ; --
s_axis_s2mm_tdest : in std_logic_vector (4 downto 0) := "00000" ; --
--
-- Stream to Memory Map Status Steam Interface --
s2mm_sts_reset_out_n : out std_logic ; -- CR573702
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0) := (others => '0'); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0) := (others => '1'); --
s_axis_s2mm_sts_tvalid : in std_logic := '0'; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic := '0'; --
--
-- MM2S and S2MM Channel Interrupts --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic ; --
axi_dma_tstvec : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
);
end axi_dma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- The FREQ are needed only for ASYNC mode, for SYNC mode these are irrelevant
-- For Async, mm2s or s2mm >= sg >= lite
constant C_S_AXI_LITE_ACLK_FREQ_HZ : integer := 100000000;
-- AXI Lite clock frequency in hertz
constant C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- AXI MM2S clock frequency in hertz
constant C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- AXI S2MM clock frequency in hertz
constant C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000;
-- Scatter Gather clock frequency in hertz
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_string (value_in_1 : integer)
return string is
Variable max_value : string (1 to 5) := "00000";
begin
If (value_in_1 = 1) Then
max_value := "11100";
else
max_value := "11111";
End if;
Return (max_value);
end function funct_get_string;
-- -------------------------------------------------------------------
--
--
--
-- -------------------------------------------------------------------
-- -- Function
-- --
-- -- Function Name: funct_rnd2pwr_of_2
-- --
-- -- Function Description:
-- -- Rounds the input value up to the nearest power of 2 between
-- -- 128 and 8192.
-- --
-- -------------------------------------------------------------------
-- function funct_rnd2pwr_of_2 (input_value : integer) return integer is
--
-- Variable temp_pwr2 : Integer := 128;
--
-- begin
--
-- if (input_value <= 128) then
--
-- temp_pwr2 := 128;
--
-- elsif (input_value <= 256) then
--
-- temp_pwr2 := 256;
--
-- elsif (input_value <= 512) then
--
-- temp_pwr2 := 512;
--
-- elsif (input_value <= 1024) then
--
-- temp_pwr2 := 1024;
--
-- elsif (input_value <= 2048) then
--
-- temp_pwr2 := 2048;
--
-- elsif (input_value <= 4096) then
--
-- temp_pwr2 := 4096;
--
-- else
--
-- temp_pwr2 := 8192;
--
-- end if;
--
--
-- Return (temp_pwr2);
--
-- end function funct_rnd2pwr_of_2;
-- -------------------------------------------------------------------
--
--
--
--
--
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
constant skid_enable : string := (funct_get_string(0));
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
-- Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
-- (funct_get_max(4, 4)+2)
-- * C_M_AXI_MAX_BURST_LEN;
--
-- -- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- -- power of 2
-- Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
-- funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Scatter Gather Engine Configuration
-- Number of Fetch Descriptors to Queue
constant MCDMA : integer := (1 - C_ENABLE_MULTI_CHANNEL);
constant DESC_QUEUE : integer := (1*MCDMA);
constant STSCNTRL_ENABLE : integer := (C_SG_INCLUDE_STSCNTRL_STRM*MCDMA);
constant APPLENGTH_ENABLE : integer := (C_SG_USE_STSAPP_LENGTH*MCDMA);
constant C_SG_LENGTH_WIDTH_INT : integer := (C_SG_LENGTH_WIDTH*MCDMA + 23*C_ENABLE_MULTI_CHANNEL);
-- Comment the foll 2 line to disable queuing for McDMA and uncomment the 3rd and 4th lines
--constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
-- Number of Update Descriptors to Queue
--constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * C_SG_INCLUDE_DESC_QUEUE;
constant SG_FTCH_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of Update Descriptors to Queue
constant SG_UPDT_DESC2QUEUE : integer := ((DESC_QUEUE * 4)*MCDMA + (2*C_ENABLE_MULTI_CHANNEL)) * DESC_QUEUE;
-- Number of fetch words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_FETCH : integer := 8 + (5 * STSCNTRL_ENABLE);
-- Number of fetch words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_FETCH : integer := 8; -- Only need to fetch 1st 8wrds for s2mm
-- Number of update words per descriptor for channel 1 (MM2S)
constant SG_CH1_WORDS_TO_UPDATE : integer := 1; -- Only status needs update for mm2s
-- Number of update words per descriptor for channel 2 (S2MM)
constant SG_CH2_WORDS_TO_UPDATE : integer := 1 + (5 * STSCNTRL_ENABLE);
-- First word offset (referenced to descriptor beginning) to update for channel 1 (MM2S)
constant SG_CH1_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- First word offset (referenced to descriptor beginning) to update for channel 2 (MM2S)
constant SG_CH2_FIRST_UPDATE_WORD : integer := 7; -- status word in descriptor
-- Enable stale descriptor check for channel 1
constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- Enable stale descriptor check for channel 2
constant SG_CH2_ENBL_STALE_ERROR : integer := 1;
-- Width of descriptor fetch bus
constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- Width of descriptor update pointer bus
constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- Width of descriptor update status bus
constant S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33; -- IOC (1 bit) & DescStatus (32 bits)
-- Include SG Descriptor Updates
constant INCLUDE_DESC_UPDATE : integer := 1;
-- Include SG Interrupt Logic
constant INCLUDE_INTRPT : integer := 1;
-- Include SG Delay Interrupt
constant INCLUDE_DLYTMR : integer := 1;
-- Primary DataMover Configuration
-- DataMover Command / Status FIFO Depth
-- Note :Set maximum to the number of update descriptors to queue, to prevent lock up do to
-- update data fifo full before
--constant DM_CMDSTS_FIFO_DEPTH : integer := 1*C_ENABLE_MULTI_CHANNEL + (max2(1,SG_UPDT_DESC2QUEUE))*MCDMA;
constant DM_CMDSTS_FIFO_DEPTH : integer := max2(1,SG_UPDT_DESC2QUEUE);
constant DM_CMDSTS_FIFO_DEPTH_1 : integer := ((1-C_PRMRY_IS_ACLK_ASYNC)+C_PRMRY_IS_ACLK_ASYNC*DM_CMDSTS_FIFO_DEPTH);
-- DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- Enable indeterminate BTT on datamover when stscntrl stream not included or
-- when use status app rx length is not enable or when in Simple DMA mode.
constant DM_SUPPORT_INDET_BTT : integer := 1 - (STSCNTRL_ENABLE
* APPLENGTH_ENABLE
* C_INCLUDE_SG) - C_MICRO_DMA;
-- Indterminate BTT Mode additional status vector width
constant INDETBTT_ADDED_STS_WIDTH : integer := 24;
-- Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- DataMover status width - is based on mode of operation
constant DM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH
+ (DM_SUPPORT_INDET_BTT * INDETBTT_ADDED_STS_WIDTH);
-- DataMover outstanding address request fifo depth
constant DM_ADDR_PIPE_DEPTH : integer := 1;
-- AXI DataMover Full mode value
constant AXI_FULL_MODE : integer := 1;
-- AXI DataMover mode for MM2S Channel (0 if channel not included)
constant MM2S_AXI_FULL_MODE : integer := (C_INCLUDE_MM2S) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_MM2S;
-- AXI DataMover mode for S2MM Channel (0 if channel not included)
constant S2MM_AXI_FULL_MODE : integer := (C_INCLUDE_S2MM) * AXI_FULL_MODE + C_MICRO_DMA*C_INCLUDE_S2MM;
-- Minimum value required for length width based on burst size and stream dwidth
-- If user sets c_sg_length_width too small based on setting of burst size and
-- dwidth then this will reset the width to a larger mimimum requirement.
constant DM_BTT_LENGTH_WIDTH : integer := max2((required_btt_width(C_M_AXIS_MM2S_TDATA_WIDTH,
C_MM2S_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_MM2S),
(required_btt_width(C_S_AXIS_S2MM_TDATA_WIDTH,
C_S2MM_BURST_SIZE,
C_SG_LENGTH_WIDTH_INT)*C_INCLUDE_S2MM));
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_MM2S_INCLUDE_SF : integer := enable_snf(C_INCLUDE_MM2S_SF,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH);
-- Enable store and forward on datamover if data widths are mismatched (allows upsizers
-- to be instantiated) or when enabled by user.
constant DM_S2MM_INCLUDE_SF : integer := enable_snf(C_INCLUDE_S2MM_SF,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH);
-- Always allow datamover address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- Return correct freq_hz parameter depending on if sg engine is included
constant M_AXI_SG_ACLK_FREQ_HZ :integer := hertz_prmtr_select(C_INCLUDE_SG,
C_S_AXI_LITE_ACLK_FREQ_HZ,
C_M_AXI_SG_ACLK_FREQ_HZ);
-- Scatter / Gather is always configure for synchronous operation for AXI DMA
constant SG_IS_SYNCHRONOUS : integer := 0;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi_lite_aclk : std_logic := '1';
signal axi_sg_aclk : std_logic := '1';
signal m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard)
signal dm_m_axi_sg_aresetn : std_logic := '1'; -- SG Reset on sg aclk domain (Soft/Hard) (Raw)
signal m_axi_mm2s_aresetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal m_axi_s2mm_aresetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)(Raw)
signal mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg aclk domain (Soft/Hard)
signal s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg aclk domain (Soft/Hard)
signal mm2s_prmry_resetn : std_logic := '1'; -- MM2S Channel Reset on s2mm aclk domain (Soft/Hard)
signal s2mm_prmry_resetn : std_logic := '1'; -- S2MM Channel Reset on s2mm aclk domain (Soft/Hard)
signal axi_lite_reset_n : std_logic := '1'; -- AXI Lite Interface Reset (Hard Only)
signal m_axi_sg_hrdresetn : std_logic := '1'; -- AXI Lite Interface Reset on SG clock domain (Hard Only)
signal dm_mm2s_scndry_resetn : std_logic := '1'; -- MM2S Channel Reset on sg domain (Soft/Hard)(Raw)
signal dm_s2mm_scndry_resetn : std_logic := '1'; -- S2MM Channel Reset on sg domain (Soft/Hard)(Raw)
-- Register Module Signals
signal mm2s_halted_clr : std_logic := '0';
signal mm2s_halted_set : std_logic := '0';
signal mm2s_idle_set : std_logic := '0';
signal mm2s_idle_clr : std_logic := '0';
signal mm2s_dma_interr_set : std_logic := '0';
signal mm2s_dma_slverr_set : std_logic := '0';
signal mm2s_dma_decerr_set : std_logic := '0';
signal mm2s_ioc_irq_set : std_logic := '0';
signal mm2s_dly_irq_set : std_logic := '0';
signal mm2s_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal mm2s_new_curdesc_wren : std_logic := '0';
signal mm2s_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_tailpntr_updated : std_logic := '0';
signal mm2s_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal mm2s_length_wren : std_logic := '0';
signal mm2s_smpl_interr_set : std_logic := '0';
signal mm2s_smpl_slverr_set : std_logic := '0';
signal mm2s_smpl_decerr_set : std_logic := '0';
signal mm2s_smpl_done : std_logic := '0';
signal mm2s_packet_sof : std_logic := '0';
signal mm2s_packet_eof : std_logic := '0';
signal mm2s_all_idle : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal mm2s_dlyirq_dsble : std_logic := '0'; -- CR605888
signal s2mm_halted_clr : std_logic := '0';
signal s2mm_halted_set : std_logic := '0';
signal s2mm_idle_set : std_logic := '0';
signal s2mm_idle_clr : std_logic := '0';
signal s2mm_dma_interr_set : std_logic := '0';
signal s2mm_dma_slverr_set : std_logic := '0';
signal s2mm_dma_decerr_set : std_logic := '0';
signal s2mm_ioc_irq_set : std_logic := '0';
signal s2mm_dly_irq_set : std_logic := '0';
signal s2mm_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal s2mm_new_curdesc_wren : std_logic := '0';
signal s2mm_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_tailpntr_updated : std_logic := '0';
signal s2mm_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_length_wren : std_logic := '0';
signal s2mm_bytes_rcvd : std_logic_vector(C_SG_LENGTH_WIDTH_INT-1 downto 0) := (others => '0');
signal s2mm_bytes_rcvd_wren : std_logic := '0';
signal s2mm_smpl_interr_set : std_logic := '0';
signal s2mm_smpl_slverr_set : std_logic := '0';
signal s2mm_smpl_decerr_set : std_logic := '0';
signal s2mm_smpl_done : std_logic := '0';
signal s2mm_packet_sof : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
signal s2mm_all_idle : std_logic := '0';
signal s2mm_error : std_logic := '0';
signal s2mm_dlyirq_dsble : std_logic := '0'; -- CR605888
signal mm2s_stop : std_logic := '0';
signal s2mm_stop : std_logic := '0';
signal ftch_error : std_logic := '0';
signal ftch_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_error : std_logic := '0';
signal updt_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
--*********************************
-- MM2S Signals
--*********************************
-- MM2S DMA Controller Signals
signal mm2s_desc_flush : std_logic := '0';
signal mm2s_ftch_idle : std_logic := '0';
signal mm2s_updt_idle : std_logic := '0';
signal mm2s_updt_ioc_irq_set : std_logic := '0';
signal mm2s_irqthresh_wren : std_logic := '0';
signal mm2s_irqdelay_wren : std_logic := '0';
signal mm2s_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG MM2S Descriptor Fetch AXI Stream IN
signal m_axis_mm2s_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid_new : std_logic := '0';
signal m_axis_mm2s_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_ftch_tvalid : std_logic := '0';
signal m_axis_mm2s_ftch_tready : std_logic := '0';
signal m_axis_mm2s_ftch_tlast : std_logic := '0';
-- SG MM2S Descriptor Update AXI Stream Out
signal s_axis_mm2s_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtptr_tvalid : std_logic := '0';
signal s_axis_mm2s_updtptr_tready : std_logic := '0';
signal s_axis_mm2s_updtptr_tlast : std_logic := '0';
signal s_axis_mm2s_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_mm2s_updtsts_tvalid : std_logic := '0';
signal s_axis_mm2s_updtsts_tready : std_logic := '0';
signal s_axis_mm2s_updtsts_tlast : std_logic := '0';
-- DataMover MM2S Command Stream Signals
signal s_axis_mm2s_cmd_tvalid_split : std_logic := '0';
signal s_axis_mm2s_cmd_tready_split : std_logic := '0';
signal s_axis_mm2s_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_s2mm_cmd_tvalid_split : std_logic := '0';
signal s_axis_s2mm_cmd_tready_split : std_logic := '0';
signal s_axis_s2mm_cmd_tdata_split : std_logic_vector
((2*C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s_axis_mm2s_cmd_tvalid : std_logic := '0';
signal s_axis_mm2s_cmd_tready : std_logic := '0';
signal s_axis_mm2s_cmd_tdata : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover MM2S Status Stream Signals
signal m_axis_mm2s_sts_tvalid : std_logic := '0';
signal m_axis_mm2s_sts_tvalid_int : std_logic := '0';
signal m_axis_mm2s_sts_tready : std_logic := '0';
signal m_axis_mm2s_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tdata_int : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_mm2s_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
signal mm2s_halt : std_logic := '0';
signal mm2s_halt_cmplt : std_logic := '0';
-- S2MM DMA Controller Signals
signal s2mm_desc_flush : std_logic := '0';
signal s2mm_ftch_idle : std_logic := '0';
signal s2mm_updt_idle : std_logic := '0';
signal s2mm_updt_ioc_irq_set : std_logic := '0';
signal s2mm_irqthresh_wren : std_logic := '0';
signal s2mm_irqdelay_wren : std_logic := '0';
signal s2mm_irqthresh_rstdsbl : std_logic := '0'; -- CR572013
-- SG S2MM Descriptor Fetch AXI Stream IN
signal m_axis_s2mm_ftch_tdata_new : std_logic_vector(96 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_new : std_logic_vector(63 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tdata_mcdma_nxt : std_logic_vector(31 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid_new : std_logic := '0';
signal m_axis_ftch2_desc_available, m_axis_ftch1_desc_available : std_logic;
signal m_axis_s2mm_ftch_tdata : std_logic_vector(M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_s2mm_ftch_tvalid : std_logic := '0';
signal m_axis_s2mm_ftch_tready : std_logic := '0';
signal m_axis_s2mm_ftch_tlast : std_logic := '0';
signal mm2s_axis_info : std_logic_vector(13 downto 0) := (others => '0');
-- SG S2MM Descriptor Update AXI Stream Out
signal s_axis_s2mm_updtptr_tdata : std_logic_vector(S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtptr_tvalid : std_logic := '0';
signal s_axis_s2mm_updtptr_tready : std_logic := '0';
signal s_axis_s2mm_updtptr_tlast : std_logic := '0';
signal s_axis_s2mm_updtsts_tdata : std_logic_vector(S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_updtsts_tvalid : std_logic := '0';
signal s_axis_s2mm_updtsts_tready : std_logic := '0';
signal s_axis_s2mm_updtsts_tlast : std_logic := '0';
-- DataMover S2MM Command Stream Signals
signal s_axis_s2mm_cmd_tvalid : std_logic := '0';
signal s_axis_s2mm_cmd_tready : std_logic := '0';
signal s_axis_s2mm_cmd_tdata : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH+(8*C_ENABLE_MULTI_CHANNEL))-1 downto 0) := (others => '0');
-- DataMover S2MM Status Stream Signals
signal m_axis_s2mm_sts_tvalid : std_logic := '0';
signal m_axis_s2mm_sts_tvalid_int : std_logic := '0';
signal m_axis_s2mm_sts_tready : std_logic := '0';
signal m_axis_s2mm_sts_tdata : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tdata_int : std_logic_vector(DM_STATUS_WIDTH - 1 downto 0) := (others => '0');
signal m_axis_s2mm_sts_tkeep : std_logic_vector((DM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
signal s2mm_halt : std_logic := '0';
signal s2mm_halt_cmplt : std_logic := '0';
-- Error Status Control
signal mm2s_ftch_interr_set : std_logic := '0';
signal mm2s_ftch_slverr_set : std_logic := '0';
signal mm2s_ftch_decerr_set : std_logic := '0';
signal mm2s_updt_interr_set : std_logic := '0';
signal mm2s_updt_slverr_set : std_logic := '0';
signal mm2s_updt_decerr_set : std_logic := '0';
signal mm2s_ftch_err_early : std_logic := '0';
signal mm2s_ftch_stale_desc : std_logic := '0';
signal s2mm_updt_interr_set : std_logic := '0';
signal s2mm_updt_slverr_set : std_logic := '0';
signal s2mm_updt_decerr_set : std_logic := '0';
signal s2mm_ftch_interr_set : std_logic := '0';
signal s2mm_ftch_slverr_set : std_logic := '0';
signal s2mm_ftch_decerr_set : std_logic := '0';
signal s2mm_ftch_err_early : std_logic := '0';
signal s2mm_ftch_stale_desc : std_logic := '0';
signal soft_reset_clr : std_logic := '0';
signal soft_reset : std_logic := '0';
signal s_axis_s2mm_tready_i : std_logic := '0';
signal s_axis_s2mm_tready_int : std_logic := '0';
signal m_axis_mm2s_tlast_i : std_logic := '0';
signal m_axis_mm2s_tlast_i_user : std_logic := '0';
signal m_axis_mm2s_tvalid_i : std_logic := '0';
signal sg_ctl : std_logic_vector (7 downto 0);
signal s_axis_s2mm_tvalid_int : std_logic;
signal s_axis_s2mm_tlast_int : std_logic;
signal tdest_out_int : std_logic_vector (6 downto 0);
signal same_tdest : std_logic;
signal s2mm_eof_s2mm : std_logic;
signal ch2_update_active : std_logic;
signal s2mm_desc_info_in : std_logic_vector (13 downto 0);
signal m_axis_mm2s_tlast_i_mcdma : std_logic;
signal s2mm_run_stop_del : std_logic;
signal s2mm_desc_flush_del : std_logic;
signal s2mm_tvalid_latch : std_logic;
signal s2mm_tvalid_latch_del : std_logic;
signal clock_splt : std_logic;
signal clock_splt_s2mm : std_logic;
signal updt_cmpt : std_logic;
signal cmpt_updt : std_logic_vector (1 downto 0);
signal reset1, reset2 : std_logic;
signal mm2s_cntrl_strm_stop : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- AXI DMA Test Vector (For Xilinx Internal Use Only)
axi_dma_tstvec(31 downto 6) <= (others => '0');
axi_dma_tstvec(5) <= s2mm_updt_ioc_irq_set;
axi_dma_tstvec(4) <= mm2s_updt_ioc_irq_set;
axi_dma_tstvec(3) <= s2mm_packet_eof;
axi_dma_tstvec(2) <= s2mm_packet_sof;
axi_dma_tstvec(1) <= mm2s_packet_eof;
axi_dma_tstvec(0) <= mm2s_packet_sof;
-- Primary MM2S Stream outputs (used internally to gen eof and sof for
-- interrupt coalescing
m_axis_mm2s_tlast <= m_axis_mm2s_tlast_i;
m_axis_mm2s_tvalid <= m_axis_mm2s_tvalid_i;
-- Primary S2MM Stream output (used internally to gen eof and sof for
-- interrupt coalescing
s_axis_s2mm_tready <= s_axis_s2mm_tready_i;
GEN_INCLUDE_SG : if C_INCLUDE_SG = 1 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= m_axi_sg_aclk;
end generate GEN_INCLUDE_SG;
GEN_EXCLUDE_SG : if C_INCLUDE_SG = 0 generate
axi_lite_aclk <= s_axi_lite_aclk;
axi_sg_aclk <= s_axi_lite_aclk;
end generate GEN_EXCLUDE_SG;
-------------------------------------------------------------------------------
-- AXI DMA Reset Module
-------------------------------------------------------------------------------
I_RST_MODULE : entity axi_dma_v7_1.axi_dma_rst_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_M_AXI_MM2S_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_M_AXI_S2MM_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_M_AXI_SG_ACLK_FREQ_HZ => M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
s_axi_lite_aclk => axi_lite_aclk ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
-----------------------------------------------------------------------
-- Hard Reset
-----------------------------------------------------------------------
axi_resetn => axi_resetn ,
-----------------------------------------------------------------------
-- Soft Reset
-----------------------------------------------------------------------
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
mm2s_stop => mm2s_stop ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
s2mm_stop => s2mm_stop ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-----------------------------------------------------------------------
-- MM2S Distributed Reset Out (m_axi_mm2s_aclk)
-----------------------------------------------------------------------
dm_mm2s_prmry_resetn => m_axi_mm2s_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_mm2s_scndry_resetn => dm_mm2s_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n , -- AXI Stream Control Reset Outputs
mm2s_scndry_resetn => mm2s_scndry_resetn , -- AXI Secondary Reset
mm2s_prmry_resetn => mm2s_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- S2MM Distributed Reset Out (m_axi_s2mm_aclk)
-----------------------------------------------------------------------
dm_s2mm_prmry_resetn => m_axi_s2mm_aresetn , -- AXI DataMover Primary Reset (Raw)
dm_s2mm_scndry_resetn => dm_s2mm_scndry_resetn , -- AXI DataMover Secondary Reset (Raw)
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Primary Reset Outputs
s2mm_sts_reset_out_n => s2mm_sts_reset_out_n , -- AXI Stream Control Reset Outputs
s2mm_scndry_resetn => s2mm_scndry_resetn , -- AXI Secondary Reset
s2mm_prmry_resetn => s2mm_prmry_resetn , -- AXI Primary Reset
-----------------------------------------------------------------------
-- Scatter Gather Distributed Reset Out (m_axi_sg_aclk)
-----------------------------------------------------------------------
m_axi_sg_aresetn => m_axi_sg_aresetn , -- AXI Scatter Gather Reset Out
dm_m_axi_sg_aresetn => dm_m_axi_sg_aresetn , -- AXI Scatter Gather Datamover Reset Out
-----------------------------------------------------------------------
-- Hard Reset Out (s_axi_lite_aclk)
-----------------------------------------------------------------------
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn , -- AXI Lite Ingerface (sg aclk) (Hard Only)
s_axi_lite_resetn => axi_lite_reset_n -- AXI Lite Interface reset (Hard Only)
);
-------------------------------------------------------------------------------
-- AXI DMA Register Module
-------------------------------------------------------------------------------
I_AXI_DMA_REG_MODULE : entity axi_dma_v7_1.axi_dma_reg_module
generic map(
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_AXI_LITE_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset_n => axi_lite_reset_n ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
m_axi_sg_hrdresetn => m_axi_sg_hrdresetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- MM2S DMASR Status
mm2s_stop => mm2s_stop ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_dma_interr_set => mm2s_dma_interr_set ,
mm2s_dma_slverr_set => mm2s_dma_slverr_set ,
mm2s_dma_decerr_set => mm2s_dma_decerr_set ,
mm2s_ioc_irq_set => mm2s_ioc_irq_set ,
mm2s_dly_irq_set => mm2s_dly_irq_set ,
mm2s_irqthresh_wren => mm2s_irqthresh_wren ,
mm2s_irqdelay_wren => mm2s_irqdelay_wren ,
mm2s_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
mm2s_irqdelay_status => mm2s_irqdelay_status ,
mm2s_irqthresh_status => mm2s_irqthresh_status ,
mm2s_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
mm2s_ftch_interr_set => mm2s_ftch_interr_set ,
mm2s_ftch_slverr_set => mm2s_ftch_slverr_set ,
mm2s_ftch_decerr_set => mm2s_ftch_decerr_set ,
mm2s_updt_interr_set => mm2s_updt_interr_set ,
mm2s_updt_slverr_set => mm2s_updt_slverr_set ,
mm2s_updt_decerr_set => mm2s_updt_decerr_set ,
-- MM2S CURDESC Update
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_new_curdesc => mm2s_new_curdesc ,
-- MM2S TAILDESC Update
mm2s_tailpntr_updated => mm2s_tailpntr_updated ,
-- MM2S Registers
mm2s_dmacr => mm2s_dmacr ,
mm2s_dmasr => mm2s_dmasr ,
mm2s_curdesc => mm2s_curdesc ,
mm2s_taildesc => mm2s_taildesc ,
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
s2mm_sof => s2mm_packet_sof ,
s2mm_eof => s2mm_packet_eof ,
-- S2MM DMASR Status
s2mm_stop => s2mm_stop ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_dma_interr_set => s2mm_dma_interr_set ,
s2mm_dma_slverr_set => s2mm_dma_slverr_set ,
s2mm_dma_decerr_set => s2mm_dma_decerr_set ,
s2mm_ioc_irq_set => s2mm_ioc_irq_set ,
s2mm_dly_irq_set => s2mm_dly_irq_set ,
s2mm_irqthresh_wren => s2mm_irqthresh_wren ,
s2mm_irqdelay_wren => s2mm_irqdelay_wren ,
s2mm_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
s2mm_irqdelay_status => s2mm_irqdelay_status ,
s2mm_irqthresh_status => s2mm_irqthresh_status ,
s2mm_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
s2mm_ftch_interr_set => s2mm_ftch_interr_set ,
s2mm_ftch_slverr_set => s2mm_ftch_slverr_set ,
s2mm_ftch_decerr_set => s2mm_ftch_decerr_set ,
s2mm_updt_interr_set => s2mm_updt_interr_set ,
s2mm_updt_slverr_set => s2mm_updt_slverr_set ,
s2mm_updt_decerr_set => s2mm_updt_decerr_set ,
-- MM2S CURDESC Update
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_tvalid => s_axis_s2mm_tvalid ,
s2mm_tvalid_latch => s2mm_tvalid_latch ,
s2mm_tvalid_latch_del => s2mm_tvalid_latch_del ,
-- MM2S TAILDESC Update
s2mm_tailpntr_updated => s2mm_tailpntr_updated ,
-- S2MM Registers
s2mm_dmacr => s2mm_dmacr ,
s2mm_dmasr => s2mm_dmasr ,
s2mm_curdesc => s2mm_curdesc ,
s2mm_taildesc => s2mm_taildesc ,
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
tdest_in => tdest_out_int, --s_axis_s2mm_tdest ,
same_tdest_in => same_tdest,
sg_ctl => sg_ctl ,
-- Soft reset and clear
soft_reset => soft_reset ,
soft_reset_clr => soft_reset_clr ,
-- Fetch/Update error addresses
ftch_error_addr => ftch_error_addr ,
updt_error_addr => updt_error_addr ,
-- DMA Interrupt Outputs
mm2s_introut => mm2s_introut ,
s2mm_introut => s2mm_introut
);
-------------------------------------------------------------------------------
-- Scatter Gather Mode (C_INCLUDE_SG = 1)
-------------------------------------------------------------------------------
GEN_SG_ENGINE : if C_INCLUDE_SG = 1 generate
begin
-- reset1 <= dm_m_axi_sg_aresetn and s2mm_tvalid_latch;
-- reset2 <= m_axi_sg_aresetn and s2mm_tvalid_latch;
s2mm_run_stop_del <= s2mm_tvalid_latch_del and s2mm_dmacr(DMACR_RS_BIT);
-- s2mm_run_stop_del <= (not (updt_cmpt)) and s2mm_dmacr(DMACR_RS_BIT);
s2mm_desc_flush_del <= s2mm_desc_flush or (not s2mm_tvalid_latch);
-- Scatter Gather Engine
I_SG_ENGINE : entity axi_sg_v4_1.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_AXIS_IS_ASYNC => SG_IS_SYNCHRONOUS ,
C_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_INCLUDE_CH1 => C_INCLUDE_MM2S ,
C_INCLUDE_CH2 => C_INCLUDE_S2MM ,
C_INCLUDE_DESC_UPDATE => INCLUDE_DESC_UPDATE ,
C_INCLUDE_INTRPT => INCLUDE_INTRPT ,
C_INCLUDE_DLYTMR => INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => STSCNTRL_ENABLE ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_NUM_MM2S_CHANNELS => C_NUM_MM2S_CHANNELS ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
dm_resetn => dm_m_axi_sg_aresetn ,
p_reset_n => mm2s_prmry_resetn ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => m_axi_sg_awuser ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => m_axi_sg_aruser ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
sg_ctl => sg_ctl ,
-- Channel 1 Control and Status
ch1_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
ch1_cyclic => mm2s_dmacr(CYCLIC_BIT) ,
ch1_desc_flush => mm2s_desc_flush ,
ch1_cntrl_strm_stop => mm2s_cntrl_strm_stop ,
ch1_ftch_idle => mm2s_ftch_idle ,
ch1_ftch_interr_set => mm2s_ftch_interr_set ,
ch1_ftch_slverr_set => mm2s_ftch_slverr_set ,
ch1_ftch_decerr_set => mm2s_ftch_decerr_set ,
ch1_ftch_err_early => mm2s_ftch_err_early ,
ch1_ftch_stale_desc => mm2s_ftch_stale_desc ,
ch1_updt_idle => mm2s_updt_idle ,
ch1_updt_ioc_irq_set => mm2s_updt_ioc_irq_set ,
ch1_updt_interr_set => mm2s_updt_interr_set ,
ch1_updt_slverr_set => mm2s_updt_slverr_set ,
ch1_updt_decerr_set => mm2s_updt_decerr_set ,
ch1_dma_interr_set => mm2s_dma_interr_set ,
ch1_dma_slverr_set => mm2s_dma_slverr_set ,
ch1_dma_decerr_set => mm2s_dma_decerr_set ,
ch1_tailpntr_enabled => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => mm2s_tailpntr_updated ,
ch1_taildesc => mm2s_taildesc ,
ch1_curdesc => mm2s_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
--ch1_dlyirq_dsble => mm2s_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch1_dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
ch1_irqthresh_rstdsbl => mm2s_irqthresh_rstdsbl , -- CR572013
ch1_irqdelay_wren => mm2s_irqdelay_wren ,
ch1_irqdelay => mm2s_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch1_irqthresh_wren => mm2s_irqthresh_wren ,
ch1_irqthresh => mm2s_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch1_packet_sof => mm2s_packet_sof ,
ch1_packet_eof => mm2s_packet_eof ,
ch1_ioc_irq_set => mm2s_ioc_irq_set ,
ch1_dly_irq_set => mm2s_dly_irq_set ,
ch1_irqdelay_status => mm2s_irqdelay_status ,
ch1_irqthresh_status => mm2s_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_sg_aclk ,
m_axis_ch1_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => axi_sg_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => s2mm_run_stop_del , --s2mm_dmacr(DMACR_RS_BIT) ,
ch2_cyclic => s2mm_dmacr(CYCLIC_BIT) ,
ch2_desc_flush => s2mm_desc_flush_del, --s2mm_desc_flush ,
ch2_ftch_idle => s2mm_ftch_idle ,
ch2_ftch_interr_set => s2mm_ftch_interr_set ,
ch2_ftch_slverr_set => s2mm_ftch_slverr_set ,
ch2_ftch_decerr_set => s2mm_ftch_decerr_set ,
ch2_ftch_err_early => s2mm_ftch_err_early ,
ch2_ftch_stale_desc => s2mm_ftch_stale_desc ,
ch2_updt_idle => s2mm_updt_idle ,
ch2_updt_ioc_irq_set => s2mm_updt_ioc_irq_set , -- For TestVector
ch2_updt_interr_set => s2mm_updt_interr_set ,
ch2_updt_slverr_set => s2mm_updt_slverr_set ,
ch2_updt_decerr_set => s2mm_updt_decerr_set ,
ch2_dma_interr_set => s2mm_dma_interr_set ,
ch2_dma_slverr_set => s2mm_dma_slverr_set ,
ch2_dma_decerr_set => s2mm_dma_decerr_set ,
ch2_tailpntr_enabled => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
ch2_taildesc_wren => s2mm_tailpntr_updated ,
ch2_taildesc => s2mm_taildesc ,
ch2_curdesc => s2mm_curdesc ,
-- Channel 2 Interrupt Coalescing Signals
--ch2_dlyirq_dsble => s2mm_dmasr(DMASR_DLYIRQ_BIT) , -- CR605888
ch2_dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
ch2_irqthresh_rstdsbl => s2mm_irqthresh_rstdsbl , -- CR572013
ch2_irqdelay_wren => s2mm_irqdelay_wren ,
ch2_irqdelay => s2mm_dmacr(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT),
ch2_irqthresh_wren => s2mm_irqthresh_wren ,
ch2_irqthresh => s2mm_dmacr(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT),
ch2_packet_sof => s2mm_packet_sof ,
ch2_packet_eof => s2mm_packet_eof ,
ch2_ioc_irq_set => s2mm_ioc_irq_set ,
ch2_dly_irq_set => s2mm_dly_irq_set ,
ch2_irqdelay_status => s2mm_irqdelay_status ,
ch2_irqthresh_status => s2mm_irqthresh_status ,
ch2_update_active => ch2_update_active ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_sg_aclk ,
m_axis_ch2_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_ch2_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => axi_sg_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_ch2_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Error addresses
ftch_error => ftch_error ,
ftch_error_addr => ftch_error_addr ,
updt_error => updt_error ,
updt_error_addr => updt_error_addr ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate GEN_SG_ENGINE;
-------------------------------------------------------------------------------
-- Exclude Scatter Gather Engine (Simple DMA Mode Enabled)
-------------------------------------------------------------------------------
GEN_NO_SG_ENGINE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather AXI Master Interface Tie-Off
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
m_axi_sg_awvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0';
m_axi_sg_wvalid <= '0';
m_axi_sg_bready <= '0';
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arcache <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arvalid <= '0';
m_axi_sg_rready <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
-- MM2S Signal Remapping/Tie Off for Simple DMA Mode
m_axis_mm2s_ftch_tdata <= (others => '0');
m_axis_mm2s_ftch_tvalid <= '0';
m_axis_mm2s_ftch_tlast <= '0';
s_axis_mm2s_updtptr_tready <= '0';
s_axis_mm2s_updtsts_tready <= '0';
mm2s_ftch_idle <= '1';
mm2s_updt_idle <= '1';
mm2s_ftch_interr_set <= '0';
mm2s_ftch_slverr_set <= '0';
mm2s_ftch_decerr_set <= '0';
mm2s_ftch_err_early <= '0';
mm2s_ftch_stale_desc <= '0';
mm2s_updt_interr_set <= '0';
mm2s_updt_slverr_set <= '0';
mm2s_updt_decerr_set <= '0';
mm2s_updt_ioc_irq_set <= mm2s_smpl_done; -- For TestVector
mm2s_dma_interr_set <= mm2s_smpl_interr_set; -- To DMASR
mm2s_dma_slverr_set <= mm2s_smpl_slverr_set; -- To DMASR
mm2s_dma_decerr_set <= mm2s_smpl_decerr_set; -- To DMASR
-- S2MM Signal Remapping/Tie Off for Simple DMA Mode
m_axis_s2mm_ftch_tdata <= (others => '0');
m_axis_s2mm_ftch_tvalid <= '0';
m_axis_s2mm_ftch_tlast <= '0';
s_axis_s2mm_updtptr_tready <= '0';
s_axis_s2mm_updtsts_tready <= '0';
s2mm_ftch_idle <= '1';
s2mm_updt_idle <= '1';
s2mm_ftch_interr_set <= '0';
s2mm_ftch_slverr_set <= '0';
s2mm_ftch_decerr_set <= '0';
s2mm_ftch_err_early <= '0';
s2mm_ftch_stale_desc <= '0';
s2mm_updt_interr_set <= '0';
s2mm_updt_slverr_set <= '0';
s2mm_updt_decerr_set <= '0';
s2mm_updt_ioc_irq_set <= s2mm_smpl_done; -- For TestVector
s2mm_dma_interr_set <= s2mm_smpl_interr_set; -- To DMASR
s2mm_dma_slverr_set <= s2mm_smpl_slverr_set; -- To DMASR
s2mm_dma_decerr_set <= s2mm_smpl_decerr_set; -- To DMASR
ftch_error <= '0';
ftch_error_addr <= (others => '0');
updt_error <= '0';
updt_error_addr <= (others=> '0');
-- CR595462 - Removed interrupt coalescing logic for Simple DMA mode and replaced
-- with interrupt complete.
mm2s_ioc_irq_set <= mm2s_smpl_done;
mm2s_dly_irq_set <= '0';
mm2s_irqdelay_status <= (others => '0');
mm2s_irqthresh_status <= (others => '0');
s2mm_ioc_irq_set <= s2mm_smpl_done;
s2mm_dly_irq_set <= '0';
s2mm_irqdelay_status <= (others => '0');
s2mm_irqthresh_status <= (others => '0');
end generate GEN_NO_SG_ENGINE;
-------------------------------------------------------------------------------
-- MM2S DMA Controller
-------------------------------------------------------------------------------
I_MM2S_DMA_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
soft_reset => soft_reset ,
-- MM2S Control and Status
mm2s_run_stop => mm2s_dmacr(DMACR_RS_BIT) ,
mm2s_keyhole => mm2s_dmacr(DMACR_KH_BIT) ,
mm2s_halted => mm2s_dmasr(DMASR_HALTED_BIT) ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr ,
mm2s_stop => mm2s_stop ,
mm2s_ftch_err_early => mm2s_ftch_err_early ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_desc_flush => mm2s_desc_flush ,
cntrl_strm_stop => mm2s_cntrl_strm_stop ,
mm2s_tailpntr_enble => mm2s_dmacr(DMACR_TAILPEN_BIT) ,
mm2s_all_idle => mm2s_all_idle ,
mm2s_error => mm2s_error ,
s2mm_error => s2mm_error ,
-- Simple DMA Mode Signals
mm2s_sa => mm2s_sa ,
mm2s_length => mm2s_length ,
mm2s_length_wren => mm2s_length_wren ,
mm2s_smple_done => mm2s_smpl_done ,
mm2s_interr_set => mm2s_smpl_interr_set ,
mm2s_slverr_set => mm2s_smpl_slverr_set ,
mm2s_decerr_set => mm2s_smpl_decerr_set ,
m_axis_mm2s_aclk => m_axi_mm2s_aclk,
mm2s_strm_tlast => m_axis_mm2s_tlast_i_user,
mm2s_strm_tready => m_axis_mm2s_tready,
mm2s_axis_info => mm2s_axis_info,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- Currently Being Processed Descriptor
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready_split ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
mm2s_err => mm2s_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => open, --m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => open, --m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => open, --m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => '0', --m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => open --m_axis_mm2s_cntrl_tlast
);
m_axis_mm2s_tuser <= mm2s_axis_info (13 downto 10);
m_axis_mm2s_tid <= mm2s_axis_info (9 downto 5); --
m_axis_mm2s_tdest <= mm2s_axis_info (4 downto 0) ; --
-- If MM2S channel included then include sof/eof generator
INCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 1 generate
begin
-------------------------------------------------------------------------------
-- MM2S SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_MM2S_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_mm2s_aclk ,
p_reset_n => mm2s_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => mm2s_scndry_resetn ,
axis_tready => m_axis_mm2s_tready ,
axis_tvalid => m_axis_mm2s_tvalid_i ,
axis_tlast => m_axis_mm2s_tlast_i ,
packet_sof => mm2s_packet_sof ,
packet_eof => mm2s_packet_eof
);
end generate INCLUDE_MM2S_SOF_EOF_GENERATOR;
-- If MM2S channel not included then exclude sof/eof generator
EXCLUDE_MM2S_SOF_EOF_GENERATOR : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_packet_sof <= '0';
mm2s_packet_eof <= '0';
end generate EXCLUDE_MM2S_SOF_EOF_GENERATOR;
-------------------------------------------------------------------------------
-- S2MM DMA Controller
-------------------------------------------------------------------------------
I_S2MM_DMA_MNGR : entity axi_dma_v7_1.axi_dma_s2mm_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_INCLUDE_STSCNTRL_STRM => STSCNTRL_ENABLE ,
C_SG_INCLUDE_DESC_QUEUE => DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => APPLENGTH_ENABLE ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH_INT ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => S_AXIS_UPDSTS_TDATA_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
-- Primary Clock and Reset
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
soft_reset => soft_reset ,
-- S2MM Control and Status
s2mm_run_stop => s2mm_dmacr(DMACR_RS_BIT) ,
s2mm_keyhole => s2mm_dmacr(DMACR_KH_BIT) ,
s2mm_halted => s2mm_dmasr(DMASR_HALTED_BIT) ,
s2mm_packet_eof_out => s2mm_eof_s2mm ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr ,
s2mm_stop => s2mm_stop ,
s2mm_ftch_err_early => s2mm_ftch_err_early ,
s2mm_ftch_stale_desc => s2mm_ftch_stale_desc ,
s2mm_desc_flush => s2mm_desc_flush ,
s2mm_tailpntr_enble => s2mm_dmacr(DMACR_TAILPEN_BIT) ,
s2mm_all_idle => s2mm_all_idle ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_error => s2mm_error ,
mm2s_error => mm2s_error ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- Simple DMA Mode Signals
s2mm_da => s2mm_da ,
s2mm_length => s2mm_length ,
s2mm_length_wren => s2mm_length_wren ,
s2mm_smple_done => s2mm_smpl_done ,
s2mm_interr_set => s2mm_smpl_interr_set ,
s2mm_slverr_set => s2mm_smpl_slverr_set ,
s2mm_decerr_set => s2mm_smpl_decerr_set ,
s2mm_bytes_rcvd => s2mm_bytes_rcvd ,
s2mm_bytes_rcvd_wren => s2mm_bytes_rcvd_wren ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- Currently Being Processed Descriptor
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
-- User Command Interface Ports (AXI Stream)
-- s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
-- s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
-- s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready_split ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata_split ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
s2mm_err => s2mm_err ,
updt_error => updt_error ,
ftch_error => ftch_error ,
-- Stream to Memory Map Status Stream Interface
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
-- If S2MM channel included then include sof/eof generator
INCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 1 generate
begin
-------------------------------------------------------------------------------
-- S2MM SOF / EOF generation for interrupt coalescing
-------------------------------------------------------------------------------
I_S2MM_SOFEOF_GEN : entity axi_dma_v7_1.axi_dma_sofeof_gen
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
axi_prmry_aclk => m_axi_s2mm_aclk ,
p_reset_n => s2mm_prmry_resetn ,
m_axi_sg_aclk => axi_sg_aclk ,
m_axi_sg_aresetn => s2mm_scndry_resetn ,
axis_tready => s_axis_s2mm_tready_i ,
axis_tvalid => s_axis_s2mm_tvalid ,
axis_tlast => s_axis_s2mm_tlast ,
packet_sof => s2mm_packet_sof ,
packet_eof => s2mm_packet_eof
);
end generate INCLUDE_S2MM_SOF_EOF_GENERATOR;
-- If S2MM channel not included then exclude sof/eof generator
EXCLUDE_S2MM_SOF_EOF_GENERATOR : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_packet_sof <= '0';
s2mm_packet_eof <= '0';
end generate EXCLUDE_S2MM_SOF_EOF_GENERATOR;
INCLUDE_S2MM_GATE : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
cmpt_updt <= m_axis_s2mm_sts_tvalid & s2mm_eof_s2mm;
I_S2MM_GATE_GEN : entity axi_dma_v7_1.axi_dma_s2mm
generic map (
C_FAMILY => C_FAMILY
)
port map (
clk_in => m_axi_s2mm_aclk,
sg_clk => axi_sg_aclk,
resetn => s2mm_prmry_resetn,
reset_sg => m_axi_sg_aresetn,
s2mm_tvalid => s_axis_s2mm_tvalid,
s2mm_tready => s_axis_s2mm_tready_i,
s2mm_tlast => s_axis_s2mm_tlast,
s2mm_tdest => s_axis_s2mm_tdest,
s2mm_tuser => s_axis_s2mm_tuser,
s2mm_tid => s_axis_s2mm_tid,
desc_available => s_axis_s2mm_cmd_tvalid_split,
-- s2mm_eof => s2mm_eof_s2mm,
s2mm_eof_det => cmpt_updt, --m_axis_s2mm_sts_tvalid, --s2mm_eof_s2mm,
ch2_update_active => ch2_update_active,
tdest_out => tdest_out_int,
same_tdest => same_tdest,
-- to DM
-- updt_cmpt => updt_cmpt,
s2mm_desc_info => s2mm_desc_info_in,
s2mm_tvalid_out => open, --s_axis_s2mm_tvalid_int,
s2mm_tready_out => open, --s_axis_s2mm_tready_i,
s2mm_tlast_out => open, --s_axis_s2mm_tlast_int,
s2mm_tdest_out => open
);
end generate INCLUDE_S2MM_GATE;
INCLUDE_S2MM_NOGATE : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
updt_cmpt <= '0';
tdest_out_int <= (others => '0');
same_tdest <= '0';
s_axis_s2mm_tvalid_int <= s_axis_s2mm_tvalid;
s_axis_s2mm_tlast_int <= s_axis_s2mm_tlast;
end generate INCLUDE_S2MM_NOGATE;
MM2S_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_MM2S = 1) generate
begin
CLOCKS : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt <= axi_sg_aclk;
end generate CLOCKS;
CLOCKS_SYNC : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt <= m_axi_mm2s_aclk;
end generate CLOCKS_SYNC;
I_COMMAND_MM2S_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_INCLUDE_S2MM => 0,
C_DM_STATUS_WIDTH => 8
)
port map (
clock => clock_splt, --axi_sg_aclk,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_mm2s_aclk, --axi_sg_aclk,
aresetn => m_axi_mm2s_aresetn,
-- MM2S command coming from MM2S_MNGR
s_axis_cmd_tvalid => s_axis_mm2s_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_mm2s_cmd_tready_split,
s_axis_cmd_tdata => s_axis_mm2s_cmd_tdata_split,
-- MM2S split command to DM
s_axis_cmd_tvalid_s => s_axis_mm2s_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_mm2s_cmd_tready,
s_axis_cmd_tdata_s => s_axis_mm2s_cmd_tdata,
tvalid_from_datamover => m_axis_mm2s_sts_tvalid_int,
status_in => m_axis_mm2s_sts_tdata_int,
tvalid_unsplit => m_axis_mm2s_sts_tvalid,
status_out => m_axis_mm2s_sts_tdata,
tlast_stream_data => m_axis_mm2s_tlast_i_mcdma,
tready_stream_data => m_axis_mm2s_tready,
tlast_unsplit => m_axis_mm2s_tlast_i,
tlast_unsplit_user => m_axis_mm2s_tlast_i_user
);
end generate MM2S_SPLIT;
MM2S_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_MM2S = 1) generate
begin
s_axis_mm2s_cmd_tvalid <= s_axis_mm2s_cmd_tvalid_split;
s_axis_mm2s_cmd_tready_split <= s_axis_mm2s_cmd_tready;
s_axis_mm2s_cmd_tdata <= s_axis_mm2s_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_mm2s_sts_tvalid <= m_axis_mm2s_sts_tvalid_int;
m_axis_mm2s_sts_tdata <= m_axis_mm2s_sts_tdata_int;
m_axis_mm2s_tlast_i <= m_axis_mm2s_tlast_i_mcdma;
m_axis_mm2s_tlast_i_user <= '0';
end generate MM2S_SPLIT_NOMCDMA;
S2MM_SPLIT : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
CLOCKS_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
clock_splt_s2mm <= axi_sg_aclk;
end generate CLOCKS_S2MM;
CLOCKS_SYNC_S2MM : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
clock_splt_s2mm <= m_axi_s2mm_aclk;
end generate CLOCKS_SYNC_S2MM;
I_COMMAND_S2MM_SPLITTER : entity axi_dma_v7_1.axi_dma_cmd_split
generic map (
C_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_INCLUDE_S2MM => C_INCLUDE_S2MM,
C_DM_STATUS_WIDTH => DM_STATUS_WIDTH
)
port map (
clock => clock_splt_s2mm,
sgresetn => m_axi_sg_aresetn,
clock_sec => m_axi_s2mm_aclk, --axi_sg_aclk, --m_axi_s2mm_aclk,
aresetn => m_axi_s2mm_aresetn,
-- S2MM command coming from S2MM_MNGR
s_axis_cmd_tvalid => s_axis_s2mm_cmd_tvalid_split,
s_axis_cmd_tready => s_axis_s2mm_cmd_tready_split,
s_axis_cmd_tdata => s_axis_s2mm_cmd_tdata_split,
-- S2MM split command to DM
s_axis_cmd_tvalid_s => s_axis_s2mm_cmd_tvalid,
s_axis_cmd_tready_s => s_axis_s2mm_cmd_tready,
s_axis_cmd_tdata_s => s_axis_s2mm_cmd_tdata,
tvalid_from_datamover => m_axis_s2mm_sts_tvalid_int,
status_in => m_axis_s2mm_sts_tdata_int,
tvalid_unsplit => m_axis_s2mm_sts_tvalid,
status_out => m_axis_s2mm_sts_tdata,
tlast_stream_data => '0',
tready_stream_data => '0',
tlast_unsplit => open,
tlast_unsplit_user => open
);
end generate S2MM_SPLIT;
S2MM_SPLIT_NOMCDMA : if (C_ENABLE_MULTI_CHANNEL = 0 and C_INCLUDE_S2MM = 1) generate
begin
s_axis_s2mm_cmd_tvalid <= s_axis_s2mm_cmd_tvalid_split;
s_axis_s2mm_cmd_tready_split <= s_axis_s2mm_cmd_tready;
s_axis_s2mm_cmd_tdata <= s_axis_s2mm_cmd_tdata_split ((C_M_AXI_MM2S_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0);
m_axis_s2mm_sts_tvalid <= m_axis_s2mm_sts_tvalid_int;
m_axis_s2mm_sts_tdata <= m_axis_s2mm_sts_tdata_int;
end generate S2MM_SPLIT_NOMCDMA;
-------------------------------------------------------------------------------
-- Primary MM2S and S2MM DataMover
-------------------------------------------------------------------------------
I_PRMRY_DATAMOVER : entity axi_datamover_v5_1.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_AXI_FULL_MODE,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_MM2S_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE,
C_MM2S_BURST_SIZE => C_MM2S_BURST_SIZE,
C_MM2S_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_MM2S_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_MM2S_INCLUDE_SF => DM_MM2S_INCLUDE_SF,
C_ENABLE_CACHE_USER => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_SKID_BUF => skid_enable, --"11111",
C_MICRO_DMA => C_MICRO_DMA,
C_INCLUDE_S2MM => S2MM_AXI_FULL_MODE,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH_1,
C_S2MM_STSCMD_IS_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE,
C_S2MM_BURST_SIZE => C_S2MM_BURST_SIZE,
C_S2MM_BTT_USED => DM_BTT_LENGTH_WIDTH,
C_S2MM_SUPPORT_INDET_BTT => DM_SUPPORT_INDET_BTT,
C_S2MM_ADDR_PIPE_DEPTH => DM_ADDR_PIPE_DEPTH,
C_S2MM_INCLUDE_SF => DM_S2MM_INCLUDE_SF,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_mm2s_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata
(((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid_int ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata_int ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_mm2s_araddr ,
m_axi_mm2s_arlen => m_axi_mm2s_arlen ,
m_axi_mm2s_arsize => m_axi_mm2s_arsize ,
m_axi_mm2s_arburst => m_axi_mm2s_arburst ,
m_axi_mm2s_arprot => m_axi_mm2s_arprot ,
m_axi_mm2s_arcache => m_axi_mm2s_arcache ,
m_axi_mm2s_aruser => m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid ,
m_axi_mm2s_arready => m_axi_mm2s_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_mm2s_rdata ,
m_axi_mm2s_rresp => m_axi_mm2s_rresp ,
m_axi_mm2s_rlast => m_axi_mm2s_rlast ,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid ,
m_axi_mm2s_rready => m_axi_mm2s_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast_i_mcdma ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid_i ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_s2mm_aclk ,
m_axi_s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_s2mm_scndry_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata (
((8*C_ENABLE_MULTI_CHANNEL)+
C_M_AXI_MM2S_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid_int ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata_int ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr ,
m_axi_s2mm_awlen => m_axi_s2mm_awlen ,
m_axi_s2mm_awsize => m_axi_s2mm_awsize ,
m_axi_s2mm_awburst => m_axi_s2mm_awburst ,
m_axi_s2mm_awprot => m_axi_s2mm_awprot ,
m_axi_s2mm_awcache => m_axi_s2mm_awcache ,
m_axi_s2mm_awuser => m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid ,
m_axi_s2mm_awready => m_axi_s2mm_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_s2mm_wdata ,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb ,
m_axi_s2mm_wlast => m_axi_s2mm_wlast ,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid ,
m_axi_s2mm_wready => m_axi_s2mm_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_s2mm_bresp ,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid ,
m_axi_s2mm_bready => m_axi_s2mm_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready_i ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end implementation;
| bsd-2-clause | 01ef18d166dca0b0e35fd3d10899e03b | 0.43641 | 3.776795 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/fei4_rx_channel.vhd | 2 | 6,256 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: RX channel
-- # FE-I4 Style Rx Channel; Sync, Align & Decode
-- ####################################
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library decode_8b10b;
entity fei4_rx_channel is
port (
-- Sys connect
rst_n_i : in std_logic;
clk_160_i : in std_logic;
clk_640_i : in std_logic;
enable_i : in std_logic;
-- Input
rx_data_i : in std_logic;
trig_tag_i : in std_logic_vector(31 downto 0);
-- Output
rx_data_o : out std_logic_vector(25 downto 0);
rx_valid_o : out std_logic;
rx_stat_o : out std_logic_vector(7 downto 0);
rx_data_raw_o : out std_logic_vector(7 downto 0)
);
end fei4_rx_channel;
architecture behavioral of fei4_rx_channel is
component cdr_serdes
port (
-- clocks
clk160 : in std_logic;
clk640 : in std_logic;
-- reset
reset : in std_logic;
-- data input
din : in std_logic;
-- data output
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end component;
component data_alignment
port
(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(1 downto 0);
din_valid : in std_logic_vector(1 downto 0);
dout : out std_logic_vector(9 downto 0);
dout_valid : out std_logic;
dout_sync : out std_logic
);
end component;
component decode_8b10b_wrapper
port(
CLK : IN std_logic;
DIN : IN std_logic_vector(9 downto 0);
CE : IN std_logic;
SINIT : IN std_logic;
DOUT : OUT std_logic_vector(7 downto 0);
KOUT : OUT std_logic;
CODE_ERR : OUT std_logic;
DISP_ERR : OUT std_logic;
ND : OUT std_logic
);
end component;
constant c_SOF : std_logic_vector(7 downto 0) := x"fc";
constant c_EOF : std_logic_vector(7 downto 0) := x"bc";
constant c_IDLE : std_logic_vector(7 downto 0) := x"3c";
signal data_raw_value : std_logic_vector(1 downto 0);
signal data_raw_valid : std_logic_vector(1 downto 0);
signal data_raw_lock : std_logic;
signal data_enc_value : std_logic_vector(9 downto 0);
signal data_enc_valid : std_logic;
signal data_enc_sync : std_logic;
signal data_enc_value_rev : std_logic_vector(9 downto 0);
signal data_enc_valid_rev : std_logic;
signal data_enc_valid_rev_d : std_logic;
signal data_dec_value : std_logic_vector(7 downto 0);
signal data_dec_valid : std_logic;
signal data_dec_kchar : std_logic;
signal data_dec_decerr : std_logic;
signal data_dec_disperr : std_logic;
signal data_fram_cnt : unsigned(1 downto 0);
signal data_frame_flag : std_logic;
signal data_frame_value : std_logic_vector(25 downto 0);
signal data_frame_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
begin
-- Status Output
rx_stat_o <= status;
status(0) <= data_raw_lock;
status(1) <= data_enc_sync;
status(2) <= data_dec_decerr;
status(3) <= data_dec_disperr;
status(5 downto 4) <= data_raw_value;
status(7 downto 6) <= data_raw_valid;
rx_data_raw_o <= data_dec_value;
-- Frame collector
rx_data_o <= data_frame_value;
rx_valid_o <= data_frame_valid and data_raw_lock and data_enc_sync and enable_i;
framing_proc : process(clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fram_cnt <= (others => '0');
data_frame_flag <= '0';
data_frame_value <= (others => '0');
data_frame_valid <= '0';
elsif rising_edge(clk_160_i) then
-- Count bytes
if (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt = 2) then
data_fram_cnt <= (others => '0');
data_frame_valid <= '1';
elsif (data_frame_flag = '1' and data_dec_valid = '1' and data_fram_cnt < 2) then
data_fram_cnt <= data_fram_cnt + 1;
data_frame_valid <= '0';
elsif (data_frame_flag = '0') then
data_fram_cnt <= (others => '0');
data_frame_valid <= '0';
else
data_frame_valid <= '0';
end if;
-- Mark Start and End of Frame
if (data_dec_valid = '1' and data_dec_kchar = '1' and data_dec_value = c_SOF and data_enc_sync = '1') then
data_frame_flag <= '1';
data_frame_value(25 downto 24) <= "01"; -- tag code
data_frame_value(23 downto 0) <= trig_tag_i(23 downto 0);
data_frame_valid <= '1';
elsif (data_dec_valid = '1' and data_dec_kchar = '1' and (data_dec_value = c_EOF or data_dec_value = c_IDLE)) then
data_frame_flag <= '0';
end if;
-- Build Frame
if (data_frame_flag = '1' and data_dec_valid = '1' and data_dec_kchar = '0' ) then
data_frame_value(25 downto 24) <= "00"; -- no special code
data_frame_value(23 downto 16) <= data_frame_value(15 downto 8);
data_frame_value(15 downto 8) <= data_frame_value(7 downto 0);
data_frame_value(7 downto 0) <= data_dec_value;
end if;
end if;
end process framing_proc;
-- Reverse bit order to make it standard
reverse_proc : process (clk_160_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_enc_value_rev <= (others => '0');
data_enc_valid_rev <= '0';
data_enc_valid_rev_d <= '0';
data_dec_valid <= '0';
elsif rising_edge(clk_160_i) then
for I in 0 to 9 loop
data_enc_value_rev(I) <= data_enc_value(9-I);
end loop;
data_enc_valid_rev <= data_enc_valid;
data_enc_valid_rev_d <= data_enc_valid_rev;
data_dec_valid <= data_enc_valid_rev_d;
end if;
end process reverse_proc;
cmp_cdr_serdes : cdr_serdes port map (
clk160 => clk_160_i,
clk640 => clk_640_i,
reset => not rst_n_i,
din => rx_data_i,
data_value => data_raw_value,
data_valid => data_raw_valid,
data_lock => data_raw_lock
);
cmp_data_align : data_alignment port map (
clk => clk_160_i,
reset => not rst_n_i,
din => data_raw_value,
din_valid => data_raw_valid,
dout => data_enc_value,
dout_valid => data_enc_valid,
dout_sync => data_enc_sync
);
cmp_decoder: decode_8b10b_wrapper PORT MAP(
CLK => clk_160_i,
DIN => data_enc_value_rev,
CE => data_enc_valid_rev,
SINIT => '0',
DOUT => data_dec_value,
KOUT => data_dec_kchar,
CODE_ERR => data_dec_decErr,
DISP_ERR => data_dec_dispErr,
ND => open
);
end behavioral;
| gpl-3.0 | dec0edbe1dcaa19f5d4b1e3700207ae8 | 0.617008 | 2.723552 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/wrap_brst.vhd | 1 | 51,441 | -------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
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`protect end_protected
| bsd-2-clause | ae85a440a3a6f4f08506cf7fd4f29bff | 0.919665 | 1.928398 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_pkg.vhd | 3 | 9,683 | ---------------------------------------------------------------------------
--
-- Module : decode_8b10b_pkg.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : 8b/10b Decoder package file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
---------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Package Declaration
-------------------------------------------------------------------------------
PACKAGE decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
CONSTANT TFF : TIME := 2 ns;
CONSTANT CONST_NEG : STRING (1 TO 2) := "00";
CONSTANT CONST_POS : STRING (1 TO 2) := "01";
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit (
bit : INTEGER
) RETURN STRING;
FUNCTION bint_2_sl (
X : INTEGER
) RETURN STD_LOGIC;
FUNCTION concat_sinit (
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING
) RETURN STRING;
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER
) RETURN STD_LOGIC_VECTOR;
FUNCTION calc_init_val_rd (
SINIT_VAL : STRING(10 DOWNTO 1)
) RETURN INTEGER;
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER
) RETURN INTEGER;
END decode_8b10b_pkg;
-------------------------------------------------------------------------------
-- Package Body
-------------------------------------------------------------------------------
PACKAGE BODY decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into a single-character-string ("0" or "1")
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit(bit : INTEGER) RETURN STRING IS
BEGIN
IF (bit = 1) THEN
RETURN "1";
ELSE
RETURN "0";
END IF;
END int_to_str_1bit;
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into std_logic ('0' or '1')
-------------------------------------------------------------------------------
FUNCTION bint_2_sl (X : INTEGER) RETURN STD_LOGIC IS
BEGIN
IF (X = 0) THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
END bint_2_sl;
-------------------------------------------------------------------------------
-- Calculate the SINIT value for the inferred BRAM using the generics:
-- C_SINIT_DOUT, C_SINIT_KOUT, and C_SINIT_RUN_DISP
-------------------------------------------------------------------------------
FUNCTION concat_sinit(
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING)
RETURN STRING IS
VARIABLE tmp_sym_disp : STRING(1 TO 2);
CONSTANT TMP_CODE_ERR : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_0 : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_1 : STRING(1 TO 1) := "1";
VARIABLE tmp_str : STRING(1 TO 14);
BEGIN
IF (integer_run_disp = 1) THEN
tmp_sym_disp := CONST_POS; -- D0.0+ has sym_disp of pos
ELSE
tmp_sym_disp := CONST_NEG; -- D0.0- has sym_disp of neg
END IF;
IF (integer_kout = 1) THEN
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_1 & string_dout;
ELSE
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_0 & string_dout;
END IF;
RETURN tmp_str;
END concat_sinit;
-----------------------------------------------------------------------------
-- Convert a string containing 1's and 0's into a std_logic_vector of
-- width nbits
-----------------------------------------------------------------------------
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE ret : STD_LOGIC_VECTOR(bitsin'range);
VARIABLE ret0s : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE retpadded : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE offset : INTEGER := 0;
BEGIN
IF(bitsin'length = 0) THEN -- Make all '0's
RETURN ret0s;
END IF;
IF(bitsin'length < nbits) THEN -- pad MSBs with '0's
offset := nbits - bitsin'length;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
retpadded(i+offset) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
retpadded(i+offset) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
retpadded(i+offset) := 'Z';
ELSIF (bitsin(i) = '0') THEN
retpadded(i+offset) := '0';
END IF;
END LOOP;
retpadded(1 TO offset) := (OTHERS => '0');
RETURN retpadded;
END IF;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
ret(i) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
ret(i) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
ret(i) := 'Z';
ELSIF (bitsin(i) = '0') THEN
ret(i) := '0';
END IF;
END LOOP;
RETURN ret;
END str_to_slv;
-----------------------------------------------------------------------------
-- Translate the SINIT string value from the core wrapper to
-- C_SINIT_RUN_DISP
-----------------------------------------------------------------------------
FUNCTION calc_init_val_rd (SINIT_VAL : STRING(10 DOWNTO 1)) RETURN INTEGER IS
VARIABLE tmp_init_val : INTEGER;
BEGIN
CASE SINIT_VAL IS
WHEN "0000000001" => tmp_init_val := 1; --D.0.0 (pos)
WHEN "0000000000" => tmp_init_val := 0; --D.0.0 (neg)
WHEN "0100101001" => tmp_init_val := 1; --D.10.2 (pos)
WHEN "0100101000" => tmp_init_val := 0; --D.10.2 (neg)
WHEN "1011010101" => tmp_init_val := 1; --D.21.5 (pos)
WHEN "1011010100" => tmp_init_val := 0; --D.21.5 (neg)
WHEN OTHERS => tmp_init_val := 0; --invalid init value
END CASE;
RETURN tmp_init_val;
END calc_init_val_rd;
-----------------------------------------------------------------------------
-- If C_HAS_BPORTS = 1, then the optional B ports are configured the
-- same as the optional A ports
-- If C_HAS_BPORTS = 0, then the optional B ports are disabled (= 0)
-----------------------------------------------------------------------------
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER)
RETURN INTEGER IS
VARIABLE has_bport : INTEGER;
BEGIN
IF (C_HAS_BPORTS = 1) THEN
has_bport := has_aport;
ELSE
has_bport := 0;
END IF;
RETURN has_bport;
END has_bport;
END decode_8b10b_pkg;
| gpl-3.0 | 9bfb1d26abdd4163bd4dcc301eac2ea9 | 0.473407 | 4.332438 | false | false | false | false |
rjarzmik/mips_processor | WB/Writeback.vhd | 1 | 6,600 | -------------------------------------------------------------------------------
-- Title : Writeback instruction's result
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Writeback.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-16
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Writes back a MIPS instruction result into the register file
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-16 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
use work.instruction_defs.all;
-------------------------------------------------------------------------------
entity Writeback is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
NB_REGISTERS : positive := 34
);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic; -- stall current instruction
kill_req : in std_logic; -- kill current instruction
i_reg1 : in register_port_type;
i_reg2 : in register_port_type;
i_jump_target : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_is_jump : in std_logic;
o_reg1 : out register_port_type;
o_reg2 : out register_port_type;
o_is_jump : out std_logic;
o_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
-- Carry-over signals
i_instr_tag : in instr_tag_t;
o_instr_tag : out instr_tag_t;
-- Debug signal
i_dbg_wb_pc : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
o_dbg_wb_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0)
);
end entity Writeback;
-------------------------------------------------------------------------------
architecture rtl of Writeback is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal reg1 : register_port_type;
signal reg2 : register_port_type;
signal is_nop : boolean;
signal last_is_jump : std_logic;
signal last_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal last_instr_tag : instr_tag_t;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
is_nop <= true when i_reg1.we = '0' and i_reg2.we = '0' and
not i_instr_tag.is_branch and not i_instr_tag.is_ja and
not i_instr_tag.is_jr else false;
process(rst, clk, stall_req)
begin
if rst = '1' then
reg1.we <= '0';
reg2.we <= '0';
o_instr_tag <= INSTR_TAG_NONE;
last_instr_tag <= INSTR_TAG_NONE;
last_is_jump <= '0';
last_jump_target <= (others => 'X');
elsif rising_edge(clk) then
if kill_req = '1' then
reg1.we <= '0';
reg2.we <= '0';
o_is_jump <= '0';
o_jump_target <= (others => 'X');
o_instr_tag <= INSTR_TAG_NONE;
elsif stall_req = '0' then
if not is_nop then
last_instr_tag <=
get_instr_change_is_branch_taken(i_instr_tag, i_is_jump = '1');
last_is_jump <= i_is_jump;
last_jump_target <= i_jump_target;
end if;
-- Branch delay slot of 1 :
--- If branch or jump, delay setting o_is_jump and o_jump_target to
--- the next no-NOP instruction
--- If not, forward as is.
if (last_instr_tag.is_branch or last_instr_tag.is_ja
or last_instr_tag.is_jr) and not is_nop then
-- Falsify the outputs to fake the jump/branch happens on the next
-- after jump/branch instruction, ie. delay slot of 1.
-- Transfer the jump and the writeback instruction together
-- The o_instr_tag is changed from the instruction just after the
-- branch to the instruction branch, for branch prediction.
o_is_jump <= last_is_jump;
o_jump_target <= last_jump_target;
o_instr_tag <=
get_instr_change_is_branch_taken(
get_instr_change_is_branch(
get_instr_change_is_ja(
get_instr_change_is_jr(i_instr_tag, last_instr_tag.is_jr),
last_instr_tag.is_ja),
last_instr_tag.is_branch),
last_instr_tag.is_branch_taken);
elsif (i_instr_tag.is_branch or i_instr_tag.is_ja
or i_instr_tag.is_jr) then
-- As the jump information is kept in last_*, wipe out any
-- jump/branch sign from this instruction, as it will be reapplied on
-- the next one.
o_is_jump <= '0';
o_jump_target <= (others => 'X');
o_instr_tag <=
get_instr_change_is_branch_taken(
get_instr_change_is_branch(
get_instr_change_is_ja(
get_instr_change_is_jr(i_instr_tag, false),
false),
false),
false);
else
-- Here there wasn't a "jump/branch" kept nor on the input
-- instruction, so forward normally everything.
o_is_jump <= i_is_jump;
o_jump_target <= i_jump_target;
o_instr_tag <= i_instr_tag;
end if;
reg1 <= i_reg1;
reg2 <= i_reg2;
end if;
end if;
end process;
debug : process(rst, clk, stall_req, kill_req)
begin
if rst = '1' then
o_dbg_wb_pc <= (others => 'X');
elsif rising_edge(clk) and kill_req = '1' then
o_dbg_wb_pc <= (others => 'X');
elsif rising_edge(clk) and stall_req = '1' then
elsif rising_edge(clk) then
o_dbg_wb_pc <= i_dbg_wb_pc;
end if;
end process debug;
o_reg1 <= reg1;
o_reg2 <= reg2;
end architecture rtl;
-------------------------------------------------------------------------------
| gpl-3.0 | 8cb8e45ada5c1e2410d2768d347581a9 | 0.468636 | 3.942652 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_028_test_input.fixed_upper.vhd | 1 | 566 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
END if;
END if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
END if;
END if;
end process;
end architecture RTL;
| gpl-3.0 | 2b1c522c80b2abb0c476605e80b7eea3 | 0.379859 | 3.19774 | false | false | false | false |
Yarr/Yarr-fw | rtl/i2c-master/i2c_master_wb_top.vhd | 2 | 9,181 | -- ==================================================================
-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- ------------------------------------------------------------------
-- Copyright (c) 2013 by Lattice Semiconductor Corporation
-- ALL RIGHTS RESERVED
-- ------------------------------------------------------------------
--
-- Permission:
--
-- Lattice SG Pte. Ltd. grants permission to use this code
-- pursuant to the terms of the Lattice Reference Design License Agreement.
--
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice SG Pte. Ltd.
-- 101 Thomson Road, United Square #07-02
-- Singapore 307591
--
--
-- TEL: 1-800-Lattice (USA and Canada)
-- +65-6631-2000 (Singapore)
-- +1-503-268-8001 (other locations)
--
-- web: http:--www.latticesemi.com/
-- email: [email protected]
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_wb_top is
generic (
ARST_LVL : integer := 0
);
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end;
architecture arch of i2c_master_wb_top is
component i2c_master_bit_ctrl
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command complete acknowledge
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- i2c bus arbitration lost
din : in std_logic;
dout : out std_logic;
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable (active low)
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable (active low)
);
end component;
component i2c_master_byte_ctrl
port (
clk : in std_logic; -- master clock
rst : in std_logic; -- synchronous active high reset
nReset : in std_logic; -- asynchronous active low reset
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- control inputs
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- status outputs
cmd_ack : out std_logic;
ack_out : out std_logic; -- i2c clock line input
dout : out std_logic_vector(7 downto 0);
i2c_al : in std_logic;
-- signals for bit_controller
core_cmd : out std_logic_vector(3 downto 0);
core_txd : out std_logic;
core_rxd : in std_logic;
core_ack : in std_logic
);
end component;
component i2c_master_registers
port (
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_wacc : in std_logic;
i2c_al : in std_logic;
i2c_busy : in std_logic;
done : in std_logic;
irxack : in std_logic;
prer : out std_logic_vector(15 downto 0); -- clock prescale register
ctr : out std_logic_vector(7 downto 0); -- control register
txr : out std_logic_vector(7 downto 0); -- transmit register
cr : out std_logic_vector(7 downto 0); -- command register
sr : out std_logic_vector(7 downto 0) -- status register
);
end component;
signal prer : std_logic_vector(15 downto 0);
signal ctr : std_logic_vector(7 downto 0);
signal txr : std_logic_vector(7 downto 0);
signal rxr : std_logic_vector(7 downto 0);
signal cr : std_logic_vector(7 downto 0);
signal sr : std_logic_vector(7 downto 0);
signal done : std_logic;
signal core_en : std_logic;
signal ien : std_logic;
signal irxack : std_logic;
signal irq_flag : std_logic;
signal i2c_busy : std_logic;
signal i2c_al : std_logic;
signal core_cmd : std_logic_vector(3 downto 0);
signal core_txd : std_logic;
signal core_ack, core_rxd : std_logic;
signal scl_pad_i : std_logic;
signal scl_pad_o : std_logic;
signal scl_padoen_o : std_logic;
signal sda_pad_i : std_logic;
signal sda_pad_o : std_logic;
signal sda_padoen_o : std_logic;
signal rst_i : std_logic;
signal sta : std_logic;
signal sto : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal ack : std_logic;
signal iack : std_logic;
signal wb_ack_o_int : std_logic;
signal wb_wacc : std_logic;
signal acki : std_logic;
begin
scl_pad_i <= scl;
sda_pad_i <= sda;
rst_i <= arst_i when (ARST_LVL = 0) else NOT(arst_i);
wb_wacc <= wb_cyc_i AND wb_stb_i AND wb_we_i;
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
acki <= cr(0);
core_en <= ctr(7);
ien <= ctr(6);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o_int <= wb_cyc_i AND wb_stb_i AND NOT(wb_ack_o_int);
end if;
end process;
wb_ack_o <= wb_ack_o_int;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
case (wb_adr_i) is
when "000" => wb_dat_o <= prer(7 downto 0);
when "001" => wb_dat_o <= prer(15 downto 8);
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr;
when "100" => wb_dat_o <= sr;
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= "00000000";
when others => NULL;
end case;
end if;
end process;
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif rising_edge(wb_clk_i) then
wb_inta_o <= sr(0) AND ien;
end if;
end process;
byte_controller: i2c_master_byte_ctrl port map(
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
i2c_al => i2c_al,
core_cmd => core_cmd,
core_ack => core_ack,
core_txd => core_txd,
core_rxd => core_rxd);
bit_controller: i2c_master_bit_ctrl port map(
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => i2c_al,
din => core_txd,
dout => core_rxd,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o);
registers: i2c_master_registers port map(
wb_clk_i => wb_clk_i,
rst_i => rst_i,
wb_rst_i => wb_rst_i,
wb_dat_i => wb_dat_i,
wb_wacc => wb_wacc,
wb_adr_i => wb_adr_i,
i2c_al => i2c_al,
i2c_busy => i2c_busy,
done => done,
irxack => irxack,
prer => prer,
ctr => ctr,
txr => txr,
cr => cr,
sr => sr);
scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
end arch;
| gpl-3.0 | d8c4e224dd05b88afbf3b8162fd3949e | 0.509531 | 3.002289 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/exponent/rule_500_test_input.fixed_upper.vhd | 1 | 373 |
architecture rtl of fifo is
constant con_1 : natural := 20E10;
constant con_2 : natural := 20.56E10;
constant con_3 : natural := 20E-10;
constant con_4 : natural := 20.56E-10;
constant con_5 : natural := 20E10;
constant con_6 : natural := 20.56E10;
constant con_7 : natural := 20E-10;
constant con_8 : natural := 20.56E-10;
begin
end architecture rtl;
| gpl-3.0 | 1e1682c89695478c1b9e18c318e92b45 | 0.659517 | 3.008065 | false | false | false | false |
eurobotics/aversive4dspic | modules/devices/encoders/encoders_eirbot/xilinx_vhdl/compteur.vhd | 1 | 1,595 | LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY compteur IS
GENERIC ( Nb_bascules : natural := 1
);
PORT ( AB : IN unsigned(1 DOWNTO 0);
cpt : OUT unsigned(7 DOWNTO 0);
clk : IN std_ulogic;
INV : IN std_ulogic
);
END compteur;
ARCHITECTURE Behavioral OF compteur IS
TYPE tableau IS ARRAY (Nb_bascules downto 0) OF unsigned(1 DOWNTO 0);
SIGNAL A_B : tableau;
SIGNAL tmp : unsigned(7 DOWNTO 0);
BEGIN
-- double latch des codeurs
copie : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk) ;
A_B(0)<= AB(1) & (AB(0) XOR INV);
FOR i IN 1 TO Nb_bascules LOOP
A_B(i) <= A_B(i-1);
END LOOP;
END PROCESS copie;
-- decodage de la quadrature et comptage
comptage: PROCESS
BEGIN
WAIT UNTIL falling_edge(clk) ;
IF (A_B(Nb_bascules-1) = "00" and A_B(Nb_bascules) = "01") OR (A_B(Nb_bascules-1) = "01" AND A_B(Nb_bascules) = "11") OR (A_B(Nb_bascules-1) = "11" AND A_B(Nb_bascules) = "10") OR (A_B(Nb_bascules-1) = "10" AND A_B(Nb_bascules) = "00") THEN
tmp <= tmp - 1;
ELSIF (A_B(Nb_bascules) = "00" and A_B(Nb_bascules-1) = "01") OR (A_B(Nb_bascules) = "01" AND A_B(Nb_bascules-1) = "11") OR (A_B(Nb_bascules) = "11" AND A_B(Nb_bascules-1) = "10") OR (A_B(Nb_bascules) = "10" AND A_B(Nb_bascules-1) = "00") THEN
tmp <= tmp + 1;
END IF;
END PROCESS comptage;
cpt <= tmp;
END Behavioral;
| gpl-3.0 | 6fc6cc8bffa992ef7fe0ed0065d724ae | 0.579937 | 2.645108 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_011_test_input.fixed_new_line_after_assign_no.vhd | 1 | 369 |
architecture RTL of FIFO is
begin
-- These are passing
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
-- Failing variations
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
-- Arrays should be ignored
a <= (
b => 0,
c => 6
);
end architecture RTL;
| gpl-3.0 | d4704f0c401c493bd1cfa4c063c3e298 | 0.439024 | 3.127119 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/component/rule_017_test_input.fixed_seperate_generic.vhd | 1 | 705 |
architecture RTl of FIFO is
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
-- Failures below
component fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end component fifo;
begin
end architecture RTL;
| gpl-3.0 | c02ddcdcb0de8d80b5d89be8919d530d | 0.551773 | 3.671875 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/after/rule_001_test_input.vhd | 1 | 2,507 |
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (falling_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (rising_edge(clk)) then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This checks detection of after outside clock processes
a <= b after 10 ns;
-- Violations below -----------------------------------
-- This process checks for missing after statements
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c;
c <= d;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (falling_edge(clk)) then
a <= b;
b <= c after 1 ns;
c <= d;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (rising_edge(clk)) then
a <= b;
b <= c;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- This process checks for a clock process without a reset
CLK_PROC : process (reset, clk) is
begin
if (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d;
d <= e;
end if;
end process CLK_PROC;
end architecture ARCH;
| gpl-3.0 | 0d1cde2f06c00d83c8556d5012ebb7e6 | 0.523734 | 3.521067 | false | false | false | false |
lvd2/zxevo | unsupported/solegstar/fpga/current/sim_models/T80_ALU.vhd | 15 | 11,889 | -- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
| gpl-3.0 | 9b8aca443e4b6dee8acfc8d7b6826d0e | 0.537051 | 2.621032 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/fifo_generator_v11_0/simulation/fifo_generator_v11_0.vhd | 2 | 376,161 | -------------------------------------------------------------------------------
--
-- FIFO Generator - VHDL Behavioral Model
--
-------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Filename: fifo_generator_v11_0.vhd
--
-- Author : Xilinx
--
-------------------------------------------------------------------------------
-- Structure:
--
-- fifo_generator_v11_0.vhd
-- |
-- +-fifo_generator_v11_0_conv
-- |
-- +-fifo_generator_v11_0_bhv_as
-- |
-- +-fifo_generator_v11_0_bhv_ss
-- |
-- +-fifo_generator_v11_0_bhv_preload0
--
-------------------------------------------------------------------------------
-- Description:
--
-- The VHDL behavioral model for the FIFO Generator.
--
-- The behavioral model has three parts:
-- - The behavioral model for independent clocks FIFOs (_as)
-- - The behavioral model for common clock FIFOs (_ss)
-- - The "preload logic" block which implements First-word Fall-through
--
-------------------------------------------------------------------------------
--#############################################################################
--#############################################################################
-- Independent Clocks FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Independent Clocks Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v11_0_bhv_as IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2
);
PORT(
---------------------------------------------------------------------------
-- Input and Output Declarations
---------------------------------------------------------------------------
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VALID : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v11_0_bhv_as;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v11_0_bhv_as IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH - 1;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION div_roundup
-- Returns data_value / divisor, with the result rounded-up (if fractional)
-------------------------------------------------------------------------------
FUNCTION divroundup (
data_value : integer;
divisor : integer)
RETURN integer IS
VARIABLE div : integer;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- Derived Constants
-----------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_FIFO_RD_DEPTH : integer
:= actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY);
CONSTANT C_SMALLER_DATA_WIDTH : integer
:= get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_DEPTH_RATIO_WR : integer
:= if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1);
CONSTANT C_DEPTH_RATIO_RD : integer
:= if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1);
-- "Extra Words" is the number of write words which fit into the two
-- first-word fall-through output register stages (if using FWFT).
-- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1.
-- This value is used to calculate the adjusted PROG_FULL threshold
-- value for FWFT.
-- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
-- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
-- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
-- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD);
-- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT
-- value for the core when using FWFT.
-- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
-- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
-- -----------------|------------------|-----------------|---------------
-- 1 | 8 | C_RD_PNTR_WIDTH | 2
-- 1 | 4 | C_RD_PNTR_WIDTH | 2
-- 1 | 2 | C_RD_PNTR_WIDTH | 2
-- 1 | 1 | C_WR_PNTR_WIDTH | 2
-- 2 | 1 | C_WR_PNTR_WIDTH | 4
-- 4 | 1 | C_WR_PNTR_WIDTH | 8
-- 8 | 1 | C_WR_PNTR_WIDTH | 16
CONSTANT EXTRA_WORDS_DC : integer
:= if_then_else ((C_DEPTH_RATIO_WR = 1),2,
(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD));
CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT
CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED;
CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED;
CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT
CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer
:=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0),
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT
-- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error
-- injection is selected.
CONSTANT NO_ERR_INJECTION : integer
:= if_then_else(C_USE_ECC = 0,1,
if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0));
-- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection
-- is selected.
CONSTANT SBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 1),1,0);
-- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection
-- is selected.
CONSTANT DBIT_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 2),1,0);
-- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit
-- error injection are selected.
CONSTANT BOTH_ERR_INJECTION : integer
:= if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 3),1,0);
CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
TYPE wr_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
TYPE rd_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pntr_q : wr_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL rd_pntr_q : rd_sync_array := (OTHERS => (OTHERS => '0'));
-------------------------------------------------------------------------------
-- Signals Declaration
-------------------------------------------------------------------------------
SIGNAL wr_point : integer := 0;
SIGNAL rd_point : integer := 0;
SIGNAL wr_point_d1 : integer := 0;
SIGNAL rd_point_d1 : integer := 0;
SIGNAL num_wr_words : integer := 0;
SIGNAL num_rd_words : integer := 0;
SIGNAL adj_wr_point : integer := 0;
SIGNAL adj_rd_point : integer := 0;
SIGNAL adj_wr_point_d1: integer := 0;
SIGNAL adj_rd_point_d1: integer := 0;
SIGNAL wr_rst_i : std_logic := '0';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL wr_rst_d1 : std_logic := '0';
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL valid_out : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL width_gt1 : std_logic := '0';
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS=>'0');
SIGNAL empty_int : boolean := TRUE;
SIGNAL empty_comb : std_logic := '1';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL empty_comb_d1 : std_logic := '1';
SIGNAL almost_empty_int : boolean := TRUE;
SIGNAL full_int : boolean := FALSE;
SIGNAL full_comb : std_logic := '0';
SIGNAL ram_wr_en : std_logic := '0';
SIGNAL almost_full_int : boolean := FALSE;
SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL stage1_valid : std_logic := '0';
SIGNAL stage2_valid : std_logic := '0';
SIGNAL diff_pntr_wr : integer := 0;
SIGNAL diff_pntr_rd : integer := 0;
SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
-------------------------------------------------------------------------------
--Linked List types
-------------------------------------------------------------------------------
TYPE listtyp;
TYPE listptr IS ACCESS listtyp;
TYPE listtyp IS RECORD
data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0);
older : listptr;
newer : listptr;
END RECORD;
-------------------------------------------------------------------------------
--Processes for linked list implementation. The functions are
--1. "newlist" - Create a new linked list
--2. "add" - Add a data element to a linked list
--3. "read" - Read the data from the tail of the linked list
--4. "remove" - Remove the tail from the linked list
--5. "sizeof" - Calculate the size of the linked list
-------------------------------------------------------------------------------
--1. Create a new linked list
PROCEDURE newlist (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
BEGIN
head := NULL;
tail := NULL;
cntr := 0;
END;
--2. Add a data element to a linked list
PROCEDURE add (
head : INOUT listptr;
tail : INOUT listptr;
data : IN std_logic_vector;
cntr : INOUT integer;
inj_err : IN std_logic_vector(2 DOWNTO 0)
) IS
VARIABLE oldhead : listptr;
VARIABLE newhead : listptr;
VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0);
BEGIN
--------------------------------------------------------------------------
--a. Create a pointer to the existing head, if applicable
--b. Create a new node for the list
--c. Make the new node point to the old head
--d. Make the old head point back to the new node (for doubly-linked list)
--e. Put the data into the new head node
--f. If the new head we just created is the only node in the list,
-- make the tail point to it
--g. Return the new head pointer
--------------------------------------------------------------------------
IF (head /= NULL) THEN
oldhead := head;
END IF;
newhead := NEW listtyp;
newhead.older := oldhead;
IF (head /= NULL) THEN
oldhead.newer := newhead;
END IF;
CASE inj_err(1 DOWNTO 0) IS
-- For both error injection, pass only the double bit error injection
-- as dbit error has priority over single bit error injection
WHEN "11" => newhead.data := inj_err(1) & '0' & data;
WHEN "10" => newhead.data := inj_err(1) & '0' & data;
WHEN "01" => newhead.data := '0' & inj_err(0) & data;
WHEN OTHERS => newhead.data := '0' & '0' & data;
END CASE;
-- Increment the counter when data is added to the list
cntr := cntr + 1;
IF (newhead.older = NULL) THEN
tail := newhead;
END IF;
head := newhead;
END;
--3. Read the data from the tail of the linked list
PROCEDURE read (
tail : INOUT listptr;
data : OUT std_logic_vector;
err_type : OUT std_logic_vector(1 DOWNTO 0)
) IS
VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
BEGIN
data_int := tail.data;
-- MSB two bits carry the error injection type.
err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH);
IF (err_type_int(1) = '0') THEN
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH = 2) THEN
data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
ELSIF (C_DOUT_WIDTH > 2) THEN
data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) &
data_int(data_int'high-4 DOWNTO 0);
ELSE
data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0);
END IF;
err_type := err_type_int;
END;
--4. Remove the tail from the linked list
PROCEDURE remove (
head : INOUT listptr;
tail : INOUT listptr;
cntr : INOUT integer) IS
VARIABLE oldtail : listptr;
VARIABLE newtail : listptr;
BEGIN
--------------------------------------------------------------------------
--Make a copy of the old tail pointer
--a. If there is no newer node, then set the tail pointer to nothing
-- (list is empty)
-- otherwise, make the next newer node the new tail, and make it point
-- to nothing older
--b. Clean up the memory for the old tail node
--c. If the new tail is nothing, then we have an empty list, and head
-- should also be set to nothing
--d. Return the new tail
--------------------------------------------------------------------------
oldtail := tail;
IF (oldtail.newer = NULL) THEN
newtail := NULL;
ELSE
newtail := oldtail.newer;
newtail.older := NULL;
END IF;
DEALLOCATE(oldtail);
IF (newtail = NULL) THEN
head := NULL;
END IF;
tail := newtail;
-- Decrement the counter when data is removed from the list
cntr := cntr - 1;
END;
--5. Calculate the size of the linked list
PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS
VARIABLE curlink : listptr;
VARIABLE tmpsize : integer := 0;
BEGIN
--------------------------------------------------------------------------
--a. If head is null, then there is nothing in the list to traverse
-- start with the head node (which implies at least one node exists)
-- Loop through each node until you find the one that points to nothing
-- (the tail)
--b. Return the number of nodes
--------------------------------------------------------------------------
IF (head /= NULL) THEN
curlink := head;
tmpsize := 1;
WHILE (curlink.older /= NULL) LOOP
tmpsize := tmpsize + 1;
curlink := curlink.older;
END LOOP;
END IF;
size := tmpsize;
END;
-----------------------------------------------------------------------------
-- converts integer to specified length std_logic_vector : dropping least
-- significant bits if integer is bigger than what can be represented by
-- the vector
-----------------------------------------------------------------------------
FUNCTION count(
fifo_count : IN integer;
pointer_width : IN integer;
counter_width : IN integer)
RETURN std_logic_vector IS
VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0)
:= (OTHERS => '0');
VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0)
:= (OTHERS => '0');
BEGIN
temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width);
IF (counter_width <= pointer_width) THEN
output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width);
ELSE
output := temp(counter_width - 1 DOWNTO 0);
END IF;
RETURN output;
END count;
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
-- Asynchronous FIFO
-------------------------------------------------------------------------------
gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE
wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH);
rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH);
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
-------------------------------------------------------------------------------
-- calculate number of words in wr and rd domain according to the deepest port
--
-- These steps circumvent the linked-list data structure and keep track of
-- wr_point and rd_point pointers much like the core itself does. The behavioral
-- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done
-- because the sizeof() function always returns the exact number of words in
-- the linked list, and can not account for delays when crossing clock domains.
-------------------------------------------------------------------------------
adj_wr_point <= wr_point * C_DEPTH_RATIO_RD;
adj_rd_point <= rd_point * C_DEPTH_RATIO_WR;
adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD;
adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR;
width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0';
PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1)
BEGIN
IF (adj_wr_point >= adj_rd_point_d1) THEN
num_wr_words <= adj_wr_point - adj_rd_point_d1;
ELSE
num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1;
END IF;
IF (adj_wr_point_d1 >= adj_rd_point) THEN
num_rd_words <= adj_wr_point_d1 - adj_rd_point;
ELSE
num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point;
END IF;
END PROCESS;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_VALID_LOW
-------------------------------------------------------------------------------
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_out;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_out;
END GENERATE gnvh;
-------------------------------------------------------------------------------
--Calculate UNDERFLOW based on C_UNDERFLOW_LOW
-------------------------------------------------------------------------------
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
-------------------------------------------------------------------------------
--Assign PROG_FULL and PROG_EMPTY
-------------------------------------------------------------------------------
PROG_FULL <= prog_full_reg;
PROG_EMPTY <= prog_empty_reg;
-------------------------------------------------------------------------------
--Assign RD_DATA_COUNT and WR_DATA_COUNT
-------------------------------------------------------------------------------
rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE
grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE grdc_fwft_ext;
gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH);
END GENERATE gnrdc_fwft_ext;
END GENERATE rdc;
nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nrdc;
wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE
gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE
WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gwdc_fwft_ext;
gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE
WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH);
END GENERATE gnwdc_fwft_ext;
END GENERATE wdc;
nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE
WR_DATA_COUNT <= (OTHERS=>'0');
END GENERATE nwdc;
-------------------------------------------------------------------------------
-- Write data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
CONSTANT C_PNTR_WIDTH : integer
:= if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH),
C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH);
SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(
if_then_else ((C_DEPTH_RATIO_WR=1),2
,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD))
,C_PNTR_WIDTH+1);
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
BEGIN
-----------------------------------------------------------------------------
--Adjust write and read pointer to the deepest port width
-----------------------------------------------------------------------------
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH
gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
END GENERATE gpadr;
--C_PNTR_WIDTH=C_RD_PNTR_WIDTH
gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr;
adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0');
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE gpadw;
--C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH
ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE
adjusted_wr_pntr <= wr_pntr;
adjusted_rd_pntr <= rd_pntr_wr;
END GENERATE ngpad;
-----------------------------------------------------------------------------
--Calculate words in write domain
-----------------------------------------------------------------------------
--Subtract the pointers to get the number of words in the RAM, *THEN* pad
--the result
diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
pwdc : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_data_count_i <= (OTHERS=>'0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_i <= diff_wr_rd + extra_words;
END IF;
END PROCESS pwdc;
gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0);
END GENERATE gdc0;
gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE
wdc_fwft_ext_as
<= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gdc1;
END GENERATE wdc_fwft_ext;
-------------------------------------------------------------------------------
-- Read data count calculation if Use Extra Logic option is used
-------------------------------------------------------------------------------
rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= (OTHERS => '0');
SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1);
SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0)
:= conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1);
SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS=>'0');
BEGIN
----------------------------------------------------------------------------
-- If write depth is smaller than read depth, pad write pointer.
-- If write depth is bigger than read depth, trim write pointer.
----------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= WR_PNTR_RD;
adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adjusted_wr_pntr_r
<= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-----------------------------------------------------------------------------
-- This accounts for preload 0 by explicitly handling the preload states
-- which do not have both output stages filled. As a result, the rd_data_count
-- produced will always accurately reflect the number of READABLE words at
-- a given time.
-----------------------------------------------------------------------------
diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR;
diff_wr_rd <= '0' & diff_wr_rd_tmp;
prdc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rdc_fwft_ext_as <= zero;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (stage2_valid = '0') THEN
rdc_fwft_ext_as <= zero;
ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN
rdc_fwft_ext_as <= one;
ELSE
rdc_fwft_ext_as <= diff_wr_rd + two;
END IF;
END IF;
END PROCESS prdc;
END GENERATE rdc_fwft_ext;
-------------------------------------------------------------------------------
-- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
-------------------------------------------------------------------------------
gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH)
<= wr_pntr_rd;
adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gpad;
gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE
adj_wr_pntr_rd
<= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH);
END GENERATE gtrim;
-------------------------------------------------------------------------------
-- Generate Empty
-------------------------------------------------------------------------------
-- ram_rd_en used to determine EMPTY should depend on the EMPTY.
ram_rd_en <= RD_EN AND (NOT empty_comb);
empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Empty
-------------------------------------------------------------------------------
almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND
(adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Empty & Almost Empty
-- Generate read data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
empty_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_comb <= '1' AFTER C_TCQ;
empty_comb_d1 <= '1' AFTER C_TCQ;
ALMOST_EMPTY <= '1' AFTER C_TCQ;
rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) -
rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
empty_comb_d1 <= empty_comb AFTER C_TCQ;
IF (empty_int) THEN
empty_comb <= '1' AFTER C_TCQ;
ELSE
empty_comb <= '0' AFTER C_TCQ;
END IF;
IF (empty_comb = '0') THEN
IF (almost_empty_int) THEN
ALMOST_EMPTY <= '1' AFTER C_TCQ;
ELSE
ALMOST_EMPTY <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation
-------------------------------------------------------------------------------
gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH)
<= rd_pntr_wr;
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)
<= (OTHERS => '0');
END GENERATE gfpad;
gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
adj_rd_pntr_wr
<= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH);
END GENERATE gftrim;
-------------------------------------------------------------------------------
-- Generate Full
-------------------------------------------------------------------------------
-- ram_wr_en used to determine FULL should depend on the FULL.
ram_wr_en <= WR_EN AND (NOT full_comb);
full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Generate Almost Full
-------------------------------------------------------------------------------
almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND
(adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH))));
-------------------------------------------------------------------------------
-- Registering Full & Almost Full
-- Generate write data count if Use Extra Logic is not selected.
-------------------------------------------------------------------------------
full_proc : PROCESS (WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) -
adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ;
IF (full_int) THEN
full_comb <= '1' AFTER C_TCQ;
ELSE
full_comb <= '0' AFTER C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
ALMOST_FULL <= '0' AFTER C_TCQ;
ELSIF (full_comb = '0') THEN
IF (almost_full_int) THEN
ALMOST_FULL <= '1' AFTER C_TCQ;
ELSE
ALMOST_FULL <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Counter that determines the FWFT read duration.
-------------------------------------------------------------------------------
-- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT.
grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE
SIGNAL user_empty_fb_d1 : std_logic := '1';
BEGIN
grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_fwft_cnt <= (others => '0');
user_empty_fb_d1 <= '1';
stage1_valid <= '0';
stage2_valid <= '0';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
user_empty_fb_d1 <= USER_EMPTY_FB;
IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN
rd_fwft_cnt <= (others => '0') AFTER C_TCQ;
ELSIF (empty_comb = '0') THEN
IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN
rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ;
END IF;
END IF;
IF (stage1_valid = '0' AND stage2_valid = '0') THEN
IF (empty_comb = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN
IF (empty_comb = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN
IF (empty_comb = '1' AND RD_EN_USER = '1') THEN
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
ELSE
stage1_valid <= '1' AFTER C_TCQ;
stage2_valid <= '1' AFTER C_TCQ;
END IF;
ELSE
stage1_valid <= '0' AFTER C_TCQ;
stage2_valid <= '0' AFTER C_TCQ;
END IF;
END IF;
END PROCESS grd_fwft_proc;
END GENERATE grd_fwft;
gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE
rd_fwft_cnt <= X"2";
END GENERATE gnrd_fwft;
-------------------------------------------------------------------------------
-- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY
-------------------------------------------------------------------------------
FULL <= full_comb;
EMPTY <= empty_comb;
-------------------------------------------------------------------------------
-- Asynchronous FIFO using linked lists
-------------------------------------------------------------------------------
FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i)
--Declare the linked-list head/tail pointers and the size value
VARIABLE head : listptr;
VARIABLE tail : listptr;
VARIABLE size : integer := 0;
VARIABLE cntr : integer := 0;
VARIABLE cntr_size_var_int : integer := 0;
--Data is the internal version of the DOUT bus
VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0)
:= hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width);
VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Temporary values for calculating adjusted prog_empty/prog_full thresholds
VARIABLE prog_empty_actual_assert_thresh : integer := 0;
VARIABLE prog_empty_actual_negate_thresh : integer := 0;
VARIABLE prog_full_actual_assert_thresh : integer := 0;
VARIABLE prog_full_actual_negate_thresh : integer := 0;
VARIABLE diff_pntr : integer := 0;
BEGIN
-- Calculate the current contents of the FIFO (size)
-- Warning: This value should only be calculated once each time this
-- process is entered.
-- It is updated instantaneously for both write and read operations,
-- so it is not ideal to use for signals which must consider the
-- latency of crossing clock domains.
-- cntr_size_var_int is updated only once when the process is entered
-- This variable is used in the conditions instead of cntr which has the
-- latest value.
cntr_size_var_int := cntr;
-- RESET CONDITIONS
IF wr_rst_i = '1' THEN
wr_point <= 0 after C_TCQ;
wr_point_d1 <= 0 after C_TCQ;
wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ;
rd_pntr_wr <= (OTHERS => '0') after C_TCQ;
rd_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
--Create new linked list
newlist(head, tail,cntr);
diff_pntr := 0;
---------------------------------------------------------------------------
-- Write to FIFO
---------------------------------------------------------------------------
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
rd_pntr_q <= rd_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & rd_pntr_wr_d1;
-- Delay the write pointer before passing to RD_CLK domain to accommodate
-- the binary to gray converion
wr_pntr_rd1 <= wr_pntr after C_TCQ;
rd_pntr_wr <= rd_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
wr_point_d1 <= wr_point after C_TCQ;
--The following IF statement setup default values of full_i and almost_full_i.
--The values might be overwritten in the next IF statement.
--If writing, then it is not possible to predict how many
--words will actually be in the FIFO after the write concludes
--(because the number of reads which happen in this time can
-- not be determined).
--Therefore, treat it pessimistically and always assume that
-- the write will happen without a read (assume the FIFO is
-- C_DEPTH_RATIO_RD fuller than it is).
--Note:
--1. cntr_size_var_int is the deepest depth between write depth and read depth
-- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain.
--2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle
-- if wr_en=1 (C_DEPTH_RATIO_RD=one write word)
--3. For asymmetric FIFO, if write width is narrower than read width. Don't
-- have to consider partial words.
--4. For asymmetric FIFO, if read width is narrower than write width,
-- the worse case that FIFO is going to full is depicted in the following
-- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a
-- is the worse case. Therefore, in the calculation, actual FIFO depth is
-- substarcted to one write word and added one read word.
-- -------
-- | | |
-- wr_pntr-->| |---
-- | | |
-- ---|---
-- | | |
-- | |---
-- | | |
-- ---|---
-- | | |<--rd_pntr_a
-- | |---
-- | | |<--rd_pntr_b
-- ---|---
-- Update full_i and almost_full_i if user is writing to the FIFO.
-- Assign overflow and wr_ack.
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
-- User is writing to a FIFO which is NOT reporting FULL
IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN
-- FIFO really is Full
--Report Overflow and do not acknowledge the write
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN
-- FIFO is almost full
-- This write will succeed, and FIFO will go FULL
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN
-- FIFO is one away from almost full
-- This write will succeed, and FIFO will go almost_full_i
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
ELSE
-- FIFO is no where near FULL
--Write will succeed, no change in status
FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP
add(head, tail,
DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr,
(width_gt1 & INJECTDBITERR & INJECTSBITERR));
END LOOP;
wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ;
END IF;
ELSE --IF full_i = '1'
-- User is writing to a FIFO which IS reporting FULL
--Write will fail
END IF; --full_i
ELSE --WR_EN/='1'
--No write attempted, so neither overflow or acknowledge
END IF; --WR_EN
END IF; --WR_CLK
---------------------------------------------------------------------------
-- Read from FIFO
---------------------------------------------------------------------------
IF rd_rst_i = '1' THEN
-- Whenever user is attempting to read from
-- an EMPTY FIFO, the core should report an underflow error, even if
-- the core is in a RESET condition.
rd_point <= 0 after C_TCQ;
rd_point_d1 <= 0 after C_TCQ;
rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ;
wr_pntr_rd <= (OTHERS => '0') after C_TCQ;
wr_pntr_q <= (OTHERS => (OTHERS => '0')) after C_TCQ;
-- DRAM resets asynchronously
IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
-- BRAM resets synchronously
IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
END IF;
-- Reset only if ECC is not selected as ECC does not support reset.
IF (C_USE_ECC = 0) THEN
err_type := (OTHERS => '0');
END IF ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
wr_pntr_q <= wr_pntr_q(C_SYNCHRONIZER_STAGE-2 downto 0) & wr_pntr_rd1;
-- Delay the read pointer before passing to WR_CLK domain to accommodate
-- the binary to gray converion
rd_pntr_wr_d1 <= rd_pntr after C_TCQ;
wr_pntr_rd <= wr_pntr_q(C_SYNCHRONIZER_STAGE-1) after C_TCQ;
rd_point_d1 <= rd_point after C_TCQ;
---------------------------------------------------------------------------
-- Read Latency 1
---------------------------------------------------------------------------
--The following IF statement setup default values of empty_i and
--almost_empty_i. The values might be overwritten in the next IF statement.
--Note:
--cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain.
IF (ram_rd_en = '1') THEN
IF empty_comb /= '1' THEN
IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN
--FIFO is going almost empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN
--FIFO is going empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN
--FIFO is empty
ELSE
--FIFO is not empty
FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP
read(tail,
data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),
err_type);
remove(head, tail,cntr);
END LOOP;
rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ;
END IF;
ELSE
--FIFO is empty
END IF;
END IF; --RD_EN
END IF; --RD_CLK
dout_i <= data after C_TCQ;
sbiterr_i <= err_type(0) after C_TCQ;
dbiterr_i <= err_type(1) after C_TCQ;
END PROCESS;
-----------------------------------------------------------------------------
-- Programmable FULL flags
-----------------------------------------------------------------------------
proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE)
BEGIN
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC);
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH);
END IF;
ELSE -- STD
IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input
pf_input_thr_assert_val <= PROG_FULL_THRESH;
ELSE -- Multiple threshold inputs
pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT;
pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE;
END IF;
END IF;
END PROCESS proc_pf_input;
proc_pf: PROCESS(WR_CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
diff_pntr_wr <= 0;
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (ram_wr_en = '0') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ;
ELSIF (ram_wr_en = '1') THEN
diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ;
END IF;
IF (RST_FULL_GEN = '1') THEN
prog_full_reg <= '0' after C_TCQ;
ELSIF (C_PROG_FULL_TYPE = 1) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 2) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 3) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSE
prog_full_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSIF (C_PROG_FULL_TYPE = 4) THEN
IF (full_comb = '0') THEN
IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN
prog_full_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN
prog_full_reg <= '0' after C_TCQ;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
ELSE
prog_full_reg <= prog_full_reg after C_TCQ;
END IF;
END IF; --C_PROG_FULL_TYPE
END IF; -- WR_CLK
END PROCESS proc_pf;
---------------------------------------------------------------------------
-- Programmable EMPTY Flags
---------------------------------------------------------------------------
proc_pe: PROCESS(RD_CLK, rd_rst_i)
VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (rd_rst_i = '1') THEN
diff_pntr_rd <= 0;
prog_empty_reg <= '1';
pe_thr_assert_val := (OTHERS => '0');
pe_thr_negate_val := (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (ram_rd_en = '0') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ;
ELSIF (ram_rd_en = '1') THEN
diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ;
ELSE
diff_pntr_rd <= diff_pntr_rd after C_TCQ;
END IF;
IF (C_PROG_EMPTY_TYPE = 1) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 2) THEN
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 3) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= pe_thr_assert_val) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSE
prog_empty_reg <= '0' after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSIF (C_PROG_EMPTY_TYPE = 4) THEN
-- If empty input threshold is selected, then subtract 2 for FWFT to
-- compensate the FWFT stage, otherwise assign the input value.
IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10";
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10";
ELSE
pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT;
pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE;
END IF;
IF (empty_comb = '0') THEN
IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN
prog_empty_reg <= '1' after C_TCQ;
ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN
prog_empty_reg <= '0' after C_TCQ;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
ELSE
prog_empty_reg <= prog_empty_reg after C_TCQ;
END IF;
END IF; --C_PROG_EMPTY_TYPE
END IF; -- RD_CLK
END PROCESS proc_pe;
-----------------------------------------------------------------------------
-- overflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
povflw: PROCESS (WR_CLK)
BEGIN
IF WR_CLK'event AND WR_CLK = '1' THEN
overflow_i <= full_comb AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE govflw;
-----------------------------------------------------------------------------
-- underflow_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
punflw: PROCESS (RD_CLK)
BEGIN
IF RD_CLK'event AND RD_CLK = '1' THEN
underflow_i <= empty_comb and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE gunflw;
-----------------------------------------------------------------------------
-- wr_ack_i generation: Asynchronous FIFO
-----------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF wr_rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_CLK'event AND WR_CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF WR_EN = '1' THEN
IF full_comb /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
----------------------------------------------------------------------------
-- valid_i generation: Asynchronous FIFO
----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_comb /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------
-- Delay valid_d1
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1
-----------------------------------------------------------------
gv0_as: IF (C_USE_EMBEDDED_REG=1
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF rd_rst_i = '1' THEN
valid_d1 <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN
valid_d1 <= valid_i after C_TCQ;
END IF;
END PROCESS;
END GENERATE gv0_as;
gv1_as: IF NOT (C_USE_EMBEDDED_REG=1
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
valid_d1 <= valid_i;
END GENERATE gv1_as;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Use delayed Valid AND DOUT if we have a LATENCY=2 configurations
-- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 )
--Otherwise, connect the valid and DOUT values up directly, with no
--additional latency.
-----------------------------------------------------------------------------
gv0: IF (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
gv1: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_d1;
END GENERATE gv1;
PROCESS (rd_rst_i , RD_CLK )
BEGIN
IF (rd_rst_i = '1') THEN
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1) THEN
IF (RD_CLK 'event AND RD_CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN
ram_rd_en_d1 <= ram_rd_en after C_TCQ;
IF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
gv1: IF NOT (C_PRELOAD_LATENCY=2
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
gv2a: IF (C_HAS_VALID = 1) GENERATE
valid_out <= valid_i;
END GENERATE gv2a;
DOUT <= dout_i;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END GENERATE gv1;
END GENERATE gnll_afifo;
-------------------------------------------------------------------------------
-- Low Latency Asynchronous FIFO
-------------------------------------------------------------------------------
gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE
TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL ll_afifo_full : std_logic := '0';
SIGNAL ll_afifo_empty : std_logic := '1';
SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0';
SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0';
SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0';
BEGIN
wr_rst_i <= WR_RST;
rd_rst_i <= RD_RST;
write_allow <= WR_EN AND (NOT ll_afifo_full);
read_allow <= RD_EN AND (NOT ll_afifo_empty);
wrptr_proc : PROCESS (WR_CLK,wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
wr_pntr_ll_afifo <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
-------------------------------------------------------------------------------
-- Fill the Memory
-------------------------------------------------------------------------------
wr_mem : PROCESS (WR_CLK)
BEGIN
IF (WR_CLK'event AND WR_CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
rdptr_proc : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
rd_pntr_ll_afifo_q <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ;
END IF;
END PROCESS rdptr_proc;
rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
rd_mem : PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK = '1') THEN
DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ;
END IF;
END PROCESS rd_mem;
-------------------------------------------------------------------------------
-- Generate EMPTY
-------------------------------------------------------------------------------
wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0';
wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector(
(conv_integer(rd_pntr_ll_afifo_q)+1),
C_RD_PNTR_WIDTH)) ELSE '0';
proc_empty : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
ll_afifo_empty <= '1';
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ;
END IF;
END PROCESS proc_empty;
-------------------------------------------------------------------------------
-- Generate FULL
-------------------------------------------------------------------------------
rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+1),
C_WR_PNTR_WIDTH)) ELSE '0';
rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector(
(conv_integer(wr_pntr_ll_afifo)+2),
C_WR_PNTR_WIDTH)) ELSE '0';
proc_full : PROCESS (WR_CLK, wr_rst_i)
BEGIN
IF (wr_rst_i = '1') THEN
ll_afifo_full <= '1';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ;
END IF;
END PROCESS proc_full;
EMPTY <= ll_afifo_empty;
FULL <= ll_afifo_full;
END GENERATE gll_afifo;
END behavioral;
--#############################################################################
--#############################################################################
-- Common Clock FIFO Behavioral Model
--#############################################################################
--#############################################################################
-------------------------------------------------------------------------------
-- Library Declaration
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- Common-Clock Entity Declaration - This is NOT the top-level entity
-------------------------------------------------------------------------------
ENTITY fifo_generator_v11_0_bhv_ss IS
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
RD_EN : IN std_logic := '0';
WR_EN : IN std_logic := '0';
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
EMPTY : OUT std_logic := '1';
FULL : OUT std_logic := '0';
ALMOST_EMPTY : OUT std_logic := '1';
ALMOST_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
PROG_FULL : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v11_0_bhv_ss;
-------------------------------------------------------------------------------
-- Architecture Heading
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v11_0_bhv_ss IS
-----------------------------------------------------------------------------
-- FUNCTION actual_fifo_depth
-- Returns the actual depth of the FIFO (may differ from what the user
-- specified)
--
-- The FIFO depth is always represented as 2^n (16,32,64,128,256)
-- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain
-- options. This function returns the actual depth of the fifo, as seen by
-- the user.
-------------------------------------------------------------------------------
FUNCTION actual_fifo_depth(
C_FIFO_DEPTH : integer;
C_PRELOAD_REGS : integer;
C_PRELOAD_LATENCY : integer;
C_COMMON_CLOCK : integer)
RETURN integer IS
BEGIN
RETURN C_FIFO_DEPTH;
END actual_fifo_depth;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic
-- Returns a single bit (as std_logic) from an integer 1/0 value.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS
BEGIN
IF (value=1) THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END int_2_std_logic;
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
-----------------------------------------------------------------------------
-- FUNCTION get_lesser
-- Returns a minimum value
-------------------------------------------------------------------------------
FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : boolean;
true_case : std_logic;
false_case : std_logic)
RETURN std_logic IS
VARIABLE retval : std_logic := '0';
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--------------------------------------------------------------------------------
-- Constant Declaration
--------------------------------------------------------------------------------
CONSTANT C_FIFO_WR_DEPTH : integer
:= actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1);
CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH);
CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH;
CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0),
C_DIN_WIDTH+2, C_DIN_WIDTH);
CONSTANT OF_INIT_VAL : std_logic := if_then_else((C_HAS_OVERFLOW = 1 AND C_OVERFLOW_LOW = 1),'1','0');
CONSTANT UF_INIT_VAL : std_logic := if_then_else((C_HAS_UNDERFLOW = 1 AND C_UNDERFLOW_LOW = 1),'1','0');
TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Internal Signals
-------------------------------------------------------------------------------
SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow : std_logic := '0';
SIGNAL read_allow : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL full_i : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_full_i : std_logic := '0';
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
SIGNAL rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL wr_ack_i : std_logic := '0';
SIGNAL overflow_i : std_logic := OF_INIT_VAL;
SIGNAL valid_i : std_logic := '0';
SIGNAL valid_d1 : std_logic := '0';
SIGNAL underflow_i : std_logic := UF_INIT_VAL;
--The delayed reset is used to deassert prog_full
SIGNAL rst_q : std_logic := '0';
SIGNAL prog_full_reg : std_logic := '0';
SIGNAL prog_full_noreg : std_logic := '0';
SIGNAL prog_empty_reg : std_logic := '1';
SIGNAL prog_empty_noreg: std_logic := '1';
SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
SIGNAL sbiterr_i : std_logic := '0';
SIGNAL dbiterr_i : std_logic := '0';
SIGNAL ram_rd_en_d1 : std_logic := '0';
SIGNAL mem_pntr : integer := 0;
SIGNAL ram_wr_en_i : std_logic := '0';
SIGNAL ram_rd_en_i : std_logic := '0';
SIGNAL comp1 : std_logic := '0';
SIGNAL comp0 : std_logic := '0';
SIGNAL going_full : std_logic := '0';
SIGNAL leaving_full : std_logic := '0';
SIGNAL ram_full_comb : std_logic := '0';
SIGNAL ecomp1 : std_logic := '0';
SIGNAL ecomp0 : std_logic := '0';
SIGNAL going_empty : std_logic := '0';
SIGNAL leaving_empty : std_logic := '0';
SIGNAL ram_empty_comb : std_logic := '0';
-------------------------------------------------------------------------------
-- architecture begins here
-------------------------------------------------------------------------------
BEGIN
rst_i <= RST;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
END GENERATE gsrst;
--No SRST
nosrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE nosrst;
gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE
SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
diff_count <= wr_pntr - rd_pntr;
gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count;
DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ;
END GENERATE;
gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE
DATA_COUNT <=
diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH);
END GENERATE;
END GENERATE gdc;
gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE
DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc;
-------------------------------------------------------------------------------
--Calculate WR_ACK based on C_WR_ACK_LOW parameters
-------------------------------------------------------------------------------
gwalow : IF (C_WR_ACK_LOW = 0) GENERATE
WR_ACK <= wr_ack_i;
END GENERATE gwalow;
gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE
WR_ACK <= NOT wr_ack_i;
END GENERATE gwahgh;
-------------------------------------------------------------------------------
--Calculate OVERFLOW based on C_OVERFLOW_LOW parameters
-------------------------------------------------------------------------------
govlow : IF (C_OVERFLOW_LOW = 0) GENERATE
OVERFLOW <= overflow_i;
END GENERATE govlow;
govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE
OVERFLOW <= NOT overflow_i;
END GENERATE govhgh;
-------------------------------------------------------------------------------
--Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings
-------------------------------------------------------------------------------
gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnvl : IF (C_VALID_LOW = 0) GENERATE
VALID <= valid_d1;
END GENERATE gnvl;
gnvh : IF (C_VALID_LOW = 1) GENERATE
VALID <= NOT valid_d1;
END GENERATE gnvh;
END GENERATE gvlat1;
-------------------------------------------------------------------------------
-- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings
-------------------------------------------------------------------------------
guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE
gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE
UNDERFLOW <= underflow_i;
END GENERATE gnul;
gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE
UNDERFLOW <= NOT underflow_i;
END GENERATE gnuh;
END GENERATE guflat1;
FULL <= full_i;
ALMOST_FULL <= almost_full_i;
EMPTY <= empty_i;
ALMOST_EMPTY <= almost_empty_i;
write_allow <= WR_EN AND (NOT full_i);
read_allow <= RD_EN AND (NOT empty_i);
wrptr_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
wr_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
wr_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (write_allow = '1') THEN
wr_pntr <= wr_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS wrptr_proc;
gecc_mem: IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gecc_mem;
gnecc_mem: IF NOT (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE
wr_mem : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (write_allow = '1') THEN
memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ;
END IF;
END IF;
END PROCESS wr_mem;
END GENERATE gnecc_mem;
rdptr_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
rd_pntr <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
rd_pntr <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (read_allow = '1') THEN
rd_pntr <= rd_pntr + "1" AFTER C_TCQ;
END IF;
END IF;
END PROCESS rdptr_proc;
-------------------------------------------------------------------------------
-- Generate DOUT for common clock low latency FIFO
-------------------------------------------------------------------------------
gll_dout: IF(C_FIFO_TYPE = 2) GENERATE
SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q;
dout_reg : PROCESS (CLK)
BEGIN
IF (CLK'event AND CLK = '1') THEN
dout_q <= dout_i AFTER C_TCQ;
END IF;
END PROCESS dout_reg;
END GENERATE gll_dout;
gnll_dout: IF (C_FIFO_TYPE < 2) GENERATE
-------------------------------------------------------------------------------
-- Generate DOUT for BRAM
-------------------------------------------------------------------------------
gbm_dout: IF (C_MEMORY_TYPE < 2) GENERATE
BEGIN
rd_mem : PROCESS (CLK)
VARIABLE dout_tmp : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
IF (CLK'event AND CLK = '1') THEN
IF (RST_FULL_FF = '1' OR srst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ;
END IF;
ELSIF (read_allow = '1') THEN
dout_tmp := memory(conv_integer(rd_pntr));
IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) THEN
IF (dout_tmp(dout_tmp'high) = '1') THEN
IF (C_DOUT_WIDTH > 2) THEN
dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 2) & NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ;
ELSIF (C_DOUT_WIDTH = 2) THEN
dout_i <= NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ;
ELSE
dout_i(0) <= dout_tmp(0) AFTER C_TCQ;
END IF;
dbiterr_i <= dout_tmp(dout_tmp'high) AFTER C_TCQ;
sbiterr_i <= '0' AFTER C_TCQ;
ELSE
dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 0) AFTER C_TCQ;
sbiterr_i <= dout_tmp(dout_tmp'high-1) AFTER C_TCQ;
dbiterr_i <= '0' AFTER C_TCQ;
END IF;
ELSE
dout_i <= dout_tmp AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS rd_mem;
END GENERATE gbm_dout;
-------------------------------------------------------------------------------
-- Generate DOUT for DRAM
-------------------------------------------------------------------------------
gdm_dout: IF (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3) GENERATE
rd_mem : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
END IF;
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ;
END IF;
ELSIF (read_allow = '1') THEN
dout_i <= memory(conv_integer(rd_pntr)) AFTER C_TCQ;
END IF;
END IF;
END PROCESS rd_mem;
END GENERATE gdm_dout;
END GENERATE gnll_dout;
-------------------------------------------------------------------------------
-- Generate FULL flag
-------------------------------------------------------------------------------
comp1 <= '1' WHEN (rd_pntr = (wr_pntr + "1")) ELSE '0';
comp0 <= '1' WHEN (rd_pntr = wr_pntr) ELSE '0';
going_full <= (comp1 AND write_allow AND NOT read_allow);
leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN;
ram_full_comb <= going_full OR (NOT leaving_full AND full_i);
full_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
full_i <= ram_full_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS full_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_FULL flag
-------------------------------------------------------------------------------
gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE
SIGNAL fcomp2 : std_logic := '0';
SIGNAL going_afull : std_logic := '0';
SIGNAL leaving_afull : std_logic := '0';
SIGNAL ram_afull_comb : std_logic := '0';
BEGIN
fcomp2 <= '1' WHEN (rd_pntr = (wr_pntr + "10")) ELSE '0';
going_afull <= (fcomp2 AND write_allow AND NOT read_allow);
leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN;
ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i);
af_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSE
almost_full_i <= ram_afull_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS af_proc;
END GENERATE gaf_ss;
-------------------------------------------------------------------------------
-- Generate EMPTY flag
-------------------------------------------------------------------------------
ecomp1 <= '1' WHEN (wr_pntr = (rd_pntr + "1")) ELSE '0';
ecomp0 <= '1' WHEN (wr_pntr = rd_pntr) ELSE '0';
going_empty <= (ecomp1 AND NOT write_allow AND read_allow);
leaving_empty <= (ecomp0 AND write_allow);
ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i);
empty_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
empty_i <= '1' AFTER C_TCQ;
ELSE
empty_i <= ram_empty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_proc;
-------------------------------------------------------------------------------
-- Generate ALMOST_EMPTY flag
-------------------------------------------------------------------------------
gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE
SIGNAL ecomp2 : std_logic := '0';
SIGNAL going_aempty : std_logic := '0';
SIGNAL leaving_aempty : std_logic := '0';
SIGNAL ram_aempty_comb : std_logic := '1';
BEGIN
ecomp2 <= '1' WHEN (wr_pntr = (rd_pntr + "10")) ELSE '0';
going_aempty <= (ecomp2 AND NOT write_allow AND read_allow);
leaving_aempty <= (ecomp1 AND write_allow AND NOT read_allow);
ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i);
ae_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
almost_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
almost_empty_i <= '1' AFTER C_TCQ;
ELSE
almost_empty_i <= ram_aempty_comb AFTER C_TCQ;
END IF;
END IF;
END PROCESS ae_proc;
END GENERATE gae_ss;
-------------------------------------------------------------------------------
-- Generate PROG_FULL and PROG_EMPTY flags
-------------------------------------------------------------------------------
gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE
SIGNAL diff_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL write_allow_q : std_logic := '0';
SIGNAL read_allow_q : std_logic := '0';
SIGNAL write_only : std_logic := '0';
SIGNAL write_only_q : std_logic := '0';
SIGNAL read_only : std_logic := '0';
SIGNAL read_only_q : std_logic := '0';
SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL);
SIGNAL prog_empty_i : std_logic := '1';
CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_ASSERT_VAL - 2, -- FWFT
C_PROG_FULL_THRESH_ASSERT_VAL); -- STD
CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_FULL_THRESH_NEGATE_VAL - 2, -- FWFT
C_PROG_FULL_THRESH_NEGATE_VAL); -- STD
CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2,
C_PROG_EMPTY_THRESH_ASSERT_VAL);
CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL);
BEGIN
write_only <= write_allow AND NOT read_allow;
write_only_q <= write_allow_q AND NOT read_allow_q;
read_only <= read_allow AND NOT write_allow;
read_only_q <= read_allow_q AND NOT write_allow_q;
wr_rd_q_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
write_allow_q <= '0';
read_allow_q <= '0';
diff_pntr <= (OTHERS => '0');
diff_pntr_pe <= (OTHERS => '0');
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
write_allow_q <= '0' AFTER C_TCQ;
read_allow_q <= '0' AFTER C_TCQ;
diff_pntr <= (OTHERS => '0') AFTER C_TCQ;
diff_pntr_pe <= (OTHERS => '0') AFTER C_TCQ;
ELSE
write_allow_q <= write_allow AFTER C_TCQ;
read_allow_q <= read_allow AFTER C_TCQ;
-- Add 1 to the difference pointer value when only write happens.
IF (write_only = '1') THEN
diff_pntr <= wr_pntr - rd_pntr + "1" AFTER C_TCQ;
ELSE
diff_pntr <= wr_pntr - rd_pntr AFTER C_TCQ;
END IF;
-- Add 1 to the difference pointer value when write or both write & read or no write & read happen.
IF (read_only = '1') THEN
diff_pntr_pe <= wr_pntr - rd_pntr - "1" AFTER C_TCQ;
ELSE
diff_pntr_pe <= wr_pntr - rd_pntr AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS wr_rd_q_proc;
-------------------------------------------------------------------------------
-- Generate PROG_FULL flag
-------------------------------------------------------------------------------
gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold constant
-------------------------------------------------------------------------------
gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE
pf1_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf1_proc;
END GENERATE gpf1;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE
pf2_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf2_proc;
END GENERATE gpf2;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for single programmable threshold input port
-------------------------------------------------------------------------------
gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH;
pf3_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) > pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN
IF (read_only_q = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf3_proc;
END GENERATE gpf3;
-------------------------------------------------------------------------------
-- Generate PROG_FULL for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE
SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pf_assert_val <= PROG_FULL_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT;
pf_negate_val <= PROG_FULL_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE;
pf4_proc : PROCESS (CLK, RST_FULL_FF)
BEGIN
IF (RST_FULL_FF = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL);
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ;
ELSIF (RST_FULL_GEN = '1') THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr) >= pf_assert_val) THEN
prog_full_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR
(conv_integer(diff_pntr) < pf_negate_val)) THEN
prog_full_i <= '0' AFTER C_TCQ;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
ELSE
prog_full_i <= prog_full_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pf4_proc;
END GENERATE gpf4;
PROG_FULL <= prog_full_i;
END GENERATE gpf;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY flag
-------------------------------------------------------------------------------
gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold constant
-------------------------------------------------------------------------------
gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE
pe1_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe1_proc;
END GENERATE gpe1;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold constants
-------------------------------------------------------------------------------
gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE
pe2_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe2_proc;
END GENERATE gpe2;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for single programmable threshold input port
-------------------------------------------------------------------------------
gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH;
pe3_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN
IF (write_only_q = '1') THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= '1' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= '0' AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe3_proc;
END GENERATE gpe3;
-------------------------------------------------------------------------------
-- Generate PROG_EMPTY for multiple programmable threshold input ports
-------------------------------------------------------------------------------
gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE
SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL pe_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT;
pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE;
pe4_proc : PROCESS (CLK, rst_i)
BEGIN
IF (rst_i = '1') THEN
prog_empty_i <= '1';
ELSIF (CLK'event AND CLK = '1') THEN
IF (srst_i = '1') THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (almost_full_i = '0') THEN
IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN
prog_empty_i <= '1' AFTER C_TCQ;
ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR
(conv_integer(diff_pntr_pe) > pe_negate_val)) THEN
prog_empty_i <= '0' AFTER C_TCQ;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
ELSE
prog_empty_i <= prog_empty_i AFTER C_TCQ;
END IF;
END IF;
END PROCESS pe4_proc;
END GENERATE gpe4;
PROG_EMPTY <= prog_empty_i;
END GENERATE gpe;
END GENERATE gpf_pe;
-------------------------------------------------------------------------------
-- overflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
govflw: IF (C_HAS_OVERFLOW = 1) GENERATE
povflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
overflow_i <= full_i AND WR_EN after C_TCQ;
END IF;
END PROCESS povflw;
END GENERATE govflw;
-------------------------------------------------------------------------------
-- underflow_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE
punflw: PROCESS (CLK)
BEGIN
IF CLK'event AND CLK = '1' THEN
underflow_i <= empty_i and RD_EN after C_TCQ;
END IF;
END PROCESS punflw;
END GENERATE gunflw;
-------------------------------------------------------------------------------
-- wr_ack_i generation: Synchronous FIFO
-------------------------------------------------------------------------------
gwack: IF (C_HAS_WR_ACK = 1) GENERATE
pwack: PROCESS (CLK,rst_i)
BEGIN
IF rst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
wr_ack_i <= '0' after C_TCQ;
IF srst_i = '1' THEN
wr_ack_i <= '0' after C_TCQ;
ELSIF WR_EN = '1' THEN
IF full_i /= '1' THEN
wr_ack_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS pwack;
END GENERATE gwack;
-----------------------------------------------------------------------------
-- valid_i generation: Synchronous FIFO
-----------------------------------------------------------------------------
gvld_i: IF (C_HAS_VALID = 1) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF rst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF srst_i = '1' THEN
valid_i <= '0' after C_TCQ;
ELSE --srst_i=0
-- Setup default value for underflow and valid
valid_i <= '0' after C_TCQ;
IF RD_EN = '1' THEN
IF empty_i /= '1' THEN
valid_i <= '1' after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE gvld_i;
-----------------------------------------------------------------------------
--Delay Valid AND DOUT
--if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD
-----------------------------------------------------------------------------
gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE
gv0: IF (C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE
PROCESS (rst_i , CLK )
BEGIN
IF (rst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
IF (CLK'event AND CLK = '1') THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
IF (C_USE_ECC = 0) THEN
SBITERR <= '0' after C_TCQ;
DBITERR <= '0' after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (CLK 'event AND CLK = '1') THEN
ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ;
valid_d1 <= valid_i after C_TCQ;
IF (srst_i = '1') THEN
IF (C_USE_DOUT_RST = 1) THEN
DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ram_rd_en_d1 <= '0' after C_TCQ;
valid_d1 <= '0' after C_TCQ;
ELSIF (ram_rd_en_d1 = '1') THEN
DOUT <= dout_i after C_TCQ;
SBITERR <= sbiterr_i after C_TCQ;
DBITERR <= dbiterr_i after C_TCQ;
END IF;
END IF;
END PROCESS;
END GENERATE gv0;
END GENERATE gnll_fifo1;
gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0))
AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE
valid_d1 <= valid_i;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
END GENERATE gv1;
END behavioral;
--#############################################################################
--#############################################################################
-- Preload Latency 0 (First-Word Fall-Through) Module
--#############################################################################
--#############################################################################
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fifo_generator_v11_0_bhv_preload0 IS
GENERIC (
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic := '0';
USERDBITERR : OUT std_logic := '0';
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0) := (OTHERS => '0')
);
END fifo_generator_v11_0_bhv_preload0;
ARCHITECTURE behavioral OF fifo_generator_v11_0_bhv_preload0 IS
-----------------------------------------------------------------------------
-- FUNCTION hexstr_to_std_logic_vec
-- Returns a std_logic_vector for a hexadecimal string
-------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH);
SIGNAL preloadstage1 : std_logic := '0';
SIGNAL preloadstage2 : std_logic := '0';
SIGNAL ram_valid_i : std_logic := '0';
SIGNAL read_data_valid_i : std_logic := '0';
SIGNAL ram_regout_en : std_logic := '0';
SIGNAL ram_rd_en : std_logic := '0';
SIGNAL empty_i : std_logic := '1';
SIGNAL empty_q : std_logic := '1';
SIGNAL rd_en_q : std_logic := '0';
SIGNAL almost_empty_i : std_logic := '1';
SIGNAL almost_empty_q : std_logic := '1';
SIGNAL rd_rst_i : std_logic := '0';
SIGNAL srst_i : std_logic := '0';
BEGIN -- behavioral
grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
rd_rst_i <= RD_RST;
end generate grst;
ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE
rd_rst_i <= '0';
END GENERATE ngrst;
--SRST
gsrst : IF (C_HAS_SRST=1) GENERATE
srst_i <= SRST;
END GENERATE gsrst;
--SRST
ngsrst : IF (C_HAS_SRST=0) GENERATE
srst_i <= '0';
END GENERATE ngsrst;
gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE
CONSTANT INVALID : std_logic_vector (1 downto 0) := "00";
CONSTANT STAGE1_VALID : std_logic_vector (1 downto 0) := "10";
CONSTANT STAGE2_VALID : std_logic_vector (1 downto 0) := "01";
CONSTANT BOTH_STAGES_VALID : std_logic_vector (1 downto 0) := "11";
SIGNAL curr_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
SIGNAL next_fwft_state : std_logic_vector (1 DOWNTO 0) := INVALID;
BEGIN
proc_fwft_fsm : PROCESS ( curr_fwft_state, RD_EN, FIFOEMPTY)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
IF (FIFOEMPTY = '0') THEN
next_fwft_state <= STAGE1_VALID;
ELSE --FIFOEMPTY = '1'
next_fwft_state <= INVALID;
END IF;
WHEN STAGE1_VALID =>
IF (FIFOEMPTY = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSE -- FIFOEMPTY = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN STAGE2_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= INVALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= STAGE1_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '0') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- FIFOEMPTY = '1' AND RD_EN = '0'
next_fwft_state <= STAGE2_VALID;
END IF;
WHEN BOTH_STAGES_VALID =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_fwft_state <= STAGE2_VALID;
ELSIF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
next_fwft_state <= BOTH_STAGES_VALID;
ELSE -- RD_EN = '0'
next_fwft_state <= BOTH_STAGES_VALID;
END IF;
WHEN OTHERS =>
next_fwft_state <= INVALID;
END CASE;
END PROCESS proc_fwft_fsm;
proc_fsm_reg: PROCESS (rd_rst_i, RD_CLK)
BEGIN
IF (rd_rst_i = '1') THEN
curr_fwft_state <= INVALID;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
curr_fwft_state <= INVALID AFTER C_TCQ;
ELSE
curr_fwft_state <= next_fwft_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_fsm_reg;
proc_regen: PROCESS (curr_fwft_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_fwft_state IS
WHEN INVALID =>
STAGE2_REG_EN <= '0';
WHEN STAGE1_VALID =>
STAGE2_REG_EN <= '1';
WHEN STAGE2_VALID =>
STAGE2_REG_EN <= '0';
WHEN BOTH_STAGES_VALID =>
IF (RD_EN = '1') THEN
STAGE2_REG_EN <= '1';
ELSE
STAGE2_REG_EN <= '0';
END IF;
WHEN OTHERS =>
STAGE2_REG_EN <= '0';
END CASE;
END PROCESS proc_regen;
VALID_STAGES <= curr_fwft_state;
--------------------------------------------------------------------------------
-- preloadstage2 indicates that stage2 needs to be updated. This is true
-- whenever read_data_valid is false, and RAM_valid is true.
--------------------------------------------------------------------------------
preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN);
--------------------------------------------------------------------------------
-- preloadstage1 indicates that stage1 needs to be updated. This is true
-- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
-- false (indicating that Stage1 needs updating), or preloadstage2 is active
-- (indicating that Stage2 is going to update, so Stage1, therefore, must
-- also be updated to keep it valid.
--------------------------------------------------------------------------------
preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY));
--------------------------------------------------------------------------------
-- Calculate RAM_REGOUT_EN
-- The output registers are controlled by the ram_regout_en signal.
-- These registers should be updated either when the output in Stage2 is
-- invalid (preloadstage2), OR when the user is reading, in which case the
-- Stage2 value will go invalid unless it is replenished.
--------------------------------------------------------------------------------
ram_regout_en <= preloadstage2;
--------------------------------------------------------------------------------
-- Calculate RAM_RD_EN
-- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
-- update the value in Stage1.
-- One case when this happens is when preloadstage1=true, which indicates
-- that the data in Stage1 or Stage2 is invalid, and needs to automatically
-- be updated.
-- The other case is when the user is reading from the FIFO, which guarantees
-- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
-- replinished by data from the memory. So, as long as the RAM has data in it,
-- a read of the RAM should occur.
--------------------------------------------------------------------------------
ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1;
END GENERATE gnll_fifo;
gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE
SIGNAL empty_d1 : STD_LOGIC := '1';
SIGNAL fe_of_empty : STD_LOGIC := '0';
SIGNAL curr_state : STD_LOGIC := '0';
SIGNAL next_state : STD_LOGIC := '0';
SIGNAL leaving_empty_fwft : STD_LOGIC := '0';
SIGNAL going_empty_fwft : STD_LOGIC := '0';
BEGIN
fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
next_state <= '1';
ELSE
next_state <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
next_state <= '0';
ELSE
next_state <= '1';
END IF;
WHEN OTHERS =>
next_state <= '0';
END CASE;
END PROCESS fsm_proc;
empty_reg: PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i = '1') THEN
empty_d1 <= '1';
empty_i <= '1';
ram_valid_i <= '0';
curr_state <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i = '1') THEN
empty_d1 <= '1' AFTER C_TCQ;
empty_i <= '1' AFTER C_TCQ;
ram_valid_i <= '0' AFTER C_TCQ;
curr_state <= '0' AFTER C_TCQ;
ELSE
empty_d1 <= FIFOEMPTY AFTER C_TCQ;
curr_state <= next_state AFTER C_TCQ;
empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ;
ram_valid_i <= next_state AFTER C_TCQ;
END IF;
END IF;
END PROCESS empty_reg;
fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY);
prege: PROCESS (curr_state, FIFOEMPTY, RD_EN)
BEGIN
CASE curr_state IS
WHEN '0' =>
IF (FIFOEMPTY = '0') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN '1' =>
IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN
ram_regout_en <= '1';
ram_rd_en <= '1';
ELSE
ram_regout_en <= '0';
ram_rd_en <= '0';
END IF;
WHEN OTHERS =>
ram_regout_en <= '0';
ram_rd_en <= '0';
END CASE;
END PROCESS prege;
ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty
BEGIN
CASE curr_state IS
WHEN '0' =>
leaving_empty_fwft <= fe_of_empty;
WHEN '1' =>
leaving_empty_fwft <= '1';
WHEN OTHERS =>
leaving_empty_fwft <= '0';
END CASE;
END PROCESS ple;
pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty
BEGIN
CASE curr_state IS
WHEN '1' =>
IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN
going_empty_fwft <= '1';
ELSE
going_empty_fwft <= '0';
END IF;
WHEN OTHERS =>
going_empty_fwft <= '0';
END CASE;
END PROCESS pge;
END GENERATE gll_fifo;
--------------------------------------------------------------------------------
-- Calculate ram_valid
-- ram_valid indicates that the data in Stage1 is valid.
--
-- If the RAM is being read from on this clock cycle (ram_rd_en=1), then
-- ram_valid is certainly going to be true.
-- If the RAM is not being read from, but the output registers are being
-- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
-- therefore causing ram_valid to be false.
-- Otherwise, ram_valid will remain unchanged.
--------------------------------------------------------------------------------
gvalid: IF (C_FIFO_TYPE < 2) GENERATE
regout_valid: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_valid
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
ram_valid_i <= '0' after C_TCQ;
ELSE
IF ram_rd_en = '1' THEN
ram_valid_i <= '1' after C_TCQ;
ELSE
IF ram_regout_en = '1' THEN
ram_valid_i <= '0' after C_TCQ;
ELSE
ram_valid_i <= ram_valid_i after C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS regout_valid;
END GENERATE gvalid;
--------------------------------------------------------------------------------
-- Calculate READ_DATA_VALID
-- READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
-- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
-- such that the data in Stage1 is propogated into Stage2.
--------------------------------------------------------------------------------
regout_dvalid : PROCESS (RD_CLK, rd_rst_i)
BEGIN
IF (rd_rst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
read_data_valid_i <= '0' after C_TCQ;
ELSE
read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_dvalid;
-------------------------------------------------------------------------------
-- Calculate EMPTY
-- Defined as the inverse of READ_DATA_VALID
--
-- Description:
--
-- If read_data_valid_i indicates that the output is not valid,
-- and there is no valid data on the output of the ram to preload it
-- with, then we will report empty.
--
-- If there is no valid data on the output of the ram and we are
-- reading, then the FIFO will go empty.
--
-------------------------------------------------------------------------------
gempty: IF (C_FIFO_TYPE < 2) GENERATE
regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i)
BEGIN
IF (rd_rst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (srst_i='1') THEN
empty_i <= '1' after C_TCQ;
ELSE
empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ;
END IF;
END IF; --RD_CLK
END PROCESS regout_empty;
END GENERATE gempty;
regout_empty_q: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN --
empty_q <= empty_i after C_TCQ;
END IF;
END PROCESS regout_empty_q;
regout_rd_en: PROCESS (RD_CLK)
BEGIN -- PROCESS regout_rd_en
IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
rd_en_q <= RD_EN after C_TCQ;
END IF;
END PROCESS regout_rd_en;
-------------------------------------------------------------------------------
-- Calculate user_almost_empty
-- user_almost_empty is defined such that, unless more words are written
-- to the FIFO, the next read will cause the FIFO to go EMPTY.
--
-- In most cases, whenever the output registers are updated (due to a user
-- read or a preload condition), then user_almost_empty will update to
-- whatever RAM_EMPTY is.
--
-- The exception is when the output is valid, the user is not reading, and
-- Stage1 is not empty. In this condition, Stage1 will be preloaded from the
-- memory, so we need to make sure user_almost_empty deasserts properly under
-- this condition.
-------------------------------------------------------------------------------
regout_aempty: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_empty
IF rd_rst_i = '1' THEN -- asynchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF srst_i = '1' THEN -- synchronous reset (active high)
almost_empty_i <= '1' after C_TCQ;
almost_empty_q <= '1' after C_TCQ;
ELSE
IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN
almost_empty_i <= FIFOEMPTY after C_TCQ;
END IF;
almost_empty_q <= almost_empty_i after C_TCQ;
END IF;
END IF;
END PROCESS regout_aempty;
USEREMPTY <= empty_i;
USERALMOSTEMPTY <= almost_empty_i;
FIFORDEN <= ram_rd_en;
RAMVALID <= ram_valid_i;
guvh: IF C_USERVALID_LOW=0 GENERATE
USERVALID <= read_data_valid_i;
END GENERATE guvh;
guvl: if C_USERVALID_LOW=1 GENERATE
USERVALID <= NOT read_data_valid_i;
END GENERATE guvl;
gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE
USERUNDERFLOW <= empty_q AND rd_en_q;
END GENERATE gufh;
gufl: if C_USERUNDERFLOW_LOW=1 GENERATE
USERUNDERFLOW <= NOT (empty_q AND rd_en_q);
END GENERATE gufl;
regout_lat0: PROCESS (RD_CLK, rd_rst_i)
BEGIN -- PROCESS regout_lat0
IF (rd_rst_i = '1') THEN -- asynchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
-- DRAM resets asynchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
-- BRAM resets synchronously
IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN
IF (RD_CLK'event AND RD_CLK = '1') THEN
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
END IF;
ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge
IF (srst_i = '1') THEN -- synchronous reset (active high)
IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF
USERSBITERR <= '0' after C_TCQ;
USERDBITERR <= '0' after C_TCQ;
END IF;
IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high)
USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ;
END IF;
ELSE
IF (ram_regout_en = '1') THEN
USERDATA_int <= FIFODATA after C_TCQ;
USERSBITERR <= FIFOSBITERR after C_TCQ;
USERDBITERR <= FIFODBITERR after C_TCQ;
END IF;
END IF;
END IF;
END PROCESS regout_lat0;
USERDATA <= USERDATA_int ; -- rle, fixed bug R62
END behavioral;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for Conventional FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v11_0;
USE fifo_generator_v11_0.fifo_generator_v11_0_bhv_as;
USE fifo_generator_v11_0.fifo_generator_v11_0_bhv_ss;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the conventional
-- FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v11_0_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END fifo_generator_v11_0_conv;
-------------------------------------------------------------------------------
-- Definition of Parameters
-------------------------------------------------------------------------------
-- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
-- C_COUNT_TYPE : --not used
-- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
-- C_DEFAULT_VALUE : --not used
-- C_DIN_WIDTH : Width of DIN bus
-- C_DOUT_RST_VAL : Reset value of DOUT
-- C_DOUT_WIDTH : Width of DOUT bus
-- C_ENABLE_RLOCS : --not used
-- C_FAMILY : not used in bhv model
-- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
-- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
-- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
-- C_HAS_BACKUP : --not used
-- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
-- C_HAS_INT_CLK : not used in bhv model
-- C_HAS_MEMINIT_FILE : --not used
-- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
-- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
-- C_HAS_RD_RST : --not used
-- C_HAS_RST : 1=Core has Async Rst
-- C_HAS_SRST : 1=Core has Sync Rst
-- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
-- C_HAS_VALID : 1=Core has VALID flag
-- C_HAS_WR_ACK : 1=Core has WR_ACK flag
-- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
-- C_HAS_WR_RST : --not used
-- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
-- 1=Common-Clock ShiftRam
-- 2=Indep. Clocks Bram/Dram
-- 3=Virtex-4 Built-in
-- 4=Virtex-5 Built-in
-- C_INIT_WR_PNTR_VAL : --not used
-- C_MEMORY_TYPE : 1=Block RAM
-- 2=Distributed RAM
-- 3=Shift RAM
-- 4=Built-in FIFO
-- C_MIF_FILE_NAME : --not used
-- C_OPTIMIZATION_MODE : --not used
-- C_OVERFLOW_LOW : 1=OVERFLOW active low
-- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
-- C_PRELOAD_REGS : 1=Use output registers
-- C_PRIM_FIFO_TYPE : not used in bhv model
-- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
-- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
-- C_PROG_EMPTY_TYPE : 0=No programmable empty
-- 1=Single prog empty thresh constant
-- 2=Multiple prog empty thresh constants
-- 3=Single prog empty thresh input
-- 4=Multiple prog empty thresh inputs
-- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
-- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
-- C_PROG_FULL_TYPE : 0=No prog full
-- 1=Single prog full thresh constant
-- 2=Multiple prog full thresh constants
-- 3=Single prog full thresh input
-- 4=Multiple prog full thresh inputs
-- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
-- C_RD_DEPTH : Depth of read interface (2^N)
-- C_RD_FREQ : not used in bhv model
-- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
-- C_UNDERFLOW_LOW : 1=UNDERFLOW active low
-- C_USE_DOUT_RST : 1=Resets DOUT on RST
-- C_USE_ECC : not used in bhv model
-- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
-- C_USE_FIFO16_FLAGS : not used in bhv model
-- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
-- C_VALID_LOW : 1=VALID active low
-- C_WR_ACK_LOW : 1=WR_ACK active low
-- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
-- C_WR_DEPTH : Depth of write interface (2^N)
-- C_WR_FREQ : not used in bhv model
-- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
-- C_WR_RESPONSE_LATENCY : --not used
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- BACKUP : Not used
-- BACKUP_MARKER: Not used
-- CLK : Clock
-- DIN : Input data bus
-- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
-- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
-- PROG_FULL_THRESH : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
-- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
-- RD_CLK : Read Domain Clock
-- RD_EN : Read enable
-- RD_RST : Not used
-- RST : Asynchronous Reset
-- SRST : Synchronous Reset
-- WR_CLK : Write Domain Clock
-- WR_EN : Write enable
-- WR_RST : Not used
-- INT_CLK : Internal Clock
-- ALMOST_EMPTY : One word remaining in FIFO
-- ALMOST_FULL : One empty space remaining in FIFO
-- DATA_COUNT : Number of data words in fifo( synchronous to CLK)
-- DOUT : Output data bus
-- EMPTY : Empty flag
-- FULL : Full flag
-- OVERFLOW : Last write rejected
-- PROG_EMPTY : Programmable Empty Flag
-- PROG_FULL : Programmable Full Flag
-- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
-- UNDERFLOW : Last read rejected
-- VALID : Last read acknowledged, DOUT bus VALID
-- WR_ACK : Last write acknowledged
-- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
-- SBITERR : Single Bit ECC Error Detected
-- DBITERR : Double Bit ECC Error Detected
-------------------------------------------------------------------------------
ARCHITECTURE behavioral OF fifo_generator_v11_0_conv IS
-----------------------------------------------------------------------------
-- FUNCTION two_comp
-- Returns a 2's complement value
-------------------------------------------------------------------------------
FUNCTION two_comp(
vect : std_logic_vector)
RETURN std_logic_vector IS
VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0);
VARIABLE toggle : integer := 0;
BEGIN
FOR i IN 0 TO vect'high LOOP
IF (toggle = 1) THEN
IF (vect(i) = '0') THEN
local_vect(i) := '1';
ELSE
local_vect(i) := '0';
END IF;
ELSE
local_vect(i) := vect(i);
IF (vect(i) = '1') THEN
toggle := 1;
END IF;
END IF;
END LOOP;
RETURN local_vect;
END two_comp;
-----------------------------------------------------------------------------
-- FUNCTION int_2_std_logic_vector
-- Returns a std_logic_vector for an integer value for a given width.
-------------------------------------------------------------------------------
FUNCTION int_2_std_logic_vector(
value, bitwidth : integer )
RETURN std_logic_vector IS
VARIABLE running_value : integer := value;
VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0);
BEGIN
IF (value < 0) THEN
running_value := -1 * value;
END IF;
FOR i IN 0 TO bitwidth-1 LOOP
IF running_value MOD 2 = 0 THEN
running_result(i) := '0';
ELSE
running_result(i) := '1';
END IF;
running_value := running_value/2;
END LOOP;
IF (value < 0) THEN -- find the 2s complement
RETURN two_comp(running_result);
ELSE
RETURN running_result;
END IF;
END int_2_std_logic_vector;
COMPONENT fifo_generator_v11_0_bhv_as
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations
--------------------------------------------------------------------------------
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 2;
C_HAS_RST : integer := 1;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 2;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
RD_CLK : IN std_logic;
RD_EN : IN std_logic;
RD_EN_USER : IN std_logic;
RST : IN std_logic;
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
WR_RST : IN std_logic;
RD_RST : IN std_logic;
WR_CLK : IN std_logic;
WR_EN : IN std_logic;
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
USER_EMPTY_FB : IN std_logic := '1';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v11_0_bhv_ss
GENERIC (
--------------------------------------------------------------------------------
-- Generic Declarations (alphabetical)
--------------------------------------------------------------------------------
C_DATA_COUNT_WIDTH : integer := 2;
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RST : integer := 0;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DEPTH : integer := 256;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_ECC : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DEPTH : integer := 256;
C_WR_PNTR_WIDTH : integer := 8;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
RST : IN std_logic := '0';
RST_FULL_GEN : IN std_logic := '0';
RST_FULL_FF : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
ALMOST_EMPTY : OUT std_logic;
ALMOST_FULL : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic;
OVERFLOW : OUT std_logic;
PROG_EMPTY : OUT std_logic;
PROG_FULL : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
WR_ACK : OUT std_logic;
DBITERR : OUT std_logic := '0';
SBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v11_0_bhv_preload0
GENERIC (
C_DOUT_RST_VAL : string;
C_DOUT_WIDTH : integer;
C_HAS_RST : integer;
C_HAS_SRST : integer;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USERVALID_LOW : integer := 0;
C_USERUNDERFLOW_LOW : integer := 0;
C_TCQ : time := 100 ps;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0
);
PORT (
RD_CLK : IN std_logic;
RD_RST : IN std_logic;
SRST : IN std_logic;
RD_EN : IN std_logic;
FIFOEMPTY : IN std_logic;
FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FIFOSBITERR : IN std_logic;
FIFODBITERR : IN std_logic;
USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
USERVALID : OUT std_logic;
USERUNDERFLOW : OUT std_logic;
USEREMPTY : OUT std_logic;
USERALMOSTEMPTY : OUT std_logic;
RAMVALID : OUT std_logic;
FIFORDEN : OUT std_logic;
USERSBITERR : OUT std_logic;
USERDBITERR : OUT std_logic;
STAGE2_REG_EN : OUT std_logic;
VALID_STAGES : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
-- Constant to have clock to register delay
CONSTANT C_TCQ : time := 100 ps;
SIGNAL zero : std_logic := '0';
SIGNAL CLK_INT : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals for delayed input signals
-- All the input signals except Clock are delayed by 100 ps and then given to
-- the models.
-----------------------------------------------------------------------------
SIGNAL rst_delayed : std_logic := '0';
SIGNAL srst_delayed : std_logic := '0';
SIGNAL wr_rst_delayed : std_logic := '0';
SIGNAL rd_rst_delayed : std_logic := '0';
SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_en_delayed : std_logic := '0';
SIGNAL rd_en_delayed : std_logic := '0';
SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL injectdbiterr_delayed : std_logic := '0';
SIGNAL injectsbiterr_delayed : std_logic := '0';
-----------------------------------------------------------------------------
-- Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
SIGNAL rd_en_fifo_in : std_logic;
SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fifo_out : std_logic;
SIGNAL almost_empty_fifo_out : std_logic;
SIGNAL valid_fifo_out : std_logic;
SIGNAL underflow_fifo_out : std_logic;
SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL SS_FWFT_RD : std_logic := '0' ;
SIGNAL SS_FWFT_WR : std_logic := '0' ;
SIGNAL FULL_int : std_logic ;
SIGNAL almost_full_i : std_logic ;
SIGNAL prog_full_i : std_logic ;
SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
signal valid_p0_out : std_logic;
signal empty_p0_out : std_logic;
signal underflow_p0_out : std_logic;
signal almost_empty_p0_out : std_logic;
signal empty_p0_out_q : std_logic;
signal almost_empty_p0_out_q : std_logic;
SIGNAL ram_valid : std_logic; --Internal signal used to monitor the
--ram_valid state
signal rst_fwft : std_logic;
signal sbiterr_fifo_out : std_logic;
signal dbiterr_fifo_out : std_logic;
signal wr_rst_i : std_logic := '0';
signal rd_rst_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal rst_full_gen_i : std_logic := '0';
signal rst_full_ff_i : std_logic := '0';
signal rst_2_sync : std_logic := '0';
signal clk_2_sync : std_logic := '0';
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-----------------------------------------------------------------------------
-- FUNCTION log2roundup
-- Returns a log2 of the input value
-----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : integer)
RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL);
CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0);
CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0);
BEGIN
rst_delayed <= RST AFTER C_TCQ;
srst_delayed <= SRST AFTER C_TCQ;
wr_rst_delayed <= WR_RST AFTER C_TCQ;
rd_rst_delayed <= RD_RST AFTER C_TCQ;
din_delayed <= DIN AFTER C_TCQ;
wr_en_delayed <= WR_EN AFTER C_TCQ;
rd_en_delayed <= RD_EN AFTER C_TCQ;
prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ;
prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ;
prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ;
prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ;
prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ;
prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ;
injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ;
injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ;
--Assign Ground Signal
zero <= '0';
ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado." SEVERITY FAILURE;
--
ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE;
ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE;
ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE;
gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1) OR (C_MEMORY_TYPE = 4)) GENERATE
fgss : fifo_generator_v11_0_bhv_ss
GENERIC MAP (
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_MEMORY_TYPE => if_then_else(C_MEMORY_TYPE = 4, 1, C_MEMORY_TYPE),
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
CLK => CLK,
DIN => din_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
RD_EN => rd_en_fifo_in,
RST => rst_i,
SRST => srst_delayed,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_EN => wr_en_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
--Outputs
ALMOST_EMPTY => almost_empty_fifo_out,
ALMOST_FULL => almost_full_i,
DATA_COUNT => data_count_fifo_out,
DOUT => dout_fifo_out,
EMPTY => empty_fifo_out,
FULL => FULL_int,
OVERFLOW => OVERFLOW,
PROG_EMPTY => PROG_EMPTY,
PROG_FULL => prog_full_i,
UNDERFLOW => underflow_fifo_out,
VALID => valid_fifo_out,
WR_ACK => WR_ACK,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_ss;
gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE
fgas : fifo_generator_v11_0_bhv_as
GENERIC MAP (
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => if_then_else((C_AXI_TYPE = 0 AND C_FIFO_TYPE = 1), 1, C_HAS_ALMOST_FULL),
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RST => C_HAS_RST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_ECC => C_USE_ECC,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_TCQ => C_TCQ,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP(
--Inputs
WR_CLK => WR_CLK,
RD_CLK => RD_CLK,
RST => rst_i,
RST_FULL_GEN => rst_full_gen_i,
RST_FULL_FF => rst_full_ff_i,
WR_RST => wr_rst_i,
RD_RST => rd_rst_i,
DIN => din_delayed,
RD_EN => rd_en_fifo_in,
WR_EN => wr_en_delayed,
RD_EN_USER => rd_en_delayed,
PROG_FULL_THRESH => prog_full_thresh_delayed,
PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed,
PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed,
PROG_EMPTY_THRESH => prog_empty_thresh_delayed,
PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed,
PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed,
INJECTDBITERR => injectdbiterr_delayed,
INJECTSBITERR => injectsbiterr_delayed,
USER_EMPTY_FB => empty_p0_out,
--Outputs
DOUT => dout_fifo_out,
FULL => FULL_int,
ALMOST_FULL => almost_full_i,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => empty_fifo_out,
ALMOST_EMPTY => almost_empty_fifo_out,
VALID => valid_fifo_out,
UNDERFLOW => underflow_fifo_out,
RD_DATA_COUNT => rd_data_count_fifo_out,
WR_DATA_COUNT => wr_data_count_fifo_out,
PROG_FULL => prog_full_i,
PROG_EMPTY => PROG_EMPTY,
DBITERR => dbiterr_fifo_out,
SBITERR => sbiterr_fifo_out
);
END GENERATE gen_as;
ALMOST_FULL <= almost_full_i;
PROG_FULL <= prog_full_i;
-------------------------------------------------------------------------
-- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK ---
-------------------------------------------------------------------------
clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE
CLK_INT <= CLK;
END GENERATE clock_fwft_common;
clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE
CLK_INT <= RD_CLK;
END GENERATE clock_fwft;
-----------------------------------------------------------------------------
-- Connect Internal Signals
-- In the normal case, these signals tie directly to the FIFO's inputs and
-- outputs.
-- In the case of Preload Latency 0 or 1, these are the intermediate
-- signals between the internal FIFO and the preload logic.
-----------------------------------------------------------------------------
latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE
rd_en_fifo_in <= rd_en_delayed;
DOUT <= dout_fifo_out;
VALID <= valid_fifo_out;
EMPTY <= empty_fifo_out;
ALMOST_EMPTY <= almost_empty_fifo_out;
UNDERFLOW <= underflow_fifo_out;
RD_DATA_COUNT <= rd_data_count_fifo_out;
WR_DATA_COUNT <= wr_data_count_fifo_out;
SBITERR <= sbiterr_fifo_out;
DBITERR <= dbiterr_fifo_out;
END GENERATE latnrm;
lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE
SIGNAL sbiterr_fwft : STD_LOGIC := '0';
SIGNAL dbiterr_fwft : STD_LOGIC := '0';
SIGNAL rd_en_to_fwft_fifo : STD_LOGIC := '0';
SIGNAL dout_fwft : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
SIGNAL empty_fwft : STD_LOGIC := '0';
SIGNAL valid_stages_i : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL stage2_reg_en_i : STD_LOGIC := '0';
BEGIN
rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
lat0logic : fifo_generator_v11_0_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => C_FIFO_TYPE
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
RD_EN => rd_en_to_fwft_fifo,
FIFOEMPTY => empty_fifo_out,
FIFODATA => dout_fifo_out,
FIFOSBITERR => sbiterr_fifo_out,
FIFODBITERR => dbiterr_fifo_out,
USERDATA => dout_fwft,
USERVALID => valid_p0_out,
USEREMPTY => empty_fwft,
USERALMOSTEMPTY => almost_empty_p0_out,
USERUNDERFLOW => underflow_p0_out,
RAMVALID => ram_valid, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_fifo_in,
USERSBITERR => sbiterr_fwft,
USERDBITERR => dbiterr_fwft,
STAGE2_REG_EN => stage2_reg_en_i,
VALID_STAGES => valid_stages_i
);
gberr_non_pkt_fifo: IF (C_FIFO_TYPE /= 1) GENERATE
VALID <= valid_p0_out;
ALMOST_EMPTY <= almost_empty_p0_out;
UNDERFLOW <= underflow_p0_out;
SBITERR <= sbiterr_fwft;
DBITERR <= dbiterr_fwft;
dout_p0_out <= dout_fwft;
rd_en_to_fwft_fifo <= rd_en_delayed;
empty_p0_out <= empty_fwft;
END GENERATE gberr_non_pkt_fifo;
rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) GENERATE
eclk: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk;
rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc;
END GENERATE rdcg;
rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH)) GENERATE
eclk1: PROCESS (CLK_INT,rst_fwft)
BEGIN -- process eclk
IF (rst_fwft='1') THEN
empty_p0_out_q <= '1' after C_TCQ;
almost_empty_p0_out_q <= '1' after C_TCQ;
ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge
empty_p0_out_q <= empty_p0_out after C_TCQ;
almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ;
END IF;
END PROCESS eclk1;
rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q,
almost_empty_p0_out_q,rst_fwft)
BEGIN -- process rcsproc
IF (empty_p0_out_q='1' OR rst_fwft='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSIF (almost_empty_p0_out_q='1') THEN
RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH);
ELSE
RD_DATA_COUNT <= rd_data_count_fifo_out ;
END IF;
END PROCESS rcsproc1;
END GENERATE rdcg1;
nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE
RD_DATA_COUNT <= rd_data_count_fifo_out;
END GENERATE nrdcg;
WR_DATA_COUNT <= wr_data_count_fifo_out;
---------------------------------------------------
-- logics for common-clock data count with fwft
-- For common-clock FIFOs with FWFT, data count
-- is calculated as an up-down counter to maintain
-- accuracy.
---------------------------------------------------
grd_en_npkt: IF (C_FIFO_TYPE /= 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ;
END GENERATE ngfwft_rd;
END GENERATE grd_en_npkt;
grd_en_pkt: IF (C_FIFO_TYPE = 1) GENERATE
gfwft_rd: IF (C_VALID_LOW = 0) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND valid_p0_out ;
END GENERATE gfwft_rd;
ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE
SS_FWFT_RD <= (NOT empty_p0_out) AND rd_en_delayed AND (NOT valid_p0_out);
END GENERATE ngfwft_rd;
END GENERATE grd_en_pkt;
SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ;
cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE
count_fwft: PROCESS (CLK, rst_fwft)
BEGIN
IF (rst_fwft = '1' AND C_HAS_RST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSIF CLK'event AND CLK = '1' THEN
IF (srst_delayed='1' AND C_HAS_SRST=1) THEN
DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ;
ELSE
IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ;
ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN
DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ;
ELSE
DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ;
END IF ;
END IF;
END IF;
END PROCESS count_fwft;
END GENERATE cc_data_cnt;
----------------------------------------------
DOUT <= dout_p0_out;
EMPTY <= empty_p0_out;
gpkt_fifo_fwft: IF (C_FIFO_TYPE = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_plus1 : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_pkt_count_reg : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL eop_at_stage2 : STD_LOGIC := '0';
SIGNAL ram_pkt_empty : STD_LOGIC := '0';
SIGNAL ram_pkt_empty_d1 : STD_LOGIC := '0';
SIGNAL pkt_ready_to_read : STD_LOGIC := '0';
SIGNAL fwft_stage1_valid : STD_LOGIC := '0';
SIGNAL fwft_stage2_valid : STD_LOGIC := '0';
SIGNAL rd_en_2_stage2 : STD_LOGIC := '0';
SIGNAL ram_wr_en_pkt_fifo : STD_LOGIC := '0';
SIGNAL wr_eop : STD_LOGIC := '0';
SIGNAL dummy_wr_eop : STD_LOGIC := '0';
SIGNAL ram_rd_en_compare : STD_LOGIC := '0';
SIGNAL partial_packet : STD_LOGIC := '0';
SIGNAL wr_rst_fwft_pkt_fifo : STD_LOGIC := '0';
SIGNAL stage1_eop : STD_LOGIC := '0';
SIGNAL stage1_eop_d1 : STD_LOGIC := '0';
SIGNAL rd_en_fifo_in_d1 : STD_LOGIC := '0';
BEGIN
wr_rst_fwft_pkt_fifo <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0';
-- Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
-- When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
-- When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
-- write packet count
gdummy_wr_eop: IF (C_AXI_TYPE = 0) GENERATE
SIGNAL packet_empty_wr : std_logic := '1';
BEGIN
proc_dummy_wr_eop: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
partial_packet <= '0';
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed = '1') THEN
partial_packet <= '0' AFTER C_TCQ;
ELSE
IF (almost_full_i = '1' AND ram_wr_en_pkt_fifo = '1' AND packet_empty_wr = '1' AND din_delayed(0) = '0') THEN
partial_packet <= '1' AFTER C_TCQ;
ELSE
IF (partial_packet = '1' AND din_delayed(0) = '1' AND ram_wr_en_pkt_fifo = '1') THEN
partial_packet <= '0' AFTER C_TCQ;
END IF;
END IF;
END IF;
END IF;
END PROCESS proc_dummy_wr_eop;
dummy_wr_eop <= almost_full_i AND ram_wr_en_pkt_fifo AND packet_empty_wr AND (NOT din_delayed(0)) AND (NOT partial_packet);
-- Synchronize the packet EMPTY in WR clock domain to generate the dummy WR_EOP
gpkt_empty_sync: IF (C_COMMON_CLOCK = 0) GENERATE
TYPE pkt_empty_array IS ARRAY (0 TO C_SYNCHRONIZER_STAGE-1) OF STD_LOGIC;
SIGNAL pkt_empty_sync : pkt_empty_array := (OTHERS => '1');
BEGIN
proc_empty_sync: PROCESS (wr_rst_fwft_pkt_fifo, WR_CLK)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
pkt_empty_sync <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
pkt_empty_sync <= pkt_empty_sync(1 to C_SYNCHRONIZER_STAGE-1) & empty_p0_out AFTER C_TCQ;
END IF;
END PROCESS proc_empty_sync;
packet_empty_wr <= pkt_empty_sync(0);
END GENERATE gpkt_empty_sync;
gnpkt_empty_sync: IF (C_COMMON_CLOCK = 1) GENERATE
packet_empty_wr <= empty_p0_out;
END GENERATE gnpkt_empty_sync;
END GENERATE gdummy_wr_eop;
proc_stage1_eop: PROCESS (rst_fwft, CLK_INT)
BEGIN
IF (rst_fwft = '1') THEN
stage1_eop_d1 <= '0';
rd_en_fifo_in_d1 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed = '1') THEN
stage1_eop_d1 <= '0' AFTER C_TCQ;
rd_en_fifo_in_d1 <= '0' AFTER C_TCQ;
ELSE
stage1_eop_d1 <= stage1_eop AFTER C_TCQ;
rd_en_fifo_in_d1 <= rd_en_fifo_in AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_stage1_eop;
stage1_eop <= dout_fifo_out(0) WHEN (rd_en_fifo_in_d1 = '1') ELSE stage1_eop_d1;
ram_wr_en_pkt_fifo <= wr_en_delayed AND (NOT FULL_int);
wr_eop <= ram_wr_en_pkt_fifo AND ((din_delayed(0) AND (NOT partial_packet)) OR dummy_wr_eop);
ram_rd_en_compare <= stage2_reg_en_i AND stage1_eop;
pkt_fifo_fwft : fifo_generator_v11_0_bhv_preload0
GENERIC MAP (
C_DOUT_RST_VAL => C_DOUT_RST_VAL,
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USERVALID_LOW => C_VALID_LOW,
C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_FIFO_TYPE => 2 -- Enable low latency fwft logic
)
PORT MAP (
RD_CLK => CLK_INT,
RD_RST => rst_fwft,
SRST => srst_delayed,
RD_EN => rd_en_delayed,
FIFOEMPTY => pkt_ready_to_read,
FIFODATA => dout_fwft,
FIFOSBITERR => sbiterr_fwft,
FIFODBITERR => dbiterr_fwft,
USERDATA => dout_p0_out,
USERVALID => OPEN,
USEREMPTY => empty_p0_out,
USERALMOSTEMPTY => OPEN,
USERUNDERFLOW => OPEN,
RAMVALID => OPEN, --Used for observing the state of the ram_valid
FIFORDEN => rd_en_2_stage2,
USERSBITERR => SBITERR,
USERDBITERR => DBITERR,
STAGE2_REG_EN => OPEN,
VALID_STAGES => OPEN
);
pkt_ready_to_read <= NOT ((ram_pkt_empty NOR empty_fwft) AND ((valid_stages_i(0) AND valid_stages_i(1)) OR eop_at_stage2));
rd_en_to_fwft_fifo <= NOT empty_fwft AND rd_en_2_stage2;
pregsm : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
eop_at_stage2 <= '0';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (stage2_reg_en_i = '1') THEN
eop_at_stage2 <= stage1_eop AFTER C_TCQ;
END IF;
END IF;
END PROCESS pregsm;
-----------------------------------------------------------------------------
-- Write and Read Packet Count
-----------------------------------------------------------------------------
proc_wr_pkt_cnt: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
IF (srst_delayed='1') THEN
wr_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
ELSIF (wr_eop = '1') THEN
wr_pkt_count <= wr_pkt_count + int_2_std_logic_vector(1,C_WR_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_wr_pkt_cnt;
grss_pkt_cnt : IF C_COMMON_CLOCK = 1 GENERATE
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count <= (OTHERS => '0');
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH);
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (srst_delayed='1') THEN
rd_pkt_count <= (OTHERS => '0') AFTER C_TCQ;
rd_pkt_count_plus1 <= int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
ELSIF (stage2_reg_en_i = '1' AND stage1_eop = '1') THEN
rd_pkt_count <= rd_pkt_count + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
rd_pkt_count_plus1 <= rd_pkt_count_plus1 + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH) AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (SRST='1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
ELSE
IF ((rd_pkt_count = wr_pkt_count) AND wr_eop = '1') THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count_plus1 = wr_pkt_count) AND wr_eop = '0' AND almost_full_i = '0' AND ram_rd_en_compare = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END IF;
END PROCESS proc_pkt_empty;
END GENERATE grss_pkt_cnt;
gras_pkt_cnt : IF C_COMMON_CLOCK = 0 GENERATE
TYPE wr_pkt_cnt_sync_array IS ARRAY (C_SYNCHRONIZER_STAGE-1 DOWNTO 0) OF std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0);
SIGNAL wr_pkt_count_q : wr_pkt_cnt_sync_array := (OTHERS => (OTHERS => '0'));
SIGNAL wr_pkt_count_b2g : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wr_pkt_count_rd : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
proc_wr_pkt_cnt_b2g: PROCESS (WR_CLK, wr_rst_fwft_pkt_fifo)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_b2g <= (OTHERS => '0');
ELSIF (WR_CLK'event AND WR_CLK = '1') THEN
wr_pkt_count_b2g <= wr_pkt_count AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_b2g;
-- Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
proc_wr_pkt_cnt_rd: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (wr_rst_fwft_pkt_fifo = '1') THEN
wr_pkt_count_q <= (OTHERS => (OTHERS => '0'));
wr_pkt_count_rd <= (OTHERS => '0');
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
wr_pkt_count_q <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-2 DOWNTO 0) & wr_pkt_count_b2g AFTER C_TCQ;
wr_pkt_count_rd <= wr_pkt_count_q(C_SYNCHRONIZER_STAGE-1) AFTER C_TCQ;
END IF;
END PROCESS proc_wr_pkt_cnt_rd;
rd_pkt_count <= rd_pkt_count_reg + int_2_std_logic_vector(1,C_RD_PNTR_WIDTH)
WHEN (stage1_eop = '1') ELSE rd_pkt_count_reg;
proc_rd_pkt_cnt: PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
rd_pkt_count_reg <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK = '1') THEN
IF (rd_en_fifo_in = '1') THEN
rd_pkt_count_reg <= rd_pkt_count AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_rd_pkt_cnt;
proc_pkt_empty_as : PROCESS (CLK_INT, rst_fwft)
BEGIN
IF (rst_fwft = '1') THEN
ram_pkt_empty <= '1';
ram_pkt_empty_d1 <= '1';
ELSIF (CLK_INT'event AND CLK_INT = '1') THEN
IF (rd_pkt_count /= wr_pkt_count_rd) THEN
ram_pkt_empty <= '0' AFTER C_TCQ;
ram_pkt_empty_d1 <= '0' AFTER C_TCQ;
ELSIF (ram_pkt_empty_d1 = '1' AND rd_en_to_fwft_fifo = '1') THEN
ram_pkt_empty <= '1' AFTER C_TCQ;
ELSIF ((rd_pkt_count = wr_pkt_count_rd) AND stage2_reg_en_i = '1') THEN
ram_pkt_empty_d1 <= '1' AFTER C_TCQ;
END IF;
END IF;
END PROCESS proc_pkt_empty_as;
END GENERATE gras_pkt_cnt;
END GENERATE gpkt_fifo_fwft;
END GENERATE lat0;
gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE
begin
ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR
(C_USE_FWFT_DATA_COUNT = 0) )GENERATE
begin
DATA_COUNT <= data_count_fifo_out ;
end generate ss_count ;
ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1) ) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ;
end generate ss_count_fwft1 ;
ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND
(C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND
(C_USE_FWFT_DATA_COUNT = 1)) GENERATE
begin
DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ;
end generate ss_count_fwft2 ;
end generate gdc_fwft;
FULL <= FULL_int;
-------------------------------------------------------------------------------
-- If there is a reset input, generate internal reset signals
-- The latency of reset will match the core behavior
-------------------------------------------------------------------------------
--Single RST
grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE
grst : IF (C_HAS_RST = 1) GENERATE
gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE
SIGNAL rd_rst_asreg : std_logic:= '0';
SIGNAL rd_rst_asreg_d1 : std_logic:= '0';
SIGNAL rd_rst_asreg_d2 : std_logic:= '0';
SIGNAL rd_rst_comb : std_logic:= '0';
SIGNAL rd_rst_reg : std_logic:= '0';
SIGNAL wr_rst_asreg : std_logic:= '0';
SIGNAL wr_rst_asreg_d1 : std_logic:= '0';
SIGNAL wr_rst_asreg_d2 : std_logic:= '0';
SIGNAL wr_rst_comb : std_logic:= '0';
SIGNAL wr_rst_reg : std_logic:= '0';
BEGIN
PROCESS (WR_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
wr_rst_asreg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
IF (wr_rst_asreg_d1 = '1') THEN
wr_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ;
wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (wr_rst_asreg, wr_rst_asreg_d2)
BEGIN
wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg;
END PROCESS;
PROCESS (WR_CLK, wr_rst_comb)
BEGIN
IF (wr_rst_comb = '1') THEN
wr_rst_reg <= '1' after C_TCQ;
ELSIF (WR_CLK'event and WR_CLK = '1') THEN
wr_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
PROCESS (RD_CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rd_rst_asreg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
IF (rd_rst_asreg_d1 = '1') THEN
rd_rst_asreg <= '0' after C_TCQ;
END IF;
END IF;
IF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ;
rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rd_rst_asreg, rd_rst_asreg_d2)
BEGIN
rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg;
END PROCESS;
PROCESS (RD_CLK, rd_rst_comb)
BEGIN
IF (rd_rst_comb = '1') THEN
rd_rst_reg <= '1' after C_TCQ;
ELSIF (RD_CLK'event and RD_CLK = '1') THEN
rd_rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
wr_rst_i <= wr_rst_reg;
rd_rst_i <= rd_rst_reg;
END GENERATE gic_rst;
gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
SIGNAL rst_reg : std_logic := '0';
BEGIN
PROCESS (CLK, rst_delayed)
BEGIN
IF (rst_delayed = '1') THEN
rst_asreg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
IF (rst_asreg_d1 = '1') THEN
rst_asreg <= '0' after C_TCQ;
ELSE
rst_asreg <= rst_asreg after C_TCQ;
END IF;
END IF;
IF (CLK'event and CLK = '1') THEN
rst_asreg_d1 <= rst_asreg after C_TCQ;
rst_asreg_d2 <= rst_asreg_d1 after C_TCQ;
END IF;
END PROCESS;
PROCESS (rst_asreg, rst_asreg_d2)
BEGIN
rst_comb <= NOT rst_asreg_d2 AND rst_asreg;
END PROCESS;
PROCESS (CLK, rst_comb)
BEGIN
IF (rst_comb = '1') THEN
rst_reg <= '1' after C_TCQ;
ELSIF (CLK'event and CLK = '1') THEN
rst_reg <= '0' after C_TCQ;
END IF;
END PROCESS;
rst_i <= rst_reg;
END GENERATE gcc_rst;
END GENERATE grst;
gnrst : IF (C_HAS_RST = 0) GENERATE
wr_rst_i <= '0';
rd_rst_i <= '0';
rst_i <= '0';
END GENERATE gnrst;
END GENERATE grst_sync;
gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE
wr_rst_i <= wr_rst_delayed;
rd_rst_i <= rd_rst_delayed;
rst_i <= '0';
END GENERATE gnrst_sync;
rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed;
clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK;
grstd1 : IF (C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE
-- RST_FULL_GEN replaces the reset falling edge detection used to de-assert
-- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
-- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
-- PROG_FULL
grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
SIGNAL rst_d3 : STD_LOGIC := '1';
BEGIN
grst_f: IF (C_HAS_SRST = 0) GENERATE
prst: PROCESS (rst_2_sync, clk_2_sync)
BEGIN
IF (rst_2_sync = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
rst_d3 <= '1';
rst_full_gen_i <= '0';
ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END PROCESS prst;
rst_full_ff_i <= rst_d2;
END GENERATE grst_f;
ngrst_f: IF (C_HAS_SRST = 1) GENERATE
prst: PROCESS (clk_2_sync)
BEGIN
IF (clk_2_sync'event AND clk_2_sync = '1') THEN
IF (srst_delayed = '1') THEN
rst_d1 <= '1' AFTER C_TCQ;
rst_d2 <= '1' AFTER C_TCQ;
rst_d3 <= '1' AFTER C_TCQ;
rst_full_gen_i <= '0' AFTER C_TCQ;
ELSE
rst_d1 <= '0' AFTER C_TCQ;
rst_d2 <= rst_d1 AFTER C_TCQ;
rst_d3 <= rst_d2 AFTER C_TCQ;
rst_full_gen_i <= rst_d3 AFTER C_TCQ;
END IF;
END IF;
END PROCESS prst;
rst_full_ff_i <= '0';
END GENERATE ngrst_f;
END GENERATE grst_full;
gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE
rst_full_gen_i <= '0';
rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i;
END GENERATE gnrst_full;
END GENERATE grstd1;
END behavioral;
-------------------------------------------------------------------------------
--
-- Register Slice
-- Register one AXI channel on forward and/or reverse signal path
--
----------------------------------------------------------------------------
--
-- Structure:
-- reg_slice
--
----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fifo_generator_v11_0_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END fifo_generator_v11_0_axic_reg_slice;
ARCHITECTURE xilinx OF fifo_generator_v11_0_axic_reg_slice IS
SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output
SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register
SIGNAL rst_asreg : std_logic := '0';
SIGNAL rst_asreg_d1 : std_logic := '0';
SIGNAL rst_asreg_d2 : std_logic := '0';
SIGNAL rst_comb : std_logic := '0';
-- Constant to have clock to register delay
CONSTANT TFF : time := 100 ps;
BEGIN
--------------------------------------------------------------------
--
-- Both FWD and REV mode
--
--------------------------------------------------------------------
gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE
CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL load_s1 : STD_LOGIC;
SIGNAL load_s2 : STD_LOGIC;
SIGNAL load_s1_from_s2 : BOOLEAN;
BEGIN
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with either slave side data or from storage2
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s1 = '1') THEN
IF (load_s1_from_s2) THEN
storage_data1 <= storage_data2 AFTER TFF;
ELSE
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END IF;
END PROCESS;
-- Load storage2 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (load_s2 = '1') THEN
storage_data2 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
-- Always load s2 on a valid transaction even if it's unnecessary
load_s2 <= S_VALID AND s_ready_i;
-- Loading s1
PROCESS(state,S_VALID,M_READY)
BEGIN
IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction
-- Load when ONE if we both have read and write at the same time
(state = ONE AND S_VALID = '1' AND M_READY = '1') OR
-- Load when TWO and we have a transaction on Master side
(state = TWO AND M_READY = '1')) THEN
load_s1 <= '1';
ELSE
load_s1 <= '0';
END IF;
END PROCESS;
load_s1_from_s2 <= (state = TWO);
-- State Machine for handling output signals
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
state <= ZERO AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSE
CASE state IS
WHEN ZERO => -- No transaction stored locally
IF (S_VALID = '1') THEN -- Got one so move to ONE
state <= ONE AFTER TFF;
END IF;
WHEN ONE => -- One transaction stored locally
IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO
state <= ZERO AFTER TFF;
END IF;
IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO
state <= TWO AFTER TFF;
s_ready_i <= '0' AFTER TFF;
END IF;
WHEN TWO => -- TWO transaction stored locally
IF (M_READY = '1') THEN -- Read out one so move to ONE
state <= ONE AFTER TFF;
s_ready_i <= '1' AFTER TFF;
END IF;
WHEN OTHERS =>
state <= state AFTER TFF;
END CASE;
END IF;
END IF;
END PROCESS;
m_valid_i <= state(0);
END GENERATE gfwd_rev;
--------------------------------------------------------------------
--
-- C_REG_CONFIG = 1
-- Light-weight mode.
-- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
-- Operates same as 1-deep FIFO
--
--------------------------------------------------------------------
gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE
-- assign local signal to its output signal
S_READY <= s_ready_i;
M_VALID <= m_valid_i;
-- Reset delay register
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
areset_d1 <= ARESET AFTER TFF;
END IF;
END PROCESS;
-- Load storage1 with slave side data
PROCESS(ACLK)
BEGIN
IF (ACLK'event AND ACLK = '1') THEN
IF (ARESET = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (areset_d1 = '1') THEN
s_ready_i <= '1' AFTER TFF;
ELSIF (m_valid_i = '1' AND M_READY = '1') THEN
s_ready_i <= '1' AFTER TFF;
m_valid_i <= '0' AFTER TFF;
ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN
s_ready_i <= '0' AFTER TFF;
m_valid_i <= '1' AFTER TFF;
END IF;
IF (m_valid_i = '0') THEN
storage_data1 <= S_PAYLOAD_DATA AFTER TFF;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= storage_data1;
END GENERATE gfwd_rev_pipeline1;
end xilinx;-- reg_slice
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Top-level Behavioral Model for AXI
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY fifo_generator_v11_0;
USE fifo_generator_v11_0.fifo_generator_v11_0_conv;
-------------------------------------------------------------------------------
-- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model
-------------------------------------------------------------------------------
ENTITY fifo_generator_v11_0 IS
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex6";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN : IN std_logic := '0';
RD_EN : IN std_logic := '0';
-- Optional inputs
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
FULL : OUT std_logic := '0';
ALMOST_FULL : OUT std_logic := '0';
WR_ACK : OUT std_logic := '0';
OVERFLOW : OUT std_logic := '0';
EMPTY : OUT std_logic := '1';
ALMOST_EMPTY : OUT std_logic := '1';
VALID : OUT std_logic := '0';
UNDERFLOW : OUT std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL : OUT std_logic := '0';
PROG_EMPTY : OUT std_logic := '1';
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0';
-- AXI Global Signal
M_ACLK : IN std_logic := '0';
S_ACLK : IN std_logic := '0';
S_ARESETN : IN std_logic := '1'; -- Active low reset, default value set to 1
M_ACLK_EN : IN std_logic := '0';
S_ACLK_EN : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN std_logic := '0';
S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_AWVALID : OUT std_logic := '0';
M_AXI_AWREADY : IN std_logic := '0';
M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WLAST : OUT std_logic := '0';
M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_WVALID : OUT std_logic := '0';
M_AXI_WREADY : IN std_logic := '0';
M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID : IN std_logic := '0';
M_AXI_BREADY : OUT std_logic := '0';
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK : IN std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic := '0';
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RLAST : OUT std_logic := '0';
S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RVALID : OUT std_logic := '0';
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLEN : OUT std_logic_vector(C_AXI_LEN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARLOCK : OUT std_logic_vector(C_AXI_LOCK_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_ARVALID : OUT std_logic := '0';
M_AXI_ARREADY : IN std_logic := '0';
M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST : IN std_logic := '0';
M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID : IN std_logic := '0';
M_AXI_RREADY : OUT std_logic := '0';
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic := '0';
S_AXIS_TREADY : OUT std_logic := '0';
S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST : IN std_logic := '0';
S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic := '0';
M_AXIS_TREADY : IN std_logic := '0';
M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TLAST : OUT std_logic := '0';
M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic := '0';
AXI_AW_INJECTDBITERR : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0) := (OTHERS => '0');
AXI_AW_SBITERR : OUT std_logic := '0';
AXI_AW_DBITERR : OUT std_logic := '0';
AXI_AW_OVERFLOW : OUT std_logic := '0';
AXI_AW_UNDERFLOW : OUT std_logic := '0';
AXI_AW_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic := '0';
AXI_W_INJECTDBITERR : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
AXI_W_SBITERR : OUT std_logic := '0';
AXI_W_DBITERR : OUT std_logic := '0';
AXI_W_OVERFLOW : OUT std_logic := '0';
AXI_W_UNDERFLOW : OUT std_logic := '0';
AXI_W_PROG_FULL : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic := '0';
AXI_B_INJECTDBITERR : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0) := (OTHERS => '0');
AXI_B_SBITERR : OUT std_logic := '0';
AXI_B_DBITERR : OUT std_logic := '0';
AXI_B_OVERFLOW : OUT std_logic := '0';
AXI_B_UNDERFLOW : OUT std_logic := '0';
AXI_B_PROG_FULL : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic := '0';
AXI_AR_INJECTDBITERR : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0) := (OTHERS => '0');
AXI_AR_SBITERR : OUT std_logic := '0';
AXI_AR_DBITERR : OUT std_logic := '0';
AXI_AR_OVERFLOW : OUT std_logic := '0';
AXI_AR_UNDERFLOW : OUT std_logic := '0';
AXI_AR_PROG_FULL : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic := '0';
AXI_R_INJECTDBITERR : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
AXI_R_SBITERR : OUT std_logic := '0';
AXI_R_DBITERR : OUT std_logic := '0';
AXI_R_OVERFLOW : OUT std_logic := '0';
AXI_R_UNDERFLOW : OUT std_logic := '0';
AXI_R_PROG_FULL : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic := '0';
AXIS_INJECTDBITERR : IN std_logic := '0';
AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
AXIS_SBITERR : OUT std_logic := '0';
AXIS_DBITERR : OUT std_logic := '0';
AXIS_OVERFLOW : OUT std_logic := '0';
AXIS_UNDERFLOW : OUT std_logic := '0';
AXIS_PROG_FULL : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY : OUT STD_LOGIC := '1'
);
END fifo_generator_v11_0;
ARCHITECTURE behavioral OF fifo_generator_v11_0 IS
COMPONENT fifo_generator_v11_0_conv IS
GENERIC (
---------------------------------------------------------------------------
-- Generic Declarations
---------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0; --not used
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := ""; --not used
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0; --not used
C_FAMILY : string := ""; --not used in bhv model
C_FULL_FLAGS_RST_VAL : integer := 0;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0; --not used
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0; --not used in bhv model
C_HAS_MEMINIT_FILE : integer := 0; --not used
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0; --not used
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0; --not used
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0; --not used
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := ""; --not used
C_OPTIMIZATION_MODE : integer := 0; --not used
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model
C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1; --not used in bhv model
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1; --not used in bhv model
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1; --not used
C_MSGON_VAL : integer := 1; --not used in bhv model
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_FIFO_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
C_AXI_TYPE : integer := 0
);
PORT(
--------------------------------------------------------------------------------
-- Input and Output Declarations
--------------------------------------------------------------------------------
BACKUP : IN std_logic := '0';
BACKUP_MARKER : IN std_logic := '0';
CLK : IN std_logic := '0';
RST : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_CLK : IN std_logic := '0';
WR_RST : IN std_logic := '0';
RD_CLK : IN std_logic := '0';
RD_RST : IN std_logic := '0';
DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); --
WR_EN : IN std_logic; --Mandatory input
RD_EN : IN std_logic; --Mandatory input
--Mandatory input
PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK : IN std_logic := '0';
INJECTDBITERR : IN std_logic := '0';
INJECTSBITERR : IN std_logic := '0';
DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL : OUT std_logic;
ALMOST_FULL : OUT std_logic;
WR_ACK : OUT std_logic;
OVERFLOW : OUT std_logic;
EMPTY : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
VALID : OUT std_logic;
UNDERFLOW : OUT std_logic;
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
SBITERR : OUT std_logic := '0';
DBITERR : OUT std_logic := '0'
);
END COMPONENT;
COMPONENT fifo_generator_v11_0_axic_reg_slice IS
GENERIC (
C_FAMILY : string := "";
C_DATA_WIDTH : integer := 32;
C_REG_CONFIG : integer := 0
);
PORT (
-- System Signals
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
-- Slave side
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC := '0';
-- Master side
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_VALID : OUT STD_LOGIC := '0';
M_READY : IN STD_LOGIC
);
END COMPONENT;
-- CONSTANT C_AXI_LEN_WIDTH : integer := 8;
CONSTANT C_AXI_SIZE_WIDTH : integer := 3;
CONSTANT C_AXI_BURST_WIDTH : integer := 2;
-- CONSTANT C_AXI_LOCK_WIDTH : integer := 2;
CONSTANT C_AXI_CACHE_WIDTH : integer := 4;
CONSTANT C_AXI_PROT_WIDTH : integer := 3;
CONSTANT C_AXI_QOS_WIDTH : integer := 4;
CONSTANT C_AXI_REGION_WIDTH : integer := 4;
CONSTANT C_AXI_BRESP_WIDTH : integer := 2;
CONSTANT C_AXI_RRESP_WIDTH : integer := 2;
CONSTANT TFF : time := 100 ps;
-----------------------------------------------------------------------------
-- FUNCTION if_then_else
-- Returns a true case or flase case based on the condition
-------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : integer;
false_case : integer)
RETURN integer IS
VARIABLE retval : integer := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
------------------------------------------------------------------------------
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed and returns string.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : boolean;
true_case : string;
false_case : string)
RETURN string IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
--------------------------------------------------------
-- FUNCION : map_ready_valid
-- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL
-- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY
--------------------------------------------------------
FUNCTION map_ready_valid(
pf_pe_type : integer;
full_empty : std_logic;
af_ae : std_logic;
pf_pe : std_logic)
RETURN std_logic IS
BEGIN
IF (pf_pe_type = 5) THEN
RETURN NOT full_empty;
ELSIF (pf_pe_type = 6) THEN
RETURN NOT af_ae;
ELSE
RETURN NOT pf_pe;
END IF;
END map_ready_valid;
SIGNAL inverted_reset : std_logic := '0';
SIGNAL axi_rs_rst : std_logic := '0';
BEGIN
inverted_reset <= NOT S_ARESETN;
gaxi_rs_rst: IF (C_INTERFACE_TYPE > 0 AND (C_AXIS_TYPE = 1 OR C_WACH_TYPE = 1 OR
C_WDCH_TYPE = 1 OR C_WRCH_TYPE = 1 OR C_RACH_TYPE = 1 OR C_RDCH_TYPE = 1)) GENERATE
SIGNAL rst_d1 : STD_LOGIC := '1';
SIGNAL rst_d2 : STD_LOGIC := '1';
BEGIN
prst: PROCESS (inverted_reset, S_ACLK)
BEGIN
IF (inverted_reset = '1') THEN
rst_d1 <= '1';
rst_d2 <= '1';
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
rst_d1 <= '0' AFTER TFF;
rst_d2 <= rst_d1 AFTER TFF;
END IF;
END PROCESS prst;
axi_rs_rst <= rst_d2;
END GENERATE gaxi_rs_rst;
---------------------------------------------------------------------------
-- Top level instance for Conventional FIFO.
---------------------------------------------------------------------------
gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE
inst_conv_fifo: fifo_generator_v11_0_conv
GENERIC map(
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_DIN_WIDTH => C_DIN_WIDTH,
C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"),
C_DOUT_WIDTH => C_DOUT_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT,
C_HAS_RD_RST => C_HAS_RD_RST,
C_HAS_RST => C_HAS_RST,
C_HAS_SRST => C_HAS_SRST,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_HAS_VALID => C_HAS_VALID,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT,
C_HAS_WR_RST => C_HAS_WR_RST,
C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL,
C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE,
C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_RD_DEPTH,
C_RD_FREQ => C_RD_FREQ,
C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_USE_DOUT_RST => C_USE_DOUT_RST,
C_USE_ECC => C_USE_ECC,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => C_VALID_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_WR_DEPTH,
C_WR_FREQ => C_WR_FREQ,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
CLK => CLK,
RST => RST,
SRST => SRST,
WR_CLK => WR_CLK,
WR_RST => WR_RST,
RD_CLK => RD_CLK,
RD_RST => RD_RST,
DIN => DIN,
WR_EN => WR_EN,
RD_EN => RD_EN,
PROG_EMPTY_THRESH => PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT,
PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE,
PROG_FULL_THRESH => PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT,
PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE,
INT_CLK => INT_CLK,
INJECTDBITERR => INJECTDBITERR,
INJECTSBITERR => INJECTSBITERR,
--Outputs
DOUT => DOUT,
FULL => FULL,
ALMOST_FULL => ALMOST_FULL,
WR_ACK => WR_ACK,
OVERFLOW => OVERFLOW,
EMPTY => EMPTY,
ALMOST_EMPTY => ALMOST_EMPTY,
VALID => VALID,
UNDERFLOW => UNDERFLOW,
DATA_COUNT => DATA_COUNT,
RD_DATA_COUNT => RD_DATA_COUNT,
WR_DATA_COUNT => WR_DATA_COUNT,
PROG_FULL => PROG_FULL,
PROG_EMPTY => PROG_EMPTY,
SBITERR => SBITERR,
DBITERR => DBITERR
);
END GENERATE gconvfifo; -- End of conventional FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Top level instance for ramfifo in AXI Streaming FIFO core. It implements:
-- * BRAM based FIFO
-- * Dist RAM based FIFO
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXIS_TYPE < 2)) GENERATE
SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_full : std_logic := '0';
SIGNAL axis_almost_full : std_logic := '0';
SIGNAL axis_empty : std_logic := '0';
SIGNAL axis_s_axis_tready : std_logic := '0';
SIGNAL axis_m_axis_tvalid : std_logic := '0';
SIGNAL axis_wr_en : std_logic := '0';
SIGNAL axis_rd_en : std_logic := '0';
SIGNAL axis_dc : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
SIGNAL axis_pkt_read : STD_LOGIC := '0';
CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS);
CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET);
CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET);
CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET);
CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET);
CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET);
BEGIN
-- Generate the DIN to FIFO by concatinating the AXIS optional ports
gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE
axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA;
M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET);
END GENERATE gdin1;
gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE
axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB;
M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET);
END GENERATE gdin2;
gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE
axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP;
M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET);
END GENERATE gdin3;
gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE
axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID;
M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET);
END GENERATE gdin4;
gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE
axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST;
M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET);
END GENERATE gdin5;
gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE
axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER;
M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET);
END GENERATE gdin6;
gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE
axis_din(0) <= S_AXIS_TLAST;
M_AXIS_TLAST <= axis_dout(0);
END GENERATE gdin7;
-- Write protection
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 0) GENERATE
gwe_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_wr_en <= S_AXIS_TVALID AND axis_s_axis_tready;
END GENERATE gwe_pkt;
gwe: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_wr_en <= S_AXIS_TVALID;
END GENERATE gwe;
END GENERATE gaxis_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 0) GENERATE
axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID;
END GENERATE gaxis_wr_en2;
-- Read protection
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 0) GENERATE
gre_pkt: IF (C_APPLICATION_TYPE_AXIS = 1) GENERATE
axis_rd_en <= M_AXIS_TREADY AND axis_m_axis_tvalid;
END GENERATE gre_pkt;
gre_npkt: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
axis_rd_en <= M_AXIS_TREADY;
END GENERATE gre_npkt;
END GENERATE gaxis_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 0) GENERATE
axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY;
END GENERATE gaxis_rd_en2;
gaxisf: IF (C_AXIS_TYPE = 0) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
BEGIN
axis_we <= axis_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE axis_wr_en AND S_ACLK_EN;
axis_re <= axis_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE axis_rd_en AND M_ACLK_EN;
axisf : fifo_generator_v11_0_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 2 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,4)),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 2),0,
if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 11 OR C_IMPLEMENTATION_TYPE_AXIS = 12),2,5)),
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_AXIS,
C_WR_DEPTH => C_WR_DEPTH_AXIS,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_DOUT_WIDTH => C_DIN_WIDTH_AXIS,
C_RD_DEPTH => C_WR_DEPTH_AXIS,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS,
C_USE_ECC => C_USE_ECC_AXIS,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => if_then_else(C_APPLICATION_TYPE_AXIS = 1,1,0),
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else(C_APPLICATION_TYPE_AXIS = 1,0,C_APPLICATION_TYPE_AXIS),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => 0,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => axis_we,
RD_EN => axis_re,
PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXIS_INJECTDBITERR,
INJECTSBITERR => AXIS_INJECTSBITERR,
DIN => axis_din,
DOUT => axis_dout,
FULL => axis_full,
EMPTY => axis_empty,
ALMOST_FULL => axis_almost_full,
PROG_FULL => AXIS_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXIS_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => AXIS_OVERFLOW,
VALID => OPEN,
UNDERFLOW => AXIS_UNDERFLOW,
DATA_COUNT => axis_dc,
RD_DATA_COUNT => AXIS_RD_DATA_COUNT,
WR_DATA_COUNT => AXIS_WR_DATA_COUNT,
SBITERR => AXIS_SBITERR,
DBITERR => AXIS_DBITERR
);
axis_s_axis_tready <= NOT axis_full;
axis_m_axis_tvalid <= NOT axis_empty WHEN (C_APPLICATION_TYPE_AXIS /= 1) ELSE NOT axis_empty AND axis_pkt_read;
S_AXIS_TREADY <= axis_s_axis_tready;
M_AXIS_TVALID <= axis_m_axis_tvalid;
gaxis_pkt_fifo: IF (C_APPLICATION_TYPE_AXIS = 1 AND C_COMMON_CLOCK = 1) GENERATE
SIGNAL axis_wr_eop : STD_LOGIC := '0';
SIGNAL axis_wr_eop_d1 : STD_LOGIC := '0';
SIGNAL axis_rd_eop : STD_LOGIC := '0';
SIGNAL axis_pkt_cnt : INTEGER := 0;
BEGIN
axis_wr_eop <= axis_we AND S_AXIS_TLAST;
axis_rd_eop <= axis_re AND axis_dout(0);
-- Packet Read Generation logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_read <= '0';
axis_wr_eop_d1 <= '0';
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
axis_wr_eop_d1 <= axis_wr_eop;
IF (axis_rd_eop = '1' AND (axis_pkt_cnt = 1) AND axis_wr_eop_d1 = '0') THEN
axis_pkt_read <= '0' AFTER TFF;
ELSIF ((axis_pkt_cnt > 0) OR (axis_almost_full = '1' AND axis_empty = '0')) THEN
axis_pkt_read <= '1' AFTER TFF;
END IF;
END IF;
END PROCESS;
-- Packet count logic
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_pkt_cnt <= 0;
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_wr_eop_d1 = '1' AND axis_rd_eop = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt + 1 AFTER TFF;
ELSIF (axis_rd_eop = '1' AND axis_wr_eop_d1 = '0') THEN
axis_pkt_cnt <= axis_pkt_cnt - 1 AFTER TFF;
END IF;
END IF;
END PROCESS;
END GENERATE gaxis_pkt_fifo;
gdc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 1 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
SIGNAL axis_dc_pkt_fifo : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_AXIS DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
axis_dc_pkt_fifo <= (OTHERS => '0');
ELSIF (S_ACLK = '1' AND S_ACLK'EVENT) THEN
IF (axis_we = '1' AND axis_re = '0') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo + "1" AFTER TFF;
ELSIF (axis_we = '0' AND axis_re = '1') THEN
axis_dc_pkt_fifo <= axis_dc_pkt_fifo - "1" AFTER TFF;
END IF;
END IF;
END PROCESS;
AXIS_DATA_COUNT <= axis_dc_pkt_fifo;
END GENERATE gdc_pkt;
gndc_pkt: IF (C_HAS_DATA_COUNTS_AXIS = 0 AND C_APPLICATION_TYPE_AXIS = 1) GENERATE
AXIS_DATA_COUNT <= (OTHERS => '0');
END GENERATE gndc_pkt;
gdc: IF (C_APPLICATION_TYPE_AXIS /= 1) GENERATE
AXIS_DATA_COUNT <= axis_dc;
END GENERATE gdc;
END GENERATE gaxisf;
-- Register Slice for AXI Streaming
gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE
SIGNAL axis_we : STD_LOGIC := '0';
SIGNAL axis_re : STD_LOGIC := '0';
BEGIN
axis_we <= S_AXIS_TVALID WHEN (C_HAS_SLAVE_CE = 0) ELSE S_AXIS_TVALID AND S_ACLK_EN;
axis_re <= M_AXIS_TREADY WHEN (C_HAS_MASTER_CE = 0) ELSE M_AXIS_TREADY AND M_ACLK_EN;
axis_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_AXIS,
C_REG_CONFIG => C_REG_SLICE_MODE_AXIS
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => axis_din,
S_VALID => axis_we,
S_READY => S_AXIS_TREADY,
-- Master side
M_PAYLOAD_DATA => axis_dout,
M_VALID => M_AXIS_TVALID,
M_READY => axis_re
);
END GENERATE gaxis_reg_slice;
END GENERATE gaxis_fifo;
gaxifull: IF (C_INTERFACE_TYPE = 2) GENERATE
SIGNAL axi_rd_underflow_i : std_logic := '0';
SIGNAL axi_rd_overflow_i : std_logic := '0';
SIGNAL axi_wr_underflow_i : std_logic := '0';
SIGNAL axi_wr_overflow_i : std_logic := '0';
BEGIN
gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE
SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_dout_pkt : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wach_full : std_logic := '0';
SIGNAL wach_almost_full : std_logic := '0';
SIGNAL wach_prog_full : std_logic := '0';
SIGNAL wach_empty : std_logic := '0';
SIGNAL wach_almost_empty : std_logic := '0';
SIGNAL wach_prog_empty : std_logic := '0';
SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wdch_full : std_logic := '0';
SIGNAL wdch_almost_full : std_logic := '0';
SIGNAL wdch_prog_full : std_logic := '0';
SIGNAL wdch_empty : std_logic := '0';
SIGNAL wdch_almost_empty : std_logic := '0';
SIGNAL wdch_prog_empty : std_logic := '0';
SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL wrch_full : std_logic := '0';
SIGNAL wrch_almost_full : std_logic := '0';
SIGNAL wrch_prog_full : std_logic := '0';
SIGNAL wrch_empty : std_logic := '0';
SIGNAL wrch_almost_empty : std_logic := '0';
SIGNAL wrch_prog_empty : std_logic := '0';
SIGNAL axi_aw_underflow_i : std_logic := '0';
SIGNAL axi_w_underflow_i : std_logic := '0';
SIGNAL axi_b_underflow_i : std_logic := '0';
SIGNAL axi_aw_overflow_i : std_logic := '0';
SIGNAL axi_w_overflow_i : std_logic := '0';
SIGNAL axi_b_overflow_i : std_logic := '0';
SIGNAL wach_s_axi_awready : std_logic := '0';
SIGNAL wach_m_axi_awvalid : std_logic := '0';
SIGNAL wach_wr_en : std_logic := '0';
SIGNAL wach_rd_en : std_logic := '0';
SIGNAL wdch_s_axi_wready : std_logic := '0';
SIGNAL wdch_m_axi_wvalid : std_logic := '0';
SIGNAL wdch_wr_en : std_logic := '0';
SIGNAL wdch_rd_en : std_logic := '0';
SIGNAL wrch_s_axi_bvalid : std_logic := '0';
SIGNAL wrch_m_axi_bready : std_logic := '0';
SIGNAL wrch_wr_en : std_logic := '0';
SIGNAL wrch_rd_en : std_logic := '0';
SIGNAL awvalid_en : std_logic := '0';
SIGNAL awready_pkt : std_logic := '0';
SIGNAL wdch_we : STD_LOGIC := '0';
CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH);
CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET);
CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET);
CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET);
CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET);
CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET);
CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT AWREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWQOS_OFFSET - C_AXI_REGION_WIDTH, AWQOS_OFFSET);
CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET);
CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 3 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH);
CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET);
CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH);
CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH;
CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_wr_ch: IF (C_AXI_TYPE /= 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE
wach_din(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET) <= S_AXI_AWUSER;
M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET);
END GENERATE gwach_din1;
gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE
M_AXI_AWUSER <= (OTHERS => '0');
END GENERATE gwach_din2;
gwach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wach_din(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET) <= S_AXI_AWID;
M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET);
END GENERATE gwach_din3;
gwach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_AWID <= (OTHERS => '0');
END GENERATE gwach_din4;
gwach_din5: IF (C_AXI_TYPE = 1) GENERATE
wach_din(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET) <= S_AXI_AWREGION;
M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET);
END GENERATE gwach_din5;
gwach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_AWREGION <= (OTHERS => '0');
END GENERATE gwach_din6;
wach_din(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET) <= S_AXI_AWADDR;
wach_din(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET) <= S_AXI_AWLEN;
wach_din(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET) <= S_AXI_AWSIZE;
wach_din(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET) <= S_AXI_AWBURST;
wach_din(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET) <= S_AXI_AWLOCK;
wach_din(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET) <= S_AXI_AWCACHE;
wach_din(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET) <= S_AXI_AWPROT;
wach_din(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET) <= S_AXI_AWQOS;
M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET);
M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET);
M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET);
M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET);
M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET);
M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET);
M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET);
END GENERATE gwach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE
wdch_din(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET) <= S_AXI_WUSER;
M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET);
END GENERATE gwdch_din1;
gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE
M_AXI_WUSER <= (OTHERS => '0');
END GENERATE gwdch_din2;
gwdch_din3: IF (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
wdch_din(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET) <= S_AXI_WID;
M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET);
END GENERATE gwdch_din3;
gwdch_din4: IF NOT (C_HAS_AXI_ID = 1 AND C_AXI_TYPE = 3) GENERATE
M_AXI_WID <= (OTHERS => '0');
END GENERATE gwdch_din4;
wdch_din(WID_OFFSET-1 DOWNTO WDATA_OFFSET) <= S_AXI_WDATA;
wdch_din(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET) <= S_AXI_WSTRB;
wdch_din(0) <= S_AXI_WLAST;
M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
M_AXI_WLAST <= wdch_dout(0);
END GENERATE gwdch1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE
wrch_din(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET) <= M_AXI_BUSER;
S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET);
END GENERATE gwrch_din1;
gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE
S_AXI_BUSER <= (OTHERS => '0');
END GENERATE gwrch_din2;
gwrch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
wrch_din(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET) <= M_AXI_BID;
S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET);
END GENERATE gwrch_din3;
gwrch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_BID <= (OTHERS => '0');
END GENERATE gwrch_din4;
wrch_din(BID_OFFSET-1 DOWNTO BRESP_OFFSET) <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_full_din_wr_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports
axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE
gwach1: IF (C_WACH_TYPE < 2) GENERATE
wach_din <= S_AXI_AWADDR & S_AXI_AWPROT;
M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET);
M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET);
END GENERATE gwach1;
gwdch1: IF (C_WDCH_TYPE < 2) GENERATE
wdch_din <= S_AXI_WDATA & S_AXI_WSTRB;
M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET);
M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET);
END GENERATE gwdch1;
gwrch1: IF (C_WRCH_TYPE < 2) GENERATE
wrch_din <= M_AXI_BRESP;
S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET);
END GENERATE gwrch1;
END GENERATE axi_lite_din_wr_ch;
-- Write protection for Write Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 0) GENERATE
wach_wr_en <= S_AXI_AWVALID;
END GENERATE gwach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 0) GENERATE
wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID;
END GENERATE gwach_wr_en2;
-- Write protection for Write Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 0) GENERATE
wdch_wr_en <= S_AXI_WVALID;
END GENERATE gwdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 0) GENERATE
wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID;
END GENERATE gwdch_wr_en2;
-- Write protection for Write Response Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 0) GENERATE
wrch_wr_en <= M_AXI_BVALID;
END GENERATE gwrch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 0) GENERATE
wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID;
END GENERATE gwrch_wr_en2;
-- Read protection for Write Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 0) GENERATE
gpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= awready_pkt AND awvalid_en;
END GENERATE;
gnpkt_mm_wach_rd_en1: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= M_AXI_AWREADY;
END GENERATE;
END GENERATE gwach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 0) GENERATE
gaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
END GENERATE gaxi_mm_wach_rd_en2;
gnaxi_mm_wach_rd_en2: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY;
END GENERATE gnaxi_mm_wach_rd_en2;
END GENERATE gwach_rd_en2;
-- Read protection for Write Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 0) GENERATE
wdch_rd_en <= M_AXI_WREADY;
END GENERATE gwdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 0) GENERATE
wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY;
END GENERATE gwdch_rd_en2;
-- Read protection for Write Response Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 0) GENERATE
wrch_rd_en <= S_AXI_BREADY;
END GENERATE gwrch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 0) GENERATE
wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY;
END GENERATE gwrch_rd_en2;
gwach2: IF (C_WACH_TYPE = 0) GENERATE
SIGNAL wach_we : STD_LOGIC := '0';
SIGNAL wach_re : STD_LOGIC := '0';
BEGIN
wach_we <= wach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wach_wr_en AND S_ACLK_EN;
wach_re <= wach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wach_rd_en AND M_ACLK_EN;
axi_wach : fifo_generator_v11_0_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WACH,
C_WR_DEPTH => C_WR_DEPTH_WACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_DOUT_WIDTH => C_DIN_WIDTH_WACH,
C_RD_DEPTH => C_WR_DEPTH_WACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH,
C_USE_ECC => C_USE_ECC_WACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_WACH = 1),0,C_APPLICATION_TYPE_WACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wach_we,
RD_EN => wach_re,
PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AW_INJECTDBITERR,
INJECTSBITERR => AXI_AW_INJECTSBITERR,
DIN => wach_din,
DOUT => wach_dout_pkt,
FULL => wach_full,
EMPTY => wach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AW_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AW_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_aw_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_aw_underflow_i,
DATA_COUNT => AXI_AW_DATA_COUNT,
RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT,
SBITERR => AXI_AW_SBITERR,
DBITERR => AXI_AW_DBITERR
);
-- wach_s_axi_awready <= map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full);
-- wach_m_axi_awvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty);
wach_s_axi_awready <= NOT wach_full;
wach_m_axi_awvalid <= NOT wach_empty;
S_AXI_AWREADY <= wach_s_axi_awready;
gawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL awvalid_pkt : STD_LOGIC := '0';
BEGIN
awvalid_pkt <= wach_m_axi_awvalid AND awvalid_en;
wach_pkt_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => wach_dout_pkt,
S_VALID => awvalid_pkt,
S_READY => awready_pkt,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gawvld_pkt_fifo;
gnawvld_pkt_fifo: IF (C_APPLICATION_TYPE_WACH /= 1) GENERATE
M_AXI_AWVALID <= wach_m_axi_awvalid;
wach_dout <= wach_dout_pkt;
END GENERATE gnawvld_pkt_fifo;
gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AW_UNDERFLOW <= axi_aw_underflow_i;
END GENERATE gaxi_wr_ch_uf1;
gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AW_OVERFLOW <= axi_aw_overflow_i;
END GENERATE gaxi_wr_ch_of1;
END GENERATE gwach2;
-- Register Slice for Write Address Channel
gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE
wach_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WACH,
C_REG_CONFIG => C_REG_SLICE_MODE_WACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wach_din,
S_VALID => S_AXI_AWVALID,
S_READY => S_AXI_AWREADY,
-- Master side
M_PAYLOAD_DATA => wach_dout,
M_VALID => M_AXI_AWVALID,
M_READY => M_AXI_AWREADY
);
END GENERATE gwach_reg_slice;
gwdch2: IF (C_WDCH_TYPE = 0) GENERATE
SIGNAL wdch_re : STD_LOGIC := '0';
BEGIN
wdch_we <= wdch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wdch_wr_en AND S_ACLK_EN;
wdch_re <= wdch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wdch_rd_en AND M_ACLK_EN;
axi_wdch : fifo_generator_v11_0_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WDCH,
C_WR_DEPTH => C_WR_DEPTH_WDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WDCH,
C_RD_DEPTH => C_WR_DEPTH_WDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH,
C_USE_ECC => C_USE_ECC_WDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wdch_we,
RD_EN => wdch_re,
PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_W_INJECTDBITERR,
INJECTSBITERR => AXI_W_INJECTSBITERR,
DIN => wdch_din,
DOUT => wdch_dout,
FULL => wdch_full,
EMPTY => wdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_W_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_W_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_w_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_w_underflow_i,
DATA_COUNT => AXI_W_DATA_COUNT,
RD_DATA_COUNT => AXI_W_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_W_WR_DATA_COUNT,
SBITERR => AXI_W_SBITERR,
DBITERR => AXI_W_DBITERR
);
-- wdch_s_axi_wready <= map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full);
-- wdch_m_axi_wvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty);
wdch_s_axi_wready <= NOT wdch_full;
wdch_m_axi_wvalid <= NOT wdch_empty;
S_AXI_WREADY <= wdch_s_axi_wready;
M_AXI_WVALID <= wdch_m_axi_wvalid;
gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_W_UNDERFLOW <= axi_w_underflow_i;
END GENERATE gaxi_wr_ch_uf2;
gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_W_OVERFLOW <= axi_w_overflow_i;
END GENERATE gaxi_wr_ch_of2;
END GENERATE gwdch2;
-- Register Slice for Write Data Channel
gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE
wdch_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wdch_din,
S_VALID => S_AXI_WVALID,
S_READY => S_AXI_WREADY,
-- Master side
M_PAYLOAD_DATA => wdch_dout,
M_VALID => M_AXI_WVALID,
M_READY => M_AXI_WREADY
);
END GENERATE gwdch_reg_slice;
gwrch2: IF (C_WRCH_TYPE = 0) GENERATE
SIGNAL wrch_we : STD_LOGIC := '0';
SIGNAL wrch_re : STD_LOGIC := '0';
BEGIN
wrch_we <= wrch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE wrch_wr_en AND S_ACLK_EN;
wrch_re <= wrch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE wrch_rd_en AND M_ACLK_EN;
axi_wrch : fifo_generator_v11_0_conv -- Write Response Channel
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_WRCH,
C_WR_DEPTH => C_WR_DEPTH_WRCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_DOUT_WIDTH => C_DIN_WIDTH_WRCH,
C_RD_DEPTH => C_WR_DEPTH_WRCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH,
C_USE_ECC => C_USE_ECC_WRCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_RD_FREQ => C_RD_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_WR_FREQ => C_WR_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => wrch_we,
RD_EN => wrch_re,
PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_B_INJECTDBITERR,
INJECTSBITERR => AXI_B_INJECTSBITERR,
DIN => wrch_din,
DOUT => wrch_dout,
FULL => wrch_full,
EMPTY => wrch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_B_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_B_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_b_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_b_underflow_i,
DATA_COUNT => AXI_B_DATA_COUNT,
RD_DATA_COUNT => AXI_B_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_B_WR_DATA_COUNT,
SBITERR => AXI_B_SBITERR,
DBITERR => AXI_B_DBITERR
);
-- wrch_s_axi_bvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty);
-- wrch_m_axi_bready <= map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full);
wrch_s_axi_bvalid <= NOT wrch_empty;
wrch_m_axi_bready <= NOT wrch_full;
S_AXI_BVALID <= wrch_s_axi_bvalid;
M_AXI_BREADY <= wrch_m_axi_bready;
gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_B_UNDERFLOW <= axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf3;
gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_B_OVERFLOW <= axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of3;
END GENERATE gwrch2;
-- Register Slice for Write Response Channel
gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE
wrch_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_WRCH,
C_REG_CONFIG => C_REG_SLICE_MODE_WRCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => wrch_din,
S_VALID => M_AXI_BVALID,
S_READY => M_AXI_BREADY,
-- Master side
M_PAYLOAD_DATA => wrch_dout,
M_VALID => S_AXI_BVALID,
M_READY => S_AXI_BREADY
);
END GENERATE gwrch_reg_slice;
gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i;
END GENERATE gaxi_wr_ch_uf4;
gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i;
END GENERATE gaxi_wr_ch_of4;
gaxi_pkt_fifo_wr: IF (C_APPLICATION_TYPE_WACH = 1) GENERATE
SIGNAL wr_pkt_count : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_WDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
BEGIN
txn_count_en_up <= wdch_s_axi_wready AND wdch_we AND wdch_din(0);
txn_count_en_down <= wach_m_axi_awvalid AND awready_pkt AND awvalid_en;
gaxi_mm_cc_pkt_wr: IF (C_COMMON_CLOCK = 1) GENERATE
proc_wr_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
wr_pkt_count <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (txn_count_en_up = '1' AND txn_count_en_down = '0') THEN
wr_pkt_count <= wr_pkt_count + conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
ELSIF (txn_count_en_down = '1' AND txn_count_en_up = '0') THEN
wr_pkt_count <= wr_pkt_count - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_WDCH+1);
END IF;
END IF;
END PROCESS proc_wr_txn_cnt;
awvalid_en <= '1' WHEN (wr_pkt_count > conv_std_logic_vector(0,C_WR_PNTR_WIDTH_WDCH)) ELSE '0';
END GENERATE gaxi_mm_cc_pkt_wr;
END GENERATE gaxi_pkt_fifo_wr;
END GENERATE gwrch;
grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE
SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_dout_pkt : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rach_full : std_logic := '0';
SIGNAL rach_almost_full : std_logic := '0';
SIGNAL rach_prog_full : std_logic := '0';
SIGNAL rach_empty : std_logic := '0';
SIGNAL rach_almost_empty : std_logic := '0';
SIGNAL rach_prog_empty : std_logic := '0';
SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdch_full : std_logic := '0';
SIGNAL rdch_almost_full : std_logic := '0';
SIGNAL rdch_prog_full : std_logic := '0';
SIGNAL rdch_empty : std_logic := '0';
SIGNAL rdch_almost_empty : std_logic := '0';
SIGNAL rdch_prog_empty : std_logic := '0';
SIGNAL axi_ar_underflow_i : std_logic := '0';
SIGNAL axi_ar_overflow_i : std_logic := '0';
SIGNAL axi_r_underflow_i : std_logic := '0';
SIGNAL axi_r_overflow_i : std_logic := '0';
SIGNAL rach_s_axi_arready : std_logic := '0';
SIGNAL rach_m_axi_arvalid : std_logic := '0';
SIGNAL rach_wr_en : std_logic := '0';
SIGNAL rach_rd_en : std_logic := '0';
SIGNAL rdch_m_axi_rready : std_logic := '0';
SIGNAL rdch_s_axi_rvalid : std_logic := '0';
SIGNAL rdch_wr_en : std_logic := '0';
SIGNAL rdch_rd_en : std_logic := '0';
SIGNAL arvalid_en : std_logic := '0';
SIGNAL arready_pkt : std_logic := '0';
SIGNAL rdch_re : STD_LOGIC := '0';
CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH);
CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH;
CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET);
CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET);
CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET);
CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET);
CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET);
CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH;
CONSTANT ARREGION_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARQOS_OFFSET - C_AXI_REGION_WIDTH,ARQOS_OFFSET);
CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET);
CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE /= 2 AND C_HAS_AXI_ID = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH);
CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH;
CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH;
CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET);
BEGIN
-- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports
axi_full_din_rd_ch: IF (C_AXI_TYPE /= 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE
rach_din(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET) <= S_AXI_ARUSER;
M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET);
END GENERATE grach_din1;
grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE
M_AXI_ARUSER <= (OTHERS => '0');
END GENERATE grach_din2;
grach_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rach_din(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET) <= S_AXI_ARID;
M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET);
END GENERATE grach_din3;
grach_din4: IF (C_HAS_AXI_ID = 0) GENERATE
M_AXI_ARID <= (OTHERS => '0');
END GENERATE grach_din4;
grach_din5: IF (C_AXI_TYPE = 1) GENERATE
rach_din(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET) <= S_AXI_ARREGION;
M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET);
END GENERATE grach_din5;
grach_din6: IF (C_AXI_TYPE = 0) GENERATE
M_AXI_ARREGION <= (OTHERS => '0');
END GENERATE grach_din6;
rach_din(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET) <= S_AXI_ARADDR;
rach_din(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET) <= S_AXI_ARLEN;
rach_din(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET) <= S_AXI_ARSIZE;
rach_din(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET) <= S_AXI_ARBURST;
rach_din(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET) <= S_AXI_ARLOCK;
rach_din(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET) <= S_AXI_ARCACHE;
rach_din(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET) <= S_AXI_ARPROT;
rach_din(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET) <= S_AXI_ARQOS;
M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET);
M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET);
M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET);
M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET);
M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET);
M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET);
M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET);
END GENERATE grach1;
-- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE
rdch_din(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET) <= M_AXI_RUSER;
S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET);
END GENERATE grdch_din1;
grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE
S_AXI_RUSER <= (OTHERS => '0');
END GENERATE grdch_din2;
grdch_din3: IF (C_HAS_AXI_ID = 1) GENERATE
rdch_din(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET) <= M_AXI_RID;
S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET);
END GENERATE grdch_din3;
grdch_din4: IF (C_HAS_AXI_ID = 0) GENERATE
S_AXI_RID <= (OTHERS => '0');
END GENERATE grdch_din4;
rdch_din(RID_OFFSET-1 DOWNTO RDATA_OFFSET) <= M_AXI_RDATA;
rdch_din(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET) <= M_AXI_RRESP;
rdch_din(0) <= M_AXI_RLAST;
S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
S_AXI_RLAST <= rdch_dout(0);
END GENERATE grdch1;
END GENERATE axi_full_din_rd_ch;
-- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports
axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE
grach1: IF (C_RACH_TYPE < 2) GENERATE
rach_din <= S_AXI_ARADDR & S_AXI_ARPROT;
M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET);
M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET);
END GENERATE grach1;
grdch1: IF (C_RDCH_TYPE < 2) GENERATE
rdch_din <= M_AXI_RDATA & M_AXI_RRESP;
S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET);
S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET);
END GENERATE grdch1;
END GENERATE axi_lite_din_rd_ch;
-- Write protection for Read Address Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 0) GENERATE
rach_wr_en <= S_AXI_ARVALID;
END GENERATE grach_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 0) GENERATE
rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID;
END GENERATE grach_wr_en2;
-- Write protection for Read Data Channel
-- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt
grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 0) GENERATE
rdch_wr_en <= M_AXI_RVALID;
END GENERATE grdch_wr_en1;
-- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL
grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 0) GENERATE
rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID;
END GENERATE grdch_wr_en2;
-- Read protection for Read Address Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 0) GENERATE
gpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= arready_pkt AND arvalid_en;
END GENERATE;
gnpkt_mm_rach_rd_en1: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= M_AXI_ARREADY;
END GENERATE;
END GENERATE grach_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 0) GENERATE
gaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
END GENERATE gaxi_mm_rach_rd_en2;
gnaxi_mm_rach_rd_en2: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY;
END GENERATE gnaxi_mm_rach_rd_en2;
END GENERATE grach_rd_en2;
-- Read protection for Read Data Channel
-- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt
grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 0) GENERATE
rdch_rd_en <= S_AXI_RREADY;
END GENERATE grdch_rd_en1;
-- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY
grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 0) GENERATE
rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY;
END GENERATE grdch_rd_en2;
grach2: IF (C_RACH_TYPE = 0) GENERATE
SIGNAL rach_we : STD_LOGIC := '0';
SIGNAL rach_re : STD_LOGIC := '0';
BEGIN
rach_we <= rach_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rach_wr_en AND S_ACLK_EN;
rach_re <= rach_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE rach_rd_en AND M_ACLK_EN;
axi_rach : fifo_generator_v11_0_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RACH,
C_WR_DEPTH => C_WR_DEPTH_RACH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_DOUT_WIDTH => C_DIN_WIDTH_RACH,
C_RD_DEPTH => C_WR_DEPTH_RACH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH,
C_USE_ECC => C_USE_ECC_RACH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => if_then_else((C_APPLICATION_TYPE_RACH = 1),0,C_APPLICATION_TYPE_RACH),
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => S_ACLK,
RD_CLK => M_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rach_we,
RD_EN => rach_re,
PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_AR_INJECTDBITERR,
INJECTSBITERR => AXI_AR_INJECTSBITERR,
DIN => rach_din,
DOUT => rach_dout_pkt,
FULL => rach_full,
EMPTY => rach_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_AR_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_AR_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_ar_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_ar_underflow_i,
DATA_COUNT => AXI_AR_DATA_COUNT,
RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT,
SBITERR => AXI_AR_SBITERR,
DBITERR => AXI_AR_DBITERR
);
-- rach_s_axi_arready <= map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full);
-- rach_m_axi_arvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty);
rach_s_axi_arready <= NOT rach_full;
rach_m_axi_arvalid <= NOT rach_empty;
S_AXI_ARREADY <= rach_s_axi_arready;
gaxi_arvld: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL arvalid_pkt : STD_LOGIC := '0';
BEGIN
arvalid_pkt <= rach_m_axi_arvalid AND arvalid_en;
rach_pkt_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => 1
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => inverted_reset,
-- Slave side
S_PAYLOAD_DATA => rach_dout_pkt,
S_VALID => arvalid_pkt,
S_READY => arready_pkt,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE gaxi_arvld;
gnaxi_arvld: IF (C_APPLICATION_TYPE_RACH /= 1) GENERATE
M_AXI_ARVALID <= rach_m_axi_arvalid;
rach_dout <= rach_dout_pkt;
END GENERATE gnaxi_arvld;
gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_AR_UNDERFLOW <= axi_ar_underflow_i;
END GENERATE gaxi_rd_ch_uf1;
gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_AR_OVERFLOW <= axi_ar_overflow_i;
END GENERATE gaxi_rd_ch_of1;
END GENERATE grach2;
-- Register Slice for Read Address Channel
grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE
rach_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RACH,
C_REG_CONFIG => C_REG_SLICE_MODE_RACH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rach_din,
S_VALID => S_AXI_ARVALID,
S_READY => S_AXI_ARREADY,
-- Master side
M_PAYLOAD_DATA => rach_dout,
M_VALID => M_AXI_ARVALID,
M_READY => M_AXI_ARREADY
);
END GENERATE grach_reg_slice;
grdch2: IF (C_RDCH_TYPE = 0) GENERATE
SIGNAL rdch_we : STD_LOGIC := '0';
BEGIN
rdch_we <= rdch_wr_en WHEN (C_HAS_SLAVE_CE = 0) ELSE rdch_wr_en AND S_ACLK_EN;
rdch_re <= rdch_rd_en WHEN (C_HAS_MASTER_CE = 0) ELSE rdch_rd_en AND M_ACLK_EN;
axi_rdch : fifo_generator_v11_0_conv
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_COMMON_CLOCK => C_COMMON_CLOCK,
C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,2),
C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH <= 6),0,2), -- CCBI
C_PRELOAD_REGS => 1, -- Always FWFT for AXI
C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI
C_DIN_WIDTH => C_DIN_WIDTH_RDCH,
C_WR_DEPTH => C_WR_DEPTH_RDCH,
C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_DOUT_WIDTH => C_DIN_WIDTH_RDCH,
C_RD_DEPTH => C_WR_DEPTH_RDCH,
C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH,
C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH,
C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH,
C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH,
C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH,
C_USE_ECC => C_USE_ECC_RDCH,
C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
-- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO
C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_AXI_TYPE => if_then_else(C_INTERFACE_TYPE = 1, 0, C_AXI_TYPE),
C_HAS_WR_RST => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_DOUT_RST_VAL => "0",
C_HAS_VALID => C_HAS_VALID,
C_VALID_LOW => C_VALID_LOW,
C_HAS_UNDERFLOW => C_HAS_UNDERFLOW,
C_UNDERFLOW_LOW => C_UNDERFLOW_LOW,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_HAS_OVERFLOW => C_HAS_OVERFLOW,
C_OVERFLOW_LOW => C_OVERFLOW_LOW,
C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true
C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0),
C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1,
C_FULL_FLAGS_RST_VAL => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_DOUT_RST => 0,
C_MSGON_VAL => C_MSGON_VAL,
C_ENABLE_RST_SYNC => 1,
C_COUNT_TYPE => C_COUNT_TYPE,
C_DEFAULT_VALUE => C_DEFAULT_VALUE,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_HAS_BACKUP => C_HAS_BACKUP,
C_HAS_INT_CLK => C_HAS_INT_CLK,
C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE,
C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL,
C_MIF_FILE_NAME => C_MIF_FILE_NAME,
C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE,
C_WR_FREQ => C_WR_FREQ,
C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS,
C_RD_FREQ => C_RD_FREQ,
C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY
)
PORT MAP(
--Inputs
BACKUP => BACKUP,
BACKUP_MARKER => BACKUP_MARKER,
INT_CLK => INT_CLK,
CLK => S_ACLK,
WR_CLK => M_ACLK,
RD_CLK => S_ACLK,
RST => inverted_reset,
SRST => '0',
WR_RST => inverted_reset,
RD_RST => inverted_reset,
WR_EN => rdch_we,
RD_EN => rdch_re,
PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH,
PROG_FULL_THRESH_ASSERT => (OTHERS => '0'),
PROG_FULL_THRESH_NEGATE => (OTHERS => '0'),
PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH,
PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'),
PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'),
INJECTDBITERR => AXI_R_INJECTDBITERR,
INJECTSBITERR => AXI_R_INJECTSBITERR,
DIN => rdch_din,
DOUT => rdch_dout,
FULL => rdch_full,
EMPTY => rdch_empty,
ALMOST_FULL => OPEN,
PROG_FULL => AXI_R_PROG_FULL,
ALMOST_EMPTY => OPEN,
PROG_EMPTY => AXI_R_PROG_EMPTY,
WR_ACK => OPEN,
OVERFLOW => axi_r_overflow_i,
VALID => OPEN,
UNDERFLOW => axi_r_underflow_i,
DATA_COUNT => AXI_R_DATA_COUNT,
RD_DATA_COUNT => AXI_R_RD_DATA_COUNT,
WR_DATA_COUNT => AXI_R_WR_DATA_COUNT,
SBITERR => AXI_R_SBITERR,
DBITERR => AXI_R_DBITERR
);
-- rdch_s_axi_rvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty);
-- rdch_m_axi_rready <= map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full);
rdch_s_axi_rvalid <= NOT rdch_empty;
rdch_m_axi_rready <= NOT rdch_full;
S_AXI_RVALID <= rdch_s_axi_rvalid;
M_AXI_RREADY <= rdch_m_axi_rready;
gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE
AXI_R_UNDERFLOW <= axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf2;
gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE
AXI_R_OVERFLOW <= axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of2;
END GENERATE grdch2;
-- Register Slice for Read Data Channel
grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE
rdch_reg_slice: fifo_generator_v11_0_axic_reg_slice
GENERIC MAP (
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DIN_WIDTH_RDCH,
C_REG_CONFIG => C_REG_SLICE_MODE_RDCH
)
PORT MAP(
-- System Signals
ACLK => S_ACLK,
ARESET => axi_rs_rst,
-- Slave side
S_PAYLOAD_DATA => rdch_din,
S_VALID => M_AXI_RVALID,
S_READY => M_AXI_RREADY,
-- Master side
M_PAYLOAD_DATA => rdch_dout,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY
);
END GENERATE grdch_reg_slice;
gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i;
END GENERATE gaxi_rd_ch_uf3;
gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i;
END GENERATE gaxi_rd_ch_of3;
gaxi_pkt_fifo_rd: IF (C_APPLICATION_TYPE_RACH = 1) GENERATE
SIGNAL rd_burst_length : STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_free_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_fifo_committed_space : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH_RDCH DOWNTO 0) := (OTHERS => '0');
SIGNAL txn_count_en_up : STD_LOGIC := '0';
SIGNAL txn_count_en_down : STD_LOGIC := '0';
SIGNAL rdch_rd_ok : STD_LOGIC := '0';
SIGNAL accept_next_pkt : STD_LOGIC := '0';
SIGNAL decrement_val : INTEGER := 0;
BEGIN
rd_burst_length <= ('0' & rach_dout_pkt(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET)) + conv_std_logic_vector(1,9);
accept_next_pkt <= rach_m_axi_arvalid AND arready_pkt AND arvalid_en;
rdch_rd_ok <= rdch_re AND rdch_s_axi_rvalid;
arvalid_en <= '1' WHEN (rd_fifo_free_space >= rd_burst_length) ELSE '0';
gaxi_mm_cc_pkt_rd: IF (C_COMMON_CLOCK = 1) GENERATE
rd_fifo_free_space <= conv_std_logic_vector(C_WR_DEPTH_RDCH-conv_integer(rd_fifo_committed_space),C_WR_PNTR_WIDTH_RDCH+1);
decrement_val <= 1 WHEN (rdch_rd_ok = '1') ELSE 0;
proc_rd_txn_cnt: PROCESS (S_ACLK, inverted_reset)
BEGIN
IF (inverted_reset = '1') THEN
rd_fifo_committed_space <= (OTHERS => '0');
ELSIF (S_ACLK'EVENT AND S_ACLK = '1') THEN
IF (accept_next_pkt = '1') THEN
-- Subtract 1 if read happens on read data FIFO while adding ARLEN
rd_fifo_committed_space <= rd_fifo_committed_space + conv_std_logic_vector((conv_integer(rd_burst_length) - decrement_val), C_WR_PNTR_WIDTH_RDCH+1);
ELSIF (rdch_rd_ok = '1') THEN
-- Subtract 1 whenever read happens on read data FIFO
rd_fifo_committed_space <= rd_fifo_committed_space - conv_std_logic_vector(1,C_WR_PNTR_WIDTH_RDCH+1);
END IF;
END IF;
END PROCESS proc_rd_txn_cnt;
END GENERATE gaxi_mm_cc_pkt_rd;
END GENERATE gaxi_pkt_fifo_rd;
END GENERATE grdch;
gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE
grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i;
END GENERATE grdwr_uf1;
grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
UNDERFLOW <= axi_wr_underflow_i;
END GENERATE grdwr_uf2;
grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
UNDERFLOW <= axi_rd_underflow_i;
END GENERATE grdwr_uf3;
END GENERATE gaxi_comm_uf;
gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE
grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i;
END GENERATE grdwr_of1;
grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE
OVERFLOW <= axi_wr_overflow_i;
END GENERATE grdwr_of2;
grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE
OVERFLOW <= axi_rd_overflow_i;
END GENERATE grdwr_of3;
END GENERATE gaxi_comm_of;
END GENERATE gaxifull;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pass Through Logic or Wiring Logic
---------------------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR
C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE
gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel
M_AXI_AWID <= S_AXI_AWID;
M_AXI_AWADDR <= S_AXI_AWADDR;
M_AXI_AWLEN <= S_AXI_AWLEN;
M_AXI_AWSIZE <= S_AXI_AWSIZE;
M_AXI_AWBURST <= S_AXI_AWBURST;
M_AXI_AWLOCK <= S_AXI_AWLOCK;
M_AXI_AWCACHE <= S_AXI_AWCACHE;
M_AXI_AWPROT <= S_AXI_AWPROT;
M_AXI_AWQOS <= S_AXI_AWQOS;
M_AXI_AWREGION <= S_AXI_AWREGION;
M_AXI_AWUSER <= S_AXI_AWUSER;
S_AXI_AWREADY <= M_AXI_AWREADY;
M_AXI_AWVALID <= S_AXI_AWVALID;
END GENERATE gwach_pass_through;
-- Wiring logic for Write Data Channel
gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE
M_AXI_WID <= S_AXI_WID;
M_AXI_WDATA <= S_AXI_WDATA;
M_AXI_WSTRB <= S_AXI_WSTRB;
M_AXI_WLAST <= S_AXI_WLAST;
M_AXI_WUSER <= S_AXI_WUSER;
S_AXI_WREADY <= M_AXI_WREADY;
M_AXI_WVALID <= S_AXI_WVALID;
END GENERATE gwdch_pass_through;
-- Wiring logic for Write Response Channel
gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE
S_AXI_BID <= M_AXI_BID;
S_AXI_BRESP <= M_AXI_BRESP;
S_AXI_BUSER <= M_AXI_BUSER;
M_AXI_BREADY <= S_AXI_BREADY;
S_AXI_BVALID <= M_AXI_BVALID;
END GENERATE gwrch_pass_through;
-- Pass Through Logic for Read Channel
grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel
M_AXI_ARID <= S_AXI_ARID;
M_AXI_ARADDR <= S_AXI_ARADDR;
M_AXI_ARLEN <= S_AXI_ARLEN;
M_AXI_ARSIZE <= S_AXI_ARSIZE;
M_AXI_ARBURST <= S_AXI_ARBURST;
M_AXI_ARLOCK <= S_AXI_ARLOCK;
M_AXI_ARCACHE <= S_AXI_ARCACHE;
M_AXI_ARPROT <= S_AXI_ARPROT;
M_AXI_ARQOS <= S_AXI_ARQOS;
M_AXI_ARREGION <= S_AXI_ARREGION;
M_AXI_ARUSER <= S_AXI_ARUSER;
S_AXI_ARREADY <= M_AXI_ARREADY;
M_AXI_ARVALID <= S_AXI_ARVALID;
END GENERATE grach_pass_through;
grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel
S_AXI_RID <= M_AXI_RID;
S_AXI_RLAST <= M_AXI_RLAST;
S_AXI_RUSER <= M_AXI_RUSER;
S_AXI_RDATA <= M_AXI_RDATA;
S_AXI_RRESP <= M_AXI_RRESP;
S_AXI_RVALID <= M_AXI_RVALID;
M_AXI_RREADY <= S_AXI_RREADY;
END GENERATE grdch_pass_through;
gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TKEEP <= S_AXIS_TKEEP;
M_AXIS_TID <= S_AXIS_TID;
M_AXIS_TDEST <= S_AXIS_TDEST;
M_AXIS_TUSER <= S_AXIS_TUSER;
M_AXIS_TLAST <= S_AXIS_TLAST;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TVALID <= S_AXIS_TVALID;
END GENERATE gaxis_pass_through;
END GENERATE gaxi_pass_through;
END behavioral;
| bsd-2-clause | ce73cbfbca2cb869c2ecbd772456046f | 0.466175 | 3.791525 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_waveforms/rule_101_test_input.vhd | 2 | 409 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when(rd_en = '1') else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when(rd_en = '1') else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when(rd_en = '1') else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
| gpl-3.0 | aad27e0d1900a5ea619ff6ec51ecb18b | 0.528117 | 2.524691 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/fir_compiler_v7_1_viv.vhd | 2 | 86,797 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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Tk3OrsXkmA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62512)
`protect data_block
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| mit | 68abc8ba23bfb6ff6004f4b0a139038b | 0.952936 | 1.820636 | false | false | false | false |
zcold/fft.vhdl | lib/fixed_pkg_c.vhdl | 1 | 304,037 | -- --------------------------------------------------------------------
-- "fixed_pkg_c.vhdl" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_float_types.all;
-- use ieee_proposed.fixed_pkg.all;
--
-- This verison is designed to work with the VHDL-93 compilers
-- synthesis tools. Please note the "%%%" comments. These are where we
-- diverge from the VHDL-200X LRM.
-- --------------------------------------------------------------------
-- Version : $Revision: 2.0 $
-- Date : $Date: 2011/01/26 15:55:27 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library IEEE_PROPOSED;
use IEEE_PROPOSED.fixed_float_types.all;
package fixed_pkg is
-- generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
constant fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
constant fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
-- Extra bits used in divide routines
constant fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
constant no_warning : BOOLEAN := (false
);
-- Author David Bishop ([email protected])
-- base Unsigned fixed point type, downto direction assumed
type UNRESOLVED_ufixed is array (INTEGER range <>) of STD_ULOGIC;
-- base Signed fixed point type, downto direction assumed
type UNRESOLVED_sfixed is array (INTEGER range <>) of STD_ULOGIC;
subtype U_ufixed is UNRESOLVED_ufixed;
subtype U_sfixed is UNRESOLVED_sfixed;
subtype ufixed is UNRESOLVED_ufixed;
subtype sfixed is UNRESOLVED_sfixed;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Absolute value, 2's complement
-- abs sfixed(a downto b) = sfixed(a+1 downto b)
function "abs" (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Negation, 2's complement
-- - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (arg : UNRESOLVED_sfixed)return UNRESOLVED_sfixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "+" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(maximum(a,c)+1 downto minimum(b,d))
function "-" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function "rem" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function "mod" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "+" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto minimum(0,d))
function "-" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "rem" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_ufixed; r : NATURAL) return UNRESOLVED_ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto minimum(d,0))
function "mod" (l : NATURAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "+" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "+" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto minimum(0,b))
function "-" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto minimum(0,d))
function "-" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "rem" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "rem" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto minimum(b,0))
function "mod" (l : UNRESOLVED_sfixed; r : INTEGER) return UNRESOLVED_sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto minimum(d,0))
function "mod" (l : INTEGER; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (minimum(a,c) downto minimum(b,d))
function remainder (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (minimum(a,c) downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto minimum(b, d))
function modulo (
l, r : UNRESOLVED_sfixed;
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (maximum(a,c) downto minimum(b,d))
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the binary point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED) return UNRESOLVED_ufixed;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER) return UNRESOLVED_sfixed;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED) return UNRESOLVED_sfixed;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l, r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l, r : UNRESOLVED_sfixed) return STD_ULOGIC;
function std_match (l, r : UNRESOLVED_ufixed) return BOOLEAN;
function std_match (l, r : UNRESOLVED_sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "maximum(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : NATURAL) return STD_ULOGIC;
function \?=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : NATURAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : NATURAL)
return UNRESOLVED_ufixed;
function maximum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function minimum (l : NATURAL; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_ufixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_ufixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_ufixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function maximum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function minimum (l : UNRESOLVED_ufixed; r : REAL) return UNRESOLVED_ufixed;
function minimum (l : REAL; r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "maximum(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : INTEGER) return STD_ULOGIC;
function \?=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : INTEGER; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function maximum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : INTEGER)
return UNRESOLVED_sfixed;
function minimum (l : INTEGER; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "/=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<=" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function ">" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "<" (l : UNRESOLVED_sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "/=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<=" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function ">" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function "<" (l : REAL; r : UNRESOLVED_sfixed) return BOOLEAN;
function \?=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?/=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<=\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?>\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?<\ (l : UNRESOLVED_sfixed; r : REAL) return STD_ULOGIC;
function \?=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?/=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<=\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?>\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function \?<\ (l : REAL; r : UNRESOLVED_sfixed) return STD_ULOGIC;
function maximum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function maximum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function minimum (l : UNRESOLVED_sfixed; r : REAL) return UNRESOLVED_sfixed;
function minimum (l : REAL; r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed;
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed;
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (l : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "and" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "or" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nand" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "nor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "xnor" (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function "not" (l : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "and" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "or" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nand" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "nor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function "xnor" (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "and" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "or" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nand" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "nor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
function "xnor" (l : UNRESOLVED_ufixed; r : STD_ULOGIC)
return UNRESOLVED_ufixed;
function "and" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "and" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "or" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "or" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nand" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nand" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "nor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "nor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
function "xnor" (l : STD_ULOGIC; r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
function "xnor" (l : UNRESOLVED_sfixed; r : STD_ULOGIC)
return UNRESOLVED_sfixed;
-- Reduction operators, same as numeric_std functions
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC;
-- returns arg'low-1 if not found
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
-- returns arg'high+1 if not found
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is fixed_round, then the result will be rounded.
-- If the MSB of the remainder is a "1" AND the LSB of the unrounded result
-- is a '1' or the lower bits of the remainder include a '1' then the result
-- will be increased by the smallest representable number for that type.
-- "overflow_style" can be fixed_saturate or fixed_wrap.
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- "size_res" functions create the size of the output from the indices
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed;
-- Performs a conversion. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : UNRESOLVED_ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : UNRESOLVED_ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL;
-- Integer to UNRESOLVED_sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed;
-- Conversion from ufixed to sfixed
function to_sfixed (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_sfixed;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : UNRESOLVED_sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED;
-- signed fixed point to real
function to_real (
arg : UNRESOLVED_sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'a' or 'A' (abs), 'n' or 'N' (unary -)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
--
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_ufixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed;
-- maps meta-logical values
function to_01 (
s : UNRESOLVED_sfixed; -- fixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed;
function Is_X (arg : UNRESOLVED_ufixed) return BOOLEAN;
function Is_X (arg : UNRESOLVED_sfixed) return BOOLEAN;
function to_X01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_X01Z (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_X01Z (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
function to_UX01 (arg : UNRESOLVED_ufixed) return UNRESOLVED_ufixed;
function to_UX01 (arg : UNRESOLVED_sfixed) return UNRESOLVED_sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not convert these vectors because of their negative index.
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_ufixed
return STD_LOGIC_VECTOR];
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR;
alias to_StdLogicVector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
alias to_Std_Logic_Vector is to_slv [UNRESOLVED_sfixed
return STD_LOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_ufixed
return STD_ULOGIC_VECTOR];
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR;
alias to_StdULogicVector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
alias to_Std_ULogic_Vector is to_sulv [UNRESOLVED_sfixed
return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- rtl_synthesis off
-- pragma synthesis_off
--===========================================================================
-- string and textio Functions
--===========================================================================
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias bwrite is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias bread is READ [LINE, UNRESOLVED_ufixed];
alias bread is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias bread is READ [LINE, UNRESOLVED_sfixed];
alias bread is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_ufixed, SIDE, width];
alias BINARY_WRITE is WRITE [LINE, UNRESOLVED_sfixed, SIDE, width];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_ufixed];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias BINARY_READ is READ [LINE, UNRESOLVED_sfixed];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_ufixed];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNRESOLVED_sfixed];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed);
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN);
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNRESOLVED_ufixed];
alias HEX_READ is HREAD [LINE, UNRESOLVED_sfixed];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_ufixed, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, UNRESOLVED_sfixed, SIDE, WIDTH];
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (value : UNRESOLVED_ufixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_ufixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_ufixed return STRING];
function to_ostring (value : UNRESOLVED_ufixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_ufixed return STRING];
function to_hstring (value : UNRESOLVED_ufixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_ufixed return STRING];
function to_string (value : UNRESOLVED_sfixed) return STRING;
alias to_bstring is to_string [UNRESOLVED_sfixed return STRING];
alias TO_BINARY_STRING is TO_STRING [UNRESOLVED_sfixed return STRING];
function to_ostring (value : UNRESOLVED_sfixed) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [UNRESOLVED_sfixed return STRING];
function to_hstring (value : UNRESOLVED_sfixed) return STRING;
alias TO_HEX_STRING is TO_HSTRING [UNRESOLVED_sfixed return STRING];
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, INTEGER, INTEGER
return UNRESOLVED_sfixed];
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_ufixed
return UNRESOLVED_ufixed];
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING, UNRESOLVED_sfixed
return UNRESOLVED_sfixed];
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed;
alias from_bstring is from_string [STRING return UNRESOLVED_ufixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_ufixed];
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_ufixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_ufixed];
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed;
alias from_bstring is from_string [STRING return UNRESOLVED_sfixed];
alias from_binary_string is from_string [STRING return UNRESOLVED_sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed;
alias from_octal_string is from_ostring [STRING return UNRESOLVED_sfixed];
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed;
alias from_hex_string is from_hstring [STRING return UNRESOLVED_sfixed];
-- rtl_synthesis on
-- pragma synthesis_on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed;
end package fixed_pkg;
-------------------------------------------------------------------------------
-- Proposed package body for the VHDL-200x-FT fixed_pkg package
-- (Fixed point math package)
-- This package body supplies a recommended implementation of these functions
-- Version : $Revision: 2.0 $
-- Date : $Date: 2011/01/26 15:55:27 $
--
-- Created for VHDL-200X-ft, David Bishop ([email protected])
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : UNRESOLVED_ufixed (0 downto 1) := (others => '0');
constant NASF : UNRESOLVED_sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_ULOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
-- %%% Replicated functions
function maximum (
l, r : integer) -- inputs
return integer is
begin -- function max
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (
l, r : integer) -- inputs
return integer is
begin -- function min
if l > r then return r;
else return l;
end if;
end function minimum;
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
function or_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reduce (BUS_int (BUS_int'left downto Half));
Lower := or_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reduce;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reduce (arg : STD_ULOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reduce (BUS_int (BUS_int'left downto Half));
Lower := and_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reduce;
function xor_reduce (arg : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_ULOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reduce (BUS_int (BUS_int'left downto Half));
Lower := xor_reduce (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reduce;
function nand_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not and_reduce (arg);
end function nand_reduce;
function nor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not or_reduce (arg);
end function nor_reduce;
function xnor_reduce(arg : std_ulogic_vector) return STD_ULOGIC is
begin
return not xor_reduce (arg);
end function xnor_reduce;
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-- constant match_logic_table : stdlogic_table := (
-- -----------------------------------------------------
-- -- U X 0 1 Z W L H - | |
-- -----------------------------------------------------
-- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
-- ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
-- ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
-- ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
-- ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
-- ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
-- ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
-- ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
-- ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
-- );
-- purpose: Syntheis verison of the match_logic_table
function match_logic_table (
l, r : std_ulogic)
return std_ulogic is
variable lx, rx : STD_ULOGIC;
begin -- match_logic_table
lx := to_x01(l);
rx := to_x01(r);
if lx = 'X' or rx = 'X' then
return 'X';
elsif lx = rx then
return '1';
else
return '0';
end if;
end match_logic_table;
-- constant no_match_logic_table : stdlogic_table := (
-- -----------------------------------------------------
-- -- U X 0 1 Z W L H - | |
-- -----------------------------------------------------
-- ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
-- ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
-- ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
-- ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
-- ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
-- ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
-- ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
-- ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
-- ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
-- );
function no_match_logic_table (
l, r : std_ulogic)
return std_ulogic is
begin -- no_match_logic_table
return not match_logic_table (l, r);
end no_match_logic_table;
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- Id: M.3B
function \?=\ (L, R: SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
result := 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function \?/=\ (L, R : SIGNED) return std_ulogic is
constant L_LEFT : INTEGER := L'LENGTH-1;
constant R_LEFT : INTEGER := R'LENGTH-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAXIMUM(L'LENGTH, R'LENGTH);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% END replicated functions
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition, silent
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report fixed_pkg'instance_name
& " Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_sfixed) -- input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_sfixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : UNRESOLVED_ufixed) -- input
return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : UNRESOLVED_ufixed (arg'range);
begin -- function cleanvec
assert not (arg'ascending and (arg'low /= INTEGER'low))
report fixed_pkg'instance_name
& " Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type convert a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_ufixed(arg);
return result;
end function to_fixed;
-- Type convert a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin -- function to_fixed
result := UNRESOLVED_sfixed(arg);
return result;
end function to_fixed;
-- Type convert a "ufixed" into an "unsigned", used internally
function to_uns (
arg : UNRESOLVED_ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
return slv;
end function to_uns;
-- Type convert an "sfixed" into a "signed", used internally
function to_s (
arg : UNRESOLVED_sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
return slv;
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_ufixed;
result : out UNRESOLVED_ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0)
:= (others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in UNRESOLVED_sfixed;
result : out UNRESOLVED_sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reduce (STD_ULOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : UNRESOLVED_ufixed;
remainder : UNRESOLVED_ufixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : UNRESOLVED_sfixed;
remainder : UNRESOLVED_sfixed;
overflow_style : fixed_overflow_style_type := fixed_overflow_style)
return UNRESOLVED_sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : UNRESOLVED_sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reduce (to_sulv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- Sign bit not fixed when wrapping
end if;
end if;
return result;
end function round_fixed;
-- converts an sfixed into a ufixed. The output is the same length as the
-- input, because abs("1000") = "1000" = 8.
function to_ufixed (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_ufixed
is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : UNRESOLVED_sfixed(left_index+1 downto right_index);
variable result : UNRESOLVED_ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := UNRESOLVED_ufixed (xarg (left_index downto right_index));
return result;
end function to_ufixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- Conversion functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_sulv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_sulv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
variable result : STD_ULOGIC_VECTOR (arg'length-1 downto 0);
begin
if arg'length < 1 then
return NSLV;
end if;
result := STD_ULOGIC_VECTOR (arg);
return result;
end function to_sulv;
function to_slv (
arg : UNRESOLVED_ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_slv (
arg : UNRESOLVED_sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
begin
return to_stdlogicvector(to_sulv(arg));
end function to_slv;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_UFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return unresolved_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report fixed_pkg'instance_name & "TO_SFIXED(SLV) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
-- Addition
function "+" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mine(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1 or result'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : UNRESOLVED_sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : UNRESOLVED_ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return UNRESOLVED_ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : UNRESOLVED_sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return UNRESOLVED_sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : UNRESOLVED_ufixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (l'high - mine(r'low, r'low) downto
mine (l'low, l'low) - r'high -1);
variable dresult : UNRESOLVED_ufixed (result'high downto result'low -guard_bits);
variable lresize : UNRESOLVED_ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : UNRESOLVED_sfixed;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (l'high - mine(r'low, r'low) + 1 downto
mine (l'low, l'low) - r'high);
variable dresult : UNRESOLVED_sfixed (result'high downto result'low-guard_bits);
variable lresize : UNRESOLVED_sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report fixed_pkg'instance_name
& "DIVIDE(sfixed) Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- overflow impossible
round_style => round_style);
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
constant one : UNRESOLVED_ufixed (0 downto 0) := "1";
begin
return divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
constant one : UNRESOLVED_sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : UNRESOLVED_sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide (l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return remainder (l, r);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return remainder (l, r);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (minimum(l'high, r'high) downto
mine(l'low, r'low));
variable lresize : UNRESOLVED_ufixed (maximum(l'high, r'low) downto
mins(r'low, r'low)-guard_bits);
variable rresize : UNRESOLVED_ufixed (r'high downto r'low-guard_bits);
variable dresult : UNRESOLVED_ufixed (rresize'range);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (rresize'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rresize := resize (arg => r,
left_index => rresize'high,
right_index => rresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
rslv := to_uns (rresize);
if (rslv = 0) then
report fixed_pkg'instance_name
& "remainder(ufixed) Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap, -- can't overflow
round_style => round_style);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (minimum(r'high, l'high) downto
mine(r'low, l'low));
variable neg_result : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
result := UNRESOLVED_sfixed (remainder (
l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return modulo (l, r);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return modulo(l, r);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : UNRESOLVED_ufixed; -- fixed point input
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style,
guard_bits => guard_bits);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return UNRESOLVED_sfixed is
variable l_abs : UNRESOLVED_ufixed (l'range);
variable r_abs : UNRESOLVED_ufixed (r'range);
variable result : UNRESOLVED_sfixed (r'high downto
mine(r'low, l'low));
variable dresult : UNRESOLVED_sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := to_ufixed (l);
r_abs := to_ufixed (r);
dresult := "0" & UNRESOLVED_sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in UNRESOLVED_ufixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in UNRESOLVED_sfixed;
c_in : in STD_ULOGIC;
result : out UNRESOLVED_sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : UNRESOLVED_ufixed; N : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_ufixed; N : SIGNED)
return UNRESOLVED_ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : UNRESOLVED_sfixed; N : SIGNED)
return UNRESOLVED_sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : UNRESOLVED_sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_rightmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_ufixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function find_rightmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'reverse_range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_rightmost;
function find_leftmost (arg : UNRESOLVED_sfixed; y : STD_ULOGIC)
return INTEGER is
begin
for_loop : for i in arg'range loop
if \?=\ (arg(i), y) = '1' then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_leftmost;
function "sll" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_ufixed; COUNT : INTEGER)
return UNRESOLVED_ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : UNRESOLVED_sfixed; COUNT : INTEGER)
return UNRESOLVED_sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : UNRESOLVED_sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_ufixed; COUNT : NATURAL)
return UNRESOLVED_ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : UNRESOLVED_sfixed; COUNT : NATURAL)
return UNRESOLVED_sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_sulv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) and to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) or to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nand to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) nor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
variable RESULT : STD_ULOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_sulv(L) xnor to_sulv(R);
else
assert NO_WARNING
report fixed_pkg'instance_name
& """xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'X');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_ufixed; R : STD_ULOGIC)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : UNRESOLVED_sfixed; R : STD_ULOGIC)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operator_reduces
function and_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_ufixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
function and_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return and_reduce (to_sulv(l));
end function and_reduce;
function nand_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nand_reduce (to_sulv(l));
end function nand_reduce;
function or_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return or_reduce (to_sulv(l));
end function or_reduce;
function nor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return nor_reduce (to_sulv(l));
end function nor_reduce;
function xor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xor_reduce (to_sulv(l));
end function xor_reduce;
function xnor_reduce (l : UNRESOLVED_sfixed) return STD_ULOGIC is
begin
return xnor_reduce (to_sulv(l));
end function xnor_reduce;
-- End reduction operator_reduces
function \?=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
function \?=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?=\ (lslv, rslv);
end if;
end function \?=\;
function \?/=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?/=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?/=\ (lslv, rslv);
end if;
end function \?/=\;
function \?>\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>\ (lslv, rslv);
end if;
end function \?>\;
function \?>=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?>="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?>=\ (lslv, rslv);
end if;
end function \?>=\;
function \?<\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<"": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<\ (lslv, rslv);
end if;
end function \?<\;
function \?<=\ (L, R : UNRESOLVED_sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """?<="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return \?<=\ (lslv, rslv);
end if;
end function \?<=\;
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : UNRESOLVED_ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : UNRESOLVED_sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_sulv(L), to_sulv(R));
else
assert NO_WARNING
report fixed_pkg'instance_name
& "STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
-- compare functions
function "=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """>="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report fixed_pkg'instance_name
& """<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function maximum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return lresize;
else return rresize;
end if;
end function maximum;
function minimum (l, r : UNRESOLVED_ufixed) return UNRESOLVED_ufixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function minimum (l, r : UNRESOLVED_sfixed) return UNRESOLVED_sfixed is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : UNRESOLVED_sfixed (left_index downto right_index);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
if lresize > rresize then return rresize;
else return lresize;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw);
variable sresult : UNRESOLVED_ufixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : NATURAL; -- internal version of arg
begin
if (result'length < 1) then
return NAUF;
end if;
if arg /= 0 then
argx := arg;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := '0';
else
sresult(I) := '1';
end if;
argx := argx/2;
end loop;
if argx /= 0 then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_UFIXED(NATURAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
return saturate (left_index, right_index);
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw);
variable sresult : UNRESOLVED_sfixed (left_index downto 0) :=
(others => '0'); -- integer portion
variable argx : INTEGER; -- internal version of arg
variable sign : STD_ULOGIC; -- sign of input
begin
if (result'length < 1) then -- null range
return NASF;
end if;
if arg /= 0 then
if (arg < 0) then
sign := '1';
argx := -(arg + 1);
else
sign := '0';
argx := arg;
end if;
for I in 0 to sresult'left loop
if (argx mod 2) = 0 then
sresult(I) := sign;
else
sresult(I) := not sign;
end if;
argx := argx/2;
end loop;
if argx /= 0 or left_index < 0 or sign /= sresult(sresult'left) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_saturate then -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
end if;
result := resize (arg => sresult,
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
else
result := (others => '0');
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_ufixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_ufixed (left_index downto
fw-guard_bits) :=
(others => '0');
variable presult : REAL;
-- variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report fixed_pkg'instance_name
& "TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_UFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mins (right_index, right_index); -- catch literals
variable result : UNRESOLVED_sfixed (left_index downto fw) :=
(others => '0');
variable Xresult : UNRESOLVED_sfixed (left_index+1 downto fw-guard_bits) :=
(others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report fixed_pkg'instance_name
& "TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_ufixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NAUF;
end if;
result := resize (arg => UNRESOLVED_ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- converted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return UNRESOLVED_ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return UNRESOLVED_ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- left index (high index)
constant right_index : INTEGER := 0; -- right index
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
variable result : UNRESOLVED_sfixed (left_index downto right_index);
begin
if arg'length < 1 or (left_index < right_index) then
return NASF;
end if;
result := resize (arg => UNRESOLVED_sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- converted version
function to_sfixed (
arg : SIGNED) -- signed
return UNRESOLVED_sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return UNRESOLVED_sfixed(xarg);
end function to_sfixed;
function to_sfixed (arg : UNRESOLVED_ufixed) return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := UNRESOLVED_sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function to_sfixed;
-- Because of the fairly complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : UNRESOLVED_ufixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : UNRESOLVED_sfixed;
operation : CHARACTER := 'X';
size_res2 : UNRESOLVED_sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
constant sat : UNRESOLVED_ufixed (left_index downto right_index) :=
(others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable sat : UNRESOLVED_sfixed (left_index downto right_index) :=
(others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : UNRESOLVED_ufixed) -- only the size of this is used
return UNRESOLVED_ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : UNRESOLVED_sfixed) -- only the size of this is used
return UNRESOLVED_sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_UFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_ULOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report fixed_pkg'instance_name
& "TO_SFIX (STD_ULOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : UNRESOLVED_ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
constant size : NATURAL; -- length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : UNRESOLVED_sfixed; -- sfixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : UNRESOLVED_ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (ufixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : UNRESOLVED_sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : UNRESOLVED_sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : UNRESOLVED_ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := to_x01(cleanvec(arg));
if (Is_X(arg_int)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_REAL (sfixed): metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := to_ufixed (arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : UNRESOLVED_ufixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (left_index+1 downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (ufixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : UNRESOLVED_sfixed; -- fixed point input
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (left_index+1 downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_INTEGER (sfixed): metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : UNRESOLVED_ufixed; -- ufixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (s'range); -- result
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(ufixed): null detected, returning NULL"
severity warning;
return NAUF;
end if;
return to_fixed (to_01(to_uns(s), XMAP), s'high, s'low);
end function to_01;
function to_01 (
s : UNRESOLVED_sfixed; -- sfixed point input
constant XMAP : STD_ULOGIC := '0') -- Map x to
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (s'range);
begin
if (s'length < 1) then
assert NO_WARNING
report fixed_pkg'instance_name
& "TO_01(sfixed): null detected, returning NULL"
severity warning;
return NASF;
end if;
return to_fixed (to_01(to_s(s), XMAP), s'high, s'low);
end function to_01;
function Is_X (
arg : UNRESOLVED_ufixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function Is_X (
arg : UNRESOLVED_sfixed)
return BOOLEAN is
variable argslv : STD_ULOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_sulv(arg);
return Is_X (argslv);
end function Is_X;
function To_X01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01(to_sulv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_X01Z(to_sulv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return to_ufixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return to_sfixed (To_UX01(to_sulv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : UNRESOLVED_ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_ufixed (arghigh downto arglow);
variable result : UNRESOLVED_ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reduce(to_sulv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style = fixed_saturate and
or_reduce (to_sulv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : UNRESOLVED_sfixed (arghigh downto arglow);
variable result : UNRESOLVED_sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) then
reduced := or_reduce (to_sulv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reduce (to_sulv(invec(arghigh-1 downto
left_index)));
if overflow_style = fixed_saturate and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'left downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : UNRESOLVED_ufixed; -- input
size_res : UNRESOLVED_ufixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_ufixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_ufixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NAUF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : UNRESOLVED_sfixed; -- input
size_res : UNRESOLVED_sfixed; -- for size only
constant overflow_style : fixed_overflow_style_type := fixed_overflow_style;
constant round_style : fixed_round_style_type := fixed_round_style)
return UNRESOLVED_sfixed is
constant fw : INTEGER := mine (size_res'low, size_res'low); -- catch literals
variable result : UNRESOLVED_sfixed (size_res'high downto fw);
begin
if (result'length < 1 or arg'length < 1) then
return NASF;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded math functions for real
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, l'low));
end function "+";
function "+" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) + r);
end function "+";
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, l'low));
end function "-";
function "-" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) - r);
end function "-";
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, l'low));
end function "*";
function "*" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) * r);
end function "*";
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, l'low));
end function "/";
function "/" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, l'low));
end function "rem";
function "rem" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : REAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, r'low) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : REAL)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, l'low));
end function "mod";
function "mod" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, r'low) mod r);
end function "mod";
-- Overloaded math functions for integers
function "+" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l + to_ufixed (r, l'high, 0));
end function "+";
function "+" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) + r);
end function "+";
function "+" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l + to_sfixed (r, l'high, 0));
end function "+";
function "+" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) + r);
end function "+";
-- Overloaded functions
function "-" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l - to_ufixed (r, l'high, 0));
end function "-";
function "-" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) - r);
end function "-";
function "-" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l - to_sfixed (r, l'high, 0));
end function "-";
function "-" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) - r);
end function "-";
-- Overloaded functions
function "*" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l * to_ufixed (r, l'high, 0));
end function "*";
function "*" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) * r);
end function "*";
function "*" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l * to_sfixed (r, l'high, 0));
end function "*";
function "*" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) * r);
end function "*";
-- Overloaded functions
function "/" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l / to_ufixed (r, l'high, 0));
end function "/";
function "/" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) / r);
end function "/";
function "/" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l / to_sfixed (r, l'high, 0));
end function "/";
function "/" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) / r);
end function "/";
function "rem" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l rem to_ufixed (r, l'high, 0));
end function "rem";
function "rem" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) rem r);
end function "rem";
function "rem" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l rem to_sfixed (r, l'high, 0));
end function "rem";
function "rem" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) rem r);
end function "rem";
function "mod" (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return (l mod to_ufixed (r, l'high, 0));
end function "mod";
function "mod" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return (to_ufixed (l, r'high, 0) mod r);
end function "mod";
function "mod" (
l : UNRESOLVED_sfixed; -- fixed point input
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return (l mod to_sfixed (r, l'high, 0));
end function "mod";
function "mod" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return UNRESOLVED_sfixed is
begin
return (to_sfixed (l, r'high, 0) mod r);
end function "mod";
-- overloaded ufixed compare functions with integer
function "=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : NATURAL) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed; -- fixed point input
r : NATURAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- NATURAL to ufixed
function "=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : NATURAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded ufixed compare functions with real
function "=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_ufixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_ufixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_ufixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_ufixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_ufixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_ufixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_ufixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_ufixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_ufixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_ufixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_ufixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_ufixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_ufixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_ufixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return maximum (l, to_ufixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_ufixed;
r : REAL)
return UNRESOLVED_ufixed is
begin
return minimum (l, to_ufixed (r, l'high, l'low));
end function minimum;
-- real and ufixed
function "=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_ufixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_ufixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_ufixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_ufixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_ufixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_ufixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return maximum (to_ufixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_ufixed) -- fixed point input
return UNRESOLVED_ufixed is
begin
return minimum (to_ufixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with integer
function "=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : INTEGER)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : INTEGER)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : INTEGER)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- integer and sfixed
function "=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : INTEGER;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : INTEGER;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- overloaded sfixed compare functions with real
function "=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l = to_sfixed (r, l'high, l'low));
end function "=";
function "/=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l /= to_sfixed (r, l'high, l'low));
end function "/=";
function ">=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l >= to_sfixed (r, l'high, l'low));
end function ">=";
function "<=" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l <= to_sfixed (r, l'high, l'low));
end function "<=";
function ">" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l > to_sfixed (r, l'high, l'low));
end function ">";
function "<" (
l : UNRESOLVED_sfixed;
r : REAL)
return BOOLEAN is
begin
return (l < to_sfixed (r, l'high, l'low));
end function "<";
function \?=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?=\ (l, to_sfixed (r, l'high, l'low));
end function \?=\;
function \?/=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?/=\ (l, to_sfixed (r, l'high, l'low));
end function \?/=\;
function \?>=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>=\ (l, to_sfixed (r, l'high, l'low));
end function \?>=\;
function \?<=\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<=\ (l, to_sfixed (r, l'high, l'low));
end function \?<=\;
function \?>\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?>\ (l, to_sfixed (r, l'high, l'low));
end function \?>\;
function \?<\ (
l : UNRESOLVED_sfixed;
r : REAL)
return STD_ULOGIC is
begin
return \?<\ (l, to_sfixed (r, l'high, l'low));
end function \?<\;
function maximum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return maximum (l, to_sfixed (r, l'high, l'low));
end function maximum;
function minimum (
l : UNRESOLVED_sfixed;
r : REAL)
return UNRESOLVED_sfixed is
begin
return minimum (l, to_sfixed (r, l'high, l'low));
end function minimum;
-- REAL and sfixed
function "=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) = r);
end function "=";
function "/=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) /= r);
end function "/=";
function ">=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) >= r);
end function ">=";
function "<=" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) <= r);
end function "<=";
function ">" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) > r);
end function ">";
function "<" (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (l, r'high, r'low) < r);
end function "<";
function \?=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?=\ (to_sfixed (l, r'high, r'low), r);
end function \?=\;
function \?/=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?/=\ (to_sfixed (l, r'high, r'low), r);
end function \?/=\;
function \?>=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>=\ (to_sfixed (l, r'high, r'low), r);
end function \?>=\;
function \?<=\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<=\ (to_sfixed (l, r'high, r'low), r);
end function \?<=\;
function \?>\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?>\ (to_sfixed (l, r'high, r'low), r);
end function \?>\;
function \?<\ (
l : REAL;
r : UNRESOLVED_sfixed) -- fixed point input
return STD_ULOGIC is
begin
return \?<\ (to_sfixed (l, r'high, r'low), r);
end function \?<\;
function maximum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return maximum (to_sfixed (l, r'high, r'low), r);
end function maximum;
function minimum (
l : REAL;
r : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return minimum (to_sfixed (l, r'high, r'low), r);
end function minimum;
-- rtl_synthesis off
-- pragma synthesis_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- %%% Replicated Textio functions
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report fixed_pkg'instance_name
& "HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-- %%% END replicated textio functions
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : ufixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(ufixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(ufixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(ufixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(ufixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(ufixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : ufixed (VALUE'range);
variable i : INTEGER; -- index variable
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := value'high;
GOOD := false;
while i >= VALUE'low loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = value'high then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
return;
elsif i /= -1 then -- Seperator in the wrong spot
return;
end if;
founddot := true;
lastu := false;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character/short read
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then -- reading done
GOOD := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
variable mv : sfixed (VALUE'range);
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a "."
begin -- READ
VALUE := (VALUE'range => 'U');
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := value'high;
while i >= VALUE'low loop
if readOk = false then -- Bail out if there was a bad read
report fixed_pkg'instance_name & "READ(sfixed) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = value'high then
report fixed_pkg'instance_name & "READ(sfixed) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = '.' then -- binary point
if founddot then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Two binary points found in input string" severity error;
return;
elsif i /= -1 then -- Seperator in the wrong spot
report fixed_pkg'instance_name & "READ(sfixed) "
& "Decimal point does not match number format "
severity error;
return;
end if;
founddot := true;
lastu := false;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report fixed_pkg'instance_name & "READ(sfixed) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report fixed_pkg'instance_name & "READ(sfixed) "
& "Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i - 1;
if i < mv'low then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
variable value_ufixed : UNRESOLVED_ufixed (VALUE'range);
begin -- READ
READ (L => L, VALUE => value_ufixed, GOOD => GOOD);
VALUE := UNRESOLVED_sfixed (value_ufixed);
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
-- purpose: Routines common to the OREAD routines
procedure OREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "OREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "OREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (2 downto 0); -- 3 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2triBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-2) := nybble;
i := i - 3;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
igood := true; -- read into a null array
idex := -1;
end if;
end procedure OREAD_common;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD (L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => false);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "OREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-2)/3)*3;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
OREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in UNRESOLVED_sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: Routines common to the OREAD routines
procedure HREAD_common (
L : inout LINE;
slv : out STD_ULOGIC_VECTOR;
igood : out BOOLEAN;
idex : out INTEGER;
constant bpoint : in INTEGER; -- binary point
constant message : in BOOLEAN;
constant smath : in BOOLEAN) is
-- purpose: error message routine
procedure errmes (
constant mess : in STRING) is -- error message
begin
if message then
if smath then
report fixed_pkg'instance_name
& "HREAD(sfixed) "
& mess
severity error;
else
report fixed_pkg'instance_name
& "HREAD(ufixed) "
& mess
severity error;
end if;
end if;
end procedure errmes;
variable xgood : BOOLEAN;
variable nybble : STD_ULOGIC_VECTOR (3 downto 0); -- 4 bits
variable c : CHARACTER;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
variable founddot : BOOLEAN := false; -- found a dot.
begin
Skip_whitespace (L);
if slv'length > 0 then
i := slv'high;
read (l, c, xgood);
while i > 0 loop
if xgood = false then
errmes ("Error: end of string encountered");
exit;
elsif c = '_' then
if i = slv'length then
errmes ("Error: String begins with an ""_""");
xgood := false;
exit;
elsif lastu then
errmes ("Error: Two underscores detected in input string ""__""");
xgood := false;
exit;
else
lastu := true;
end if;
elsif (c = '.') then
if (i + 1 /= bpoint) then
errmes ("encountered ""."" at wrong index");
xgood := false;
exit;
elsif i = slv'length then
errmes ("encounted a ""."" at the beginning of the line");
xgood := false;
exit;
elsif founddot then
errmes ("Two ""."" encounted in input string");
xgood := false;
exit;
end if;
founddot := true;
lastu := false;
else
Char2QuadBits(c, nybble, xgood, message);
if not xgood then
exit;
end if;
slv (i downto i-3) := nybble;
i := i - 4;
lastu := false;
end if;
if i > 0 then
read (L, c, xgood);
end if;
end loop;
idex := i;
igood := xgood;
else
idex := -1;
igood := true; -- read null string
end if;
end procedure HREAD_common;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if igood then
if not ((i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(ufixed): Vector truncated"
severity warning;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => false);
if (igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')) then
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => true,
smath => true);
if igood then -- We did not get another error
if not ((i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated."
severity error;
else
if (or_reduce (slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report fixed_pkg'instance_name
& "HREAD(sfixed): Vector truncated"
severity warning;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end if;
end if;
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out UNRESOLVED_sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(0, VALUE'low)-3)/4)*4;
variable slv : STD_ULOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable valuex : UNRESOLVED_sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable i : INTEGER;
begin
VALUE := (VALUE'range => 'U');
HREAD_common ( L => L,
slv => slv,
igood => igood,
idex => i,
bpoint => -lbv,
message => false,
smath => true);
if (igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reduce (slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))) then
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
good := true;
else
good := false;
end if;
end procedure HREAD;
function to_string (value : UNRESOLVED_ufixed) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable subval : UNRESOLVED_ufixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_string (resize (sfixed(value), 0, value'low));
else
return to_string (resize (value, 0, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_string (value : UNRESOLVED_sfixed) return STRING is
variable s : STRING(1 to value'length + 1) := (others => ' ');
variable subval : UNRESOLVED_sfixed (value'high downto -1);
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_string(subval);
else
return to_string (resize (value, value'high, -1));
end if;
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx + 1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx + 1;
end loop;
return s;
end if;
end if;
end function to_string;
function to_ostring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_ufixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_ostring (resize (sfixed(value), 2, value'low));
else
return to_ostring (resize (value, 2, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value (value'low));
else
lpad := (others => '0');
end if;
return to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_ufixed) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_ufixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
if value(value'high) = 'Z' then
return to_hstring (resize (sfixed(value), 3, value'low));
else
return to_hstring (resize (value, 3, value'low));
end if;
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad);
end if;
end if;
end function to_hstring;
function to_ostring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
variable subval : UNRESOLVED_sfixed (value'high downto -3);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_ostring(subval);
else
return to_ostring (resize (value, value'high, -3));
end if;
else
pad := (others => value(value'high));
slv := to_sulv (value);
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_ostring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_ostring;
function to_hstring (value : UNRESOLVED_sfixed) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
variable subval : UNRESOLVED_sfixed (value'high downto -4);
variable lpad : STD_ULOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1);
variable slv : STD_ULOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low));
elsif value'low >= 0 then
if Is_X (value(value'low)) then
subval := (others => value(value'low));
subval (value'range) := value;
return to_hstring(subval);
else
return to_hstring (resize (value, value'high, -4));
end if;
else
slv := to_sulv (value);
pad := (others => value(value'high));
if Is_X (value (value'low)) then
lpad := (others => value(value'low));
else
lpad := (others => '0');
end if;
return to_hstring(pad & slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0) & lpad);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
variable result : UNRESOLVED_ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
variable result : UNRESOLVED_sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report fixed_pkg'instance_name
& "from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_ufixed)
return UNRESOLVED_ufixed is
begin
return from_hstring(hstring, size_res'high, size_res'low);
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_string (bstring, size_res'high, size_res'low);
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_ostring (ostring, size_res'high, size_res'low);
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : UNRESOLVED_sfixed)
return UNRESOLVED_sfixed is
begin
return from_hstring (hstring, size_res'high, size_res'low);
end function from_hstring;
-- purpose: Calculate the string boundaries
procedure calculate_string_boundry (
arg : in STRING; -- input string
left_index : out INTEGER; -- left
right_index : out INTEGER) is -- right
-- examples "10001.111" would return +4, -3
-- "07X.44" would return +2, -2 (then the octal routine would multiply)
-- "A_B_._C" would return +1, -1 (then the hex routine would multiply)
alias xarg : STRING (arg'length downto 1) is arg; -- make it downto range
variable l, r : INTEGER; -- internal indexes
variable founddot : BOOLEAN := false;
begin
if arg'length > 0 then
l := xarg'high - 1;
r := 0;
for i in xarg'range loop
if xarg(i) = '_' then
if r = 0 then
l := l - 1;
else
r := r + 1;
end if;
elsif xarg(i) = ' ' or xarg(i) = NBSP or xarg(i) = HT then
report fixed_pkg'instance_name
& "Found a space in the input STRING " & xarg
severity error;
elsif xarg(i) = '.' then
if founddot then
report fixed_pkg'instance_name
& "Found two binary points in input string " & xarg
severity error;
else
l := l - i;
r := -i + 1;
founddot := true;
end if;
end if;
end loop;
left_index := l;
right_index := r;
else
left_index := 0;
right_index := 0;
end if;
end procedure calculate_string_boundry;
-- Direct conversion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
-- Direct octal and hex conversion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_ufixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (bstring, left_index, right_index);
return from_string (bstring, left_index, right_index);
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (ostring, left_index, right_index);
return from_ostring (ostring, ((left_index+1)*3)-1, right_index*3);
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return UNRESOLVED_sfixed is
variable left_index, right_index : INTEGER;
begin
calculate_string_boundry (hstring, left_index, right_index);
return from_hstring (hstring, ((left_index+1)*4)-1, right_index*4);
end function from_hstring;
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
end package body fixed_pkg;
| mit | 1a66fa50ea3ef66a3a23ee1c79906c4b | 0.568138 | 3.973457 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_pntr.vhd | 1 | 21,571 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
ch2_eof_detected : in std_logic ; --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
tail_updt : in std_logic;
tail_updt_latch : out std_logic;
ch2_updt_done : in std_logic;
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal first : std_logic;
signal eof_latch : std_logic;
signal ch2_sg_idle_int : std_logic;
attribute mark_debug of ch1_fetch_address_i : signal is "true";
attribute mark_debug of ch2_fetch_address_i : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch1_fetch_address <= ch1_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif((ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0'))then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch2_fetch_address <= ch2_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1' or ch2_eof_detected = '1')then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
ch2_sg_idle_int <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
-- Needed for multi channel
EOF_LATCH_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_taildesc_wren = '1' or eof_latch = '1')then -- nned to have some reset condition here
eof_latch <= '0';
elsif (ch2_sg_idle_int = '1' and ch2_updt_done = '1') then
eof_latch <= '1';
end if;
end if;
end process EOF_LATCH_PROC;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or eof_latch = '1')then -- nned to have some reset condition here
tail_updt_latch <= '0';
first <= '0';
elsif (tail_updt = '1') then
tail_updt_latch <= '0';
elsif(ch2_taildesc_wren = '1' and first = '0')then
first <= '1';
elsif(ch2_taildesc_wren = '1' and first = '1')then
tail_updt_latch <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
tail_updt_latch <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
| bsd-2-clause | 18cf332a0550fd4451924ad8a0a37776 | 0.420426 | 4.858333 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_200_test_input.vhd | 1 | 356 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
package my_pkg is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end package my_pkg;
-- Violation below
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
| gpl-3.0 | fdd61fd3d1380fe15698fdf0416582e0 | 0.581461 | 3.358491 | false | false | false | false |
zcold/fft.vhdl | src/cbf.vhdl | 1 | 4,722 | -- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------
-- clocked butterfly operation
----------------------
-- Description
-- This design unit `cbf` is for performing clocked butterfly operation on complex
-- fixed point numbers with configurable data width. The value of the inputs are
-- limited to (+1, -1]. MSB is sign bit and the rest bits are all decimal part.
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
entity cbf is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- clock
clk : in std_logic;
nrst : in std_logic;
-- x0, input 0
x0_re : in sfixed (0 downto 1 - data_width);
x0_im : in sfixed (0 downto 1 - data_width);
-- x1, input 1
x1_re : in sfixed (0 downto 1 - data_width);
x1_im : in sfixed (0 downto 1 - data_width);
-- wk, twiddle factor
wk_re : in sfixed (0 downto 1 - data_width);
wk_im : in sfixed (0 downto 1 - data_width);
-- y0, output 0
y0_re : out sfixed(0 downto 1 - data_width);
y0_im : out sfixed(0 downto 1 - data_width);
-- y1, output 1
y1_re : out sfixed(0 downto 1 - data_width);
y1_im : out sfixed(0 downto 1 - data_width)
);
end cbf;
-- Function Implementation 0
architecture FIMP_0 of cbf is
-- internal signals for x
signal x0_re_int : sfixed (0 downto 1 - data_width);
signal x0_im_int : sfixed (0 downto 1 - data_width);
signal x1_re_int : sfixed (0 downto 1 - data_width);
signal x1_im_int : sfixed (0 downto 1 - data_width);
-- internal signals for twiddle factor
signal wk_re_int : sfixed (0 downto 1 - data_width);
signal wk_im_int : sfixed (0 downto 1 - data_width);
-- combinatorial butterfly operation
component bf is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- x0, input 0
x0_re : in sfixed (0 downto 1 - data_width);
x0_im : in sfixed (0 downto 1 - data_width);
-- x1, input 1
x1_re : in sfixed (0 downto 1 - data_width);
x1_im : in sfixed (0 downto 1 - data_width);
-- wk, twiddle factor
wk_re : in sfixed (0 downto 1 - data_width);
wk_im : in sfixed (0 downto 1 - data_width);
-- y0, output 0
y0_re : out sfixed(0 downto 1 - data_width);
y0_im : out sfixed(0 downto 1 - data_width);
-- y1, output 1
y1_re : out sfixed(0 downto 1 - data_width);
y1_im : out sfixed(0 downto 1 - data_width)
);
end component;
begin
-- registered inputs
process(clk, nrst)
begin
if (nrst = '0') then
x0_re_int <= (others => '0');
x0_im_int <= (others => '0');
x1_re_int <= (others => '0');
x1_im_int <= (others => '0');
wk_re_int <= (others => '0');
wk_im_int <= (others => '0');
elsif (clk'event and clk = '1') then
x0_re_int <= x0_re;
x0_im_int <= x0_im;
x1_re_int <= x1_re;
x1_im_int <= x1_im;
wk_re_int <= wk_re;
wk_im_int <= wk_im;
end if;
end process;
-- connect the combinatorial butterfly operation
bf_0: bf
generic map (data_width)
port map (x0_re_int, x0_im_int, x1_re_int, x1_im_int,
wk_re_int, wk_im_int,
y0_re, y0_im, y1_re, y1_im);
end FIMP_0;
| mit | 597b207d90be543ab8baadcbbc1dd84e | 0.59784 | 3.547708 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_005_test_input.vhd | 1 | 610 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
when others =>
z <= a;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
when STATE_1 =>
a <= b;
b <= c;
c <= d;
when others=>
z <= a;
when others =>
z <= a;
end case;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | 726902d183662a81b11fb7403b8b5a36 | 0.409836 | 3.505747 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_strb_gen2.vhd | 1 | 102,358 | -------------------------------------------------------------------------------
-- axi_datamover_strb_gen2.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_strb_gen2.vhd
--
-- Description:
-- Second generation AXI Strobe Generator module. This design leverages
-- look up table approach vs real-time calculation. This design method is
-- used to reduce logic levels and improve final Fmax timing.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_strb_gen2.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for lines 2404 through 2964
-- by removing commented-out code.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_strb_gen2 is
generic (
C_OP_MODE : Integer range 0 to 1 := 0;
-- 0 = offset/length mode
-- 1 = offset/offset mode,
C_STRB_WIDTH : Integer := 8;
-- number of addr bits needed
C_OFFSET_WIDTH : Integer := 3;
-- log2(C_STRB_WIDTH)
C_NUM_BYTES_WIDTH : Integer := 4
-- log2(C_STRB_WIDTH)+1 in offset/length mode (C_OP_MODE = 0)
-- log2(C_STRB_WIDTH) in offset/offset mode (C_OP_MODE = 1)
);
port (
-- Starting offset input -----------------------------------------------------
--
start_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the starting address offset of the strobe value --
------------------------------------------------------------------------------
-- used in both offset/offset and offset/length modes
-- Endig Offset Input --------------------------------------------------------
--
end_addr_offset : In std_logic_vector(C_OFFSET_WIDTH-1 downto 0); --
-- Specifies the ending address offset of the strobe value --
-- used in only offset/offset mode (C_OP_MODE = 1) --
------------------------------------------------------------------------------
-- Number of valid Bytes input (from starting offset) ------------------------
--
num_valid_bytes : In std_logic_vector(C_NUM_BYTES_WIDTH-1 downto 0); --
-- Specifies the number of valid bytes from starting offset --
-- used in only offset/length mode (C_OP_MODE = 0) --
------------------------------------------------------------------------------
-- Generated Strobe output ---------------------------------------------------
--
strb_out : out std_logic_vector(C_STRB_WIDTH-1 downto 0) --
------------------------------------------------------------------------------
);
end entity axi_datamover_strb_gen2;
architecture implementation of axi_datamover_strb_gen2 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_2
--
-- Function Description:
-- returns the 2-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_2 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11";
when others =>
var_start_vector := "10";
end case;
Return (var_start_vector);
end function get_start_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_2
--
-- Function Description:
-- Returns the 2-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_2 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(1 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "01";
when others =>
var_end_vector := "11";
end case;
Return (var_end_vector);
end function get_end_2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_4
--
-- Function Description:
-- returns the 4-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_4 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111";
when 1 =>
var_start_vector := "1110";
when 2 =>
var_start_vector := "1100";
when others =>
var_start_vector := "1000";
end case;
Return (var_start_vector);
end function get_start_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_4
--
-- Function Description:
-- Returns the 4-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_4 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(3 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0001";
when 1 =>
var_end_vector := "0011";
when 2 =>
var_end_vector := "0111";
when others =>
var_end_vector := "1111";
end case;
Return (var_end_vector);
end function get_end_4;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_8
--
-- Function Description:
-- returns the 8-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_8 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111";
when 1 =>
var_start_vector := "11111110";
when 2 =>
var_start_vector := "11111100";
when 3 =>
var_start_vector := "11111000";
when 4 =>
var_start_vector := "11110000";
when 5 =>
var_start_vector := "11100000";
when 6 =>
var_start_vector := "11000000";
when others =>
var_start_vector := "10000000";
end case;
Return (var_start_vector);
end function get_start_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_8
--
-- Function Description:
-- Returns the 8-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_8 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(7 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000001";
when 1 =>
var_end_vector := "00000011";
when 2 =>
var_end_vector := "00000111";
when 3 =>
var_end_vector := "00001111";
when 4 =>
var_end_vector := "00011111";
when 5 =>
var_end_vector := "00111111";
when 6 =>
var_end_vector := "01111111";
when others =>
var_end_vector := "11111111";
end case;
Return (var_end_vector);
end function get_end_8;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_16
--
-- Function Description:
-- returns the 16-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_16 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111";
when 1 =>
var_start_vector := "1111111111111110";
when 2 =>
var_start_vector := "1111111111111100";
when 3 =>
var_start_vector := "1111111111111000";
when 4 =>
var_start_vector := "1111111111110000";
when 5 =>
var_start_vector := "1111111111100000";
when 6 =>
var_start_vector := "1111111111000000";
when 7 =>
var_start_vector := "1111111110000000";
when 8 =>
var_start_vector := "1111111100000000";
when 9 =>
var_start_vector := "1111111000000000";
when 10 =>
var_start_vector := "1111110000000000";
when 11 =>
var_start_vector := "1111100000000000";
when 12 =>
var_start_vector := "1111000000000000";
when 13 =>
var_start_vector := "1110000000000000";
when 14 =>
var_start_vector := "1100000000000000";
when others =>
var_start_vector := "1000000000000000";
end case;
Return (var_start_vector);
end function get_start_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_16
--
-- Function Description:
-- Returns the 16-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_16 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(15 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000001";
when 1 =>
var_end_vector := "0000000000000011";
when 2 =>
var_end_vector := "0000000000000111";
when 3 =>
var_end_vector := "0000000000001111";
when 4 =>
var_end_vector := "0000000000011111";
when 5 =>
var_end_vector := "0000000000111111";
when 6 =>
var_end_vector := "0000000001111111";
when 7 =>
var_end_vector := "0000000011111111";
when 8 =>
var_end_vector := "0000000111111111";
when 9 =>
var_end_vector := "0000001111111111";
when 10 =>
var_end_vector := "0000011111111111";
when 11 =>
var_end_vector := "0000111111111111";
when 12 =>
var_end_vector := "0001111111111111";
when 13 =>
var_end_vector := "0011111111111111";
when 14 =>
var_end_vector := "0111111111111111";
when others =>
var_end_vector := "1111111111111111";
end case;
Return (var_end_vector);
end function get_end_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_32
--
-- Function Description:
-- returns the 32-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_32 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "11111111111111111111111111111111";
when 1 =>
var_start_vector := "11111111111111111111111111111110";
when 2 =>
var_start_vector := "11111111111111111111111111111100";
when 3 =>
var_start_vector := "11111111111111111111111111111000";
when 4 =>
var_start_vector := "11111111111111111111111111110000";
when 5 =>
var_start_vector := "11111111111111111111111111100000";
when 6 =>
var_start_vector := "11111111111111111111111111000000";
when 7 =>
var_start_vector := "11111111111111111111111110000000";
when 8 =>
var_start_vector := "11111111111111111111111100000000";
when 9 =>
var_start_vector := "11111111111111111111111000000000";
when 10 =>
var_start_vector := "11111111111111111111110000000000";
when 11 =>
var_start_vector := "11111111111111111111100000000000";
when 12 =>
var_start_vector := "11111111111111111111000000000000";
when 13 =>
var_start_vector := "11111111111111111110000000000000";
when 14 =>
var_start_vector := "11111111111111111100000000000000";
when 15 =>
var_start_vector := "11111111111111111000000000000000";
when 16 =>
var_start_vector := "11111111111111110000000000000000";
when 17 =>
var_start_vector := "11111111111111100000000000000000";
when 18 =>
var_start_vector := "11111111111111000000000000000000";
when 19 =>
var_start_vector := "11111111111110000000000000000000";
when 20 =>
var_start_vector := "11111111111100000000000000000000";
when 21 =>
var_start_vector := "11111111111000000000000000000000";
when 22 =>
var_start_vector := "11111111110000000000000000000000";
when 23 =>
var_start_vector := "11111111100000000000000000000000";
when 24 =>
var_start_vector := "11111111000000000000000000000000";
when 25 =>
var_start_vector := "11111110000000000000000000000000";
when 26 =>
var_start_vector := "11111100000000000000000000000000";
when 27 =>
var_start_vector := "11111000000000000000000000000000";
when 28 =>
var_start_vector := "11110000000000000000000000000000";
when 29 =>
var_start_vector := "11100000000000000000000000000000";
when 30 =>
var_start_vector := "11000000000000000000000000000000";
when others =>
var_start_vector := "10000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_32
--
-- Function Description:
-- Returns the 32-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_32 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(31 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "00000000000000000000000000000001";
when 1 =>
var_end_vector := "00000000000000000000000000000011";
when 2 =>
var_end_vector := "00000000000000000000000000000111";
when 3 =>
var_end_vector := "00000000000000000000000000001111";
when 4 =>
var_end_vector := "00000000000000000000000000011111";
when 5 =>
var_end_vector := "00000000000000000000000000111111";
when 6 =>
var_end_vector := "00000000000000000000000001111111";
when 7 =>
var_end_vector := "00000000000000000000000011111111";
when 8 =>
var_end_vector := "00000000000000000000000111111111";
when 9 =>
var_end_vector := "00000000000000000000001111111111";
when 10 =>
var_end_vector := "00000000000000000000011111111111";
when 11 =>
var_end_vector := "00000000000000000000111111111111";
when 12 =>
var_end_vector := "00000000000000000001111111111111";
when 13 =>
var_end_vector := "00000000000000000011111111111111";
when 14 =>
var_end_vector := "00000000000000000111111111111111";
when 15 =>
var_end_vector := "00000000000000001111111111111111";
when 16 =>
var_end_vector := "00000000000000011111111111111111";
when 17 =>
var_end_vector := "00000000000000111111111111111111";
when 18 =>
var_end_vector := "00000000000001111111111111111111";
when 19 =>
var_end_vector := "00000000000011111111111111111111";
when 20 =>
var_end_vector := "00000000000111111111111111111111";
when 21 =>
var_end_vector := "00000000001111111111111111111111";
when 22 =>
var_end_vector := "00000000011111111111111111111111";
when 23 =>
var_end_vector := "00000000111111111111111111111111";
when 24 =>
var_end_vector := "00000001111111111111111111111111";
when 25 =>
var_end_vector := "00000011111111111111111111111111";
when 26 =>
var_end_vector := "00000111111111111111111111111111";
when 27 =>
var_end_vector := "00001111111111111111111111111111";
when 28 =>
var_end_vector := "00011111111111111111111111111111";
when 29 =>
var_end_vector := "00111111111111111111111111111111";
when 30 =>
var_end_vector := "01111111111111111111111111111111";
when others =>
var_end_vector := "11111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_32;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_64
--
-- Function Description:
-- returns the 64-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_64 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111111";
when 1 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111110";
when 2 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111100";
when 3 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111111000";
when 4 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111110000";
when 5 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111100000";
when 6 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111111000000";
when 7 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111110000000";
when 8 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111100000000";
when 9 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111111000000000";
when 10 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111110000000000";
when 11 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111100000000000";
when 12 =>
var_start_vector := "1111111111111111111111111111111111111111111111111111000000000000";
when 13 =>
var_start_vector := "1111111111111111111111111111111111111111111111111110000000000000";
when 14 =>
var_start_vector := "1111111111111111111111111111111111111111111111111100000000000000";
when 15 =>
var_start_vector := "1111111111111111111111111111111111111111111111111000000000000000";
when 16 =>
var_start_vector := "1111111111111111111111111111111111111111111111110000000000000000";
when 17 =>
var_start_vector := "1111111111111111111111111111111111111111111111100000000000000000";
when 18 =>
var_start_vector := "1111111111111111111111111111111111111111111111000000000000000000";
when 19 =>
var_start_vector := "1111111111111111111111111111111111111111111110000000000000000000";
when 20 =>
var_start_vector := "1111111111111111111111111111111111111111111100000000000000000000";
when 21 =>
var_start_vector := "1111111111111111111111111111111111111111111000000000000000000000";
when 22 =>
var_start_vector := "1111111111111111111111111111111111111111110000000000000000000000";
when 23 =>
var_start_vector := "1111111111111111111111111111111111111111100000000000000000000000";
when 24 =>
var_start_vector := "1111111111111111111111111111111111111111000000000000000000000000";
when 25 =>
var_start_vector := "1111111111111111111111111111111111111110000000000000000000000000";
when 26 =>
var_start_vector := "1111111111111111111111111111111111111100000000000000000000000000";
when 27 =>
var_start_vector := "1111111111111111111111111111111111111000000000000000000000000000";
when 28 =>
var_start_vector := "1111111111111111111111111111111111110000000000000000000000000000";
when 29 =>
var_start_vector := "1111111111111111111111111111111111100000000000000000000000000000";
when 30 =>
var_start_vector := "1111111111111111111111111111111111000000000000000000000000000000";
when 31 =>
var_start_vector := "1111111111111111111111111111111110000000000000000000000000000000";
when 32 =>
var_start_vector := "1111111111111111111111111111111100000000000000000000000000000000";
when 33 =>
var_start_vector := "1111111111111111111111111111111000000000000000000000000000000000";
when 34 =>
var_start_vector := "1111111111111111111111111111110000000000000000000000000000000000";
when 35 =>
var_start_vector := "1111111111111111111111111111100000000000000000000000000000000000";
when 36 =>
var_start_vector := "1111111111111111111111111111000000000000000000000000000000000000";
when 37 =>
var_start_vector := "1111111111111111111111111110000000000000000000000000000000000000";
when 38 =>
var_start_vector := "1111111111111111111111111100000000000000000000000000000000000000";
when 39 =>
var_start_vector := "1111111111111111111111111000000000000000000000000000000000000000";
when 40 =>
var_start_vector := "1111111111111111111111110000000000000000000000000000000000000000";
when 41 =>
var_start_vector := "1111111111111111111111100000000000000000000000000000000000000000";
when 42 =>
var_start_vector := "1111111111111111111111000000000000000000000000000000000000000000";
when 43 =>
var_start_vector := "1111111111111111111110000000000000000000000000000000000000000000";
when 44 =>
var_start_vector := "1111111111111111111100000000000000000000000000000000000000000000";
when 45 =>
var_start_vector := "1111111111111111111000000000000000000000000000000000000000000000";
when 46 =>
var_start_vector := "1111111111111111110000000000000000000000000000000000000000000000";
when 47 =>
var_start_vector := "1111111111111111100000000000000000000000000000000000000000000000";
when 48 =>
var_start_vector := "1111111111111111000000000000000000000000000000000000000000000000";
when 49 =>
var_start_vector := "1111111111111110000000000000000000000000000000000000000000000000";
when 50 =>
var_start_vector := "1111111111111100000000000000000000000000000000000000000000000000";
when 51 =>
var_start_vector := "1111111111111000000000000000000000000000000000000000000000000000";
when 52 =>
var_start_vector := "1111111111110000000000000000000000000000000000000000000000000000";
when 53 =>
var_start_vector := "1111111111100000000000000000000000000000000000000000000000000000";
when 54 =>
var_start_vector := "1111111111000000000000000000000000000000000000000000000000000000";
when 55 =>
var_start_vector := "1111111110000000000000000000000000000000000000000000000000000000";
when 56 =>
var_start_vector := "1111111100000000000000000000000000000000000000000000000000000000";
when 57 =>
var_start_vector := "1111111000000000000000000000000000000000000000000000000000000000";
when 58 =>
var_start_vector := "1111110000000000000000000000000000000000000000000000000000000000";
when 59 =>
var_start_vector := "1111100000000000000000000000000000000000000000000000000000000000";
when 60 =>
var_start_vector := "1111000000000000000000000000000000000000000000000000000000000000";
when 61 =>
var_start_vector := "1110000000000000000000000000000000000000000000000000000000000000";
when 62 =>
var_start_vector := "1100000000000000000000000000000000000000000000000000000000000000";
when others =>
var_start_vector := "1000000000000000000000000000000000000000000000000000000000000000";
end case;
Return (var_start_vector);
end function get_start_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_64
--
-- Function Description:
-- Returns the 64-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_64 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(63 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000001";
when 1 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000011";
when 2 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000000111";
when 3 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000001111";
when 4 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000011111";
when 5 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000000111111";
when 6 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000001111111";
when 7 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000011111111";
when 8 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000000111111111";
when 9 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000001111111111";
when 10 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000011111111111";
when 11 =>
var_end_vector := "0000000000000000000000000000000000000000000000000000111111111111";
when 12 =>
var_end_vector := "0000000000000000000000000000000000000000000000000001111111111111";
when 13 =>
var_end_vector := "0000000000000000000000000000000000000000000000000011111111111111";
when 14 =>
var_end_vector := "0000000000000000000000000000000000000000000000000111111111111111";
when 15 =>
var_end_vector := "0000000000000000000000000000000000000000000000001111111111111111";
when 16 =>
var_end_vector := "0000000000000000000000000000000000000000000000011111111111111111";
when 17 =>
var_end_vector := "0000000000000000000000000000000000000000000000111111111111111111";
when 18 =>
var_end_vector := "0000000000000000000000000000000000000000000001111111111111111111";
when 19 =>
var_end_vector := "0000000000000000000000000000000000000000000011111111111111111111";
when 20 =>
var_end_vector := "0000000000000000000000000000000000000000000111111111111111111111";
when 21 =>
var_end_vector := "0000000000000000000000000000000000000000001111111111111111111111";
when 22 =>
var_end_vector := "0000000000000000000000000000000000000000011111111111111111111111";
when 23 =>
var_end_vector := "0000000000000000000000000000000000000000111111111111111111111111";
when 24 =>
var_end_vector := "0000000000000000000000000000000000000001111111111111111111111111";
when 25 =>
var_end_vector := "0000000000000000000000000000000000000011111111111111111111111111";
when 26 =>
var_end_vector := "0000000000000000000000000000000000000111111111111111111111111111";
when 27 =>
var_end_vector := "0000000000000000000000000000000000001111111111111111111111111111";
when 28 =>
var_end_vector := "0000000000000000000000000000000000011111111111111111111111111111";
when 29 =>
var_end_vector := "0000000000000000000000000000000000111111111111111111111111111111";
when 30 =>
var_end_vector := "0000000000000000000000000000000001111111111111111111111111111111";
when 31 =>
var_end_vector := "0000000000000000000000000000000011111111111111111111111111111111";
when 32 =>
var_end_vector := "0000000000000000000000000000000111111111111111111111111111111111";
when 33 =>
var_end_vector := "0000000000000000000000000000001111111111111111111111111111111111";
when 34 =>
var_end_vector := "0000000000000000000000000000011111111111111111111111111111111111";
when 35 =>
var_end_vector := "0000000000000000000000000000111111111111111111111111111111111111";
when 36 =>
var_end_vector := "0000000000000000000000000001111111111111111111111111111111111111";
when 37 =>
var_end_vector := "0000000000000000000000000011111111111111111111111111111111111111";
when 38 =>
var_end_vector := "0000000000000000000000000111111111111111111111111111111111111111";
when 39 =>
var_end_vector := "0000000000000000000000001111111111111111111111111111111111111111";
when 40 =>
var_end_vector := "0000000000000000000000011111111111111111111111111111111111111111";
when 41 =>
var_end_vector := "0000000000000000000000111111111111111111111111111111111111111111";
when 42 =>
var_end_vector := "0000000000000000000001111111111111111111111111111111111111111111";
when 43 =>
var_end_vector := "0000000000000000000011111111111111111111111111111111111111111111";
when 44 =>
var_end_vector := "0000000000000000000111111111111111111111111111111111111111111111";
when 45 =>
var_end_vector := "0000000000000000001111111111111111111111111111111111111111111111";
when 46 =>
var_end_vector := "0000000000000000011111111111111111111111111111111111111111111111";
when 47 =>
var_end_vector := "0000000000000000111111111111111111111111111111111111111111111111";
when 48 =>
var_end_vector := "0000000000000001111111111111111111111111111111111111111111111111";
when 49 =>
var_end_vector := "0000000000000011111111111111111111111111111111111111111111111111";
when 50 =>
var_end_vector := "0000000000000111111111111111111111111111111111111111111111111111";
when 51 =>
var_end_vector := "0000000000001111111111111111111111111111111111111111111111111111";
when 52 =>
var_end_vector := "0000000000011111111111111111111111111111111111111111111111111111";
when 53 =>
var_end_vector := "0000000000111111111111111111111111111111111111111111111111111111";
when 54 =>
var_end_vector := "0000000001111111111111111111111111111111111111111111111111111111";
when 55 =>
var_end_vector := "0000000011111111111111111111111111111111111111111111111111111111";
when 56 =>
var_end_vector := "0000000111111111111111111111111111111111111111111111111111111111";
when 57 =>
var_end_vector := "0000001111111111111111111111111111111111111111111111111111111111";
when 58 =>
var_end_vector := "0000011111111111111111111111111111111111111111111111111111111111";
when 59 =>
var_end_vector := "0000111111111111111111111111111111111111111111111111111111111111";
when 60 =>
var_end_vector := "0001111111111111111111111111111111111111111111111111111111111111";
when 61 =>
var_end_vector := "0011111111111111111111111111111111111111111111111111111111111111";
when 62 =>
var_end_vector := "0111111111111111111111111111111111111111111111111111111111111111";
when others =>
var_end_vector := "1111111111111111111111111111111111111111111111111111111111111111";
end case;
Return (var_end_vector);
end function get_end_64;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_128
--
-- Function Description:
-- returns the 128-bit vector filled with '1's from the start
-- offset to the end of of the vector
--
-------------------------------------------------------------------
function get_start_128 (start_offset : natural) return std_logic_vector is
Variable var_start_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case start_offset is
when 0 =>
var_start_vector(127 downto 0) := (others => '1');
when 1 =>
var_start_vector(127 downto 1) := (others => '1');
var_start_vector( 0 downto 0) := (others => '0');
when 2 =>
var_start_vector(127 downto 2) := (others => '1');
var_start_vector( 1 downto 0) := (others => '0');
when 3 =>
var_start_vector(127 downto 3) := (others => '1');
var_start_vector( 2 downto 0) := (others => '0');
when 4 =>
var_start_vector(127 downto 4) := (others => '1');
var_start_vector( 3 downto 0) := (others => '0');
when 5 =>
var_start_vector(127 downto 5) := (others => '1');
var_start_vector( 4 downto 0) := (others => '0');
when 6 =>
var_start_vector(127 downto 6) := (others => '1');
var_start_vector( 5 downto 0) := (others => '0');
when 7 =>
var_start_vector(127 downto 7) := (others => '1');
var_start_vector( 6 downto 0) := (others => '0');
when 8 =>
var_start_vector(127 downto 8) := (others => '1');
var_start_vector( 7 downto 0) := (others => '0');
when 9 =>
var_start_vector(127 downto 9) := (others => '1');
var_start_vector( 8 downto 0) := (others => '0');
when 10 =>
var_start_vector(127 downto 10) := (others => '1');
var_start_vector( 9 downto 0) := (others => '0');
when 11 =>
var_start_vector(127 downto 11) := (others => '1');
var_start_vector( 10 downto 0) := (others => '0');
when 12 =>
var_start_vector(127 downto 12) := (others => '1');
var_start_vector( 11 downto 0) := (others => '0');
when 13 =>
var_start_vector(127 downto 13) := (others => '1');
var_start_vector( 12 downto 0) := (others => '0');
when 14 =>
var_start_vector(127 downto 14) := (others => '1');
var_start_vector( 13 downto 0) := (others => '0');
when 15 =>
var_start_vector(127 downto 15) := (others => '1');
var_start_vector( 14 downto 0) := (others => '0');
when 16 =>
var_start_vector(127 downto 16) := (others => '1');
var_start_vector( 15 downto 0) := (others => '0');
when 17 =>
var_start_vector(127 downto 17) := (others => '1');
var_start_vector( 16 downto 0) := (others => '0');
when 18 =>
var_start_vector(127 downto 18) := (others => '1');
var_start_vector( 17 downto 0) := (others => '0');
when 19 =>
var_start_vector(127 downto 19) := (others => '1');
var_start_vector( 18 downto 0) := (others => '0');
when 20 =>
var_start_vector(127 downto 20) := (others => '1');
var_start_vector( 19 downto 0) := (others => '0');
when 21 =>
var_start_vector(127 downto 21) := (others => '1');
var_start_vector( 20 downto 0) := (others => '0');
when 22 =>
var_start_vector(127 downto 22) := (others => '1');
var_start_vector( 21 downto 0) := (others => '0');
when 23 =>
var_start_vector(127 downto 23) := (others => '1');
var_start_vector( 22 downto 0) := (others => '0');
when 24 =>
var_start_vector(127 downto 24) := (others => '1');
var_start_vector( 23 downto 0) := (others => '0');
when 25 =>
var_start_vector(127 downto 25) := (others => '1');
var_start_vector( 24 downto 0) := (others => '0');
when 26 =>
var_start_vector(127 downto 26) := (others => '1');
var_start_vector( 25 downto 0) := (others => '0');
when 27 =>
var_start_vector(127 downto 27) := (others => '1');
var_start_vector( 26 downto 0) := (others => '0');
when 28 =>
var_start_vector(127 downto 28) := (others => '1');
var_start_vector( 27 downto 0) := (others => '0');
when 29 =>
var_start_vector(127 downto 29) := (others => '1');
var_start_vector( 28 downto 0) := (others => '0');
when 30 =>
var_start_vector(127 downto 30) := (others => '1');
var_start_vector( 29 downto 0) := (others => '0');
when 31 =>
var_start_vector(127 downto 31) := (others => '1');
var_start_vector( 30 downto 0) := (others => '0');
when 32 =>
var_start_vector(127 downto 32) := (others => '1');
var_start_vector( 31 downto 0) := (others => '0');
when 33 =>
var_start_vector(127 downto 33) := (others => '1');
var_start_vector( 32 downto 0) := (others => '0');
when 34 =>
var_start_vector(127 downto 34) := (others => '1');
var_start_vector( 33 downto 0) := (others => '0');
when 35 =>
var_start_vector(127 downto 35) := (others => '1');
var_start_vector( 34 downto 0) := (others => '0');
when 36 =>
var_start_vector(127 downto 36) := (others => '1');
var_start_vector( 35 downto 0) := (others => '0');
when 37 =>
var_start_vector(127 downto 37) := (others => '1');
var_start_vector( 36 downto 0) := (others => '0');
when 38 =>
var_start_vector(127 downto 38) := (others => '1');
var_start_vector( 37 downto 0) := (others => '0');
when 39 =>
var_start_vector(127 downto 39) := (others => '1');
var_start_vector( 38 downto 0) := (others => '0');
when 40 =>
var_start_vector(127 downto 40) := (others => '1');
var_start_vector( 39 downto 0) := (others => '0');
when 41 =>
var_start_vector(127 downto 41) := (others => '1');
var_start_vector( 40 downto 0) := (others => '0');
when 42 =>
var_start_vector(127 downto 42) := (others => '1');
var_start_vector( 41 downto 0) := (others => '0');
when 43 =>
var_start_vector(127 downto 43) := (others => '1');
var_start_vector( 42 downto 0) := (others => '0');
when 44 =>
var_start_vector(127 downto 44) := (others => '1');
var_start_vector( 43 downto 0) := (others => '0');
when 45 =>
var_start_vector(127 downto 45) := (others => '1');
var_start_vector( 44 downto 0) := (others => '0');
when 46 =>
var_start_vector(127 downto 46) := (others => '1');
var_start_vector( 45 downto 0) := (others => '0');
when 47 =>
var_start_vector(127 downto 47) := (others => '1');
var_start_vector( 46 downto 0) := (others => '0');
when 48 =>
var_start_vector(127 downto 48) := (others => '1');
var_start_vector( 47 downto 0) := (others => '0');
when 49 =>
var_start_vector(127 downto 49) := (others => '1');
var_start_vector( 48 downto 0) := (others => '0');
when 50 =>
var_start_vector(127 downto 50) := (others => '1');
var_start_vector( 49 downto 0) := (others => '0');
when 51 =>
var_start_vector(127 downto 51) := (others => '1');
var_start_vector( 50 downto 0) := (others => '0');
when 52 =>
var_start_vector(127 downto 52) := (others => '1');
var_start_vector( 51 downto 0) := (others => '0');
when 53 =>
var_start_vector(127 downto 53) := (others => '1');
var_start_vector( 52 downto 0) := (others => '0');
when 54 =>
var_start_vector(127 downto 54) := (others => '1');
var_start_vector( 53 downto 0) := (others => '0');
when 55 =>
var_start_vector(127 downto 55) := (others => '1');
var_start_vector( 54 downto 0) := (others => '0');
when 56 =>
var_start_vector(127 downto 56) := (others => '1');
var_start_vector( 55 downto 0) := (others => '0');
when 57 =>
var_start_vector(127 downto 57) := (others => '1');
var_start_vector( 56 downto 0) := (others => '0');
when 58 =>
var_start_vector(127 downto 58) := (others => '1');
var_start_vector( 57 downto 0) := (others => '0');
when 59 =>
var_start_vector(127 downto 59) := (others => '1');
var_start_vector( 58 downto 0) := (others => '0');
when 60 =>
var_start_vector(127 downto 60) := (others => '1');
var_start_vector( 59 downto 0) := (others => '0');
when 61 =>
var_start_vector(127 downto 61) := (others => '1');
var_start_vector( 60 downto 0) := (others => '0');
when 62 =>
var_start_vector(127 downto 62) := (others => '1');
var_start_vector( 61 downto 0) := (others => '0');
when 63 =>
var_start_vector(127 downto 63) := (others => '1');
var_start_vector( 62 downto 0) := (others => '0');
when 64 =>
var_start_vector(127 downto 64) := (others => '1');
var_start_vector( 63 downto 0) := (others => '0');
when 65 =>
var_start_vector(127 downto 65) := (others => '1');
var_start_vector( 64 downto 0) := (others => '0');
when 66 =>
var_start_vector(127 downto 66) := (others => '1');
var_start_vector( 65 downto 0) := (others => '0');
when 67 =>
var_start_vector(127 downto 67) := (others => '1');
var_start_vector( 66 downto 0) := (others => '0');
when 68 =>
var_start_vector(127 downto 68) := (others => '1');
var_start_vector( 67 downto 0) := (others => '0');
when 69 =>
var_start_vector(127 downto 69) := (others => '1');
var_start_vector( 68 downto 0) := (others => '0');
when 70 =>
var_start_vector(127 downto 70) := (others => '1');
var_start_vector( 69 downto 0) := (others => '0');
when 71 =>
var_start_vector(127 downto 71) := (others => '1');
var_start_vector( 70 downto 0) := (others => '0');
when 72 =>
var_start_vector(127 downto 72) := (others => '1');
var_start_vector( 71 downto 0) := (others => '0');
when 73 =>
var_start_vector(127 downto 73) := (others => '1');
var_start_vector( 72 downto 0) := (others => '0');
when 74 =>
var_start_vector(127 downto 74) := (others => '1');
var_start_vector( 73 downto 0) := (others => '0');
when 75 =>
var_start_vector(127 downto 75) := (others => '1');
var_start_vector( 74 downto 0) := (others => '0');
when 76 =>
var_start_vector(127 downto 76) := (others => '1');
var_start_vector( 75 downto 0) := (others => '0');
when 77 =>
var_start_vector(127 downto 77) := (others => '1');
var_start_vector( 76 downto 0) := (others => '0');
when 78 =>
var_start_vector(127 downto 78) := (others => '1');
var_start_vector( 77 downto 0) := (others => '0');
when 79 =>
var_start_vector(127 downto 79) := (others => '1');
var_start_vector( 78 downto 0) := (others => '0');
when 80 =>
var_start_vector(127 downto 80) := (others => '1');
var_start_vector( 79 downto 0) := (others => '0');
when 81 =>
var_start_vector(127 downto 81) := (others => '1');
var_start_vector( 80 downto 0) := (others => '0');
when 82 =>
var_start_vector(127 downto 82) := (others => '1');
var_start_vector( 81 downto 0) := (others => '0');
when 83 =>
var_start_vector(127 downto 83) := (others => '1');
var_start_vector( 82 downto 0) := (others => '0');
when 84 =>
var_start_vector(127 downto 84) := (others => '1');
var_start_vector( 83 downto 0) := (others => '0');
when 85 =>
var_start_vector(127 downto 85) := (others => '1');
var_start_vector( 84 downto 0) := (others => '0');
when 86 =>
var_start_vector(127 downto 86) := (others => '1');
var_start_vector( 85 downto 0) := (others => '0');
when 87 =>
var_start_vector(127 downto 87) := (others => '1');
var_start_vector( 86 downto 0) := (others => '0');
when 88 =>
var_start_vector(127 downto 88) := (others => '1');
var_start_vector( 87 downto 0) := (others => '0');
when 89 =>
var_start_vector(127 downto 89) := (others => '1');
var_start_vector( 88 downto 0) := (others => '0');
when 90 =>
var_start_vector(127 downto 90) := (others => '1');
var_start_vector( 89 downto 0) := (others => '0');
when 91 =>
var_start_vector(127 downto 91) := (others => '1');
var_start_vector( 90 downto 0) := (others => '0');
when 92 =>
var_start_vector(127 downto 92) := (others => '1');
var_start_vector( 91 downto 0) := (others => '0');
when 93 =>
var_start_vector(127 downto 93) := (others => '1');
var_start_vector( 92 downto 0) := (others => '0');
when 94 =>
var_start_vector(127 downto 94) := (others => '1');
var_start_vector( 93 downto 0) := (others => '0');
when 95 =>
var_start_vector(127 downto 95) := (others => '1');
var_start_vector( 94 downto 0) := (others => '0');
when 96 =>
var_start_vector(127 downto 96) := (others => '1');
var_start_vector( 95 downto 0) := (others => '0');
when 97 =>
var_start_vector(127 downto 97) := (others => '1');
var_start_vector( 96 downto 0) := (others => '0');
when 98 =>
var_start_vector(127 downto 98) := (others => '1');
var_start_vector( 97 downto 0) := (others => '0');
when 99 =>
var_start_vector(127 downto 99) := (others => '1');
var_start_vector( 98 downto 0) := (others => '0');
when 100 =>
var_start_vector(127 downto 100) := (others => '1');
var_start_vector( 99 downto 0) := (others => '0');
when 101 =>
var_start_vector(127 downto 101) := (others => '1');
var_start_vector(100 downto 0) := (others => '0');
when 102 =>
var_start_vector(127 downto 102) := (others => '1');
var_start_vector(101 downto 0) := (others => '0');
when 103 =>
var_start_vector(127 downto 103) := (others => '1');
var_start_vector(102 downto 0) := (others => '0');
when 104 =>
var_start_vector(127 downto 104) := (others => '1');
var_start_vector(103 downto 0) := (others => '0');
when 105 =>
var_start_vector(127 downto 105) := (others => '1');
var_start_vector(104 downto 0) := (others => '0');
when 106 =>
var_start_vector(127 downto 106) := (others => '1');
var_start_vector(105 downto 0) := (others => '0');
when 107 =>
var_start_vector(127 downto 107) := (others => '1');
var_start_vector(106 downto 0) := (others => '0');
when 108 =>
var_start_vector(127 downto 108) := (others => '1');
var_start_vector(107 downto 0) := (others => '0');
when 109 =>
var_start_vector(127 downto 109) := (others => '1');
var_start_vector(108 downto 0) := (others => '0');
when 110 =>
var_start_vector(127 downto 110) := (others => '1');
var_start_vector(109 downto 0) := (others => '0');
when 111 =>
var_start_vector(127 downto 111) := (others => '1');
var_start_vector(110 downto 0) := (others => '0');
when 112 =>
var_start_vector(127 downto 112) := (others => '1');
var_start_vector(111 downto 0) := (others => '0');
when 113 =>
var_start_vector(127 downto 113) := (others => '1');
var_start_vector(112 downto 0) := (others => '0');
when 114 =>
var_start_vector(127 downto 114) := (others => '1');
var_start_vector(113 downto 0) := (others => '0');
when 115 =>
var_start_vector(127 downto 115) := (others => '1');
var_start_vector(114 downto 0) := (others => '0');
when 116 =>
var_start_vector(127 downto 116) := (others => '1');
var_start_vector(115 downto 0) := (others => '0');
when 117 =>
var_start_vector(127 downto 117) := (others => '1');
var_start_vector(116 downto 0) := (others => '0');
when 118 =>
var_start_vector(127 downto 118) := (others => '1');
var_start_vector(117 downto 0) := (others => '0');
when 119 =>
var_start_vector(127 downto 119) := (others => '1');
var_start_vector(118 downto 0) := (others => '0');
when 120 =>
var_start_vector(127 downto 120) := (others => '1');
var_start_vector(119 downto 0) := (others => '0');
when 121 =>
var_start_vector(127 downto 121) := (others => '1');
var_start_vector(120 downto 0) := (others => '0');
when 122 =>
var_start_vector(127 downto 122) := (others => '1');
var_start_vector(121 downto 0) := (others => '0');
when 123 =>
var_start_vector(127 downto 123) := (others => '1');
var_start_vector(122 downto 0) := (others => '0');
when 124 =>
var_start_vector(127 downto 124) := (others => '1');
var_start_vector(123 downto 0) := (others => '0');
when 125 =>
var_start_vector(127 downto 125) := (others => '1');
var_start_vector(124 downto 0) := (others => '0');
when 126 =>
var_start_vector(127 downto 126) := (others => '1');
var_start_vector(125 downto 0) := (others => '0');
when others =>
var_start_vector(127 downto 127) := (others => '1');
var_start_vector(126 downto 0) := (others => '0');
end case;
Return (var_start_vector);
end function get_start_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_128
--
-- Function Description:
-- Returns the 128-bit vector filled with '1's from the lsbit
-- of the vector to the end offset.
--
-------------------------------------------------------------------
function get_end_128 (end_offset : natural) return std_logic_vector is
Variable var_end_vector : std_logic_vector(127 downto 0) := (others => '0');
begin
case end_offset is
when 0 =>
var_end_vector(127 downto 1) := (others => '0');
var_end_vector( 0 downto 0) := (others => '1');
when 1 =>
var_end_vector(127 downto 2) := (others => '0');
var_end_vector( 1 downto 0) := (others => '1');
when 2 =>
var_end_vector(127 downto 3) := (others => '0');
var_end_vector( 2 downto 0) := (others => '1');
when 3 =>
var_end_vector(127 downto 4) := (others => '0');
var_end_vector( 3 downto 0) := (others => '1');
when 4 =>
var_end_vector(127 downto 5) := (others => '0');
var_end_vector( 4 downto 0) := (others => '1');
when 5 =>
var_end_vector(127 downto 6) := (others => '0');
var_end_vector( 5 downto 0) := (others => '1');
when 6 =>
var_end_vector(127 downto 7) := (others => '0');
var_end_vector( 6 downto 0) := (others => '1');
when 7 =>
var_end_vector(127 downto 8) := (others => '0');
var_end_vector( 7 downto 0) := (others => '1');
when 8 =>
var_end_vector(127 downto 9) := (others => '0');
var_end_vector( 8 downto 0) := (others => '1');
when 9 =>
var_end_vector(127 downto 10) := (others => '0');
var_end_vector( 9 downto 0) := (others => '1');
when 10 =>
var_end_vector(127 downto 11) := (others => '0');
var_end_vector( 10 downto 0) := (others => '1');
when 11 =>
var_end_vector(127 downto 12) := (others => '0');
var_end_vector( 11 downto 0) := (others => '1');
when 12 =>
var_end_vector(127 downto 13) := (others => '0');
var_end_vector( 12 downto 0) := (others => '1');
when 13 =>
var_end_vector(127 downto 14) := (others => '0');
var_end_vector( 13 downto 0) := (others => '1');
when 14 =>
var_end_vector(127 downto 15) := (others => '0');
var_end_vector( 14 downto 0) := (others => '1');
when 15 =>
var_end_vector(127 downto 16) := (others => '0');
var_end_vector( 15 downto 0) := (others => '1');
when 16 =>
var_end_vector(127 downto 17) := (others => '0');
var_end_vector( 16 downto 0) := (others => '1');
when 17 =>
var_end_vector(127 downto 18) := (others => '0');
var_end_vector( 17 downto 0) := (others => '1');
when 18 =>
var_end_vector(127 downto 19) := (others => '0');
var_end_vector( 18 downto 0) := (others => '1');
when 19 =>
var_end_vector(127 downto 20) := (others => '0');
var_end_vector( 19 downto 0) := (others => '1');
when 20 =>
var_end_vector(127 downto 21) := (others => '0');
var_end_vector( 20 downto 0) := (others => '1');
when 21 =>
var_end_vector(127 downto 22) := (others => '0');
var_end_vector( 21 downto 0) := (others => '1');
when 22 =>
var_end_vector(127 downto 23) := (others => '0');
var_end_vector( 22 downto 0) := (others => '1');
when 23 =>
var_end_vector(127 downto 24) := (others => '0');
var_end_vector( 23 downto 0) := (others => '1');
when 24 =>
var_end_vector(127 downto 25) := (others => '0');
var_end_vector( 24 downto 0) := (others => '1');
when 25 =>
var_end_vector(127 downto 26) := (others => '0');
var_end_vector( 25 downto 0) := (others => '1');
when 26 =>
var_end_vector(127 downto 27) := (others => '0');
var_end_vector( 26 downto 0) := (others => '1');
when 27 =>
var_end_vector(127 downto 28) := (others => '0');
var_end_vector( 27 downto 0) := (others => '1');
when 28 =>
var_end_vector(127 downto 29) := (others => '0');
var_end_vector( 28 downto 0) := (others => '1');
when 29 =>
var_end_vector(127 downto 30) := (others => '0');
var_end_vector( 29 downto 0) := (others => '1');
when 30 =>
var_end_vector(127 downto 31) := (others => '0');
var_end_vector( 30 downto 0) := (others => '1');
when 31 =>
var_end_vector(127 downto 32) := (others => '0');
var_end_vector( 31 downto 0) := (others => '1');
when 32 =>
var_end_vector(127 downto 33) := (others => '0');
var_end_vector( 32 downto 0) := (others => '1');
when 33 =>
var_end_vector(127 downto 34) := (others => '0');
var_end_vector( 33 downto 0) := (others => '1');
when 34 =>
var_end_vector(127 downto 35) := (others => '0');
var_end_vector( 34 downto 0) := (others => '1');
when 35 =>
var_end_vector(127 downto 36) := (others => '0');
var_end_vector( 35 downto 0) := (others => '1');
when 36 =>
var_end_vector(127 downto 37) := (others => '0');
var_end_vector( 36 downto 0) := (others => '1');
when 37 =>
var_end_vector(127 downto 38) := (others => '0');
var_end_vector( 37 downto 0) := (others => '1');
when 38 =>
var_end_vector(127 downto 39) := (others => '0');
var_end_vector( 38 downto 0) := (others => '1');
when 39 =>
var_end_vector(127 downto 40) := (others => '0');
var_end_vector( 39 downto 0) := (others => '1');
when 40 =>
var_end_vector(127 downto 41) := (others => '0');
var_end_vector( 40 downto 0) := (others => '1');
when 41 =>
var_end_vector(127 downto 42) := (others => '0');
var_end_vector( 41 downto 0) := (others => '1');
when 42 =>
var_end_vector(127 downto 43) := (others => '0');
var_end_vector( 42 downto 0) := (others => '1');
when 43 =>
var_end_vector(127 downto 44) := (others => '0');
var_end_vector( 43 downto 0) := (others => '1');
when 44 =>
var_end_vector(127 downto 45) := (others => '0');
var_end_vector( 44 downto 0) := (others => '1');
when 45 =>
var_end_vector(127 downto 46) := (others => '0');
var_end_vector( 45 downto 0) := (others => '1');
when 46 =>
var_end_vector(127 downto 47) := (others => '0');
var_end_vector( 46 downto 0) := (others => '1');
when 47 =>
var_end_vector(127 downto 48) := (others => '0');
var_end_vector( 47 downto 0) := (others => '1');
when 48 =>
var_end_vector(127 downto 49) := (others => '0');
var_end_vector( 48 downto 0) := (others => '1');
when 49 =>
var_end_vector(127 downto 50) := (others => '0');
var_end_vector( 49 downto 0) := (others => '1');
when 50 =>
var_end_vector(127 downto 51) := (others => '0');
var_end_vector( 50 downto 0) := (others => '1');
when 51 =>
var_end_vector(127 downto 52) := (others => '0');
var_end_vector( 51 downto 0) := (others => '1');
when 52 =>
var_end_vector(127 downto 53) := (others => '0');
var_end_vector( 52 downto 0) := (others => '1');
when 53 =>
var_end_vector(127 downto 54) := (others => '0');
var_end_vector( 53 downto 0) := (others => '1');
when 54 =>
var_end_vector(127 downto 55) := (others => '0');
var_end_vector( 54 downto 0) := (others => '1');
when 55 =>
var_end_vector(127 downto 56) := (others => '0');
var_end_vector( 55 downto 0) := (others => '1');
when 56 =>
var_end_vector(127 downto 57) := (others => '0');
var_end_vector( 56 downto 0) := (others => '1');
when 57 =>
var_end_vector(127 downto 58) := (others => '0');
var_end_vector( 57 downto 0) := (others => '1');
when 58 =>
var_end_vector(127 downto 59) := (others => '0');
var_end_vector( 58 downto 0) := (others => '1');
when 59 =>
var_end_vector(127 downto 60) := (others => '0');
var_end_vector( 59 downto 0) := (others => '1');
when 60 =>
var_end_vector(127 downto 61) := (others => '0');
var_end_vector( 60 downto 0) := (others => '1');
when 61 =>
var_end_vector(127 downto 62) := (others => '0');
var_end_vector( 61 downto 0) := (others => '1');
when 62 =>
var_end_vector(127 downto 63) := (others => '0');
var_end_vector( 62 downto 0) := (others => '1');
when 63 =>
var_end_vector(127 downto 64) := (others => '0');
var_end_vector( 63 downto 0) := (others => '1');
when 64 =>
var_end_vector(127 downto 65) := (others => '0');
var_end_vector( 64 downto 0) := (others => '1');
when 65 =>
var_end_vector(127 downto 66) := (others => '0');
var_end_vector( 65 downto 0) := (others => '1');
when 66 =>
var_end_vector(127 downto 67) := (others => '0');
var_end_vector( 66 downto 0) := (others => '1');
when 67 =>
var_end_vector(127 downto 68) := (others => '0');
var_end_vector( 67 downto 0) := (others => '1');
when 68 =>
var_end_vector(127 downto 69) := (others => '0');
var_end_vector( 68 downto 0) := (others => '1');
when 69 =>
var_end_vector(127 downto 70) := (others => '0');
var_end_vector( 69 downto 0) := (others => '1');
when 70 =>
var_end_vector(127 downto 71) := (others => '0');
var_end_vector( 70 downto 0) := (others => '1');
when 71 =>
var_end_vector(127 downto 72) := (others => '0');
var_end_vector( 71 downto 0) := (others => '1');
when 72 =>
var_end_vector(127 downto 73) := (others => '0');
var_end_vector( 72 downto 0) := (others => '1');
when 73 =>
var_end_vector(127 downto 74) := (others => '0');
var_end_vector( 73 downto 0) := (others => '1');
when 74 =>
var_end_vector(127 downto 75) := (others => '0');
var_end_vector( 74 downto 0) := (others => '1');
when 75 =>
var_end_vector(127 downto 76) := (others => '0');
var_end_vector( 75 downto 0) := (others => '1');
when 76 =>
var_end_vector(127 downto 77) := (others => '0');
var_end_vector( 76 downto 0) := (others => '1');
when 77 =>
var_end_vector(127 downto 78) := (others => '0');
var_end_vector( 77 downto 0) := (others => '1');
when 78 =>
var_end_vector(127 downto 79) := (others => '0');
var_end_vector( 78 downto 0) := (others => '1');
when 79 =>
var_end_vector(127 downto 80) := (others => '0');
var_end_vector( 79 downto 0) := (others => '1');
when 80 =>
var_end_vector(127 downto 81) := (others => '0');
var_end_vector( 80 downto 0) := (others => '1');
when 81 =>
var_end_vector(127 downto 82) := (others => '0');
var_end_vector( 81 downto 0) := (others => '1');
when 82 =>
var_end_vector(127 downto 83) := (others => '0');
var_end_vector( 82 downto 0) := (others => '1');
when 83 =>
var_end_vector(127 downto 84) := (others => '0');
var_end_vector( 83 downto 0) := (others => '1');
when 84 =>
var_end_vector(127 downto 85) := (others => '0');
var_end_vector( 84 downto 0) := (others => '1');
when 85 =>
var_end_vector(127 downto 86) := (others => '0');
var_end_vector( 85 downto 0) := (others => '1');
when 86 =>
var_end_vector(127 downto 87) := (others => '0');
var_end_vector( 86 downto 0) := (others => '1');
when 87 =>
var_end_vector(127 downto 88) := (others => '0');
var_end_vector( 87 downto 0) := (others => '1');
when 88 =>
var_end_vector(127 downto 89) := (others => '0');
var_end_vector( 88 downto 0) := (others => '1');
when 89 =>
var_end_vector(127 downto 90) := (others => '0');
var_end_vector( 89 downto 0) := (others => '1');
when 90 =>
var_end_vector(127 downto 91) := (others => '0');
var_end_vector( 90 downto 0) := (others => '1');
when 91 =>
var_end_vector(127 downto 92) := (others => '0');
var_end_vector( 91 downto 0) := (others => '1');
when 92 =>
var_end_vector(127 downto 93) := (others => '0');
var_end_vector( 92 downto 0) := (others => '1');
when 93 =>
var_end_vector(127 downto 94) := (others => '0');
var_end_vector( 93 downto 0) := (others => '1');
when 94 =>
var_end_vector(127 downto 95) := (others => '0');
var_end_vector( 94 downto 0) := (others => '1');
when 95 =>
var_end_vector(127 downto 96) := (others => '0');
var_end_vector( 95 downto 0) := (others => '1');
when 96 =>
var_end_vector(127 downto 97) := (others => '0');
var_end_vector( 96 downto 0) := (others => '1');
when 97 =>
var_end_vector(127 downto 98) := (others => '0');
var_end_vector( 97 downto 0) := (others => '1');
when 98 =>
var_end_vector(127 downto 99) := (others => '0');
var_end_vector( 98 downto 0) := (others => '1');
when 99 =>
var_end_vector(127 downto 100) := (others => '0');
var_end_vector( 99 downto 0) := (others => '1');
when 100 =>
var_end_vector(127 downto 101) := (others => '0');
var_end_vector(100 downto 0) := (others => '1');
when 101 =>
var_end_vector(127 downto 102) := (others => '0');
var_end_vector(101 downto 0) := (others => '1');
when 102 =>
var_end_vector(127 downto 103) := (others => '0');
var_end_vector(102 downto 0) := (others => '1');
when 103 =>
var_end_vector(127 downto 104) := (others => '0');
var_end_vector(103 downto 0) := (others => '1');
when 104 =>
var_end_vector(127 downto 105) := (others => '0');
var_end_vector(104 downto 0) := (others => '1');
when 105 =>
var_end_vector(127 downto 106) := (others => '0');
var_end_vector(105 downto 0) := (others => '1');
when 106 =>
var_end_vector(127 downto 107) := (others => '0');
var_end_vector(106 downto 0) := (others => '1');
when 107 =>
var_end_vector(127 downto 108) := (others => '0');
var_end_vector(107 downto 0) := (others => '1');
when 108 =>
var_end_vector(127 downto 109) := (others => '0');
var_end_vector(108 downto 0) := (others => '1');
when 109 =>
var_end_vector(127 downto 110) := (others => '0');
var_end_vector(109 downto 0) := (others => '1');
when 110 =>
var_end_vector(127 downto 111) := (others => '0');
var_end_vector(110 downto 0) := (others => '1');
when 111 =>
var_end_vector(127 downto 112) := (others => '0');
var_end_vector(111 downto 0) := (others => '1');
when 112 =>
var_end_vector(127 downto 113) := (others => '0');
var_end_vector(112 downto 0) := (others => '1');
when 113 =>
var_end_vector(127 downto 114) := (others => '0');
var_end_vector(113 downto 0) := (others => '1');
when 114 =>
var_end_vector(127 downto 115) := (others => '0');
var_end_vector(114 downto 0) := (others => '1');
when 115 =>
var_end_vector(127 downto 116) := (others => '0');
var_end_vector(115 downto 0) := (others => '1');
when 116 =>
var_end_vector(127 downto 117) := (others => '0');
var_end_vector(116 downto 0) := (others => '1');
when 117 =>
var_end_vector(127 downto 118) := (others => '0');
var_end_vector(117 downto 0) := (others => '1');
when 118 =>
var_end_vector(127 downto 119) := (others => '0');
var_end_vector(118 downto 0) := (others => '1');
when 119 =>
var_end_vector(127 downto 120) := (others => '0');
var_end_vector(119 downto 0) := (others => '1');
when 120 =>
var_end_vector(127 downto 121) := (others => '0');
var_end_vector(120 downto 0) := (others => '1');
when 121 =>
var_end_vector(127 downto 122) := (others => '0');
var_end_vector(121 downto 0) := (others => '1');
when 122 =>
var_end_vector(127 downto 123) := (others => '0');
var_end_vector(122 downto 0) := (others => '1');
when 123 =>
var_end_vector(127 downto 124) := (others => '0');
var_end_vector(123 downto 0) := (others => '1');
when 124 =>
var_end_vector(127 downto 125) := (others => '0');
var_end_vector(124 downto 0) := (others => '1');
when 125 =>
var_end_vector(127 downto 126) := (others => '0');
var_end_vector(125 downto 0) := (others => '1');
when 126 =>
var_end_vector(127 downto 127) := (others => '0');
var_end_vector(126 downto 0) := (others => '1');
when others =>
var_end_vector(127 downto 0) := (others => '1');
end case;
Return (var_end_vector);
end function get_end_128;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_value
--
-- Function Description:
-- Returns a value that cannot exceed a clip value.
--
-------------------------------------------------------------------
function funct_clip_value (input_value : natural;
max_value : natural) return natural is
Variable temp_value : Natural := 0;
begin
If (input_value <= max_value) Then
temp_value := input_value;
Else
temp_value := max_value;
End if;
Return (temp_value);
end function funct_clip_value;
-- Constants
Constant INTERNAL_CALC_WIDTH : integer := C_NUM_BYTES_WIDTH+(C_OP_MODE*2); -- Add 2 bits of math headroom
-- if op Mode = 1
-- Signals
signal sig_ouput_stbs : std_logic_vector(C_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_start_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal sig_end_offset_un : unsigned(INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-- Assign the output strobe value
strb_out <= sig_ouput_stbs ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_OFF_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start and end offsets are being provided.
--
--
------------------------------------------------------------
GEN_OFF_OFF_CASE : if (C_OP_MODE = 1) generate
begin
sig_start_offset_un <= RESIZE(UNSIGNED(start_addr_offset), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= RESIZE(UNSIGNED(end_addr_offset), INTERNAL_CALC_WIDTH);
end generate GEN_OFF_OFF_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OFF_LEN_CASE
--
-- If Generate Description:
-- Calculates the internal start and end offsets for the
-- case when start offset and length are being provided.
--
------------------------------------------------------------
GEN_OFF_LEN_CASE : if (C_OP_MODE = 0) generate
-- Local Constants Declarations
Constant L_INTERNAL_CALC_WIDTH : integer := INTERNAL_CALC_WIDTH;
Constant L_ONE : unsigned := TO_UNSIGNED(1, L_INTERNAL_CALC_WIDTH);
Constant L_ZERO : unsigned := TO_UNSIGNED(0, L_INTERNAL_CALC_WIDTH);
Constant MAX_VALUE : natural := C_STRB_WIDTH-1;
-- local signals
signal lsig_addr_offset_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_num_valid_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_length_adjust_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_incr_offset_bytes_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_us : unsigned(L_INTERNAL_CALC_WIDTH-1 downto 0) := (others => '0');
signal lsig_end_addr_int : integer := 0;
signal lsig_strt_addr_int : integer := 0;
begin
lsig_addr_offset_us <= RESIZE(UNSIGNED(start_addr_offset), L_INTERNAL_CALC_WIDTH);
lsig_num_valid_bytes_us <= RESIZE(UNSIGNED(num_valid_bytes) , L_INTERNAL_CALC_WIDTH);
lsig_length_adjust_us <= L_ZERO
When (lsig_num_valid_bytes_us = L_ZERO)
Else L_ONE;
lsig_incr_offset_bytes_us <= lsig_num_valid_bytes_us - lsig_length_adjust_us;
lsig_end_addr_us <= lsig_addr_offset_us + lsig_incr_offset_bytes_us;
lsig_strt_addr_int <= TO_INTEGER(lsig_addr_offset_us);
lsig_end_addr_int <= TO_INTEGER(lsig_end_addr_us);
sig_start_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_strt_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH);
sig_end_offset_un <= TO_UNSIGNED(funct_clip_value(lsig_end_addr_int, MAX_VALUE), INTERNAL_CALC_WIDTH) ;
end generate GEN_OFF_LEN_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_1BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 1-bit strobe width case.
--
--
------------------------------------------------------------
GEN_1BIT_CASE : if (C_STRB_WIDTH = 1) generate
begin
sig_ouput_stbs <= (others => '1') ;
end generate GEN_1BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_2BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 2-bit strobe width case.
--
--
------------------------------------------------------------
GEN_2BIT_CASE : if (C_STRB_WIDTH = 2) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 1;
Signal lsig_start_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(1 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(1 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_2(lsig_start_offset);
lsig_end_vect <= get_end_2(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_2BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_4BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 4-bit strobe width case.
--
--
------------------------------------------------------------
GEN_4BIT_CASE : if (C_STRB_WIDTH = 4) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 3;
Signal lsig_start_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(3 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(3 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_4(lsig_start_offset);
lsig_end_vect <= get_end_4(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_4BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_8BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 8-bit strobe width case.
--
--
------------------------------------------------------------
GEN_8BIT_CASE : if (C_STRB_WIDTH = 8) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 7;
Signal lsig_start_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(7 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(7 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_8(lsig_start_offset);
lsig_end_vect <= get_end_8(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_8BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_16BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 16-bit strobe width case.
--
--
------------------------------------------------------------
GEN_16BIT_CASE : if (C_STRB_WIDTH = 16) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 15;
Signal lsig_start_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(15 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(15 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_16(lsig_start_offset);
lsig_end_vect <= get_end_16(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_16BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_32BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 32-bit strobe width case.
--
--
------------------------------------------------------------
GEN_32BIT_CASE : if (C_STRB_WIDTH = 32) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 31;
Signal lsig_start_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(31 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(31 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_32(lsig_start_offset);
lsig_end_vect <= get_end_32(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_32BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_64BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_64BIT_CASE : if (C_STRB_WIDTH = 64) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 63;
Signal lsig_start_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(63 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(63 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_64(lsig_start_offset);
lsig_end_vect <= get_end_64(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_64BIT_CASE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_128BIT_CASE
--
-- If Generate Description:
-- Generates the strobes for the 64-bit strobe width case.
--
--
------------------------------------------------------------
GEN_128BIT_CASE : if (C_STRB_WIDTH = 128) generate
-- local signals
Signal lsig_start_offset : Natural := 0;
Signal lsig_end_offset : Natural := 127;
Signal lsig_start_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_end_vect : std_logic_vector(127 downto 0) := (others => '0');
Signal lsig_cmplt_vect : std_logic_vector(127 downto 0) := (others => '0');
begin
lsig_start_offset <= TO_INTEGER(sig_start_offset_un) ;
lsig_end_offset <= TO_INTEGER(sig_end_offset_un ) ;
lsig_start_vect <= get_start_128(lsig_start_offset);
lsig_end_vect <= get_end_128(lsig_end_offset) ;
lsig_cmplt_vect <= lsig_start_vect and
lsig_end_vect;
sig_ouput_stbs <= lsig_cmplt_vect ;
end generate GEN_128BIT_CASE;
end implementation;
| bsd-2-clause | 53ea934e0489bcec709ddb12fbb13e59 | 0.454366 | 4.923898 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_waveforms/rule_100_test_input.vhd | 2 | 397 |
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0'when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 | bde3ec380b9558c811d72155c1f3198c | 0.544081 | 2.544872 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd | 1 | 61,339 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_realign.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_realign.vhd
--
-- Description:
-- This file implements the S2MM Data Realignment module. THe S2MM direction is
-- more complex than the MM2S direction since the DRE needs to be upstream from
-- the Write Data Controller. This requires the S2MM DRE to be running 2 to
-- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer
-- bubble insertion.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_s2mm_realign.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 5/9/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added the Store and Forward Starting Address
-- Offset ports and support logic for data upsizer
-- in the Store and Forward modules.
-- ^^^^^^
--
-- DET 6/14/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR613211
-- - Added push-pull register for the start addr offset output to
-- align the timing of the offset changes to Store and Forward with
-- the variable TLAST assertion on the DRE output.
-- ^^^^^^
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 6/29/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Incorporated a state machine to manage the command load into
-- the DRE and the Scatter modules. This was needed to adjust to
-- interface timing differences with the Scatter Module when the
-- Indeterminate BTT mode overflow absorption modification was added.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_s2mm_dre;
use axi_datamover_v5_1.axi_datamover_s2mm_scatter;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_realign is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the IBTT Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_INCLUDE_DRE : Integer range 0 to 1 := 1;
-- Includes/Omits the S2MM DRE
-- 0 = Omit
-- 1 = Include
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal command queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_SUPPORT_SCATTER : Integer range 0 to 1 := 1;
-- Includes/Omits the Scatter functionality
-- 0 = omit
-- 1 = include
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_BTT_USED : Integer range 8 to 23 := 16;
-- Indicates the width of the input command BTT that is actually
-- used
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Input and Output Stream Data ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the input command Tag port
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ;
-- Sets the width of the Store and Forward Start offset ports
C_FAMILY : String := "virtex7"
-- specifies the target FPGA familiy
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------------
-- Write Data Controller or IBTT Indeterminate BTT I/O -------------------------
--
wdc2dre_wready : In std_logic; --
-- Write READY input from WDC or SF --
--
dre2wdc_wvalid : Out std_logic; --
-- Write VALID output to WDC or SF --
--
dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to WDC or SF --
--
dre2wdc_wlast : Out std_logic; --
-- Write LAST output to WDC or SF --
--
dre2wdc_eop : Out std_logic; --
-- End of Packet indicator for the Stream input to WDC or SF --
--------------------------------------------------------------------------------
-- Starting offset output for the Store and Forward Modules -------------------
--
dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
--------------------------------------------------------------------------------
-- AXI Slave Stream In ----------------------------------------------------------
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY input --
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST output --
--------------------------------------------------------------------------------
-- Command Calculator Interface ---------------------------------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2dre_cmd_cmplt : In std_logic; --
-- The last tranfer command of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- Premature TLAST assertion error flag -----------------------------
--
dre2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the DRE detected --
-- a Early/Late TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------
-- DRE Halted Status ------------------------------------------------
--
dre2all_halted : Out std_logic --
-- When asserted, this indicates the DRE has satisfied --
-- all pending transfers queued by the command calculator --
-- and is halted. --
---------------------------------------------------------------------
);
end entity axi_datamover_s2mm_realign;
architecture implementation of axi_datamover_s2mm_realign is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations --------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_realign_fifo
--
-- Function Description:
-- Assures that the Realigner cmd fifo depth is at least 4 deep else it
-- is equal to the pipe depth.
--
-------------------------------------------------------------------
function funct_size_realign_fifo (pipe_depth : integer) return integer is
Variable temp_fifo_depth : Integer := 4;
begin
If (pipe_depth < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := pipe_depth;
End if;
Return (temp_fifo_depth);
end function funct_size_realign_fifo;
-- Constant Declarations --------------------------------------------
Constant BYTE_WIDTH : integer := 8; -- bits
Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH;
Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant BTT_WIDTH : integer := C_BTT_USED;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0)
:= (others => '0');
Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH);
Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
BTT_WIDTH + -- BTT field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and
C_STREAM_DWIDTH <= 64 and
C_STREAM_DWIDTH >= 16);
Constant OMIT_DRE : boolean := not(INCLUDE_DRE);
-- Type Declarations --------------------------------------------
type TYPE_CMD_CNTL_SM is (
INIT,
LD_DRE_SCATTER_FIRST,
CHK_POP_FIRST ,
LD_DRE_SCATTER_SECOND,
CHK_POP_SECOND,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT;
Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT;
signal sig_sm_ld_dre_cmd_ns : std_logic := '0';
signal sig_sm_ld_dre_cmd : std_logic := '0';
signal sig_sm_ld_scatter_cmd_ns : std_logic := '0';
signal sig_sm_ld_scatter_cmd : std_logic := '0';
signal sig_sm_pop_cmd_fifo_ns : std_logic := '0';
signal sig_sm_pop_cmd_fifo : std_logic := '0';
signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_cmd_cmplt_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_dre2wdc_tlast : std_logic := '0';
signal sig_dre2wdc_tvalid : std_logic := '0';
signal sig_wdc2dre_tready : std_logic := '0';
signal sig_tlast_err0r : std_logic := '0';
signal sig_dre_halted : std_logic := '0';
signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_strm2scatter_tlast : std_logic := '0';
signal sig_strm2scatter_tvalid : std_logic := '0';
signal sig_scatter2strm_tready : std_logic := '0';
signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_scatter2dre_tlast : std_logic := '0';
signal sig_scatter2dre_tvalid : std_logic := '0';
signal sig_dre2scatter_tready : std_logic := '0';
signal sig_scatter2dre_flush : std_logic := '0';
signal sig_scatter2drc_eop : std_logic := '0';
signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_scatter2drc_cmd_ready : std_logic := '0';
signal sig_drc2scatter_push_cmd : std_logic;
signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0);
signal sig_drc2scatter_eof : std_logic;
signal sig_scatter2all_tlast_error : std_logic := '0';
signal sig_need_cmd_flush : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_strt_offset : std_logic := '0';
signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Port connections
-- Input Stream Attachment
s2mm_strm_wready <= sig_scatter2strm_tready ;
sig_strm2scatter_tvalid <= s2mm_strm_wvalid ;
sig_strm2scatter_tdata <= s2mm_strm_wdata ;
sig_strm2scatter_tstrb <= s2mm_strm_wstrb ;
sig_strm2scatter_tlast <= s2mm_strm_wlast ;
-- Write Data Controller Stream Attachment
sig_wdc2dre_tready <= wdc2dre_wready ;
dre2wdc_wvalid <= sig_dre2wdc_tvalid ;
dre2wdc_wdata <= sig_dre2wdc_tdata ;
dre2wdc_wstrb <= sig_dre2wdc_tstrb ;
dre2wdc_wlast <= sig_dre2wdc_tlast ;
-- Status/Error flags
dre2all_tlast_error <= sig_tlast_err0r ;
dre2all_halted <= sig_dre_halted ;
-- Store and Forward Starting Offset Output
dre2sf_strt_offset <= sig_dre2sf_strt_offset ;
-------------------------------------------------------------
-- Internal logic
sig_dre_halted <= sig_dre_align_ready;
-------------------------------------------------------------
-- DRE Handshake signals
sig_dre_src_align <= sig_curr_src_align_reg ;
sig_dre_dest_align <= sig_curr_dest_align_reg;
sig_dre_use_autodest <= '0'; -- not used
sig_dre_flush <= '0'; -- not used
-------------------------------------------------------------------------
-------- Realigner Command FIFO and controls
-------------------------------------------------------------------------
-- Command Calculator Handshake
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_cmd_cmplt &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_btt &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX);
sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECTL_FIFO_WIDTH ,
C_DEPTH => DRECTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_sm_pop_cmd_fifo ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-------- DRE and Scatter Command Loader State Machine
-------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CMDCNTL_SM_COMBINATIONAL
--
-- Process Description:
-- Command Controller State Machine combinational implementation
-- The design is based on the premise that for every parent
-- command loaded into the S2MM, the Realigner can be loaded with
-- 1 or 2 commands spawned from it. The first command is used to
-- align ensuing transfers (in MMap space) to a max burst address
-- boundary. Then, if the parent command's BTT value is not satisfied
-- after the first command completes, a second command is generated
-- and loaded in the Realigner for the remaining BTT value. The
-- command complete bit in the Realigner command indicates if the
-- first command the final command or the second command (if needed)
-- is the final command,
-------------------------------------------------------------
CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state ,
sig_fifo_rd_cmd_valid ,
sig_dre_align_ready ,
sig_scatter2drc_cmd_ready ,
sig_need_cmd_flush ,
sig_curr_cmd_cmplt_reg ,
sig_curr_calc_error_reg
)
begin
-- SM Defaults
sig_cmdcntl_sm_state_ns <= INIT;
sig_sm_ld_dre_cmd_ns <= '0';
sig_sm_ld_scatter_cmd_ns <= '0';
sig_sm_pop_cmd_fifo_ns <= '0';
case sig_cmdcntl_sm_state is
--------------------------------------------
when INIT =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
--------------------------------------------
when LD_DRE_SCATTER_FIRST =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
End if;
--------------------------------------------
when CHK_POP_FIRST =>
If (sig_curr_cmd_cmplt_reg = '1') Then
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST;
Else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when LD_DRE_SCATTER_SECOND =>
If (sig_fifo_rd_cmd_valid = '1' and
sig_curr_calc_error_reg = '1') Then
sig_cmdcntl_sm_state_ns <= ERROR_TRAP;
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_need_cmd_flush = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ;
sig_sm_pop_cmd_fifo_ns <= '1';
elsif (sig_fifo_rd_cmd_valid = '1' and
sig_dre_align_ready = '1' and
sig_scatter2drc_cmd_ready = '1') Then
sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ;
sig_sm_ld_dre_cmd_ns <= '1';
sig_sm_ld_scatter_cmd_ns <= '1';
sig_sm_pop_cmd_fifo_ns <= '1';
else
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND;
End if;
--------------------------------------------
when CHK_POP_SECOND =>
sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ;
--------------------------------------------
when ERROR_TRAP =>
sig_cmdcntl_sm_state_ns <= ERROR_TRAP ;
--------------------------------------------
when others =>
sig_cmdcntl_sm_state_ns <= INIT;
end case;
end process CMDCNTL_SM_COMBINATIONAL;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMDCNTL_SM_REGISTERED
--
-- Process Description:
-- Command Controller State Machine registered implementation
--
-------------------------------------------------------------
CMDCNTL_SM_REGISTERED : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_cmdcntl_sm_state <= INIT;
sig_sm_ld_dre_cmd <= '0' ;
sig_sm_ld_scatter_cmd <= '0' ;
sig_sm_pop_cmd_fifo <= '0' ;
else
sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ;
sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ;
sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ;
sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ;
end if;
end if;
end process CMDCNTL_SM_REGISTERED;
-------------------------------------------------------------------------
-------- DRE Instance and controls
-------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE
--
-- If Generate Description:
-- Includes the instance for the DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate
signal lsig_eop_reg : std_logic := '0';
signal lsig_dre_load_beat : std_logic := '0';
signal lsig_dre_tlast_output_beat : std_logic := '0';
signal lsig_set_eop : std_logic := '0';
signal lsig_tlast_err_reg1 : std_logic := '0';
signal lsig_tlast_err_reg2 : std_logic := '0';
signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pushreg_full : std_logic := '0';
signal lsig_pushreg_empty : std_logic := '0';
signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal lsig_pullreg_full : std_logic := '0';
signal lsig_pullreg_empty : std_logic := '0';
signal lsig_pull_new_offset : std_logic := '0';
signal lsig_push_new_offset : std_logic := '0';
begin
------------------------------------------------------------
-- Instance: I_S2MM_DRE_BLOCK
--
-- Description:
-- Instance for the S2MM Data Realignment Engine (DRE)
--
------------------------------------------------------------
I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1.axi_datamover_s2mm_dre
generic map (
C_DWIDTH => C_STREAM_DWIDTH ,
C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH
)
port map (
-- Clock and Reset
dre_clk => primary_aclk ,
dre_rst => mmap_reset ,
-- Alignment Control (Independent from Stream Input timing)
dre_align_ready => sig_dre_align_ready ,
dre_align_valid => sig_sm_ld_dre_cmd ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_scatter2dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
-- Flush Control (Aligned to input Stream timing)
dre_flush => sig_scatter2dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_scatter2dre_tstrb ,
dre_in_tdata => sig_scatter2dre_tdata ,
dre_in_tlast => sig_scatter2dre_tlast ,
dre_in_tvalid => sig_scatter2dre_tvalid ,
dre_in_tready => sig_dre2scatter_tready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2wdc_tstrb ,
dre_out_tdata => sig_dre2wdc_tdata ,
dre_out_tlast => sig_dre2wdc_tlast ,
dre_out_tvalid => sig_dre2wdc_tvalid ,
dre_out_tready => sig_wdc2dre_tready
);
lsig_dre_load_beat <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready;
lsig_set_eop <= sig_scatter2drc_eop and
lsig_dre_load_beat ;
lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and
sig_wdc2dre_tready and
sig_dre2wdc_tlast;
dre2wdc_eop <= lsig_dre_tlast_output_beat and
lsig_eop_reg;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG
--
-- Process Description:
-- Implements a flop for holding the EOP from the Scatter
-- Engine until the corresponding packet clears out of the DRE.
-- THis is used to transfer the EOP marker to the DRE output
-- stream without the need for the DRE to pass it through.
--
-------------------------------------------------------------
IMP_EOP_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(lsig_dre_tlast_output_beat = '1' and
lsig_set_eop = '0')) then
lsig_eop_reg <= '0';
elsif (lsig_set_eop = '1') then
lsig_eop_reg <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_EOP_REG;
-- Delay TLAST Error by 2 clocks to compensate for DRE minimum
-- delay of 2 clocks for the stream data.
sig_tlast_err0r <= lsig_tlast_err_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_DELAY
--
-- Process Description:
-- Implements a 2 clock delay to better align the TLAST
-- error detection with the Stream output data to the WDC
-- which has a minimum 2 clock delay through the DRE.
--
-------------------------------------------------------------
IMP_TLAST_ERR_DELAY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_tlast_err_reg1 <= '0';
lsig_tlast_err_reg2 <= '0';
else
lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error;
lsig_tlast_err_reg2 <= lsig_tlast_err_reg1;
end if;
end if;
end process IMP_TLAST_ERR_DELAY;
-------------------------------------------------------------------------
-- Store and Forward Start Address Offset Registers Logic
-- Push-pull register is used to to time align the starting address
-- offset (ripped from the Realigner command via parsing) to DRE
-- TLAST output timing. The offset output of the pull register must
-- be valid on the first output databeat of the DRE to the Store and
-- Forward module.
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg;
-- lsig_push_new_offset <= sig_dre_align_ready and
-- sig_gated_dre_align_valid ;
lsig_push_new_offset <= sig_sm_ld_dre_cmd ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the input register for holding the starting address
-- offset sent to the external Store and Forward functions.
--
-------------------------------------------------------------
IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
elsif (lsig_push_new_offset = '1') then
lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg;
lsig_pushreg_full <= '1';
lsig_pushreg_empty <= '0';
elsif (lsig_pull_new_offset = '1') then
lsig_push_strt_offset_reg <= (others => '0');
lsig_pushreg_full <= '0';
lsig_pushreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PUSH_STRT_OFFSET_REG;
-- Pull the next offset (if one exists) into the pull register
-- when the DRE outputs a TLAST. If the pull register is empty
-- and the push register has an offset, then push the new value
-- into the pull register.
lsig_pull_new_offset <= (sig_dre2wdc_tlast and
sig_dre2wdc_tvalid and
sig_wdc2dre_tready) or
(lsig_pushreg_full and
lsig_pullreg_empty);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PULL_STRT_OFFSET_REG
--
-- Process Description:
-- Implements the output register for holding the starting
-- address offset sent to the Store and Forward modul's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_PULL_STRT_OFFSET_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '1') then
lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg;
lsig_pullreg_full <= '1';
lsig_pullreg_empty <= '0';
elsif (lsig_pull_new_offset = '1' and
lsig_pushreg_full = '0') then
lsig_pull_strt_offset_reg <= (others => '0');
lsig_pullreg_full <= '0';
lsig_pullreg_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PULL_STRT_OFFSET_REG;
end generate GEN_INCLUDE_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_DRE
--
-- If Generate Description:
-- Omits the DRE from the Re-aligner.
--
--
------------------------------------------------------------
GEN_OMIT_DRE : if (OMIT_DRE) generate
begin
-- DRE always ready
sig_dre_align_ready <= '1';
-- -- Let the Scatter engine control the Realigner command
-- -- flow.
-- sig_dre_align_ready <= sig_scatter2drc_cmd_ready;
-- Pass through signal connections
sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ;
sig_dre2wdc_tdata <= sig_scatter2dre_tdata ;
sig_dre2wdc_tlast <= sig_scatter2dre_tlast ;
sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ;
sig_dre2scatter_tready <= sig_wdc2dre_tready ;
dre2wdc_eop <= sig_scatter2drc_eop ;
-- Just pass TLAST Error through when no DRE is present
sig_tlast_err0r <= sig_scatter2all_tlast_error;
-------------------------------------------------------------------------
-------- Store and Forward Start Address Offset Register Logic
-------------------------------------------------------------------------
sig_dre2sf_strt_offset <= sig_output_strt_offset_reg;
sig_ld_strt_offset <= sig_sm_ld_dre_cmd;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STRT_OFFSET_OUTPUT
--
-- Process Description:
-- Implements the register for holding the starting address
-- offset sent to the S2MM Store and Forward module's upsizer
-- logic.
--
-------------------------------------------------------------
IMP_STRT_OFFSET_OUTPUT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_output_strt_offset_reg <= (others => '0');
elsif (sig_ld_strt_offset = '1') then
sig_output_strt_offset_reg <= sig_curr_strt_offset_reg;
else
null; -- Hold Current State
end if;
end if;
end process IMP_STRT_OFFSET_OUTPUT;
end generate GEN_OMIT_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SCATTER
--
-- If Generate Description:
-- This IfGen implements the Scatter function which is a pre-
-- processor for the S2MM DRE. The scatter function breaks up
-- a continous input stream of data into constituant parts
-- as described by a set of loaded commands that together
-- describe an entire input packet.
--
------------------------------------------------------------
GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate
begin
-- Load the Scatter Engine command when the DRE command
-- is loaded
-- sig_drc2scatter_push_cmd <= sig_dre_align_ready and
-- sig_gated_dre_align_valid;
sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ;
-- Assign the new Bytes to Transfer (BTT) qualifier for the
-- Scatter Engine
sig_drc2scatter_btt <= sig_curr_btt_reg;
-- Assign the new End of Frame (EOF) qualifier for the
-- Scatter Engine
sig_drc2scatter_eof <= sig_curr_eof_reg;
------------------------------------------------------------
-- Instance: I_S2MM_SCATTER
--
-- Description:
-- Instance for the Scatter Engine. This block breaks up a
-- input stream per commands loaded.
--
------------------------------------------------------------
I_S2MM_SCATTER : entity axi_datamover_v5_1.axi_datamover_s2mm_scatter
generic map (
C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT ,
C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_BTT_USED => BTT_WIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input & Reset input
primary_aclk => primary_aclk ,
mmap_reset => mmap_reset ,
-- DRE Realign Controller I/O ----------------------------
scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready ,
drc2scatter_push_cmd => sig_drc2scatter_push_cmd ,
drc2scatter_btt => sig_drc2scatter_btt ,
drc2scatter_eof => sig_drc2scatter_eof ,
-- DRE Source Alignment -----------------------------------
scatter2drc_src_align => sig_scatter2dre_src_align ,
-- AXI Slave Stream In -----------------------------------
s2mm_strm_tready => sig_scatter2strm_tready ,
s2mm_strm_tvalid => sig_strm2scatter_tvalid ,
s2mm_strm_tdata => sig_strm2scatter_tdata ,
s2mm_strm_tstrb => sig_strm2scatter_tstrb ,
s2mm_strm_tlast => sig_strm2scatter_tlast ,
-- Stream Out to S2MM DRE ---------------------------------
drc2scatter_tready => sig_dre2scatter_tready ,
scatter2drc_tvalid => sig_scatter2dre_tvalid ,
scatter2drc_tdata => sig_scatter2dre_tdata ,
scatter2drc_tstrb => sig_scatter2dre_tstrb ,
scatter2drc_tlast => sig_scatter2dre_tlast ,
scatter2drc_flush => sig_scatter2dre_flush ,
scatter2drc_eop => sig_scatter2drc_eop ,
-- Premature TLAST assertion error flag
scatter2drc_tlast_error => sig_scatter2all_tlast_error
);
end generate GEN_INCLUDE_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SCATTER
--
-- If Generate Description:
-- This IfGen omits the Scatter pre-processor.
--
--
------------------------------------------------------------
GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate
begin
-- Just housekeep the signaling
sig_scatter2drc_cmd_ready <= '1' ;
sig_scatter2drc_eop <= sig_strm2scatter_tlast ;
sig_scatter2dre_src_align <= sig_dre_src_align ;
sig_scatter2all_tlast_error <= '0' ;
sig_scatter2dre_flush <= sig_dre_flush ;
sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ;
sig_scatter2dre_tdata <= sig_strm2scatter_tdata ;
sig_scatter2dre_tlast <= sig_strm2scatter_tlast ;
sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ;
sig_scatter2strm_tready <= sig_dre2scatter_tready ;
end generate GEN_OMIT_SCATTER;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omit and special logic for Indeterminate BTT support.
--
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Include logic for the case when Indeterminate BTT is
-- included as part of the S2MM. In this mode, the actual
-- length of input stream packets is not known when the S2MM
-- is loaded with a transfer command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
signal lsig_clr_cmd_flush : std_logic := '0';
signal lsig_set_cmd_flush : std_logic := '0';
signal lsig_cmd_set_fetch_pause : std_logic := '0';
signal lsig_cmd_clr_fetch_pause : std_logic := '0';
signal lsig_cmd_fetch_pause : std_logic := '0';
begin
lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and
not(sig_curr_cmd_cmplt_reg) and
not(sig_need_cmd_flush);
lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2dre_tlast;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FETCH_PAUSE
--
-- Process Description:
-- Implements the flop for the flag that causes the command
-- queue manager to pause fetching the next command if the
-- current command does not have the command complete bit set.
-- The pause remains set until the associated TLAST for the
-- command is output from the Scatter Engine. If the Tlast is
-- also accompanied by a EOP and the pause is set, then the
-- ensuing command (which will have the cmd cmplt bit set) must
-- be flushed from the queue and not loaded into the Scatter
-- Engine or DRE, This is normally associated with indeterminate
-- packets that are actually shorter than the intial align to
-- max burst child command sent to the Realigner, The next loaded
-- child command is to finish the remainder of the indeterminate
-- packet up to the full BTT value in the original parent command.
-- This child command becomes stranded in the Realigner command fifo
-- and has to be flushed.
--
-------------------------------------------------------------
IMP_CMD_FETCH_PAUSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_cmd_clr_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '0';
elsif (lsig_cmd_set_fetch_pause = '1') then
lsig_cmd_fetch_pause <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FETCH_PAUSE;
-- Clear the flush needed flag when the command with the command
-- complete marker is popped off of the command queue.
lsig_clr_cmd_flush <= sig_need_cmd_flush and
sig_sm_pop_cmd_fifo;
-- The command queue has to be flushed if the stream EOP marker
-- is transfered out of the Scatter Engine when the corresponding
-- command being executed does not have the command complete
-- marker set.
lsig_set_cmd_flush <= lsig_cmd_fetch_pause and
sig_scatter2dre_tvalid and
sig_dre2scatter_tready and
sig_scatter2drc_eop;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_FLUSH_FLOP
--
-- Process Description:
-- Implements the flop for holding the command flush flag.
-- This is only needed in Indeterminate BTT mode.
--
-------------------------------------------------------------
IMP_CMD_FLUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_cmd_flush = '1') then
sig_need_cmd_flush <= '0';
elsif (lsig_set_cmd_flush = '1') then
sig_need_cmd_flush <= '1';
else
null; -- Hold current state
end if;
end if;
end process IMP_CMD_FLUSH_FLOP;
end generate GEN_ENABLE_INDET_BTT;
end implementation;
| bsd-2-clause | 451dce0dfee38c5f462c9396d6362faf | 0.42958 | 4.885623 | false | false | false | false |
niketancm/tsea26 | lab2-3/rtl/mac_dp.vhd | 1 | 8,226 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mac_dp is
port (
clk_i : in std_logic;
reset_i : in std_logic;
c_scalefactor : in std_logic_vector(2 downto 0);
c_macop : in std_logic_vector(3 downto 0);
c_dosat : in std_logic;
mac_operanda : in signed(39 downto 0); -- From ACR/RF
mac_operandb : in signed(39 downto 0); -- From ACR/RF
mul_opa_reg : in signed(16 downto 0); -- From multiplier
mul_opb_reg : in signed(16 downto 0); -- From multiplier
scale_overflow : out std_logic;
sat_flag : out std_logic; -- 1 if data was saturated
mac_result : out signed(39 downto 0); -- macunit output data
add_pos_overflow : out std_logic; -- positive overflow
add_neg_overflow : out std_logic); -- negative overflow
end mac_dp;
architecture mac_dp_rtl of mac_dp is
signal mul_sig : signed(33 downto 0);
signal adder_opb, adder_opa, to_scaling, adder_result, mul_guarded_reg,
abs_result, round_result, from_scaling : signed(39 downto 0);
signal adder_cin : std_logic;
signal add_pos_overflow1, add_pos_overflow2 : std_logic;
signal add_neg_overflow1, add_neg_overflow2 : std_logic;
signal c_invopb, c_opbsel : std_logic_vector(1 downto 0);
signal c_opasel : std_logic_vector(2 downto 0);
signal tmp, tmp2 : signed(40 downto 0);
component mac_scale
port (
scale_overflow : out std_logic;
from_scaling : out signed(39 downto 0);
to_scaling : in signed(39 downto 0);
c_scalefactor : in std_logic_vector(2 downto 0));
end component;
component saturation
port (
value_i : in signed(39 downto 0);
do_sat_i : in std_logic;
value_o : out signed(39 downto 0);
did_sat_o : out std_logic);
end component;
begin -- behav
-- purpose: Control table for the MAC
-- type : combinational
ctrl_table: process (c_macop)
begin -- process ctrl_table
case c_macop is
-----------------------------------------------------------------------------------------------------
when "0000" => c_invopb <= "00"; c_opasel <= "000"; c_opbsel <= "00"; -- CLR
when "0001" => c_invopb <= "00"; c_opasel <= "001"; c_opbsel <= "01"; -- ADD
when "0010" => c_invopb <= "01"; c_opasel <= "001"; c_opbsel <= "01"; -- SUB
when "0011" => c_invopb <= "01"; c_opasel <= "001"; c_opbsel <= "01"; -- CMP
when "0100" => c_invopb <= "01"; c_opasel <= "000"; c_opbsel <= "01"; -- NEG
-----------------------------------------------------------------------------------------------------
--We use c_inopb = "10". to select the msb of macoperandb, and add or subract depending upon it is negative or not.
when "0101" => c_invopb <= "10"; c_opasel <= "000"; c_opbsel <= "01"; -- ABS
-----------------------------------------------------------------------------------------------------
when "0110" => c_invopb <= "00"; c_opasel <= "000"; c_opbsel <= "10"; -- MUL
when "0111" => c_invopb <= "00"; c_opasel <= "001"; c_opbsel <= "10"; -- MAC
when "1000" => c_invopb <= "01"; c_opasel <= "001"; c_opbsel <= "10"; -- MDM
-----------------------------------------------------------------------------------------------------
when "1001" => c_invopb <= "00"; c_opasel <= "000"; c_opbsel <= "01"; -- MOVE
--This is for the round operation, where we add X"8000" to the mac_operandb
when "1010" => c_invopb <= "00"; c_opasel <= "010"; c_opbsel <= "01"; -- MOVE_ROUND
-----------------------------------------------------------------------------------------------------
when others => c_invopb <= "00"; c_opasel <= "000"; c_opbsel <= "00"; -- NOP
-----------------------------------------------------------------------------------------------------
end case;
end process ctrl_table;
-- Operation descriptions
-- CLR: mac_result = 0
-- ADD: mac_result = mac_operanda + mac_operandb
-- SUB: mac_result = mac_operanda - mac_operandb
-- CMP: mac_result = mac_operanda - mac_operandb
-- NEG: mac_result = 0 - mac_operandb
-- ABS: mac_result = abs(mac_operandb)
-- MUL: mac_result = mul_opa * mul_opb
-- MAC: mac_result = mac_operanda + mul_opa * mul_opb
-- MDM: mac_result = mac_operanda - mul_opa * mul_opb
-- MOVE: mac_result = mac_operandb
-- MOVE_ROUND: mac_result = round(mac_operandb)
-- NOP: mac_result = 0
-----------------------------------------------------------------------------
-- Multiplier
mul_sig <= mul_opa_reg * mul_opb_reg;
-- purpose: Pipeline stage for the multiplier result
-- type : sequential
mulpipe: process (clk_i)
begin -- process mulpipe
if rising_edge(clk_i) then
if reset_i = '0' then
mul_guarded_reg <= (others => '0');
else
mul_guarded_reg <= (39 downto 34 => mul_sig(33)) & mul_sig;
end if;
end if;
end process mulpipe;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Create OpA to adder
with c_opasel select
adder_opa <=
(others => '0') when "000",
mac_operanda when "001",
x"0000008000" when others; --for rounding operation
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Create OpB temporary value before scaling
with c_opbsel select
to_scaling <=
(others => '0') when "00",
mac_operandb when "01",
mul_guarded_reg when others;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Scaling stuff
scaling : mac_scale
port map (scale_overflow => scale_overflow,
from_scaling => from_scaling,
to_scaling => to_scaling,
c_scalefactor => c_scalefactor);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Invert OpB if necessary
with c_invopb select
adder_cin <=
'0' when "00",
'1' when "01",
mac_operandb(39) when others; --for abs operation.depending upon the
--msb we add the number or its 2's complement.
--
with adder_cin select
adder_opb <=
from_scaling when '0',
not from_scaling when others;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- The adder itself
tmp <= adder_opa + adder_opb + ((40 downto 1 => '0') & adder_cin);
adder_result <= tmp(39 downto 0);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Create some overflow flag related signals
add_pos_overflow1 <= (not adder_opa(39) and not adder_opb(39) and adder_result(39));
--To determine the overflow for the abs operation.
add_pos_overflow2 <= '1' when ((c_opasel = "010") and (abs_result = x"7fffffffff")) else '0';
add_pos_overflow <= add_pos_overflow1 or add_pos_overflow2;
add_neg_overflow1 <= (adder_opa(39) and adder_opb(39) and not adder_result(39));
--To determine the overflow for rounding operation.
add_neg_overflow2 <= '1' when ((c_invopb = "10") and (adder_result = x"8000000000")) else '0';
add_neg_overflow <= add_neg_overflow1 or add_neg_overflow2;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Saturation handling is done in a separate module that you need to edit!
sat_box : saturation port map (
value_i => adder_result,
do_sat_i => c_dosat,
value_o => mac_result,
did_sat_o => sat_flag);
-----------------------------------------------------------------------------
end architecture mac_dp_rtl;
| gpl-2.0 | 7a8a9267836e0e0c3fc2e1aee9be1965 | 0.457938 | 3.96052 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_top.vhd | 2 | 71,839 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | cd33048ca732804f971ab8ec1b2c6eab | 0.95238 | 1.820599 | false | false | false | false |
okaxaki/vm2413 | SlotCounter.vhd | 2 | 904 | --
-- SlotCounter.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity SlotCounter is
generic (
DELAY : integer range 0 to MAXSLOT*4-1
);
port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : out SLOT_TYPE;
stage : out STAGE_TYPE
);
end SlotCounter;
architecture RTL of SlotCounter is
begin
process(clk, reset)
variable count : integer range 0 to MAXSLOT*4-1;
begin
if reset = '1' then
count := MAXSLOT*4-1-DELAY;
elsif clk'event and clk='1' then if clkena ='1' then
if count = MAXSLOT*4-1 then
count := 0;
else
count := count + 1;
end if;
slot <= count/4;
stage <= count mod 4;
end if; end if;
end process;
end RTL;
| mit | 80bea0ae1317fc4abb434b865d5097e0 | 0.54646 | 3.424242 | false | false | false | false |
kjellhar/axi_mmc | src/vhdl/mmc_dat_if.vhd | 1 | 8,080 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/03/2014 02:00:27 PM
-- Design Name:
-- Module Name: mmc_dat_if - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mmc_dat_if is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
receive_dat_trigger_i : in std_logic;
transmit_dat_trigger_i : in std_logic;
dat_block_finished_o : out std_logic;
bus_width_i : in std_logic_vector (1 downto 0);
data_fifo_out_i : in std_logic_vector (31 downto 0);
data_fifo_out_wr_i : in std_logic;
data_fifo_out_full_o : out std_logic;
data_fifo_in_o : out std_logic_vector (31 downto 0);
data_fifo_in_rd_i : in std_logic;
data_fifo_in_empty_o : out std_logic;
dat_out_o : out std_logic_vector (7 downto 0);
dat_in_i : in std_logic_vector (7 downto 0)
);
end mmc_dat_if;
architecture rtl of mmc_dat_if is
COMPONENT mmc_dat_fifo
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
component mmc_crc16 is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
enable : in std_logic;
serial_in : in std_logic;
crc16_out : out std_logic_vector (15 downto 0)
);
end component;
type block_state_t is (
IDLE,
RX_START_BIT,
RX_DATA_BLOCK,
RX_CRC1,
RX_CRC2,
TX_START_BIT,
TX_DATA_BLOCK,
TX_CRC1,
TX_CRC2
);
signal block_state : block_state_t := IDLE;
signal next_block_state : block_state_t;
signal byte_counter : integer range 0 to 511 := 0;
signal bit_counter : integer range 0 to 31 := 31;
signal shift_en : std_logic := '0';
signal data_fifo_out_rd_en : std_logic := '0';
signal data_fifo_out_dout : std_logic_vector (31 downto 0);
signal data_fifo_out_empty : std_logic;
signal data_fifo_out_count : std_logic_vector (9 downto 0);
signal data_fifo_in_din : std_logic_vector (31 downto 0);
signal data_fifo_in_wr_en : std_logic;
signal data_fifo_out_full : std_logic;
signal data_fifo_in_count : std_logic_vector (9 downto 0);
signal crc16_clear : std_logic;
signal crc16_en : std_logic;
signal crc16_serial_in : std_logic;
signal crc16 : std_logic_vector (15 downto 0);
signal dat0_shiftreg : std_logic_vector (31 downto 0) := (others => '1');
signal dat0_word : std_logic_vector (31 downto 0);
begin
dat_out_o(0) <= dat0_shiftreg(31);
dat_out_o(7 downto 1) <= "1111111";
dat0_word <= data_fifo_out_dout (7 downto 0) &
data_fifo_out_dout (15 downto 8) &
data_fifo_out_dout (23 downto 16) &
data_fifo_out_dout (31 downto 24);
data_fifo_in_din <= dat0_shiftreg (7 downto 1) & dat_in_i(0) &
dat0_shiftreg (15 downto 8) &
dat0_shiftreg (23 downto 16) &
dat0_shiftreg (31 downto 24);
-- 8bit shift register (DAT0)
process
begin
wait until rising_edge(clk) and shift_en='1';
data_fifo_out_rd_en <= '0';
data_fifo_in_wr_en <= '0';
if bit_counter=31 then
bit_counter <= bit_counter - 1;
if block_state=RX_DATA_BLOCK then
dat0_shiftreg <= dat0_shiftreg (30 downto 0) & dat_in_i(0);
else
dat0_shiftreg <= dat0_word;
data_fifo_out_rd_en <= '1';
end if;
elsif bit_counter /= 0 then
bit_counter <= bit_counter - 1;
dat0_shiftreg <= dat0_shiftreg (30 downto 0) & dat_in_i(0);
elsif bit_counter = 0 then
bit_counter <= 31;
dat0_shiftreg <= dat0_shiftreg (30 downto 0) & dat_in_i(0);
if block_state=RX_DATA_BLOCK then
data_fifo_in_wr_en <= '1';
end if;
end if;
end process;
-- block control module
process
begin
wait until rising_edge(clk) and clk_en='1';
if reset='1' then
block_state <= IDLE;
else
block_state <= next_block_state;
end if;
end process;
process (block_state, transmit_dat_trigger_i, receive_dat_trigger_i, dat_in_i, byte_counter)
begin
next_block_state <= block_state;
case block_state is
when IDLE =>
if transmit_dat_trigger_i='1' then
next_block_state <= TX_START_BIT;
elsif receive_dat_trigger_i='1' then
next_block_state <= RX_START_BIT;
end if;
when RX_START_BIT =>
if dat_in_i(0)='0' then
next_block_state <= RX_DATA_BLOCK;
end if;
when RX_DATA_BLOCK =>
if byte_counter=511 then
next_block_state <= RX_CRC1;
end if;
when RX_CRC1 =>
next_block_state <= RX_CRC2;
when RX_CRC2 =>
next_block_state <= IDLE;
when TX_START_BIT =>
next_block_state <= TX_DATA_BLOCK;
when TX_DATA_BLOCK =>
if byte_counter=511 then
next_block_state <= TX_CRC1;
end if;
when TX_CRC1 =>
next_block_state <= TX_CRC2;
when TX_CRC2 =>
next_block_state <= IDLE;
when others =>
end case;
end process;
mmc_dat_out_fifo : mmc_dat_fifo
PORT MAP (
clk => clk,
srst => reset,
din => data_fifo_out_i,
wr_en => data_fifo_out_wr_i,
rd_en => data_fifo_out_rd_en,
dout => data_fifo_out_dout,
full => data_fifo_out_full_o,
empty => data_fifo_out_empty,
data_count => data_fifo_out_count
);
mmc_dat_in_fifo : mmc_dat_fifo
PORT MAP (
clk => clk,
srst => reset,
din => data_fifo_in_din,
wr_en => data_fifo_in_wr_en,
rd_en => data_fifo_in_rd_i,
dout => data_fifo_in_o,
full => data_fifo_out_full,
empty => data_fifo_in_empty_o,
data_count => data_fifo_in_count
);
u_mmc_crc16 : mmc_crc16
Port map (
clk => clk,
clk_en => clk_en,
reset => crc16_clear,
enable => crc16_en,
serial_in => crc16_serial_in,
crc16_out => crc16
);
end rtl;
| mit | dfa1ecdb14e2225b2d61f89f2518f126 | 0.480941 | 3.833017 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_035_test_input.fixed_compact_alignment_false.vhd | 1 | 746 |
architecture RTL of FIFO is
begin
process
begin
a <= b; -- Comment
ab <= xy; -- Comment
-- Check for something
if (a = b) then
z <= y; -- Assign this statement
-- Check for this other thing
elsif (a + b -c = z) then
z <= x; -- Assign this other statement
end if;
end process;
-- Violations below
process
begin
a <= b; -- Comment
ab <= xy; -- Comment
-- Check for something
if (a = b) then
z <= y; -- Assign this statement
-- Check for this other thing
elsif (a + b -c = z) then
z <= x; -- Assign this other statement
end if;
end process;
end architecture RTL;
| gpl-3.0 | 8b23d7e04aaf599d02f0463ca9825f7a | 0.494638 | 4.076503 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/graphicsaccelerator/VGA_Top.fixed.vhd | 1 | 6,658 | library IEEE;
use ieee.std_logic_1164.all;
entity VGA_TOP is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
CLK : in std_logic;
HS : out std_logic;
VS : out std_logic;
BUTTON : in std_logic;
RESET : in std_logic;
LED : out std_logic;
ENABLES : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(6 downto 0);
INCOLOR : in std_logic_vector(2 downto 0);
MOVEUP : in std_logic;
MOVEDOWN : in std_logic;
MOVELEFT : in std_logic;
MOVERIGHT : in std_logic;
MOVEP1 : in std_logic;
MOVEP2 : in std_logic
);
end entity VGA_TOP;
architecture BEHAVIORAL of VGA_TOP is
component DEBOUNCER is
port (
CLK : in std_logic;
BUTTON : in std_logic;
DOUT : out std_logic
);
end component;
component BRESENHAMER is
port (
X1 : in std_logic_vector(9 downto 0);
Y1 : in std_logic_vector(8 downto 0);
X2 : in std_logic_vector(9 downto 0);
Y2 : in std_logic_vector(8 downto 0);
CLK : in std_logic;
STARTDRAW : in std_logic;
WRITEENABLE : out std_logic;
SS : out std_logic_vector(3 downto 0);
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(8 downto 0);
RESET : in std_logic
);
end component;
component SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in std_logic;
DATAIN : in std_logic_vector(2 downto 0);
ADDRESSX : out std_logic_vector(9 downto 0);
ADDRESSY : out std_logic_vector(8 downto 0)
);
end component;
component FRAMEBUFFER is
port (
INX : in std_logic_vector(9 downto 0);
INY : in std_logic_vector(8 downto 0);
OUTX : in std_logic_vector(9 downto 0);
OUTY : in std_logic_vector(8 downto 0);
OUTCOLOR : out std_logic_vector(2 downto 0);
INCOLOR : in std_logic_vector(2 downto 0);
BUFFERWRITE : in std_logic;
CLK : in std_logic
);
end component;
component SEVENSEGMENT is
port (
CLK : in std_logic;
DATA : in std_logic_vector(15 downto 0);
ENABLES : out std_logic_vector(3 downto 0);
SEGMENTS : out std_logic_vector(6 downto 0)
);
end component;
component POINTER is
generic (
INITX : std_logic_vector(9 downto 0);
INITY : std_logic_vector(8 downto 0)
);
port (
MOVEUP : in std_logic;
MOVEDOWN : in std_logic;
MOVELEFT : in std_logic;
MOVERIGHT : in std_logic;
MOVE : in std_logic;
CLK : in std_logic;
X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(8 downto 0);
SYNCX : in std_logic_vector(9 downto 0);
SYNCY : in std_logic_vector(8 downto 0);
HERE : out std_logic
);
end component;
component FREQDIV is
port (
CLK : in std_logic;
CLK2 : out std_logic
);
end component;
signal adx, gpu_x : std_logic_vector(9 downto 0);
signal ady, gpu_y : std_logic_vector(8 downto 0);
signal data : std_logic_vector(2 downto 0);
signal gim : std_logic_vector(22 downto 0);
signal gpu_color_to_buffer : std_logic_vector(2 downto 0);
signal bufferwrite : std_logic;
signal dout : std_logic;
signal ss : std_logic_vector(3 downto 0);
signal clk2 : std_logic;
signal p1region, p2region : std_logic;
signal rt : std_logic;
signal gt : std_logic;
signal bt : std_logic;
signal x1, x2 : std_logic_vector(9 downto 0);
signal y1, y2 : std_logic_vector(8 downto 0);
begin
INS_FRAMEBUFFER : FRAMEBUFFER
port map (
INX => gpu_x,
INY => gpu_y,
OUTX => adx,
OUTY => ady,
OUTCOLOR => data,
INCOLOR => INCOLOR,
BUFFERWRITE => bufferwrite,
CLK => CLK
);
INS_SYNCHRONIZER : SYNCHRONIZER
port map (
R => rt,
G => gt,
B => bt,
HS => HS,
VS => VS,
CLK => CLK,
DATAIN => data,
ADDRESSX => adx,
ADDRESSY => ady
);
INST_DEBOUNCER : DEBOUNCER
port map (
CLK => CLK,
BUTTON => BUTTON,
DOUT => dout
);
INST_BRESENHAMER : BRESENHAMER
port map (
WRITEENABLE => bufferwrite,
X => gpu_x,
Y => gpu_y,
X1 => x1,
Y1 => y1,
X2 => x2,
Y2 => y2,
CLK => CLK,
SS => ss,
RESET => RESET,
STARTDRAW => dout
);
LED <= bufferwrite;
R <= rt when (p1region='0' and p2region='0') else
not rt;
G <= gt when (p1region='0' and p2region='0') else
not gt;
B <= bt when (p1region='0' and p2region='0') else
not bt;
INST_SEVENSEGMENT : SEVENSEGMENT
port map (
CLK => CLK,
ENABLES => ENABLES,
SEGMENTS => SEGMENTS,
DATA(3 downto 0) => ss,
DATA(15 downto 4) => "000000000000"
);
INST_POINTER1 : POINTER
generic map (
INITX => "0000000100",
INITY => "011110000"
)
port map (
MOVEUP => MOVEUP,
MOVEDOWN => MOVEDOWN,
MOVELEFT => MOVELEFT,
MOVERIGHT => MOVERIGHT,
MOVE => MOVEP1,
CLK => clk2,
HERE => p1region,
X => x1,
Y => y1,
SYNCX => adx,
SYNCY => ady
);
INST_FREQDIV : FREQDIV
port map (
CLK => CLK,
CLK2 => clk2
);
INST_POINTER2 : POINTER
generic map (
INITX => "1001111000",
INITY => "011110000"
)
port map (
MOVEUP => MOVEUP,
MOVEDOWN => MOVEDOWN,
MOVELEFT => MOVELEFT,
MOVERIGHT => MOVERIGHT,
MOVE => MOVEP2,
CLK => clk2,
HERE => p2region,
X => x2,
Y => y2,
SYNCX => adx,
SYNCY => ady
);
end architecture BEHAVIORAL;
| gpl-3.0 | c05c8aacf361299c762c5c3c7386a5aa | 0.482427 | 3.462298 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/comment/comment_process_test_input.vhd | 1 | 811 |
architecture ARCH of ENTITY is
begin
-- comment
-- comment
-- comment
PROC_1 : process (a) is
-- comment
-- comment
begin
-- comment
a <= b; -- comment
b <= c; -- comment
d <= e; -- comment
end process PROC_1;
PROC_1 : process (a) is
-- comment
-- comment
begin
-- comment
a <= b; -- comment
b <= c; -- comment
d <= e; -- comment
end process PROC_1;
PROC_1 : process (a) is
variable a : integer 0 to 10; -- comment
variable b : natural 0 to 256; -- comment
begin
-- comment
a <= b; -- comment
b <= c; -- comment
d <= e; -- comment
end process PROC_1;
end architecture ARCH;
| gpl-3.0 | e3d4ecf48e06366d02469c58ce5eb929 | 0.447596 | 4.075377 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/concurrent_simple_signal_assignment/classification_test_input.vhd | 1 | 957 |
architecture RTL of FIFO is
begin
-- Simple form
a <= b;
-- with guarded
a <= guarded b;
-- with transport delay mechanism
a <= transport b;
-- with inertial delay machanism
a <= inertial b;
-- with reject delay mechanism
a <= reject 10 ns inertial b;
-- with guarded and transport delay mechanism
a <= guarded transport b;
-- with guarded and inertial delay machanism
a <= guarded inertial b;
-- with guarded and reject delay mechanism
a <= guarded reject 10 ns inertial b;
-- test unary operators
a <= (others => func(and b, or b, nand b, or b, nor b, xnor b));
a <= (others => func(nand b));
a <= (others => func(or b));
a <= (others => func(nor b));
a <= (others => func(xor b));
a <= (others => func(xnor b));
U_FIFO : entity something.somethingelse
generic map (
G_FIRST => (blah <= 0),
G_SECOND => 3
)
port map (
I_INPUT => blah2
);
end architecture RTL;
| gpl-3.0 | 09587054340fec8285ec6590e6bcbf83 | 0.599791 | 3.709302 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/ext_mult.vhd | 2 | 22,040 | `protect begin_protected
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`protect end_protected
| mit | 8c1552f86a99b15cc23c69679c02ff02 | 0.938158 | 1.837585 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_013_test_input.vhd | 1 | 592 |
architecture RTL of FIFO is
begin
a <= b and c or d xor e nand f nor g xor h xnor i;
a <= (b) and (c) or (d) xor (e) nand (f) nor (g) xor (h) xnor (i);
-- Violations
a <= b and c or d xor e nand f nor g xor h xnor i;
a <= (b)and(c)or(d)xor(e)nand(f)nor(g)xor(h)xnor(i);
-- Unary operators should be ignored
a <= (others => func(and b, or b, nand b, or b, nor b, xnor b));
a <= (others => func(nand b));
a <= (others => func(or b));
a <= (others => func(nor b));
a <= (others => func(xor b));
a <= (others => func(xnor b));
end architecture RTL;
| gpl-3.0 | 80c0f2a98d6571c9d1b1a8868f434677 | 0.540541 | 2.596491 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_001_test_input.fixed.vhd | 1 | 873 |
architecture RTL of FIFO is
begin
-- These are passing
SIG_LABEL : postponed a <= b;
SIG_LABEL : postponed a <= when c = '0' else '1';
SIG_LABEL : postponed with z select
a <= b when z = "000",
c when z = "001";
-- Failing variations
SIG_LABEL : postponed a <= b;
SIG_LABEL : postponed a <= when c = '0' else '1';
SIG_LABEL : postponed with z select
a <= b when z = "000",
c when z = "001";
-- Remove the labels
postponed a <= b;
postponed a <= when c = '0' else '1';
postponed with z select
a <= b when z = "000",
c when z = "001";
-- Remove the postponed keyword
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
BLOCK_LABEL : block
begin
a <= b;
z <= x;
end block BLOCK_LABEL;
end architecture RTL;
| gpl-3.0 | a2784e80b34d2f5626923ba2aa62c4cf | 0.532646 | 3.437008 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_008_test_input.fixed.vhd | 1 | 1,816 |
architecture RTL of FIFO is
begin
-- These are passing
a <= b; -- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1'; -- Comment 4
-- Failing variations
a <= b; -- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1'; -- Comment 4
process -- comment process
begin -- comment begin
a <= b; -- Comment
b <= c; -- Comment
c <= d; -- Comment
end process; -- comment end process
x <= z when b = c else -- comment a
y when c = d else -- comment b
x when d = e; -- comment c
z <= w when e = f else -- comment d
x when f = g else -- comment e
z; -- comment f
INST : INST_1 -- instantiation comment
port map ( -- port map comment
a => '0' -- port comment
); -- end port map comment
assert True -- assert comment
report "Hello" -- report comment
severity Warning; -- severity comment
procedure_call( -- procedure call comment
a => b, -- procedure call parameter 1
c => d -- procedure call parameter 2
); -- procedure call end parenthesis
-- Block
block_label : block -- Block comment
begin -- block begin comment
a <= b; -- comment z
c <= d; -- comment y
e <= f; -- comment x
end block; -- end block comment
-- Generate statements
for_generate_label : for i in 0 to 200 generate -- for generate comment
ab <= bc; -- comment zz
ac <= ad; -- coment za
ae <= af; -- comment ab
end generate; -- end for generate label
a <= b; -- comment
c <= d; -- comment
-- comment line
s <= a;
-- A
s <= b; -- B
s <= cc; -- C
end architecture RTL;
| gpl-3.0 | 8679a061378a0a51ac456a61c14d83b8 | 0.520374 | 3.839323 | false | false | false | false |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/Datapath.vhd | 1 | 2,286 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use commands.all;
entity Datapath is
port(
enabled : in std_logic;
operation_code : in std_logic_vector(3 downto 0);
operand_1 : in std_logic_vector(7 downto 0);
operand_2 : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0);
zero_flag : out std_logic;
significant_bit_flag : out std_logic
);
end entity Datapath;
architecture Datapath_Behavioural of Datapath is
signal op_result : std_logic_vector(7 downto 0);
signal add_result : std_logic_vector(7 downto 0);
signal sub_result : std_logic_vector(7 downto 0);
signal mov_result : std_logic_vector(7 downto 0);
signal result_zero_flag : std_logic;
signal result_significant_bit_flag : std_logic;
begin
--
-- represents 8-bit adder
--
add_result <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(operand_1) + CONV_INTEGER(operand_2), 8);
--
-- represents 8-bit subtraction
--
sub_result <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(operand_1) - CONV_INTEGER(operand_2), 8);
mov_result <= operand_1;
--
-- synchronous register-accumulator
--
ALU_REG : process(enabled, operation_code, operand_1, operand_2, add_result, sub_result, mov_result)
begin
if (rising_edge(enabled)) then
case operation_code is
when ADD_OP => op_result <= add_result;
when SUB_OP => op_result <= sub_result;
when LOAD_FROM_INEDEX_TO_ADDR_OP | LOAD_FROM_ADDR_TO_INDEX_OP => op_result <= mov_result;
when others => null;
end case;
end if;
end process;
FLAGS_PROCESS : process(op_result)
begin
if op_result = (op_result'range => '0') then
result_zero_flag <= '1';
else
result_zero_flag <= '0';
end if;
if op_result(7) = '1' then
result_significant_bit_flag <= '1';
else
result_significant_bit_flag <= '0';
end if;
end process;
result <= op_result;
zero_flag <= result_zero_flag;
significant_bit_flag <= result_significant_bit_flag;
end architecture Datapath_Behavioural;
| mit | 8af5e70cfb0ef41555e0214914d56847 | 0.614611 | 3.157459 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_bindec.vhd | 2 | 10,218 | `protect begin_protected
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3/w/Vmyn8NjxOg==
`protect end_protected
| bsd-2-clause | 2cf48b95f70aa0fd2654915ab438b5ce | 0.927285 | 1.928288 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_007_test_input.fixed_lower_with_upper_prefix_and_suffix.vhd | 1 | 1,897 |
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32;
PREFIX_generic_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
| gpl-3.0 | a2e72843606ea6fb8b91f4dd4285ee02 | 0.573537 | 3.120066 | false | false | false | false |
Yarr/Yarr-fw | syn/spec/top_yarr_spec_fe65p2.vhd | 1 | 62,889 | --------------------------------------------
-- Project: YARR
-- Author: Timon Heim ([email protected])
-- Description: Top module for YARR on SPEC
-- Dependencies: -
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.board_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity yarr is
port
(
-- On board 20MHz oscillator
clk20_vcxo_i : in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
pll25dac_sync_n : out std_logic; -- 25MHz VCXO
pll20dac_sync_n : out std_logic; -- 20MHz VCXO
plldac_din : out std_logic;
plldac_sclk : out std_logic;
-- From GN4124 Local bus
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
clk_125m_pllref_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
GPIO : out std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-- Font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- DDR3
DDR3_CAS_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_RZQ : inout std_logic;
DDR3_ZIO : inout std_logic;
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_DQ : inout std_logic_vector(15 downto 0);
---------------------------------------------------------
-- FMC
---------------------------------------------------------
DAC_LD : out std_logic;
INJ_SW : out std_logic;
DAC_DIN : out std_logic;
DAC_CLK : out std_logic;
DAC_CS : out std_logic;
TRIGGER_P : out std_logic;
TRIGGER_N : out std_logic;
CLK_DATA_P : out std_logic;
CLK_DATA_N : out std_logic;
RST_0_P : out std_logic;
RST_0_N : out std_logic;
CLK_CNFG_P : out std_logic;
CLK_CNFG_N : out std_logic;
PIX_D_CNFG_P : out std_logic;
PIX_D_CNFG_N : out std_logic;
LD_CNFG_P : out std_logic;
LD_CNFG_N : out std_logic;
CLK_BX_P : out std_logic;
CLK_BX_N : out std_logic;
RST_1_P : out std_logic;
RST_1_N : out std_logic;
EN_PIX_SR_CNFG_P : out std_logic;
EN_PIX_SR_CNFG_N : out std_logic;
SI_CNFG_P : out std_logic;
SI_CNFG_N : out std_logic;
SO_CNFG_P : in std_logic;
SO_CNFG_N : in std_logic;
HIT_OR_P : in std_logic;
HIT_OR_N : in std_logic;
OUT_DATA_P : in std_logic;
OUT_DATA_N : in std_logic;
EXT_4_P : out std_logic;
EXT_4_N : out std_logic;
EXT_3_P : in std_logic;
EXT_3_N : in std_logic;
EXT_2_P : out std_logic;
EXT_2_N : out std_logic;
EXT_1_P : in std_logic;
EXT_1_N : in std_logic;
IO_0 : out std_logic;
IO_1 : in std_logic
);
end yarr;
architecture rtl of yarr is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
COMPONENT fe65p2_addon
PORT(
clk_i : IN std_logic;
rst_n : IN std_logic;
serial_in : IN std_logic;
clk_rx_i : IN std_logic;
clk_bx_o : OUT std_logic;
trig_o : OUT std_logic;
clk_cnfg_o : OUT std_logic;
en_pix_sr_cnfg_o : OUT std_logic;
ld_cnfg_o : OUT std_logic;
si_cnfg_o : OUT std_logic;
pix_d_cnfg_o : OUT std_logic;
clk_data_o : OUT std_logic;
rst_0_o : OUT std_logic;
rst_1_o : OUT std_logic;
dac_sclk_o : OUT std_logic;
dac_sdi_o : OUT std_logic;
dac_ld_o : OUT std_logic;
dac_cs_o : OUT std_logic;
inj_sw_o : OUT std_logic
);
END COMPONENT;
component gn4124_core
port
(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
csr_err_i : in std_logic;
csr_rty_i : in std_logic;
csr_int_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
dma_err_i : in std_logic;
dma_rty_i : in std_logic;
dma_int_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component wb_tx_core
generic (
g_NUM_TX : integer range 1 to 32 := c_TX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- TX
tx_clk_i : in std_logic;
tx_data_o : out std_logic_vector(g_NUM_TX-1 downto 0);
trig_pulse_o : out std_logic;
-- Async
ext_trig_i : in std_logic
);
end component;
component wb_rx_core
generic (
g_NUM_RX : integer range 1 to 32 := c_RX_CHANNELS
);
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- RX IN
rx_clk_i : in std_logic;
rx_serdes_clk_i : in std_logic;
rx_data_i : in std_logic_vector(g_NUM_RX-1 downto 0);
trig_tag_i : in std_logic_vector(31 downto 0);
-- RX OUT (sync to sys_clk)
rx_valid_o : out std_logic;
rx_data_o : out std_logic_vector(31 downto 0);
busy_o : out std_logic;
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_dat_i : in std_logic_vector(31 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(31 downto 0);
rx_valid_i : in std_logic;
-- Status in
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end component;
component i2c_master_wb_top
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl : inout std_logic;
sda : inout std_logic
);
end component;
component wb_trigger_logic
port (
-- Sys connect
wb_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- To/From outside world
ext_trig_i : in std_logic_vector(3 downto 0);
ext_trig_o : out std_logic;
ext_busy_i : in std_logic;
ext_busy_o : out std_logic;
-- Eudet TLU
eudet_clk_o : out std_logic;
eudet_busy_o : out std_logic;
eudet_trig_i : in std_logic;
eudet_rst_i : in std_logic;
-- To/From inside world
clk_i : in std_logic;
trig_tag : out std_logic_vector(31 downto 0);
debug_o : out std_logic_vector(31 downto 0)
);
end component;
component ddr3_ctrl
generic(
--! Bank and port size selection
g_BANK_PORT_SELECT : string := "SPEC_BANK3_32B_32B";
--! Core's clock period in ps
g_MEMCLK_PERIOD : integer := 3000;
--! If TRUE, uses Xilinx calibration core (Input term, DQS centering)
g_CALIB_SOFT_IP : string := "TRUE";
--! User ports addresses maping (BANK_ROW_COLUMN or ROW_BANK_COLUMN)
g_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--! Simulation mode
g_SIMULATION : string := "FALSE";
--! DDR3 data port width
g_NUM_DQ_PINS : integer := 16;
--! DDR3 address port width
g_MEM_ADDR_WIDTH : integer := 14;
--! DDR3 bank address width
g_MEM_BANKADDR_WIDTH : integer := 3;
--! Wishbone port 0 data mask size (8-bit granularity)
g_P0_MASK_SIZE : integer := 4;
--! Wishbone port 0 data width
g_P0_DATA_PORT_SIZE : integer := 32;
--! Port 0 byte address width
g_P0_BYTE_ADDR_WIDTH : integer := 30;
--! Wishbone port 1 data mask size (8-bit granularity)
g_P1_MASK_SIZE : integer := 4;
--! Wishbone port 1 data width
g_P1_DATA_PORT_SIZE : integer := 32;
--! Port 1 byte address width
g_P1_BYTE_ADDR_WIDTH : integer := 30
);
port(
----------------------------------------------------------------------------
-- Clock, control and status
----------------------------------------------------------------------------
--! Clock input
clk_i : in std_logic;
--! Reset input (active low)
rst_n_i : in std_logic;
--! Status output
status_o : out std_logic_vector(31 downto 0);
----------------------------------------------------------------------------
-- DDR3 interface
----------------------------------------------------------------------------
--! DDR3 data bus
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
--! DDR3 address bus
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
--! DDR3 bank address
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
--! DDR3 row address strobe
ddr3_ras_n_o : out std_logic;
--! DDR3 column address strobe
ddr3_cas_n_o : out std_logic;
--! DDR3 write enable
ddr3_we_n_o : out std_logic;
--! DDR3 on-die termination
ddr3_odt_o : out std_logic;
--! DDR3 reset
ddr3_rst_n_o : out std_logic;
--! DDR3 clock enable
ddr3_cke_o : out std_logic;
--! DDR3 lower byte data mask
ddr3_dm_o : out std_logic;
--! DDR3 upper byte data mask
ddr3_udm_o : out std_logic;
--! DDR3 lower byte data strobe (pos)
ddr3_dqs_p_b : inout std_logic;
--! DDR3 lower byte data strobe (neg)
ddr3_dqs_n_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_p_b : inout std_logic;
--! DDR3 upper byte data strobe (pos)
ddr3_udqs_n_b : inout std_logic;
--! DDR3 clock (pos)
ddr3_clk_p_o : out std_logic;
--! DDR3 clock (neg)
ddr3_clk_n_o : out std_logic;
--! MCB internal termination calibration resistor
ddr3_rzq_b : inout std_logic;
--! MCB internal termination calibration
ddr3_zio_b : inout std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 0
----------------------------------------------------------------------------
--! Wishbone bus clock
wb0_clk_i : in std_logic;
--! Wishbone bus byte select
wb0_sel_i : in std_logic_vector(g_P0_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb0_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb0_stb_i : in std_logic;
--! Wishbone bus write enable
wb0_we_i : in std_logic;
--! Wishbone bus address
wb0_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb0_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb0_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 0
----------------------------------------------------------------------------
--! Command FIFO empty
p0_cmd_empty_o : out std_logic;
--! Command FIFO full
p0_cmd_full_o : out std_logic;
--! Read FIFO full
p0_rd_full_o : out std_logic;
--! Read FIFO empty
p0_rd_empty_o : out std_logic;
--! Read FIFO count
p0_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p0_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p0_rd_error_o : out std_logic;
--! Write FIFO full
p0_wr_full_o : out std_logic;
--! Write FIFO empty
p0_wr_empty_o : out std_logic;
--! Write FIFO count
p0_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p0_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p0_wr_error_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus - Port 1
----------------------------------------------------------------------------
--! Wishbone bus clock
wb1_clk_i : in std_logic;
--! Wishbone bus byte select
wb1_sel_i : in std_logic_vector(g_P1_MASK_SIZE - 1 downto 0);
--! Wishbone bus cycle select
wb1_cyc_i : in std_logic;
--! Wishbone bus cycle strobe
wb1_stb_i : in std_logic;
--! Wishbone bus write enable
wb1_we_i : in std_logic;
--! Wishbone bus address
wb1_addr_i : in std_logic_vector(31 downto 0);
--! Wishbone bus data input
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus data output
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
--! Wishbone bus acknowledge
wb1_ack_o : out std_logic;
--! Wishbone bus stall (for pipelined mode)
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Status - Port 1
----------------------------------------------------------------------------
--! Command FIFO empty
p1_cmd_empty_o : out std_logic;
--! Command FIFO full
p1_cmd_full_o : out std_logic;
--! Read FIFO full
p1_rd_full_o : out std_logic;
--! Read FIFO empty
p1_rd_empty_o : out std_logic;
--! Read FIFO count
p1_rd_count_o : out std_logic_vector(6 downto 0);
--! Read FIFO overflow
p1_rd_overflow_o : out std_logic;
--! Read FIFO error (pointers unsynchronized, reset required)
p1_rd_error_o : out std_logic;
--! Write FIFO full
p1_wr_full_o : out std_logic;
--! Write FIFO empty
p1_wr_empty_o : out std_logic;
--! Write FIFO count
p1_wr_count_o : out std_logic_vector(6 downto 0);
--! Write FIFO underrun
p1_wr_underrun_o : out std_logic;
--! Write FIFO error (pointers unsynchronized, reset required)
p1_wr_error_o : out std_logic
);
end component ddr3_ctrl;
component clk_gen
port
(-- Clock in ports
CLK_40_IN : in std_logic;
CLKFB_IN : in std_logic;
-- Clock out ports
CLK_640 : out std_logic;
CLK_160 : out std_logic;
CLK_80 : out std_logic;
CLK_40 : out std_logic;
CLK_40_90 : out std_logic;
CLKFB_OUT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
component ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
end component;
component ila_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 16; -- upper 4 bits used for addressing slave
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk : std_logic;
-- IO clocks
signal CLK_40 : std_logic;
signal CLK_80 : std_logic;
signal CLK_125 : std_logic;
signal CLK_160 : std_logic;
signal CLK_640 : std_logic;
signal CLK_40_buf : std_logic;
signal CLK_40_90_buf : std_logic;
signal CLK_80_buf : std_logic;
signal CLK_160_buf : std_logic;
signal CLK_640_buf : std_logic;
signal ioclk_fb : std_logic;
-- System clock generation
signal sys_clk_in : std_logic;
signal sys_clk_40_buf : std_logic;
signal sys_clk_200_buf : std_logic;
signal sys_clk_40 : std_logic;
signal sys_clk_200 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
signal locked : std_logic;
signal locked_v : std_logic_vector(1 downto 0);
signal rst_n : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0) := (others => '0');
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0) := (others => '0');
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal ram_we : std_logic;
-- DMAbus RX bridge
signal rx_dma_adr : std_logic_vector(31 downto 0);
signal rx_dma_dat_o : std_logic_vector(31 downto 0);
signal rx_dma_dat_i : std_logic_vector(31 downto 0);
signal rx_dma_cyc : std_logic;
signal rx_dma_stb : std_logic;
signal rx_dma_we : std_logic;
signal rx_dma_ack : std_logic;
signal rx_dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_out : std_logic;
-- CSR whisbone slaves for test
signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
-- I2C
signal scl_t : std_logic;
signal sda_t : std_logic;
-- Trigger logic
signal int_busy_t : std_logic;
signal trig_tag_t : std_logic_vector(31 downto 0);
signal int_trig_t : std_logic;
signal eudet_trig_t : std_logic;
signal eudet_clk_t : std_logic;
signal eudet_rst_t : std_logic;
signal eudet_busy_t : std_logic;
-- FOR TESTS
signal debug : std_logic_vector(31 downto 0);
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
signal led_k2000 : unsigned(2 downto 0);
signal led_pps : std_logic;
signal leds : std_logic_vector(3 downto 0);
-- ILA
signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG0_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG1_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal TRIG2_t : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal debug_dma : std_logic_vector(31 downto 0);
signal ddr_status : std_logic_vector(31 downto 0);
signal gn4124_core_Status : std_logic_vector(31 downto 0);
signal tx_data_o : std_logic_vector(0 downto 0);
signal trig_pulse : std_logic;
signal fe_cmd_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_clk_o : std_logic_vector(c_TX_CHANNELS-1 downto 0);
signal fe_data_i : std_logic_vector(c_RX_CHANNELS-1 downto 0);
signal rx_data : std_logic_vector(31 downto 0);
signal rx_valid : std_logic;
signal rx_busy : std_logic;
-- FMC
signal dac_ld_t : std_logic;
signal inj_sw_t : std_logic;
signal dac_din_t : std_logic;
signal dac_clk_t : std_logic;
signal dac_cs_t : std_logic;
signal trigger_t : std_logic;
signal clk_data_t : std_logic;
signal rst_0_t : std_logic;
signal clk_cnfg_t : std_logic;
signal pix_d_cnfg_t : std_logic;
signal ld_cnfg_t : std_logic;
signal clk_bx_t : std_logic;
signal rst_1_t : std_logic;
signal en_pix_sr_cnfg_t : std_logic;
signal si_cnfg_t : std_logic;
signal so_cnfg_t : std_logic;
signal hit_or_t : std_logic;
signal out_data_t : std_logic;
begin
-- Buffers
dac_ld <= dac_ld_t;
inj_sw <= inj_sw_t;
dac_din <= dac_din_t;
dac_clk <= dac_clk_t;
dac_cs <= dac_cs_t;
trigger_buf : OBUFDS port map (O => trigger_n, OB => trigger_p, I => not trigger_t); -- inv
clk_datar_buf : OBUFDS port map (O => clk_data_p, OB => clk_data_n, I => clk_data_t);
rst_0_buf : OBUFDS port map (O => rst_0_n, OB => rst_0_p, I => not rst_0_t); -- inv
clk_cnfg_buf : OBUFDS port map (O => clk_cnfg_n, OB => clk_cnfg_p, I => clk_cnfg_t); --inv
pix_d_cnfg_buf : OBUFDS port map (O => pix_d_cnfg_p, OB => pix_d_cnfg_n, I => pix_d_cnfg_t);
ld_cnfg_buf : OBUFDS port map (O => ld_cnfg_p, OB => ld_cnfg_n, I => ld_cnfg_t);
clk_bx_buf : OBUFDS port map (O => clk_bx_p, OB => clk_bx_n, I => clk_bx_t);
en_pix_sr_cnfg_buf : OBUFDS port map (O => en_pix_sr_cnfg_n, OB => en_pix_sr_cnfg_p, I => not en_pix_sr_cnfg_t); -- inv
rst_1_buf : OBUFDS port map (O => rst_1_n, OB => rst_1_p, I => not rst_1_t); --inv
si_cnfg_buf : OBUFDS port map (O => si_cnfg_p, OB => si_cnfg_n, I => si_cnfg_t);
eudet_clk_buf : OBUFDS port map (O => EXT_4_P, OB => EXT_4_N, I => not eudet_clk_t);
eudet_busy_buf : OBUFDS port map (O => EXT_2_P, OB => EXT_2_N, I => eudet_busy_t);
so_cnfg_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => so_cnfg_t, I => so_cnfg_p, IB => so_cnfg_n);
hit_or_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => hit_or_t, I => hit_or_p, IB => hit_or_n);
out_data_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => out_data_t, I => out_data_p, IB => out_data_n);
eudet_rst_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_rst_t, I => EXT_3_P, IB => EXT_3_N);
eudet_trig_buf : IBUFDS generic map(DIFF_TERM => TRUE, IBUF_LOW_PWR => FALSE) port map (O => eudet_trig_t, I => EXT_1_P, IB => EXT_1_N);
fe_data_i(0) <= not out_data_t;
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
IBUFGDS_gn_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DIFF_SSTL18_I"
)
port map (
O => l_clk, -- Clock buffer output
I => L_CLKp, -- Diff_p clock buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS_pll_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25"
)
port map (
O => CLK_125, -- Clock buffer output
I => clk_125m_pllref_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
cmp_fe65p2_addon: fe65p2_addon PORT MAP(
clk_i => CLK_40,
rst_n => rst_n,
serial_in => fe_cmd_o(0),
clk_rx_i => CLK_40,
clk_bx_o => clk_bx_t,
trig_o => trigger_t,
clk_cnfg_o => clk_cnfg_t,
en_pix_sr_cnfg_o => en_pix_sr_cnfg_t,
ld_cnfg_o => ld_cnfg_t,
si_cnfg_o => si_cnfg_t,
pix_d_cnfg_o => pix_d_cnfg_t,
clk_data_o => clk_data_t,
rst_0_o => rst_0_t,
rst_1_o => rst_1_t,
dac_sclk_o => dac_clk_t,
dac_sdi_o => dac_din_t,
dac_ld_o => dac_ld_t,
dac_cs_o => dac_cs_t,
inj_sw_o => inj_sw_t
);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => rst_n,
status_o => gn4124_core_status,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => irq_sources,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_out,
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall,
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0'
);
GPIO(0) <= irq_out;
GPIO(1) <= '0';
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk,
rst_n_i => rst_n,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
------------------------------------------------------------------------------
-- cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
-- port map(
-- rst_n_i => rst_n,
-- wb_clk_i => sys_clk,
-- wb_addr_i => wb_adr(1 downto 0),
-- wb_data_i => wb_dat_o,
-- wb_data_o => wb_dat_i(63 downto 32),
-- wb_cyc_i => wb_cyc(1),
-- wb_sel_i => wb_sel,
-- wb_stb_i => wb_stb,
-- wb_we_i => wb_we,
-- wb_ack_o => wb_ack(1),
-- dummy_stat_reg_1_i => dummy_stat_reg_1,
-- dummy_stat_reg_2_i => dummy_stat_reg_2,
-- dummy_stat_reg_3_i => dummy_stat_reg_3,
-- dummy_stat_reg_switch_i => dummy_stat_reg_switch
-- );
cmp_wb_tx_core : wb_tx_core port map
(
-- Sys connect
wb_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
wb_stall_o => wb_stall(1),
-- TX
tx_clk_i => CLK_40,
tx_data_o => fe_cmd_o,
trig_pulse_o => trig_pulse,
ext_trig_i => int_trig_t
);
cmp_wb_rx_core: wb_rx_core PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(95 downto 64),
wb_cyc_i => wb_cyc(2),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(2),
wb_stall_o => wb_stall(2),
rx_clk_i => CLK_40,
rx_serdes_clk_i => CLK_160,
rx_data_i => fe_data_i,
rx_valid_o => rx_valid,
rx_data_o => rx_data,
trig_tag_i => trig_tag_t,
busy_o => open,
debug_o => debug
);
cmp_wb_rx_bridge : wb_rx_bridge port map (
-- Sys Connect
sys_clk_i => sys_clk,
rst_n_i => rst_n,
-- Wishbone slave interface
wb_adr_i => wb_adr,
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(127 downto 96),
wb_cyc_i => wb_cyc(3),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(3),
wb_stall_o => wb_stall(3),
-- Wishbone DMA Master Interface
dma_clk_i => sys_clk,
dma_adr_o => rx_dma_adr,
dma_dat_o => rx_dma_dat_o,
dma_dat_i => rx_dma_dat_i,
dma_cyc_o => rx_dma_cyc,
dma_stb_o => rx_dma_stb,
dma_we_o => rx_dma_we,
dma_ack_i => rx_dma_ack,
dma_stall_i => rx_dma_stall,
-- Rx Interface (sync to sys_clk)
rx_data_i => rx_data,
rx_valid_i => rx_valid,
-- Status in
trig_pulse_i => trig_pulse,
-- Status out
irq_o => open,
busy_o => rx_busy
);
wb_dat_i(159 downto 136) <= (others => '0');
cmp_i2c_master : i2c_master_wb_top
port map (
wb_clk_i => sys_clk,
wb_rst_i => not rst_n,
arst_i => rst_n,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
wb_dat_o => wb_dat_i(135 downto 128),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(4),
wb_ack_o => wb_ack(4),
wb_inta_o => open,
scl => open,
sda => open
);
cmp_wb_trigger_logic: wb_trigger_logic PORT MAP(
wb_clk_i => sys_clk,
rst_n_i => rst_n,
wb_adr_i => wb_adr(31 downto 0),
wb_dat_i => wb_dat_o(31 downto 0),
wb_dat_o => wb_dat_i(191 downto 160),
wb_cyc_i => wb_cyc(5),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(5),
ext_trig_i => "00" & IO_1 & not hit_or_t,
ext_trig_o => open,
ext_busy_i => '0',
ext_busy_o => IO_0,
eudet_clk_o => eudet_clk_t,
eudet_busy_o => eudet_busy_t,
eudet_trig_i => eudet_trig_t,
eudet_rst_i => eudet_rst_t,
clk_i => CLK_40,
trig_tag => trig_tag_t
);
--wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1));
-- wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2));
-- dummy_stat_reg_1 <= X"DEADBABE";
-- dummy_stat_reg_2 <= X"BEEFFACE";
-- dummy_stat_reg_3 <= X"12345678";
-- dummy_stat_reg_switch <= X"0000000" & "000" & p2l_pll_locked;
led_red_o <= dummy_ctrl_reg_led(0);
led_green_o <= dummy_ctrl_reg_led(1);
-- TRIG0(31 downto 0) <= (others => '0');
TRIG1(31 downto 0) <= (others => '0');
TRIG2(31 downto 0) <= (others => '0');
-- TRIG0(12 downto 0) <= (others => '0');
--TRIG1(31 downto 0) <= rx_dma_dat_o;
--TRIG1(31 downto 0) <= dma_dat_i;
-- TRIG1(31 downto 0) <= gn4124_core_status;
-- TRIG2(31 downto 0) <= ddr_status;
-- TRIG0(13) <= rx_dma_cyc;
-- TRIG0(14) <= rx_dma_stb;
-- TRIG0(15) <= rx_dma_we;
-- TRIG0(16) <= rx_dma_ack;
-- TRIG0(17) <= rx_dma_stall;
-- TRIG0(18) <= dma_cyc;
-- TRIG0(19) <= dma_stb;
-- TRIG0(20) <= dma_we;
-- TRIG0(21) <= dma_ack;
-- TRIG0(22) <= dma_stall;
-- TRIG0(23) <= irq_out;
-- TRIG0(24) <= rx_busy;
-- TRIG0(31 downto 25) <= (others => '0');
-- TRIG0(0) <= rx_valid;
-- TRIG0(1) <= fe_cmd_o(0);
-- TRIG0(2) <= trig_pulse;
-- TRIG0(3) <= fe_cmd_o(0);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= rx_data;
-- TRIG2 <= debug;
-- TRIG0(0) <= scl;
-- TRIG0(1) <= sda;
-- TRIG0(2) <= wb_stb;
-- TRIG0(3) <= wb_ack(4);
-- TRIG0(31 downto 4) <= (others => '0');
-- TRIG1 <= wb_adr;
-- TRIG2 <= wb_dat_o;
TRIG0(14 downto 0) <= trig_tag_t(14 downto 0);
TRIG0(15) <= int_trig_t;
TRIG0(16) <= eudet_trig_t;
TRIG0(17) <= eudet_clk_t;
TRIG0(18) <= eudet_busy_t;
TRIG0(19) <= trigger_t;
TRIG0(20) <= hit_or_t;
ila_i : ila
port map (
CONTROL => CONTROL,
CLK => CLK_40,
-- CLK => sys_clk,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2);
ila_icon_i : ila_icon
port map (
CONTROL0 => CONTROL);
------------------------------------------------------------------------------
-- Interrupt stuff
------------------------------------------------------------------------------
-- just forward irq pulses for test
irq_to_gn4124 <= irq_sources(1) or irq_sources(0);
------------------------------------------------------------------------------
-- FOR TEST
------------------------------------------------------------------------------
p_led_cnt : process (L_RST_N, sys_clk)
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
elsif rising_edge(sys_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(23);
end if;
end process p_led_cnt;
led_pps <= led_cnt(23) and not(led_en);
p_led_k2000 : process (sys_clk, L_RST_N)
begin
if L_RST_N = '0' then
led_k2000 <= (others => '0');
leds <= "0001";
elsif rising_edge(sys_clk) then
if led_pps = '1' then
if led_k2000(2) = '0' then
if leds /= "1000" then
leds <= leds(2 downto 0) & '0';
end if;
else
if leds /= "0001" then
leds <= '0' & leds(3 downto 1);
end if;
end if;
led_k2000 <= led_k2000 + 1;
end if;
end if;
end process p_led_k2000;
AUX_LEDS_O <= not(leds);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
rst_n <= (L_RST_N and sys_clk_pll_locked and locked);
cmp_clk_gen : clk_gen
port map (
-- Clock in ports
CLK_40_IN => sys_clk_40,
CLKFB_IN => ioclk_fb,
-- Clock out ports
CLK_640 => CLK_640_buf,
CLK_160 => CLK_160_buf,
CLK_80 => CLK_80_buf,
CLK_40 => CLK_40_buf,
CLK_40_90 => CLK_40_90_buf,
CLKFB_OUT => ioclk_fb,
-- Status and control signals
RESET => not L_RST_N,
LOCKED => locked
);
BUFPLL_640 : BUFPLL
generic map (
DIVIDE => 4, -- DIVCLK divider (1-8)
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
port map (
IOCLK => CLK_640, -- 1-bit output: Output I/O clock
LOCK => open, -- 1-bit output: Synchronized LOCK output
SERDESSTROBE => open, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
GCLK => CLK_160, -- 1-bit input: BUFG clock input
LOCKED => locked, -- 1-bit input: LOCKED input from PLL
PLLIN => clk_640_buf -- 1-bit input: Clock input from PLL
);
cmp_ioclk_160_buf : BUFG
port map (
O => CLK_160,
I => CLK_160_buf);
cmp_ioclk_80_buf : BUFG
port map (
O => CLK_80,
I => CLK_80_buf);
cmp_ioclk_40_buf : BUFG
port map (
O => CLK_40,
I => CLK_40_buf);
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 40.000 MHz IO driver clock
-- 200.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
sys_clk <= l_clk;
-- AD5662BRMZ-1 DAC output powers up to 0V. The output remains valid until a
-- write sequence arrives to the DAC.
-- To avoid spurious writes, the DAC interface outputs are fixed to safe values.
pll25dac_sync_n <= '1';
pll20dac_sync_n <= '1';
plldac_din <= '0';
plldac_sclk <= '0';
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 5,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_40_buf,
CLKOUT1 => sys_clk_200_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_40,
I => sys_clk_40_buf);
cmp_clk_200_buf : BUFG
port map (
O => sys_clk_200,
I => sys_clk_200_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
cmp_ddr3_ctrl: ddr3_ctrl PORT MAP(
clk_i => ddr_clk,
rst_n_i => rst_n,
status_o => ddr_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_clk_i => sys_clk,
wb0_sel_i => dma_sel,
wb0_cyc_i => dma_cyc,
wb0_stb_i => dma_stb,
wb0_we_i => dma_we,
wb0_addr_i => dma_adr,
wb0_data_i => dma_dat_o,
wb0_data_o => dma_dat_i,
wb0_ack_o => dma_ack,
wb0_stall_o => dma_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => open,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk,
wb1_sel_i => "1111",
wb1_cyc_i => rx_dma_cyc,
wb1_stb_i => rx_dma_stb,
wb1_we_i => rx_dma_we,
wb1_addr_i => rx_dma_adr,
wb1_data_i => rx_dma_dat_o,
wb1_data_o => rx_dma_dat_i,
wb1_ack_o => rx_dma_ack,
wb1_stall_o => rx_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
end rtl;
| gpl-3.0 | b137cb036f411ba73e66c745db03e238 | 0.428326 | 3.712017 | false | false | false | false |
joaocarlos/ModelSIM-compile | countertb.vhd | 2 | 5,385 | -- Test bench for Counter Exercise
entity CounterTB is
end;
library design_library;
library IEEE;
use IEEE.Std_logic_1164.all;
architecture Bench of CounterTB is
component Counter
port (Clock, Reset, Enable, Load, UpDn: in Std_logic;
Data: in Std_logic_vector(7 downto 0);
Q: out Std_logic_vector(7 downto 0));
end component;
signal Clock, Reset, Enable, Load, UpDn: Std_logic;
signal Data, Q: Std_logic_vector(7 downto 0);
signal OK: Boolean := True;
begin
Clk: process
begin
while now <= 3000 NS loop
Clock <= '0';
wait for 5 NS;
Clock <= '1';
wait for 5 NS;
end loop;
wait;
end process;
Stim: process
begin
Enable <= '0';
Load <= '0';
UpDn <= '1';
Reset <= '1';
wait for 10 ns; -- Should be reset
Reset <= '0';
wait for 10 ns; -- Should do nothing - not enabled
Enable <= '1';
wait for 20 ns; -- Should count up to 2
UpDn <= '0';
wait for 40 ns; -- Should count downto 254
UpDn <= '1';
wait for 40 ns; -- Should count up to 2
Reset <= '1';
wait for 10 ns; -- Should be reset, overriding enable
Reset <= '0';
wait for 30 ns; -- Should count up to 3
Enable <= '0';
wait for 10 ns; -- Should do nothing - not enabled
Data <= "01111111";
Load <= '1';
wait for 10 ns; -- Should do nothing - not enabled
Load <= '0';
Enable <= '1';
wait for 10 ns; -- Should count from 3 to 4
Load <= '1';
wait for 10 ns; -- Should load 127
Load <= '0';
wait for 20 ns; -- Should count from 127 to 129
Enable <= '0';
wait for 10 ns; -- Should do nothing - not enabled
UpDn <= '0';
wait for 10 ns; -- Should do nothing - not enabled
Enable <= '1';
wait for 20 ns; -- Should count down from 129 to 127
Data <= "11110000";
Load <= '1';
wait for 10 ns; -- Should load
Reset <= '1';
wait for 10 ns; -- Should be reset, overriding load
Load <= '0';
UpDn <= '1';
wait for 10 ns; -- Should stay at 0 - still reset
Reset <= '0';
wait for 2560 ns; -- Should count from 0 round to 0
Enable <= '0';
wait;
end process;
G1: Counter port map (Clock, Reset, Enable, Load, UpDn, Data, Q);
Check: process
begin
wait for 9 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000010" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "11111111" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "11111110" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "11111111" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000010" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000010" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000011" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000011" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000011" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000100" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "01111111" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "10000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "10000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "10000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "10000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "10000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "01111111" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "11110000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000001" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000010" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000011" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000100" then
OK <= False;
end if;
wait for 2500 ns;
if Q /= "11111110" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "11111111" then
OK <= False;
end if;
wait for 10 ns;
if Q /= "00000000" then
OK <= False;
end if;
wait;
end process;
end;
| gpl-2.0 | f1e4837460cf211915e6d3233dbf1d0b | 0.499536 | 3.631153 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/process/rule_400_test_input.fixed.vhd | 1 | 460 |
architecture RTL of FIFO is
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
PROC_1 : process
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
a <= 2;
b := 1;
a <= 2;
b := 3;
a <= 3;
b := 10;
end process;
end architecture RTL;
| gpl-3.0 | 67e9b589f552e77b033ae572b9398f9d | 0.43913 | 3.484848 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/rounder.vhd | 2 | 13,395 | `protect begin_protected
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`protect end_protected
| mit | 342ada606c5bc3683974b36ca36606a8 | 0.931392 | 1.868983 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_014_test_input.fixed_upper.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
CASE boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | bcee140a8526348dd0cfeb8deb9548ce | 0.4618 | 3.308989 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/cdr_serdes.vhd | 2 | 7,015 | -- CDR with SERDES
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity cdr_serdes is
port
(
-- clocks
clk160 : in std_logic;
clk640 : in std_logic;
-- reset
reset : in std_logic;
-- data input
din : in std_logic;
-- data output
data_value : out std_logic_vector(1 downto 0);
data_valid : out std_logic_vector(1 downto 0);
data_lock : out std_logic
);
end cdr_serdes;
architecture rtl of cdr_serdes is
signal AZ : std_logic_vector(4 downto 0) := (others => '0');
signal BZ : std_logic_vector(4 downto 0) := (others => '0');
signal CZ : std_logic_vector(4 downto 0) := (others => '0');
signal DZ : std_logic_vector(4 downto 0) := (others => '0');
signal AAP, AAN : std_logic := '0';
signal BBP, BBN : std_logic := '0';
signal CCP, CCN : std_logic := '0';
signal DDP, DDN : std_logic := '0';
signal use_A : std_logic := '0';
signal use_B : std_logic := '0';
signal use_C : std_logic := '0';
signal use_D : std_logic := '0';
signal use_A1, use_A2 : std_logic := '0';
signal use_B1, use_B2 : std_logic := '0';
signal use_C1, use_C2 : std_logic := '0';
signal use_D1, use_D2 : std_logic := '0';
signal use_A_reg : std_logic := '0';
signal use_B_reg : std_logic := '0';
signal use_C_reg : std_logic := '0';
signal use_D_reg : std_logic := '0';
signal use_A_reg2 : std_logic := '0';
signal use_B_reg2 : std_logic := '0';
signal use_C_reg2 : std_logic := '0';
signal use_D_reg2 : std_logic := '0';
signal sdata_A : std_logic_vector(1 downto 0) := "00";
signal sdata_B : std_logic_vector(1 downto 0) := "00";
signal sdata_C : std_logic_vector(1 downto 0) := "00";
signal sdata_D : std_logic_vector(1 downto 0) := "00";
signal pipe_ce0 : std_logic := '0';
signal pipe_ce1 : std_logic := '0';
signal valid_int : std_logic_vector(1 downto 0) := "00";
signal lockcnt : integer range 0 to 31 := 0;
begin
serdes: ISERDES2
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
DATA_WIDTH => 4, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
CFB0 => open, -- 1-bit output: Clock feed-through route output
CFB1 => open, -- 1-bit output: Clock feed-through route output
DFB => open, -- 1-bit output: Feed-through clock output
FABRICOUT => open, -- 1-bit output: Unsynchrnonized data output
INCDEC => open, -- 1-bit output: Phase detector output
-- Q1 - Q4: 1-bit (each) output: Registered outputs to FPGA logic
Q1 => AZ(0),
Q2 => BZ(0),
Q3 => CZ(0),
Q4 => DZ(0),
SHIFTOUT => open, -- 1-bit output: Cascade output signal for master/slave I/O
VALID => open, -- 1-bit output: Output status of the phase detector
BITSLIP => '0', -- 1-bit input: Bitslip enable input
CE0 => '1', -- 1-bit input: Clock enable input
CLK0 => clk640, -- 1-bit input: I/O clock network input
CLK1 => '0', -- 1-bit input: Secondary I/O clock network input
CLKDIV => clk160, -- 1-bit input: FPGA logic domain clock input
D => din, -- 1-bit input: Input data
IOCE => '1', -- 1-bit input: Data strobe input
RST => reset, -- 1-bit input: Asynchronous reset input
SHIFTIN => '0' -- 1-bit input: Cascade input signal for master/slave I/O
);
process begin
wait until rising_edge(clk160);
if reset = '1' then
AZ(4 downto 1) <= (others => '0');
BZ(4 downto 1) <= (others => '0');
CZ(4 downto 1) <= (others => '0');
DZ(4 downto 1) <= (others => '0');
AAP <= '0'; AAN <= '0';
BBP <= '0'; BBN <= '0';
CCP <= '0'; CCN <= '0';
DDP <= '0'; DDN <= '0';
use_A1 <= '0'; use_A2 <= '0'; use_A <= '0';
use_B1 <= '0'; use_B2 <= '0'; use_B <= '0';
use_C1 <= '0'; use_C2 <= '0'; use_C <= '0';
use_D1 <= '0'; use_D2 <= '0'; use_D <= '0';
use_A_reg <= '0'; use_A_reg2 <= '0';
use_B_reg <= '0'; use_B_reg2 <= '0';
use_C_reg <= '0'; use_C_reg2 <= '0';
use_D_reg <= '0'; use_D_reg2 <= '0';
sdata_A <= "00";
sdata_B <= "00";
sdata_C <= "00";
sdata_D <= "00";
valid_int <= "00";
data_value <= "00";
data_valid <= "00";
data_lock <= '0';
lockcnt <= 0;
pipe_ce0 <= '0';
pipe_ce1 <= '0';
else
-- clock in the data
AZ(4 downto 1) <= AZ(3 downto 0);
BZ(4 downto 1) <= BZ(3 downto 0);
CZ(4 downto 1) <= CZ(3 downto 0);
DZ(4 downto 1) <= DZ(3 downto 0);
-- find positive edges
AAP <= (AZ(2) xor AZ(3)) and not AZ(2);
BBP <= (BZ(2) xor BZ(3)) and not BZ(2);
CCP <= (CZ(2) xor CZ(3)) and not CZ(2);
DDP <= (DZ(2) xor DZ(3)) and not DZ(2);
-- find negative edges
AAN <= (AZ(2) xor AZ(3)) and AZ(2);
BBN <= (BZ(2) xor BZ(3)) and BZ(2);
CCN <= (CZ(2) xor CZ(3)) and CZ(2);
DDN <= (DZ(2) xor DZ(3)) and DZ(2);
-- decision of sampling point
use_A1 <= (BBP and not CCP and not DDP and AAP);
use_A2 <= (BBN and not CCN and not DDN and AAN);
use_B1 <= (CCP and not DDP and AAP and BBP);
use_B2 <= (CCN and not DDN and AAN and BBN);
use_C1 <= (DDP and AAP and BBP and CCP);
use_C2 <= (DDN and AAN and BBN and CCN);
use_D1 <= (AAP and not BBP and not CCP and not DDP);
use_D2 <= (AAN and not BBN and not CCN and not DDN);
use_A <= use_A1 or use_A2;
use_B <= use_B1 or use_B2;
use_C <= use_C1 or use_C2;
use_D <= use_D1 or use_D2;
-- if we found an edge
if (use_A or use_B or use_C or use_D) = '1' then
lockcnt <= 31;
pipe_ce0 <= '1'; -- sync marker
pipe_ce1 <= '1';
else
if lockcnt = 0 then
pipe_ce0 <= '0';
else
lockcnt <= lockcnt - 1;
end if;
pipe_ce1 <= '0';
end if;
-- register
use_A_reg <= use_A;
use_B_reg <= use_B;
use_C_reg <= use_C;
use_D_reg <= use_D;
if pipe_ce1 = '1' then
use_A_reg2 <= use_A_reg;
use_B_reg2 <= use_B_reg;
use_C_reg2 <= use_C_reg;
use_D_reg2 <= use_D_reg;
end if;
-- collect output data
sdata_A(0) <= AZ(4) and use_A_reg2; sdata_A(1) <= AZ(4) and use_D_reg2;
sdata_B(0) <= BZ(4) and use_B_reg2; sdata_B(1) <= '0';
sdata_C(0) <= CZ(4) and use_C_reg2; sdata_C(1) <= '0';
sdata_D(0) <= DZ(4) and use_D_reg2; sdata_D(1) <= DZ(4) and use_A_reg2;
-- ouput data if we have seen an edge
if pipe_ce0 = '1' then
data_value <= sdata_A or sdata_B or sdata_C or sdata_D;
end if;
-- data valid output
if use_D_reg2 = '1' and use_A_reg = '1' then
valid_int <= "00"; -- move from A to D: no valid data
elsif use_A_reg2 = '1' and use_D_reg = '1' then
valid_int <= "11"; -- move from D to A: 2 bits valid
else
valid_int <= "01"; -- only one bit is valid
end if;
if pipe_ce0 = '1' then
data_valid <= valid_int;
else
data_valid <= "00";
end if;
data_lock <= pipe_ce0;
end if;
end process;
end architecture;
| gpl-3.0 | 1f911ad09aa50a1917c4848eb2a8bbdc | 0.560513 | 2.518851 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_012_test_input.fixed.vhd | 1 | 403 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
when STATE_1 => -- This is okay
a <= b;
when STATE_1 =>-- This is okay
a <= b;
when STATE_2 =>
a <= b;
when STATE_3 =>
a <= b;
when STATE_4 =>
null;
end case;
end process PROC_1;
end architecture ARCH;
| gpl-3.0 | fb20084489a6bb7436ba6d0d7b5ce3ed | 0.501241 | 3.358333 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/sim/mcb_flow_control.vhd | 20 | 18,501 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;
| gpl-3.0 | 667253d01ebc1e113b0647f3bebabd25 | 0.461489 | 3.611361 | false | false | false | false |
Logistic1994/CPU | module_74181.vhd | 1 | 5,810 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:40:00 05/25/2015
-- Design Name:
-- Module Name: module_74181 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_74181 is
port (
M: in std_logic; -- Ñ¡ÔñÂß¼»òÕßËãÊõ
A: in std_logic_vector(3 downto 0); -- ÊäÈëÊýA
B: in std_logic_vector(3 downto 0); -- ÊäÈëÊýB
S: in std_logic_vector(3 downto 0); -- op
C0: in std_logic; -- ½øλÊäÈë
result: out std_logic_vector(3 downto 0); -- ½á¹û
CN: out std_logic); -- ½øλÊä³ö
end module_74181;
architecture Behavioral of module_74181 is
signal lres: std_logic_vector(3 downto 0);
signal ares: std_logic_vector(4 downto 0);
signal aA, aB: std_logic_vector(4 downto 0);
begin
result <=
ares(3 downto 0) when M = '0' else
lres;
CN <=
'0' when M = '1' else
'1' when S = "0000" and ares(4) = '0' else
'0' when S = "0000" and ares(4) = '1' else
'1' when S = "1111" and ares(4) = '0' else
'0' when S = "1111" and ares(4) = '1' else
ares(4);
process(M, A, B, S, C0)
begin
if M = '1' then
-- Âß¼ÔËËã
ares <= (others => '0');
aA <= (others => '0');
aB <= (others => '0');
case S is
when "0000" =>
lres <= not A;
when "0001" =>
lres <= not (A or B);
when "0010" =>
lres <= (not A) and B;
when "0011" =>
lres <= (others => '0');
when "0100" =>
lres <= not (A and B);
when "0101" =>
lres <= not B;
when "0110" =>
lres <= A xor B;
when "0111" =>
lres <= A and (not B);
when "1000" =>
lres <= A or B;
when "1001" =>
lres <= not (A xor B);
when "1010" =>
lres <= B;
when "1011" =>
lres <= A and B;
when "1100" =>
lres <= (others => '1');
when "1101" =>
lres <= A or (not B);
when "1110" =>
lres <= A or B;
when others =>
lres <= A;
end case;
-- Êä³ö
--result <= lres;
--CN <= '0';
elsif M = '0' then
-- ËãÊõÔËËã
lres <= (others => '0');
aA <= '0' & A;
aB <= '0' & B;
case S is
when "0000" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + 1);
else
ares <= std_logic_vector(unsigned(aA));
end if;
when "0001" =>
if C0 = '0' then
ares <= aA or aB;
else
ares <= std_logic_vector(unsigned(aA or aB) + 1);
end if;
when "0010" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or (not aB)));
else
ares <= std_logic_vector(unsigned(aA or (not aB)) + 1);
end if;
when "0011" =>
if C0 = '0' then
ares <= (others => '1');
else
ares <= (others => '0');
end if;
when "0100" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and (not aB)));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and (not aB)) + 1);
end if;
when "0101" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA and (not aB)));
else
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA and (not aB)) + 1);
end if;
when "0110" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) - unsigned(aB));
else
ares <= std_logic_vector(unsigned(aA) - unsigned(aB) - 1);
end if;
when "0111" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA and (not aB)) - 1);
else
ares <= std_logic_vector(unsigned(aA and (not aB)));
end if;
when "1000" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and aB));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aA and aB) + 1);
end if;
when "1001" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aB));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aB) + 1);
end if;
when "1010" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA and aB));
else
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA and aB) + 1);
end if;
when "1011" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA and aB) - 1);
else
ares <= std_logic_vector(unsigned(aA and aB));
end if;
when "1100" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) + unsigned(aA));
else
ares <= std_logic_vector(unsigned(aA) + unsigned(aA) + 1);
end if;
when "1101" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA));
else
ares <= std_logic_vector(unsigned(aA or aB) + unsigned(aA) + 1);
end if;
when "1110" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA));
else
ares <= std_logic_vector(unsigned(aA or (not aB)) + unsigned(aA) + 1);
end if;
when "1111" =>
if C0 = '0' then
ares <= std_logic_vector(unsigned(aA) - 1);
else
ares <= aA;
end if;
when others =>
ares <= (others => '0');
end case;
-- Êä³ö
--result <= ares(3 downto 0);
--CN <= ares(4);
end if;
end process;
end Behavioral;
| gpl-2.0 | 03d192af2dc10282b4cd13dbd3d403fe | 0.526162 | 2.782567 | false | false | false | false |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined/Controller.vhd | 1 | 15,716 |
library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_unsigned.ALL;
USE ieee.numeric_std.ALL;
entity ControlUnit is
generic (BitWidth: integer;
InstructionWidth: integer);
port(
rst : in std_logic;
clk : in std_logic;
----------------------------------------
Instr_In : in std_logic_vector (InstructionWidth-1 downto 0);
Instr_Add : out std_logic_vector (BitWidth-1 downto 0);
----------------------------------------
MemRdAddress : out std_logic_vector (BitWidth-1 downto 0);
MemWrtAddress: out std_logic_vector (BitWidth-1 downto 0);
Mem_RW : out std_logic;
----------------------------------------
IO_DIR : out std_logic;
IO_RD : in std_logic_vector (BitWidth-1 downto 0);
IO_WR : out std_logic_vector (BitWidth-1 downto 0);
----------------------------------------
DPU_Flags : in std_logic_vector (3 downto 0);
DPU_Flags_FF : in std_logic_vector (3 downto 0);
DataToDPU : out std_logic_vector (BitWidth-1 downto 0);
CommandToDPU : out std_logic_vector (10 downto 0);
Reg_in_sel : out std_logic_vector (7 downto 0);
Reg_out_sel : out std_logic_vector (2 downto 0);
flush_pipeline : out std_logic;
DataFromDPU_bypass: in std_logic_vector (BitWidth-1 downto 0);
DataFromDPU : in std_logic_vector (BitWidth-1 downto 0)
);
end ControlUnit;
architecture RTL of ControlUnit is
---------------------------------------------
-- Signals and Types
---------------------------------------------
TYPE Instruction IS (PUSH,POP,
JMPEQ,Jmp_rel,Jmp,JmpZ,JmpOV,JmpC,
FlipA,And_A_R,OR_A_R,XOR_A_R,NegA,
ShiftA_R,ShiftA_L,ShiftArithL,ShiftArithR,
RRC,RLC,
LoadPC,SavePC,
Add_A_R, Add_A_Mem,Add_A_Dir, Sub_A_R,Sub_A_Mem,Sub_A_Dir,IncA,DecA,
Load_A_Mem,Load_R0_Mem,Load_R0_Dir,Store_A_Mem,load_A_R,load_R_A,Load_Ind_A,
ClearZ,ClearOV,ClearC, ClearACC,
NOP,HALT, GPIO_RD, GPIO_WR, GPIO_DIR);
signal Instr_D, Instr_E, Instr_WB :Instruction := NOP;
signal SP_in, SP_out : std_logic_vector (BitWidth-1 downto 0):= (others => '0');
signal PC_in, PC_out : std_logic_vector (BitWidth-1 downto 0):= (others => '0');
signal InstrReg_out: std_logic_vector (InstructionWidth-1 downto 0) := (others => '0');
signal arithmetic_operation : std_logic;
signal halt_signal_in, halt_signal : std_logic := '0';
signal flush_signal, flush_signal_FF: std_logic;
signal IO_WR_in, IO_WR_in_FF : std_logic_vector(BitWidth-1 downto 0);
signal IO_DIR_in, IO_DIR_FF :std_logic;
---------------------------------------------
-- OpCode Aliases
---------------------------------------------
alias opcode : std_logic_vector (5 downto 0) is InstrReg_out (InstructionWidth-1 downto BitWidth);
alias opcode_in : std_logic_vector (5 downto 0) is Instr_In (InstructionWidth-1 downto BitWidth);
begin
flush_pipeline <= flush_signal;
---------------------------------------------
-- Registers setting
---------------------------------------------
process (clk,rst)
begin
if rst = '1' then
SP_out <= (others => '0');
PC_out <= (others => '0');
InstrReg_out(InstructionWidth-1 downto BitWidth) <= "111110";
InstrReg_out(BitWidth-1 downto 0) <= (others=> '0');
Instr_E <= NOP;
Instr_WB <= NOP;
halt_signal<= '0';
flush_signal_FF<= '0';
IO_WR_in_FF <= (others=> '0');
IO_DIR_FF <= '0';
elsif clk'event and clk='1' then
IO_WR_in_FF <= IO_WR_in;
IO_DIR_FF <= IO_DIR_in;
SP_out <= SP_in;
PC_out <= PC_in;
halt_signal<= halt_signal_in;
if halt_signal = '0' then
InstrReg_out <= Instr_In;
Instr_E <= Instr_D;
Instr_WB <= Instr_E;
end if;
flush_signal_FF <= flush_signal;
end if;
end process;
---------------------------------------------
IO_DIR <= IO_DIR_FF;
IO_WR <= IO_WR_in_FF;
-----------------------------------------------------------
--Control FSM
-----------------------------------------------------------
process(PC_out,Instr_D,InstrReg_out,DataFromDPU, SP_out, DPU_Flags)
begin
IO_WR_in <= IO_WR_in_FF;
IO_DIR_in <= IO_DIR_FF;
SP_in <= SP_out;
Instr_Add <= PC_out;
Mem_RW <= '0';
MemRdAddress <= (others => '0');
DataToDPU <= (others => '0');
CommandToDPU <= "00000001000"; --do not do anything
Reg_in_sel<="00000000";
Reg_out_sel<="000";
MemWrtAddress <= (others => '0');
-----------------------Arithmetic--------------------------
if Instr_D = Add_A_R then
CommandToDPU <= "00000000010";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr_D = Add_A_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000000";
elsif Instr_D = Add_A_Dir then
DataToDPU <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000001";
-----------------------------------------------
elsif Instr_D = Sub_A_R then
CommandToDPU <= "00000000110";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr_D = Sub_A_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000100";
elsif Instr_D = Sub_A_Dir then
DataToDPU <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000000101";
-----------------------------------------------
elsif Instr_D = IncA then
CommandToDPU <= "00000000011";
elsif Instr_D = DecA then
CommandToDPU <= "00000000111";
-----------------------Shift-------------------------------
elsif Instr_D = ShiftA_R then
CommandToDPU <= "00000011100";
elsif Instr_D = ShiftA_L then
CommandToDPU <= "00000100000";
elsif Instr_D = ShiftArithL then
CommandToDPU <= "00000101100";
elsif Instr_D = ShiftArithR then
CommandToDPU <= "00000101000";
elsif Instr_D = RRC then
CommandToDPU <= "00000111000";
elsif Instr_D = RLC then
CommandToDPU <= "00000111100";
-----------------------Logical-----------------------------
elsif Instr_D = NegA then
CommandToDPU <= "00000100100";
elsif Instr_D = FlipA then
CommandToDPU <= "00000110000";
elsif Instr_D = And_A_R then
CommandToDPU <= "00000010010";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr_D = OR_A_R then
CommandToDPU <= "00000010110";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr_D = XOR_A_R then
CommandToDPU <= "00000011010";
Reg_out_sel<= InstrReg_out (2 downto 0);
-----------------------Memory------------------------------
elsif Instr_D = Load_R0_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "11000001000";
Reg_in_sel<= "00000001";
elsif Instr_D = Load_A_Mem then
MemRdAddress <= InstrReg_out (BitWidth-1 downto 0);
CommandToDPU <= "00000001100";
elsif Instr_D = SavePC then
DataToDPU <= PC_out-1;
CommandToDPU <= "00000001101";
elsif Instr_D = Load_R0_Dir then
CommandToDPU <= "01000001000";
DataToDPU <= InstrReg_out (BitWidth-1 downto 0);
Reg_in_sel<= "00000001";
Reg_out_sel<= "000";
elsif Instr_D = Load_Ind_A then
MemRdAddress <= DataFromDPU;
CommandToDPU <= "00000001100";
Reg_in_sel<= "00000000";
Reg_out_sel<= "000";
elsif Instr_D = load_A_R then
CommandToDPU <= "00000001100";
Reg_out_sel<= InstrReg_out (2 downto 0);
elsif Instr_D = load_R_A then
CommandToDPU <= "10000001000";
Reg_in_sel<= InstrReg_out (7 downto 0);
-----------------------GPIO-------------------------------
elsif Instr_D = GPIO_RD then
DataToDPU <= IO_RD;
CommandToDPU <= "00000001101";
elsif Instr_D = GPIO_WR then
IO_WR_in <= DataFromDPU;
elsif Instr_D = GPIO_DIR then
if to_integer(unsigned(InstrReg_out (BitWidth-1 downto 0))) = 0 then
IO_DIR_in <= '0';
else
IO_DIR_in <= '1';
end if;
-----------------------store-------------------------------
elsif Instr_D = Store_A_Mem then
MemWrtAddress <= InstrReg_out (BitWidth-1 downto 0);
Mem_RW <= '1';
-----------------------Stack-------------------------------
elsif Instr_D = POP then
MemRdAddress <= SP_out - "00000001";
SP_in <= SP_out - 1;
CommandToDPU <= "00000001100";
-----------------------Stack OP----------------------------
elsif Instr_D= PUSH then
MemWrtAddress <= SP_out;
SP_in <= SP_out + 1;
Mem_RW <= '1';
-----------------------ClearFlags--------------------------
elsif Instr_D = ClearZ then
CommandToDPU <= "00001001000";
elsif Instr_D = ClearOV then
CommandToDPU <= "00010001000";
elsif Instr_D = ClearC then
CommandToDPU <= "00100001000";
elsif Instr_D = ClearACC then
CommandToDPU <= "00000110100";
else
CommandToDPU <= "00000001000"; --do not do anything
end if;
end process;
--PC handling------------------------------------------------------------------------
process(Instr_D, InstrReg_out, PC_out, DPU_Flags, DPU_Flags_FF,
Instr_E, halt_signal, arithmetic_operation, DataFromDPU_bypass)begin
halt_signal_in <= halt_signal;
flush_signal <= '0';
if halt_signal = '1' then
pc_in <= PC_out;
else
PC_in <= PC_out;
if Instr_D = HALT then
halt_signal_in <= '1';
-----------------------Jump--------------------------------
elsif Instr_D = Jmp then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
flush_signal <= '1';
elsif Instr_D = JmpOV and DPU_Flags_FF(0) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
flush_signal <= '1';
elsif Instr_D = JmpZ and DPU_Flags_FF(1) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
flush_signal <= '1';
elsif Instr_D = JMPEQ and DPU_Flags_FF(2) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
flush_signal <= '1';
elsif Instr_D = JmpC and DPU_Flags_FF(3) = '1' then
PC_in <= InstrReg_out (BitWidth-1 downto 0);
flush_signal <= '1';
elsif Instr_D= Jmp_rel then
PC_in <= PC_out + InstrReg_out (BitWidth-1 downto 0);
flush_signal <= '1';
elsif Instr_D= LoadPC then
if arithmetic_operation = '1' then
PC_in <= DataFromDPU_bypass;
else
PC_in <= DataFromDPU;
end if;
flush_signal <= '1';
else
PC_in <= PC_out+1;
end if;
end if;
end process;
process(Instr_E)begin
if Instr_E = Add_A_R or Instr_E = Add_A_Mem or Instr_E = Add_A_Dir
or Instr_E = Sub_A_R or Instr_E = Sub_A_Mem or Instr_E = Sub_A_Dir
or Instr_E = IncA or Instr_E = DecA then
arithmetic_operation <= '1';
else
arithmetic_operation <= '0';
end if;
end process;
------------------------------------------------
-- Instr decoder
------------------------------------------------
process (opcode, flush_signal_FF)
begin
if flush_signal_FF = '0' then
case opcode is
when "000000" => Instr_D <= Add_A_R;
when "000001" => Instr_D <= Add_A_Mem;
when "000010" => Instr_D <= Add_A_Dir;
when "000011" => Instr_D <= Sub_A_R;
when "000100" => Instr_D <= Sub_A_Mem;
when "000101" => Instr_D <= Sub_A_Dir;
when "000110" => Instr_D <= IncA;
when "000111" => Instr_D <= DecA;
when "001000" => Instr_D <= ShiftArithR;
when "001001" => Instr_D <= ShiftArithL;
when "001010" => Instr_D <= ShiftA_R;
when "001011" => Instr_D <= ShiftA_L;
when "001100" => Instr_D <= RRC;
when "001101" => Instr_D <= RLC;
when "001110" => Instr_D <= And_A_R;
when "001111" => Instr_D <= OR_A_R;
when "010000" => Instr_D <= XOR_A_R;
when "010001" => Instr_D <= FlipA;
when "010010" => Instr_D <= NegA;
when "010011" => Instr_D <= Jmp;
when "010100" => Instr_D <= JmpZ;
when "010101" => Instr_D <= JmpOV;
when "010110" => Instr_D <= JmpC;
when "010111" => Instr_D <= Jmp_rel;
when "011000" => Instr_D <= JMPEQ;
when "011001" => Instr_D <= ClearZ;
when "011010" => Instr_D <= ClearOV;
when "011011" => Instr_D <= ClearC;
when "011100" => Instr_D <= ClearACC;
when "011101" => Instr_D <= LoadPC;
when "011110" => Instr_D <= SavePC;
when "011111" => Instr_D <= Load_A_Mem;
when "100000" => Instr_D <= Store_A_Mem;
when "100001" => Instr_D <= Load_R0_Dir;
when "100010" => Instr_D <= Load_R0_Mem;
when "100011" => Instr_D <= load_A_R;
when "100100" => Instr_D <= load_R_A;
when "100101" => Instr_D <= Load_Ind_A ;
when "100110" => Instr_D <= GPIO_DIR;
when "100111" => Instr_D <= GPIO_RD;
when "101000" => Instr_D <= GPIO_WR;
when "111100" => Instr_D <= PUSH;
when "111101" => Instr_D <= POP;
when "111110" => Instr_D <= NOP;
when "111111" => Instr_D <= HALT;
when others => Instr_D <= NOP;
end case;
else
Instr_D <= NOP;
end if;
end process;
end RTL;
| gpl-2.0 | f9a9f2c5d0f454d947e3ca4ba64062b3 | 0.439488 | 4.153277 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wrdata_cntl.vhd | 1 | 91,898 | -------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_wrdata_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 7/8/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR616212
-- - Added special case status push on TLAST error and no addresses have
-- been posted to the AXI Address Channel.
-- ^^^^^^
--
-- DET 8/19/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR616409
-- - The function funct_get_dbeat_residue_width was updated to support
-- 512 and 1024 bit transfer widths.
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Fixed Lint reported excesive line length for line 1558.
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_fifo;
use axi_datamover_v5_1.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| bsd-2-clause | 35c62a0ad9a47797a0dc4a20d1066a29 | 0.419715 | 5.071913 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_007_test_input.fixed_false.vhd | 1 | 524 |
architecture RTL of FIFO is
begin
-- These are passing
a <= '0' when c = '0' else
'1';
a <= '0' when c = '0' else-- Comment
'1' when c = '1' else -- comment
'0' when d = '1' else
'1';
-- Violations below
a <= '0' when c = '0' else
'1' when c = '1' else
'0' when d = '1' else
'1';
a <= '0' when c = '0' else
'1' when c = '1' else
'0' when d =
'1' else
'1';
a <= '0' when c = '0' else
'1' when c =
'1' else
'0' when d = '1' else
'1';
end architecture RTL;
| gpl-3.0 | 6c85fe5df84f6f8c75ae5f0ba3b5f38b | 0.46374 | 2.556098 | false | false | false | false |
Jorge9314/ElectronicaDigital | Impresora2D/Reception_8bits.vhd | 1 | 3,894 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Reception_8bits is
Port ( Divisor_Frecuencia : in STD_LOGIC;
Entrada : in STD_LOGIC;
Mensaje : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
Confirmado : out STD_LOGIC := '0');
end Reception_8bits;
architecture arq_Reception_8bits of Reception_8bits is
signal ParidadPAR : boolean := True;
-- Significa que el estado par es VERDADERO o que es PAR
signal estado : std_logic_vector(3 downto 0) := "0000";
-- El estado va a ser de la siguiente manera
-- "0000" o estado 0 significa el estado de IDLE hasta que llegue un '0'
-- "0001" o estado 1 significa que recibe el primer bit de información
-- "0010" o estado 2 significa que recibe el segundo bit de información
-- ................. significa que recibe los demas bits de información
-- "1011" o estado 11 significa que recibe el BIT DE PARIDAD PAR '0' para par y '1' para impar
-- "1100" o estado 12 significa que recibe el primer BIT DE FINALIZACION '1'
-- "1101" o estado 13 significa que recibe el segundo BIT DE FINALIZACION '1'
-- "0000" o estado 14 significa que vuelve a estar en IDLE hasta el proximo '0'
signal ConfirmadoAux : std_logic := '0';
begin
process begin
wait until rising_edge(Divisor_Frecuencia);
Confirmado <= '0';
case(estado) is
when "0000" =>
if Entrada = '0' then
ParidadPAR <= False; -- En este caso decimos que si no hay 1s es PAR
estado <= "0001";
end if;
when "0001" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(7) <= Entrada;
estado <= "0010";
when "0010" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(6) <= Entrada;
estado <= "0011";
when "0011" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(5) <= Entrada;
estado <= "0100";
when "0100" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(4) <= Entrada;
estado <= "0101";
when "0101" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(3) <= Entrada;
estado <= "0111";
when "0111" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(2) <= Entrada;
estado <= "1000";
when "1000" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(1) <= Entrada;
estado <= "1001";
when "1001" =>
if Entrada = '1' then
ParidadPAR <= not ParidadPar; -- Es IMPAR
end if;
Mensaje(0) <= Entrada;
estado <= "1011";
when "1011" =>
if ParidadPAR then
if Entrada = '1' then
ConfirmadoAux <= '1';
end if;
else
if Entrada = '0' then
ConfirmadoAux <= '1';
end if;
end if;
estado <= "1100";
when "1100" =>
-- Si el bit de parada es 1 se continua normal
-- SI NO pasamos a un estado de error y no se confirma el mensaje
if Entrada = '1' then
estado <= "1101";
else
estado <= "1110"; -- Estado de error (No se envia el mensaje)
end if;
when "1101" =>
if Entrada = '1' then
if ConfirmadoAux = '1' then
Confirmado <= '1';
end if;
estado <= "0000";
ConfirmadoAux <= '0';
else
estado <= "0000";
ConfirmadoAux <= '0';
end if;
when others =>
estado <= "0000";
ConfirmadoAux <= '0';
end case;
-- Si el mensaje se termino de recibir y esta correcto entoces
-- Confirmado es verdadero y se le asigna el Valor a Mensaje
-- y se confirma para que se pueda utilizar el mensaje
end process;
end arq_Reception_8bits;
| gpl-3.0 | 15607f918f03789f781bfdfa8c1567f1 | 0.597586 | 3.039813 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/Debouncer.vhd | 1 | 974 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Debouncer is
Port ( Clk : in STD_LOGIC;
Button : in STD_LOGIC;
Dout : out STD_LOGIC);
end Debouncer;
architecture Behavioral of Debouncer is
signal Counter,nCounter : STD_LOGIC_VECTOR (23 downto 0) := x"000000";
signal ButtonHistory,nButtonHistory : STD_LOGIC_VECTOR (1 downto 0) := "00";
signal nextHistory : STD_LOGIC := '0';
begin
nCounter <= x"FFFFFF" when Counter=x"FFFFFF" and Button='1' else
x"000000" when Counter=x"000000" and Button='0' else
Counter+1 when Button='1' else Counter-1;
nextHistory <= '0' when Counter=x"000000" else '1';
nButtonHistory <= nextHistory & ButtonHistory(1);
Dout <= '1' when ButtonHistory="01" else '0';
process (Clk) begin
if (rising_edge(Clk)) then
Counter <= nCounter;
ButtonHistory <= nButtonHistory;
end if;
end process;
end Behavioral;
| gpl-3.0 | 10ae4081b21728a70eb5b12f49b79362 | 0.671458 | 3.453901 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/Synchronizer.vhd | 2 | 3,132 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in std_logic;
DATAIN : in std_logic_vector(2 downto 0);
ADDRESSX : out std_logic_vector(9 downto 0);
ADDRESSY : out std_logic_vector(8 downto 0)
);
end entity SYNCHRONIZER;
architecture BEHAVIORAL of SYNCHRONIZER is
signal x, nx : std_logic_vector(10 downto 0) := (others=>'0');
signal y, ny : std_logic_vector(20 downto 0) := (others=>'0');
constant tpw : std_logic_vector(1 downto 0) := "00";
constant tbp : std_logic_vector(1 downto 0) := "01";
constant tdp : std_logic_vector(1 downto 0) := "10";
constant tfp : std_logic_vector(1 downto 0) := "11";
signal xstate : std_logic_vector(1 downto 0) := tpw;
signal ystate : std_logic_vector(1 downto 0) := tpw;
signal enabledisplay : std_logic;
signal addressofy, naddressofy : std_logic_vector(8 downto 0);
begin
nx <= x + 1;
ny <= y + 1;
naddressofy <= addressofy + 1;
HS <= '0' when xstate=tpw else
'1';
VS <= '0' when ystate=tpw else
'1';
enabledisplay <= '1' when xstate=tdp and ystate=tdp else
'0';
R <= dataIn(0) when enabledisplay='1' else
'0';
B <= dataIn(1) when enabledisplay='1' else
'0';
G <= dataIn(2) when enabledisplay='1' else
'0';
AddressX <= x(10 downto 1);
AddressY <= addressofy - 30;
process (Clk) is
begin
if (Clk'event and Clk = '1') then
if (xstate=tpw and x(7 downto 1)="1100000") then
x <= (others=>'0');
xstate <= tbp;
elsif (xstate=tbp and x(6 downto 1)="110000") then
x <= (others=>'0');
xstate <= tdp;
elsif (xstate=tdp and x(10 downto 1)="1010000000") then
x <= (others=>'0');
xstate <= tfp;
elsif (xstate=tfp and x(5 downto 1)="10000") then
x <= (others=>'0');
xstate <= tpw;
addressofy <= naddressofy;
else
x <= nx;
end if;
if (ystate=tpw and y(12 downto 1)="11001000000") then
y <= (others=>'0');
ystate <= tbp;
elsif (ystate=tbp and y(16 downto 1)="101101010100000") then
y <= (others=>'0');
ystate <= tdp;
elsif (ystate=tdp and y(20 downto 1)="1011101110000000000") then
y <= (others=>'0');
ystate <= tfp;
elsif (ystate=tfp and y(14 downto 1)="1111101000000") then
y <= (others=>'0');
x <= (others=>'0');
ystate <= tpw;
xstate <= tpw;
addressofy <= (others=>'0');
else
y <= ny;
end if;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | 2d2edff1e28cf92017b71c9dcc33c9b9 | 0.501596 | 3.542986 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 2 | 12,811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
| bsd-2-clause | 14464a0f7dd85176911d748eb5dc38b2 | 0.933885 | 1.878721 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_601_test_input.vhd | 1 | 491 |
architecture ARCH of ENTITY1 is
begin
INST_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 9249b066d96e91082db20ea7afa7e117 | 0.460285 | 2.789773 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic/rule_010_test_input.vhd | 1 | 441 |
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32 -- Comment
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32); -- Comment should stay
PORT (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1');
end entity FIFO;
| gpl-3.0 | 930479d4c70ada1da7fde18c36027748 | 0.575964 | 3.172662 | false | false | false | false |
niketancm/tsea26 | lab2-3/rtl/adder_ctrl.vhd | 1 | 1,543 | library ieee;
use ieee.std_logic_1164.all;
entity adder_ctrl is
port (
function_i : in std_logic_vector(2 downto 0);
opa_sign_i : in std_logic;
mx_opa_inv_o : out std_logic;
mx_ci_o : out std_logic_vector(1 downto 0));
end adder_ctrl;
architecture adder_ctrl_rtl of adder_ctrl is
begin -- adder_ctrl_rtl
adder_logic:process(function_i,opa_sign_i)
begin
--ADD instruction
I1: if(function_i= "000") then
mx_opa_inv_o <= '0';
mx_ci_o <= "00";
--ADDC instructionruction
elsif(function_i = "001") then
mx_opa_inv_o <= '0';
mx_ci_o <= "10";
--SUB instruction
elsif(function_i= "010") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
--SUBC instruction
elsif(function_i = "011") then
mx_opa_inv_o <= '1';
mx_ci_o <= "10";
--CMP instruction
elsif(function_i = "101") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
--ABS instruction
elsif(function_i= "100") then
if(opa_sign_i = '0') then
mx_opa_inv_o <= '0';
mx_ci_o <= "00";
elsif(opa_sign_i= '1') then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
end if;
--MAX instruciton
elsif(function_i= "110") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
--MIN instruciton
elsif(function_i= "111") then
mx_opa_inv_o <= '1';
mx_ci_o <= "01";
end if I1;
end process adder_logic;
end adder_ctrl_rtl;
| gpl-2.0 | 25abc379bf61522b948a83e15934993f | 0.506157 | 2.984526 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/graphicsaccelerator/Debouncer.fixed.vhd | 1 | 1,156 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity DEBOUNCER is
port (
CLK : in std_logic;
BUTTON : in std_logic;
DOUT : out std_logic
);
end entity DEBOUNCER;
architecture BEHAVIORAL of DEBOUNCER is
signal counter, ncounter : std_logic_vector(23 downto 0) := x"000000";
signal buttonhistory, nbuttonhistory : std_logic_vector(1 downto 0) := "00";
signal nexthistory : std_logic := '0';
begin
ncounter <= x"FFFFFF" when counter=x"FFFFFF" and BUTTON='1' else
x"000000" when counter=x"000000" and BUTTON='0' else
counter + 1 when BUTTON='1' else
counter - 1;
nexthistory <= '0' when counter=x"000000" else
'1';
nbuttonhistory <= nexthistory & buttonhistory(1);
DOUT <= '1' when buttonhistory="01" else
'0';
process (CLK) is
begin
if (rising_edge(CLK)) then
counter <= ncounter;
buttonhistory <= nbuttonhistory;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | ee2657ef0f5ffc9d5ef931611e212667 | 0.583045 | 3.765472 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/proc_common_v4_0/hdl/src/vhdl/family_support.vhd | 2 | 328,971 | --------------------------------------------------------------------------------
-- $Id: family_support.vhd,v 1.5.2.55 2010/12/16 15:10:57 ostlerf Exp $
--------------------------------------------------------------------------------
-- family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package family_support is
type families_type is
(
nofamily
, kintex8
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex8
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix8
, artix7
, aartix7
, artix7l
, qartix7
, qartix7l
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 863;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
-- Primitives added for OLYMPUS support
constant u_BUFGCE_DIV : primitives_type := u_ZHOLD_DELAY +1;
constant u_BUFCE_ROW : primitives_type := u_BUFGCE_DIV +1;
constant u_BUFCE_LEAF : primitives_type := u_BUFCE_ROW +1;
constant u_MMCME3_ADV : primitives_type := u_BUFCE_LEAF +1;
constant u_MMCME3_BASE : primitives_type := u_MMCME3_ADV +1;
constant u_DNA_PORTE3 : primitives_type := u_MMCME3_BASE +1;
constant u_FRAME_ECCE3 : primitives_type := u_DNA_PORTE3 +1;
constant u_ICAPE3 : primitives_type := u_FRAME_ECCE3 +1;
constant u_JTAG_SIME3 : primitives_type := u_ICAPE3 +1;
constant u_MCAP : primitives_type := u_JTAG_SIME3 +1;
constant u_SIM_CONFIGE3 : primitives_type := u_MCAP +1;
constant u_SYSMONE1 : primitives_type := u_SIM_CONFIGE3 +1;
constant u_CARRY8 : primitives_type := u_SYSMONE1 +1;
constant u_DSP48E2 : primitives_type := u_CARRY8 +1;
constant u_DSP_A_B_DATA : primitives_type := u_DSP48E2 +1;
constant u_DSP_ALU : primitives_type := u_DSP_A_B_DATA +1;
constant u_DSP_C_DATA : primitives_type := u_DSP_ALU +1;
constant u_DSP_M_DATA : primitives_type := u_DSP_C_DATA +1;
constant u_DSP_MULTIPLIER : primitives_type := u_DSP_M_DATA +1;
constant u_DSP_OUTPUT : primitives_type := u_DSP_MULTIPLIER +1;
constant u_DSP_PREADD : primitives_type := u_DSP_OUTPUT +1;
constant u_DSP_PREADD_DATA : primitives_type := u_DSP_PREADD +1;
constant u_FIFO18E2 : primitives_type := u_DSP_PREADD_DATA +1;
constant u_FIFO36E2 : primitives_type := u_FIFO18E2 +1;
constant u_RAMB18E2 : primitives_type := u_FIFO36E2 +1;
constant u_RAMB36E2 : primitives_type := u_RAMB18E2 +1;
constant u_RAM256X1D : primitives_type := u_RAMB36E2 +1;
constant u_RAM512X1S : primitives_type := u_RAM256X1D +1;
constant u_RAM32M16 : primitives_type := u_RAM512X1S +1;
constant u_RAM64M8 : primitives_type := u_RAM32M16 +1;
constant u_SYNC_UNIT : primitives_type := u_RAM64M8 +1;
constant u_BUFG_GT : primitives_type := u_SYNC_UNIT +1;
constant u_GTHE3_CHANNEL : primitives_type := u_BUFG_GT +1;
constant u_GTHE3_COMMON : primitives_type := u_GTHE3_CHANNEL +1;
constant u_GTPE3_CHANNEL : primitives_type := u_GTHE3_COMMON +1;
constant u_GTPE3_COMMON : primitives_type := u_GTPE3_CHANNEL +1;
constant u_GTY : primitives_type := u_GTPE3_COMMON +1;
constant u_GTZE2_OCTAL : primitives_type := u_GTY +1;
constant u_IBUFDS_GTE3 : primitives_type := u_GTZE2_OCTAL +1;
constant u_OBUFDS_GTE3 : primitives_type := u_IBUFDS_GTE3 +1;
constant u_PCIE_3_1 : primitives_type := u_OBUFDS_GTE3 +1;
constant u_IDELAYE3 : primitives_type := u_PCIE_3_1 +1;
constant u_ISERDESE3 : primitives_type := u_IDELAYE3 +1;
constant u_ODELAYE3 : primitives_type := u_ISERDESE3 +1;
constant u_OSERDESE3 : primitives_type := u_ODELAYE3 +1;
constant u_TXPLL : primitives_type := u_OSERDESE3 +1;
constant u_BITSLICE_CONTROL : primitives_type := u_TXPLL +1;
constant u_RX_BITSLICE : primitives_type := u_BITSLICE_CONTROL +1;
constant u_TX_BITSLICE : primitives_type := u_RX_BITSLICE +1;
constant u_IBUFCTRL : primitives_type := u_TX_BITSLICE +1;
constant u_DIFFINBUF : primitives_type := u_IBUFCTRL +1;
constant u_ADDMACC_MACRO : primitives_type := u_DIFFINBUF +1;
constant u_ADDSUB_MACRO : primitives_type := u_ADDMACC_MACRO +1;
constant u_BRAM_SDP_MACRO : primitives_type := u_ADDSUB_MACRO +1;
constant u_BRAM_SINGLE_MACRO : primitives_type := u_BRAM_SDP_MACRO +1;
constant u_BRAM_TDP_MACRO : primitives_type := u_BRAM_SINGLE_MACRO +1;
constant u_COUNTER_LOAD_MACRO : primitives_type := u_BRAM_TDP_MACRO +1;
constant u_COUNTER_TC_MACRO : primitives_type := u_COUNTER_LOAD_MACRO +1;
constant u_EQ_COMPARE_MACRO : primitives_type := u_COUNTER_TC_MACRO +1;
constant u_FIFO_DUALCLOCK_MACRO : primitives_type := u_EQ_COMPARE_MACRO +1;
constant u_FIFO_SYNC_MACRO : primitives_type := u_FIFO_DUALCLOCK_MACRO +1;
constant u_MACC_MACRO : primitives_type := u_FIFO_SYNC_MACRO +1;
constant u_MULT_MACRO : primitives_type := u_MACC_MACRO +1;
constant u_PLLE3_ADV : primitives_type := u_MULT_MACRO +1;
constant u_PLLE3_BASE : primitives_type := u_PLLE3_ADV +1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package family_support;
package body family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qkintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qkintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
artix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qartix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n,
n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n,
y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y,
n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex8 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintex8 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y),
artix8 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y,
y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n,
y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y,
y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n,
y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n,
n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, y, y, y, y, y, y, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex8 => return "virtex8" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex8 => return "kintex8" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix8 => return "artix8" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when qartix7l => return "qartix7l" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- Virtex7 Root family
if (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7l" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- Kintex8 Root family
Elsif (equalIgnoringCase(family_in, "kintex8" )) Then return "kintex8" ;
-- Virtex8 Root family
Elsif (equalIgnoringCase(family_in, "virtex8" )) Then return "virtex8" ;
-- artix8 Root family
Elsif (equalIgnoringCase(family_in, "artix8" )) Then return "artix8" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body family_support;
| bsd-2-clause | f999149cf1e67d3810519042e0347684 | 0.320035 | 3.090516 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_006_test_input.fixed.vhd | 1 | 695 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
begin
end;
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
signal a : std_logic;
begin
end;
end generate;
IF_LABEL : if a = '1' generate
signal a : std_logic;
begin
end;
end generate;
CASE_LABEL : case data generate
when a = b =>
signal a : std_logic;
begin
end;
end generate;
end;
| gpl-3.0 | d1b6bb569b3fb869cee97344a6d4d72d | 0.578417 | 3.527919 | false | false | false | false |
rjarzmik/mips_processor | Caches/memory_eviction_internal.vhd | 1 | 2,528 | -------------------------------------------------------------------------------
-- Title : Tags memory with arrays implementation
-- Project : MIPS processor implementation, compatible MIPS-1
-------------------------------------------------------------------------------
-- File : memory_eviction_internal.vhd
-- Author : Robert Jarzmik (Intel) <[email protected]>
-- Company :
-- Created : 2016-12-15
-- Last update: 2016-12-29
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-15 1.0 rjarzmik Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cache_defs.alloc_entry_t;
-------------------------------------------------------------------------------
entity memory_eviction_internal is
generic
(
ADDR_WIDTH : integer := 7;
DEBUG : boolean := false
);
port
(
clock : in std_logic;
raddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
waddr : in std_logic_vector (ADDR_WIDTH - 1 downto 0);
data : in alloc_entry_t;
rren : in std_logic;
wren : in std_logic;
q : out alloc_entry_t := (others => '0')
);
end entity memory_eviction_internal;
architecture infer of memory_eviction_internal is
type mem_block_t is array(0 to 2**ADDR_WIDTH - 1) of alloc_entry_t;
constant MEMORY_RESET : mem_block_t := (others => (others => '0'));
signal memory : mem_block_t := MEMORY_RESET;
signal raddr_reg : std_logic_vector (ADDR_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture str
process(clock, memory, raddr_reg)
begin
if rising_edge(clock) then
if rren = '1' then
raddr_reg <= raddr;
end if;
if wren = '1' then
memory(to_integer(unsigned(waddr))) <= data;
-- pragma translate_off
if DEBUG then
report "Evictmem: [" & to_hstring(waddr) & "] <= " & to_hstring(data);
end if;
-- pragma translate_on
end if;
end if;
q <= memory(to_integer(unsigned(raddr_reg)));
end process;
end architecture infer;
| gpl-3.0 | 6d4694d736fc7891f1803960a5f26ae2 | 0.465981 | 4.157895 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/FLAGS.vhd | 1 | 2,691 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:14:49 11/02/2015
-- Design Name:
-- Module Name: FLAGS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FLAGS is
Port ( FLG_C_SET : in STD_LOGIC;
FLG_C_CLR : in STD_LOGIC;
FLG_C_LD : in STD_LOGIC;
FLG_Z_LD : in STD_LOGIC;
FLG_LD_SEL : in STD_LOGIC;
FLG_SHAD_LD : in STD_LOGIC;
C : in STD_LOGIC;
Z : in STD_LOGIC;
CLK : in STD_LOGIC;
C_FLAG : out STD_LOGIC;
Z_FLAG : out STD_LOGIC);
end FLAGS;
architecture Behavioral of FLAGS is
component FlagReg
Port ( D : in STD_LOGIC; --flag input
LD : in STD_LOGIC; --load Q with the D value
SET : in STD_LOGIC; --set the flag to '1'
CLR : in STD_LOGIC; --clear the flag to '0'
CLK : in STD_LOGIC; --system clock
Q : out STD_LOGIC); --flag output
end component;
component SingleMux
port ( TO_FLAG : out std_logic;
FROM_ALU : in std_logic;
FROM_SHAD_FLG : in std_logic;
SEL : in std_logic);
end component;
signal SHAD_z_Z_MUX, SHAD_C_C_MUX, Z_Mux_flg, C_Mux_flg, Z_flg_Shad_Flg, C_flg_Shad_Flg: std_logic;
begin
C_FLAG <= C_flg_shad_flg;
Z_FLAG <= Z_flg_shad_flg;
C_FLG: FlagReg
port map ( D => c_mux_flg,
LD => FLG_C_LD,
SET => FLG_C_SET,
CLR => FLG_C_CLR,
CLK => CLK,
Q => C_flg_shad_flg);
Z_FLG: FlagReg
port map ( D => z_mux_flg,
LD => FLG_Z_LD,
SET => '0',
CLR => '0',
CLK => CLK,
Q => Z_flg_shad_flg);
SHAD_Z: FlagReg
port map ( D => z_flg_shad_flg,
LD => flg_shad_ld,
SET => '0',
CLR => '0',
CLK => CLK,
Q => shad_z_z_mux);
SHAD_C: FlagReg
port map ( D => c_flg_shad_flg,
LD => flg_shad_ld,
SET => '0',
CLR => '0',
CLK => CLK,
Q => shad_c_c_mux);
Z_MUX: SingleMux
port map ( TO_FLAG => z_mux_flg,
FROM_ALU => z,
FROM_SHAD_FLG => shad_z_z_mux,
SEL => flg_ld_sel);
C_MUX: SingleMux
port map ( TO_FLAG => c_mux_flg,
FROM_ALU => c,
FROM_SHAD_FLG => shad_c_c_mux,
SEL => flg_ld_sel);
end Behavioral;
| mit | 297a169d94c08c67311ef4101d2fba25 | 0.464511 | 2.826681 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/simulation/daala_zynq_axi_bram_ctrl_0_bram_0_tb.vhd | 1 | 4,603 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: daala_zynq_axi_bram_ctrl_0_bram_0_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY daala_zynq_axi_bram_ctrl_0_bram_0_tb IS
END ENTITY;
ARCHITECTURE daala_zynq_axi_bram_ctrl_0_bram_0_tb_ARCH OF daala_zynq_axi_bram_ctrl_0_bram_0_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 200 NS;
CLKB <= NOT CLKB;
WAIT FOR 200 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(6)='1';
IF( STATUS(5 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
daala_zynq_axi_bram_ctrl_0_bram_0_synth_inst:ENTITY work.daala_zynq_axi_bram_ctrl_0_bram_0_synth
GENERIC MAP (
C_ROM_SYNTH => 0
)
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLKB,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-2-clause | 59b71b950a810a6f89013e70bc00a5be | 0.618075 | 4.358902 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/code_examples/alignments.vhd | 1 | 1,222 |
package body my_pkg is
procedure some_proc (
a : integer;
b : integer
) is
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
) ;
variable a, b, c, d, e, f, g : integer;
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
) ;
begin
some_var := other_proc(a, b, c
d, e, f, g, h
i, j, k, l, m
);
some_other_var := other_other_proc(z);
end procedure some_proc;
end package body my_pkg;
architecture arch of ent is
begin
proc_label : process is
begin
var1 := 1;
sig1 <= 2 &
3 &
4;
sig2 <= 5;
sig3 <= 6;
end process proc_label;
PROC2_LABEL : process is
begin
if rising_edge(some_clk) then
a <= b;
end if;
end process PROC_LABEL;
end architecture arch;
| gpl-3.0 | f75e0b8991883b2edb37a939d0d60d11 | 0.4018 | 4.114478 | false | false | false | false |
wklimann/PCM3168 | CLK_GEN/CLK_GEN.vhd | 1 | 2,812 | ---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 07:25:11 11/Okt/2013
-- Design Name: clk_gen
--
-- Description:
--
-- This module is a simple clock divider which generates the BIT_CLK and the LR_CLK
-- signals for the I2S interfaces.
--
-- It's coded as a generic VHDL entity, so developer can choose the proper signal
-- width (8/16/24/32 bit) -> x BIT_CLK cycles per one LR_CLK cycle
--
-- Input takes:
-- -CLK - system clock
-- -Reset - system reset
--
-- Output provides:
-- -BIT_CLK - bit clock output
-- -LR_CLK - left/right selection -> 0 = left and 1 = right.
--
--
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
-- width: How many bits (from MSB) are gathered from the serial I2S input
generic(
width : integer := 24;
clk_divider : integer := 4 -- a multiple of 2
);
port(
-- Input ports
CLK : in std_logic; --System clock
-- Control ports
RESET : in std_logic; --Asynchronous Reset (Active Low)
-- Output ports
BIT_CLK : out std_logic; --Bit Clock
LR_CLK : out std_logic --Left/Right Clock
);
end clk_gen;
architecture rtl of clk_gen is
--signals
signal s_counter_bit : integer range 0 to clk_divider;
signal s_counter_lr : integer range 0 to width;
signal s_bit_clk : std_logic;
signal s_lr_clk : std_logic;
begin
--------------------------------------------------------------------------------
-- generates the BIT_CLK clock
--------------------------------------------------------------------------------
p_bit_clk: process(RESET, CLK)
variable v_lr_clk_enable : std_logic;
begin
if(RESET = '0') then
BIT_CLK <= '0';
LR_CLK <= '0';
s_counter_bit <= 0 ;
s_counter_lr <= 0 ;
s_bit_clk <= '0';
s_lr_clk <= '1';
v_lr_clk_enable := '0';
elsif(CLK'event and CLK = '1') then
if(s_counter_bit < (clk_divider-1)/2) then
s_counter_bit <= s_counter_bit + 1;
else
s_bit_clk <= not s_bit_clk;
s_counter_bit <= 0;
if(s_bit_clk = '1') then
v_lr_clk_enable := '1';
end if;
end if;
if(v_lr_clk_enable = '1') then
if(s_counter_lr = 0) then
s_lr_clk <= not s_lr_clk;
s_counter_lr <= s_counter_lr + 1;
elsif(s_counter_lr = width-1) then
s_counter_lr <= 0;
else
s_counter_lr <= s_counter_lr + 1;
end if;
v_lr_clk_enable := '0';
end if;
end if; -- reset / rising_edge
BIT_CLK <= s_bit_clk;
LR_CLK <= s_lr_clk;
end process p_bit_clk;
end rtl;
| gpl-2.0 | c9eac0c1d3d654ebfe9f52bd54e7e227 | 0.491465 | 3.195455 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/delay_bit.vhd | 1 | 9,480 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5280)
`protect data_block
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`protect end_protected
| mit | 14b6f9eb70d11a4ad467c932af0785b1 | 0.922468 | 1.914378 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable_assignment/rule_003_test_input.fixed.vhd | 1 | 639 |
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
-- Violations below
architecture RTL of FIFO is
begin
process
begin
a := b;
a := b;
x := z when b = 0 else y;
x := z when b = 0 else y;
with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
| gpl-3.0 | 75caf76f43690801a4f0c229e197eb76 | 0.583725 | 3.398936 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable_assignment/rule_400_test_input.vhd | 1 | 1,812 |
architecture rtl of fifo is
begin
process begin
my_signal := '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal := '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal := '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal := '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal := '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal := '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal :=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal :=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end process;
end architecture rtl;
| gpl-3.0 | 831ba908e8501ba989ffadc71470fe28 | 0.510486 | 3.330882 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_gen_ecc_decoder.vhd | 2 | 24,873 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ghVMkFjIL0GYAeVXGsR/AYSi3dpIyHIi42C3Jf2+mwEBTZoMB5e9bevdUQbbYk20mGqXOhBsrI6h
QayAk7iMBQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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`protect end_protected
| bsd-2-clause | 6792dc11ce4d78444574b0f37b4236bc | 0.944277 | 1.8434 | false | false | false | false |
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