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`protect end_protected
| bsd-2-clause | c576d630f1423edd39f650a7ffa3493c | 0.947342 | 1.823749 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/builtin/builtin_top.vhd | 2 | 47,568 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| bsd-2-clause | 7752a6fd2742045281b24248fa155c24 | 0.948873 | 1.825536 | false | false | false | false |
Logistic1994/CPU | module_P0.vhd | 1 | 1,663 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:20:36 05/29/2015
-- Design Name:
-- Module Name: module_P0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity module_P0 is
port(
clk_P0: in std_logic;
nreset: in std_logic;
P0_CS: in std_logic;
nP0_IEN: in std_logic; --ÊäÈëʹÄÜ
nP0_OEN: in std_logic; --Êä³öʹÄÜ
P0_IN: in std_logic_vector(7 downto 0);
P0_OUT: out std_logic_vector(7 downto 0);
datai: in std_logic_vector(7 downto 0);
datao: out std_logic_vector(7 downto 0);
do: out std_logic);
end module_P0;
architecture Behavioral of module_P0 is
begin
process(nreset, clk_P0)
begin
if nreset = '0' then
P0_OUT <= (others => '0');
elsif rising_edge(clk_P0) then
if P0_CS = '1' then
if nP0_IEN = '0' then
datao <= P0_IN;
do <= '1';
elsif nP0_OEN = '0' then
P0_OUT <= datai;
datao <= (others => 'Z');
do <= '0';
else
datao <= (others => 'Z');
do <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 7f5d55061758b5efb290d11ff7f13e33 | 0.568851 | 2.985637 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_018_test_input.fixed_upper.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | d4de91092accd03983177e7f3f171bfd | 0.4618 | 3.308989 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/compare.vhd | 1 | 13,460 | `protect begin_protected
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`protect end_protected
| mit | 46706b84aef61fa64451d8c1d610c290 | 0.93321 | 1.880676 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/smart_tab/spi_master.fixed.vhd | 1 | 41,199 | -----------------------------------------------------------------------------------------------------------------------
-- Author: Jonny Doin, [email protected], [email protected]
--
-- Create Date: 12:18:12 04/25/2011
-- Module Name: SPI_MASTER - RTL
-- Project Name: SPI MASTER / SLAVE INTERFACE
-- Target Devices: Spartan-6
-- Tool versions: ISE 13.1
-- Description:
--
-- This block is the SPI master interface, implemented in one single entity.
-- All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
-- a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
-- All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
-- 'sclk_i' clock.
-- For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
-- Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two
-- clock domains.
-- The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
-- It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling
-- ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
--
-- SPI CLOCK GENERATION
-- ====================
--
-- The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference
-- clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the
-- SPI_2X clock, which is 2x the desired SCK frequency.
-- All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
-- at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
-- by combinatorial clock dividers outputs.
-- The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
--
-- PARALLEL WRITE INTERFACE
-- ========================
-- The parallel interface has an input port 'di_i' and an output port 'do_o'.
-- Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
-- that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the
-- next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
-- For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
-- cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
-- If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
-- The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
-- if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
-- enters idle state and deasserts SSEL.
-- When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering
-- idle state, if a previously loaded data has already been transferred.
--
-- PARALLEL WRITE SEQUENCE
-- =======================
-- __ __ __ __ __ __ __
-- pclk_i __/ \__/ \__/ \__/ \__/ \__/ \__/ \... -- parallel interface clock
-- ___________
-- di_req_o ________/ \_____________________... -- 'di_req_o' asserted on rising edge of 'pclk_i'
-- ______________ ___________________________...
-- di_i __old_data____X______new_data_____________... -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
-- _______
-- wren_i __________________________/ \_______... -- user strobes 'wren_i' for one cycle of 'pclk_i'
--
--
-- PARALLEL READ INTERFACE
-- =======================
-- An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
-- the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
-- The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
-- 'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
-- When the interface is idle, data at the 'do_o' port holds the last word received.
--
-- PARALLEL READ SEQUENCE
-- ======================
-- ______ ______ ______ ______
-- spi_clk bit1 \______/ bitN \______/bitN-1\______/bitN-2\__... -- internal spi 2x base clock
-- _ __ __ __ __ __ __ __ __
-- pclk_i \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \_... -- parallel interface clock (may be async to sclk_i)
-- _____________ _____________________________________... -- 1) rx data is transferred to 'do_buffer_reg'
-- do_o ___old_data__X__________new_data___________________... -- after last rx bit, at rising 'spi_clk'.
-- ____________
-- do_valid_o ____________________________/ \_________... -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
-- -- on the 3rd 'pclk_i' rising edge.
--
--
-- The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
-- but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
-- of the interface, for full duplex operation.
--
-- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
-- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
--
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
--
-- This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
--
-- Author(s): Jonny Doin, [email protected], [email protected]
--
-- Copyright (C) 2011 Jonny Doin
-- -----------------------------
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains the original copyright notice and the associated
-- disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser
-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download
-- it from http://www.gnu.org/licenses/lgpl.txt
--
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
--
-- 2011/04/28 v0.01.0010 [JD] shifter implemented as a sequential process. timing problems and async issues in synthesis.
-- 2011/05/01 v0.01.0030 [JD] changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
-- 2011/05/05 v0.01.0034 [JD] added an internal buffer register for rx_data, to allow greater liberty in data load/store.
-- 2011/05/08 v0.10.0038 [JD] increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
-- logic, based on generics, and do_valid_o signal.
-- 2011/05/13 v0.20.0045 [JD] streamlined signal names, added PREFETCH parameter, added assertions.
-- 2011/05/17 v0.80.0049 [JD] added explicit clock synchronization circuitry across clock boundaries.
-- 2011/05/18 v0.95.0050 [JD] clock generation circuitry, with generators for all-rising-edge clock core.
-- 2011/06/05 v0.96.0053 [JD] changed async clear to sync resets.
-- 2011/06/07 v0.97.0065 [JD] added cross-clock buffers, fixed fsm async glitches.
-- 2011/06/09 v0.97.0068 [JD] reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
-- synthesis LUT overhead in Spartan-6 architecture.
-- 2011/06/11 v0.97.0075 [JD] redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
-- 2011/06/12 v0.97.0079 [JD] streamlined wr_ack for all cases and eliminated unnecessary register resets.
-- 2011/06/14 v0.97.0083 [JD] (bug CPHA effect) : redesigned SCK output circuit.
-- (minor bug) : removed fsm registers from (not rst_i) chip enable.
-- 2011/06/15 v0.97.0086 [JD] removed master MISO input register, to relax MISO data setup time (to get higher speed).
-- 2011/07/09 v1.00.0095 [JD] changed all clocking scheme to use a single high-speed clock with clock enables to control lower
-- frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
-- 2011/07/10 v1.00.0098 [JD] implemented SCK clock divider circuit to generate spi clock directly from system clock.
-- 2011/07/10 v1.10.0075 [JD] verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz,
-- 7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
-- 2011/07/16 v1.11.0080 [JD] verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
-- 2011/07/17 v1.11.0080 [JD] BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
-- BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
-- 2011/07/18 v1.12.0105 [JD] CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
-- for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
-- 2011/07/24 v1.13.0125 [JD] FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
-- Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
-- 2011/07/29 v1.14.0130 [JD] Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
-- 2011/08/01 v1.15.0135 [JD] Fixed latch inference for spi_mosi_o driver at the fsm.
-- The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
-- 2011/08/04 v1.15.0136 [JD] Fixed assertions (PREFETCH >= 1) and minor comment bugs.
--
-----------------------------------------------------------------------------------------------------------------------
-- TODO
-- ====
--
-----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
--================================================================================================================
-- SYNTHESIS CONSIDERATIONS
-- ========================
-- There are several output ports that are used to simulate and verify the core operation.
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
-- circuitry.
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
-- synthesis tool will remove the receive logic from the generated circuitry.
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
-- integrated to your circuit.
--================================================================================================================
entity spi_master is
generic (
n : positive := 32; -- 32bit serial word length is default
cpol : std_logic := '0'; -- SPI mode selection (mode 0 default)
cpha : std_logic := '0'; -- CPOL = clock polarity, CPHA = clock phase.
prefetch : positive := 2; -- prefetch lookahead cycles
spi_2x_clk_div : positive := 5 -- for a 100MHz sclk_i, yields a 10MHz SCK
);
port (
sclk_i : in std_logic := 'X'; -- high-speed serial interface system clock
pclk_i : in std_logic := 'X'; -- high-speed parallel interface system clock
rst_i : in std_logic := 'X'; -- reset core
---- serial interface ----
spi_ssel_o : out std_logic; -- spi bus slave select line
spi_sck_o : out std_logic; -- spi bus sck
spi_mosi_o : out std_logic; -- spi bus mosi output
spi_miso_i : in std_logic := 'X'; -- spi bus spi_miso_i input
---- parallel interface ----
di_req_o : out std_logic; -- preload lookahead data request line
di_i : in std_logic_vector(n - 1 downto 0) := (others => 'X'); -- parallel data in (clocked on rising spi_clk after last bit)
wren_i : in std_logic := 'X'; -- user data write enable, starts transmission when interface is idle
wr_ack_o : out std_logic; -- write acknowledge
do_valid_o : out std_logic; -- do_o data valid signal, valid during one spi_clk rising edge.
do_o : out std_logic_vector(n - 1 downto 0); -- parallel output (clocked on rising spi_clk after last bit)
--- debug ports: can be removed or left unconnected for the application circuit ---
sck_ena_o : out std_logic; -- debug: internal sck enable signal
sck_ena_ce_o : out std_logic; -- debug: internal sck clock enable signal
do_transfer_o : out std_logic; -- debug: internal transfer driver
wren_o : out std_logic; -- debug: internal state of the wren_i pulse stretcher
rx_bit_reg_o : out std_logic; -- debug: internal rx bit
state_dbg_o : out std_logic_vector(3 downto 0); -- debug: internal state register
core_clk_o : out std_logic;
core_n_clk_o : out std_logic;
core_ce_o : out std_logic;
core_n_ce_o : out std_logic;
sh_reg_dbg_o : out std_logic_vector(n - 1 downto 0) -- debug: internal shift register
);
end entity spi_master;
--================================================================================================================
-- this architecture is a pipelined register-transfer description.
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
--================================================================================================================
architecture rtl of spi_master is
-- core clocks, generated from 'sclk_i': initialized at GSR to differential values
signal core_clk : std_logic := '0'; -- continuous core clock, positive logic
signal core_n_clk : std_logic := '1'; -- continuous core clock, negative logic
signal core_ce : std_logic := '0'; -- core clock enable, positive logic
signal core_n_ce : std_logic := '1'; -- core clock enable, negative logic
-- spi bus clock, generated from the CPOL selected core clock polarity
signal spi_2x_ce : std_logic := '1'; -- spi_2x clock enable
signal spi_clk : std_logic := '0'; -- spi bus output clock
signal spi_clk_reg : std_logic; -- output pipeline delay for spi sck (do NOT global initialize)
-- core fsm clock enables
signal fsm_ce : std_logic := '1'; -- fsm clock enable
signal sck_ena_ce : std_logic := '1'; -- SCK clock enable
signal samp_ce : std_logic := '1'; -- data sampling clock enable
--
-- GLOBAL RESET:
-- all signals are initialized to zero at GSR (global set/reset) by giving explicit
-- initialization values at declaration. This is needed for all Xilinx FPGAs, and
-- especially for the Spartan-6 and newer CLB architectures, where a async reset can
-- reduce the usability of the slice registers, due to the need to share the control
-- set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
-- By using GSR for the initialization, and reducing async RESET local init to the bare
-- essential, the model achieves better LUT/FF packing and CLB usability.
--
-- internal state signals for register and combinatorial stages
signal state_next : natural range n + 1 downto 0 := 0;
signal state_reg : natural range n + 1 downto 0 := 0;
-- shifter signals for register and combinatorial stages
signal sh_next : std_logic_vector(n - 1 downto 0);
signal sh_reg : std_logic_vector(n - 1 downto 0);
-- input bit sampled buffer
signal rx_bit_reg : std_logic := '0';
-- buffered di_i data signals for register and combinatorial stages
signal di_reg : std_logic_vector(n - 1 downto 0);
-- internal wren_i stretcher for fsm combinatorial stage
signal wren : std_logic;
signal wr_ack_next : std_logic := '0';
signal wr_ack_reg : std_logic := '0';
-- internal SSEL enable control signals
signal ssel_ena_next : std_logic := '0';
signal ssel_ena_reg : std_logic := '0';
-- internal SCK enable control signals
signal sck_ena_next : std_logic;
signal sck_ena_reg : std_logic;
-- buffered do_o data signals for register and combinatorial stages
signal do_buffer_next : std_logic_vector(n - 1 downto 0);
signal do_buffer_reg : std_logic_vector(n - 1 downto 0);
-- internal signal to flag transfer to do_buffer_reg
signal do_transfer_next : std_logic := '0';
signal do_transfer_reg : std_logic := '0';
-- internal input data request signal
signal di_req_next : std_logic := '0';
signal di_req_reg : std_logic := '0';
-- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
signal do_valid_a : std_logic := '0';
signal do_valid_b : std_logic := '0';
signal do_valid_c : std_logic := '0';
signal do_valid_d : std_logic := '0';
signal do_valid_next : std_logic := '0';
signal do_valid_o_reg : std_logic := '0';
-- cross-clock di_req_reg -> di_req_o_reg pipeline
signal di_req_o_a : std_logic := '0';
signal di_req_o_b : std_logic := '0';
signal di_req_o_c : std_logic := '0';
signal di_req_o_d : std_logic := '0';
signal di_req_o_next : std_logic := '1';
signal di_req_o_reg : std_logic := '1';
begin
--=============================================================================================
-- GENERICS CONSTRAINTS CHECKING
--=============================================================================================
-- minimum word width is 8 bits
assert n >= 8
report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
severity FAILURE;
-- minimum prefetch lookahead check
assert prefetch >= 1
report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
severity FAILURE;
-- maximum prefetch lookahead check
assert prefetch <= n - 5
report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
severity FAILURE;
-- SPI_2X_CLK_DIV clock divider value must not be zero
assert spi_2x_clk_div > 0
report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
severity FAILURE;
--=============================================================================================
-- CLOCK GENERATION
--=============================================================================================
-- In order to preserve global clocking resources, the core clocking scheme is completely based
-- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
-- the spi clock generator and the input sampling clock.
-- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock
-- for the core clocking.
-- The 2 clock phases are generated by separate and synchronous FFs, and should have only
-- differential interconnect delay skew.
-- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock
-- enables are used to control clocking of all internal synchronous circuitry.
-- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output,
-- based on the configuration of CPOL and CPHA.
-- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
-- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
-----------------------------------------------------------------------------------------------
-- generate the 2x spi base clock enable from the serial high-speed input clock
spi_2x_ce_gen_proc : process (sclk_i) is
variable clk_cnt : integer range spi_2x_clk_div - 1 downto 0 := 0;
begin
if (sclk_i'event and sclk_i = '1') then
if (clk_cnt = spi_2x_clk_div - 1) then
spi_2x_ce <= '1';
clk_cnt := 0;
else
spi_2x_ce <= '0';
clk_cnt := clk_cnt + 1;
end if;
end if;
end process spi_2x_ce_gen_proc;
-----------------------------------------------------------------------------------------------
-- generate the core antiphase clocks and clock enables from the 2x base CE.
core_clock_gen_proc : process (sclk_i) is
begin
if (sclk_i'event and sclk_i = '1') then
if (spi_2x_ce = '1') then
-- generate the 2 antiphase core clocks
core_clk <= core_n_clk;
core_n_clk <= not core_n_clk;
-- generate the 2 phase core clock enables
core_ce <= core_n_clk;
core_n_ce <= not core_n_clk;
else
core_ce <= '0';
core_n_ce <= '0';
end if;
end if;
end process core_clock_gen_proc;
--=============================================================================================
-- GENERATE BLOCKS
--=============================================================================================
-- spi clk generator: generate spi_clk from core_clk depending on CPOL
spi_sck_cpol_0_proc : if cpol = '0' generate
begin
spi_clk <= core_clk; -- for CPOL=0, spi clk has idle LOW
end generate spi_sck_cpol_0_proc;
spi_sck_cpol_1_proc : if cpol = '1' generate
begin
spi_clk <= core_n_clk; -- for CPOL=1, spi clk has idle HIGH
end generate spi_sck_cpol_1_proc;
-----------------------------------------------------------------------------------------------
-- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
-- always sample data at the half-cycle of the fsm update cell
samp_ce_cpha_0_proc : if cpha = '0' generate
begin
samp_ce <= core_ce;
end generate samp_ce_cpha_0_proc;
samp_ce_cpha_1_proc : if cpha = '1' generate
begin
samp_ce <= core_n_ce;
end generate samp_ce_cpha_1_proc;
-----------------------------------------------------------------------------------------------
-- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
fsm_ce_cpha_0_proc : if cpha = '0' generate
begin
fsm_ce <= core_n_ce; -- for CPHA=0, latch registers at rising edge of negative core clock enable
end generate fsm_ce_cpha_0_proc;
fsm_ce_cpha_1_proc : if cpha = '1' generate
begin
fsm_ce <= core_ce; -- for CPHA=1, latch registers at rising edge of positive core clock enable
end generate fsm_ce_cpha_1_proc;
-----------------------------------------------------------------------------------------------
-- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
sck_ena_ce <= core_n_ce; -- for CPHA=1, SCK is advanced one-half cycle
--=============================================================================================
-- REGISTERED INPUTS
--=============================================================================================
-- rx bit flop: capture rx bit after SAMPLE edge of sck
rx_bit_proc : process (sclk_i, spi_miso_i) is
begin
if (sclk_i'event and sclk_i = '1') then
if (samp_ce = '1') then
rx_bit_reg <= spi_miso_i;
end if;
end if;
end process rx_bit_proc;
--=============================================================================================
-- CROSS-CLOCK PIPELINE TRANSFER LOGIC
--=============================================================================================
-- do_valid_o and di_req_o strobe output logic
-- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a
-- fixed-length delayed pulse for the output flags, at the parallel clock domain
out_transfer_proc : process (pclk_i, do_transfer_reg, di_req_reg,
do_valid_a, do_valid_b, do_valid_d,
di_req_o_a, di_req_o_b, di_req_o_d) is
begin
if (pclk_i'event and pclk_i = '1') then -- clock at parallel port clock
-- do_transfer_reg -> do_valid_o_reg
do_valid_a <= do_transfer_reg; -- the input signal must be at least 2 clocks long
do_valid_b <= do_valid_a; -- feed it to a ripple chain of FFDs
do_valid_c <= do_valid_b;
do_valid_d <= do_valid_c;
do_valid_o_reg <= do_valid_next; -- registered output pulse
--------------------------------
-- di_req_reg -> di_req_o_reg
di_req_o_a <= di_req_reg; -- the input signal must be at least 2 clocks long
di_req_o_b <= di_req_o_a; -- feed it to a ripple chain of FFDs
di_req_o_c <= di_req_o_b;
di_req_o_d <= di_req_o_c;
di_req_o_reg <= di_req_o_next; -- registered output pulse
end if;
-- generate a 2-clocks pulse at the 3rd clock cycle
do_valid_next <= do_valid_a and do_valid_b and not do_valid_d;
di_req_o_next <= di_req_o_a and di_req_o_b and not di_req_o_d;
end process out_transfer_proc;
-- parallel load input registers: data register and write enable
in_transfer_proc : process (pclk_i, wren_i, wr_ack_reg) is
begin
-- registered data input, input register with clock enable
if (pclk_i'event and pclk_i = '1') then
if (wren_i = '1') then
di_reg <= di_i; -- parallel data input buffer register
end if;
end if;
-- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
if (pclk_i'event and pclk_i = '1') then
if (wren_i = '1') then -- wren_i is the sync preset for wren
wren <= '1';
elsif (wr_ack_reg = '1') then -- wr_ack is the sync reset for wren
wren <= '0';
end if;
end if;
end process in_transfer_proc;
--=============================================================================================
-- REGISTER TRANSFER PROCESSES
--=============================================================================================
-- fsm state and data registers: synchronous to the spi base reference clock
core_reg_proc : process (sclk_i) is
begin
-- FF registers clocked on rising edge and cleared on sync rst_i
if (sclk_i'event and sclk_i = '1') then
if (rst_i = '1') then -- sync reset
state_reg <= 0; -- only provide local reset for the state machine
elsif (fsm_ce = '1') then -- fsm_ce is clock enable for the fsm
state_reg <= state_next; -- state register
end if;
end if;
-- FF registers clocked synchronous to the fsm state
if (sclk_i'event and sclk_i = '1') then
if (fsm_ce = '1') then
sh_reg <= sh_next; -- shift register
ssel_ena_reg <= ssel_ena_next; -- spi select enable
do_buffer_reg <= do_buffer_next; -- registered output data buffer
do_transfer_reg <= do_transfer_next; -- output data transferred to buffer
di_req_reg <= di_req_next; -- input data request
wr_ack_reg <= wr_ack_next; -- write acknowledge for data load synchronization
end if;
end if;
-- FF registers clocked one-half cycle earlier than the fsm state
if (sclk_i'event and sclk_i = '1') then
if (sck_ena_ce = '1') then
sck_ena_reg <= sck_ena_next; -- spi clock enable: look ahead logic
end if;
end if;
end process core_reg_proc;
--=============================================================================================
-- COMBINATORIAL LOGIC PROCESSES
--=============================================================================================
-- state and datapath combinatorial logic
core_combi_proc : process (sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren) is
begin
sh_next <= sh_reg; -- all output signals are assigned to (avoid latches)
ssel_ena_next <= ssel_ena_reg; -- controls the slave select line
sck_ena_next <= sck_ena_reg; -- controls the clock enable of spi sck line
do_buffer_next <= do_buffer_reg; -- output data buffer
do_transfer_next <= do_transfer_reg; -- output data flag
wr_ack_next <= wr_ack_reg; -- write acknowledge
di_req_next <= di_req_reg; -- prefetch data request
spi_mosi_o <= sh_reg(n - 1); -- default to avoid latch inference
state_next <= state_reg; -- next state
case state_reg is
when (n + 1) => -- this state is to enable SSEL before SCK
spi_mosi_o <= sh_reg(n - 1); -- shift out tx bit from the MSb
ssel_ena_next <= '1'; -- tx in progress: will assert SSEL
sck_ena_next <= '1'; -- enable SCK on next cycle (stays off on first SSEL clock cycle)
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (n) => -- deassert 'di_rdy' and stretch do_valid
spi_mosi_o <= sh_reg(n - 1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
sh_next(n - 1 downto 1) <= sh_reg(n - 2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (n - 1) downto (prefetch + 3) => -- remove 'do_transfer' and shift bits
spi_mosi_o <= sh_reg(n - 1); -- shift out tx bit from the MSb
di_req_next <= '0'; -- prefetch data request: deassert when shifting data
do_transfer_next <= '0'; -- reset 'do_valid' transfer signal
sh_next(n - 1 downto 1) <= sh_reg(n - 2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when (prefetch + 2) downto 2 => -- raise prefetch 'di_req_o' signal
spi_mosi_o <= sh_reg(n - 1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
sh_next(n - 1 downto 1) <= sh_reg(n - 2 downto 0); -- shift inner bits
sh_next(0) <= rx_bit_reg; -- shift in rx bit into LSb
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
when 1 => -- transfer rx data to do_buffer and restart if new data is written
spi_mosi_o <= sh_reg(n - 1); -- shift out tx bit from the MSb
di_req_next <= '1'; -- request data in advance to allow for pipeline delays
do_buffer_next(n - 1 downto 1) <= sh_reg(n - 2 downto 0); -- shift rx data directly into rx buffer
do_buffer_next(0) <= rx_bit_reg; -- shift last rx bit into rx buffer
do_transfer_next <= '1'; -- signal transfer to do_buffer
if (wren = '1') then -- load tx register if valid data present at di_i
state_next <= n; -- next state is top bit of new data
sh_next <= di_reg; -- load parallel data from di_reg into shifter
sck_ena_next <= '1'; -- SCK enabled
wr_ack_next <= '1'; -- acknowledge data in transfer
else
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= state_reg - 1; -- update next state at each sck pulse
end if;
when 0 => -- idle state: start and end of transmission
di_req_next <= '1'; -- will request data if shifter empty
sck_ena_next <= '0'; -- SCK disabled: tx empty, no data to send
if (wren = '1') then -- load tx register if valid data present at di_i
spi_mosi_o <= di_reg(n - 1); -- special case: shift out first tx bit from the MSb (look ahead)
ssel_ena_next <= '1'; -- enable interface SSEL
state_next <= n + 1; -- start from idle: let one cycle for SSEL settling
sh_next <= di_reg; -- load bits from di_reg into shifter
wr_ack_next <= '1'; -- acknowledge data in transfer
else
spi_mosi_o <= sh_reg(n - 1); -- shift out tx bit from the MSb
ssel_ena_next <= '0'; -- deassert SSEL: interface is idle
wr_ack_next <= '0'; -- remove write acknowledge for all but the load stages
state_next <= 0; -- when idle, keep this state
end if;
when others =>
state_next <= 0; -- state 0 is safe state
end case;
end process core_combi_proc;
--=============================================================================================
-- OUTPUT LOGIC PROCESSES
--=============================================================================================
-- data output processes
spi_ssel_o <= not ssel_ena_reg; -- active-low slave select line
do_o <= do_buffer_reg; -- parallel data out
do_valid_o <= do_valid_o_reg; -- data out valid
di_req_o <= di_req_o_reg; -- input data request for next cycle
wr_ack_o <= wr_ack_reg; -- write acknowledge
-----------------------------------------------------------------------------------------------
-- SCK out logic: pipeline phase compensation for the SCK line
-----------------------------------------------------------------------------------------------
-- This is a MUX with an output register.
-- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore
-- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency.
spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
begin
if (sclk_i'event and sclk_i = '1') then
if (sck_ena_reg = '1') then
spi_clk_reg <= spi_clk; -- copy the selected clock polarity
else
spi_clk_reg <= cpol; -- when clock disabled, set to idle polarity
end if;
end if;
spi_sck_o <= spi_clk_reg; -- connect register to output
end process spi_sck_o_gen_proc;
--=============================================================================================
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- these signals are useful for verification, and can be deleted after debug.
do_transfer_o <= do_transfer_reg;
state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
rx_bit_reg_o <= rx_bit_reg;
wren_o <= wren;
sh_reg_dbg_o <= sh_reg;
core_clk_o <= core_clk;
core_n_clk_o <= core_n_clk;
core_ce_o <= core_ce;
core_n_ce_o <= core_n_ce;
sck_ena_o <= sck_ena_reg;
sck_ena_ce_o <= sck_ena_ce;
end architecture rtl;
| gpl-3.0 | 69bea2dae46b4f767f3f417907408c8c | 0.51227 | 4.21732 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/synth/half_band_FIR.vhd | 1 | 12,231 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_1;
USE fir_compiler_v7_1.fir_compiler_v7_1;
ENTITY half_band_FIR IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END half_band_FIR;
ARCHITECTURE half_band_FIR_arch OF half_band_FIR IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF half_band_FIR_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF half_band_FIR_arch: ARCHITECTURE IS "fir_compiler_v7_1,Vivado 2014.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF half_band_FIR_arch : ARCHITECTURE IS "half_band_FIR,fir_compiler_v7_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF half_band_FIR_arch: ARCHITECTURE IS "half_band_FIR,fir_compiler_v7_1,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_COMPONENT_NAME=half_band_FIR,C_COEF_FILE=half_band_FIR.mif,C_COEF_FILE_LINES=5,C_FILTER_TYPE=7,C_INTERP_RATE=1,C_DECIM_RATE=2,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=15,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN=fixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=1,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=22,C_DATA_IP_PATH_WIDTHS=22,C_DATA_PX_PATH_WIDTHS=22,C_DATA_WIDTH=22,C_COEF_PATH_WIDTHS=15,C_COEF_WIDTH=15,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=38,C_OUTPUT_WIDTH=22,C_OUTPUT_PATH_WIDTHS=22,C_ACCUM_OP_PATH_WIDTHS=38,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NUM_MADDS=1,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=5,C_INPUT_RATE=16,C_OUTPUT_RATE=32,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=42,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=24,C_M_DATA_TUSER_WIDTH=1,C_HAS_CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_1
GENERIC MAP (
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "half_band_FIR",
C_COEF_FILE => "half_band_FIR.mif",
C_COEF_FILE_LINES => 5,
C_FILTER_TYPE => 7,
C_INTERP_RATE => 1,
C_DECIM_RATE => 2,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 15,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "1",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "22",
C_DATA_IP_PATH_WIDTHS => "22",
C_DATA_PX_PATH_WIDTHS => "22",
C_DATA_WIDTH => 22,
C_COEF_PATH_WIDTHS => "15",
C_COEF_WIDTH => 15,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "38",
C_OUTPUT_WIDTH => 22,
C_OUTPUT_PATH_WIDTHS => "22",
C_ACCUM_OP_PATH_WIDTHS => "38",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 1,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 5,
C_INPUT_RATE => 16,
C_OUTPUT_RATE => 32,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 42,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 24,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END half_band_FIR_arch;
| mit | 0cfbda243962b1c3a73e382569fc00c9 | 0.654076 | 3.090978 | false | true | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_004_test_input.fixed.vhd | 1 | 422 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Violations below
c <= d;
FOR_LABEL: for i in 0 to 7 generate
end generate;
a <= b;
IF_LABEL : if a = '1' generate
end generate;
b <= c;
CASE_LABEL : case data generate
end generate;
end;
| gpl-3.0 | cb2f9e83ee4373662a2d4f03f6ba3108 | 0.611374 | 3.403226 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/comment/rule_010_test_input.fixed.vhd | 1 | 1,144 |
-- failure
-- passed
context interfaces is
library fpga;
-- Comment 2
context fpga.constants;
-- Comment 3
-- Comment 4
-- Comment 5
use fpga.fpga_if.all;
-- Comment 6
-- Comment 7
-- use fpga.registers.all;
use fpga.functions.all;
-- Comment last
end context interfaces;
architecture RTL of FIFO is
-- failure
-- passed
-- failure
begin
-- failure
-- passed
-- failure
end architecture RTL;
architecture rtl of fifo is
constant c_cons1 : t_type :=
(
-- Comment 1
(
-- Comment 2
a => 1,
-- Comment 3
b => 2
)
-- Comment 4
);
begin end architecture RTL;
architecture RTL of FIFO is
-- pass
constant c_const1 : natural := 0;
constant c_const2 : natural := 1;
begin end architecture RTL;
library ieee;
-- Comment 1
architecture rtl of fifo is
-- Comment 2
begin
-- Comment 3
end architecture rtl;
library ieee;
-- Comment 1b
entity fifo is
-- Comment 2b
end entity;
library ieee;
-- Comment 1c
package body fifo_pkg is
-- Comment 2c
end package body;
library ieee;
-- Comment 1c
package fifo_pkg is
-- Comment 2c
end package;
| gpl-3.0 | f02e78a0e79f89bff3ecc90fbd313d2f | 0.636364 | 3.552795 | false | false | false | false |
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`protect end_protected
| bsd-2-clause | 3b2954bff76e2baf497d3bb324a8e231 | 0.948155 | 1.825513 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/c16/data_core.fixed.vhd | 1 | 5,407 | library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
-- library UNISIM;
-- use UNISIM.VComponents.all;
use work.cpu_pack.all;
entity DATA_CORE is
port (
CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
-- data in signals
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- memory/IO data
-- memory control signals
ADR : out std_logic_vector(15 downto 0);
MQ : out std_logic_vector( 7 downto 0);
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end entity DATA_CORE;
architecture BEHAVIORAL of DATA_CORE is
function b8 (A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
component ALU8 is
port (
CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
ALU_OP : in std_logic_vector( 4 downto 0);
XX : in std_logic_vector(15 downto 0);
YY : in std_logic_vector(15 downto 0);
ZZ : out std_logic_vector(15 downto 0)
);
end component;
component SELECT_YY is
port (
SY : in std_logic_vector( 3 downto 0);
IMM : in std_logic_vector(15 downto 0);
QUICK : in std_logic_vector( 3 downto 0);
RDAT : in std_logic_vector( 7 downto 0);
RR : in std_logic_vector(15 downto 0);
YY : out std_logic_vector(15 downto 0)
);
end component;
-- cpu registers
--
signal rr : std_logic_vector(15 downto 0);
signal ll : std_logic_vector(15 downto 0);
signal sp : std_logic_vector(15 downto 0);
-- internal buses
--
signal xx : std_logic_vector(15 downto 0);
signal yy : std_logic_vector(15 downto 0);
signal zz : std_logic_vector(15 downto 0);
signal adr_x : std_logic_vector(15 downto 0);
signal adr_z : std_logic_vector(15 downto 0);
signal adr_yz : std_logic_vector(15 downto 0);
signal adr_xyz : std_logic_vector(15 downto 0);
begin
ALU_8 : ALU8
port map (
CLK_I => CLK_I,
T2 => T2,
CE => CE,
CLR => CLR,
ALU_OP => OP,
XX => xx,
YY => yy,
ZZ => zz
);
SELYY : SELECT_YY
port map (
SY => SY,
IMM => IMM,
QUICK => QU,
RDAT => RDAT,
RR => rr,
YY => yy
);
ADR <= adr_xyz;
MQ <= zz(15 downto 8) when SMQ = '1' else
zz(7 downto 0);
Q_RR <= rr;
Q_LL <= ll;
Q_SP <= sp;
-- memory address
--
SEL_AX : process (SA(4 downto 3), IMM) is
variable sax : std_logic_vector(4 downto 3);
begin
sax := SA(4 downto 3);
case sax is
when SA_43_I16 =>
adr_x <= IMM;
when SA_43_I8S =>
adr_x <= b8(IMM(7)) & IMM(7 downto 0);
when others =>
adr_x <= b8(SA(3)) & b8(SA(3));
end case;
end process SEL_AX;
SEL_AZ : process (SA(2 downto 1), ll, rr, sp) is
variable saz : std_logic_vector(2 downto 1);
begin
saz := SA(2 downto 1);
case saz is
when SA_21_0 =>
adr_z <= X"0000";
when SA_21_LL =>
adr_z <= ll;
when SA_21_RR =>
adr_z <= rr;
when others =>
adr_z <= sp;
end case;
end process SEL_AZ;
SEL_AYZ : process (SA(0), adr_z) is
begin
adr_yz <= adr_z + (X"000" & "000" & SA(0));
end process SEL_AYZ;
SEL_AXYZ : process (adr_x, adr_yz) is
begin
adr_xyz <= adr_x + adr_yz;
end process SEL_AXYZ;
SEL_XX : process (SX, ll, rr, sp, PC) is
begin
case SX is
when SX_LL =>
xx <= ll;
when SX_RR =>
xx <= rr;
when SX_SP =>
xx <= sp;
when others =>
xx <= PC;
end case;
end process SEL_XX;
REGS : process (CLK_I) is
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
rr <= X"0000";
ll <= X"0000";
sp <= X"0000";
elsif (CE = '1' and T2 = '1') then
if (WE_RR = '1') then
rr <= zz;
end if;
if (WE_LL = '1') then
ll <= zz;
end if;
case WE_SP is
when SP_INC =>
sp <= adr_yz;
when SP_LOAD =>
sp <= adr_xyz;
when SP_NOP =>
null;
end case;
end if;
end if;
end process REGS;
end architecture BEHAVIORAL;
| gpl-3.0 | f3fefd7ec1f88d9af833ceac2fe2eef4 | 0.504716 | 3.197516 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/example_design/daala_zynq_axi_bram_ctrl_0_bram_0_prod.vhd | 1 | 10,967 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: daala_zynq_axi_bram_ctrl_0_bram_0_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : zynq
-- C_XDEVICEFAMILY : zynq
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 1
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 1
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 8
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 64
-- C_READ_WIDTH_A : 64
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 32
-- C_HAS_RSTB : 1
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 8
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 64
-- C_READ_WIDTH_B : 64
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 32
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY daala_zynq_axi_bram_ctrl_0_bram_0_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END daala_zynq_axi_bram_ctrl_0_bram_0_prod;
ARCHITECTURE xilinx OF daala_zynq_axi_bram_ctrl_0_bram_0_prod IS
COMPONENT daala_zynq_axi_bram_ctrl_0_bram_0_exdes IS
PORT (
--Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : daala_zynq_axi_bram_ctrl_0_bram_0_exdes
PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
RSTB => RSTB,
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| bsd-2-clause | fc9626ce46ac8c5f18b2ae42beb31ae2 | 0.490654 | 3.786948 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/demo_tb/tb_cascaded_integrator_comb.vhd | 1 | 18,633 | --------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the CIC Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the CIC Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated CIC Compiler core
-- instance named "cascaded_integrator_comb".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
-- ~ Test Phase Controller : This controls the behaviour of the other
-- blocks in the testbench, enabling and disabling
-- certain funcitonality at the appropriate times.
-- The net effect is to divide the test into a number
-- of phases, each of which tests a different feature.
-- ~ Upstream Data Master : Supplies sample data on the Data In Channel. The
-- sample data describes sine waves on each channel,
-- with each channel having a higher frequency than
-- the one below it. The same sine waves will be seen
-- on the output channels in a decimated or interpolated
-- manner.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated CIC Compiler core named "cascaded_integrator_comb".
--
-- If your CORE Generator project options were set to generate a structural
-- model, a VHDL netlist named cascaded_integrator_comb.vhd was generated.
-- If this file is not present, execute the following command in the directory
-- containing your CORE Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl cascaded_integrator_comb.ngc cascaded_integrator_comb.vhd
--
-- Compile cascaded_integrator_comb.vhd into the work library. See your simulator
-- documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_cascaded_integrator_comb is
end tb_cascaded_integrator_comb;
architecture tb of tb_cascaded_integrator_comb is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-- The number of clocks available to the CIC to process a sample (i.e. the oversampling rate).
-- (C_CLK_FREQ/C_SAMPLE_FREQ)/C_NUM_CHANNELS
--
constant CLKS_PER_SAMPLE : integer := 1;
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
--
signal aclk : std_logic := '0'; -- the master clock
-- Data Input Channel signals
--
signal s_axis_data_tvalid_to_dut : std_logic := '0'; -- Payload is valid
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- CIC is ready
signal s_axis_data_tdata_to_dut : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
-- Data Out Channel signals
--
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases
-----------------------------------------------------------------------
-- These are a convenience for viewing data in a simulator waveform viewer.
--
-- Alias for the Data field in the Data Input Channel
--
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
-- Alias for the Data field in the Data Out Channel
--
signal m_axis_data_tdata_data : std_logic_vector(21 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-----------------------------------------------------------------------
constant IP_WIDTH : integer := 2; -- Width of the input data
-- Function to generate the input sample data.
--
function calculate_next_input_sample(sample_number : in integer) return std_logic_vector is
variable A : real := 1.0; -- Amplitude for wave
variable F : real := 1.0; -- Frequency for wave
variable P : real := 0.0; -- Phase for wave
variable theta : real;
variable K : integer := 16; -- Limit factor on theta to avoid max x value supported by modelsim for sin(x)
variable y : real; -- The calculated value as a real
variable y_int : integer; -- The calculated value as an integer
variable result : std_logic_vector(IP_WIDTH-1 downto 0);
variable number_of_samples : real := 100.0 * real(16);
begin
theta := (2.0 * MATH_PI * F * real(sample_number mod integer(number_of_samples))) / number_of_samples;
y := A * sin(theta + P);
y_int := integer(round(y * real(2**(IP_WIDTH-2))));
result := std_logic_vector(to_signed(y_int, IP_WIDTH));
return result;
end function calculate_next_input_sample;
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal g_current_rate : integer := 16; -- The rate that the core is currently programmed to use
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
-- Test Phase Manager signals and variables
-- ----------------------------------------
type test_phase_t is (PHASE_START_OF_TEST,
NO_USDM_WAITSTATES, -- Upstream Data Master asserts TVALID at core rate
USDM_WAITSTATES, -- Upstream Data Master asserts TVALID with waitstates
PHASE_END_OF_TEST);
signal g_current_test_phase : test_phase_t := PHASE_START_OF_TEST; -- For debug. Add this to your waveform to see what the test is doing
signal g_usdm_waitstates_allowed : boolean := false; -- Set to true if the Upstream Data Master is allowed to insert waitstates
-- This function returns the number of output samples required by a test phase
--
function get_number_of_samples_in_test_phase (
constant NUM_CHANNELS : integer;
constant RATE : integer) return integer is
begin
-- We want to see one cycle of a sine wave at the output per channel. One cycle of the
-- input sine wave is 100 * (current rate) samples, so only 100 are required at the output
-- (per channel).
--
return 100 * NUM_CHANNELS;
end function;
-- ------------------------------------------------------------------------------------------------
-- AXI Functions
-- ------------------------------------------------------------------------------------------------
-- This procedure acts like an AXI master and sends 1 data sample on an AXI channel
--
procedure axi_master_send (
variable tdata_value : in std_logic_vector;
signal aclk : in std_logic;
signal tready : in std_logic;
signal tvalid : out std_logic;
signal tdata : out std_logic_vector) is
begin
tdata <= tdata_value;
tvalid <= '1';
-- Now wait until the rising clock edge where tready is 1
--
loop
wait until rising_edge(aclk);
exit when (tready = '1');
end loop;
tvalid <= '0';
end axi_master_send;
-- This function returns when "number_of_samples" have been seen from the Data Output Channel
--
procedure dout_channel_wait_for_samples (
signal aclk : in std_logic;
signal tvalid : in std_logic;
constant number_of_samples : in integer
) is
variable v_number_of_samples_to_wait : integer := number_of_samples;
begin
while v_number_of_samples_to_wait > 0 loop
wait until rising_edge(aclk) and tvalid = '1';
v_number_of_samples_to_wait := v_number_of_samples_to_wait - 1;
end loop;
end dout_channel_wait_for_samples;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.cascaded_integrator_comb
port map (
s_axis_data_tvalid => s_axis_data_tvalid_to_dut,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata_to_dut,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata,
aclk => aclk
);
-- ----------------------------------------------------------------------------
-- Connect the testbench to the DUT.
-- ----------------------------------------------------------------------------
-- Delay all signals so that they arrive after the clock edge.
s_axis_data_tdata_to_dut <= s_axis_data_tdata after T_HOLD;
s_axis_data_tvalid_to_dut <= s_axis_data_tvalid after T_HOLD;
-----------------------------------------------------------------------
-- Clock Generator
-----------------------------------------------------------------------
--
clock_gen : process
begin
wait for 100 ns; -- Wait for (Verilog) GSR to be de-asserted
while g_end_simulation = false loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
report "Simulation finished successfully / Test completed successfully" severity failure;
wait;
end process clock_gen;
-- ----------------------------------------------------------------------------
-- Test Phase Controller
-- ----------------------------------------------------------------------------
--
proc_phase_manager: process
variable v_samples_in_phase : integer := 0; -- The number of output samples required by the test phase
begin
-- Phase: Send data to CIC with no waitstates
-- -------------------------------------------
--
g_current_test_phase <= NO_USDM_WAITSTATES;
g_usdm_waitstates_allowed <= false;
v_samples_in_phase := get_number_of_samples_in_test_phase(RATE => g_current_rate, NUM_CHANNELS => 1);
dout_channel_wait_for_samples (aclk, m_axis_data_tvalid, v_samples_in_phase);
-- Phase: Send data to CIC with waitstates on Data In Channel
-- ----------------------------------------------------------
--
g_current_test_phase <= USDM_WAITSTATES;
g_usdm_waitstates_allowed <= true;
v_samples_in_phase := get_number_of_samples_in_test_phase(RATE => g_current_rate, NUM_CHANNELS => 1);
dout_channel_wait_for_samples (aclk, m_axis_data_tvalid, v_samples_in_phase);
-- End the test
------------------------------------------------
--
g_current_test_phase <= PHASE_END_OF_TEST;
g_end_simulation <= true;
wait;
end process proc_phase_manager;
-- ----------------------------------------------------------------------------
-- Upstream Data Master
-- ----------------------------------------------------------------------------
-- Generation of s_axis_data_tvalid and input data
--
proc_usdm : process
variable v_tdata : std_logic_vector(7 downto 0);
variable v_tlast : std_logic;
variable v_clocks_to_wait : integer := 0;
variable sample_number : integer := 0; -- This is the number of the sample being sent to the CIC and is used to calculate the next value of input data.
-- It is only incremented when the sample for the last channel is sent.
-- Variables for random waitstate generation
--
variable seed1 : integer := 2;
variable seed2 : integer := 1;
variable rand_val : real;
begin
-- Padding bits are ignored so we can set them to anything
--
v_tdata(7 downto 2) := (others => '0');
if g_usdm_waitstates_allowed = false then -- No waitstates, so run at specified input rate
-- Calculate sample value
--
v_tdata(1 downto 0) := calculate_next_input_sample(sample_number);
axi_master_send (tdata_value => v_tdata,
aclk => aclk,
tready => s_axis_data_tready,
tvalid => s_axis_data_tvalid,
tdata => s_axis_data_tdata
);
v_clocks_to_wait := (CLKS_PER_SAMPLE-1);
sample_number:= sample_number + 1;
for i in 1 to v_clocks_to_wait loop
wait until rising_edge(aclk);
end loop;
else -- Waitstates are allowed
UNIFORM(seed1, seed2, rand_val);
-- Decide how long to wait. Anywhere between 1 and 10 should be enough for this example
--
v_clocks_to_wait := integer(rand_val*9.0);
v_clocks_to_wait := v_clocks_to_wait + 1;
for i in 0 to v_clocks_to_wait-1 loop
wait until rising_edge(aclk);
exit when (g_usdm_waitstates_allowed = false);
end loop;
-- Calculate sample value
--
v_tdata(1 downto 0) := calculate_next_input_sample(sample_number);
axi_master_send (tdata_value => v_tdata,
aclk => aclk,
tready => s_axis_data_tready,
tvalid => s_axis_data_tvalid,
tdata => s_axis_data_tdata
);
sample_number:= sample_number + 1;
end if;
end process;
-------------------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-------------------------------------------------------------------------------
-- Data Input Channel alias signals
--
-- s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0) when s_axis_data_tvalid = '1' and s_axis_data_tready = '1';
-- Data Output Channel alias signals
--
-- m_axis_data_tdata_data <= m_axis_data_tdata(21 downto 0);
m_axis_data_tdata_data <= m_axis_data_tdata(21 downto 0) when m_axis_data_tvalid = '1';
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires a numerical model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
end tb;
| mit | b524aabb13a02c17a777f3b0e7932928 | 0.546826 | 4.566912 | false | true | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/exponent/rule_500_test_input.fixed_lower.vhd | 1 | 373 |
architecture rtl of fifo is
constant con_1 : natural := 20e10;
constant con_2 : natural := 20.56e10;
constant con_3 : natural := 20e-10;
constant con_4 : natural := 20.56e-10;
constant con_5 : natural := 20e10;
constant con_6 : natural := 20.56e10;
constant con_7 : natural := 20e-10;
constant con_8 : natural := 20.56e-10;
begin
end architecture rtl;
| gpl-3.0 | 9714ef87141ee54c8a99aea9d0961a44 | 0.659517 | 3.008065 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/wb_rx_bridge.vhd | 2 | 13,815 | -- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Bridge between Rx core and Mem
-- ####################################
-- # Address Map:
-- # 0x0000: Start Adr (RO)
-- # 0x0001: Data Cnt (RO)
-- # 0x0002[0]: Loopback (RW)
-- # 0x0003: Data Rate (RO)
-- # 0x0004: Loop Fifo (WO)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_dat_i : in std_logic_vector(31 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(31 downto 0);
rx_valid_i : in std_logic;
-- Status In
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end wb_rx_bridge;
architecture Behavioral of wb_rx_bridge is
-- Cmoponents
COMPONENT rx_bridge_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT rx_bridge_ctrl_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Constants
constant c_ALMOST_FULL_THRESHOLD : unsigned(10 downto 0) := TO_UNSIGNED(1900, 11);
constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((200*256), 32); -- 200kByte
constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2**14, 32); -- Counts in 5ns = 0.1ms
constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec
constant c_EMPTY_THRESHOLD : unsigned(10 downto 0) := TO_UNSIGNED(16, 11);
constant c_EMPTY_TIMEOUT : unsigned(10 downto 0) := TO_UNSIGNED(2000, 11);
-- Signals
signal data_fifo_din : std_logic_vector(31 downto 0);
signal data_fifo_dout : std_logic_vector(31 downto 0);
signal data_fifo_wren : std_logic;
signal data_fifo_rden : std_logic;
signal data_fifo_full : std_logic;
signal data_fifo_empty : std_logic;
signal data_fifo_almost_full : std_logic;
signal data_fifo_prog_empty : std_logic;
signal data_fifo_empty_cnt : unsigned(10 downto 0);
signal data_fifo_empty_true : std_logic;
signal data_fifo_empty_pressure : std_logic;
signal ctrl_fifo_din : std_logic_vector(63 downto 0);
signal ctrl_fifo_dout : std_logic_vector(63 downto 0);
signal ctrl_fifo_wren : std_logic;
signal ctrl_fifo_rden : std_logic;
signal ctrl_fifo_full : std_logic;
signal ctrl_fifo_empty : std_logic;
signal dma_stb_t : std_logic;
signal dma_stb_valid : std_logic;
signal dma_adr_cnt : unsigned(31 downto 0);
signal dma_start_adr : unsigned(31 downto 0);
signal dma_data_cnt : unsigned(31 downto 0);
signal dma_data_cnt_d : unsigned(31 downto 0);
signal dma_timeout_cnt : unsigned(31 downto 0);
signal dma_ack_cnt : unsigned(7 downto 0);
signal rx_data_local : std_logic_vector(31 downto 0);
signal rx_valid_local : std_logic;
signal rx_data_local_d : std_logic_vector(31 downto 0);
signal rx_valid_local_d : std_logic;
signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0);
signal time_cnt : unsigned(31 downto 0);
signal time_pulse : std_logic;
signal data_rate_cnt : unsigned(31 downto 0);
signal trig_cnt : unsigned(31 downto 0);
signal trig_pulse_d0 : std_logic;
signal trig_pulse_d1 : std_logic;
signal trig_pulse_pos : std_logic;
-- Registers
signal loopback : std_logic;
signal data_rate : std_logic_vector(31 downto 0);
begin
--Tie offs
irq_o <= '0';
busy_o <= data_fifo_full;
-- Wishbone Slave
wb_slave_proc: process(sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_stall_o <= '0';
ctrl_fifo_rden <= '0';
rx_valid_local <= '0';
ctrl_fifo_dout_tmp <= (others => '0');
-- Regs
loopback <= '0';
elsif rising_edge(sys_clk_i) then
-- Default
wb_ack_o <= '0';
ctrl_fifo_rden <= '0';
wb_stall_o <= '0';
rx_valid_local <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '0') then
-- READ
if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr
if (ctrl_fifo_empty = '0') then
wb_dat_o <= ctrl_fifo_dout(31 downto 0);
ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32);
wb_ack_o <= '1';
ctrl_fifo_rden <= '1';
else
wb_dat_o <= x"FFFFFFFF";
ctrl_fifo_dout_tmp <= (others => '0');
wb_ack_o <= '1';
ctrl_fifo_rden <= '0';
end if;
elsif (wb_adr_i(3 downto 0) = x"1") then -- Count
wb_dat_o <= ctrl_fifo_dout_tmp;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= loopback;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate
wb_dat_o <= data_rate;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= data_fifo_empty_true;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count
wb_dat_o <= std_logic_vector(dma_data_cnt_d);
wb_ack_o <= '1';
else
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end if;
else
-- WRITE
wb_ack_o <= '1';
if (wb_adr_i(3 downto 0) = x"2") then
loopback <= wb_dat_i(0);
elsif (wb_adr_i(3 downto 0) = x"4") then
rx_valid_local <= '1';
end if;
end if;
end if;
end if;
end process wb_slave_proc;
-- Data from Rx
data_rec : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i <= '0') then
data_fifo_wren <= '0';
data_fifo_din <= (others => '0');
elsif rising_edge(sys_clk_i) then
if (loopback = '1') then
data_fifo_wren <= rx_valid_local_d;
data_fifo_din <= rx_data_local_d;
else
data_fifo_wren <= rx_valid_i;
data_fifo_din <= rx_data_i;
end if;
end if;
end process data_rec;
-- Empty logic to produce some backpressure
data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure;
empty_proc : process(dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fifo_empty_pressure <= '0';
data_fifo_empty_cnt <= (others => '0');
elsif rising_edge(dma_clk_i) then
-- Timeout Counter
if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then
data_fifo_empty_cnt <= data_fifo_empty_cnt + 1;
elsif (data_fifo_empty_true = '1') then
data_fifo_empty_cnt <= (others => '0');
end if;
if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then
data_fifo_empty_pressure <= '0';
elsif (data_fifo_prog_empty = '0') then
data_fifo_empty_pressure <= '0';
elsif (data_fifo_empty_true = '1') then
data_fifo_empty_pressure <= '1';
end if;
end if;
end process empty_proc;
-- DMA Master and data control
dma_stb_valid <= dma_stb_t and not data_fifo_empty;
to_ddr_proc: process(dma_clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
dma_stb_t <= '0';
data_fifo_rden <= '0';
dma_adr_o <= (others => '0');
dma_dat_o <= (others => '0');
dma_cyc_o <= '0';
dma_stb_o <= '0';
dma_we_o <= '1'; -- Write only
elsif rising_edge(dma_clk_i) then
if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then
dma_stb_t <= '1';
data_fifo_rden <= '1';
else
dma_stb_t <= '0';
data_fifo_rden <= '0';
end if;
if (data_fifo_empty = '0' or dma_ack_cnt > 0) then
dma_cyc_o <= '1';
else
dma_cyc_o <= '0';
end if;
dma_adr_o <= std_logic_vector(dma_adr_cnt);
dma_dat_o <= data_fifo_dout;
dma_stb_o <= dma_stb_t and not data_fifo_empty;
dma_we_o <= '1'; -- Write only
end if;
end process to_ddr_proc;
adr_proc : process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ctrl_fifo_wren <= '0';
dma_adr_cnt <= (others => '0');
dma_start_adr <= (others => '0');
dma_data_cnt <= (others => '0');
dma_data_cnt_d <= (others => '0');
dma_timeout_cnt <= (others => '0');
ctrl_fifo_din(63 downto 0) <= (others => '0');
dma_ack_cnt <= (others => '0');
elsif rising_edge(dma_clk_i) then
-- Address Counter
if (dma_stb_valid = '1') then
dma_adr_cnt <= dma_adr_cnt + 1;
end if;
if (dma_stb_valid = '1' and dma_ack_i = '0') then
dma_ack_cnt <= dma_ack_cnt + 1;
elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then
dma_ack_cnt <= dma_ack_cnt - 1;
end if;
-- Package size counter
-- Check if Fifo is full
if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE;
dma_data_cnt <= TO_UNSIGNED(1, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE;
dma_data_cnt <= TO_UNSIGNED(0, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + dma_data_cnt;
dma_data_cnt <= TO_UNSIGNED(0, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '1') then
dma_data_cnt <= dma_data_cnt + 1;
ctrl_fifo_wren <= '0';
else
ctrl_fifo_wren <= '0';
end if;
dma_data_cnt_d <= dma_data_cnt;
-- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package
-- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt);
-- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over
-- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1);
-- end if;
-- Timeout counter
if (dma_data_cnt > 0 and data_fifo_empty = '1') then
dma_timeout_cnt <= dma_timeout_cnt + 1;
elsif (data_fifo_empty = '0') then
dma_timeout_cnt <= TO_UNSIGNED(0, 32);
end if;
end if;
end process adr_proc;
-- Data Rate maeasurement
data_rate_proc: process(sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_rate_cnt <= (others => '0');
data_rate <= (others => '0');
time_cnt <= (others => '0');
time_pulse <= '0';
elsif rising_edge(sys_clk_i) then
-- 1Hz pulser
if (time_cnt = c_TIME_FRAME) then
time_cnt <= (others => '0');
time_pulse <= '1';
else
time_cnt <= time_cnt + 1;
time_pulse <= '0';
end if;
if (time_pulse = '1') then
data_rate <= std_logic_vector(data_rate_cnt);
data_rate_cnt <= (others => '0');
elsif (data_fifo_wren = '1') then
data_rate_cnt <= data_rate_cnt + 1;
end if;
end if;
end process data_rate_proc;
-- Loopback delay
delayproc : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_data_local <= (others => '0');
rx_data_local_d <= (others => '0');
rx_valid_local_d <= '0';
elsif rising_edge(sys_clk_i) then
rx_data_local_d <= wb_dat_i;
rx_valid_local_d <= rx_valid_local;
end if;
end process;
-- Trigger sync and count
trig_sync : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_pulse_d0 <= '0';
trig_pulse_d1 <= '0';
trig_pulse_pos <= '0';
trig_cnt <= (others => '0');
elsif rising_edge(sys_clk_i) then
trig_pulse_d0 <= trig_pulse_i;
trig_pulse_d1 <= trig_pulse_d0;
if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then
trig_pulse_pos <= '1';
else
trig_pulse_pos <= '0';
end if;
if (trig_pulse_pos = '1') then
trig_cnt <= trig_cnt + 1;
end if;
end if;
end process trig_sync;
cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => sys_clk_i,
rd_clk => dma_clk_i,
din => data_fifo_din,
wr_en => data_fifo_wren,
rd_en => data_fifo_rden,
prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD),
prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD),
dout => data_fifo_dout,
full => data_fifo_full,
empty => data_fifo_empty_true,
prog_full => data_fifo_almost_full,
prog_empty => data_fifo_prog_empty
);
cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => dma_clk_i,
rd_clk => sys_clk_i,
din => ctrl_fifo_din,
wr_en => ctrl_fifo_wren,
rd_en => ctrl_fifo_rden,
dout => ctrl_fifo_dout,
full => ctrl_fifo_full,
empty => ctrl_fifo_empty
);
end Behavioral;
| gpl-3.0 | 0d88ec910f8b931c5822826492f4aeb0 | 0.597032 | 2.567844 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/concurrent_statement/classification_test_input.vhd | 1 | 5,845 |
entity BLOCK_EXAMPLE is
end entity BLOCK_EXAMPLE;
architecture RTL of BLOCK_EXAMPLE is
begin
BLK : block is
begin
LABEL : assert TRUE
report "This is a string"
severity WARNING;
-- Simple form
a <= b;
GEN : for ii in 0 to 7 generate
-- Simple form
a <= b when 'a' else
c when 'b' else
d;
LABEL : assert TRUE
report "This is a string"
severity WARNING;
BLK2 : block is
begin
assert TRUE
report "This is a string"
severity WARNING;
-- Basic version
with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
GEN2 : for jj in 0 to 7 generate
-- Simple form
simple_label : a <= b;
assert TRUE
report "This is a string"
severity WARNING;
end generate GEN2;
end block BLK2;
end generate GEN;
end block BLK;
BLK : block is
begin
-- Simple form
conditional_label : a <= b when 'a' else
c when 'b' else
d;
IF_GEN_LABEL: if a = x generate
-- Basic version
select_label : with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
BLK2 : block is
begin
LABEL : assert TRUE
report "This is a string";
-- Simple form
simple_label : postponed a <= b;
GEN2 : for jj in 0 to 7 generate
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
LABEL : assert TRUE
report "This is a string";
BLK3: block is
begin
LABEL : assert TRUE
report "This is a string";
end block BLK3;
end generate GEN2;
BLK4 : block is
begin
CASE_GEN_LABEL : case a & B & c generate
when "000" =>
LABEL : assert TRUE
report "This is a string";
-- Basic version
select_label : postponed with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
BLK4A : block is
begin
LABEL : assert TRUE
report "This is a string";
-- Simple form
postponed a <= b;
end block BLK4A;
when "001" =>
-- Simple form
postponed a <= b when 'a' else
c when 'b' else
d;
IF_GEN_LABELA: if a = y generate
LABEL : assert TRUE
severity WARNING;
-- Basic version
postponed with sel select
out1 <= a when "00",
b when "01",
c when "10",
d when others;
BLK4B : block is
begin
LABEL : assert TRUE
severity WARNING;
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
end block BLK4B;
end generate IF_GEN_LABELA;
end generate CASE_GEN_LABEL;
end block BLK4;
BLK5 : block is
begin
postponed assert TRUE
report "This is a string";
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
end block BLK5;
end block BLK2;
end generate IF_GEN_LABEL;
GEN : for ii in 0 to 7 generate
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
postponed assert TRUE
report "This is a string";
GEN2 : for jj in 0 to 7 generate
postponed assert TRUE
report "This is a string";
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
IF_GEN_LABEL2 : if b = y generate
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
BLK2 : block is
begin
LABEL : postponed assert TRUE
report "This is a string";
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
end block BLK2;
elsif x = z generate
BLK2 : block is
begin
-- Simple form
conditional_label : postponed a <= b when 'a' else
c when 'b' else
d;
LABEL : postponed assert TRUE
report "This is a string";
end block BLK2;
end generate IF_GEN_LABEL2;
end generate GEN2;
end generate GEN;
end block BLK;
end architecture RTL;
| gpl-3.0 | dca978ff8bb180d38ea728ffc66aa84b | 0.40479 | 5.402033 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_019_test_input.vhd | 1 | 622 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
CASE_LABEL : case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
PROC_2 : process (a, b, c) is
begin
CASE_LABEL : -- Some Comment
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | 2c12e8f081fb152bbacaf03c187184f9 | 0.483923 | 3.273684 | false | false | false | false |
Nibble-Knowledge/peripheral-ethernet | vhdl-serial/cpu2periph.vhd | 1 | 3,202 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:44:29 03/03/2016
-- Design Name:
-- Module Name: cpu2periph - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cpu2periph is
Port ( clk_cpu : in STD_LOGIC;
reset : in STD_LOGIC;
cpu_write : in STD_LOGIC;
cpu_data : in STD_LOGIC_VECTOR (3 downto 0);
--established : in STD_LOGIC;
buffok : in STD_LOGIC;
setbuff : out STD_LOGIC;
pcbuff : out STD_LOGIC_VECTOR (7 downto 0);
cpu_ready : out STD_LOGIC;
debug : out std_logic);
end cpu2periph;
architecture Behavioral of cpu2periph is
signal buff : std_logic_vector(pcbuff'range);
type PERIPHSTATE is (WAIT4EMPTYBUFF, WAIT4MSB, RXMSB, WAIT4LSB, RXLSB);
signal CurrState : PERIPHSTATE;
signal dbg : std_logic;
begin
process(clk_cpu, reset)
begin
if reset = '1' then
CurrState <= WAIT4EMPTYBUFF;
buff <= (others => '0');
pcbuff <= (others => '0');
cpu_ready <= '0';
dbg <= '0';
elsif rising_edge(clk_cpu) then
case CurrState is
when WAIT4EMPTYBUFF => --wait until the BUFFOK flag is cleared, which hopefully happens fast enough, and connection is established
setbuff <= '0';
if buffok = '0' then --and established = '1' then
CurrState <= WAIT4MSB;
end if;
when WAIT4MSB => --wait for CPU to request a write
if cpu_write = '1' then
cpu_ready <= '1';
CurrState <= RXMSB;
end if;
when RXMSB => --meh, quite a useless state
-- CurrState <= STOPMSB;
--when STOPMSB => --set ready low, and while cpu_write is still high, copy its data to the buffer
-- cpu_ready <= '0';
if cpu_write = '1' then
buff(7 downto 4) <= cpu_data;
else
cpu_ready <= '0';
CurrState <= WAIT4LSB;
end if;
when WAIT4LSB => --wait for CPU to request a write
if cpu_write = '1' then
cpu_ready <= '1';
CurrState <= RXLSB;
end if;
when RXLSB => --meh, quite a useless state
-- CurrState <= STOPLSB;
--when STOPLSB => --set ready low, and while cpu_write is still high, copy its data to the buffer
-- cpu_ready <= '0';
if cpu_write = '1' then
buff(3 downto 0) <= cpu_data;
else
--Our data is ready, put it into the PCBUFF and set the BUFFOK flag
cpu_ready <= '0';
pcbuff <= buff;
setbuff <= '1';
CurrState <= WAIT4EMPTYBUFF;
end if;
dbg <= not dbg;
end case;
end if;
end process;
debug <= dbg;
end Behavioral;
| unlicense | de8f084861b87638ffcecf408b802f6d | 0.574953 | 3.424599 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_bram_0/daala_zynq_axi_bram_ctrl_0_bram_0/simulation/daala_zynq_axi_bram_ctrl_0_bram_0_synth.vhd | 1 | 12,981 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v8_0 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: daala_zynq_axi_bram_ctrl_0_bram_0_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY daala_zynq_axi_bram_ctrl_0_bram_0_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE daala_zynq_axi_bram_ctrl_0_bram_0_synth_ARCH OF daala_zynq_axi_bram_ctrl_0_bram_0_synth IS
CONSTANT STIM_CNT : INTEGER := if_then_else((C_ROM_SYNTH=0),8,22);
-- TDP Configuration
COMPONENT BMG_STIM_GEN
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
RSTA : IN STD_LOGIC;
RSTB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
ENB : OUT STD_LOGIC :='0';
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END COMPONENT;
COMPONENT daala_zynq_axi_bram_ctrl_0_bram_0_exdes
PORT (
--Inputs - Port A
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_SHIFT_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_SHIFT: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_SHIFT_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ENB: STD_LOGIC := '0';
SIGNAL ENB_R: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 100 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(5 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64
)
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64
)
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 100 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST: BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
RSTA => RSTA,
RSTB => RSTB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
ENB => ENB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(6) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(6) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
ADDRA_SHIFT(31 DOWNTO 3) <= ADDRA(28 DOWNTO 0) ;
ADDRA_SHIFT(2 DOWNTO 0) <= (OTHERS=> '0' );
ADDRB_SHIFT(31 DOWNTO 3) <= ADDRB(28 DOWNTO 0);
ADDRB_SHIFT(2 DOWNTO 0) <= (OTHERS => '0');
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RESETB_SYNC_R3='1') THEN
ENB_R <= '0' AFTER 100 ns;
WEB_R <= (OTHERS=>'0') AFTER 100 ns;
DINB_R <= (OTHERS=>'0') AFTER 100 ns;
ELSE
ENB_R <= ENB AFTER 100 ns;
WEB_R <= WEB AFTER 100 ns;
DINB_R <= DINB AFTER 100 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_SHIFT_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ADDRA_SHIFT_R <= ADDRA_SHIFT AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RESETB_SYNC_R3='1') THEN
ADDRB_SHIFT_R <= (OTHERS=>'0') AFTER 100 ns;
ELSE
ADDRB_SHIFT_R <= ADDRB_SHIFT AFTER 100 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: daala_zynq_axi_bram_ctrl_0_bram_0_exdes PORT MAP (
--Port A
RSTA => RSTA,
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_SHIFT_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
RSTB => RSTB,
ENB => ENB_R,
WEB => WEB_R,
ADDRB => ADDRB_SHIFT_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| bsd-2-clause | 19ddae5beeb6e285e4efbc1f829aadf2 | 0.549881 | 3.489516 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_015_test_input.fixed_upper.vhd | 1 | 589 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 IS
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 IS
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 IS
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | 2d398ad610328aa0d629d1f6a3a21cec | 0.4618 | 3.308989 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_001_test_input.fixed.vhd | 1 | 786 |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
if a = b then
sig3 <= sig4;
sig4 <= sig5;
if c = d then
sig6 <= sig7;
sig7 <= sig8;
end if;
end if;
case address is
when 0 =>
sig5 <= sig6;
sig6 <= sig7;
sig8 <= '0' when b = '1';
end case;
end process;
-- Violations below
process
begin
sig1 <= sig2;
sig2 <= sig3;
if a = b then
sig3 <= sig4;
sig4 <= sig5;
if c = d then
sig6 <= sig7;
sig7 <= sig8;
end if;
end if;
case address is
when 0 =>
sig5 <= sig6;
sig6 <= sig7;
sig8 <= '0' when b = '1';
end case;
end process;
end architecture RTL;
| gpl-3.0 | 9dd17a4a538ee6b8aa4e1bea2d536788 | 0.454198 | 3.288703 | false | false | false | false |
okaxaki/vm2413 | VoiceMemory.vhd | 2 | 1,939 | --
-- VoiceMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity VoiceMemory is
port (
clk : in std_logic;
reset : in std_logic;
idata : in VOICE_TYPE;
wr : in std_logic;
rwaddr : in VOICE_ID_TYPE; -- read/write address
roaddr : in VOICE_ID_TYPE; -- read only address
odata : out VOICE_TYPE;
rodata : out VOICE_TYPE
);
end VoiceMemory;
architecture RTL of VoiceMemory is
-- The following array is mapped into a Single-Clock Synchronous RAM with two-read
-- addresses by Altera's QuartusII compiler.
type VOICE_ARRAY_TYPE is array (VOICE_ID_TYPE'range) of VOICE_VECTOR_TYPE;
signal voices : VOICE_ARRAY_TYPE;
component VoiceRom port (
clk : in std_logic;
addr : in VOICE_ID_TYPE;
data : out VOICE_TYPE
);
end component;
signal rom_addr : VOICE_ID_TYPE;
signal rom_data : VOICE_TYPE;
signal rstate : integer range 0 to 2;
begin
ROM2413 : VoiceRom port map(clk, rom_addr, rom_data);
process (clk, reset)
variable init_id : integer range 0 to VOICE_ID_TYPE'high+1;
begin
if reset = '1' then
init_id := 0;
rstate <= 0;
elsif clk'event and clk = '1' then
if init_id /= VOICE_ID_TYPE'high+1 then
case rstate is
when 0 =>
rom_addr <= init_id;
rstate <= 1;
when 1 =>
rstate <= 2;
when 2 =>
voices(init_id) <= CONV_VOICE_VECTOR(rom_data);
rstate <= 0;
init_id := init_id + 1;
end case;
elsif wr = '1' then
voices(rwaddr) <= CONV_VOICE_VECTOR(idata);
end if;
odata <= CONV_VOICE(voices(rwaddr));
rodata <= CONV_VOICE(voices(roaddr));
end if;
end process;
end RTL; | mit | 40f50e82e54b6a9ca6c4391090159e96 | 0.556472 | 3.610801 | false | false | false | false |
kjellhar/axi_mmc | src/vhdl/mmc_crc16.vhd | 1 | 2,164 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 10:27:20 AM
-- Design Name:
-- Module Name: mmc_crc16 - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mmc_crc16 is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
enable : in std_logic;
serial_in : in std_logic;
crc16_out : out std_logic_vector (15 downto 0)
);
end mmc_crc16;
architecture rtl of mmc_crc16 is
signal crc_reg : std_logic_vector (15 downto 0) := (others => '0');
begin
crc16_out <= crc_reg;
process
begin
wait until rising_edge(clk);
if reset='1' then
crc_reg <= (others => '0');
elsif enable='1' and clk_en='1' then
crc_reg(0) <= crc_reg(15) xor serial_in;
crc_reg(1) <= crc_reg(0);
crc_reg(2) <= crc_reg(1);
crc_reg(3) <= crc_reg(2);
crc_reg(4) <= crc_reg(3);
crc_reg(5) <= crc_reg(4) xor crc_reg(15) xor serial_in;
crc_reg(6) <= crc_reg(5);
crc_reg(7) <= crc_reg(6);
crc_reg(8) <= crc_reg(7);
crc_reg(9) <= crc_reg(8);
crc_reg(10) <= crc_reg(9);
crc_reg(11) <= crc_reg(10);
crc_reg(12) <= crc_reg(11) xor crc_reg(15) xor serial_in;
crc_reg(13) <= crc_reg(12);
crc_reg(14) <= crc_reg(13);
crc_reg(15) <= crc_reg(14);
end if;
end process;
end rtl;
| mit | 969f3091c7b930b3ead1f2328fe9772b | 0.493068 | 3.473515 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_dma_v7_1/hdl/src/vhdl/axi_dma_afifo_autord.vhd | 1 | 17,654 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.async_fifo_fg;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_dma_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_dma_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_dma_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
ATTRIBUTE async_reg : STRING;
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read_cdc_tig : std_logic := '0';
Signal first_read1 : std_logic := '0';
Signal first_read2 : std_logic := '0';
signal AFIFO_Ainit_d1_cdc_tig : std_logic;
signal AFIFO_Ainit_d2 : std_logic;
--ATTRIBUTE async_reg OF AFIFO_Ainit_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF AFIFO_Ainit_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF first_read1 : SIGNAL IS "true";
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity proc_common_v4_0.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0,
C_SYNCHRONIZER_STAGE => C_FIFO_MTBF
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit_d2 or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_SYNC_FLOP : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => AFIFO_Ainit,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => AFIFO_Ainit_d2,
scndry_vect_out => open
);
-- IMP_SYNC_FLOP : process (AFIFO_Rd_clk)
-- begin
-- if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
-- AFIFO_Ainit_d1_cdc_tig <= AFIFO_Ainit;
-- AFIFO_Ainit_d2 <= AFIFO_Ainit_d1_cdc_tig;
-- end if;
-- end process IMP_SYNC_FLOP;
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk)
begin
if (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
IMP_SYNC_FLOP1 : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => first_write,
prmry_vect_in => (others => '0'),
scndry_aclk => AFIFO_Rd_clk,
scndry_resetn => '0',
scndry_out => first_read1,
scndry_vect_out => open
);
process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (AFIFO_Ainit_d2 = '0') then
first_read2 <= '0';
elsif (sig_afifo_empty = '0') then
first_read2 <= first_read1;
end if;
end if;
end process;
autoread <= first_read1 xor first_read2;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
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`protect end_protected
| bsd-2-clause | 33305040c8fdad1df66e7a56e965c8b7 | 0.936757 | 1.887289 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_013_test_input.vhd | 1 | 607 |
architecture RTL of ENTITY1 is
constant c_size : integer := 5;
constant c_ones : std_logic_vector(C_SIZE - 1 downto 0) := (others => '1');
constant c_zeros : std_logic_vector(c_size - 1 downto 0) := (others => '0');
signal data : std_logic_vector(c_size - 1 downto 0);
begin
data <= C_ONES;
PROC_NAME : process () is
begin
data <= C_ones & c_Zeros;
if (sig2 = '0') then
data <= c_Zeros;
end if;
if (sig2 = '1') then
data <= c_ones;
end if;
if (sig3 = '1') then
data <= c_zeros;
end if;
end process PROC_NAME;
end architecture RTL;
| gpl-3.0 | 99e554a50e9c5eacd686030b70b0a3c0 | 0.565074 | 3.050251 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/code_examples/c16/data_core.vhd | 1 | 4,682 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.cpu_pack.ALL;
entity data_core is
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CLR : in std_logic;
CE : in std_logic;
-- select signals
SX : in std_logic_vector( 1 downto 0);
SY : in std_logic_vector( 3 downto 0);
OP : in std_logic_vector( 4 downto 0); -- alu op
PC : in std_logic_vector(15 downto 0); -- PC
QU : in std_logic_vector( 3 downto 0); -- quick operand
SA : in std_logic_vector(4 downto 0); -- select address
SMQ : in std_logic; -- select MQ (H/L)
-- write enable/select signal
WE_RR : in std_logic;
WE_LL : in std_logic;
WE_SP : in SP_OP;
-- data in signals
IMM : in std_logic_vector(15 downto 0); -- immediate data
RDAT : in std_logic_vector( 7 downto 0); -- memory/IO data
-- memory control signals
ADR : out std_logic_vector(15 downto 0);
MQ : out std_logic_vector( 7 downto 0);
Q_RR : out std_logic_vector(15 downto 0);
Q_LL : out std_logic_vector(15 downto 0);
Q_SP : out std_logic_vector(15 downto 0)
);
end data_core;
architecture Behavioral of data_core is
function b8(A : std_logic) return std_logic_vector is
begin
return A & A & A & A & A & A & A & A;
end;
COMPONENT alu8
PORT( CLK_I : in std_logic;
T2 : in std_logic;
CE : in std_logic;
CLR : in std_logic;
ALU_OP : IN std_logic_vector( 4 downto 0);
XX : IN std_logic_vector(15 downto 0);
YY : IN std_logic_vector(15 downto 0);
ZZ : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT select_yy
PORT( SY : IN std_logic_vector( 3 downto 0);
IMM : IN std_logic_vector(15 downto 0);
QUICK : IN std_logic_vector( 3 downto 0);
RDAT : IN std_logic_vector( 7 downto 0);
RR : IN std_logic_vector(15 downto 0);
YY : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
-- cpu registers
--
signal RR : std_logic_vector(15 downto 0);
signal LL : std_logic_vector(15 downto 0);
signal SP : std_logic_vector(15 downto 0);
-- internal buses
--
signal XX : std_logic_vector(15 downto 0);
signal YY : std_logic_vector(15 downto 0);
signal ZZ : std_logic_vector(15 downto 0);
signal ADR_X : std_logic_vector(15 downto 0);
signal ADR_Z : std_logic_vector(15 downto 0);
signal ADR_YZ : std_logic_vector(15 downto 0);
signal ADR_XYZ : std_logic_vector(15 downto 0);
begin
alu_8: alu8
PORT MAP( CLK_I => CLK_I,
T2 => T2,
CE => CE,
CLR => CLR,
ALU_OP => OP,
XX => XX,
YY => YY,
ZZ => ZZ
);
selyy: select_yy
PORT MAP( SY => SY,
IMM => IMM,
QUICK => QU,
RDAT => RDAT,
RR => RR,
YY => YY
);
ADR <= ADR_XYZ;
MQ <= ZZ(15 downto 8) when SMQ = '1' else ZZ(7 downto 0);
Q_RR <= RR;
Q_LL <= LL;
Q_SP <= SP;
-- memory address
--
sel_ax: process(SA(4 downto 3), IMM)
variable SAX : std_logic_vector(4 downto 3);
begin
SAX := SA(4 downto 3);
case SAX is
when SA_43_I16 => ADR_X <= IMM;
when SA_43_I8S => ADR_X <= b8(IMM(7)) & IMM(7 downto 0);
when others => ADR_X <= b8(SA(3)) & b8(SA(3));
end case;
end process;
sel_az: process(SA(2 downto 1), LL, RR, SP)
variable SAZ : std_logic_vector(2 downto 1);
begin
SAZ := SA(2 downto 1);
case SAZ is
when SA_21_0 => ADR_Z <= X"0000";
when SA_21_LL => ADR_Z <= LL;
when SA_21_RR => ADR_Z <= RR;
when others => ADR_Z <= SP;
end case;
end process;
sel_ayz: process(SA(0), ADR_Z)
begin
ADR_YZ <= ADR_Z + (X"000" & "000" & SA(0));
end process;
sel_axyz: process(ADR_X, ADR_YZ)
begin
ADR_XYZ <= ADR_X + ADR_YZ;
end process;
sel_xx: process(SX, LL, RR, SP, PC)
begin
case SX is
when SX_LL => XX <= LL;
when SX_RR => XX <= RR;
when SX_SP => XX <= SP;
when others => XX <= PC;
end case;
end process;
regs: process(CLK_I)
begin
if (rising_edge(CLK_I)) then
if (CLR = '1') then
RR <= X"0000";
LL <= X"0000";
SP <= X"0000";
elsif (CE = '1' and T2 = '1') then
if (WE_RR = '1') then RR <= ZZ; end if;
if (WE_LL = '1') then LL <= ZZ; end if;
case WE_SP is
when SP_INC => SP <= ADR_YZ;
when SP_LOAD => SP <= ADR_XYZ;
when SP_NOP => null;
end case;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 1dfcc050a24a6534d26ce03e3b50f726 | 0.568774 | 2.557073 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_001_test_input.fixed.vhd | 1 | 583 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end CASE;
end process PROC_2;
PROC_3 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end Case;
end process PROC_3;
end architecture ARCH;
| gpl-3.0 | 77fe944d4bb91bbd8ce4e33da674a110 | 0.466552 | 3.275281 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/case/rule_010_test_input.vhd | 1 | 433 |
architecture ARCH of ENTITY is
begin
PROC_1 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1 =>
a <= b;
b <= c;
c <= d;
end case;
end process PROC_1;
PROC_2 : process (a, b, c) is
begin
case boolean_1 is
when STATE_1=>
a <= b;
b <= c;
c <= d;
end case;
sig1 <= sig2;
end process PROC_2;
end architecture ARCH;
| gpl-3.0 | 9ddb7aeeea02b60d55c7c94a223fd502 | 0.475751 | 3.305344 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/dpr_mem.vhd | 2 | 19,986 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13056)
`protect data_block
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35/E
`protect end_protected
| mit | f2b8e419134b4d9f00be2338201f7058 | 0.941309 | 1.852614 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/ddr3k7-core/ddr3_ctrl_wb.vhd | 1 | 20,464 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: DDR3 Wishbone control core
-- Module Name: ddr3_ctrl_wb - Behavioral
-- Project Name: YARR
-- Target Devices:
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
-- Wishbone to Xilinx MiG interface
-- Dependencies:
-- ddr3_read_core
-- ddr3_write_core
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ddr3_ctrl_wb is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
----------------------------------------------------------------------------
-- Status
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- DDR controller port
----------------------------------------------------------------------------
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_sr_req_o : out std_logic;
ddr_ref_req_o : out std_logic;
ddr_zq_req_o : out std_logic;
ddr_sr_active_i : in std_logic;
ddr_ref_ack_i : in std_logic;
ddr_zq_ack_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_ui_clk_sync_rst_i : in std_logic;
ddr_init_calib_complete_i : in std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb_clk_i : in std_logic;
wb_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_addr_i : in std_logic_vector(32 - 1 downto 0);
wb_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Wishbone bus port
----------------------------------------------------------------------------
wb1_sel_i : in std_logic_vector(g_MASK_SIZE - 1 downto 0);
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(32 - 1 downto 0);
wb1_data_i : in std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
wb1_stall_o : out std_logic;
----------------------------------------------------------------------------
-- Debug ports
----------------------------------------------------------------------------
ddr_wb_rd_mask_dout_do : out std_logic_vector(7 downto 0);
ddr_wb_rd_mask_addr_dout_do : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_rd_mask_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_data_rd_data_count_do : out std_logic_vector(3 downto 0);
ddr_rd_fifo_full_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_empty_do : out std_logic_vector(1 downto 0);
ddr_rd_fifo_rd_do : out std_logic_vector(1 downto 0)
);
end entity ddr3_ctrl_wb;
architecture behavioral of ddr3_ctrl_wb is
component ddr3_write_core is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
Port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
wb_clk_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_stall_o : out STD_LOGIC;
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_wdf_data_o : out std_logic_vector(511 downto 0);
ddr_wdf_end_o : out std_logic;
ddr_wdf_mask_o : out std_logic_vector(63 downto 0);
ddr_wdf_wren_o : out std_logic;
ddr_rdy_i : in std_logic;
ddr_wdf_rdy_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_req_o : out std_logic;
ddr_gnt_i : in std_logic
);
end component;
component ddr3_read_core is
generic (
g_BYTE_ADDR_WIDTH : integer := 29;
g_MASK_SIZE : integer := 8;
g_DATA_PORT_SIZE : integer := 64;
g_NOT_CONSECUTIVE_DETECTION : boolean := false
);
Port (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i : in std_logic;
wb_clk_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (g_MASK_SIZE - 1 downto 0);
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_adr_i : in STD_LOGIC_VECTOR (32 - 1 downto 0);
wb_dat_i : in STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_dat_o : out STD_LOGIC_VECTOR (g_DATA_PORT_SIZE - 1 downto 0);
wb_ack_o : out STD_LOGIC;
wb_stall_o : out STD_LOGIC;
ddr_addr_o : out std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
ddr_cmd_o : out std_logic_vector(2 downto 0);
ddr_cmd_en_o : out std_logic;
ddr_rd_data_i : in std_logic_vector(511 downto 0);
ddr_rd_data_end_i : in std_logic;
ddr_rd_data_valid_i : in std_logic;
ddr_rdy_i : in std_logic;
ddr_ui_clk_i : in std_logic;
ddr_req_o : out std_logic;
ddr_gnt_i : in std_logic
);
end component;
component rr_arbiter is
generic (
g_CHANNELS : integer := 16
);
port (
-- sys connect
clk_i : in std_logic;
rst_i : in std_logic;
-- requests
req_i : in std_logic_vector(g_CHANNELS-1 downto 0);
-- grant
gnt_o : out std_logic_vector(g_CHANNELS-1 downto 0)
);
end component;
--------------------------------------
-- Constants
--------------------------------------
constant c_register_shift_size : integer := 8;
constant c_wb_wr0_nb : integer := 0;
constant c_wb_wr1_nb : integer := 1;
constant c_wb_rd0_nb : integer := 2;
type data_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
type mask_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_MASK_SIZE - 1 downto 0);
type addr_array is array (0 to c_register_shift_size-1) of std_logic_vector(g_BYTE_ADDR_WIDTH - 1 downto 0);
type row_array is array (0 to c_register_shift_size-1) of std_logic_vector(c_register_shift_size-1 downto 0);
--------------------------------------
-- Signals
--------------------------------------
signal rst_s : std_logic;
signal rr_rst_s : std_logic;
signal wb_sel_s : std_logic_vector(g_MASK_SIZE - 1 downto 0);
signal wb_cyc_s : std_logic;
signal wb_stb_s : std_logic;
signal wb_we_s : std_logic;
signal wb_addr_s : std_logic_vector(32 - 1 downto 0);
signal wb_data_s : std_logic_vector(g_DATA_PORT_SIZE - 1 downto 0);
signal ddr_wr_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal ddr_wr_cmd_s : std_logic_vector(2 downto 0);
signal ddr_wr_cmd_en_s: std_logic;
signal ddr_wdf_data_s : std_logic_vector(511 downto 0);
signal ddr_wdf_end_s : std_logic;
signal ddr_wdf_mask_s : std_logic_vector(63 downto 0);
signal ddr_wdf_wren_s : std_logic;
signal ddr1_wr_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal ddr1_wr_cmd_s : std_logic_vector(2 downto 0);
signal ddr1_wr_cmd_en_s: std_logic;
signal ddr1_wdf_data_s : std_logic_vector(511 downto 0);
signal ddr1_wdf_end_s : std_logic;
signal ddr1_wdf_mask_s : std_logic_vector(63 downto 0);
signal ddr1_wdf_wren_s : std_logic;
signal ddr_rd_addr_s : std_logic_vector(g_BYTE_ADDR_WIDTH-1 downto 0);
signal ddr_rd_cmd_s : std_logic_vector(2 downto 0);
signal ddr_rd_cmd_en_s : std_logic;
signal ddr_rd_data_s : std_logic_vector(511 downto 0);
signal ddr_rd_data_end_s : std_logic;
signal ddr_rd_data_valid_s : std_logic;
signal arb_req_s : std_logic_vector(2 downto 0);
signal arb_gnt_s : std_logic_vector(2 downto 0);
signal wb_wr_stall_s : std_logic;
signal wb1_wr_stall_s : std_logic;
signal wb_rd_stall_s : std_logic;
signal wb_wr_ack_s : std_logic;
signal wb1_wr_ack_s : std_logic;
signal wb_rd_ack_s : std_logic;
--------------------------------------
-- Counter
--------------------------------------
signal wb_write_wait_cnt : unsigned(7 downto 0);
signal wb_read_wait_cnt : unsigned(7 downto 0);
begin
rst_s <= not rst_n_i;
rr_rst_s <= rst_s or (not ddr_rdy_i) or (not ddr_wdf_rdy_i);
ddr_sr_req_o <= '0';
ddr_ref_req_o <= '0';
ddr_zq_req_o <= '0';
--------------------------------------
-- Wishbone input delay
--------------------------------------
p_wb_in : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_sel_s <= (others =>'0');
wb_cyc_s <= '0';
wb_stb_s <= '0';
wb_we_s <= '0';
wb_addr_s <= (others =>'0');
wb_data_s <= (others =>'0');
elsif rising_edge(wb_clk_i) then
wb_sel_s <= wb_sel_i;
wb_cyc_s <= wb_cyc_i;
wb_stb_s <= wb_stb_i;
wb_we_s <= wb_we_i;
wb_addr_s <= wb_addr_i;
wb_data_s <= wb_data_i;
end if;
end process p_wb_in;
--------------------------------------
-- Wishbone ack and stall
--------------------------------------
wb_ack_o <= wb_wr_ack_s or wb_rd_ack_s;
wb_stall_o <= wb_wr_stall_s or wb_rd_stall_s;
wb1_ack_o <= wb1_wr_ack_s;
wb1_stall_o <= wb1_wr_stall_s;
--------------------------------------
-- Wishbone write
--------------------------------------
ddr3_write_core_cmp0:ddr3_write_core
generic map (
g_BYTE_ADDR_WIDTH => g_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_MASK_SIZE,
g_DATA_PORT_SIZE => g_DATA_PORT_SIZE,
g_NOT_CONSECUTIVE_DETECTION => g_NOT_CONSECUTIVE_DETECTION
)
Port map (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_we_i => wb_we_i,
wb_adr_i => wb_addr_i,
wb_dat_i => wb_data_i,
wb_dat_o => open,
wb_ack_o => wb_wr_ack_s,
wb_stall_o => wb_wr_stall_s,
ddr_addr_o => ddr_wr_addr_s,
ddr_cmd_o => ddr_wr_cmd_s,
ddr_cmd_en_o => ddr_wr_cmd_en_s,
ddr_wdf_data_o => ddr_wdf_data_s,
ddr_wdf_end_o => ddr_wdf_end_s,
ddr_wdf_mask_o => ddr_wdf_mask_s,
ddr_wdf_wren_o => ddr_wdf_wren_s,
ddr_rdy_i => ddr_rdy_i,
ddr_wdf_rdy_i => ddr_wdf_rdy_i,
ddr_ui_clk_i => ddr_ui_clk_i,
ddr_req_o => arb_req_s(c_wb_wr0_nb),
ddr_gnt_i => arb_gnt_s(c_wb_wr0_nb)
);
ddr3_write_core_cmp1:ddr3_write_core
generic map (
g_BYTE_ADDR_WIDTH => g_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_MASK_SIZE,
g_DATA_PORT_SIZE => g_DATA_PORT_SIZE,
g_NOT_CONSECUTIVE_DETECTION => g_NOT_CONSECUTIVE_DETECTION
)
Port map (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_sel_i => wb1_sel_i,
wb_stb_i => wb1_stb_i,
wb_cyc_i => wb1_cyc_i,
wb_we_i => wb1_we_i,
wb_adr_i => wb1_addr_i,
wb_dat_i => wb1_data_i,
wb_dat_o => wb1_data_o,
wb_ack_o => wb1_wr_ack_s,
wb_stall_o => wb1_wr_stall_s,
ddr_addr_o => ddr1_wr_addr_s,
ddr_cmd_o => ddr1_wr_cmd_s,
ddr_cmd_en_o => ddr1_wr_cmd_en_s,
ddr_wdf_data_o => ddr1_wdf_data_s,
ddr_wdf_end_o => ddr1_wdf_end_s,
ddr_wdf_mask_o => ddr1_wdf_mask_s,
ddr_wdf_wren_o => ddr1_wdf_wren_s,
ddr_rdy_i => ddr_rdy_i,
ddr_wdf_rdy_i => ddr_wdf_rdy_i,
ddr_ui_clk_i => ddr_ui_clk_i,
ddr_req_o => arb_req_s(c_wb_wr1_nb),
ddr_gnt_i => arb_gnt_s(c_wb_wr1_nb)
);
--------------------------------------
-- Wishbone read
--------------------------------------
ddr3_read_core_cmp:ddr3_read_core
generic map (
g_BYTE_ADDR_WIDTH => g_BYTE_ADDR_WIDTH,
g_MASK_SIZE => g_MASK_SIZE,
g_DATA_PORT_SIZE => g_DATA_PORT_SIZE,
g_NOT_CONSECUTIVE_DETECTION => g_NOT_CONSECUTIVE_DETECTION
)
Port map (
----------------------------------------------------------------------------
-- Reset input (active low)
----------------------------------------------------------------------------
rst_n_i => rst_n_i,
wb_clk_i => wb_clk_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_we_i => wb_we_i,
wb_adr_i => wb_addr_i,
wb_dat_i => wb_data_i,
wb_dat_o => wb_data_o,
wb_ack_o => wb_rd_ack_s,
wb_stall_o => wb_rd_stall_s,
ddr_rd_data_i => ddr_rd_data_s,
ddr_rd_data_end_i => ddr_rd_data_end_s,
ddr_rd_data_valid_i => ddr_rd_data_valid_s,
ddr_addr_o => ddr_rd_addr_s,
ddr_cmd_o => ddr_rd_cmd_s,
ddr_cmd_en_o => ddr_rd_cmd_en_s,
ddr_rdy_i => ddr_rdy_i,
ddr_ui_clk_i => ddr_ui_clk_i,
ddr_req_o => arb_req_s(c_wb_rd0_nb),
ddr_gnt_i => arb_gnt_s(c_wb_rd0_nb)
);
--------------------------------------
-- DDR CMD
--------------------------------------
ddr_addr_o <= ddr_wr_addr_s when arb_gnt_s(c_wb_wr0_nb) = '1' else
ddr_rd_addr_s when arb_gnt_s(c_wb_rd0_nb) = '1' else
ddr1_wr_addr_s when arb_gnt_s(c_wb_wr1_nb) = '1' else
(others => '0');
ddr_cmd_o <= ddr_wr_cmd_s when arb_gnt_s(c_wb_wr0_nb) = '1' else
ddr_rd_cmd_s when arb_gnt_s(c_wb_rd0_nb) = '1' else
ddr1_wr_cmd_s when arb_gnt_s(c_wb_wr1_nb) = '1' else
(others => '0');
ddr_cmd_en_o<= ddr_wr_cmd_en_s or ddr1_wr_cmd_en_s or ddr_rd_cmd_en_s;
cmp_rr_arbiter:rr_arbiter
generic map (
g_CHANNELS => 3
)
port map (
-- sys connect
clk_i => ddr_ui_clk_i,
rst_i => rr_rst_s,
-- requests
req_i => arb_req_s,
-- grant
gnt_o => arb_gnt_s
);
--------------------------------------
-- DDR Data out
--------------------------------------
ddr_wdf_data_o <= ddr_wdf_data_s when arb_gnt_s(c_wb_wr0_nb) = '1' else
ddr1_wdf_data_s;
ddr_wdf_end_o <= ddr_wdf_end_s when arb_gnt_s(c_wb_wr0_nb) = '1' else
ddr1_wdf_end_s;
ddr_wdf_mask_o <= ddr_wdf_mask_s when arb_gnt_s(c_wb_wr0_nb) = '1' else
ddr1_wdf_mask_s;
ddr_wdf_wren_o <= ddr_wdf_wren_s when arb_gnt_s(c_wb_wr0_nb) = '1' else
ddr1_wdf_wren_s;
--------------------------------------
-- DDR Data in
--------------------------------------
ddr_rd_data_s <= ddr_rd_data_i;
ddr_rd_data_end_s <= ddr_rd_data_end_i;
ddr_rd_data_valid_s <= ddr_rd_data_valid_i;
end architecture behavioral;
| gpl-3.0 | a9b18ca2d3dadf318b4eca77a3a36673 | 0.398016 | 3.621947 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/sim/cascaded_integrator_comb.vhd | 1 | 7,211 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0;
USE cic_compiler_v4_0.cic_compiler_v4_0;
ENTITY cascaded_integrator_comb IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END cascaded_integrator_comb;
ARCHITECTURE cascaded_integrator_comb_arch OF cascaded_integrator_comb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cascaded_integrator_comb_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0
GENERIC MAP (
C_COMPONENT_NAME => "cascaded_integrator_comb",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 5,
C_DIFF_DELAY => 1,
C_RATE => 16,
C_INPUT_WIDTH => 2,
C_OUTPUT_WIDTH => 22,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 16,
C_MAX_RATE => 16,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_C1 => 22,
C_C2 => 22,
C_C3 => 22,
C_C4 => 22,
C_C5 => 22,
C_C6 => 0,
C_I1 => 22,
C_I2 => 22,
C_I3 => 22,
C_I4 => 22,
C_I5 => 22,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 8,
C_M_AXIS_DATA_TDATA_WIDTH => 24,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END cascaded_integrator_comb_arch;
| mit | 7ae634e0b87f146e6362854d0673374e | 0.653585 | 3.396609 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/axi_slave_4to1.vhd | 3 | 47,179 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33184)
`protect data_block
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| mit | ea4813eba15c7ca9a663e8027abebd72 | 0.948113 | 1.826025 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/entity/rule_018_test_input.fixed_combined_generic.vhd | 1 | 662 |
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic := '0'; -- Comment
sig2 : std_logic := '1'; -- Comment
sig3 : std_logic := 'Z' -- Comment
);
end entity fifo;
| gpl-3.0 | 561ef4396d3a408e6af03ba9c5d28574 | 0.509063 | 3.152381 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux2_1_x_n.vhd | 1 | 5,422 | -------------------------------------------------------------------------------
-- axi_datamover_dre_mux2_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux2_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 2 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_dre_mux2_1_x_n.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 2 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux2_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 2x Mux slice
);
port (
Sel : In std_logic;
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 inputl
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux2_1_x_n; --
Architecture implementation of axi_datamover_dre_mux2_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT2_1
--
-- Process Description:
-- This process implements an 2 to 1 mux.
--
-------------------------------------------------------------
SELECT2_1 : process (Sel, I0, I1)
begin
case Sel is
when '0' =>
Y <= I0;
when '1' =>
Y <= I1;
when others =>
Y <= I0;
end case;
end process SELECT2_1;
end implementation; -- axi_datamover_dre_mux2_1_x_n
-------------------------------------------------------------------------------
-- End 2 to 1 xN Mux
-------------------------------------------------------------------------------
| bsd-2-clause | 1abbd673ade6d7668cce9b956e50a2f1 | 0.48377 | 4.920145 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/constant/rule_014_test_input.vhd | 1 | 735 |
architecture RTL of FIFO is
constant con1 : integer := a + b + c + d;
constant con1 : integer :=
a + b + c + d;
constant con2 : integer := a + b +
c + d;
constant con3 : integer :=
(
0,
1,
2,
3
);
constant con4 : dictionary :=
(
(3, 4, 5),
(1, 2, 3),
(9, 8, 7)
);
-- Violations
constant con2 : integer := a + b +
c + d;
constant con2 : integer := a + b +
c + d;
constant con1 : integer :=
a + b + c + d;
constant con3 : integer :=
(
0,
1,
2,
3
);
constant con4 : dictionary :=
(
(3, 4, 5),
(1, 2, 3),
(9, 8, 7)
);
begin
end architecture RTL;
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tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/blk_mem_gen_v8_0/blk_mem_axi_write_wrapper.vhd | 2 | 66,283 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | 0faf68a69feec1a3f39d660a8f8b218d | 0.950425 | 1.812844 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_generate_statement/rule_300_test_input.fixed.vhd | 1 | 297 |
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
elsif a = '0' generate
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
elsif a = '0' generate
end generate;
IF_LABEL : if a = '1' generate
elsif a = '0' generate
end generate;
end;
| gpl-3.0 | 3e0b8ca495e43cb59e9c81db449b7ba4 | 0.609428 | 3.263736 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd | 1 | 17,799 | -------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_skid2mm_buf.vhd
-- |
-- |- axi_datamover_wr_demux.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
| bsd-2-clause | 935f1a763a5c6c3fd89f757516735bab | 0.468453 | 4.47661 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/after/rule_002_test_input.vhd | 1 | 744 |
architecture ARCH of ENTITY is
begin
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
-- Violations
CLK_PROC : process (reset, clk) is
begin
if (reset = '1') then
a <= '0';
b <= '1';
c <= '0';
d <= '1';
elsif (clk'event and clk = '1') then
a <= b after 1 ns;
b <= c after 1 ns;
c <= d after 1 ns;
d <= e after 1 ns;
end if;
end process CLK_PROC;
end architecture ARCH;
| gpl-3.0 | 486a533ee1967dbda084d7acc33d12d9 | 0.443548 | 3.234783 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_010_test_input.fixed.vhd | 1 | 279 |
architecture RTL of FIFO is
begin
a <= b & c;
-- violations
a <= b & c;
a <= b & c;
a <= b & c;
-- Multiple violations
a <= b & c & d & e;
-- Extra spaces
a <= b & c & d & e;
-- This is okay
a <= b
& c
& d;
end architecture RTL;
| gpl-3.0 | bfea4430ca10d539d3a1277ba2f043c5 | 0.433692 | 3 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/wbexp-core/wbexp_core.vhd | 1 | 36,291 | ----------------------------------------------------------------------------------
-- Company: LBNL
-- Engineer: Arnaud Sautaux
--
-- Create Date: 07/27/2017 10:50:41 AM
-- Design Name: Wishbone express core
-- Module Name: wshexp_core - Behavioral
-- Project Name: YARR
-- Target Devices:
-- Tool Versions: Vivado v2016.2 (64 bit)
-- Description:
-- Wishbone express top level
-- Dependencies:
-- wbexp_core_pkg
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.wshexp_core_pkg.ALL;
entity wshexp_core is
Generic(
AXI_BUS_WIDTH : integer := 64
);
Port (
clk_i : in STD_LOGIC; --! PCIe user clock 250 MHz
wb_clk_i : in STD_LOGIC; --! Wishbone bus clock
rst_i : in STD_LOGIC; --! Reset input active high
---------------------------------------------------------
-- AXI-Stream bus
m_axis_tx_tready_i : in STD_LOGIC; --! AXI-Stream bus: Transmit destination ready to accept data
m_axis_tx_tdata_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0); --! AXI-Stream bus: Transmit data
m_axis_tx_tkeep_o : out STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0); --! AXI-Stream bus: Transmit data strobe
m_axis_tx_tlast_o : out STD_LOGIC; --! AXI-Stream bus: Indicates the last data beaf of a packet
m_axis_tx_tvalid_o : out STD_LOGIC; --! AXI-Stream bus: Indicates valid transmit data
m_axis_tx_tuser_o : out STD_LOGIC_VECTOR(3 DOWNTO 0); --! AXI-Stream bus: Indicates custom informations about the transmit destination [PG054]
s_axis_rx_tdata_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH-1 DOWNTO 0); --! AXI-Stream bus: Receive data
s_axis_rx_tkeep_i : in STD_LOGIC_VECTOR(AXI_BUS_WIDTH/8-1 DOWNTO 0); --! AXI-Stream bus: Receive data strobe
s_axis_rx_tlast_i : in STD_LOGIC; --! AXI-Stream bus: Indicates the last data beaf of a packet
s_axis_rx_tvalid_i : in STD_LOGIC; --! AXI-Stream bus: Indicates valid receive data
s_axis_rx_tready_o : out STD_LOGIC; --! AXI-Stream bus: Receive source ready to accept data
s_axis_rx_tuser_i : in STD_LOGIC_VECTOR(21 DOWNTO 0); --! AXI-Stream bus: Indicates custom informations about the receive source [PG054]
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_adr_o : out std_logic_vector(31 downto 0); --! DMA Wishbone Bus: Adress
dma_dat_o : out std_logic_vector(63 downto 0); --! DMA Wishbone Bus: Data out
dma_dat_i : in std_logic_vector(63 downto 0); --! DMA Wishbone Bus: Data in
dma_sel_o : out std_logic_vector(7 downto 0); --! DMA Wishbone Bus: Byte select
dma_cyc_o : out std_logic; --! DMA Wishbone Bus: Read or write cycle
dma_stb_o : out std_logic; --! DMA Wishbone Bus: Read or write strobe
dma_we_o : out std_logic; --! DMA Wishbone Bus: Write enable
dma_ack_i : in std_logic; --! DMA Wishbone Bus: Acknowledge
dma_stall_i : in std_logic; --! DMA Wishbone Bus: for pipelined Wishbone
---------------------------------------------------------
-- CSR wishbone interface (master classic)
csr_adr_o : out std_logic_vector(31 downto 0); --! CSR Wishbone Bus: Address
csr_dat_o : out std_logic_vector(31 downto 0); --! CSR Wishbone Bus: Data out
csr_sel_o : out std_logic_vector(3 downto 0); --! CSR Wishbone Bus: Byte select
csr_stb_o : out std_logic; --! CSR Wishbone Bus: Read or write cycle
csr_we_o : out std_logic; --! CSR Wishbone Bus: Write enable
csr_cyc_o : out std_logic; --! CSR Wishbone Bus: Read or write strobe
csr_dat_i : in std_logic_vector(31 downto 0); --! CSR Wishbone Bus: Data in
csr_ack_i : in std_logic; --! CSR Wishbone Bus: Acknoledge
csr_stall_i : in std_logic; --! CSR Wishbone Bus: for pipelined Wishbone
csr_err_i : in std_logic; --! CSR Wishbone Bus: Error
csr_rty_i : in std_logic; --! not used internally
csr_int_i : in std_logic; --! not used internally
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_adr_i : in std_logic_vector(31 downto 0); --! DMA Registers Bus: Address
dma_reg_dat_i : in std_logic_vector(31 downto 0); --! DMA Registers Bus: Data in
dma_reg_sel_i : in std_logic_vector(3 downto 0); --! DMA Registers Bus: Byte select
dma_reg_stb_i : in std_logic; --! DMA Registers Bus: Read or write strobe
dma_reg_we_i : in std_logic; --! DMA Registers Bus: Write enable
dma_reg_cyc_i : in std_logic; --! DMA Registers Bus: Read or write cycle
dma_reg_dat_o : out std_logic_vector(31 downto 0); --! DMA Registers Bus: Data out
dma_reg_ack_o : out std_logic; --! DMA Registers Bus: Acknoledge
dma_reg_stall_o : out std_logic; --! DMA Registers Bus: for pipelined wishbone
---------------------------------------------------------
-- PCIe interrupt config
cfg_interrupt_o : out STD_LOGIC; --! Interrupt request signal
cfg_interrupt_rdy_i : in STD_LOGIC; --! Interrupt grant signal
cfg_interrupt_assert_o : out STD_LOGIC; --! Not used
cfg_interrupt_di_o : out STD_LOGIC_VECTOR(7 DOWNTO 0); --! Interrupt message data out
cfg_interrupt_do_i : in STD_LOGIC_VECTOR(7 DOWNTO 0); --! Interrupt message data in
cfg_interrupt_mmenable_i : in STD_LOGIC_VECTOR(2 DOWNTO 0); --! Intteurpt multiple message enable
cfg_interrupt_msienable_i : in STD_LOGIC; --! Not used
cfg_interrupt_msixenable_i : in STD_LOGIC; --! Not used
cfg_interrupt_msixfm_i : in STD_LOGIC; --! Not used
cfg_interrupt_stat_o : out STD_LOGIC; --! Not used
cfg_pciecap_interrupt_msgnum_o : out STD_LOGIC_VECTOR(4 DOWNTO 0); --! Not used
---------------------------------------------------------
-- PCIe ID
cfg_bus_number_i : in STD_LOGIC_VECTOR(7 DOWNTO 0); --! PCIe bus number (usually 0)
cfg_device_number_i : in STD_LOGIC_VECTOR(4 DOWNTO 0); --! PCIe device number (lspci)
cfg_function_number_i : in STD_LOGIC_VECTOR(2 DOWNTO 0) --! PCIe function number (lspci)
);
end wshexp_core;
architecture Behavioral of wshexp_core is
constant axis_data_width_c : integer := 64;
---------------------------------------------------------
-- Reset and Clocks
signal rst_n_s : std_logic;
---------------------------------------------------------
-- PCIe
signal cfg_interrupt_s : std_logic;
signal pcie_id_s : std_logic_vector (15 downto 0); -- Completer/Requester ID
---------------------------------------------------------
-- Slave AXI-Stream from arbiter to pcie_tx
signal s_axis_rx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal s_axis_rx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal s_axis_rx_tuser_s : STD_LOGIC_VECTOR (21 downto 0);
signal s_axis_rx_tlast_s : STD_LOGIC;
signal s_axis_rx_tvalid_s :STD_LOGIC;
signal s_axis_rx_tready_s : STD_LOGIC;
---------------------------------------------------------
-- Master AXI-Stream pcie_rx to wishbone master
signal m_axis_tx_tdata_s : STD_LOGIC_VECTOR (axis_data_width_c - 1 downto 0);
signal m_axis_tx_tkeep_s : STD_LOGIC_VECTOR (axis_data_width_c/8 - 1 downto 0);
signal m_axis_tx_tuser_s : STD_LOGIC_VECTOR (3 downto 0);
signal m_axis_tx_tlast_s : STD_LOGIC;
signal m_axis_tx_tvalid_s : STD_LOGIC;
signal m_axis_tx_tready_s : STD_LOGIC;
---------------------------------------------------------
-- From Packet decoder to Wishbone master (wbm)
signal pd_wbm_address_s : STD_LOGIC_VECTOR(63 downto 0);
signal pd_wbm_data_s : STD_LOGIC_VECTOR(31 downto 0);
signal p2l_wbm_rdy_s : std_logic;
signal pd_pdm_data_valid_w_s : std_logic_vector(1 downto 0);
signal pd_wbm_valid_s : std_logic;
signal pd_wbm_hdr_rid_s : std_logic_vector(15 downto 0); -- Requester ID
signal pd_wbm_hdr_tag_s : std_logic_vector(7 downto 0);
signal pd_wbm_target_mrd_s : std_logic; -- Target memory read
signal pd_wbm_target_mwr_s : std_logic;
signal wbm_pd_ready_s : std_logic;
signal pd_op_s : STD_LOGIC_VECTOR(2 downto 0);
signal pd_header_type_s : STD_LOGIC;
signal pd_payload_length_s : STD_LOGIC_VECTOR(9 downto 0);
---------------------------------------------------------
-- From Wishbone master (wbm) to L2P DMA
signal pd_pdm_data_valid_s : STD_LOGIC;
signal pd_pdm_data_last_s : STD_LOGIC;
signal pd_pdm_data_s : STD_LOGIC_VECTOR(AXI_BUS_WIDTH - 1 downto 0);
signal pd_pdm_keep_s : std_logic_vector(7 downto 0);
signal p2l_dma_rdy_s : std_logic;
---------------------------------------------------------
-- From the DMA ctrl registers to the L2P DMA master and P2L DMA master
signal dma_ctrl_carrier_addr_s : std_logic_vector(31 downto 0);
signal dma_ctrl_host_addr_h_s : std_logic_vector(31 downto 0);
signal dma_ctrl_host_addr_l_s : std_logic_vector(31 downto 0);
signal dma_ctrl_len_s : std_logic_vector(31 downto 0);
signal dma_ctrl_start_l2p_s : std_logic; -- To the L2P DMA master
signal dma_ctrl_start_p2l_s : std_logic; -- To the P2L DMA master
signal dma_ctrl_start_next_s : std_logic; -- To the P2L DMA master
signal dma_ctrl_byte_swap_s : std_logic_vector(1 downto 0);
signal dma_ctrl_abort_s : std_logic;
signal dma_ctrl_done_s : std_logic;
signal dma_ctrl_error_s : std_logic;
signal dma_ctrl_l2p_done_s : std_logic;
signal dma_ctrl_l2p_error_s : std_logic;
signal dma_ctrl_p2l_done_s : std_logic;
signal dma_ctrl_p2l_error_s : std_logic;
---------------------------------------------------------
-- From P2L Master to the Arbiter
signal pdm_arb_tvalid_s : std_logic; -- Read completion signals
signal pdm_arb_tlast_s : std_logic; -- Toward the arbiter
signal pdm_arb_tdata_s : std_logic_vector(63 downto 0);
signal pdm_arb_tkeep_s : std_logic_vector(7 downto 0);
signal pdm_arb_req_s : std_logic;
signal pdm_arb_tready_s : std_logic;
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
signal p2l_dma_adr_s : std_logic_vector(31 downto 0); -- Adress
signal p2l_dma_dat_s2m_s : std_logic_vector(63 downto 0); -- Data in
signal p2l_dma_dat_m2s_s : std_logic_vector(63 downto 0); -- Data out
signal p2l_dma_sel_s : std_logic_vector(7 downto 0); -- Byte select
signal p2l_dma_cyc_s : std_logic; -- Read or write cycle
signal p2l_dma_stb_s : std_logic; -- Read or write strobe
signal p2l_dma_we_s : std_logic; -- Write
signal p2l_dma_ack_s : std_logic; -- Acknowledge
signal p2l_dma_stall_s : std_logic; -- for pipelined Wishbone
signal l2p_dma_adr_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_dat_s2m_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_dat_m2s_s : std_logic_vector(64-1 downto 0);
signal l2p_dma_sel_s : std_logic_vector(3 downto 0);
signal l2p_dma_cyc_s : std_logic;
signal l2p_dma_stb_s : std_logic;
signal l2p_dma_we_s : std_logic;
signal l2p_dma_ack_s : std_logic;
signal l2p_dma_stall_s : std_logic;
signal dma_adr_s : std_logic_vector(31 downto 0); -- Adress
signal dma_dat_s2m_s : std_logic_vector(63 downto 0); -- Data in
signal dma_dat_m2s_s : std_logic_vector(63 downto 0); -- Data out
signal dma_sel_s : std_logic_vector(7 downto 0); -- Byte select
signal dma_cyc_s : std_logic; -- Read or write cycle
signal dma_stb_s : std_logic; -- Read or write strobe
signal dma_we_s : std_logic; -- Write
signal dma_ack_s : std_logic; -- Acknowledge
signal dma_stall_s : std_logic; -- for pipelined Wishbone
---------------------------------------------------------
-- From DMA ctrl registers to PCIe
signal dma_ctrl_irq_s : std_logic_vector(1 downto 0);
---------------------------------------------------------
-- From P2L DMA master to DMA ctrl registers
signal next_item_carrier_addr_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_h_s : std_logic_vector(31 downto 0);
signal next_item_host_addr_l_s : std_logic_vector(31 downto 0);
signal next_item_len_s : std_logic_vector(31 downto 0);
signal next_item_next_l_s : std_logic_vector(31 downto 0);
signal next_item_next_h_s : std_logic_vector(31 downto 0);
signal next_item_attrib_s : std_logic_vector(31 downto 0);
signal next_item_valid_s : std_logic;
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
signal ldm_arb_tdata_s : std_logic_vector (AXI_BUS_WIDTH - 1 downto 0);
signal ldm_arb_tkeep_s : std_logic_vector (AXI_BUS_WIDTH/8 - 1 downto 0);
signal ldm_arb_tlast_s : std_logic;
signal ldm_arb_tvalid_s : std_logic;
signal ldm_arb_tready_s : std_logic;
signal ldm_arb_req_s : std_logic;
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
signal wbm_arb_tdata_s : std_logic_vector (AXI_BUS_WIDTH - 1 downto 0);
signal wbm_arb_tkeep_s : std_logic_vector (AXI_BUS_WIDTH/8 - 1 downto 0);
signal wbm_arb_tlast_s : std_logic;
signal wbm_arb_tvalid_s : std_logic;
signal wbm_arb_req_s : std_logic;
signal wbm_arb_tready_s : std_logic;
begin
rst_n_s <= not rst_i;
wbm_pd_ready_s <= p2l_wbm_rdy_s and p2l_dma_rdy_s;
-- Slave AXI-Stream
s_axis_rx_tdata_s <= s_axis_rx_tdata_i;
s_axis_rx_tkeep_s <= s_axis_rx_tkeep_i;
s_axis_rx_tlast_s <= s_axis_rx_tlast_i;
s_axis_rx_tready_o <= s_axis_rx_tready_s;
s_axis_rx_tuser_s <= s_axis_rx_tuser_i;
s_axis_rx_tvalid_s <= s_axis_rx_tvalid_i;
-- Master AXI-Stream
m_axis_tx_tdata_o <= m_axis_tx_tdata_s;
m_axis_tx_tkeep_o <= m_axis_tx_tkeep_s;
m_axis_tx_tuser_o <= m_axis_tx_tuser_s;
m_axis_tx_tlast_o <= m_axis_tx_tlast_s;
m_axis_tx_tvalid_o <= m_axis_tx_tvalid_s;
m_axis_tx_tready_s <= m_axis_tx_tready_i;
---------------------------------------------------------
-- PCIe interrupt and ID
cfg_interrupt_assert_o <= '0';
cfg_interrupt_di_o <= (others => '0');
cfg_interrupt_stat_o <= '0';
cfg_pciecap_interrupt_msgnum_o <= (others => '0');
cfg_interrupt_o <= cfg_interrupt_s;
interrupt_p : process(rst_i,clk_i,cfg_interrupt_rdy_i)
-- interrupt_p : process(rst_i,clk_i)
begin
if (rst_i = '1') then
cfg_interrupt_s <= '0';
elsif (cfg_interrupt_rdy_i = '1') then
cfg_interrupt_s <= '0';
elsif(clk_i'event and clk_i = '1') then
cfg_interrupt_s <= cfg_interrupt_s;
--if (cfg_interrupt_rdy_i = '1') then
--cfg_interrupt_s <= '0';
if (dma_ctrl_irq_s /= "00") then
cfg_interrupt_s <= '1';
end if;
end if;
end process interrupt_p;
id_p : process(rst_i,clk_i)
begin
if (rst_i = '1') then
pcie_id_s <= (others=> '0');
elsif(clk_i'event and clk_i = '1') then
pcie_id_s <= cfg_bus_number_i & cfg_device_number_i & cfg_function_number_i;
end if;
end process id_p;
-- DMA registers is a classic wishbone slave supporting single pipelined cycles
dma_reg_stall_o <= '0';
p2l_dec_comp:p2l_decoder
port map(
clk_i => clk_i,
rst_i => rst_i,
-- Slave AXI-Stream
s_axis_rx_tdata_i => s_axis_rx_tdata_s,
s_axis_rx_tkeep_i => s_axis_rx_tkeep_s,
s_axis_rx_tlast_i => s_axis_rx_tlast_s,
s_axis_rx_tready_o => s_axis_rx_tready_s,
s_axis_rx_tuser_i => s_axis_rx_tuser_s,
s_axis_rx_tvalid_i => s_axis_rx_tvalid_s,
-- To the wishbone master
pd_wbm_address_o => pd_wbm_address_s,
pd_wbm_data_o => pd_wbm_data_s,
pd_wbm_valid_o => pd_wbm_valid_s,
pd_wbm_hdr_rid_o => pd_wbm_hdr_rid_s,
pd_wbm_hdr_tag_o => pd_wbm_hdr_tag_s,
pd_wbm_target_mrd_o => pd_wbm_target_mrd_s,
pd_wbm_target_mwr_o => pd_wbm_target_mwr_s,
wbm_pd_ready_i => wbm_pd_ready_s,
pd_op_o => pd_op_s,
pd_header_type_o => pd_header_type_s,
pd_payload_length_o => pd_payload_length_s,
-- L2P DMA
pd_pdm_data_valid_o => pd_pdm_data_valid_s,
pd_pdm_data_valid_w_o => pd_pdm_data_valid_w_s,
pd_pdm_data_last_o => pd_pdm_data_last_s,
pd_pdm_keep_o => pd_pdm_keep_s,
pd_pdm_data_o => pd_pdm_data_s
);
csr_adr_o(31) <= '0';
wb32:wbmaster32
generic map (
g_ACK_TIMEOUT => 100 -- Wishbone ACK timeout (in wb_clk cycles)
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- From P2L packet decoder
--
-- Header
pd_wbm_hdr_start_i => pd_wbm_valid_s, -- Header strobe
--pd_wbm_hdr_length_i : in std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
pd_wbm_hdr_rid_i => pd_wbm_hdr_rid_s, -- Requester ID
pd_wbm_hdr_cid_i => pcie_id_s, --X"0100", -- Completer ID
pd_wbm_hdr_tag_i => pd_wbm_hdr_tag_s,
pd_wbm_target_mrd_i => pd_wbm_target_mrd_s, -- Target memory read
pd_wbm_target_mwr_i => pd_wbm_target_mwr_s, -- Target memory write
--
-- Address
pd_wbm_addr_start_i => pd_wbm_valid_s, -- Address strobe
pd_wbm_addr_i => pd_wbm_address_s(31 downto 0),-- Target address (in byte) that will increment with data
-- increment = 4 bytes
--
-- Data
pd_wbm_data_valid_i => pd_wbm_valid_s, -- Indicates Data is valid
pd_wbm_data_i => pd_wbm_data_s, -- Data
---------------------------------------------------------
-- P2L channel control
p_wr_rdy_o => open,-- Ready to accept target write
p2l_rdy_o => p2l_wbm_rdy_s,--wbm_pd_ready_s, -- De-asserted to pause transfer already in progress
p_rd_d_rdy_i => "11",-- Asserted when GN4124 ready to accept read completion with data
---------------------------------------------------------
-- To the arbiter (L2P data)
wbm_arb_tdata_o => wbm_arb_tdata_s,
wbm_arb_tkeep_o => wbm_arb_tkeep_s,
wbm_arb_tlast_o => wbm_arb_tlast_s,
wbm_arb_tvalid_o => wbm_arb_tvalid_s,
wbm_arb_tready_i => wbm_arb_tready_s,
wbm_arb_req_o => wbm_arb_req_s,
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i => wb_clk_i, -- Wishbone bus clock
wb_adr_o => csr_adr_o(30 downto 0),-- Address
wb_dat_o => csr_dat_o,-- Data out
wb_sel_o => csr_sel_o, -- Byte select
wb_stb_o => csr_stb_o, -- Strobe
wb_we_o => csr_we_o, -- Write
wb_cyc_o => csr_cyc_o, -- Cycle
wb_dat_i => csr_dat_i,-- Data in
wb_ack_i => csr_ack_i, -- Acknowledge
wb_stall_i => csr_stall_i, -- Stall
wb_err_i => csr_err_i, -- Error
wb_rty_i => csr_rty_i, -- Retry
wb_int_i => csr_int_i -- Interrupt
);
p2l_dma:p2l_dma_master
generic map (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP => false
)
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
l2p_rid_i => pcie_id_s,
---------------------------------------------------------
-- From the DMA controller
dma_ctrl_carrier_addr_i => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_s,
dma_ctrl_len_i => dma_ctrl_len_s,
dma_ctrl_start_p2l_i => dma_ctrl_start_p2l_s,
dma_ctrl_start_next_i => dma_ctrl_start_next_s,
dma_ctrl_done_o => dma_ctrl_p2l_done_s,
dma_ctrl_error_o => dma_ctrl_p2l_error_s,
dma_ctrl_byte_swap_i => "111",
dma_ctrl_abort_i => dma_ctrl_abort_s,
---------------------------------------------------------
-- From P2L Decoder (receive the read completion)
--
-- Header
pd_pdm_master_cpld_i => '1', -- Master read completion with data
pd_pdm_master_cpln_i => '0', -- Master read completion without data
--
-- Data
pd_pdm_data_valid_i => pd_pdm_data_valid_s, -- Indicates Data is valid
pd_pdm_data_valid_w_i => pd_pdm_data_valid_w_s,
pd_pdm_data_last_i => pd_pdm_data_last_s, -- Indicates end of the packet
pd_pdm_data_i => pd_pdm_data_s, -- Data
pd_pdm_be_i => pd_pdm_keep_s, -- Byte Enable for data
---------------------------------------------------------
-- P2L control
p2l_rdy_o => p2l_dma_rdy_s, -- De-asserted to pause transfer already in progress
rx_error_o => open, -- Asserted when transfer is aborted
---------------------------------------------------------
-- To the P2L Interface (send the DMA Master Read request)
pdm_arb_tvalid_o => pdm_arb_tvalid_s, -- Read completion signals
pdm_arb_tlast_o => pdm_arb_tlast_s, -- Toward the arbiter
pdm_arb_tdata_o => pdm_arb_tdata_s,
pdm_arb_tkeep_o => pdm_arb_tkeep_s,
pdm_arb_req_o => pdm_arb_req_s,
arb_pdm_gnt_i => pdm_arb_tready_s,
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
p2l_dma_clk_i => wb_clk_i, -- Bus clock
p2l_dma_adr_o => p2l_dma_adr_s, -- Adress
p2l_dma_dat_i => p2l_dma_dat_s2m_s, -- Data in
p2l_dma_dat_o => p2l_dma_dat_m2s_s, -- Data out
p2l_dma_sel_o => p2l_dma_sel_s, -- Byte select
p2l_dma_cyc_o => p2l_dma_cyc_s, -- Read or write cycle
p2l_dma_stb_o => p2l_dma_stb_s, -- Read or write strobe
p2l_dma_we_o => p2l_dma_we_s, -- Write
p2l_dma_ack_i => p2l_dma_ack_s, -- Acknowledge
p2l_dma_stall_i => p2l_dma_stall_s, -- for pipelined Wishbone
l2p_dma_cyc_i => l2p_dma_cyc_s, -- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- To the DMA controller
next_item_carrier_addr_o => next_item_carrier_addr_s,
next_item_host_addr_h_o => next_item_host_addr_h_s,
next_item_host_addr_l_o => next_item_host_addr_l_s,
next_item_len_o => next_item_len_s,
next_item_next_l_o => next_item_next_l_s,
next_item_next_h_o => next_item_next_h_s,
next_item_attrib_o => next_item_attrib_s,
next_item_valid_o => next_item_valid_s
);
l2p_dma : l2p_dma_master
port map
(
clk_i => clk_i,
rst_n_i => rst_n_s,
l2p_rid_i => pcie_id_s,
dma_ctrl_target_addr_i => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_i => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_i => dma_ctrl_host_addr_l_s,
dma_ctrl_len_i => dma_ctrl_len_s,
dma_ctrl_start_l2p_i => dma_ctrl_start_l2p_s,
dma_ctrl_done_o => dma_ctrl_l2p_done_s,
dma_ctrl_error_o => dma_ctrl_l2p_error_s,
dma_ctrl_byte_swap_i => "000",
dma_ctrl_abort_i => dma_ctrl_abort_s,
ldm_arb_tvalid_o => ldm_arb_tvalid_s,
ldm_arb_tlast_o => ldm_arb_tlast_s,
ldm_arb_tdata_o => ldm_arb_tdata_s,
ldm_arb_tkeep_o => ldm_arb_tkeep_s,
ldm_arb_req_o => ldm_arb_req_s,
arb_ldm_gnt_i => ldm_arb_tready_s,
l2p_edb_o => open,
ldm_arb_tready_i => ldm_arb_tready_s,
l2p_rdy_i => '1',
tx_error_i => '0',
l2p_dma_clk_i => wb_clk_i,
l2p_dma_adr_o => l2p_dma_adr_s,
l2p_dma_dat_i => l2p_dma_dat_s2m_s,
l2p_dma_dat_o => l2p_dma_dat_m2s_s,
l2p_dma_sel_o => l2p_dma_sel_s,
l2p_dma_cyc_o => l2p_dma_cyc_s,
l2p_dma_stb_o => l2p_dma_stb_s,
l2p_dma_we_o => l2p_dma_we_s,
l2p_dma_ack_i => l2p_dma_ack_s,
l2p_dma_stall_i => l2p_dma_stall_s,
p2l_dma_cyc_i => p2l_dma_cyc_s--,
--DMA Debug
--l2p_current_state_do => l2p_current_state_ds,
--l2p_data_cnt_do => l2p_data_cnt_ds,
--l2p_len_cnt_do => l2p_len_cnt_ds,
--l2p_timeout_cnt_do => l2p_timeout_cnt_ds,
--wb_timeout_cnt_do => wb_timeout_cnt_ds,
-- Data FIFO
--data_fifo_rd_do => data_fifo_rd_ds,
--data_fifo_wr_do => data_fifo_wr_ds,
--data_fifo_empty_do => data_fifo_empty_ds,
--data_fifo_full_do => data_fifo_full_ds,
--data_fifo_dout_do => data_fifo_dout_ds,
--data_fifo_din_do => data_fifo_din_ds,
-- Addr FIFO
--addr_fifo_rd_do => addr_fifo_rd_ds,
--addr_fifo_wr_do => addr_fifo_wr_ds,
--addr_fifo_empty_do => addr_fifo_empty_ds,
--addr_fifo_full_do => addr_fifo_full_ds,
--addr_fifo_dout_do => addr_fifo_dout_ds,
--addr_fifo_din_do => addr_fifo_din_ds
);
dma_ctrl:dma_controller
port map
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- Interrupt request
dma_ctrl_irq_o => dma_ctrl_irq_s,
---------------------------------------------------------
-- To the L2P DMA master and P2L DMA master
dma_ctrl_carrier_addr_o => dma_ctrl_carrier_addr_s,
dma_ctrl_host_addr_h_o => dma_ctrl_host_addr_h_s,
dma_ctrl_host_addr_l_o => dma_ctrl_host_addr_l_s,
dma_ctrl_len_o => dma_ctrl_len_s,
dma_ctrl_start_l2p_o => dma_ctrl_start_l2p_s, -- To the L2P DMA master
dma_ctrl_start_p2l_o => dma_ctrl_start_p2l_s, -- To the P2L DMA master
dma_ctrl_start_next_o => dma_ctrl_start_next_s, -- To the P2L DMA master
dma_ctrl_byte_swap_o => dma_ctrl_byte_swap_s,
dma_ctrl_abort_o => dma_ctrl_abort_s,
dma_ctrl_done_i => dma_ctrl_done_s,
dma_ctrl_error_i => dma_ctrl_error_s,
---------------------------------------------------------
-- From P2L DMA master
next_item_carrier_addr_i => next_item_carrier_addr_s,
next_item_host_addr_h_i => next_item_host_addr_h_s,
next_item_host_addr_l_i => next_item_host_addr_l_s,
next_item_len_i => next_item_len_s,
next_item_next_l_i => next_item_next_l_s,
next_item_next_h_i => next_item_next_h_s,
next_item_attrib_i => next_item_attrib_s,
next_item_valid_i => next_item_valid_s,
---------------------------------------------------------
-- Wishbone slave interface
wb_clk_i => wb_clk_i, -- Bus clock
wb_adr_i => dma_reg_adr_i(3 downto 0), -- Adress
wb_dat_o => dma_reg_dat_o, -- Data in
wb_dat_i => dma_reg_dat_i, -- Data out
wb_sel_i => dma_reg_sel_i, -- Byte select
wb_cyc_i => dma_reg_cyc_i, -- Read or write cycle
wb_stb_i => dma_reg_stb_i, -- Read or write strobe
wb_we_i => dma_reg_we_i, -- Write
wb_ack_o => dma_reg_ack_o--, -- Acknowledge
---------------------------------------------------------
-- Debug interface
--dma_ctrl_current_state_do => dma_ctrl_current_state_ds,
--dma_ctrl_do => dma_ctrl_ds,
--dma_stat_do => dma_stat_ds,
--dma_attrib_do => dma_attrib_ds
);
-- Status signals from DMA masters
dma_ctrl_done_s <= dma_ctrl_l2p_done_s or dma_ctrl_p2l_done_s;
dma_ctrl_error_s <= dma_ctrl_l2p_error_s or dma_ctrl_p2l_error_s;
arbiter:l2p_arbiter
port map(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => clk_i,
rst_n_i => rst_n_s,
---------------------------------------------------------
-- From Wishbone master (wbm) to arbiter (arb)
wbm_arb_tdata_i => wbm_arb_tdata_s,
wbm_arb_tkeep_i => wbm_arb_tkeep_s,
wbm_arb_tlast_i => wbm_arb_tlast_s,
wbm_arb_tvalid_i => wbm_arb_tvalid_s,
wbm_arb_req_i => wbm_arb_req_s,
wbm_arb_tready_o => wbm_arb_tready_s,
---------------------------------------------------------
-- From P2L DMA master (pdm) to arbiter (arb)
pdm_arb_tdata_i => pdm_arb_tdata_s,
pdm_arb_tkeep_i => pdm_arb_tkeep_s,
pdm_arb_tlast_i => pdm_arb_tlast_s,
pdm_arb_tvalid_i => pdm_arb_tvalid_s,
pdm_arb_req_i => pdm_arb_req_s,
pdm_arb_tready_o => pdm_arb_tready_s,
arb_pdm_gnt_o => open,
---------------------------------------------------------
-- From L2P DMA master (ldm) to arbiter (arb)
ldm_arb_tdata_i => ldm_arb_tdata_s,
ldm_arb_tkeep_i => ldm_arb_tkeep_s,
ldm_arb_tlast_i => ldm_arb_tlast_s,
ldm_arb_tvalid_i => ldm_arb_tvalid_s,
ldm_arb_req_i => ldm_arb_req_s,
ldm_arb_tready_o => ldm_arb_tready_s,
arb_ldm_gnt_o => open,
---------------------------------------------------------
-- From arbiter (arb) to pcie_tx (tx)
axis_tx_tdata_o => m_axis_tx_tdata_s,
axis_tx_tkeep_o => m_axis_tx_tkeep_s,
axis_tx_tuser_o => m_axis_tx_tuser_s,
axis_tx_tlast_o => m_axis_tx_tlast_s,
axis_tx_tvalid_o => m_axis_tx_tvalid_s,
axis_tx_tready_i => m_axis_tx_tready_s--,
---------------------------------------------------------
-- Debug
--eop_do => eop_s
);
dma_mux: process(
l2p_dma_adr_s,l2p_dma_dat_m2s_s,l2p_dma_sel_s,l2p_dma_cyc_s,l2p_dma_stb_s,l2p_dma_we_s,
p2l_dma_adr_s,p2l_dma_dat_m2s_s,p2l_dma_sel_s,p2l_dma_cyc_s,p2l_dma_stb_s,p2l_dma_we_s)
begin
if l2p_dma_cyc_s = '1' then
dma_adr_s <= l2p_dma_adr_s(31 downto 0);
dma_dat_m2s_s <= l2p_dma_dat_m2s_s;
dma_sel_s <= l2p_dma_sel_s & l2p_dma_sel_s;
dma_cyc_s <= l2p_dma_cyc_s;
dma_stb_s <= l2p_dma_stb_s;
dma_we_s <= l2p_dma_we_s;
elsif p2l_dma_cyc_s = '1' then
dma_adr_s <= p2l_dma_adr_s;
dma_dat_m2s_s <= p2l_dma_dat_m2s_s;
dma_sel_s <= p2l_dma_sel_s;
dma_cyc_s <= p2l_dma_cyc_s;
dma_stb_s <= p2l_dma_stb_s;
dma_we_s <= p2l_dma_we_s;
else
dma_adr_s <= (others => '0');
dma_dat_m2s_s <= (others => '0');
dma_sel_s <= (others => '0');
dma_cyc_s <= '0';
dma_stb_s <= '0';
dma_we_s <= '0';
end if;
end process dma_mux;
l2p_dma_dat_s2m_s <= dma_dat_s2m_s;
p2l_dma_dat_s2m_s <= dma_dat_s2m_s;
l2p_dma_ack_s <= dma_ack_s;
p2l_dma_ack_s <= dma_ack_s;
l2p_dma_stall_s <= dma_stall_s;
p2l_dma_stall_s <= dma_stall_s;
--dma_stall_s <= '0';
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_adr_o <= dma_adr_s;
dma_dat_o <= dma_dat_m2s_s;
dma_dat_s2m_s <= dma_dat_i;
dma_sel_o <= dma_sel_s;
dma_cyc_o <= dma_cyc_s;
dma_stb_o <= dma_stb_s;
dma_we_o <= dma_we_s;
dma_ack_s <= dma_ack_i;
dma_stall_s <= dma_stall_i;
-- axis_debug : ila_axis
-- PORT MAP (
-- clk => clk_i,
-- probe0 => s_axis_rx_tdata_s,
-- probe1 => s_axis_rx_tkeep_s,
-- probe2(0) => s_axis_rx_tlast_s,
-- probe3(0) => s_axis_rx_tvalid_s,
-- probe4(0) => s_axis_rx_tready_s,
-- probe5 => m_axis_tx_tdata_s,
-- probe6 => m_axis_tx_tkeep_s,
-- probe7(0) => m_axis_tx_tlast_s,
-- probe8(0) => m_axis_tx_tvalid_s,
-- probe9(0) => m_axis_tx_tready_s,
-- probe10 => s_axis_rx_tuser_i,
-- probe11(0) => dma_ctrl_start_l2p_s,
-- probe12(0) => dma_ctrl_start_p2l_s,
-- probe13(0) => dma_ctrl_start_next_s,
-- probe14(0) => dma_ctrl_abort_s,
-- probe15(0) => dma_ctrl_done_s,
-- probe16(0) => dma_ctrl_error_s,
-- probe17(0) => '0',--user_lnk_up_i,
-- probe18(0) => '0',--cfg_interrupt_s,
-- probe19(0) => '0',--cfg_interrupt_rdy_i,
-- probe20(0) => '0',--dma_ctrl_done_s,
-- probe21 => (others => '0'),--wbm_arb_tready_s & wbm_arb_tready_s & ldm_arb_tready_s,--dma_ctrl_current_state_ds,
-- probe22(0) => next_item_valid_s, --tx_err_drop_i,
-- probe23 => (others => '0')--iteration_count_s
-- );
-- pipelined_wishbone_debug : ila_wsh_pipe
-- PORT MAP (
-- clk => wb_clk_i,
-- probe0 => dma_adr_s,
-- probe1 => dma_dat_s2m_s,
-- probe2 => dma_dat_m2s_s,
-- probe3 => dma_sel_s,
-- probe4(0) => dma_cyc_s,
-- probe5(0) => dma_stb_s,
-- probe6(0) => dma_we_s,
-- probe7(0) => dma_ack_s,
-- probe8(0) => dma_stall_s,
-- probe9(0) => l2p_dma_cyc_s,
-- probe10(0) => p2l_dma_cyc_s,
-- probe11(0) => dma_ctrl_start_l2p_s,
-- probe12(0) => dma_ctrl_start_p2l_s,
-- probe13(0) => dma_ctrl_start_next_s,
-- probe14 => (others => '0'),--ddr_rd_mask_rd_data_count_ds,
-- probe15 => (others => '0'),--ddr_rd_data_rd_data_count_ds,
-- probe16 => (others => '0'),--ddr_wb_rd_mask_addr_dout_ds & ddr_wb_rd_mask_dout_ds,
-- probe17 => (others => '0')--iteration_count_s
-- );
end Behavioral;
| gpl-3.0 | 4c8e6ca8e8b42530f887c4d3c15b0943 | 0.494778 | 3.146164 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/ALU.vhd | 1 | 2,900 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:54:00 10/26/2015
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_UNSIGNED.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
RESULT : out STD_LOGIC_VECTOR (7 downto 0);
C : out STD_LOGIC;
Z : out STD_LOGIC);
end ALU;
architecture Behavioral of ALU is
begin
process(A, B, Cin, SEL)
variable v_res : std_logic_vector(8 downto 0);
variable tmp : std_logic_vector(8 downto 0);
begin
case SEL is
when "0000" => --Add
v_res := ('0' & A) + ('0' & B);
C <= v_res(8);
when "0001" => --AddC
v_res := ('0' & A) + ('0' & B) + Cin;
C <= v_res(8);
when "0010" => --Sub
v_res := ('0' & A) - ('0' & B);
C <= v_res(8);
when "0011" => --SubC
v_res := ('0' & A) - ('0' & B) - Cin;
C <= v_res(8);
when "0100" => --Cmp
tmp := ('0' & A) - ('0' & B);
v_res := tmp;
C <= tmp(8);
if(tmp = "000000000") then z <= '1';
end if;
when "0101" => --And
v_res := '0' & (A and B);
C <= '0';
when "0110" => --Or
v_res := '0' & (A or B);
C <= '0';
when "0111" => --Exor
v_res := '0' & (A xor B);
C <= '0';
when "1000" => --Test
tmp := '0' & (A and B);
v_res := tmp;
C <= '0';
if(tmp = "000000000") then z <= '1';
end if;
when "1001" => --LSL
v_res := A & Cin;
C <= v_res(8);
when "1010" => --LSR
tmp := Cin & A;
v_res := '0' & tmp(8 downto 1);
c <= A(0);
when "1011" => --ROL
v_res := '0' & A(6 downto 0) & A(7);
c <= A(7);
when "1100" => --ROAR
v_res := '0' & A(0) & A(7 downto 1);
C <= A(0);
when "1101" => --ASR
v_res := '0' & A(7) & A(7 downto 1);
C <= A(0);
when "1110" => --MOV
v_res := '0' & B;
C <= Cin;
when others =>
v_res := (others => '1');
c <= Cin;
end case;
if (v_res(7 downto 0) = x"00") then
z <= '1';
else
z <= '0';
end if;
Result <= v_res(7 downto 0);
end process;
end Behavioral;
| mit | f202156d7bb97d865d5bd105b524cdaa | 0.458966 | 2.783109 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/procedure_call/rule_401_test_input.vhd | 1 | 500 |
architecture rtl of fifo is
begin
-- Valid formatting
connect_ports(
port_1 => data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
-- Invalid formatting
process
begin
connect_ports(
port_1 => data,
port_2=> enable,
port_3 => overflow,
port_4 => underflow
);
end process;
connect_ports(
port_1=> data,
port_2 => enable,
port_3 => overflow,
port_4 => underflow
);
end architecture;
| gpl-3.0 | a671ed7455f56538df13dcd7283ddfa8 | 0.548 | 3.649635 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd | 1 | 72,317 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_full_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_full_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Full Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_mm2s_full_wrap.vhd
-- |
-- |-- axi_datamover_reset.vhd
-- |-- axi_datamover_cmd_status.vhd
-- |-- axi_datamover_pcc.vhd
-- |-- axi_datamover_mm2s_dre.vhd
-- |-- axi_datamover_addr_cntl.vhd
-- |-- axi_datamover_rddata_cntl.vhd
-- |-- axi_datamover_rd_status_cntl.vhd
-- |-- axi_datamover_skid2mm_buf.vhd
-- |-- axi_datamover_skid_buf
-- |-- axi_datamover_rd_sf
--
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
-- DET 5/9/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added General Purpose Store and Forward support.
-- ^^^^^^
--
-- DET 6/10/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- -- Per CR613147
-- - Routed the DRE Flush control from the RDC to the Read Store and
-- Forward instance.
-- ^^^^^^
--
-- DET 6/20/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Added 512 and 1024 data width support
-- ^^^^^^
--
-- DET 9/1/2011 Initial Version for EDK 13.3
-- ~~~~~~
-- - Per a Lint warning, added the output port mstr2dre_cmd_cmplt to the
-- instance of the PCC.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_reset;
use axi_datamover_v5_1.axi_datamover_cmd_status;
use axi_datamover_v5_1.axi_datamover_pcc;
use axi_datamover_v5_1.axi_datamover_addr_cntl;
use axi_datamover_v5_1.axi_datamover_rddata_cntl;
use axi_datamover_v5_1.axi_datamover_rd_status_cntl;
use axi_datamover_v5_1.axi_datamover_mm2s_dre;
Use axi_datamover_v5_1.axi_datamover_rd_sf;
use axi_datamover_v5_1.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_full_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 1;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Lite MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the incllusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit Store and Forward
-- 1 = Include Store and Forward
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ---------------------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- MM2S Halt request input control --------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Error discrete output ------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
-------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ---------
-- Used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
-------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ----------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
-------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -------------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
---------------------------------------------------------------
-- Address Posting contols ------------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
---------------------------------------------------------------
-- MM2S AXI Address Channel I/O ---------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals ------------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
------------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O -----------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
---------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
----------------------------------------------------------------------------------------
-- Testing Support I/O -------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------
);
end entity axi_datamover_mm2s_full_wrap;
architecture implementation of axi_datamover_mm2s_full_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 7 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when 256 =>
num_addr_bits_needed := 5;
when 512 =>
num_addr_bits_needed := 6;
when others => -- 1024 bits
num_addr_bits_needed := 7;
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_include_dre
--
-- Function Description:
-- This function desides if conditions are right for allowing DRE
-- inclusion.
--
-------------------------------------------------------------------
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width < 128 and
needed_data_width > 8) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_get_align_width
--
-- Function Description:
-- This function calculates the needed DRE alignment port width\
-- based upon the inclusion of DRE and the needed bit width of the
-- DRE.
--
-------------------------------------------------------------------
function func_get_align_width (dre_included : integer;
dre_data_width : integer) return integer is
Variable align_port_width : Integer := 1;
begin
if (dre_included = 1) then
If (dre_data_width = 64) Then
align_port_width := 3;
Elsif (dre_data_width = 32) Then
align_port_width := 2;
else -- 16 bit data width
align_port_width := 1;
End if;
else -- no DRE
align_port_width := 1;
end if;
Return (align_port_width);
end function func_get_align_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_sf_offset_width
--
-- Function Description:
-- This function calculates the address offset width needed by
-- the GP Store and Forward module with data packing.
--
-------------------------------------------------------------------
function funct_get_sf_offset_width (mmap_dwidth : integer;
stream_dwidth : integer) return integer is
Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth;
Variable fvar_temp_offset_width : Integer := 1;
begin
case FCONST_WIDTH_RATIO is
when 1 =>
fvar_temp_offset_width := 1;
when 2 =>
fvar_temp_offset_width := 1;
when 4 =>
fvar_temp_offset_width := 2;
when 8 =>
fvar_temp_offset_width := 3;
when 16 =>
fvar_temp_offset_width := 4;
when 32 =>
fvar_temp_offset_width := 5;
when 64 =>
fvar_temp_offset_width := 6;
when others => -- 128 ratio
fvar_temp_offset_width := 7;
end case;
Return (fvar_temp_offset_width);
end function funct_get_sf_offset_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stream_width2use
--
-- Function Description:
-- This function calculates the Stream width to use for MM2S
-- modules upstream from the downsizing Store and Forward. If
-- Store and Forward is present, then the effective native width
-- is the MMAP data width. If no Store and Forward then the Stream
-- width is the input Native Data width from the User.
--
-------------------------------------------------------------------
function funct_get_stream_width2use (mmap_data_width : integer;
stream_data_width : integer;
sf_enabled : integer) return integer is
Variable fvar_temp_width : Integer := 32;
begin
If (sf_enabled = 1) Then
fvar_temp_width := mmap_data_width;
Else
fvar_temp_width := stream_data_width;
End if;
Return (fvar_temp_width);
end function funct_get_stream_width2use;
-- Constant Declarations ----------------------------------------
Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH,
C_MM2S_SDATA_WIDTH,
C_INCLUDE_MM2S_GP_SF);
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S;
Constant IS_MM2S : integer range 0 to 1 := 1;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH;
Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE;
Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE;
Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH;
Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED;
Constant NO_INDET_BTT : integer range 0 to 1 := 0;
Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE,
C_MM2S_SDATA_WIDTH);
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE,
C_MM2S_SDATA_WIDTH);
-- Calculates the minimum needed depth of the Store and Forward FIFO
-- based on the MM2S pipeline depth and the max allowed Burst length
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE;
-- Assigns the depth of the optional Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-- Calculate the width of the Store and Forward Starting Address Offset bus
Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH,
MM2S_SDATA_WIDTH);
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_sf2rdc_wready : std_logic := '0';
signal sig_rdc2sf_wvalid : std_logic := '0';
signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_rdc2sf_wlast : std_logic := '0';
signal sig_skid2dre_wready : std_logic := '0';
signal sig_dre2skid_wvalid : std_logic := '0';
signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dre2skid_wlast : std_logic := '0';
signal sig_dre2sf_wready : std_logic := '0';
signal sig_sf2dre_wvalid : std_logic := '0';
signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2dre_wlast : std_logic := '0';
signal sig_rdc2dre_new_align : std_logic := '0';
signal sig_rdc2dre_use_autodest : std_logic := '0';
signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_rdc2dre_flush : std_logic := '0';
signal sig_sf2dre_new_align : std_logic := '0';
signal sig_sf2dre_use_autodest : std_logic := '0';
signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2dre_flush : std_logic := '0';
signal sig_dre_new_align : std_logic := '0';
signal sig_dre_use_autodest : std_logic := '0';
signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush : std_logic := '0';
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_sf_allow_addr_req : std_logic := '0';
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_addr_req_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_sf2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2sf_cmd_valid : std_logic := '0';
signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0');
signal sig_mstr2sf_drr : std_logic := '0';
signal sig_mstr2sf_eof : std_logic := '0';
signal sig_mstr2sf_calc_error : std_logic := '0';
signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_data2sf_cmd_cmplt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
signal mm2s_aruser_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug vector output
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc
mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc
-- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values
sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values
end generate GEN_CACHE2;
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_PCC
--
-- Description:
-- Predictive Command Calculator Block
--
------------------------------------------------------------
I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc
generic map (
C_IS_MM2S => IS_MM2S ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_BTT_USED => MM2S_BTT_USED ,
C_SUPPORT_INDET_BTT => NO_INDET_BTT ,
C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
calc_error => sig_calc2dm_calc_err ,
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_btt => sig_mstr2sf_btt ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_cmd_cmplt => open ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl
generic map (
C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => mm2s_arcache_int ,
addr2axi_auser => mm2s_aruser_int ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => sig_mm2s_allow_addr_req ,
addr_req_posted => sig_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => sig_rdc2dre_new_align ,
mm2s_dre_use_autodest => sig_rdc2dre_use_autodest ,
mm2s_dre_src_align => sig_rdc2dre_src_align ,
mm2s_dre_dest_align => sig_rdc2dre_dest_align ,
mm2s_dre_flush => sig_rdc2dre_flush ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => sig_rdc2sf_wvalid ,
mm2s_strm_wready => sig_sf2rdc_wready ,
mm2s_strm_wdata => sig_rdc2sf_wdata ,
mm2s_strm_wstrb => sig_rdc2sf_wstrb ,
mm2s_strm_wlast => sig_rdc2sf_wlast ,
-- MM2S Store and Forward Supplimental Control ----------
mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => sig_mstr2data_sequential ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => sig_mstr2data_dre_src_align ,
mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_SF
--
-- If Generate Description:
-- Include the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate
begin
-- Merge external address posting control with the
-- Store and Forward address posting control
sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and
mm2s_allow_addr_req;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
sig_dre_new_align <= sig_sf2dre_new_align ;
sig_dre_use_autodest <= sig_sf2dre_use_autodest ;
sig_dre_src_align <= sig_sf2dre_src_align ;
sig_dre_dest_align <= sig_sf2dre_dest_align ;
sig_dre_flush <= sig_sf2dre_flush ;
------------------------------------------------------------
-- Instance: I_RD_SF
--
-- Description:
-- Instance for the MM2S Store and Forward module with
-- downsizer support.
--
------------------------------------------------------------
I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf
generic map (
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
C_DRE_IS_USED => INCLUDE_DRE ,
C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset inputs -------------------------------
aclk => mm2s_aclk ,
reset => sig_mmap_rst ,
-- DataMover Read Side Address Pipelining Control Interface
ok_to_post_rd_addr => sig_sf_allow_addr_req ,
rd_addr_posted => sig_addr_req_posted ,
rd_xfer_cmplt => sig_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S Read Data Controller -----
sf2sin_tready => sig_sf2rdc_wready ,
sin2sf_tvalid => sig_rdc2sf_wvalid ,
sin2sf_tdata => sig_rdc2sf_wdata ,
sin2sf_tkeep => sig_rdc2sf_wstrb ,
sin2sf_tlast => sig_rdc2sf_wlast ,
-- RDC Store and Forward Supplimental Controls ----------
data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt ,
data2sf_dre_flush => sig_rdc2dre_flush ,
-- DRE Control Interface from the Command Calculator -----------------------------
dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready ,
mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid ,
mstr2dre_tag => sig_mstr2sf_tag ,
mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align ,
mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align ,
mstr2dre_drr => sig_mstr2sf_drr ,
mstr2dre_eof => sig_mstr2sf_eof ,
mstr2dre_calc_error => sig_mstr2sf_calc_error ,
mstr2dre_strt_offset => sig_mstr2sf_strt_offset ,
-- MM2S DRE Control -------------------------------------------------------------
sf2dre_new_align => sig_sf2dre_new_align ,
sf2dre_use_autodest => sig_sf2dre_use_autodest ,
sf2dre_src_align => sig_sf2dre_src_align ,
sf2dre_dest_align => sig_sf2dre_dest_align ,
sf2dre_flush => sig_sf2dre_flush ,
-- Stream Out ----------------------------------
sout2sf_tready => sig_dre2sf_wready ,
sf2sout_tvalid => sig_sf2dre_wvalid ,
sf2sout_tdata => sig_sf2dre_wdata ,
sf2sout_tkeep => sig_sf2dre_wstrb ,
sf2sout_tlast => sig_sf2dre_wlast
);
-- ------------------------------------------------------------
-- -- Instance: I_RD_SF
-- --
-- -- Description:
-- -- Instance for the MM2S Store and Forward module.
-- --
-- ------------------------------------------------------------
-- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf
-- generic map (
--
-- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
-- C_MAX_BURST_LEN => MM2S_BURST_SIZE ,
-- C_DRE_IS_USED => INCLUDE_DRE ,
-- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
--
-- -- Clock and Reset inputs -------------------------------
-- aclk => mm2s_aclk ,
-- reset => sig_mmap_rst ,
--
--
-- -- DataMover Read Side Address Pipelining Control Interface
-- ok_to_post_rd_addr => sig_sf_allow_addr_req ,
-- rd_addr_posted => sig_addr_req_posted ,
-- rd_xfer_cmplt => sig_rd_xfer_cmplt ,
--
--
--
-- -- Read Side Stream In from DataMover MM2S -----
-- sf2sin_tready => sig_sf2dre_wready ,
-- sin2sf_tvalid => sig_dre2sf_wvalid ,
-- sin2sf_tdata => sig_dre2sf_wdata ,
-- sin2sf_tkeep => sig_dre2sf_wstrb ,
-- sin2sf_tlast => sig_dre2sf_wlast ,
--
--
--
-- -- Stream Out ----------------------------------
-- sout2sf_tready => sig_skid2sf_wready ,
-- sf2sout_tvalid => sig_sf2skid_wvalid ,
-- sf2sout_tdata => sig_sf2skid_wdata ,
-- sf2sout_tkeep => sig_sf2skid_wstrb ,
-- sf2sout_tlast => sig_sf2skid_wlast
--
-- );
end generate GEN_INCLUDE_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_SF
--
-- If Generate Description:
-- Omit the MM2S Store and Forward function
--
--
------------------------------------------------------------
GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate
begin
-- Allow external address posting control
-- Ignore Store and Forward Control
sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ;
sig_sf_allow_addr_req <= '0' ;
-- Address Posting support outputs
mm2s_addr_req_posted <= sig_addr_req_posted ;
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ;
-- DRE Control Bus (Connect to the Read data Controller)
sig_dre_new_align <= sig_rdc2dre_new_align ;
sig_dre_use_autodest <= sig_rdc2dre_use_autodest ;
sig_dre_src_align <= sig_rdc2dre_src_align ;
sig_dre_dest_align <= sig_rdc2dre_dest_align ;
sig_dre_flush <= sig_rdc2dre_flush ;
-- Just pass stream signals through
sig_sf2rdc_wready <= sig_dre2sf_wready ;
sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ;
sig_sf2dre_wdata <= sig_rdc2sf_wdata ;
sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ;
sig_sf2dre_wlast <= sig_rdc2sf_wlast ;
-- Always enable the DRE Cmd bus for loading to keep from
-- stalling the PCC module
sig_sf2mstr_cmd_ready <= LOGIC_HIGH;
end generate GEN_NO_MM2S_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_MM2S_DRE
--
-- If Generate Description:
-- Include the MM2S DRE
--
--
------------------------------------------------------------
GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DRE64
--
-- Description:
-- Instance for the MM2S DRE whach can support widths of
-- 16 bits to 64 bits.
--
------------------------------------------------------------
I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre
generic map (
C_DWIDTH => MM2S_SDATA_WIDTH ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH
)
port map (
-- Control inputs
dre_clk => mm2s_aclk ,
dre_rst => sig_stream_rst ,
dre_new_align => sig_dre_new_align ,
dre_use_autodest => sig_dre_use_autodest ,
dre_src_align => sig_dre_src_align ,
dre_dest_align => sig_dre_dest_align ,
dre_flush => sig_dre_flush ,
-- Stream Inputs
dre_in_tstrb => sig_sf2dre_wstrb ,
dre_in_tdata => sig_sf2dre_wdata ,
dre_in_tlast => sig_sf2dre_wlast ,
dre_in_tvalid => sig_sf2dre_wvalid ,
dre_in_tready => sig_dre2sf_wready ,
-- Stream Outputs
dre_out_tstrb => sig_dre2skid_wstrb ,
dre_out_tdata => sig_dre2skid_wdata ,
dre_out_tlast => sig_dre2skid_wlast ,
dre_out_tvalid => sig_dre2skid_wvalid ,
dre_out_tready => sig_skid2dre_wready
);
end generate GEN_INCLUDE_MM2S_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_MM2S_DRE
--
-- If Generate Description:
-- Omit the MM2S DRE and housekeep the signals that it
-- needs to output.
--
------------------------------------------------------------
GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate
begin
-- Just pass stream signals through from the Store
-- and Forward module
sig_dre2sf_wready <= sig_skid2dre_wready ;
sig_dre2skid_wvalid <= sig_sf2dre_wvalid ;
sig_dre2skid_wdata <= sig_sf2dre_wdata ;
sig_dre2skid_wstrb <= sig_sf2dre_wstrb ;
sig_dre2skid_wlast <= sig_sf2dre_wlast ;
end generate GEN_NO_MM2S_DRE;
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => MM2S_SDATA_WIDTH
)
port map (
-- System Ports
aclk => mm2s_aclk ,
arst => sig_stream_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => sig_dre2skid_wvalid ,
s_ready => sig_skid2dre_wready ,
s_data => sig_dre2skid_wdata ,
s_strb => sig_dre2skid_wstrb ,
s_last => sig_dre2skid_wlast ,
-- Master Side (Stream Data Output
m_valid => mm2s_strm_wvalid ,
m_ready => mm2s_strm_wready ,
m_data => mm2s_strm_wdata ,
m_strb => mm2s_strm_wstrb ,
m_last => mm2s_strm_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate
begin
mm2s_strm_wvalid <= sig_dre2skid_wvalid;
sig_skid2dre_wready <= mm2s_strm_wready;
mm2s_strm_wdata <= sig_dre2skid_wdata;
mm2s_strm_wstrb <= sig_dre2skid_wstrb;
mm2s_strm_wlast <= sig_dre2skid_wlast;
end generate DISABLE_AXIS_SKID;
end implementation;
| bsd-2-clause | fa1884eb1b2cd3161cceb5d276882a1c | 0.438652 | 4.206433 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/conditional_expressions/rule_501_test_input.fixed_lower.vhd | 1 | 400 |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
| gpl-3.0 | 174c3045c96dce113502b3b4d3ff972a | 0.54 | 2.564103 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port_map/rule_002_test_input.fixed_lower.vhd | 1 | 585 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 8ed009a6d6e56a179825682b899af60f | 0.492308 | 2.683486 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_031_test_input.fixed_upper.vhd | 1 | 545 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : COMPONENT INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : COMPONENT INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 09796b8c82263e2755c262f22309dffb | 0.486239 | 2.809278 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/imports/Nexys4_PDM_RefProj/hp_rc.vhd | 1 | 3,374 | -------------------------------------------------------------------------------
--
-- COPYRIGHT (C) 2013, Digilent RO. All rights reserved
--
-------------------------------------------------------------------------------
-- FILE NAME : hp_rc.vhd
-- MODULE NAME : DC Component Remover (High-pass RC filter)
-- AUTHOR : Mihaita Nagy
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2013-06-20 Mihaita Nagy Created
-------------------------------------------------------------------------------
-- DESCRIPTION : Based on Xilinx's WP279 this module models a high-pass
-- first order RC filter.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_signed.all;
entity hp_rc is
port(
clk_i : in std_logic; -- 100 MHz
rst_i : in std_logic;
en_i : in std_logic; -- sampling frequency
data_i : in std_logic_vector(15 downto 0);
data_o : out std_logic_vector(15 downto 0)
);
end hp_rc;
architecture Behavioral of hp_rc is
------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------------
constant D : integer range 1 to 32 := 32; -- fc = ~120 Hz, rolls off 24 dB for 40 Hz and lower
constant SHIFT_POS : integer := integer(ceil(log2(real(D))));
--constant MAX_SHIFT_POS : integer := 12; --
constant SIZE : integer := SHIFT_POS+16;
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal int_sub : std_logic_vector(16 downto 0) := (others => '0');
--signal int_sub : std_logic_vector((28-SHIFT_POS) downto 0) := (others => '0');
signal int_mult : std_logic_vector(SIZE downto 0) := (others => '0');
signal int_temp : std_logic_vector(SIZE downto 0) := (others => '0');
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
-- Subtracting only the integer part and discard the fractional part
-- of int_temp. The subtractor:
int_sub <= (data_i(15) & data_i) - int_temp(SIZE downto (SIZE-16));
-- Multiply by the power of two => right shift with log2 of the power
-- of two. Sign extending:
int_mult(SIZE downto (SIZE-SHIFT_POS)+1) <= (others => int_sub(16));
-- Right shifting:
int_mult((SIZE-SHIFT_POS) downto 0) <= int_sub;
-- Final output:
data_o <= int_sub(15 downto 0);
-- Integral part
Integrate: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
int_temp <= (others => '0');
else
if en_i = '1' then
int_temp <= int_temp + int_mult;
end if;
end if;
end if;
end process Integrate;
end Behavioral;
| mit | 57d4cb7e6daa0cd797bd1f651636092d | 0.428571 | 4.565629 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/cic_compiler_v4_0_comp.vhd | 1 | 11,620 | `protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6864)
`protect data_block
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| mit | c8d601fbb0d512ecf7e3efe39eaab090 | 0.927539 | 1.873891 | false | false | false | false |
rjarzmik/mips_processor | DI/RegisterFile.vhd | 1 | 4,023 | -------------------------------------------------------------------------------
-- Title : Register File
-- Project :
-------------------------------------------------------------------------------
-- File : RegisterFile.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-12
-- Last update: 2017-01-03
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: MIPS Register File, 32 registers
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-12 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity RegisterFile is
generic (
DATA_WIDTH : positive := 32;
NB_REGISTERS : positive := 32; -- r0 to r31
NB_REGISTERS_SPECIAL : positive := 2 -- mflo and mfhi
);
port (
clk : in std_logic;
rst : in std_logic;
stall_req : in std_logic;
a_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
b_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
-- Writeback register
rwb_reg1_we : in std_logic;
rwb_reg1_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg1_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
rwb_reg2_we : in std_logic;
rwb_reg2_idx : in natural range 0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1;
rwb_reg2_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
-- Output read registers, set on clk rising edge
a : out std_logic_vector(DATA_WIDTH - 1 downto 0);
b : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity RegisterFile;
-------------------------------------------------------------------------------
architecture rtl of RegisterFile is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
type r_array is array (0 to NB_REGISTERS + NB_REGISTERS_SPECIAL - 1) of
std_logic_vector(DATA_WIDTH -1 downto 0);
signal registers : r_array := (
x"00000000", -- r0
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000",
x"00000000");
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
process(rst, clk, rwb_reg1_we, rwb_reg2_we)
begin
if rst = '1' then
a <= (others => 'X');
b <= (others => 'X');
elsif rising_edge(clk) then
if rwb_reg1_we = '1' then
registers(rwb_reg1_idx) <= rwb_reg1_data;
end if;
if rwb_reg2_we = '1' then
registers(rwb_reg2_idx) <= rwb_reg2_data;
end if;
if stall_req = '0' then
a <= registers(a_idx);
b <= registers(b_idx);
end if;
end if;
end process;
end architecture rtl;
-------------------------------------------------------------------------------
| gpl-3.0 | 7f5f25cf40b936d724995eecde606c24 | 0.425553 | 4.284345 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/sequential/rule_007_test_input.vhd | 1 | 282 |
architecture RTL of FIFO is
begin
process
begin
sig1 <= sig2;
sig2 <= sig3;
end process;
-- Violations below
process
begin
sig1 <= sig2; sig2 <= sig3; -- Comment 1
siga <= sigb; sigb <= sigc; sigc <= sigd;
end process;
end architecture RTL;
| gpl-3.0 | e6a0f6053dcea4445b1e972a54a5e063 | 0.599291 | 3.39759 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_proc_sys_reset_0/sim/daala_zynq_proc_sys_reset_0.vhd | 1 | 5,857 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY daala_zynq_proc_sys_reset_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END daala_zynq_proc_sys_reset_0;
ARCHITECTURE daala_zynq_proc_sys_reset_0_arch OF daala_zynq_proc_sys_reset_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF daala_zynq_proc_sys_reset_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END daala_zynq_proc_sys_reset_0_arch;
| bsd-2-clause | 72df4b2504065cd7fd9bcdaf177f0b00 | 0.707188 | 3.593252 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/transpose_single_rate.vhd | 2 | 148,289 | `protect begin_protected
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| mit | ab29fcb743d1e056588587cd09c40f86 | 0.954278 | 1.812182 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/rx-core/xapp1017/serdes_1_to_468_idelay_ddr.vhd | 1 | 21,977 | ------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_468_idelay_ddr.v
-- / / Date Last Modified: Mar 30, 2016
-- /___/ /\ Date Created: Mar 5, 2011
-- \ \ / \
-- \___\/\___\
--
--Device: 7 Series
--Purpose: 1 to 4 DDR data receiver.
-- Data formatting is set by the DATA_FORMAT parameter.
-- PER_CLOCK (default) format receives bits for 0, 1, 2 .. on the same sample edge
-- PER_CHANL format receives bits for 0, 4, 8 .. on the same sample edge
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_468_idelay_ddr is generic (
S : integer := 8 ; -- Set the serdes factor to 4, 6 or 8
D : integer := 8 ; -- Set the number of inputs
CLKIN_PERIOD : real := 2.000 ; -- clock period (ns) of input clock on clkin_p
REF_FREQ : real := 200.0 ; -- Parameter to set reference frequency used by idelay controller
HIGH_PERFORMANCE_MODE : string := "FALSE" ; -- Parameter to set HIGH_PERFORMANCE_MODE of input delays to reduce jitter
DATA_FORMAT : string := "PER_CLOCK") ; -- Used to determine method for mapping input parallel word to output serial words
port (
-- clkin_p : in std_logic ; -- Input from LVDS clock pin
-- clkin_n : in std_logic ; -- Input from LVDS clock pin
datain_p : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
datain_n : in std_logic_vector(D-1 downto 0) ; -- Input from LVDS receiver pin
enable_phase_detector : in std_logic ; -- Enables the phase detector logic when high
enable_monitor : in std_logic ; -- Enables the monitor logic when high, note time-shared with phase detector function
reset : in std_logic ; -- Reset line
bitslip : in std_logic ; -- bitslip
idelay_rdy : in std_logic ; -- input delays are ready
rxclk : in std_logic ; -- Global/BUFIO rx clock network
system_clk : in std_logic ; -- Global/Regional clock output
rx_lckd : out std_logic ; --
rx_data : out std_logic_vector((S*D)-1 downto 0) ; -- Output data
bit_rate_value : in std_logic_vector(15 downto 0) ; -- Bit rate in Mbps, eg X"0585
dcd_correct : in std_logic ; -- '0' = square, '1' = assume 10% DCD
bit_time_value : out std_logic_vector(4 downto 0) ; -- Calculated bit time value for slave devices
debug : out std_logic_vector(10*D+18 downto 0) ; -- Debug bus
eye_info : out std_logic_vector(32*D-1 downto 0) ; -- Eye info
m_delay_1hot : out std_logic_vector(32*D-1 downto 0) ; -- Master delay control value as a one-hot vector
clock_sweep : out std_logic_vector(31 downto 0)) ; -- clock Eye info
end serdes_1_to_468_idelay_ddr ;
architecture arch_serdes_1_to_468_idelay_ddr of serdes_1_to_468_idelay_ddr is
component delay_controller_wrap is generic (
S : integer := 4) ; -- Set the number of bits
port (
m_datain : in std_logic_vector(S-1 downto 0) ; -- Inputs from master serdes
s_datain : in std_logic_vector(S-1 downto 0) ; -- Inputs from slave serdes
enable_phase_detector : in std_logic ; -- Enables the phase detector logic when high
enable_monitor : in std_logic ; -- Enables the eye monitoring logic when high
reset : in std_logic ; -- Reset line synchronous to clk
clk : in std_logic ; -- Global/Regional clock
c_delay_in : in std_logic_vector(4 downto 0) ; -- delay value found on clock line
m_delay_out : out std_logic_vector(4 downto 0) ; -- Master delay control value
s_delay_out : out std_logic_vector(4 downto 0) ; -- Master delay control value
data_out : out std_logic_vector(S-1 downto 0) ; -- Output data
results : out std_logic_vector(31 downto 0) ; -- eye monitor result data
m_delay_1hot : out std_logic_vector(31 downto 0) ; -- Master delay control value as a one-hot vector
debug : out std_logic_vector(1 downto 0) ; -- debug data
del_mech : in std_logic ; -- changes delay mechanism slightly at higher bit rates
bt_val : in std_logic_vector(4 downto 0)) ; -- Calculated bit time value for slave devices
end component ;
signal m_delay_val_in : std_logic_vector(5*D-1 downto 0) ;
signal s_delay_val_in : std_logic_vector(5*D-1 downto 0) ;
signal m_delay_val_out : std_logic_vector(5*D-1 downto 0) ;
signal s_delay_val_out : std_logic_vector(5*D-1 downto 0) ;
signal cdataout : std_logic_vector(3 downto 0) ;
signal bsstate : std_logic_vector(1 downto 0) ;
signal bcount : std_logic_vector(3 downto 0) ;
signal clk_iserdes_data_d : std_logic_vector(3 downto 0) ;
signal enable : std_logic ;
signal flag1 : std_logic ;
signal state2_count : std_logic_vector(4 downto 0) := "00000" ;
signal rx_lckd_int : std_logic ;
signal rx_lckd_intd4 : std_logic ;
signal not_rx_lckd_intd4 : std_logic ;
signal rx_data_in_p : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_n : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_m : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_s : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_md : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_sd : std_logic_vector(D-1 downto 0) ;
signal mdataout : std_logic_vector(S*D-1 downto 0) ;
signal mdataoutd : std_logic_vector(S*D-1 downto 0) ;
signal sdataout : std_logic_vector(S*D-1 downto 0) ;
signal s_serdes : std_logic_vector(8*D-1 downto 0) ;
signal m_serdes : std_logic_vector(8*D-1 downto 0) ;
signal system_clk_int : std_logic ;
signal data_different : std_logic ;
signal bt_val : std_logic_vector(4 downto 0) ;
signal su_locked : std_logic ;
signal m_count : std_logic_vector(5 downto 0) ;
signal c_sweep_delay : std_logic_vector(4 downto 0) := "00000" ;
signal c_found_val : std_logic_vector(4 downto 0) ;
signal c_found_offset : std_logic_vector(4 downto 0) ;
signal temp_shift : std_logic_vector(31 downto 0) ;
signal rx_clk_in_p : std_logic ;
signal rx_clk_in_pc : std_logic ;
signal rx_clk_in_pd : std_logic ;
signal rxclk_int : std_logic ;
signal rst_iserdes : std_logic ;
signal not_rxclk : std_logic ;
signal clock_sweep_int : std_logic_vector(31 downto 0) ;
signal zflag : std_logic ;
signal del_mech : std_logic ;
signal bt_val_d2 : std_logic_vector(4 downto 0) ;
signal del_debug : std_logic_vector(2*D-1 downto 0) ;
signal initial_delay : std_logic_vector(4 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input data bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
attribute IODELAY_GROUP : STRING;
begin
debug <= "0000000" & del_debug(1 downto 0) & cdataout & s_delay_val_out & m_delay_val_out & bitslip & initial_delay ;
rx_lckd <= not reset;-- not not_rx_lckd_intd4 and su_locked ;
bit_time_value <= bt_val ;
system_clk_int <= system_clk ; -- theim: use external
not_rxclk <= not rxclk;
clock_sweep <= clock_sweep_int ;
rxclk_int <= rxclk ; -- theim: use external;
bt_val_d2 <= '0' & bt_val(4 downto 1) ;
--cdataout <= m_serdes(3 downto 0); -- theim: hardcoded
loop11a : if REF_FREQ <= 210.0 generate -- Generate tap number to be used for input bit rate (200 MHz ref clock)
bt_val <= "00111" when bit_rate_value > X"1984" else
"01000" when bit_rate_value > X"1717" else
"01001" when bit_rate_value > X"1514" else
"01010" when bit_rate_value > X"1353" else
"01011" when bit_rate_value > X"1224" else
"01100" when bit_rate_value > X"1117" else
"01101" when bit_rate_value > X"1027" else
"01110" when bit_rate_value > X"0951" else
"01111" when bit_rate_value > X"0885" else
"10000" when bit_rate_value > X"0828" else
"10001" when bit_rate_value > X"0778" else
"10010" when bit_rate_value > X"0733" else
"10011" when bit_rate_value > X"0694" else
"10100" when bit_rate_value > X"0658" else
"10101" when bit_rate_value > X"0626" else
"10110" when bit_rate_value > X"0597" else
"10111" when bit_rate_value > X"0570" else
"11000" when bit_rate_value > X"0546" else
"11001" when bit_rate_value > X"0524" else
"11010" when bit_rate_value > X"0503" else
"11011" when bit_rate_value > X"0484" else
"11100" when bit_rate_value > X"0466" else
"11101" when bit_rate_value > X"0450" else
"11110" when bit_rate_value > X"0435" else
"11111" ; -- min bit rate 420 Mbps
del_mech <= '1' when bt_val < "10110" else '0' ; -- adjust delay mechanism when tap values are low enough
end generate ;
loop11b : if REF_FREQ > 210.0 generate -- Generate tap number to be used for input bit rate (300 MHz ref clock)
bt_val <= "01010" when (dcd_correct = '0' and bit_rate_value > X"2030") or (dcd_correct = '1' and bit_rate_value > X"1845")else
"01011" when (dcd_correct = '0' and bit_rate_value > X"1836") or (dcd_correct = '1' and bit_rate_value > X"1669")else
"01100" when (dcd_correct = '0' and bit_rate_value > X"1675") or (dcd_correct = '1' and bit_rate_value > X"1523")else
"01101" when (dcd_correct = '0' and bit_rate_value > X"1541") or (dcd_correct = '1' and bit_rate_value > X"1401")else
"01110" when (dcd_correct = '0' and bit_rate_value > X"1426") or (dcd_correct = '1' and bit_rate_value > X"1297")else
"01111" when (dcd_correct = '0' and bit_rate_value > X"1328") or (dcd_correct = '1' and bit_rate_value > X"1207")else
"10000" when (dcd_correct = '0' and bit_rate_value > X"1242") or (dcd_correct = '1' and bit_rate_value > X"1129")else
"10001" when (dcd_correct = '0' and bit_rate_value > X"1167") or (dcd_correct = '1' and bit_rate_value > X"1061")else
"10010" when (dcd_correct = '0' and bit_rate_value > X"1100") or (dcd_correct = '1' and bit_rate_value > X"0999")else
"10011" when (dcd_correct = '0' and bit_rate_value > X"1040") or (dcd_correct = '1' and bit_rate_value > X"0946")else
"10100" when (dcd_correct = '0' and bit_rate_value > X"0987") or (dcd_correct = '1' and bit_rate_value > X"0897")else
"10101" when (dcd_correct = '0' and bit_rate_value > X"0939") or (dcd_correct = '1' and bit_rate_value > X"0853")else
"10110" when (dcd_correct = '0' and bit_rate_value > X"0895") or (dcd_correct = '1' and bit_rate_value > X"0814")else
"10111" when (dcd_correct = '0' and bit_rate_value > X"0855") or (dcd_correct = '1' and bit_rate_value > X"0777")else
"11000" when (dcd_correct = '0' and bit_rate_value > X"0819") or (dcd_correct = '1' and bit_rate_value > X"0744")else
"11001" when (dcd_correct = '0' and bit_rate_value > X"0785") or (dcd_correct = '1' and bit_rate_value > X"0714")else
"11010" when (dcd_correct = '0' and bit_rate_value > X"0754") or (dcd_correct = '1' and bit_rate_value > X"0686")else
"11011" when (dcd_correct = '0' and bit_rate_value > X"0726") or (dcd_correct = '1' and bit_rate_value > X"0660")else
"11100" when (dcd_correct = '0' and bit_rate_value > X"0700") or (dcd_correct = '1' and bit_rate_value > X"0636")else
"11101" when (dcd_correct = '0' and bit_rate_value > X"0675") or (dcd_correct = '1' and bit_rate_value > X"0614")else
"11110" when (dcd_correct = '0' and bit_rate_value > X"0652") or (dcd_correct = '1' and bit_rate_value > X"0593")else
"11111" ; -- min bit rate 631 Mbps
del_mech <= '1' when bt_val < "10110" else '0' ; -- adjust delay mechanism when tap values are low enough
end generate ;
process (system_clk_int) begin -- sweep data
if system_clk_int'event and system_clk_int = '1' then
if su_locked = '0' then
c_sweep_delay <= "00000" ;
temp_shift <= (0 => '1', others => '0') ;
clock_sweep_int <= (others => '0') ;
zflag <= '0' ;
not_rx_lckd_intd4 <= '1' ;
rx_lckd_intd4 <= '0' ;
initial_delay <= "00000" ;
else
not_rx_lckd_intd4 <= not rx_lckd_intd4 ;
if state2_count = "11111" then
if c_sweep_delay /= bt_val then
if zflag = '0' then
c_sweep_delay <= c_sweep_delay + 1 ;
temp_shift <= temp_shift(30 downto 0) & temp_shift(31) ;
else
zflag <= '0' ;
end if ;
else
c_sweep_delay <= "00000" ;
zflag <= '1' ; -- need to check tap 0 twice bacause of wraparound
temp_shift <= (0 => '1', others => '0') ;
end if ;
if zflag = '0' then
if data_different = '1' then
clock_sweep_int <= clock_sweep_int and not temp_shift ;
if initial_delay = "00000" then
rx_lckd_intd4 <= '1' ;
if c_sweep_delay < '0' & bt_val(4 downto 1) then -- choose the lowest delay value to minimise jitter
initial_delay <= c_sweep_delay + ('0' & bt_val(4 downto 1)) ;
else
initial_delay <= c_sweep_delay - ('0' & bt_val(4 downto 1)) ;
end if ;
end if ;
else
clock_sweep_int <= clock_sweep_int or temp_shift ;
end if ;
end if ;
end if ;
end if ;
end if ;
end process ;
process (system_clk_int, reset, idelay_rdy) begin
if reset = '1' or idelay_rdy = '0' then
su_locked <= '0' ;
m_count <= "000000" ;
rst_iserdes <= '1' ;
elsif system_clk_int'event and system_clk_int = '1' then -- startup delay
if m_count = "111100" then
rst_iserdes <= '0' ;
m_count <= m_count + 1 ;
elsif m_count = "111111" then
su_locked <= '1' ;
else
m_count <= m_count + 1 ;
end if ;
end if ;
end process ;
process (system_clk_int) begin -- sweep data
if system_clk_int'event and system_clk_int = '1' then
if su_locked = '0' then
state2_count <= "00000" ;
else
state2_count <= state2_count + 1 ;
if state2_count = "00000" then
clk_iserdes_data_d <= cdataout ;
elsif state2_count <= "01000" then
data_different <= '0' ;
elsif cdataout /= clk_iserdes_data_d then
data_different <= '1' ;
end if ;
end if ;
end if ;
end process ;
loop3 : for i in 0 to D-1 generate
dc_inst : delay_controller_wrap generic map (
S => S)
port map (
m_datain => mdataout(S*i+S-1 downto S*i),
s_datain => sdataout(S*i+S-1 downto S*i),
enable_phase_detector => enable_phase_detector,
enable_monitor => enable_monitor,
--reset => not_rx_lckd_intd4,
reset => reset,
clk => system_clk_int,
--c_delay_in => initial_delay,
c_delay_in => "00000",
m_delay_out => m_delay_val_in(5*i+4 downto 5*i),
s_delay_out => s_delay_val_in(5*i+4 downto 5*i),
data_out => mdataoutd(S*i+S-1 downto S*i),
bt_val => bt_val,
del_mech => del_mech,
debug => del_debug(i*2+1 downto i*2),
m_delay_1hot => m_delay_1hot(32*i+31 downto 32*i),
results => eye_info(32*i+31 downto 32*i)) ;
end generate ;
-- Data bit Receivers
loop0 : for i in 0 to D-1 generate
attribute IODELAY_GROUP of idelay_m : label is "aurora";
attribute IODELAY_GROUP of idelay_s : label is "aurora";
begin
loop1 : for j in 0 to S-1 generate -- Assign data bits to correct serdes according to required format
loop1a : if DATA_FORMAT = "PER_CLOCK" generate
rx_data(D*j+i) <= mdataoutd(S*i+j) ;
end generate ;
loop1b : if DATA_FORMAT = "PER_CHANL" generate
rx_data(S*i+j) <= mdataoutd(S*i+j) ;
end generate ;
end generate ;
--data_in : IBUFDS_DIFF_OUT generic map(
-- IBUF_LOW_PWR => FALSE)
--port map (
-- I => datain_p(i),
-- IB => datain_n(i),
-- O => rx_data_in_p(i),
-- OB => rx_data_in_n(i));
rx_data_in_p <= datain_p;
rx_data_in_n <= datain_n;
rx_data_in_m(i) <= rx_data_in_p(i) xor RX_SWAP_MASK(i) ;
rx_data_in_s(i) <= rx_data_in_n(i) xor RX_SWAP_MASK(i) ;
idelay_m : IDELAYE2 generic map(
REFCLK_FREQUENCY => REF_FREQ,
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_VALUE => 0,
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VAR_LOAD")
port map(
DATAOUT => rx_data_in_md(i),
C => system_clk_int,
CE => '0',
INC => '0',
DATAIN => '0',
IDATAIN => rx_data_in_m(i),
LD => '1',
LDPIPEEN => '0',
REGRST => '0',
CINVCTRL => '0',
CNTVALUEIN => m_delay_val_in(5*i+4 downto 5*i),
CNTVALUEOUT => m_delay_val_out(5*i+4 downto 5*i));
iserdes_m : ISERDESE2 generic map(
DATA_WIDTH => S,
DATA_RATE => "DDR",
SERDES_MODE => "MASTER",
IOBDELAY => "IFD",
DYN_CLK_INV_EN => "FALSE",
INTERFACE_TYPE => "NETWORKING")
port map (
D => '0',
DDLY => rx_data_in_md(i),
CE1 => '1',
CE2 => '1',
CLK => rxclk_int,
CLKB => not_rxclk,
RST => rst_iserdes,
CLKDIV => system_clk_int,
CLKDIVP => '0',
OCLK => '0',
OCLKB => '0',
DYNCLKSEL => '0',
DYNCLKDIVSEL => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
BITSLIP => bitslip,
O => open,
Q8 => m_serdes(8*i+0),
Q7 => m_serdes(8*i+1),
Q6 => m_serdes(8*i+2),
Q5 => m_serdes(8*i+3),
Q4 => m_serdes(8*i+4),
Q3 => m_serdes(8*i+5),
Q2 => m_serdes(8*i+6),
Q1 => m_serdes(8*i+7),
OFB => '0',
SHIFTOUT1 => open,
SHIFTOUT2 => open);
idelay_s : IDELAYE2 generic map(
REFCLK_FREQUENCY => REF_FREQ,
HIGH_PERFORMANCE_MODE => HIGH_PERFORMANCE_MODE,
IDELAY_VALUE => 0,
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VAR_LOAD")
port map(
DATAOUT => rx_data_in_sd(i),
C => system_clk_int,
CE => '0',
INC => '0',
DATAIN => '0',
IDATAIN => rx_data_in_s(i),
LD => '1',
LDPIPEEN => '0',
REGRST => '0',
CINVCTRL => '0',
CNTVALUEIN => s_delay_val_in(5*i+4 downto 5*i),
CNTVALUEOUT => s_delay_val_out(5*i+4 downto 5*i));
iserdes_s : ISERDESE2 generic map(
DATA_WIDTH => S,
DATA_RATE => "DDR",
-- SERDES_MODE => "MASTER",
IOBDELAY => "IFD",
DYN_CLK_INV_EN => "FALSE",
INTERFACE_TYPE => "NETWORKING")
port map (
D => '0',
DDLY => rx_data_in_sd(i),
CE1 => '1',
CE2 => '1',
CLK => rxclk_int,
CLKB => not_rxclk,
RST => rst_iserdes,
CLKDIV => system_clk_int,
CLKDIVP => '0',
OCLK => '0',
OCLKB => '0',
DYNCLKSEL => '0',
DYNCLKDIVSEL => '0',
SHIFTIN1 => '0',
SHIFTIN2 => '0',
BITSLIP => bitslip,
O => open,
Q8 => s_serdes(8*i+0),
Q7 => s_serdes(8*i+1),
Q6 => s_serdes(8*i+2),
Q5 => s_serdes(8*i+3),
Q4 => s_serdes(8*i+4),
Q3 => s_serdes(8*i+5),
Q2 => s_serdes(8*i+6),
Q1 => s_serdes(8*i+7),
OFB => '0',
SHIFTOUT1 => open,
SHIFTOUT2 => open);
-- sort out necessary bits from iserdes
loop0a : if S = 4 generate
mdataout(4*i+3 downto 4*i) <= m_serdes(8*i+7 downto 8*i+4) ;
sdataout(4*i+3 downto 4*i) <= not s_serdes(8*i+7 downto 8*i+4) ;
end generate ;
loop0b : if S = 6 generate
mdataout(6*i+5 downto 6*i) <= m_serdes(8*i+7 downto 8*i+2) ;
sdataout(6*i+5 downto 6*i) <= not s_serdes(8*i+7 downto 8*i+2) ;
end generate ;
loop0c : if S = 8 generate
mdataout(8*i+7 downto 8*i) <= m_serdes(8*i+7 downto 8*i) ;
sdataout(8*i+7 downto 8*i) <= not s_serdes(8*i+7 downto 8*i) ;
end generate ;
end generate ;
end arch_serdes_1_to_468_idelay_ddr ;
| gpl-3.0 | be4cd7c74f3635b0ba58c212bc0462a5 | 0.601356 | 2.793923 | false | false | false | false |
okaxaki/vm2413 | EnvelopeMemory.vhd | 2 | 1,128 | --
-- EnvelopeMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity EnvelopeMemory is port (
clk : in std_logic;
reset : in std_logic;
waddr : in SLOT_TYPE;
wr : in std_logic;
wdata : in EGDATA_TYPE;
raddr : in SLOT_TYPE;
rdata : out EGDATA_TYPE
);
end EnvelopeMemory;
architecture RTL of EnvelopeMemory is
type EGDATA_ARRAY is array (0 to MAXSLOT-1) of EGDATA_VECTOR_TYPE;
signal egdata_set : EGDATA_ARRAY;
begin
process (clk, reset)
variable init_slot : integer range 0 to SLOT_TYPE'high+1;
begin
if reset = '1' then
init_slot := 0;
elsif clk'event and clk = '1' then
if init_slot /= SLOT_TYPE'high + 1 then
egdata_set(init_slot) <= (others=>'1');
init_slot := init_slot + 1;
elsif wr = '1' then
egdata_set(waddr) <= CONV_EGDATA_VECTOR(wdata);
end if;
rdata <= CONV_EGDATA(egdata_set(raddr));
end if;
end process;
end RTL;
| mit | 6611d6691e0f2e9dd074a4d15b758924 | 0.562057 | 3.317647 | false | false | false | false |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/TestBench/microprocessor_TB.vhd | 1 | 1,025 | library ieee;
use ieee.NUMERIC_STD.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity microprocessor_tb is
end microprocessor_tb;
architecture TB_ARCHITECTURE of microprocessor_tb is
component MicroProcessor
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
stop : out STD_LOGIC);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC := '0';
signal start : STD_LOGIC := '0';
signal stop : STD_LOGIC := '0';
constant CLK_PERIOD : time := 10 ns;
begin
UUT : microprocessor
port map(
clk => clk,
rst => rst,
start => start,
stop => stop
);
CLK_P : process
begin
clk <= '0';
wait for CLK_PERIOD / 2;
clk <= '1';
wait for CLK_PERIOD / 2;
end process;
MAIN_P : process
begin
rst <= '1';
wait for CLK_PERIOD;
rst <= '0';
start <= '1';
wait for 100 * CLK_PERIOD;
wait;
end process;
end TB_ARCHITECTURE; | mit | 1406431a3b1c77534185fbf976b5d166 | 0.595122 | 2.89548 | false | false | false | false |
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`protect end_protected
| mit | 10419f2b69d2f39155b09a91b2018f37 | 0.947943 | 1.833566 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generic_map/rule_002_test_input.fixed_upper.vhd | 1 | 585 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
PORT_1(3 downto 0) => w_port_1,
PORT_2 => w_port_2,
PORT_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
end architecture ARCH;
| gpl-3.0 | d82f325f07fa3f383aeef94b2fa56117 | 0.492308 | 2.683486 | false | false | false | false |
okaxaki/vm2413 | PhaseMemory.vhd | 2 | 1,057 | --
-- PhaseMemory.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity PhaseMemory is
port (
clk : in std_logic;
reset : in std_logic;
slot : in SLOT_TYPE;
memwr : in std_logic;
memout : out PHASE_TYPE;
memin : in PHASE_TYPE
);
end PhaseMemory;
architecture RTL of PhaseMemory is
type PHASE_ARRAY_TYPE is array (0 to MAXSLOT-1) of PHASE_TYPE;
signal phase_array : PHASE_ARRAY_TYPE;
begin
process (clk, reset)
variable init_slot : integer range 0 to MAXSLOT;
begin
if reset = '1' then
init_slot := 0;
elsif clk'event and clk = '1' then
if init_slot /= MAXSLOT then
phase_array(init_slot) <= (others=>'0');
init_slot := init_slot + 1;
elsif memwr = '1' then
phase_array(slot) <= memin;
end if;
memout <= phase_array(slot);
end if;
end process;
end RTL; | mit | d320dc131ad091b5c9059f40d62c9fe0 | 0.543992 | 3.523333 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/aggregate/classification_test_input.vhd | 1 | 493 |
architecture rtl of fifo is begin
s_foo <= (
item => 12,
another_item => 34
);
proc_label : process is
begin
s_foo <= (
item => 12,
another_item => 34
);
end process proc_label;
s_foo <= ( item1 => 12,
item2 => f(a, b ,c),
item3 => 36,
item4 => (
itemA => 3,
itemB => 4
)
);
end architecture rtl;
| gpl-3.0 | 38170f2d607a249ea28acae7e445aa06 | 0.361055 | 4.142857 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd | 1 | 89,724 | -------------------------------------------------------------------------------
-- axi_datamover_s2mm_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_s2mm_dre.vhd
-- |
-- |-- axi_datamover_dre_mux8_1_x_n.vhd
-- |-- axi_datamover_dre_mux4_1_x_n.vhd
-- |-- axi_datamover_dre_mux2_1_x_n.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
-- DET 9/1/2011 Initial
-- ~~~~~~
-- - Per a Lint warning, added a range to the varables lvar_loop_count and
-- lvar_last_strb_hole_position.
-- ^^^^^^
--
-- PVK 9/16/2011
-- ~~~~~~~
-- - Removed else clause in some of the clocked process. This was reported
-- as synthesis warning in modelsim.
-- ^^^^^^^
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the width of the alignment control inputs
-- Should be log2(C_DWIDTH)
);
port (
-- Clock and Reset Input ----------------------------------------------
--
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------------------------------------
-- Alignment Control (Independent from Stream Input timing) ----------
--
dre_align_ready : Out std_logic; --
dre_align_valid : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Flush Control (Aligned to input Stream timing) --------------------
--
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Stream Input Channel ----------------------------------------------
--
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Stream Output Channel ---------------------------------------------
--
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_s2mm_dre;
architecture implementation of axi_datamover_s2mm_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
Signal sig_cntl_accept : std_logic := '0';
Signal sig_dre_halted : std_logic := '0';
begin --(architecture implementation)
-- Misc port assignments
dre_align_ready <= sig_dre_halted or
sig_flush_db2_complete ;
dre_in_tready <= sig_input_accept ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
-- Internal logic
sig_cntl_accept <= dre_align_valid and
(sig_dre_halted or
sig_flush_db2_complete);
sig_pipeline_halt <= sig_dre_halted or
(sig_dre_tvalid_i and
not(dre_out_tready));
sig_output_xfer <= sig_dre_tvalid_i and
dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt);
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
not(sig_pipeline_halt) and
not(sig_input_flush_stall);
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or
sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
------------------------------------------------------------------------------------
-- DRE Halted logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_HALTED_FLOP
--
-- Process Description:
-- Implements a flop for the Halted state flag. All DRE
-- operation is halted until a new alignment control is
-- loaded. The DRE automatically goes into halted state
-- at reset and at completion of a flush operation.
--
-------------------------------------------------------------
IMP_DRE_HALTED_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
(sig_flush_db2_complete = '1' and
dre_align_valid = '0'))then
sig_dre_halted <= '1'; -- default to halted state
elsif (sig_cntl_accept = '1') then
sig_dre_halted <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_DRE_HALTED_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Input Register for the flush command
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
Signal s_case_i_64 : Integer range 0 to 7 := 0;
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
Signal s_case_i_32 : Integer range 0 to 3 := 0;
signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
Signal s_case_i_16 : Integer range 0 to 1 := 0;
signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic := '0';
Signal sig_shift_case_reg : std_logic := '0';
Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| bsd-2-clause | 9d0e3329381042cb3ed9e2ab855b55f5 | 0.367962 | 4.619234 | false | false | false | false |
Yarr/Yarr-fw | ip-cores/spartan6/fifo_32x512.vhd | 2 | 7,687 | --------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- Generated from component ID: xilinx.com:ip:fifo_generator:6.2
-- You must compile the wrapper file fifo_32x512.vhd when simulating
-- the core, fifo_32x512. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_32x512 IS
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(31 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
prog_full_thresh_assert: in std_logic_vector(9 downto 0);
prog_full_thresh_negate: in std_logic_vector(9 downto 0);
dout: out std_logic_vector(31 downto 0);
full: out std_logic;
empty: out std_logic;
valid: out std_logic;
prog_full: out std_logic);
END fifo_32x512;
ARCHITECTURE fifo_32x512_a OF fifo_32x512 IS
-- synthesis translate_off
component wrapped_fifo_32x512
port (
rst: in std_logic;
wr_clk: in std_logic;
rd_clk: in std_logic;
din: in std_logic_vector(31 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
prog_full_thresh_assert: in std_logic_vector(9 downto 0);
prog_full_thresh_negate: in std_logic_vector(9 downto 0);
dout: out std_logic_vector(31 downto 0);
full: out std_logic;
empty: out std_logic;
valid: out std_logic;
prog_full: out std_logic);
end component;
-- Configuration specification
for all : wrapped_fifo_32x512 use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 32,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 32,
c_msgon_val => 1,
c_rd_depth => 1024,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 10,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 10,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 10,
c_enable_rlocs => 0,
c_wr_pntr_width => 10,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 10,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 1020,
c_wr_depth => 1024,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 1021,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "1kx36",
c_count_type => 0,
c_prog_full_type => 4,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_32x512
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
dout => dout,
full => full,
empty => empty,
valid => valid,
prog_full => prog_full);
-- synthesis translate_on
END fifo_32x512_a;
| gpl-3.0 | 2b200318440d0d8f405919c23ec9b0b0 | 0.546767 | 3.695673 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/element_association/rule_100_test_input.vhd | 1 | 343 |
architecture rtl of fifo is
begin
a <= (others => (others => '0'));
process begin
a <= (others => (others => '0'));
end process;
end architecture;
architecture rtl of fifo is
begin
a <= (others=> (others => '0'));
process begin
a <= (others => (others=> '0'));
end process;
end architecture;
| gpl-3.0 | a3f55692d38f8cf2d7bfadcee511fed6 | 0.542274 | 3.648936 | false | false | false | false |
okaxaki/vm2413 | Controller.vhd | 2 | 14,628 | --
-- Controller.vhd
-- The core controller module of VM2413
--
-- [Description]
--
-- The Controller is the beginning module of the OPLL slot calculation.
-- It manages register accesses from I/O and sends proper voice parameters
-- to the succeding PhaseGenerator and EnvelopeGenerator modules.
-- The one cycle of the Controller consists of 4 stages as follows.
--
-- 1st stage:
-- * Prepare to read the register value for the current slot from RegisterMemory.
-- * Prepare to read the voice parameter for the current slot from VoiceMemory.
-- * Prepare to read the user-voice data from VoiceMemory.
--
-- 2nd stage:
-- * Wait for RegisterMemory and VoiceMemory
--
-- 3rd clock stage:
-- * Update register value if wr='1' and addr points the current OPLL channel.
-- * Update voice parameter if wr='1' and addr points the voice parameter area.
-- * Write register value to RegisterMemory.
-- * Write voice parameter to VoiceMemory.
--
-- 4th stage:
-- * Send voice and register parameters to PhaseGenerator and EnvelopeGenerator.
-- * Increment the number of the current slot.
--
-- Each stage is completed in one clock. Thus the Controller traverses all 18 opll
-- slots in 72 clocks.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity Controller is port (
clk : in std_logic;
reset : in std_logic;
clkena : in std_logic;
slot : in SLOT_TYPE;
stage : in STAGE_TYPE;
wr : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : in std_logic_vector(7 downto 0);
-- Output Parameters for PhaseGenerator and EnvelopeGenerator
am : out AM_TYPE;
pm : out PM_TYPE;
wf : out WF_TYPE;
ml : out ML_TYPE;
tl : out DB_TYPE;
fb : out FB_TYPE;
ar : out AR_TYPE;
dr : out DR_TYPE;
sl : out SL_TYPE;
rr : out RR_TYPE;
blk : out BLK_TYPE;
fnum : out FNUM_TYPE;
rks : out RKS_TYPE;
key : out std_logic;
rhythm : out std_logic
-- slot_out : out SLOT_ID
);
end Controller;
architecture RTL of Controller is
-- The array which caches instrument number of each channel.
type INST_ARRAY is array (CH_TYPE'range) of integer range 0 to 15;
signal inst_cache : INST_ARRAY;
type KL_ARRAY is array (0 to 15) of std_logic_vector(5 downto 0);
constant kl_table : KL_ARRAY :=
( "000000", "011000", "100000", "100101",
"101000", "101011", "101101", "101111",
"110000", "110010", "110011", "110100",
"110101", "110110", "110111", "111000" ); -- 0.75dB/Step, 6dB/OCT
component RegisterMemory port (
clk : in std_logic;
reset : in std_logic;
addr : in CH_TYPE;
wr : in std_logic;
idata : in REGS_TYPE;
odata : out REGS_TYPE );
end component;
component VoiceMemory port (
clk : in std_logic;
reset : in std_logic;
idata : in VOICE_TYPE;
wr : in std_logic;
rwaddr : in VOICE_ID_TYPE;
roaddr : in VOICE_ID_TYPE;
odata : out VOICE_TYPE;
rodata : out VOICE_TYPE );
end component;
-- Signals for the READ-ONLY access ports of VoiceMemory module.
signal slot_voice_addr : VOICE_ID_TYPE;
signal slot_voice_data : VOICE_TYPE;
-- Signals for the READ-WRITE access ports of VoiceMemory module.
signal user_voice_wr : std_logic;
signal user_voice_addr : VOICE_ID_TYPE;
signal user_voice_rdata : VOICE_TYPE;
signal user_voice_wdata : VOICE_TYPE;
signal extra_mode : std_logic;
-- Signals for the RegisterMemory module.
signal regs_wr : std_logic;
signal regs_addr : CH_TYPE;
signal regs_rdata : REGS_TYPE;
signal regs_wdata : REGS_TYPE;
begin -- RTL
RMEM : RegisterMemory port map (
clk, reset, regs_addr, regs_wr, regs_wdata, regs_rdata
);
VMEM : VoiceMemory port map (
clk, reset, user_voice_wdata, user_voice_wr, user_voice_addr, slot_voice_addr,
user_voice_rdata, slot_voice_data );
process (clk, reset)
variable rflag : std_logic_vector(7 downto 0);
variable kflag : std_logic;
variable tll : std_logic_vector(DB_TYPE'high+1 downto 0);
variable kll : std_logic_vector(DB_TYPE'high+1 downto 0);
variable regs_tmp : REGS_TYPE;
variable user_voice_tmp : VOICE_TYPE;
variable fb_buf : FB_TYPE;
variable wf_buf : WF_TYPE;
variable extra_mode : std_logic;
variable vindex : VOICE_ID_TYPE;
begin -- process
if(reset = '1') then
key <= '0';
rhythm <= '0';
tll := (others=>'0');
kll := (others=>'0');
kflag := '0';
rflag := (others=>'0');
user_voice_wr <= '0';
user_voice_addr <= 0;
slot_voice_addr <= 0;
regs_addr <= 0;
regs_wr <='0';
ar <= (others=>'0');
dr <= (others=>'0');
sl <= (others=>'0');
rr <= (others=>'0');
tl <= (others=>'0');
fb <= (others=>'0');
wf <= '0';
ml <= (others=>'0');
fnum <= (others=>'0');
blk <= (others=>'0');
key <= '0';
rks <= (others=>'0');
rhythm <= '0';
extra_mode := '0';
vindex := 0;
elsif clk'event and clk='1' then if clkena='1' then
case stage is
--------------------------------------------------------------------------
-- 1st stage (setting up a read request for Register and Voice memories.)
--------------------------------------------------------------------------
when 0 =>
regs_addr <= slot/2;
if rflag(5) = '1' and 12 <= slot then
slot_voice_addr <= slot - 12 + 32;
else
slot_voice_addr <= inst_cache(slot/2) * 2 + slot mod 2;
end if;
if extra_mode = '0' then
-- Alternately read modulator or carrior.
vindex := slot mod 2;
else
if vindex = VOICE_ID_TYPE'high then
vindex:= 0;
else
vindex:= vindex + 1;
end if;
end if;
user_voice_addr <= vindex;
regs_wr <= '0';
user_voice_wr <='0';
--------------------------------------------------------------------------
-- 2nd stage (just a wait for Register and Voice memories.)
--------------------------------------------------------------------------
when 1 =>
null;
--------------------------------------------------------------------------
-- 3rd stage (updating a register and voice parameters.)
--------------------------------------------------------------------------
when 2 =>
if wr='1' then
if ( extra_mode = '0' and CONV_INTEGER(addr) < 8 ) or
( extra_mode = '1' and ( CONV_INTEGER(addr) - 64 ) / 8 = vindex / 2 ) then
-- Update user voice parameter.
user_voice_tmp := user_voice_rdata;
case addr(2 downto 1) is
when "00" =>
if CONV_INTEGER(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.AM := data(7);
user_voice_tmp.PM := data(6);
user_voice_tmp.EG := data(5);
user_voice_tmp.KR := data(4);
user_voice_tmp.ML := data(3 downto 0);
user_voice_wr <= '1';
end if;
when "01" =>
if addr(0)='0' and (vindex mod 2 = 0) then
user_voice_tmp.KL := data(7 downto 6);
user_voice_tmp.TL := data(5 downto 0);
user_voice_wr <= '1';
elsif addr(0)='1' and (vindex mod 2 = 0) then
user_voice_tmp.WF := data(3);
user_voice_tmp.FB := data(2 downto 0);
user_voice_wr <= '1';
elsif addr(0)='1' and (vindex mod 2 = 1) then
user_voice_tmp.KL := data(7 downto 6);
user_voice_tmp.WF := data(4);
user_voice_wr <= '1';
end if;
when "10" =>
if CONV_INTEGER(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.AR := data(7 downto 4);
user_voice_tmp.DR := data(3 downto 0);
user_voice_wr <= '1';
end if;
when "11" =>
if CONV_INTEGER(addr(0 downto 0)) = (vindex mod 2) then
user_voice_tmp.SL := data(7 downto 4);
user_voice_tmp.RR := data(3 downto 0);
user_voice_wr <= '1';
end if;
end case;
user_voice_wdata <= user_voice_tmp;
elsif CONV_INTEGER(addr) = 14 then
rflag := data;
elsif CONV_INTEGER(addr) < 16 then
null;
elsif CONV_INTEGER(addr) <= 56 then
if( CONV_INTEGER(addr(3 downto 0) ) = slot / 2 ) then
regs_tmp := regs_rdata;
case addr(5 downto 4) is
when "01" => -- register 0x10 to 0x18 (Lower 8bits of f-number)
regs_tmp.FNUM(7 downto 0) := data;
regs_wr <= '1';
when "10" => -- register 0x20 to 0x28 (Sustine, key and MSB of f-number)
regs_tmp.SUS := data(5);
regs_tmp.KEY := data(4);
regs_tmp.BLK := data(3 downto 1);
regs_tmp.FNUM(8) := data(0);
regs_wr <= '1';
when "11" => -- register 0x30 to 0x38 (Instrument and volume)
regs_tmp.INST := data(7 downto 4);
regs_tmp.VOL := data(3 downto 0);
regs_wr <='1';
when others =>
null;
end case;
regs_wdata <= regs_tmp;
end if;
elsif CONV_INTEGER(addr) = 240 then
if data(7 downto 0) = "10000000" then
extra_mode := '1';
else
extra_mode := '0';
end if;
end if;
end if;
--------------------------------------------------------------------------
-- 4th stage (updating a register and voice parameters.)
--------------------------------------------------------------------------
when 3 =>
-- Output slot number (for explicit synchonization with other units).
-- slot_out <= slot;
-- Updating Insturument Cache
inst_cache(slot/2) <= CONV_INTEGER(regs_rdata.INST);
rhythm <= rflag(5);
-- Updating rhythm status and key flag
if rflag(5) = '1' and 12 <= slot then
case slot is
when 12 | 13 => -- BD
kflag := rflag(4);
when 14 => -- HH
kflag := rflag(0);
when 15 => -- SD
kflag := rflag(3);
when 16 => -- TOM
kflag := rflag(2);
when 17 => -- CYM
kflag := rflag(1);
when others => null;
end case;
else
kflag := '0';
end if;
kflag := kflag or regs_rdata.KEY;
-- Calculate key-scale attenuation amount.
kll := (("0"&kl_table(CONV_INTEGER(regs_rdata.FNUM(8 downto 5))))
- ("0"&("111"-regs_rdata.BLK)&"000")) & '0';
if kll(kll'high) ='1' or slot_voice_data.KL = "00" then
kll := (others=>'0');
else
kll := SHR(kll, "11" - slot_voice_data.KL );
end if;
-- Calculate base total level from volume register value.
if rflag(5) = '1' and (slot = 14 or slot = 16) then -- HH and CYM
tll := ('0' & regs_rdata.INST & "000");
elsif (slot mod 2) = 0 then
tll := ('0' & slot_voice_data.TL & '0'); -- MOD
else
tll := ('0' & regs_rdata.VOL & "000"); -- CAR
end if;
tll := tll + kll;
if tll(tll'high) ='1' then
tl <= (others=>'1');
else
tl <= tll(tl'range);
end if;
-- Output Rks, f-number, block and key-status.
fnum <= regs_rdata.FNUM;
blk <= regs_rdata.BLK;
key <= kflag;
if rflag(5) = '1' and 14 <= slot then
if slot_voice_data.KR = '1' then
rks <= "0101";
else
rks <= "00" & regs_rdata.BLK(2 downto 1);
end if;
else
if slot_voice_data.KR = '1' then
rks <= regs_rdata.BLK & regs_rdata.FNUM(8);
else
rks <= "00" & regs_rdata.BLK(2 downto 1);
end if;
end if;
-- Output voice parameters
-- Note that WF and FB output MUST keep its value
-- at least 3 clocks since the Operator module will fetch
-- the WF and FB 2 clocks later of this stage.
am <= slot_voice_data.AM;
pm <= slot_voice_data.PM;
ml <= slot_voice_data.ML;
wf_buf := slot_voice_data.WF;
fb_buf := slot_voice_data.FB;
wf <= wf_buf;
fb <= fb_buf;
ar <= slot_voice_data.AR;
dr <= slot_voice_data.DR;
sl <= slot_voice_data.SL;
-- Output release rate (depends on the sustine and envelope type).
if( kflag = '1' ) then -- Key on
if slot_voice_data.EG = '1' then
rr <= "0000";
else
rr <= slot_voice_data.RR;
end if;
else -- Key off
if (slot mod 2) = 0 and not ( rflag(5) = '1' and (7 <= slot/2) ) then
rr <= "0000";
elsif regs_rdata.SUS = '1' then
rr <= "0101";
elsif slot_voice_data.EG = '0' then
rr <= "0111";
else
rr <= slot_voice_data.RR;
end if;
end if;
end case;
end if; end if;
end process;
end RTL;
| mit | b0b2d377469e5a6978e721742529fa6e | 0.459871 | 3.972841 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/indent_only/graphicsaccelerator/Bresenhamer.vhd | 1 | 7,160 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Bresenhamer is
Port ( WriteEnable : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (8 downto 0);
X1 : in STD_LOGIC_VECTOR (9 downto 0);
Y1 : in STD_LOGIC_VECTOR (8 downto 0);
X2 : in STD_LOGIC_VECTOR (9 downto 0);
Y2 : in STD_LOGIC_VECTOR (8 downto 0);
SS : out STD_LOGIC_VECTOR (3 downto 0);
Clk : in STD_LOGIC;
StartDraw : in STD_LOGIC;
dbg : out STD_LOGIC_VECTOR (11 downto 0);
Reset : in STD_LOGIC);
end Bresenhamer;
architecture Behavioral of Bresenhamer is
signal myX1,myX2 : STD_LOGIC_VECTOR (11 downto 0);
signal myY1,myY2 : STD_LOGIC_VECTOR (11 downto 0);
signal p,p0_1,p0_2,p0_3,p0_4,p0_5,p0_6,p0_7,p0_8 : STD_LOGIC_VECTOR (11 downto 0);
signal p_1,p_2,p_3,p_4,p_5,p_6,p_7,p_8 : STD_LOGIC_VECTOR (11 downto 0);
signal ndx,ndy : STD_LOGIC_VECTOR (11 downto 0);
signal dx,dy,t_2dx,t_2dy,neg_dx,neg_dy,t_2neg_dx,t_2neg_dy : STD_LOGIC_VECTOR (11 downto 0);
signal dx_minus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal minus_dx_minus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal minus_dx_plus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal dx_plus_dy : STD_LOGIC_VECTOR (11 downto 0);
signal State : STD_LOGIC_VECTOR(3 downto 0) := "0000";
signal condX1X2,condY1Y2 : STD_LOGIC;
signal ccounter : STD_LOGIC_VECTOR (18 downto 0) := "0000000000000000000";
constant IDLE : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant INIT : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant CASE1 : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant CASE2 : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant CASE3 : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant CASE4 : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant CASE5 : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant CASE6 : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant CASE7 : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant CASE8 : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant CLEAR : STD_LOGIC_VECTOR(3 downto 0) := "1010";
begin
ndx <= ("00" & X2)-("00" & X1);
ndy <= ("000" & Y2)-("000" & Y1);
neg_dx <= 0-dx;
neg_dy <= 0-dy;
dbg <= p;
dx_minus_dy <= dx+neg_dy;
minus_dx_minus_dy <= neg_dx+neg_dy;
minus_dx_plus_dy <= neg_dx+dy;
dx_plus_dy <= dx+dy;
t_2dy <= dy(10 downto 0) & '0';
t_2dx <= dx(10 downto 0) & '0';
t_2neg_dy <= neg_dy(10 downto 0) & '0';
t_2neg_dx <= neg_dx(10 downto 0) & '0';
p0_1 <= t_2dy+neg_dx;
p0_2 <= t_2dx+neg_dy;
p0_3 <= t_2neg_dx+dy;
p0_4 <= t_2dy+neg_dx;
p0_5 <= t_2neg_dy+dx;
p0_6 <= t_2neg_dx+dy;
p0_7 <= t_2dx+neg_dy;
p0_8 <= t_2neg_dy+dx;
p_1 <= p+t_2dy when p(11)='1' else p+t_2dy+t_2neg_dx;
p_2 <= p+t_2dx when p(11)='1' else p+t_2dx+t_2neg_dy;
p_3 <= p+t_2neg_dx when p(11)='1' else p+t_2neg_dx+t_2neg_dy;
p_4 <= p+t_2dy when p(11)='1' else p+t_2dy+t_2dx;
p_5 <= p+t_2neg_dy when p(11)='1' else p+t_2neg_dy+t_2dx;
p_6 <= p+t_2neg_dx when p(11)='1' else p+t_2neg_dx+t_2dy;
p_7 <= p+t_2dx when p(11)='1' else p+t_2dx+t_2dy;
p_8 <= p+t_2neg_dy when p(11)='1' else p+t_2neg_dy+t_2neg_dx;
X <= ccounter(9 downto 0) when State = CLEAR else myX1(9 downto 0);
Y <= ccounter(18 downto 10) when State = CLEAR else myY1(8 downto 0);
SS <= State;
WriteEnable <= '0' when State = IDLE or State = INIT else '1';
process (Clk) begin
if (rising_edge(Clk)) then
if (State = IDLE) then
if (Reset = '1') then
State <= CLEAR;
ccounter <= (others=>'0');
elsif (StartDraw = '1') then
myX1(9 downto 0) <= X1;
myX1(11 downto 10) <= "00";
myY1(8 downto 0) <= Y1;
myY1(11 downto 9) <= "000";
myX2(9 downto 0) <= X2;
myX2(11 downto 10) <= "00";
myY2(8 downto 0) <= Y2;
myY2(11 downto 9) <= "000";
dx <= ndx;
dy <= ndy;
State <= INIT;
end if;
elsif (State = INIT) then
if (dx(11) = '0' and dy(11) = '0' and dx_minus_dy(11) = '0') then
State <= CASE1;
p <= p0_1;
elsif (dx(11) = '0' and dy(11) = '0' and dx_minus_dy(11) = '1') then
State <= CASE2;
p <= p0_2;
elsif (dx(11) = '1' and dy(11) = '0' and minus_dx_minus_dy(11) = '1') then
State <= CASE3;
p <= p0_3;
elsif (dx(11) = '1' and dy(11) = '0' and minus_dx_minus_dy(11) = '0') then
State <= CASE4;
p <= p0_4;
elsif (dx(11) = '1' and dy(11) = '1' and minus_dx_plus_dy(11) = '0') then
State <= CASE5;
p <= p0_5;
elsif (dx(11) = '1' and dy(11) = '1' and minus_dx_plus_dy(11) = '1') then
State <= CASE6;
p <= p0_6;
elsif (dx(11) = '0' and dy(11) = '1' and dx_plus_dy(11) = '1') then
State <= CASE7;
p <= p0_7;
else
State <= CASE8;
p <= p0_8;
end if;
elsif (State = CASE1) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 + 1;
p <= p_1;
if (P(11) = '0') then
myY1 <= myY1 + 1;
end if;
end if;
elsif (State = CASE2) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 + 1;
p <= p_2;
if (P(11) = '0') then
myX1 <= myX1 + 1;
end if;
end if;
elsif (State = CASE3) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 + 1;
p <= p_3;
if (P(11) = '0') then
myX1 <= myX1 - 1;
end if;
end if;
elsif (State = CASE4) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 - 1;
p <= p_4;
if (P(11) = '0') then
myY1 <= myY1 + 1;
end if;
end if;
elsif (State = CASE5) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 - 1;
p <= p_5;
if (P(11) = '0') then
myY1 <= myY1 - 1;
end if;
end if;
elsif (State = CASE6) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 - 1;
p <= p_6;
if (P(11) = '0') then
myX1 <= myX1 - 1;
end if;
end if;
elsif (State = CASE7) then
if (myY1 = myY2) then
State <= IDLE;
else
myY1 <= myY1 - 1;
p <= p_7;
if (P(11) = '0') then
myX1 <= myX1 + 1;
end if;
end if;
elsif (State = CASE8) then
if (myX1 = myX2) then
State <= IDLE;
else
myX1 <= myX1 + 1;
p <= p_8;
if (P(11) = '0') then
myY1 <= myY1 - 1;
end if;
end if;
elsif (State = CLEAR) then
ccounter <= ccounter + 1;
if (ccounter = "1111111111111111111") then
State <= IDLE;
end if;
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 2b23c006fb170a176ecdd3f79c1ea981 | 0.500978 | 2.719332 | false | false | false | false |
siavooshpayandehazad/TTU_CPU_Project | pico_CPU_pipelined/InstMem.vhd | 1 | 3,654 |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.pico_cpu.all;
entity InstMem is
generic (BitWidth: integer;
InstructionWidth: integer);
port ( address : in std_logic_vector(BitWidth-1 downto 0);
data : out std_logic_vector(InstructionWidth-1 downto 0) );
end entity InstMem;
architecture behavioral of InstMem is
type mem is array ( 0 to InstMem_depth-1) of std_logic_vector(InstructionWidth-1 downto 0);
constant my_InstMem : mem := (
0 => "10000100000000000000000000000000011000",--Load_R0_Dir R0 = 24
1 => "00111100000000000000000000000000000000",--OR_A_R0 ACC = 24
2 => "00011000000000000000000000000000000000",--IncA ACC = 25
3 => "00001100000000000000000000000000000000",--Sub_A_R0 ACC = 1
4 => "11111000000000000000000000000000000000",--NOP
5 => "01011000000000000000000000000000000111",--JmpC 7 Jump
6 => "00011000000000000000000000000000000000",--IncA should be skipped!
7 => "00110000000000000000000000000000000000",--RRC
8 => "00110100000000000000000000000000000000",--RLC ACC = 1
9 => "11111000000000000000000000000000000000",--NOP
10 => "01101100000000000000000000000000000000",--ClearC
11 => "10000000000000000000000000000000010000",--Store_A_Mem MEM[16] = 1
12 => "11110000000000000000000000000000000000",--PUSH
13 => "01111000000000000000000000000000000000",--SavePC
14 => "11110000000000000000000000000000000000",--PUSH
15 => "01001100000000000000000000000000010101",--Jmp 21
16 => "00011000000000000000000000000000000000",--IncA should be skipped!
17 => "11110100000000000000000000000000000000", --pop
18 => "00100100000000000000000000000000000000", --ShiftArithL
19 => "00011100000000000000000000000000000000",--DecA
20 => "11111100000000000000000000000000000000", --HALT
21 => "01111100000000000000000000000000010000",--Load_A_Mem
22 => "00111000000000000000000000000000000000",--AND
23 => "01010000000000000000000000000000011010",--JMPZ 26
24 => "01101100000000000000000000000000000000",--ClearZ
25 => "00000100000000000000000000000000010000",--Add_A_Mem
26 => "00010000000000000000000000000000010000",--Sub_A_Mem
27 => "00000000000000000000000000000000000000",--ADD_A_B
28 => "00010100000000000000000000000000001100",--SUB_A_DIR C
29 => "01000100000000000000000000000000000000",--FlipA
30 => "01000000000000000000000000000000000000",--XOR_A_B
31 => "01001000000000000000000000000000000000",--NegA
32 => "00100000000000000000000000000000000000",--ShiftArithR
33 => "00101100000000000000000000000000000000",--ShiftA_L
34 => "00101000000000000000000000000000000000",--ShiftA_R
35 => "10011000000000000000000000000000000001",--GPIO_DIR SET GPIO AS OUTPUT
36 => "10100000000000000000000000000000101010",--GPIO_WR SET GPIO AS OUTPUT
37 => "01110000000000000000000000000000000000",--ClearACC
38 => "10011000000000000000000000000000000000",--GPIO_DIR SET GPIO AS in
39 => "11111000000000000000000000000000000000",--NOP
40 => "10011100000000000000000000000000000000",--GPIO_RD SET GPIO AS OUTPUT
41 => "11110100000000000000000000000000000000",--POP
42 => "00001000000000000000000000000000000110",--Add_A_Dir
43 => "01110100000000000000000000000000000000",--LoadPC
others => "00000000000000000000000000000000000000"
);
begin
process(address)begin
if to_integer(unsigned(address)) <= InstMem_depth-1 then
data <= my_InstMem(to_integer(unsigned(address)));
else
data <= (others => '0');
end if;
end process;
end architecture behavioral;
| gpl-2.0 | a4d7579f2a5960654d9080631c499dd6 | 0.732074 | 4.745455 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/ua_narrow.vhd | 1 | 18,160 | -------------------------------------------------------------------------------
-- ua_narrow.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: ua_narrow.vhd
--
-- Description: Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/8/2011 v1.03a
-- ~~~~~~
-- Update bit vector usage of address LSB for calculating ua_narrow_load.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Update range of integer signals.
-- ^^^^^^
-- JLJ 3/4/2011 v1.03a
-- ~~~~~~
-- Remove use of local function, Create_Size_Max.
-- ^^^^^^
-- JLJ 3/11/2011 v1.03a
-- ~~~~~~
-- Remove C_AXI_DATA_WIDTH generate statments.
-- ^^^^^^
-- JLJ 3/14/2011 v1.03a
-- ~~~~~~
-- Update ua_narrow_load signal assignment to pass simulations & XST.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, ua_narrow_wrap_gt_width,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity ua_narrow is
generic (
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_NARROW_BURST_CNT_LEN : integer := 4
-- Size of narrow burst counter
);
port (
curr_wrap_burst : in std_logic;
curr_incr_burst : in std_logic;
bram_addr_ld_en : in std_logic;
curr_axlen : in std_logic_vector (7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector (2 downto 0) := (others => '0');
curr_axaddr_lsb : in std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
curr_ua_narrow_wrap : out std_logic;
curr_ua_narrow_incr : out std_logic;
ua_narrow_load : out std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0)
:= (others => '0')
);
end entity ua_narrow;
-------------------------------------------------------------------------------
architecture implementation of ua_narrow is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- Use constant to compare when LSB of ADDR is equal to zero.
constant axaddr_lsb_zero : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Convert # of data bytes for AXI data bus into an unsigned vector (C_MAX_LSHIFT_SIZE:0).
constant C_AXI_DATA_WIDTH_BYTES_UNSIGNED : unsigned (C_MAX_LSHIFT_SIZE downto 0) :=
to_unsigned (C_AXI_DATA_WIDTH_BYTES, C_MAX_LSHIFT_SIZE+1);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal ua_narrow_wrap_gt_width : std_logic := '0';
signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal curr_axsize_int : integer := 0;
signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
signal curr_axlen_unsigned_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
signal bytes_per_addr : integer := 1; -- range 1 to 128 := 1;
signal size_plus_lsb : integer := 1; -- range 1 to 256 := 1;
signal narrow_addr_offset : integer := 1;
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
-- v1.03a
-- Added for narrow INCR bursts with UA addresses
-- Check if burst is a) INCR type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
curr_ua_narrow_incr <= '1' when (curr_incr_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1')
else '0';
-- v1.03a
-- Detect narrow WRAP bursts
-- Detect if the operation is a) WRAP type,
-- b) a narrow burst (SIZE = full width of bus)
-- c) LSB of address is non zero
-- d) complete size of WRAP is larger than width of BRAM
curr_ua_narrow_wrap <= '1' when (curr_wrap_burst = '1') and
(curr_axsize (2 downto 0) /= C_AXI_SIZE_MAX) and
(curr_axaddr_lsb /= axaddr_lsb_zero) and
(bram_addr_ld_en = '1') and
(ua_narrow_wrap_gt_width = '1')
else '0';
---------------------------------------------------------------------------
-- v1.03a
-- Check condition if narrow burst wraps within the size of the BRAM width.
-- Check if size * length > BRAM width in bytes.
--
-- When asserted = '1', means that narrow burst counter is not preloaded early,
-- the BRAM burst will be contained within the BRAM data width.
curr_axsize_unsigned <= unsigned (curr_axsize);
curr_axsize_int <= to_integer (curr_axsize_unsigned);
curr_axlen_unsigned <= unsigned (curr_axlen);
-- Original logic with multiply function.
--
-- ua_narrow_wrap_gt_width <= '0' when (((2**(to_integer (curr_axsize_unsigned))) *
-- unsigned (curr_axlen (7 downto 0)))
-- < C_AXI_DATA_WIDTH_BYTES)
-- else '1';
-- Replace with left shift operation of AxLEN.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
LEN_LSHIFT: process (curr_axlen_unsigned, curr_axsize_int)
begin
for i in C_MAX_LSHIFT_SIZE downto 0 loop
if (i >= curr_axsize_int + 8) then
curr_axlen_unsigned_lshift (i) <= '0';
elsif (i >= curr_axsize_int) then
curr_axlen_unsigned_lshift (i) <= curr_axlen_unsigned (i - curr_axsize_int);
else
curr_axlen_unsigned_lshift (i) <= '0';
end if;
end loop;
end process LEN_LSHIFT;
-- Final result.
ua_narrow_wrap_gt_width <= '0' when (curr_axlen_unsigned_lshift < C_AXI_DATA_WIDTH_BYTES_UNSIGNED)
else '1';
---------------------------------------------------------------------------
-- v1.03a
-- For narrow burst transfer, provides the number of bytes per address
-- XST does not support divisors that are not constants AND powers of two.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_axsize_unsigned)));
-- With this new process:
-- Replace case statement with unsigned signal comparator.
DIV_AXSIZE: process (curr_axsize)
begin
case (curr_axsize) is
when "000" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES / 128; -- Max SIZE for 1024-bit AXI bus
when others => bytes_per_addr <= C_AXI_DATA_WIDTH_BYTES;
end case;
end process DIV_AXSIZE;
-- Original statement.
-- XST does not support divisors that are not constants AND powers of two.
-- Insert process to perform (size_plus_lsb / size_bytes_int) function in generation of ua_narrow_load.
--
-- size_bytes_int <= (2**(to_integer (curr_axsize_unsigned)));
--
-- ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
-- (size_plus_lsb / size_bytes_int), C_NARROW_BURST_CNT_LEN));
-- AxSIZE + LSB of address
-- Use all LSB address bit lanes for the narrow transfer based on C_S_AXI_DATA_WIDTH
size_plus_lsb <= (2**(to_integer (curr_axsize_unsigned))) +
to_integer (unsigned (curr_axaddr_lsb (C_AXI_DATA_WIDTH_BYTES_LOG2-1 downto 0)));
-- Process to keep synthesis with divide by constants that are a power of 2.
DIV_SIZE_BYTES: process (size_plus_lsb,
curr_axsize)
begin
-- Use unsigned w/ curr_axsize signal
case (curr_axsize) is
when "000" => narrow_addr_offset <= size_plus_lsb / 1;
when "001" => narrow_addr_offset <= size_plus_lsb / 2;
when "010" => narrow_addr_offset <= size_plus_lsb / 4;
when "011" => narrow_addr_offset <= size_plus_lsb / 8;
when "100" => narrow_addr_offset <= size_plus_lsb / 16;
when "101" => narrow_addr_offset <= size_plus_lsb / 32;
when "110" => narrow_addr_offset <= size_plus_lsb / 64;
when "111" => narrow_addr_offset <= size_plus_lsb / 128; -- Max SIZE for 1024-bit AXI bus
when others => narrow_addr_offset <= size_plus_lsb;
end case;
end process DIV_SIZE_BYTES;
-- Final new statement.
-- Passing in simulation and XST.
ua_narrow_load <= std_logic_vector (to_unsigned (bytes_per_addr -
narrow_addr_offset, C_NARROW_BURST_CNT_LEN))
when (bytes_per_addr >= narrow_addr_offset)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
end architecture implementation;
| bsd-2-clause | c9a7beb301c1cf84468620218a767651 | 0.49554 | 4.173753 | false | false | false | false |
zcold/fft.vhdl | src/fft_top.vhdl | 1 | 8,732 | -- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------
-- N-point FFT control
----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
entity fft_top is
generic (
-- data width of the real and imaginary part
data_width : integer := 16;
-- points
number_of_points : integer := 64;
-- stages
-- 2^nos = nop
number_of_stages : integer := 6;
-- number of bufferfly operators
number_of_butterfly_operators : integer := 1
);
port (
-- system clock
clk : in std_logic;
-- system reset
nrst : in std_logic;
-- all operations are done
done : out std_logic;
-- initial data
data_in_re : in std_logic_vector (number_of_points * data_width - 1 downto 0);
data_in_im : in std_logic_vector (number_of_points * data_width - 1 downto 0);
-- output data
data_out_re : out std_logic_vector (number_of_points * data_width - 1 downto 0);
data_out_im : out std_logic_vector (number_of_points * data_width - 1 downto 0)
);
end fft_top;
-- Function Implementation 0
architecture FIMP_0 of fft_top is
-- signals between controller and butterfly operators
signal x0_re : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal x0_im : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal x1_re : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal x1_im : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal y0_re : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal y0_im : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal y1_re : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal y1_im : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal wk_re : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
signal wk_im : std_logic_vector (number_of_butterfly_operators * data_width - 1 downto 0);
-- twiddle factors
signal wk_in_re : std_logic_vector (number_of_points/2 * data_width - 1 downto 0);
signal wk_in_im : std_logic_vector (number_of_points/2 * data_width - 1 downto 0);
component cbf_slv is
generic (
-- data width of the real and imaginary part
data_width : integer range 0 to 128 := 16
);
port (
-- clock
clk : in std_logic;
nrst : in std_logic;
-- x0, input 0
x0_re : in std_logic_vector (data_width - 1 downto 0);
x0_im : in std_logic_vector (data_width - 1 downto 0);
-- x1, input 1
x1_re : in std_logic_vector (data_width - 1 downto 0);
x1_im : in std_logic_vector (data_width - 1 downto 0);
-- wk, twiddle factor
wk_re : in std_logic_vector (data_width - 1 downto 0);
wk_im : in std_logic_vector (data_width - 1 downto 0);
-- y0, output 0
y0_re : out std_logic_vector (data_width - 1 downto 0);
y0_im : out std_logic_vector (data_width - 1 downto 0);
-- y1, output 1
y1_re : out std_logic_vector (data_width - 1 downto 0);
y1_im : out std_logic_vector (data_width - 1 downto 0)
);
end component;
component radix_2_fft_control is
generic (
-- data width of the real and imaginary part
data_width : integer := 16;
-- points
number_of_points : integer := 64;
-- stages
-- 2^nos = nop
number_of_stages : integer := 6;
-- number of bufferfly operators
number_of_butterfly_operators : integer := 1
);
port (
-- system clock
clk : in std_logic;
-- system reset
nrst : in std_logic;
-- all operations are done
done : out std_logic;
-- x0 for butterfly operators
x0_re : out std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
x0_im : out std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
-- x1 for butterfly operators
x1_re : out std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
x1_im : out std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
-- twiddle factor for butterfly operators
wk_re : out std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
wk_im : out std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
-- y0 for butterfly operators
y0_re : in std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
y0_im : in std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
-- y1 for butterfly operators
y1_re : in std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
y1_im : in std_logic_vector(number_of_butterfly_operators * data_width - 1 downto 0);
-- initial data
data_in_re : in std_logic_vector (number_of_points * data_width - 1 downto 0);
data_in_im : in std_logic_vector (number_of_points * data_width - 1 downto 0);
-- output data
data_out_re : out std_logic_vector (number_of_points * data_width - 1 downto 0);
data_out_im : out std_logic_vector (number_of_points * data_width - 1 downto 0);
-- twiddle factor
wk_in_re : in std_logic_vector (number_of_points/2 * data_width - 1 downto 0);
wk_in_im : in std_logic_vector (number_of_points/2 * data_width - 1 downto 0)
);
end component;
component twiddle_factor is
generic (
-- data width of the real and imaginary part
data_width : integer := 16
);
port (
-- twiddle factor output
wk_out_re : out std_logic_vector (64 / 2 * data_width - 1 downto 0);
wk_out_im : out std_logic_vector (64 / 2 * data_width - 1 downto 0)
);
end component;
begin
GEN_CBF: for i in 0 to number_of_butterfly_operators - 1 generate
cbf_slv_0: cbf_slv
generic map (data_width)
port map ( clk, nrst,
x0_re( (i+1) * data_width - 1 downto i * data_width),
x0_im( (i+1) * data_width - 1 downto i * data_width),
x1_re( (i+1) * data_width - 1 downto i * data_width),
x1_im( (i+1) * data_width - 1 downto i * data_width),
wk_re( (i+1) * data_width - 1 downto i * data_width),
wk_im( (i+1) * data_width - 1 downto i * data_width),
y0_re( (i+1) * data_width - 1 downto i * data_width),
y0_im( (i+1) * data_width - 1 downto i * data_width),
y1_re( (i+1) * data_width - 1 downto i * data_width),
y1_im( (i+1) * data_width - 1 downto i * data_width));
end generate GEN_CBF;
radix_2_fft_control_0: radix_2_fft_control
generic map(data_width, number_of_points, number_of_stages, number_of_butterfly_operators)
port map( clk, nrst, done,
x0_re, x0_im,
x1_re, x1_im,
wk_re, wk_im,
y0_re, y0_im,
y1_re, y1_im,
data_in_re, data_in_im,
data_out_re, data_out_im,
wk_in_re, wk_in_im);
twiddle_factor_0: twiddle_factor
generic map (data_width)
port map(wk_in_re, wk_in_im);
end FIMP_0;
| mit | eba4ebfcc916fb2a096dcfbb976154e6 | 0.614521 | 3.498397 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_035_test_input.vhd | 1 | 820 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : entity fifo_dsn.INST1(rtl);
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
);
U_INST3 : INST3
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violation below
U_INST1 : entity fifo_dsn.INST1(rtl)
;
U_INST2 : component INST2
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
;
U_INST3 : INST3
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
)
;
end architecture ARCH;
| gpl-3.0 | f540affdeed7d55f41e207b7961b20ed | 0.454878 | 2.760943 | false | false | false | false |
Yarr/Yarr-fw | syn/kintex7/rd53_ohio_16x1_160Mbps/board_pkg.vhd | 1 | 953 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.hw_type_pkg.all;
package board_pkg is
constant c_FW_IDENT : std_logic_vector(31 downto 0) := c_HW_IDENT & x"030212";
constant c_TX_ENCODING : string := "OSERDES";
constant c_TX_CHANNELS : integer := 4;
constant c_RX_CHANNELS : integer := 16;
constant c_FE_TYPE : string := "RD53";
constant c_RX_NUM_LANES : integer := 1;
constant c_RX_SPEED : string := "0160";
constant c_TX_IDLE_WORD : std_logic_vector(31 downto 0) := x"AAAAAAAA";
constant c_TX_SYNC_WORD : std_logic_vector(31 downto 0) := x"817e817e";
constant c_TX_SYNC_INTERVAL : unsigned(7 downto 0) := to_unsigned(16,8);
constant c_TX_AZ_WORD : std_logic_vector(31 downto 0) := x"00000000";
constant c_TX_AZ_INTERVAL : unsigned(15 downto 0) := to_unsigned(500,16);
constant c_TX_40_DIVIDER : unsigned(3 downto 0) := to_unsigned(4,4);
end board_pkg;
| gpl-3.0 | 10ffb5977e6867a7cde49aad9345a53f | 0.665268 | 3.006309 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/port_map/rule_008_test_input.vhd | 1 | 634 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map(
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (w_port_1,
PORT_2 => w_port_2,
w_port_3
);
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (PORT_1 => w_port_1,
w_port_2,
w_port_3
);
end architecture ARCH;
| gpl-3.0 | 24134554799e301a1acc73f5e43e6356 | 0.446372 | 2.663866 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/styles/jcl/graphicsaccelerator/Synchronizer.fixed.vhd | 1 | 3,248 |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity SYNCHRONIZER is
port (
R : out std_logic;
G : out std_logic;
B : out std_logic;
HS : out std_logic;
VS : out std_logic;
CLK : in std_logic;
DATAIN : in std_logic_vector(2 downto 0);
ADDRESSX : out std_logic_vector(9 downto 0);
ADDRESSY : out std_logic_vector(8 downto 0)
);
end entity SYNCHRONIZER;
architecture BEHAVIORAL of SYNCHRONIZER is
signal x, nx : std_logic_vector(10 downto 0) := (others => '0');
signal y, ny : std_logic_vector(20 downto 0) := (others => '0');
constant tpw : std_logic_vector(1 downto 0) := "00";
constant tbp : std_logic_vector(1 downto 0) := "01";
constant tdp : std_logic_vector(1 downto 0) := "10";
constant tfp : std_logic_vector(1 downto 0) := "11";
signal xstate : std_logic_vector(1 downto 0) := tpw;
signal ystate : std_logic_vector(1 downto 0) := tpw;
signal enabledisplay : std_logic;
signal addressofy, naddressofy : std_logic_vector(8 downto 0);
begin
nx <= x + 1;
ny <= y + 1;
naddressofy <= addressofy + 1;
HS <= '0' when xstate=tpw else
'1';
VS <= '0' when ystate=tpw else
'1';
enabledisplay <= '1' when xstate=tdp and ystate=tdp else
'0';
R <= DATAIN(0) when enabledisplay='1' else
'0';
B <= DATAIN(1) when enabledisplay='1' else
'0';
G <= DATAIN(2) when enabledisplay='1' else
'0';
ADDRESSX <= x(10 downto 1);
ADDRESSY <= addressofy - 30;
process (CLK) is
begin
if (CLK'event and CLK = '1') then
if (xstate=tpw and x(7 downto 1)="1100000") then
x <= (others => '0');
xstate <= tbp;
elsif (xstate=tbp and x(6 downto 1)="110000") then
x <= (others => '0');
xstate <= tdp;
elsif (xstate=tdp and x(10 downto 1)="1010000000") then
x <= (others => '0');
xstate <= tfp;
elsif (xstate=tfp and x(5 downto 1)="10000") then
x <= (others => '0');
xstate <= tpw;
addressofy <= naddressofy;
else
x <= nx;
end if;
if (ystate=tpw and y(12 downto 1)="11001000000") then
y <= (others => '0');
ystate <= tbp;
elsif (ystate=tbp and y(16 downto 1)="101101010100000") then
y <= (others => '0');
ystate <= tdp;
elsif (ystate=tdp and y(20 downto 1)="1011101110000000000") then
y <= (others => '0');
ystate <= tfp;
elsif (ystate=tfp and y(14 downto 1)="1111101000000") then
y <= (others => '0');
x <= (others => '0');
ystate <= tpw;
xstate <= tpw;
addressofy <= (others => '0');
else
y <= ny;
end if;
end if;
end process;
end architecture BEHAVIORAL;
| gpl-3.0 | 22f27174c4e7e6157da4eadf691cbd7d | 0.483682 | 3.584989 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/if_statement/rule_011_test_input.fixed.vhd | 1 | 953 |
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Check loop statements
if a = '1' then
else
LOOP_LABEL : loop
end loop;
end if;
if a = '1' then
else
loop
end loop;
end if;
if a = '1' then
else
while a = 0
loop
end loop;
end if;
if a = '1' then
else
for i in 0 to 13
loop
end loop;
end if;
end process;
end architecture RTL;
| gpl-3.0 | 0cd373cbc1cb17fd0c8fe214bbd7ca82 | 0.391396 | 3.428058 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/axi_slave_2to1.vhd | 3 | 31,357 | `protect begin_protected
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21472)
`protect data_block
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`protect end_protected
| mit | 1ed6edc95187bd26f34dd76a0687bccc | 0.946615 | 1.83966 | false | false | false | false |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/MicroProcessor.vhd | 1 | 6,163 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity MicroProcessor is
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
stop : out std_logic
);
end MicroProcessor;
architecture MicroProcessor_Behavioural of MicroProcessor is
component MicroROM is
port(
read_enable : in std_logic;
address : in std_logic_vector(7 downto 0);
data_output : out std_logic_vector(27 downto 0)
);
end component;
component MRAM is
port(
clk : in std_logic;
read_write : in std_logic;
read_address_1 : in std_logic_vector(7 downto 0);
read_address_2 : in std_logic_vector(7 downto 0);
write_address : in std_logic_vector(7 downto 0);
read_data_port_1 : out std_logic_vector(7 downto 0);
read_data_port_2 : out std_logic_vector(7 downto 0);
write_data_port : in std_logic_vector(7 downto 0)
);
end component;
component Datapath is
port(
enabled : in std_logic;
operation_code : in std_logic_vector(3 downto 0);
operand_1 : in std_logic_vector(7 downto 0);
operand_2 : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0);
zero_flag : out std_logic;
significant_bit_flag : out std_logic
);
end component;
component Controller is
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
stop : out std_logic;
rom_enabled : out std_logic;
rom_address : out std_logic_vector(7 downto 0);
rom_data_output : in std_logic_vector(27 downto 0);
ram_read_write : out std_logic;
ram_write_data_port : out std_logic_vector(7 downto 0);
ram_write_address : out std_logic_vector(7 downto 0);
ram_read_data_port_1 : in std_logic_vector(7 downto 0);
ram_read_data_port_2 : in std_logic_vector(7 downto 0);
ram_read_address_1 : out std_logic_vector(7 downto 0);
ram_read_address_2 : out std_logic_vector(7 downto 0);
datapath_enabled : out std_logic;
datapath_operation_code : out std_logic_vector(3 downto 0);
datapath_operand_1 : out std_logic_vector(7 downto 0);
datapath_operand_2 : out std_logic_vector(7 downto 0);
datapath_result : in std_logic_vector(7 downto 0);
datapath_zero_flag : in std_logic;
datapath_significant_bit_flag : in std_logic
);
end component;
signal mp_ram_read_write : std_logic;
signal mp_ram_read_address_1 : std_logic_vector(7 downto 0);
signal mp_ram_read_address_2 : std_logic_vector(7 downto 0);
signal mp_ram_write_address : std_logic_vector(7 downto 0);
signal mp_ram_read_data_port_1 : std_logic_vector(7 downto 0);
signal mp_ram_read_data_port_2 : std_logic_vector(7 downto 0);
signal mp_ram_write_data_port : std_logic_vector(7 downto 0);
signal mp_rom_read_enable : std_logic;
signal mp_rom_address : std_logic_vector(7 downto 0);
signal mp_rom_data_output : std_logic_vector(27 downto 0);
signal mp_datapath_enabled : std_logic;
signal mp_datapath_operation_code : std_logic_vector(3 downto 0);
signal mp_datapath_operand_1 : std_logic_vector(7 downto 0);
signal mp_datapath_operand_2 : std_logic_vector(7 downto 0);
signal mp_datapath_result : std_logic_vector(7 downto 0);
signal mp_datapath_zero_flag : std_logic;
signal mp_datapath_significant_bit_flag : std_logic;
begin
U_RAM : entity MRAM port map(
clk => clk,
write_data_port => mp_ram_write_data_port,
write_address => mp_ram_write_address,
read_data_port_1 => mp_ram_read_data_port_1,
read_data_port_2 => mp_ram_read_data_port_2,
read_address_1 => mp_ram_read_address_1,
read_address_2 => mp_ram_read_address_2,
read_write => mp_ram_read_write
);
U_ROM : entity MicroROM port map(
read_enable => mp_rom_read_enable,
address => mp_rom_address,
data_output => mp_rom_data_output
);
U_DATAPATH : Datapath port map(
enabled => mp_datapath_enabled,
operation_code => mp_datapath_operation_code,
operand_1 => mp_datapath_operand_1,
operand_2 => mp_datapath_operand_2,
result => mp_datapath_result,
zero_flag => mp_datapath_zero_flag,
significant_bit_flag => mp_datapath_significant_bit_flag
);
U_CONTROLLER : Controller port map(
clk => clk,
rst => rst,
start => start,
stop => stop,
rom_enabled => mp_rom_read_enable,
rom_address => mp_rom_address,
rom_data_output => mp_rom_data_output,
ram_read_write => mp_ram_read_write,
ram_write_data_port => mp_ram_write_data_port,
ram_write_address => mp_ram_write_address,
ram_read_data_port_1 => mp_ram_read_data_port_1,
ram_read_data_port_2 => mp_ram_read_data_port_2,
ram_read_address_1 => mp_ram_read_address_1,
ram_read_address_2 => mp_ram_read_address_2,
datapath_enabled => mp_datapath_enabled,
datapath_operation_code => mp_datapath_operation_code,
datapath_operand_1 => mp_datapath_operand_1,
datapath_operand_2 => mp_datapath_operand_2,
datapath_result => mp_datapath_result,
datapath_zero_flag => mp_datapath_zero_flag,
datapath_significant_bit_flag => mp_datapath_significant_bit_flag
);
end MicroProcessor_Behavioural;
| mit | cc6fea4ddf36c28a917bcf871269bffa | 0.56969 | 3.248814 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/variable_assignment/rule_006_test_input.fixed.vhd | 1 | 681 |
architecture RTL of FIFO is
begin
process
begin
SIMPLE_LABEL : x := z;
a := b;
CONDITIONAL_LABEL : x := z when b = 0 else y;
x := z when b = 0 else y;
SELECTED_LABEL : with some_expression select a := b when z = 1;
with some_expression select a := b when z = 1;
end process;
end architecture;
-- Violations below
architecture RTL of FIFO is
begin
process
begin
a := b or c -- comment
d and z
w or x; -- This should stay
x := z when b = 0 else -- check for something
y;
with some_expression
--comment
select a := b
--comment
when z = 1;
end process;
end architecture;
| gpl-3.0 | 1b01d573b88abb053b0a34e156fcacb8 | 0.572687 | 3.681081 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/concurrent_procedure_call_statement/classification_test_input.vhd | 1 | 445 |
architecture RTL of FIFO is
begin
Proc1 (Clock, A, Sig1, Sig2, Var1, Var2, Period);
READ (L => BufLine, VALUE => Q);
LABEL1: Proc1 (Clock);
LABEL2 : READ (L => BufLine,
VALUE => Q);
LABEL1: postponed Proc1 (Clock);
LABEL2 : postponed READ (L => BufLine,
VALUE => Q);
postponed Proc1 (Clock);
postponed READ (L => BufLine,
VALUE => Q);
end architecture RTL;
| gpl-3.0 | 8f5ae105ac6805a11fdd2cfd01fd13ab | 0.541573 | 3.531746 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_003_test_input.fixed.vhd | 2 | 525 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 76f098258b4771817fdf83928c33be60 | 0.470476 | 2.734375 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/common/shft_wrapper.vhd | 2 | 13,889 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | 8e1cc103ebd0dc859334176243a4a69c | 0.932177 | 1.88351 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/ieee/rule_500_test_input.fixed_upper.vhd | 1 | 2,637 |
entity FIFO is
generic (
G_GEN1 : STD_LOGIC,
G_GEN2 : STD_LOGIC_VECTOR(3 downto 0),
G_GEN3 : INTEGER,
G_GEN4 : SIGNED(15 downto 0),
G_GEN5 : UNSIGNED(7 downto 0)
);
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end entity FIFO;
architecture rtl of fifo is
signal my_sig : STD_LOGIC;
constant my_con : STD_LOGIC_VECTOR(3 downto 0);
procedure my_proc (
init : in STD_LOGIC
) is
variable my_sig : STD_LOGIC;
constant my_con : STD_LOGIC_VECTOR(3 downto 0);
begin
end procedure;
component MY_COMP is
generic (
G_GEN1 : STD_LOGIC,
G_GEN2 : STD_LOGIC_VECTOR(3 downto 0),
G_GEN3 : INTEGER,
G_GEN4 : SIGNED(15 downto 0),
G_GEN5 : UNSIGNED(7 downto 0)
);
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end component;
begin
end architecture rtl;
--====== UPPERCASE before
entity FIFO is
generic (
G_GEN1 : STD_LOGIC,
G_GEN2 : STD_LOGIC_VECTOR(3 downto 0),
G_GEN3 : INTEGER,
G_GEN4 : SIGNED(15 downto 0),
G_GEN5 : UNSIGNED(7 downto 0)
);
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end entity FIFO;
architecture rtl of fifo is
signal my_sig : STD_LOGIC;
constant my_con : STD_LOGIC_VECTOR(3 downto 0);
procedure my_proc (
init : in STD_LOGIC
) is
variable my_sig : STD_LOGIC;
constant my_con : STD_LOGIC_VECTOR(3 downto 0);
begin
end procedure;
component MY_COMP is
generic (
G_GEN1 : STD_LOGIC,
G_GEN2 : STD_LOGIC_VECTOR(3 downto 0),
G_GEN3 : INTEGER,
G_GEN4 : SIGNED(15 downto 0),
G_GEN5 : UNSIGNED(7 downto 0)
);
port (
I_PORT1 : in INTEGER;
I_PORT2 : in STD_LOGIC;
I_PORTA : in t_user2;
I_PORT3 : in STD_LOGIC_VECTOR(3 downto 0);
I_PORT4 : in SIGNED(15 downto 0);
I_PORT5 : in UNSIGNED(7 downto 0);
I_PORT6 : in STD_ULOGIC;
I_PORT7 : in t_user1
);
end component;
begin
end architecture rtl;
| gpl-3.0 | ccd441539046db0ef014d0e19735dfab | 0.591202 | 2.979661 | false | false | false | false |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/MRAM.vhd | 1 | 2,265 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity MRAM is
port(
read_write : in std_logic;
clk : in std_logic;
read_address_1 : in std_logic_vector(7 downto 0);
read_address_2 : in std_logic_vector(7 downto 0);
write_address : in std_logic_vector(7 downto 0);
read_data_port_1 : out std_logic_vector(7 downto 0);
read_data_port_2 : out std_logic_vector(7 downto 0);
write_data_port : in std_logic_vector(7 downto 0)
);
end MRAM;
architecture Beh_GPR of MRAM is
subtype byte is std_logic_vector(7 downto 0);
type RAM_t is array (0 to 255) of byte;
--
-- Initial state for memory
--
signal RAM : RAM_t := (
"00000101", -- 5 a[0]
"00000011", -- 3 a[1]
"00000001", -- 1 a[2]
"00000100", -- 4 a[3]
"00000000", -- 0 a[4] [-]
"00000011", -- 3 a[5] outer loop: max index value
"00000100", -- 4 a[6] inner loop: max index value
"00000000", -- 0 a[7] outer loop: current index
"00000000", -- 0 a[8] inner loop: current index
"00000001", -- 1 a[9] constant one = 1
"00000000", -- 0 a[10] constant zero = 0
"00000000", -- 0 a[11] reserved cell (temp 1)
"00000000", -- 0 a[12] reserved cell (temp 2)
"00000000", -- 0 a[13] reserved cell (temp 3)
others => "00000000"
);
signal data_win : byte;
signal data_1out : byte;
signal data_2out : byte;
Begin
data_win <= write_data_port;
WRITE : process(clk)
begin
if (rising_edge(clk)) then
if (read_write = '0') then
RAM(conv_integer(write_address)) <= data_win;
end if;
end if;
end process;
data_1out <= RAM(conv_integer(read_address_1));
data_2out <= RAM(conv_integer(read_address_2));
READ : process(clk)
begin
if (rising_edge(clk)) then
if (read_write = '1') then
read_data_port_1 <= data_1out;
read_data_port_2 <= data_2out;
else
read_data_port_1 <= (others => 'Z');
read_data_port_2 <= (others => 'Z');
end if;
end if;
end process;
End Beh_GPR; | mit | 25fcbe9259e88638f22a78ef6b549ff0 | 0.535982 | 2.918814 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/generate/rule_400_test_input.vhd | 1 | 1,681 |
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
CASE_LABEL : case data generate
when a = 1 =>
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
IF_LABEL : if a = '1' generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
CASE_LABEL : case data generate
when a = 1 =>
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
end;
| gpl-3.0 | bbbd5722d61533acf54d5c2fddb3685d | 0.549673 | 3.891204 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axi_dma_0_0/axi_sg_v4_1/hdl/src/vhdl/axi_sg_sfifo_autord.vhd | 1 | 20,297 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- axi_sg_sfifo_autord.vhd
-- |
-- |--- sync_fifo_fg (FIFO Generator wrapper)
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_sg_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
-- Sets the width of the FIFO Data
C_DEPTH : integer := 128;
-- Sets the depth of the FIFO
C_DATA_CNT_WIDTH : integer := 8;
-- Sets the width of the FIFO Data Count output
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
-- Indicates the need for an almost empty flag from the internal FIFO
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
-- Indicates the need for an almost full flag from the internal FIFO
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- Sets the type of memory to use for the FIFO
-- 0 = Distributed Logic
-- 1 = Block Ram
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- FIFO Inputs ------------------------------------------------------------------
SFIFO_Sinit : In std_logic; --
SFIFO_Clk : In std_logic; --
SFIFO_Wr_en : In std_logic; --
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Rd_en : In std_logic; --
SFIFO_Clr_Rd_Data_Valid : In std_logic; --
--------------------------------------------------------------------------------
-- FIFO Outputs -----------------------------------------------------------------
SFIFO_DValid : Out std_logic; --
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
SFIFO_Full : Out std_logic; --
SFIFO_Empty : Out std_logic; --
SFIFO_Almost_full : Out std_logic; --
SFIFO_Almost_empty : Out std_logic; --
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); --
SFIFO_Rd_ack : Out std_logic --
--------------------------------------------------------------------------------
);
end entity axi_sg_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity proc_common_v4_0.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
| bsd-2-clause | 36402bb90dae37c8a5cb1a192eebb62c | 0.426368 | 4.96745 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/synth/cascaded_integrator_comb.vhd | 1 | 8,417 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cic_compiler:4.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cic_compiler_v4_0;
USE cic_compiler_v4_0.cic_compiler_v4_0;
ENTITY cascaded_integrator_comb IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC
);
END cascaded_integrator_comb;
ARCHITECTURE cascaded_integrator_comb_arch OF cascaded_integrator_comb IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cascaded_integrator_comb_arch: ARCHITECTURE IS "yes";
COMPONENT cic_compiler_v4_0 IS
GENERIC (
C_COMPONENT_NAME : STRING;
C_FILTER_TYPE : INTEGER;
C_NUM_STAGES : INTEGER;
C_DIFF_DELAY : INTEGER;
C_RATE : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_USE_DSP : INTEGER;
C_HAS_ROUNDING : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_RATE_TYPE : INTEGER;
C_MIN_RATE : INTEGER;
C_MAX_RATE : INTEGER;
C_SAMPLE_FREQ : INTEGER;
C_CLK_FREQ : INTEGER;
C_USE_STREAMING_INTERFACE : INTEGER;
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_C1 : INTEGER;
C_C2 : INTEGER;
C_C3 : INTEGER;
C_C4 : INTEGER;
C_C5 : INTEGER;
C_C6 : INTEGER;
C_I1 : INTEGER;
C_I2 : INTEGER;
C_I3 : INTEGER;
C_I4 : INTEGER;
C_I5 : INTEGER;
C_I6 : INTEGER;
C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
C_HAS_DOUT_TREADY : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_halted : OUT STD_LOGIC
);
END COMPONENT cic_compiler_v4_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cascaded_integrator_comb_arch: ARCHITECTURE IS "cic_compiler_v4_0,Vivado 2014.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cascaded_integrator_comb_arch : ARCHITECTURE IS "cascaded_integrator_comb,cic_compiler_v4_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cascaded_integrator_comb_arch: ARCHITECTURE IS "cascaded_integrator_comb,cic_compiler_v4_0,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_COMPONENT_NAME=cascaded_integrator_comb,C_FILTER_TYPE=1,C_NUM_STAGES=5,C_DIFF_DELAY=1,C_RATE=16,C_INPUT_WIDTH=2,C_OUTPUT_WIDTH=22,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=16,C_MAX_RATE=16,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_C1=22,C_C2=22,C_C3=22,C_C4=22,C_C5=22,C_C6=0,C_I1=22,C_I2=22,C_I3=22,C_I4=22,C_I5=22,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=8,C_M_AXIS_DATA_TDATA_WIDTH=24,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
BEGIN
U0 : cic_compiler_v4_0
GENERIC MAP (
C_COMPONENT_NAME => "cascaded_integrator_comb",
C_FILTER_TYPE => 1,
C_NUM_STAGES => 5,
C_DIFF_DELAY => 1,
C_RATE => 16,
C_INPUT_WIDTH => 2,
C_OUTPUT_WIDTH => 22,
C_USE_DSP => 1,
C_HAS_ROUNDING => 0,
C_NUM_CHANNELS => 1,
C_RATE_TYPE => 0,
C_MIN_RATE => 16,
C_MAX_RATE => 16,
C_SAMPLE_FREQ => 1,
C_CLK_FREQ => 1,
C_USE_STREAMING_INTERFACE => 1,
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_C1 => 22,
C_C2 => 22,
C_C3 => 22,
C_C4 => 22,
C_C5 => 22,
C_C6 => 0,
C_I1 => 22,
C_I2 => 22,
C_I3 => 22,
C_I4 => 22,
C_I5 => 22,
C_I6 => 0,
C_S_AXIS_CONFIG_TDATA_WIDTH => 1,
C_S_AXIS_DATA_TDATA_WIDTH => 8,
C_M_AXIS_DATA_TDATA_WIDTH => 24,
C_M_AXIS_DATA_TUSER_WIDTH => 1,
C_HAS_DOUT_TREADY => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0'
);
END cascaded_integrator_comb_arch;
| mit | ca37d02b6c3c4058282e1fb1c159b19c | 0.669597 | 3.216278 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/instantiation/rule_004_test_input.vhd | 1 | 535 |
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1: INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
a <= b;
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
| gpl-3.0 | 72a3c09ee4158e8e02ac3f0672441103 | 0.465421 | 2.70202 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_010_test_input.vhd | 1 | 447 |
architecture RTL of FIFO is
begin
-- These are passing
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
with z select
a <= b when z = "000",
c when z = "001";
-- Failing variations
a <= b or
d;
a <= '0' when c = '0' else
'1' when d = '1' else
'Z';
with z select
a <= b when z = "000",
c when z = "001";
end architecture RTL;
| gpl-3.0 | cf0ccb905129d75ae3a56f7046223c15 | 0.438479 | 3.170213 | false | false | false | false |
Yarr/Yarr-fw | rtl/kintex7/rx-core/xapp1017/delay_controller_wrap.vhd | 1 | 18,736 | ------------------------------------------------------------------------------
-- Copyright (c) 2012 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: delay_controller_wrap.vhd
-- / / Date Last Modified: Mar 30, 2016
-- /___/ /\ Date Created: Jan 8, 2013
-- \ \ / \
-- \___\/\___\
--
--Device: 7 Series
--Purpose: Controls delays on a per-bit basis
-- Number of bits from each seres set via an attribute
--
--Reference: XAPP585.pdf
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity delay_controller_wrap is generic (
S : integer := 4) ; -- Set the number of bits
port (
m_datain : in std_logic_vector(S-1 downto 0) ; -- Inputs from master serdes
s_datain : in std_logic_vector(S-1 downto 0) ; -- Inputs from slave serdes
enable_phase_detector : in std_logic ; -- Enables the phase detector logic when high
enable_monitor : in std_logic ; -- Enables the eye monitoring logic when high
reset : in std_logic ; -- Reset line synchronous to clk
clk : in std_logic ; -- Global/Regional clock
c_delay_in : in std_logic_vector(4 downto 0) ; -- delay value found on clock line
m_delay_out : out std_logic_vector(4 downto 0) ; -- Master delay control value
s_delay_out : out std_logic_vector(4 downto 0) ; -- Master delay control value
data_out : out std_logic_vector(S-1 downto 0) ; -- Output data
results : out std_logic_vector(31 downto 0) ; -- eye monitor result data
m_delay_1hot : out std_logic_vector(31 downto 0) ; -- Master delay control value as a one-hot vector
debug : out std_logic_vector(1 downto 0) ; -- debug data
del_mech : in std_logic ; -- changes delay mechanism slightly at higher bit rates
bt_val : in std_logic_vector(4 downto 0)) ; -- Calculated bit time value for slave devices
end delay_controller_wrap ;
architecture arch_delay_controller_wrap of delay_controller_wrap is
signal mdataouta : std_logic_vector(S-1 downto 0) ;
signal mdataoutb : std_logic ;
signal mdataoutc : std_logic_vector(S-1 downto 0) ;
signal sdataouta : std_logic_vector(S-1 downto 0) ;
signal sdataoutb : std_logic ;
signal sdataoutc : std_logic_vector(S-1 downto 0) ;
signal s_ovflw : std_logic ;
signal m_delay_mux : std_logic_vector(1 downto 0) ;
signal s_delay_mux : std_logic_vector(1 downto 0) ;
signal data_mux : std_logic ;
signal dec_run : std_logic ;
signal inc_run : std_logic ;
signal eye_run : std_logic ;
signal s_state : std_logic_vector(4 downto 0) ;
signal pdcount : std_logic_vector(5 downto 0) ;
signal m_delay_val_int : std_logic_vector(4 downto 0) ;
signal s_delay_val_int : std_logic_vector(4 downto 0) ;
signal s_delay_val_eye : std_logic_vector(4 downto 0) ;
signal meq_max : std_logic ;
signal meq_min : std_logic ;
signal pd_max : std_logic ;
signal pd_min : std_logic ;
signal delay_change : std_logic ;
signal msxoria : std_logic_vector(7 downto 0) ;
signal msxorda : std_logic_vector(7 downto 0) ;
signal action : std_logic_vector(1 downto 0) ;
signal msxor_cti : std_logic_vector(1 downto 0) ;
signal msxor_ctd : std_logic_vector(1 downto 0) ;
signal msxor_ctix : std_logic_vector(1 downto 0) ;
signal msxor_ctdx : std_logic_vector(1 downto 0) ;
signal msxor_ctiy : std_logic_vector(2 downto 0) ;
signal msxor_ctdy : std_logic_vector(2 downto 0) ;
signal match : std_logic_vector(7 downto 0) ;
signal shifter : std_logic_vector(31 downto 0) := (0=>'1', others => '0') ;
signal pd_hold : std_logic_vector(7 downto 0) ;
signal res_int : std_logic_vector(31 downto 0) := (others => '0') ;
signal bt_val_d2 : std_logic_vector(4 downto 0) ;
begin
m_delay_out <= m_delay_val_int ;
s_delay_out <= s_delay_val_int ;
results <= res_int ;
debug <= action ;
bt_val_d2 <= '0' & bt_val(4 downto 1) ;
loop2 : if S /= 8 generate -- phase detector filter, works on changes in data only
loop3 : for i in S to 7 generate
msxoria(i) <= '0' ; -- unused early bits
msxorda(i) <= '0' ; -- unused late bits
end generate ;
end generate ;
loop0 : for i in 0 to S-2 generate
msxoria(i+1) <= ((not s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and not sdataouta(i)) or (not mdataouta(i) and mdataouta(i+1) and sdataouta(i)))) or
( s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and not sdataouta(i+1)) or (not mdataouta(i) and mdataouta(i+1) and sdataouta(i+1))))) ; -- early bits
msxorda(i+1) <= ((not s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and sdataouta(i)) or (not mdataouta(i) and mdataouta(i+1) and not sdataouta(i))))) or
( s_ovflw and ((mdataouta(i) and not mdataouta(i+1) and sdataouta(i+1)) or (not mdataouta(i) and mdataouta(i+1) and not sdataouta(i+1)))) ; -- late bits
end generate ;
msxoria(0) <= ((not s_ovflw and ((mdataoutb and not mdataouta(0) and not sdataoutb) or (not mdataoutb and mdataouta(0) and sdataoutb))) or -- first early bit
( s_ovflw and ((mdataoutb and not mdataouta(0) and not sdataouta(0)) or (not mdataoutb and mdataouta(0) and sdataouta(0))))) ;
msxorda(0) <= ((not s_ovflw and ((mdataoutb and not mdataouta(0) and sdataoutb) or (not mdataoutb and mdataouta(0) and not sdataoutb)))) or -- first late bit
( s_ovflw and ((mdataoutb and not mdataouta(0) and sdataouta(0)) or (not mdataoutb and mdataouta(0) and not sdataouta(0)))) ;
process (clk) begin
if clk'event and clk = '1' then -- generate number of incs or decs for low 4 bits
case (msxoria(3 downto 0)) is
when X"0" => msxor_cti <= "00" ;
when X"1" => msxor_cti <= "01" ;
when X"2" => msxor_cti <= "01" ;
when X"3" => msxor_cti <= "10" ;
when X"4" => msxor_cti <= "01" ;
when X"5" => msxor_cti <= "10" ;
when X"6" => msxor_cti <= "10" ;
when X"8" => msxor_cti <= "01" ;
when X"9" => msxor_cti <= "10" ;
when X"A" => msxor_cti <= "10" ;
when X"C" => msxor_cti <= "10" ;
when others => msxor_cti <= "11" ;
end case ;
case (msxorda(3 downto 0)) is
when X"0" => msxor_ctd <= "00" ;
when X"1" => msxor_ctd <= "01" ;
when X"2" => msxor_ctd <= "01" ;
when X"3" => msxor_ctd <= "10" ;
when X"4" => msxor_ctd <= "01" ;
when X"5" => msxor_ctd <= "10" ;
when X"6" => msxor_ctd <= "10" ;
when X"8" => msxor_ctd <= "01" ;
when X"9" => msxor_ctd <= "10" ;
when X"A" => msxor_ctd <= "10" ;
when X"C" => msxor_ctd <= "10" ;
when others => msxor_ctd <= "11" ;
end case ;
case (msxoria(7 downto 4)) is -- generate number of incs or decs for high n bits, max 4
when X"0" => msxor_ctix <= "00" ;
when X"1" => msxor_ctix <= "01" ;
when X"2" => msxor_ctix <= "01" ;
when X"3" => msxor_ctix <= "10" ;
when X"4" => msxor_ctix <= "01" ;
when X"5" => msxor_ctix <= "10" ;
when X"6" => msxor_ctix <= "10" ;
when X"8" => msxor_ctix <= "01" ;
when X"9" => msxor_ctix <= "10" ;
when X"A" => msxor_ctix <= "10" ;
when X"C" => msxor_ctix <= "10" ;
when others => msxor_ctix <= "11" ;
end case ;
case (msxorda(7 downto 4)) is
when X"0" => msxor_ctdx <= "00" ;
when X"1" => msxor_ctdx <= "01" ;
when X"2" => msxor_ctdx <= "01" ;
when X"3" => msxor_ctdx <= "10" ;
when X"4" => msxor_ctdx <= "01" ;
when X"5" => msxor_ctdx <= "10" ;
when X"6" => msxor_ctdx <= "10" ;
when X"8" => msxor_ctdx <= "01" ;
when X"9" => msxor_ctdx <= "10" ;
when X"A" => msxor_ctdx <= "10" ;
when X"C" => msxor_ctdx <= "10" ;
when others => msxor_ctdx <= "11" ;
end case ;
end if ;
end process ;
msxor_ctiy <= ('0' & msxor_cti) + ('0' & msxor_ctix) ;
msxor_ctdy <= ('0' & msxor_ctd) + ('0' & msxor_ctdx) ;
process (clk) begin
if clk'event and clk = '1' then
if msxor_ctiy = msxor_ctdy then
action <= "00" ;
elsif msxor_ctiy > msxor_ctdy then
action <= "01" ;
else
action <= "10" ;
end if ;
end if ;
end process ;
process (clk) begin
if clk'event and clk = '1' then
mdataouta <= m_datain ;
mdataoutb <= mdataouta(S-1) ;
sdataouta <= s_datain ;
sdataoutb <= sdataouta(S-1) ;
end if ;
end process ;
process (clk) begin
if clk'event and clk = '1' then -- per bit delay shift state machine
if reset = '1' then
s_ovflw <= '0' ;
pdcount <= "100000" ;
m_delay_val_int <= c_delay_in ; -- initial master delay
s_delay_val_int <= "00000" ; -- initial slave delay
data_mux <= '0' ;
m_delay_mux <= "01" ;
s_delay_mux <= "01" ;
s_state <= "00000" ;
inc_run <= '0' ;
dec_run <= '0' ;
eye_run <= '0' ;
pd_hold <= "00000000" ;
s_delay_val_eye <= "00000" ;
else
case (m_delay_mux) is
when "00" => mdataoutc <= mdataouta(S-2 downto 0) & mdataoutb ;
when "10" => mdataoutc <= m_datain(0) & mdataouta(S-1 downto 1) ;
when others => mdataoutc <= mdataouta ;
end case ;
case (s_delay_mux) is
when "00" => sdataoutc <= sdataouta(S-2 downto 0) & sdataoutb ;
when "10" => sdataoutc <= s_datain(0) & sdataouta(S-1 downto 1) ;
when others => sdataoutc <= sdataouta ;
end case ;
if m_delay_val_int = bt_val then
meq_max <= '1' ;
else
meq_max <= '0' ;
end if ;
if m_delay_val_int = "00000" then
meq_min <= '1' ;
else
meq_min <= '0' ;
end if ;
if pdcount = "111111" and pd_max = '0' and delay_change = '0' then
pd_max <= '1' ;
else
pd_max <= '0' ;
end if ;
if pdcount = "000000" and pd_min = '0' and delay_change = '0' then
pd_min <= '1' ;
else
pd_min <= '0' ;
end if ;
if delay_change = '1' or inc_run = '1' or dec_run = '1' or eye_run = '1' then
pd_hold <= "11111111" ;
pdcount <= "100000" ;
elsif pd_hold(7) = '1' then
pdcount <= "100000" ;
pd_hold <= pd_hold(6 downto 0) & '0' ;
elsif action(0) = '1' and pdcount /= "111111" then -- increment filter count
pdcount <= pdcount + 1 ;
elsif action(1) = '1' and pdcount /= "000000" then -- decrement filter count
pdcount <= pdcount - 1 ;
end if ;
if ((enable_phase_detector = '1' and pd_max = '1' and delay_change = '0') or inc_run = '1') then -- increment delays, check for master delay = max
delay_change <= '1' ;
if meq_max = '0' and inc_run = '0' then
m_delay_val_int <= m_delay_val_int + 1 ;
else -- master is max
s_state(3 downto 0) <= s_state(3 downto 0) + 1 ;
case (s_state(3 downto 0)) is
when "0000" => inc_run <= '1' ; s_delay_val_int <= bt_val ; -- indicate state machine running and set slave delay to bit time
when "0110" => data_mux <= '1' ; m_delay_val_int <= "00000" ; -- change data mux over to forward slave data and set master delay to zero
when "1001" => m_delay_mux <= m_delay_mux - 1 ; -- change master delay mux over to forward with a 1-bit less advance
when "1110" => data_mux <= '0' ; -- change data mux over to forward master data
when "1111" => s_delay_mux <= m_delay_mux ; inc_run <= '0' ; -- change slave delay mux over to forward with a 1-bit less advance
when others => inc_run <= '1' ;
end case ;
end if ;
elsif ((enable_phase_detector = '1' and pd_min = '1' and delay_change = '0') or dec_run = '1') then -- decrement delays, check for master delay = 0
delay_change <= '1' ;
if meq_min = '0' and dec_run = '0' then
m_delay_val_int <= m_delay_val_int - 1 ;
else -- master is zero
s_state(3 downto 0) <= s_state(3 downto 0) + 1 ;
case (s_state(3 downto 0)) is
when "0000" => dec_run <= '1' ; s_delay_val_int <= "00000" ; -- indicate state machine running and set slave delay to zero
when "0110" => data_mux <= '1' ; m_delay_val_int <= bt_val ; -- change data mux over to forward slave data and set master delay to bit time
when "1001" => m_delay_mux <= m_delay_mux + 1 ; -- change master delay mux over to forward with a 1-bit more advance
when "1110" => data_mux <= '0' ; -- change data mux over to forward master data
when "1111" => s_delay_mux <= m_delay_mux ; dec_run <= '0' ; -- change slave delay mux over to forward with a 1-bit less advance
when others => dec_run <= '1' ;
end case ;
end if ;
elsif enable_monitor = '1' and (eye_run = '1' or delay_change = '1') then
delay_change <= '0' ;
s_state <= s_state + 1 ;
case (s_state) is
when "00000" => eye_run <= '1' ; s_delay_val_int <= s_delay_val_eye ; -- indicate state machine running and set slave delay to monitor value
when "10110" => if match = "11111111" then res_int <= res_int or shifter ; -- set or clear result bit
else res_int <= res_int and not shifter ; end if ;
if s_delay_val_eye = bt_val then -- only monitor active taps, ie as far as btval
shifter <= (0=>'1',others=>'0') ; s_delay_val_eye <= "00000" ;
else shifter <= shifter(30 downto 0) & shifter(31) ;
s_delay_val_eye <= s_delay_val_eye + 1 ; end if ;
eye_run <= '0' ; s_state <= "00000" ;
when others => eye_run <= '1' ;
end case ;
else
delay_change <= '0' ;
if (m_delay_val_int >= bt_val_d2) and del_mech = '0' then -- set slave delay to 1/2 bit period beyond or behind the master delay
s_delay_val_int <= m_delay_val_int - bt_val_d2 ;
s_ovflw <= '0' ;
else
s_delay_val_int <= m_delay_val_int + bt_val_d2 ; -- slave always ahead when del_mech is '1'
s_ovflw <= '1' ;
end if ;
end if ;
if enable_phase_detector = '0' and delay_change = '0' then
delay_change <= '1' ;
end if ;
end if ;
if enable_phase_detector = '1' then
if data_mux = '0' then
data_out <= mdataoutc ;
else
data_out <= sdataoutc ;
end if ;
else
data_out <= m_datain ;
end if ;
end if ;
end process ;
process (clk) begin
if clk'event and clk = '1' then
if mdataouta = sdataouta then
match <= match(6 downto 0) & '1' ;
else
match <= match(6 downto 0) & '0' ;
end if ;
end if ;
end process ;
m_delay_1hot <= X"00000001" when m_delay_val_int = "00000" else
X"00000002" when m_delay_val_int = "00001" else
X"00000004" when m_delay_val_int = "00010" else
X"00000008" when m_delay_val_int = "00011" else
X"00000010" when m_delay_val_int = "00100" else
X"00000020" when m_delay_val_int = "00101" else
X"00000040" when m_delay_val_int = "00110" else
X"00000080" when m_delay_val_int = "00111" else
X"00000100" when m_delay_val_int = "01000" else
X"00000200" when m_delay_val_int = "01001" else
X"00000400" when m_delay_val_int = "01010" else
X"00000800" when m_delay_val_int = "01011" else
X"00001000" when m_delay_val_int = "01100" else
X"00002000" when m_delay_val_int = "01101" else
X"00004000" when m_delay_val_int = "01110" else
X"00008000" when m_delay_val_int = "01111" else
X"00010000" when m_delay_val_int = "10000" else
X"00020000" when m_delay_val_int = "10001" else
X"00040000" when m_delay_val_int = "10010" else
X"00080000" when m_delay_val_int = "10011" else
X"00100000" when m_delay_val_int = "10100" else
X"00200000" when m_delay_val_int = "10101" else
X"00400000" when m_delay_val_int = "10110" else
X"00800000" when m_delay_val_int = "10111" else
X"01000000" when m_delay_val_int = "11000" else
X"02000000" when m_delay_val_int = "11001" else
X"04000000" when m_delay_val_int = "11010" else
X"08000000" when m_delay_val_int = "11011" else
X"10000000" when m_delay_val_int = "11100" else
X"20000000" when m_delay_val_int = "11101" else
X"40000000" when m_delay_val_int = "11110" else
X"80000000" ;
end arch_delay_controller_wrap ;
| gpl-3.0 | 90875b5aaaf911d87e1f503f7e80bcfb | 0.58433 | 2.889574 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/ddr3-core/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd | 10 | 90,302 | --*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
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-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for MCB Soft
-- Calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 2/09/09: moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working
-- correctly)
-- 1.2: 2/12/09: Many other changes.
-- 1.3: 2/26/09: Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within
-- STATE
-- 1.4: 3/02/09: Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.Also added reg declaration for PREVIOUS_STATE
-- 1.5: 3/16/09: Added pll_lock port, and using it to gate reset. Changing RST (except input port) to RST_reg and gating it with pll_lock.
-- 1.6: 6/05/09: Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.
-- 1.7: 6/24/09: Gave RZQ and ZIO each their own unique ADD and SDI nets
-- 2.6: 12/15/09: Changed STATE from 7-bit to 6-bit. Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to
-- RST_DELAY.
-- Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least
-- 16 clocks. Added PNSKEW option.
-- 2.7: 12/23/09: Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.
-- 2.8: 01/14/10: Added functionality to allow for SUSPEND. Changed MCB_SYSRST port from wire to reg.
-- 2.9: 02/01/10: More changes to SUSPEND and Reset logic to handle SUSPEND properly. Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced
-- with 8bit TARGET_DQS_DELAY which
-- will track most recnet Max_Value. Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_DELAY into DQS_DELAY_INITIAL.
-- Changed DQS_COUNT* to DQS_DELAY*.
-- Changed MCB_SYSRST port back to wire (from reg).
-- 3.0: 02/10/10: Added count_inc and count_dec to add few (4) UI_CLK cycles latency to the INC and DEC signals(to deal with latency on UOREFRSHFLAG)
-- 3.1: 02/23/10: Registered the DONE_SOFTANDHARD_CAL for timing.
-- 3.2: 02/28/10: Corrected the WAIT_SELFREFRESH_EXIT_DQS_CAL logic;
-- 3.3: 03/02/10: Changed PNSKEW to default on (1'b1)
-- 3.4: 03/04/10: Recoded the RST_Reg logic.
-- 3.5: 03/05/10: Changed Result register to be 16-bits. Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)
-- 3.6 03/10/10: Improvements to Reset logic.
-- 3.7: 04/26/10: Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .
-- 3.8: 05/05/10: Added fixes for the CR# 559092 (updated Mult_Divide function) and 555416 (added IOB attribute to DONE_SOFTANDHARD_CAL).
-- 3.9: 05/24/10: Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.
-- 3.10 10/22/10: Fixed PERFORM_START_DYN_CAL_AFTER_SELFREFRESH logic.
-- 3.11 2/14/11: Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic ;
MCB_UIDQLOWERINC : out std_logic ;
MCB_UIDQUPPERDEC : out std_logic ;
MCB_UIDQUPPERINC : out std_logic ;
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic ; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end entity mcb_soft_calibration;
architecture trans of mcb_soft_calibration is
constant IOI_DQ0 : std_logic_vector(4 downto 0) := ("0000" & '1');
constant IOI_DQ1 : std_logic_vector(4 downto 0) := ("0000" & '0');
constant IOI_DQ2 : std_logic_vector(4 downto 0) := ("0001" & '1');
constant IOI_DQ3 : std_logic_vector(4 downto 0) := ("0001" & '0');
constant IOI_DQ4 : std_logic_vector(4 downto 0) := ("0010" & '1');
constant IOI_DQ5 : std_logic_vector(4 downto 0) := ("0010" & '0');
constant IOI_DQ6 : std_logic_vector(4 downto 0) := ("0011" & '1');
constant IOI_DQ7 : std_logic_vector(4 downto 0) := ("0011" & '0');
constant IOI_DQ8 : std_logic_vector(4 downto 0) := ("0100" & '1');
constant IOI_DQ9 : std_logic_vector(4 downto 0) := ("0100" & '0');
constant IOI_DQ10 : std_logic_vector(4 downto 0) := ("0101" & '1');
constant IOI_DQ11 : std_logic_vector(4 downto 0) := ("0101" & '0');
constant IOI_DQ12 : std_logic_vector(4 downto 0) := ("0110" & '1');
constant IOI_DQ13 : std_logic_vector(4 downto 0) := ("0110" & '0');
constant IOI_DQ14 : std_logic_vector(4 downto 0) := ("0111" & '1');
constant IOI_DQ15 : std_logic_vector(4 downto 0) := ("0111" & '0');
constant IOI_UDM : std_logic_vector(4 downto 0) := ("1000" & '1');
constant IOI_LDM : std_logic_vector(4 downto 0) := ("1000" & '0');
constant IOI_CK_P : std_logic_vector(4 downto 0) := ("1001" & '1');
constant IOI_CK_N : std_logic_vector(4 downto 0) := ("1001" & '0');
constant IOI_RESET : std_logic_vector(4 downto 0) := ("1010" & '1');
constant IOI_A11 : std_logic_vector(4 downto 0) := ("1010" & '0');
constant IOI_WE : std_logic_vector(4 downto 0) := ("1011" & '1');
constant IOI_BA2 : std_logic_vector(4 downto 0) := ("1011" & '0');
constant IOI_BA0 : std_logic_vector(4 downto 0) := ("1100" & '1');
constant IOI_BA1 : std_logic_vector(4 downto 0) := ("1100" & '0');
constant IOI_RASN : std_logic_vector(4 downto 0) := ("1101" & '1');
constant IOI_CASN : std_logic_vector(4 downto 0) := ("1101" & '0');
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := ("1110" & '1');
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := ("1110" & '0');
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := ("1111" & '1');
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := ("1111" & '0');
constant START : std_logic_vector(5 downto 0) := "000000";
constant LOAD_RZQ_NTERM : std_logic_vector(5 downto 0) := "000001";
constant WAIT1 : std_logic_vector(5 downto 0) := "000010";
constant LOAD_RZQ_PTERM : std_logic_vector(5 downto 0) := "000011";
constant WAIT2 : std_logic_vector(5 downto 0) := "000100";
constant INC_PTERM : std_logic_vector(5 downto 0) := "000101";
constant MULTIPLY_DIVIDE : std_logic_vector(5 downto 0) := "000110";
constant LOAD_ZIO_PTERM : std_logic_vector(5 downto 0) := "000111";
constant WAIT3 : std_logic_vector(5 downto 0) := "001000";
constant LOAD_ZIO_NTERM : std_logic_vector(5 downto 0) := "001001";
constant WAIT4 : std_logic_vector(5 downto 0) := "001010";
constant INC_NTERM : std_logic_vector(5 downto 0) := "001011";
constant SKEW : std_logic_vector(5 downto 0) := "001100";
constant WAIT_FOR_START_BROADCAST : std_logic_vector(5 downto 0) := "001101";
constant BROADCAST_PTERM : std_logic_vector(5 downto 0) := "001110";
constant WAIT5 : std_logic_vector(5 downto 0) := "001111";
constant BROADCAST_NTERM : std_logic_vector(5 downto 0) := "010000";
constant WAIT6 : std_logic_vector(5 downto 0) := "010001";
constant LDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010010";
constant LDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010011";
constant LDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "010100";
constant LDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "010101";
constant LDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "010110";
constant LDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "010111";
constant LDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011000";
constant LDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011001";
constant UDQS_CLK_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011010";
constant UDQS_CLK_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011011";
constant UDQS_CLK_WRITE_N_TERM : std_logic_vector(5 downto 0) := "011100";
constant UDQS_CLK_N_TERM_WAIT : std_logic_vector(5 downto 0) := "011101";
constant UDQS_PIN_WRITE_P_TERM : std_logic_vector(5 downto 0) := "011110";
constant UDQS_PIN_P_TERM_WAIT : std_logic_vector(5 downto 0) := "011111";
constant UDQS_PIN_WRITE_N_TERM : std_logic_vector(5 downto 0) := "100000";
constant UDQS_PIN_N_TERM_WAIT : std_logic_vector(5 downto 0) := "100001";
constant OFF_RZQ_PTERM : std_logic_vector(5 downto 0) := "100010";
constant WAIT7 : std_logic_vector(5 downto 0) := "100011";
constant OFF_ZIO_NTERM : std_logic_vector(5 downto 0) := "100100";
constant WAIT8 : std_logic_vector(5 downto 0) := "100101";
constant RST_DELAY : std_logic_vector(5 downto 0) := "100110";
constant START_DYN_CAL_PRE : std_logic_vector(5 downto 0) := "100111";
constant WAIT_FOR_UODONE : std_logic_vector(5 downto 0) := "101000";
constant LDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101001";
constant LDQS_WAIT1 : std_logic_vector(5 downto 0) := "101010";
constant LDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101011";
constant LDQS_WAIT2 : std_logic_vector(5 downto 0) := "101100";
constant UDQS_WRITE_POS_INDELAY : std_logic_vector(5 downto 0) := "101101";
constant UDQS_WAIT1 : std_logic_vector(5 downto 0) := "101110";
constant UDQS_WRITE_NEG_INDELAY : std_logic_vector(5 downto 0) := "101111";
constant UDQS_WAIT2 : std_logic_vector(5 downto 0) := "110000";
constant START_DYN_CAL : std_logic_vector(5 downto 0) := "110001";
constant WRITE_CALIBRATE : std_logic_vector(5 downto 0) := "110010";
constant WAIT9 : std_logic_vector(5 downto 0) := "110011";
constant READ_MAX_VALUE : std_logic_vector(5 downto 0) := "110100";
constant WAIT10 : std_logic_vector(5 downto 0) := "110101";
constant ANALYZE_MAX_VALUE : std_logic_vector(5 downto 0) := "110110";
constant FIRST_DYN_CAL : std_logic_vector(5 downto 0) := "110111";
constant INCREMENT : std_logic_vector(5 downto 0) := "111000";
constant DECREMENT : std_logic_vector(5 downto 0) := "111001";
constant DONE : std_logic_vector(5 downto 0) := "111010";
--constant INCREMENT_TA : std_logic_vector(5 downto 0) := "111011";
constant RZQ : std_logic_vector(1 downto 0) := "00";
constant ZIO : std_logic_vector(1 downto 0) := "01";
constant MCB_PORT : std_logic_vector(1 downto 0) := "11";
constant WRITE_MODE : std_logic := '0';
constant READ_MODE : std_logic := '1';
-- IOI Registers
constant NoOp : std_logic_vector(7 downto 0) := "00000000";
constant DelayControl : std_logic_vector(7 downto 0) := "00000001";
constant PosEdgeInDly : std_logic_vector(7 downto 0) := "00000010";
constant NegEdgeInDly : std_logic_vector(7 downto 0) := "00000011";
constant PosEdgeOutDly : std_logic_vector(7 downto 0) := "00000100";
constant NegEdgeOutDly : std_logic_vector(7 downto 0) := "00000101";
constant MiscCtl1 : std_logic_vector(7 downto 0) := "00000110";
constant MiscCtl2 : std_logic_vector(7 downto 0) := "00000111";
constant MaxValue : std_logic_vector(7 downto 0) := "00001000";
-- IOB Registers
constant PDrive : std_logic_vector(7 downto 0) := "10000000";
constant PTerm : std_logic_vector(7 downto 0) := "10000001";
constant NDrive : std_logic_vector(7 downto 0) := "10000010";
constant NTerm : std_logic_vector(7 downto 0) := "10000011";
constant SlewRateCtl : std_logic_vector(7 downto 0) := "10000100";
constant LVDSControl : std_logic_vector(7 downto 0) := "10000101";
constant MiscControl : std_logic_vector(7 downto 0) := "10000110";
constant InputControl : std_logic_vector(7 downto 0) := "10000111";
constant TestReadback : std_logic_vector(7 downto 0) := "10001000";
-- No multi/divide is required when a 55 ohm resister is used on RZQ
-- localparam MULT = 1;
-- localparam DIV = 1;
-- use 7/4 scaling factor when the 100 ohm RZQ is used
constant MULT : integer := 7;
constant DIV : integer := 4;
constant PNSKEW : std_logic := '1'; -- Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required
constant PNSKEWDQS : std_logic := '1';
constant MULT_S : integer := 9;
constant DIV_S : integer := 8;
constant MULT_W : integer := 7;
constant DIV_W : integer := 8;
constant DQS_NUMERATOR : integer := 3;
constant DQS_DENOMINATOR : integer := 8;
constant INCDEC_THRESHOLD : std_logic_vector(7 downto 0) := X"03";
-- parameter for the threshold which triggers an inc/dec to occur. 2 for half, 4 for quarter,
-- 3 for three eighths
constant RST_CNT : std_logic_vector(9 downto 0) := "0000010000";
constant TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := C_MEM_TZQINIT_MAXCNT + RST_CNT;
constant IN_TERM_PASS : std_logic := '0';
constant DYN_CAL_PASS : std_logic := '1';
component iodrp_mcb_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end component;
component iodrp_controller is
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end component;
signal P_Term : std_logic_vector(5 downto 0) := "000000";
signal N_Term : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_s : std_logic_vector(5 downto 0) := "000000";
signal N_Term_s : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_w : std_logic_vector(5 downto 0) := "000000";
signal N_Term_w : std_logic_vector(6 downto 0) := "0000000";
signal P_Term_Prev : std_logic_vector(5 downto 0) := "000000";
signal N_Term_Prev : std_logic_vector(6 downto 0) := "0000000";
signal STATE : std_logic_vector(5 downto 0);
signal IODRPCTRLR_MEMCELL_ADDR : std_logic_vector(7 downto 0);
signal IODRPCTRLR_WRITE_DATA : std_logic_vector(7 downto 0);
signal Active_IODRP : std_logic_vector(1 downto 0);
signal IODRPCTRLR_R_WB : std_logic := '0';
signal IODRPCTRLR_CMD_VALID : std_logic := '0';
signal IODRPCTRLR_USE_BKST : std_logic := '0';
signal MCB_CMD_VALID : std_logic := '0';
signal MCB_USE_BKST : std_logic := '0';
signal Pre_SYSRST : std_logic := '1'; -- internally generated reset which will OR with RST input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
signal IODRP_SDO : std_logic;
signal Max_Value_Previous : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(5 downto 0) := "000000"; -- counter for adding 18 extra clock cycles after setting Calibrate bit
signal counter_en : std_logic := '0'; -- counter enable for "count"
signal First_Dyn_Cal_Done : std_logic := '0'; -- flag - high after the very first dynamic calibration is done
signal START_BROADCAST : std_logic ; -- Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance -
-- state machine will wait for this to be high
signal DQS_DELAY_INITIAL : std_logic_vector(7 downto 0) := "00000000";
signal DQS_DELAY : std_logic_vector(7 downto 0); -- contains the latest values written to LDQS and UDQS Input Delays
signal TARGET_DQS_DELAY : std_logic_vector(7 downto 0); -- used to track the target for DQS input delays - only gets updated if
-- the Max Value changes by more than the threshold
signal counter_inc : std_logic_vector(7 downto 0); -- used to delay Inc signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal counter_dec : std_logic_vector(7 downto 0); -- used to delay Dec signal by several ui_clk cycles (to deal with
-- latency on UOREFRSHFLAG)
signal IODRPCTRLR_READ_DATA : std_logic_vector(7 downto 0);
signal IODRPCTRLR_RDY_BUSY_N : std_logic;
signal IODRP_CS : std_logic;
signal MCB_READ_DATA : std_logic_vector(7 downto 0);
signal RST_reg : std_logic;
signal Block_Reset : std_logic;
signal MCB_UODATAVALID_U : std_logic;
signal Inc_Dec_REFRSH_Flag : std_logic_vector(2 downto 0); -- 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place
signal Max_Value_Delta_Up : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone up from previous Max Value read
signal Half_MV_DU : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Up
signal Max_Value_Delta_Dn : std_logic_vector(7 downto 0); -- tracks amount latest Max Value has gone down from previous Max Value read
signal Half_MV_DD : std_logic_vector(7 downto 0); -- half of Max_Value_Delta_Dn
signal RstCounter : std_logic_vector(9 downto 0) := (others => '0');
signal rst_tmp : std_logic;
signal LastPass_DynCal : std_logic;
signal First_In_Term_Done : std_logic;
signal Inc_Flag : std_logic; -- flag to increment Dynamic Delay
signal Dec_Flag : std_logic; -- flag to decrement Dynamic Delay
signal CALMODE_EQ_CALIBRATION : std_logic; -- will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE
-- parameter = "CALIBRATION"
signal DQS_DELAY_LOWER_LIMIT : std_logic_vector(7 downto 0); -- Lower limit for DQS input delays
signal DQS_DELAY_UPPER_LIMIT : std_logic_vector(7 downto 0); -- Upper limit for DQS input delays
signal SKIP_DYN_IN_TERMINATION : std_logic; -- wire to allow skipping dynamic input termination if either the
-- one-time or dynamic parameters are 1
signal SKIP_DYNAMIC_DQS_CAL : std_logic; -- wire allowing skipping dynamic DQS delay calibration if either
-- SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
signal Quarter_Max_Value : std_logic_vector(7 downto 0);
signal Half_Max_Value : std_logic_vector(7 downto 0);
signal PLL_LOCK_R1 : std_logic;
signal PLL_LOCK_R2 : std_logic;
signal MCB_RDY_BUSY_N : std_logic;
signal SELFREFRESH_REQ_R1 : std_logic;
signal SELFREFRESH_REQ_R2 : std_logic;
signal SELFREFRESH_REQ_R3 : std_logic;
signal SELFREFRESH_MCB_MODE_R1 : std_logic;
signal SELFREFRESH_MCB_MODE_R2 : std_logic;
signal SELFREFRESH_MCB_MODE_R3 : std_logic;
signal WAIT_SELFREFRESH_EXIT_DQS_CAL : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH : std_logic;
signal START_DYN_CAL_STATE_R1 : std_logic;
signal PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 : std_logic;
-- Declare intermediate signals for referenced outputs
signal IODRP_ADD_xilinx0 : std_logic;
signal IODRP_SDI_xilinx1 : std_logic;
signal MCB_UIADD_xilinx2 : std_logic;
signal MCB_UISDI_xilinx11 : std_logic;
signal MCB_UICS_xilinx6 : std_logic;
signal MCB_UIBROADCAST_xilinx4 : std_logic;
signal MCB_UIADDR_int : std_logic_vector(4 downto 0);
signal MCB_UIDONECAL_xilinx7 : std_logic;
signal MCB_UIREAD_xilinx10 : std_logic;
signal SELFREFRESH_MODE_xilinx11 : std_logic;
signal Max_Value_int : std_logic_vector(7 downto 0);
signal Rst_condition1 : std_logic;
--signal Rst_condition2 : std_logic;
signal non_violating_rst : std_logic;
signal WAIT_200us_COUNTER : std_logic_vector(15 downto 0);
signal WaitTimer : std_logic_vector(7 downto 0);
signal WarmEnough : std_logic;
signal WaitCountEnable : std_logic;
signal State_Start_DynCal_R1 : std_logic;
signal State_Start_DynCal : std_logic;
-- This function multiplies by a constant MULT and then divides by the DIV constant
function Mult_Divide (Input : std_logic_vector(7 downto 0); MULT : integer ; DIV : integer ) return std_logic_vector is
variable Result : integer := 0;
variable temp : std_logic_vector(14 downto 0) := "000000000000000";
begin
for count in 0 to (MULT-1) loop
temp := temp + ("0000000" & Input);
end loop;
Result := (to_integer(unsigned(temp))) / (DIV);
temp := std_logic_vector(to_unsigned(Result,15));
return temp(7 downto 0);
end function Mult_Divide;
attribute syn_preserve : boolean;
attribute syn_preserve of P_Term : signal is TRUE;
attribute syn_preserve of N_Term : signal is TRUE;
attribute syn_preserve of P_Term_s : signal is TRUE;
attribute syn_preserve of N_Term_s : signal is TRUE;
attribute syn_preserve of P_Term_w : signal is TRUE;
attribute syn_preserve of N_Term_w : signal is TRUE;
attribute syn_preserve of P_Term_Prev : signal is TRUE;
attribute syn_preserve of N_Term_Prev : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_MEMCELL_ADDR : signal is TRUE;
attribute syn_preserve of IODRPCTRLR_WRITE_DATA : signal is TRUE;
attribute syn_preserve of Max_Value_Previous : signal is TRUE;
attribute syn_preserve of DQS_DELAY_INITIAL : signal is TRUE;
attribute iob : string;
attribute iob of DONE_SOFTANDHARD_CAL : signal is "FALSE";
begin
-- move the default assignment here to make FORMALITY happy.
START_BROADCAST <= '1';
MCB_RECAL <= '0';
MCB_UIDQLOWERDEC <= '0';
MCB_UIADDR <= MCB_UIADDR_int;
MCB_UIDQLOWERINC <= '0';
MCB_UIDQUPPERDEC <= '0';
MCB_UIDQUPPERINC <= '0';
Max_Value <= Max_Value_int;
-- Drive referenced outputs
IODRP_ADD <= IODRP_ADD_xilinx0;
IODRP_SDI <= IODRP_SDI_xilinx1;
MCB_UIADD <= MCB_UIADD_xilinx2;
MCB_UISDI <= MCB_UISDI_xilinx11;
MCB_UICS <= MCB_UICS_xilinx6;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx4;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx7;
MCB_UIREAD <= MCB_UIREAD_xilinx10;
SELFREFRESH_MODE <= SELFREFRESH_MODE_xilinx11;
Inc_Dec_REFRSH_Flag <= (Inc_Flag & Dec_Flag & MCB_UOREFRSHFLAG);
Max_Value_Delta_Up <= Max_Value_int - Max_Value_Previous;
Half_MV_DU <= ('0' & Max_Value_Delta_Up(7 downto 1));
Max_Value_Delta_Dn <= Max_Value_Previous - Max_Value_int;
Half_MV_DD <= ('0' & Max_Value_Delta_Dn(7 downto 1));
CALMODE_EQ_CALIBRATION <= '1' when (C_MC_CALIBRATION_MODE = "CALIBRATION") else '0'; -- will calculate and set the DQS input delays if = 1'b1
Half_Max_Value <= ('0' & Max_Value_int(7 downto 1));
Quarter_Max_Value <= ("00" & Max_Value_int(7 downto 2));
DQS_DELAY_LOWER_LIMIT <= Quarter_Max_Value; -- limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here
DQS_DELAY_UPPER_LIMIT <= Half_Max_Value; -- limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here
SKIP_DYN_IN_TERMINATION <= '1' when ((SKIP_DYN_IN_TERM = 1) or (SKIP_IN_TERM_CAL = 1)) else '0';
-- skip dynamic input termination if either the one-time or dynamic parameters are 1
SKIP_DYNAMIC_DQS_CAL <= '1' when ((CALMODE_EQ_CALIBRATION = '0') or (SKIP_DYNAMIC_CAL = 1)) else '0';
-- skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if ((DQS_DELAY_INITIAL /= X"00") or (STATE = DONE)) then
DONE_SOFTANDHARD_CAL <= MCB_UODONECAL; -- high when either DQS input delays initialized, or STATE=DONE and UODONECAL high
else
DONE_SOFTANDHARD_CAL <= '0';
end if;
end if;
end process;
iodrp_controller_inst : iodrp_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => IODRPCTRLR_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => IODRPCTRLR_CMD_VALID,
rdy_busy_n => IODRPCTRLR_RDY_BUSY_N,
use_broadcast => '0',
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => IODRP_CS,
DRP_SDI => IODRP_SDI_xilinx1,
DRP_ADD => IODRP_ADD_xilinx0,
DRP_SDO => IODRP_SDO,
DRP_BKST => open
);
iodrp_mcb_controller_inst : iodrp_mcb_controller
port map (
memcell_address => IODRPCTRLR_MEMCELL_ADDR,
write_data => IODRPCTRLR_WRITE_DATA,
read_data => MCB_READ_DATA,
rd_not_write => IODRPCTRLR_R_WB,
cmd_valid => MCB_CMD_VALID,
rdy_busy_n => MCB_RDY_BUSY_N,
use_broadcast => MCB_USE_BKST,
drp_ioi_addr => MCB_UIADDR_int,
sync_rst => RST_reg,
DRP_CLK => UI_CLK,
DRP_CS => MCB_UICS_xilinx6,
DRP_SDI => MCB_UISDI_xilinx11,
DRP_ADD => MCB_UIADD_xilinx2,
DRP_BKST => MCB_UIBROADCAST_xilinx4,
DRP_SDO => MCB_UOSDO,
MCB_UIREAD => MCB_UIREAD_xilinx10
);
process (UI_CLK, RST) begin
if (RST = '1') then
if (C_SIMULATION = "TRUE") then
WAIT_200us_COUNTER <= X"7FF0";
else
WAIT_200us_COUNTER <= (others => '0');
end if;
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '1') then
WAIT_200us_COUNTER <= WAIT_200us_COUNTER;
else
WAIT_200us_COUNTER <= WAIT_200us_COUNTER + '1';
end if;
end if;
end process;
-- init_sequence_skip: if (C_SIMULATION = "TRUE") generate
-- WAIT_200us_COUNTER <= X"FFFF";
-- process
-- begin
-- report "The 200 us wait period required before CKE goes active has been skipped in Simulation";
-- wait;
-- end process;
-- end generate;
gen_CKE_Train_a: if (C_MEM_TYPE = "DDR2") generate
process (UI_CLK, RST) begin
if (RST = '1') then
CKE_Train <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
if (STATE = WAIT_FOR_UODONE and MCB_UODONECAL = '1') then
CKE_Train <= '0';
elsif (WAIT_200us_COUNTER(15) = '1' and MCB_UODONECAL = '0') then
CKE_Train <= '1';
else
CKE_Train <= '0';
end if;
end if;
end process;
end generate ;
gen_CKE_Train_b: if (not(C_MEM_TYPE = "DDR2")) generate
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
CKE_Train <= '0';
end if;
end process;
end generate ;
--********************************************
-- PLL_LOCK and RST signals
--********************************************
--MCB_SYSRST <= Pre_SYSRST or RST_reg; -- Pre_SYSRST is generated from the STATE state machine, and is OR'd with RST_reg input to drive MCB's
-- SYSRST pin (MCB_SYSRST)
rst_tmp <= not(SELFREFRESH_MODE_xilinx11) and not(PLL_LOCK_R2); -- rst_tmp becomes 1 if you lose Lock and the device is not in SUSPEND
process (UI_CLK, RST) begin
if (RST = '1') then
--Block_Reset <= '0';
--RstCounter <= (others => '0');
--elsif (UI_CLK'event and UI_CLK = '1') then
-- if (rst_tmp = '1') then -- this is to deal with not allowing the user-reset "RST" to violate TZQINIT_MAXCNT (min time between resets to DDR3)
Block_Reset <= '0';
RstCounter <= (others => '0');
elsif (UI_CLK'event and UI_CLK = '1') then
Block_Reset <= '0'; -- default to allow STATE to move out of RST_DELAY state
if (Pre_SYSRST = '1') then
RstCounter <= RST_CNT; -- whenever STATE wants to reset the MCB, set RstCounter to h10
else
if (RstCounter < TZQINIT_MAXCNT) then -- if RstCounter is less than d512 than this will execute
Block_Reset <= '1'; -- STATE won't exit RST_DELAY state
RstCounter <= RstCounter + "1"; -- and Rst_Counter increments
end if;
end if;
end if;
--end if;
end process;
-- Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT
non_violating_rst <= RST and Rst_condition1;
MCB_SYSRST <= Pre_SYSRST;
process (UI_CLK) begin
if (UI_CLK'event and UI_CLK = '1') then
if (RstCounter >= TZQINIT_MAXCNT) then
Rst_condition1 <= '1';
else
Rst_condition1 <= '0';
end if;
end if;
end process;
-- -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)
-- -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization process.
-- -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which
-- is gated by pll's lock signal. When the PLL locks again, the RST_reg stays asserted for at least 200 us which
-- will cause MCB to reset and reinitialize the memory afterwards.
-- -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at
-- its terminal count. The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module
-- The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration
-- state machine will not reset during SUSPEND.
-- -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to
-- Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST.
-- It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT
-- termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.
--process (UI_CLK) begin
-- if (UI_CLK'event and UI_CLK = '1') then
--
-- if (RstCounter < RST_CNT) then
-- Rst_condition2 <= '1';
-- else
-- Rst_condition2 <= '0';
-- end if;
-- end if;
--end process;
process (UI_CLK, non_violating_rst) begin
if (non_violating_rst = '1') then
RST_reg <= '1'; -- STATE and MCB_SYSRST will both be reset if you lose lock when the device is not in SUSPEND
elsif (UI_CLK'event and UI_CLK = '1') then
if (WAIT_200us_COUNTER(15) = '0') then
RST_reg <= '1';
else
--RST_reg <= Rst_condition2 or rst_tmp; -- insures RST_reg is at least h10 pulses long
RST_reg <= rst_tmp; -- insures RST_reg is at least h10 pulses long
end if;
end if;
end process;
--********************************************
-- SUSPEND Logic
--********************************************
process (UI_CLK,RST)
begin
if (RST = '1') then
SELFREFRESH_MCB_MODE_R1 <= '0';
SELFREFRESH_MCB_MODE_R2 <= '0';
SELFREFRESH_MCB_MODE_R3 <= '0';
SELFREFRESH_REQ_R1 <= '0';
SELFREFRESH_REQ_R2 <= '0';
SELFREFRESH_REQ_R3 <= '0';
PLL_LOCK_R1 <= '0';
PLL_LOCK_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
-- SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180
SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;
SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;
SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;
-- SELFREFRESH_REQ is clocked by user's application clock
SELFREFRESH_REQ_R1 <= SELFREFRESH_REQ;
SELFREFRESH_REQ_R2 <= SELFREFRESH_REQ_R1;
SELFREFRESH_REQ_R3 <= SELFREFRESH_REQ_R2;
PLL_LOCK_R1 <= PLL_LOCK;
PLL_LOCK_R2 <= PLL_LOCK_R1;
end if;
end process;
-- SELFREFRESH should only be deasserted after PLL_LOCK is asserted.
-- This is to make sure MCB get a locked sys_2x_clk before exiting
-- SELFREFRESH mode.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MCB_REQ <= '0';
elsif ((PLL_LOCK_R2 = '1') and (SELFREFRESH_REQ_R3 = '0') and (STATE = START_DYN_CAL)) then
SELFREFRESH_MCB_REQ <= '0';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_REQ_R3 = '1')) then
SELFREFRESH_MCB_REQ <= '1';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
elsif ((SELFREFRESH_MCB_MODE_R2 = '1') and (SELFREFRESH_MCB_MODE_R3 = '0')) then
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '1';
elsif ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (SELFREFRESH_REQ_R3 = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '1')) then
-- START_DYN_CAL is next state
WAIT_SELFREFRESH_EXIT_DQS_CAL <= '0';
end if;
end if;
end process;
-- Need to detect when SM entering START_DYN_CAL
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
START_DYN_CAL_STATE_R1 <= '0';
else
-- register PERFORM_START_DYN_CAL_AFTER_SELFREFRESH to detect end of cycle
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 <= PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;
if (STATE = START_DYN_CAL) then
START_DYN_CAL_STATE_R1 <= '1';
else
START_DYN_CAL_STATE_R1 <= '0';
end if;
if ((WAIT_SELFREFRESH_EXIT_DQS_CAL = '1') and (STATE /= START_DYN_CAL) and (START_DYN_CAL_STATE_R1 = '1')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '1';
elsif ((STATE = START_DYN_CAL) and (SELFREFRESH_MCB_MODE_R3 = '0')) then
PERFORM_START_DYN_CAL_AFTER_SELFREFRESH <= '0';
end if;
end if;
end if;
end process;
-- SELFREFRESH_MCB_MODE deasserted status is hold off
-- until Soft_Calib has at least done one loop of DQS update.
-- New logic WarmeEnough is added to make sure PLL_Lock is lockec and all IOs stable before
-- deassert the status of MCB's SELFREFRESH_MODE. This is to ensure all IOs are stable before
-- user logic sending new commands to MCB.
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
elsif (SELFREFRESH_MCB_MODE_R2 = '1') then
SELFREFRESH_MODE_xilinx11 <= '1';
elsif (WarmEnough = '1') then
SELFREFRESH_MODE_xilinx11 <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitCountEnable <= '0';
elsif (SELFREFRESH_REQ_R2 = '0' and SELFREFRESH_REQ_R1 = '1') then
WaitCountEnable <= '0';
elsif ((PERFORM_START_DYN_CAL_AFTER_SELFREFRESH = '0') and (PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1 = '1')) then
WaitCountEnable <= '1';
else
WaitCountEnable <= WaitCountEnable;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal <= '0';
elsif (STATE = START_DYN_CAL) then
State_Start_DynCal <= '1';
else
State_Start_DynCal <= '0';
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
State_Start_DynCal_R1 <= '0';
else
State_Start_DynCal_R1 <= State_Start_DynCal;
end if;
end if;
end process;
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST = '1') then
WaitTimer <= (others => '0');
WarmEnough <= '1';
elsif ((SELFREFRESH_REQ_R2 = '0') and (SELFREFRESH_REQ_R1 = '1')) then
WaitTimer <= (others => '0');
WarmEnough <= '0';
elsif (WaitTimer = X"04") then
WaitTimer <= WaitTimer ;
WarmEnough <= '1';
elsif (WaitCountEnable = '1') then
WaitTimer <= WaitTimer + '1';
else
WaitTimer <= WaitTimer ;
end if;
end if;
end process;
--********************************************
--Comparitor for Dynamic Calibration circuit
--********************************************
Dec_Flag <= '1' when (TARGET_DQS_DELAY < DQS_DELAY) else '0';
Inc_Flag <= '1' when (TARGET_DQS_DELAY > DQS_DELAY) else '0';
--*********************************************************************************************
--Counter for extra clock cycles injected after setting Calibrate bit in IODRP2 for Dynamic Cal
--*********************************************************************************************
process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then
count <= "000000";
elsif (counter_en = '1') then
count <= count + "000001";
else
count <= "000000";
end if;
end if;
end process;
--*********************************************************************************************
-- Capture narrow MCB_UODATAVALID pulse - only one sysclk90 cycle wide
--*********************************************************************************************
process (UI_CLK, MCB_UODATAVALID)
begin
if(MCB_UODATAVALID = '1') then
MCB_UODATAVALID_U <= '1';
elsif(UI_CLK'event and UI_CLK = '1') then
MCB_UODATAVALID_U <= MCB_UODATAVALID;
end if;
end process;
--**************************************************************************************************************
--Always block to mux SDI, SDO, CS, and ADD depending on which IODRP is active: RZQ, ZIO or MCB's UI port (to IODRP2_MCBs)
--**************************************************************************************************************
process (Active_IODRP, IODRP_CS, RZQ_IODRP_SDO, ZIO_IODRP_SDO)
begin
case Active_IODRP is
when RZQ =>
RZQ_IODRP_CS <= IODRP_CS;
ZIO_IODRP_CS <= '0';
IODRP_SDO <= RZQ_IODRP_SDO;
when ZIO =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= IODRP_CS;
IODRP_SDO <= ZIO_IODRP_SDO;
when MCB_PORT =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
when others =>
RZQ_IODRP_CS <= '0';
ZIO_IODRP_CS <= '0';
IODRP_SDO <= '0';
end case;
end process;
--******************************************************************
--State Machine's Always block / Case statement for Next State Logic
--
--The WAIT1,2,etc states were required after every state where the
--DRP controller was used to do a write to the IODRPs - this is because
--there's a clock cycle latency on IODRPCTRLR_RDY_BUSY_N whenever the DRP controller
--sees IODRPCTRLR_CMD_VALID go high. OFF_RZQ_PTERM and OFF_ZIO_NTERM were added
--soley for the purpose of reducing power, particularly on RZQ as
--that pin is expected to have a permanent external resistor to gnd.
--******************************************************************
NEXT_STATE_LOGIC: process (UI_CLK)
begin
if (UI_CLK'event and UI_CLK = '1') then
if (RST_reg = '1') then -- Synchronous reset
MCB_CMD_VALID <= '0';
MCB_UIADDR_int <= "00000"; -- take control of UI/UO port
MCB_UICMDEN <= '1'; -- tells MCB that it is in Soft Cal.
MCB_UIDONECAL_xilinx7 <= '0';
MCB_USE_BKST <= '0';
MCB_UIDRPUPDATE <= '1';
Pre_SYSRST <= '1'; -- keeps MCB in reset
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
P_Term_s <= "000000";
N_Term_w <= "0000000";
P_Term_w <= "000000";
N_Term_s <= "0000000";
P_Term_Prev <= "000000";
N_Term_Prev <= "0000000";
Active_IODRP <= RZQ;
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
counter_en <= '0'; --flag that the First Dynamic Calibration completed
First_Dyn_Cal_Done <= '0';
Max_Value_int <= "00000000";
Max_Value_Previous <= "00000000";
STATE <= START;
DQS_DELAY <= "00000000";
DQS_DELAY_INITIAL <= "00000000";
TARGET_DQS_DELAY <= "00000000";
LastPass_DynCal <= IN_TERM_PASS;
First_In_Term_Done <= '0';
MCB_UICMD <= '0';
MCB_UICMDIN <= '0';
MCB_UIDQCOUNT <= "0000";
counter_inc <= "00000000";
counter_dec <= "00000000";
else
counter_en <= '0';
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= NoOp;
IODRPCTRLR_R_WB <= READ_MODE;
IODRPCTRLR_USE_BKST <= '0';
MCB_CMD_VALID <= '0'; --no inc or dec
MCB_UILDQSINC <= '0'; --no inc or dec
MCB_UIUDQSINC <= '0'; --no inc or dec
MCB_UILDQSDEC <= '0'; --no inc or dec
MCB_UIUDQSDEC <= '0';
MCB_USE_BKST <= '0';
MCB_UICMDIN <= '0';
DQS_DELAY <= DQS_DELAY;
TARGET_DQS_DELAY <= TARGET_DQS_DELAY;
case STATE is
when START => --h00
MCB_UICMDEN <= '1'; -- take control of UI/UO port
MCB_UIDONECAL_xilinx7 <= '0'; -- tells MCB that it is in Soft Cal.
P_Term <= "000000";
N_Term <= "0000000";
Pre_SYSRST <= '1'; -- keeps MCB in reset
LastPass_DynCal <= IN_TERM_PASS;
if (SKIP_IN_TERM_CAL = 1) then
STATE <= WRITE_CALIBRATE;
elsif (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= START;
end if;
--***************************
-- IOB INPUT TERMINATION CAL
--***************************
when LOAD_RZQ_NTERM => --h01
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_NTERM;
else
STATE <= WAIT1;
end if;
when WAIT1 => --h02
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT1;
else
STATE <= LOAD_RZQ_PTERM;
end if;
when LOAD_RZQ_PTERM => --h03
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_RZQ_PTERM;
else
STATE <= WAIT2;
end if;
when WAIT2 => --h04
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT2;
elsif ((RZQ_IN = '1') or (P_Term = "111111")) then
STATE <= MULTIPLY_DIVIDE; -- LOAD_ZIO_PTERM
else
STATE <= INC_PTERM;
end if;
when INC_PTERM => --h05
P_Term <= P_Term + "000001";
STATE <= LOAD_RZQ_PTERM;
when MULTIPLY_DIVIDE => -- h06
-- 13/4/2011 compensate the added sync FF
P_Term <= Mult_Divide(("00" & (P_Term - '1')),MULT,DIV)(5 downto 0);
STATE <= LOAD_ZIO_PTERM;
when LOAD_ZIO_PTERM => --h07
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_PTERM;
else
STATE <= WAIT3;
end if;
when WAIT3 => --h08
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT3;
else
STATE <= LOAD_ZIO_NTERM;
end if;
when LOAD_ZIO_NTERM => --h09
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ('0' & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= LOAD_ZIO_NTERM;
else
STATE <= WAIT4;
end if;
when WAIT4 => --h0A
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
else
STATE <= INC_NTERM;
end if;
when INC_NTERM => --h0B
N_Term <= N_Term + "0000001";
STATE <= LOAD_ZIO_NTERM;
when SKEW => -- h0C
P_Term_s <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term_w <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
P_Term_w <= Mult_Divide(("00" & P_Term), MULT_W, DIV_W)(5 downto 0);
N_Term_s <= Mult_Divide(('0' & (N_Term-'1')), MULT_S, DIV_S)(6 downto 0);
P_Term <= Mult_Divide(("00" & P_Term), MULT_S, DIV_S)(5 downto 0);
N_Term <= Mult_Divide(('0' & (N_Term-'1')), MULT_W, DIV_W)(6 downto 0);
STATE <= WAIT_FOR_START_BROADCAST;
when WAIT_FOR_START_BROADCAST => --h0D
Pre_SYSRST <= '0'; -- release SYSRST, but keep UICMDEN=1 and UIDONECAL=0. This is needed to do Broadcast through UI interface, while
-- keeping the MCB in calibration mode
Active_IODRP <= MCB_PORT;
if ((START_BROADCAST and IODRPCTRLR_RDY_BUSY_N) = '1') then
if (P_Term /= P_Term_Prev) then
STATE <= BROADCAST_PTERM;
P_Term_Prev <= P_Term;
elsif (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if;
when BROADCAST_PTERM => --h0E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= ("00" & P_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_UIDRPUPDATE <= not First_In_Term_Done; -- Set the update flag if this is the first time through
MCB_USE_BKST <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_PTERM;
else
STATE <= WAIT5;
end if;
when WAIT5 => --h0F
if ((not(MCB_RDY_BUSY_N)) = '1') then
STATE <= WAIT5;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
if (N_Term /= N_Term_Prev) then
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
else
STATE <= OFF_RZQ_PTERM;
end if;
else
STATE <= WAIT5; -- wait for a Refresh cycle
end if;
else
N_Term_Prev <= N_Term;
STATE <= BROADCAST_NTERM;
end if;
when BROADCAST_NTERM => -- h10
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= ("0" & N_Term);
IODRPCTRLR_R_WB <= WRITE_MODE;
MCB_CMD_VALID <= '1';
MCB_USE_BKST <= '1';
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (MCB_RDY_BUSY_N = '1') then
STATE <= BROADCAST_NTERM;
else
STATE <= WAIT6;
end if;
when WAIT6 => -- h11
if (MCB_RDY_BUSY_N = '0') then
STATE <= WAIT6;
elsif (First_In_Term_Done = '1') then -- If first time through is already set, then this must be dynamic in term
if (MCB_UOREFRSHFLAG = '1')then
MCB_UIDRPUPDATE <= '1';
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT6; -- wait for a Refresh cycle
end if;
else
-- if (PNSKEWDQS = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
-- else
-- STATE <= OFF_RZQ_PTERM;
-- end if;
end if;
-- *********************
when LDQS_CLK_WRITE_P_TERM => -- h12
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_P_TERM;
else
STATE <= LDQS_CLK_P_TERM_WAIT;
end if;
when LDQS_CLK_P_TERM_WAIT => --7'h13
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_P_TERM_WAIT;
else
STATE <= LDQS_CLK_WRITE_N_TERM;
end if;
when LDQS_CLK_WRITE_N_TERM => --7'h14
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_CLK_WRITE_N_TERM;
else
STATE <= LDQS_CLK_N_TERM_WAIT;
end if;
--**
when LDQS_CLK_N_TERM_WAIT => --7'h15
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_CLK_N_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_P_TERM;
end if;
when LDQS_PIN_WRITE_P_TERM => --7'h16
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_P_TERM;
else
STATE <= LDQS_PIN_P_TERM_WAIT;
end if;
when LDQS_PIN_P_TERM_WAIT => --7'h17
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_P_TERM_WAIT;
else
STATE <= LDQS_PIN_WRITE_N_TERM;
end if;
when LDQS_PIN_WRITE_N_TERM => --7'h18
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_LDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_PIN_WRITE_N_TERM;
else
STATE <= LDQS_PIN_N_TERM_WAIT;
end if;
when LDQS_PIN_N_TERM_WAIT => --7'h19
if (MCB_RDY_BUSY_N = '0') then
STATE <= LDQS_PIN_N_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_P_TERM;
end if;
when UDQS_CLK_WRITE_P_TERM => --7'h1A
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_w;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_P_TERM;
else
STATE <= UDQS_CLK_P_TERM_WAIT;
end if;
when UDQS_CLK_P_TERM_WAIT => --7'h1B
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_P_TERM_WAIT;
else
STATE <= UDQS_CLK_WRITE_N_TERM;
end if;
when UDQS_CLK_WRITE_N_TERM => --7'h1C
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_s;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_CLK_WRITE_N_TERM;
else
STATE <= UDQS_CLK_N_TERM_WAIT;
end if;
when UDQS_CLK_N_TERM_WAIT => --7'h1D
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_CLK_N_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_P_TERM;
end if;
when UDQS_PIN_WRITE_P_TERM => --7'h1E
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= "00" & P_Term_s;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_P_TERM;
else
STATE <= UDQS_PIN_P_TERM_WAIT;
end if;
when UDQS_PIN_P_TERM_WAIT => --7'h1F
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_P_TERM_WAIT;
else
STATE <= UDQS_PIN_WRITE_N_TERM;
end if;
when UDQS_PIN_WRITE_N_TERM => --7'h20
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= '0' & N_Term_w;
MCB_UIADDR_int <= IOI_UDQS_PIN;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= UDQS_PIN_WRITE_N_TERM;
else
STATE <= UDQS_PIN_N_TERM_WAIT;
end if;
when UDQS_PIN_N_TERM_WAIT => --7'h21
if (MCB_RDY_BUSY_N = '0') then
STATE <= UDQS_PIN_N_TERM_WAIT;
else
STATE <= OFF_RZQ_PTERM;
end if;
-- *********************
when OFF_RZQ_PTERM => -- h22
Active_IODRP <= RZQ;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= PTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
P_Term <= "000000";
N_Term <= "0000000";
MCB_UIDRPUPDATE <= not(First_In_Term_Done); -- Set the update flag if this is the first time through
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_RZQ_PTERM;
else
STATE <= WAIT7;
end if;
when WAIT7 => -- h23
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT7;
else
STATE <= OFF_ZIO_NTERM;
end if;
when OFF_ZIO_NTERM => -- h24
Active_IODRP <= ZIO;
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= NTerm;
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= WRITE_MODE;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= OFF_ZIO_NTERM;
else
STATE <= WAIT8;
end if;
when WAIT8 => -- h25
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT8;
else
if (First_In_Term_Done = '1') then
STATE <= START_DYN_CAL; -- No need to reset the MCB if we are in InTerm tuning
else
STATE <= WRITE_CALIBRATE; -- go read the first Max_Value_int from RZQ
end if;
end if;
when RST_DELAY => -- h26
MCB_UICMDEN <= '0'; -- release control of UI/UO port
if (Block_Reset = '1') then -- this ensures that more than 512 clock cycles occur since the last reset after MCB_WRITE_CALIBRATE ???
STATE <= RST_DELAY;
else
STATE <= START_DYN_CAL_PRE;
end if;
--***************************
--DYNAMIC CALIBRATION PORTION
--***************************
when START_DYN_CAL_PRE => -- h27
LastPass_DynCal <= IN_TERM_PASS;
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '1'; -- SYSRST pulse
if (CALMODE_EQ_CALIBRATION = '0') then -- if C_MC_CALIBRATION_MODE is set to NOCALIBRATION
STATE <= START_DYN_CAL; -- we'll skip setting the DQS delays manually
else
STATE <= WAIT_FOR_UODONE;
end if;
when WAIT_FOR_UODONE => -- h28
Pre_SYSRST <= '0'; -- SYSRST pulse
if ((IODRPCTRLR_RDY_BUSY_N and MCB_UODONECAL) = '1')then --IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
MCB_UICMDEN <= '1'; -- grab UICMDEN
DQS_DELAY_INITIAL <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= WAIT_FOR_UODONE;
end if;
when LDQS_WRITE_POS_INDELAY => -- h29
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1') then
STATE <= LDQS_WRITE_POS_INDELAY;
else
STATE <= LDQS_WAIT1;
end if;
when LDQS_WAIT1 => -- h2A
if (MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT1;
else
STATE <= LDQS_WRITE_NEG_INDELAY;
end if;
when LDQS_WRITE_NEG_INDELAY => -- h2B
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_LDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= LDQS_WRITE_NEG_INDELAY;
else
STATE <= LDQS_WAIT2;
end if;
when LDQS_WAIT2 => -- 7'h2C
if(MCB_RDY_BUSY_N = '0')then
STATE <= LDQS_WAIT2;
else
STATE <= UDQS_WRITE_POS_INDELAY;
end if;
when UDQS_WRITE_POS_INDELAY => -- 7'h2D
IODRPCTRLR_MEMCELL_ADDR <= PosEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_POS_INDELAY;
else
STATE <= UDQS_WAIT1;
end if;
when UDQS_WAIT1 => -- 7'h2E
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT1;
else
STATE <= UDQS_WRITE_NEG_INDELAY;
end if;
when UDQS_WRITE_NEG_INDELAY => -- 7'h2F
IODRPCTRLR_MEMCELL_ADDR <= NegEdgeInDly;
IODRPCTRLR_R_WB <= WRITE_MODE;
IODRPCTRLR_WRITE_DATA <= DQS_DELAY_INITIAL;
MCB_UIADDR_int <= IOI_UDQS_CLK;
MCB_CMD_VALID <= '1';
if (MCB_RDY_BUSY_N = '1')then
STATE <= UDQS_WRITE_NEG_INDELAY;
else
STATE <= UDQS_WAIT2;
end if;
when UDQS_WAIT2 => -- 7'h30
if (MCB_RDY_BUSY_N = '0')then
STATE <= UDQS_WAIT2;
else
DQS_DELAY <= DQS_DELAY_INITIAL;
TARGET_DQS_DELAY <= DQS_DELAY_INITIAL;
STATE <= START_DYN_CAL;
end if;
when START_DYN_CAL => -- h31
Pre_SYSRST <= '0'; -- SYSRST not driven
counter_inc <= (others => '0');
counter_dec <= (others => '0');
if (SKIP_DYNAMIC_DQS_CAL = '1' and SKIP_DYN_IN_TERMINATION = '1')then
STATE <= DONE; --if we're skipping both dynamic algorythms, go directly to DONE
elsif ((IODRPCTRLR_RDY_BUSY_N = '1') and (MCB_UODONECAL = '1') and (SELFREFRESH_REQ_R1 = '0')) then
--IODRP Controller needs to be ready, & MCB needs to be done with hard calibration
-- Alternate between Dynamic Input Termination and Dynamic Tuning routines
if ((SKIP_DYN_IN_TERMINATION = '0') and (LastPass_DynCal = DYN_CAL_PASS)) then
LastPass_DynCal <= IN_TERM_PASS;
STATE <= LOAD_RZQ_NTERM;
else
LastPass_DynCal <= DYN_CAL_PASS;
STATE <= WRITE_CALIBRATE;
end if;
else
STATE <= START_DYN_CAL;
end if;
when WRITE_CALIBRATE => -- h32
Pre_SYSRST <= '0';
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= DelayControl;
IODRPCTRLR_WRITE_DATA <= "00100000";
IODRPCTRLR_R_WB <= WRITE_MODE;
Active_IODRP <= RZQ;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= WRITE_CALIBRATE;
else
STATE <= WAIT9;
end if;
when WAIT9 => -- h33
counter_en <= '1';
if (count < "100110") then -- this adds approximately 22 extra clock cycles after WRITE_CALIBRATE
STATE <= WAIT9;
else
STATE <= READ_MAX_VALUE;
end if;
when READ_MAX_VALUE => -- h34
IODRPCTRLR_CMD_VALID <= '1';
IODRPCTRLR_MEMCELL_ADDR <= MaxValue;
IODRPCTRLR_R_WB <= READ_MODE;
Max_Value_Previous <= Max_Value_int;
if (IODRPCTRLR_RDY_BUSY_N = '1') then
STATE <= READ_MAX_VALUE;
else
STATE <= WAIT10;
end if;
when WAIT10 => -- h35
if (IODRPCTRLR_RDY_BUSY_N = '0') then
STATE <= WAIT10;
else
Max_Value_int <= IODRPCTRLR_READ_DATA; --record the Max_Value_int from the IODRP controller
if (First_In_Term_Done = '0') then
STATE <= RST_DELAY;
First_In_Term_Done <= '1';
else
STATE <= ANALYZE_MAX_VALUE;
end if;
end if;
when ANALYZE_MAX_VALUE => -- h36 only do a Inc or Dec during a REFRESH cycle.
if (First_Dyn_Cal_Done = '0')then
STATE <= FIRST_DYN_CAL;
elsif ((Max_Value_int < Max_Value_Previous) and (Max_Value_Delta_Dn >= INCDEC_THRESHOLD)) then
STATE <= DECREMENT; -- May need to Decrement
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
-- DQS_COUNT_VIRTUAL updated (could be negative value)
elsif ((Max_Value_int > Max_Value_Previous) and (Max_Value_Delta_Up >= INCDEC_THRESHOLD)) then
STATE <= INCREMENT; -- May need to Increment
TARGET_DQS_DELAY <= Mult_Divide(Max_Value_int, DQS_NUMERATOR, DQS_DENOMINATOR);
else
Max_Value_int <= Max_Value_Previous;
STATE <= START_DYN_CAL;
end if;
when FIRST_DYN_CAL => -- h37
First_Dyn_Cal_Done <= '1'; -- set flag that the First Dynamic Calibration has been completed
STATE <= START_DYN_CAL;
when INCREMENT => -- h38
STATE <= START_DYN_CAL; -- Default case: Inc is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "101" =>
counter_inc <= counter_inc + '1';
STATE <= INCREMENT; -- Increment is still high, still in REFRSH cycle
if ((DQS_DELAY < DQS_DELAY_UPPER_LIMIT) and (counter_inc >= X"04")) then
-- if not at the upper limit yet, and you've waited 4 clks, increment
MCB_UILDQSINC <= '1';
MCB_UIUDQSINC <= '1';
DQS_DELAY <= DQS_DELAY + '1';
end if;
when "100" =>
if (DQS_DELAY < DQS_DELAY_UPPER_LIMIT) then
STATE <= INCREMENT; -- Increment is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
when DECREMENT => -- h39
STATE <= START_DYN_CAL; -- Default case: Dec is not high or no longer in REFRSH
MCB_UILDQSINC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSINC <= '0'; -- Default case: no inc or dec
MCB_UILDQSDEC <= '0'; -- Default case: no inc or dec
MCB_UIUDQSDEC <= '0'; -- Default case: no inc or dec
if (DQS_DELAY /= "00000000") then
case Inc_Dec_REFRSH_Flag is -- {Increment_Flag,Decrement_Flag,MCB_UOREFRSHFLAG},
when "011" =>
counter_dec <= counter_dec + '1';
STATE <= DECREMENT; -- Decrement is still high, still in REFRSH cycle
if ((DQS_DELAY > DQS_DELAY_LOWER_LIMIT) and (counter_dec >= X"04")) then
-- if not at the lower limit, and you've waited 4 clks, decrement
MCB_UILDQSDEC <= '1'; -- decrement
MCB_UIUDQSDEC <= '1'; -- decrement
DQS_DELAY <= DQS_DELAY - '1'; -- SBS
end if;
when "010" =>
if (DQS_DELAY > DQS_DELAY_LOWER_LIMIT) then --if not at the lower limit, decrement
STATE <= DECREMENT; --Decrement is still high, REFRESH ended - wait for next REFRESH
end if;
when others =>
STATE <= START_DYN_CAL;
end case;
end if;
when DONE => -- h3A
Pre_SYSRST <= '0'; -- SYSRST cleared
MCB_UICMDEN <= '0'; -- release UICMDEN
STATE <= DONE;
when others =>
MCB_UICMDEN <= '0'; -- release UICMDEN
MCB_UIDONECAL_xilinx7 <= '1'; -- release UIDONECAL - MCB will now initialize.
Pre_SYSRST <= '0'; -- SYSRST not driven
IODRPCTRLR_CMD_VALID <= '0';
IODRPCTRLR_MEMCELL_ADDR <= "00000000";
IODRPCTRLR_WRITE_DATA <= "00000000";
IODRPCTRLR_R_WB <= '0';
IODRPCTRLR_USE_BKST <= '0';
P_Term <= "000000";
N_Term <= "0000000";
Active_IODRP <= ZIO;
Max_Value_Previous <= "00000000";
MCB_UILDQSINC <= '0'; -- no inc or dec
MCB_UIUDQSINC <= '0'; -- no inc or dec
MCB_UILDQSDEC <= '0'; -- no inc or dec
MCB_UIUDQSDEC <= '0'; -- no inc or dec
counter_en <= '0';
First_Dyn_Cal_Done <= '0'; -- flag that the First Dynamic Calibration completed
Max_Value_int <= Max_Value_int;
STATE <= START;
end case;
end if;
end if;
end process;
end architecture trans;
| gpl-3.0 | e50824f3c8f8149ec091a6efb534f966 | 0.473002 | 4.251707 | false | false | false | false |
NicoLedwith/Dr.AluOpysel | RAT_MCU/prog_rom(test_all).vhd | 1 | 19,877 | -----------------------------------------------------------------------------
-- Definition of a single port ROM for RATASM defined by prog_rom.psm
--
-- Generated by RATASM Assembler
--
-- Standard IEEE libraries
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
entity prog_rom is
port ( ADDRESS : in std_logic_vector(9 downto 0);
INSTRUCTION : out std_logic_vector(17 downto 0);
CLK : in std_logic);
end prog_rom;
architecture low_level_definition of prog_rom is
-----------------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation.
-----------------------------------------------------------------------------
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
----------------------------------------------------------------------
-- Attributes to define ROM contents during implementation synthesis.
----------------------------------------------------------------------
attribute INIT_00 of ram_1024_x_18 : label is "A007601FA0066041A0056049A0046099A003600DA0026025A001609FA0006003";
attribute INIT_01 of ram_1024_x_18 : label is "000000000000000000000000000000000000000000008100A0096009A0086001";
attribute INIT_02 of ram_1024_x_18 : label is "4B834E824E12818A020050407001A0006F006E006D006B0B6A07630062006100";
attribute INIT_03 of ram_1024_x_18 : label is "810181F0A00343698D0A81B88201A1D8CD0A4D09620081584A834E824E1A8229";
attribute INIT_04 of ram_1024_x_18 : label is "82333D0082433C008253DB017B0FDC017C0FDD017DFF81A86100822301324140";
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000008002";
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
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begin
----------------------------------------------------------------------
--Instantiate the Xilinx primitive for a block RAM
--INIT values repeated to define contents for functional simulation
----------------------------------------------------------------------
ram_1024_x_18: RAMB16_S18
--synthesitranslate_off
--INIT values repeated to define contents for functional simulation
generic map (
INIT_00 => X"A007601FA0066041A0056049A0046099A003600DA0026025A001609FA0006003",
INIT_01 => X"000000000000000000000000000000000000000000008100A0096009A0086001",
INIT_02 => X"4B834E824E12818A020050407001A0006F006E006D006B0B6A07630062006100",
INIT_03 => X"810181F0A00343698D0A81B88201A1D8CD0A4D09620081584A834E824E1A8229",
INIT_04 => X"82333D0082433C008253DB017B0FDC017C0FDD017DFF81A86100822301324140",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000008002",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"81F8000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"000000000000000000000001222EECCF84888CF0F0FDFFFF000000FFFFFFFFFF",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => INSTRUCTION(15 downto 0),
DOP => INSTRUCTION(17 downto 16));
--
end low_level_definition;
--
----------------------------------------------------------------------
-- END OF FILE prog_rom.vhd
----------------------------------------------------------------------
| mit | d04f61655a109a257b37268635a93b3a | 0.735725 | 6.00151 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/concurrent/rule_003_test_input.vhd | 1 | 1,507 |
architecture RTL of ENT is
begin
-- Align left = no align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = no align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = no
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
-- Align left = yes and align paren = yes
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_foo <=
resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
n_bar <= a or b and c
xor z and x or
w and z;
n_bar <=
a or b and c
xor z and x or
w and z;
end architecture RTL;
| gpl-3.0 | a487d6f120d73246050106fead2327a7 | 0.474453 | 3.334071 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/shifter.vhd | 1 | 7,924 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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f7XFdYOxdQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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zTi7iedLhEYTldZbBLA=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
q2eIv8kmvmQkKwWZVPISQgHc9bA3qBQxroqw+7Jj+ongB1tHV+0b9y0o3zXYOwqfVwUjHx6Dsoqx
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4128)
`protect data_block
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FmMMEGz1LFdcDkILGPPpfT1zRwoOxgn+KEsgedKImgJJhR+VclYVgKO53JC1duNgEDLDqnfZSwVG
nkoLjW+Cs0B6wOQMewy7N7aFvvh9dOsq/1f83arsAz4EhJU2bg5tBG719MJmWNegE5UyyaRfuM1y
ndL5WGg7SGsp6SNcyrc71WfJD2G+jziRu/mCEK3qWKyXMuzNCQuaaJlpZUmHeO50Qm+mEyUPHf/j
ER3vhcljvkutgYnO48UyeYhInlzB+CrWfUE0XCaMWFAsLpSaf7SufqvmzxS7ShY3sORyJNS9MVNU
20Wc0SNH5spGp8c00zPaO8Ymwraa7TBK3ZweNaznTjqnlIQj1nM0qJnXlpDUL8kuijxtPWX3xgZ0
cwDk240mcOdQ6RfPkPVkrGwM4H4BsYbmwGB+AEZ7oVubJcl5r2zhvAFFEgoCBDQ5AEbsYn+18X+e
1rRxwRLisSzYRtoQyZEoiaN9hZyoqZUf1QdDCMlfJAiITQQ0x8+yuZcAlnGRx2HL6e1O7OIkWtc0
wqi1P0f0Iyrm6E9cn4Tnp6FwcvM976UZS1g4k2kEGL2H4s2V+OwfjZ3PBkQnJ8R5aYObFd8p8ekg
D0+EzYTpaOLtT5Ovcw5mpAENSQWgKciltNUffvYMqxoS0P2RTInkKnVv6KFXx/TK9HIY3hKFqfiD
AUYfNr/06haMRO+Khjh1Q2E98C5AWBAF2yoqW2fHvgzdNK/EQV4rA6G2a9XniIhEzhWS82yHe99o
lpmfLFqyAWUgb5rMJ76agUjGISJVDNVC
`protect end_protected
| mit | 2ea8970e6abfe86b912b8ed515d7e51c | 0.917718 | 1.923301 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/vhdlFile/case_generate_statement/classification_test_input.vhd | 1 | 1,052 |
architecture RTL of FIFO is
begin
LABEL0 : case a & b & c generate
when "000" =>
when "001" =>
end generate LABEL0;
-- Test nested case generates
LABEL0 : case a & b & c generate
when "000" =>
LABEL1 : case a & b & c generate
when "000" =>
when "001" =>
end generate LABEL1;
when "001" =>
end generate LABEL0;
-- Test deeply nested case generates
LABEL0 : case a & b & c generate
when "000" =>
LABEL1A : case a & b & c generate
when "000" =>
LABEL2A : case a & b & c generate
when "000" =>
when "001" =>
LABEL2A : case a & b & c generate
when "000" =>
when "001" =>
end generate LABEL2A;
end generate LABEL2A;
when "001" =>
end generate LABEL1A;
when "001" =>
LABEL1B : case a & b & c generate
when "000" =>
when "001" =>
end generate LABEL1B;
end generate LABEL0;
end architecture RTL;
| gpl-3.0 | 2b2aad83d813e32846376bda4e222f81 | 0.496198 | 3.881919 | false | false | false | false |
okaxaki/vm2413 | Opll.vhd | 2 | 3,506 | --
-- Opll.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
entity opll is
port(
XIN : in std_logic;
XOUT : out std_logic;
XENA : in std_logic;
D : in std_logic_vector(7 downto 0);
A : in std_logic;
CS_n : in std_logic;
WE_n : in std_logic;
IC_n : in std_logic;
MO : out std_logic_vector(9 downto 0);
RO : out std_logic_vector(9 downto 0)
);
end opll;
architecture RTL of opll is
signal reset : std_logic;
signal opllptr : std_logic_vector(7 downto 0);
signal oplldat : std_logic_vector(7 downto 0);
signal opllwr : std_logic;
signal am : AM_TYPE;
signal pm : PM_TYPE;
signal wf : WF_TYPE;
signal tl : DB_TYPE;
signal fb : FB_TYPE;
signal ar : AR_TYPE;
signal dr : DR_TYPE;
signal sl : SL_TYPE;
signal rr : RR_TYPE;
signal ml : ML_TYPE;
signal fnum: FNUM_TYPE;
signal blk : BLK_TYPE;
signal rks : RKS_TYPE;
signal key : std_logic;
signal rhythm : std_logic;
signal noise : std_logic;
signal pgout : PGOUT_TYPE;
signal egout : DB_TYPE;
signal opout : SIGNED_DB_TYPE;
signal faddr : CH_TYPE;
signal maddr : SLOT_TYPE;
signal fdata, mdata : SIGNED_LI_TYPE;
signal slot, slot2, slot5, slot8 : SLOT_TYPE;
signal stage, stage2, stage5, stage8 : STAGE_TYPE;
begin
XOUT <= XIN;
reset <= not IC_n;
process( XIN, reset )
begin
if reset ='1' then
opllwr <= '0';
opllptr <= (others =>'0');
-- D <= (others =>'Z');
elsif XIN'event and XIN = '1' then
if XENA = '1' then
if CS_n = '0' and WE_n = '0' and A ='0' then
opllptr <= D(7 downto 0);
opllwr <= '0';
elsif CS_n = '0' and WE_n = '0' and A = '1' then
oplldat <= D;
opllwr <= '1';
-- elsif CS_n ='0' and WE_n ='1' and A = '0' then
-- D <= "11111111";
-- opllwr <= '0';
-- else
-- D <= (others =>'Z');
-- opllwr <= '0';
end if;
end if; -- XENA
end if;
end process;
S0: SlotCounter generic map (0) port map(XIN,reset,XENA,slot,stage);
S2: SlotCounter generic map (2) port map(XIN,reset,XENA,slot2,stage2);
S5: SlotCounter generic map (5) port map(XIN,reset,XENA,slot5,stage5);
S8: SlotCounter generic map (8) port map(XIN,reset,XENA,slot8,stage8);
-- no delay
CT: Controller port map (
XIN,reset,XENA, slot, stage, opllwr,opllptr,oplldat,
am,pm,wf,ml,tl,fb,ar,dr,sl,rr,blk,fnum,rks,key,rhythm);
-- 2 stages delay
EG: EnvelopeGenerator port map (
XIN,reset,XENA,
slot2, stage2, rhythm,
am, tl, ar, dr, sl, rr, rks, key,
egout
);
PG: PhaseGenerator port map (
XIN,reset,XENA,
slot2, stage2, rhythm,
pm, ml, blk, fnum, key,
noise, pgout
);
-- 5 stages delay
OP: Operator port map (
XIN,reset,XENA,
slot5, stage5, rhythm,
wf, fb, noise, pgout, egout, faddr, fdata, opout
);
-- 8 stages delay
OG: OutputGenerator port map (
XIN, reset, XENA, slot8, stage8, rhythm,
opout, faddr, fdata, maddr, mdata
);
-- independent from delay
TM: TemporalMixer port map (
XIN, reset, XENA,
slot, stage, rhythm,
maddr, mdata,
MO, RO
);
end RTL;
| mit | b72d712ceec9ce17e8a8cc147fa38efa | 0.541643 | 3.144395 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/gn4124-core/p2l_decode32.vhd | 2 | 14,798 | --------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: P2L 32-bit datapath decoder (p2l_decode32.vhd)
--
-- authors: Simon Deprez ([email protected])
-- Matthieu Cattin ([email protected])
--
-- date: 31-08-2010
--
-- version: 1.0
--
-- description: PCIe to local bus packet decoder - For 32-bit data path design.
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 27-09-2010 (mcattin) Rewrite a part of the decoder logic
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
entity p2l_decode32 is
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- Input from the deserializer
des_p2l_valid_i : in std_logic;
des_p2l_dframe_i : in std_logic;
des_p2l_data_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------
-- Decoder outputs
--
-- Header
p2l_hdr_start_o : out std_logic; -- Header strobe
p2l_hdr_length_o : out std_logic_vector(9 downto 0); -- Packet length in 32-bit words multiples
p2l_hdr_cid_o : out std_logic_vector(1 downto 0); -- Completion ID
p2l_hdr_last_o : out std_logic; -- Indicates Last packet in a completion
p2l_hdr_stat_o : out std_logic_vector(1 downto 0); -- Completion Status
-- "00" = Successful completion
-- "01" = Unsupported request
-- "10" = Completer abort
-- "11" = Completion time-out
-- Packet type (for routing)
p2l_target_mrd_o : out std_logic; -- Target memory read (to wbmaster32)
p2l_target_mwr_o : out std_logic; -- Target memory write (to wbmaster32)
p2l_master_cpld_o : out std_logic; -- Master completion with data (to p2l_dma_master)
p2l_master_cpln_o : out std_logic; -- Master completion without data (to p2l_dma_master)
-- Address
p2l_addr_start_o : out std_logic; -- Address strobe
p2l_addr_o : out std_logic_vector(31 downto 0); -- Target address (in byte) that will increment with data
-- increment = 4 bytes
-- Data
p2l_d_valid_o : out std_logic; -- Indicates Data is valid
p2l_d_last_o : out std_logic; -- Indicates end of the packet
p2l_d_o : out std_logic_vector(31 downto 0); -- Data
p2l_be_o : out std_logic_vector(3 downto 0) -- Byte Enable for data
);
end p2l_decode32;
architecture rtl of p2l_decode32 is
-----------------------------------------------------------------------------
-- to_mvl Function
-----------------------------------------------------------------------------
function f_to_mvl (b : in boolean) return std_logic is
begin
if (b = true) then
return('1');
else
return('0');
end if;
end f_to_mvl;
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
signal des_p2l_valid_d : std_logic;
signal des_p2l_dframe_d : std_logic;
signal p2l_packet_start : std_logic;
signal p2l_packet_start_d : std_logic;
signal p2l_packet_end : std_logic;
signal p2l_addr_cycle : std_logic;
signal p2l_data_cycle : std_logic;
signal p2l_hdr_strobe : std_logic; -- Indicates Header start cycle
signal p2l_hdr_length : std_logic_vector(9 downto 0); -- Latched LENGTH value from header
signal p2l_hdr_cid : std_logic_vector(1 downto 0); -- Completion ID
signal p2l_hdr_last : std_logic; -- Indicates Last packet in a completion
signal p2l_hdr_stat : std_logic_vector(1 downto 0); -- Completion Status
signal p2l_addr_start : std_logic;
signal p2l_addr : unsigned(31 downto 0); -- Registered and counting Address
signal p2l_d_valid : std_logic; -- Indicates Address/Data is valid
signal p2l_d_first : std_logic;
signal p2l_d_last : std_logic; -- Indicates end of the packet
signal p2l_d : std_logic_vector(31 downto 0); -- Address/Data
signal p2l_be : std_logic_vector(3 downto 0); -- Byte Enable for data
signal p2l_hdr_fbe : std_logic_vector(3 downto 0); -- First Byte Enable
signal p2l_hdr_lbe : std_logic_vector(3 downto 0); -- Last Byte Enable
signal target_mrd : std_logic;
signal target_mwr : std_logic;
signal master_cpld : std_logic;
signal master_cpln : std_logic;
begin
-----------------------------------------------------------------------------
-- 1 tick delay version of des_p2l_valid_i and des_p2l_dframe_i,
-- for start and end frame detection
-----------------------------------------------------------------------------
process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
des_p2l_dframe_d <= '0';
des_p2l_valid_d <= '0';
elsif rising_edge(clk_i) then
des_p2l_dframe_d <= des_p2l_dframe_i;
des_p2l_valid_d <= des_p2l_valid_i;
end if;
end process;
------------------------------------------------------------------------------
-- Start and end packet detection
------------------------------------------------------------------------------
p2l_packet_start <= des_p2l_dframe_i and not(des_p2l_dframe_d) and des_p2l_valid_i;
p2l_packet_end <= des_p2l_valid_d and not(des_p2l_dframe_d);
-----------------------------------------------------------------------------
-- Decode packet type
-----------------------------------------------------------------------------
p_type_decode : process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
target_mrd <= '0';
target_mwr <= '0';
master_cpld <= '0';
master_cpln <= '0';
elsif rising_edge(clk_i) then
-- New packet starts, check type for routing
if (p2l_packet_start = '1') then
-- Target read request
target_mrd <= f_to_mvl(des_p2l_data_i(27 downto 24) = "0000");
-- Target write
target_mwr <= f_to_mvl(des_p2l_data_i(27 downto 24) = "0010");
-- Master read completion with data
master_cpld <= f_to_mvl(des_p2l_data_i(27 downto 24) = "0101");
-- Master read completion without data
master_cpln <= f_to_mvl(des_p2l_data_i(27 downto 24) = "0100");
elsif (p2l_packet_end = '1') then
target_mrd <= '0';
target_mwr <= '0';
master_cpld <= '0';
master_cpln <= '0';
end if;
end if;
end process p_type_decode;
-----------------------------------------------------------------------------
-- Packet header decoding
-----------------------------------------------------------------------------
p_header_decode : process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_hdr_strobe <= '0';
p2l_hdr_length <= (others => '0');
p2l_hdr_cid <= (others => '0');
p2l_hdr_last <= '0';
p2l_hdr_stat <= (others => '0');
p2l_hdr_fbe <= (others => '0');
p2l_hdr_lbe <= (others => '0');
elsif rising_edge(clk_i) then
if (p2l_packet_start = '1') then
p2l_hdr_strobe <= '1';
p2l_hdr_length <= des_p2l_data_i(9 downto 0);
p2l_hdr_cid <= des_p2l_data_i(11 downto 10);
p2l_hdr_last <= des_p2l_data_i(15);
if (des_p2l_data_i(26) = '1') then
-- packet type = read completion
p2l_hdr_stat <= des_p2l_data_i(17 downto 16); -- Completion status
else
-- Target read or write
p2l_hdr_fbe <= des_p2l_data_i(19 downto 16); -- First Byte Enable
p2l_hdr_lbe <= des_p2l_data_i(23 downto 20); -- Last Byte Enable
end if;
else
p2l_hdr_strobe <= '0';
end if;
end if;
end process p_header_decode;
-----------------------------------------------------------------------------
-- Packet address decoding
-----------------------------------------------------------------------------
p_addr_decode : process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_addr_cycle <= '0';
p2l_addr <= (others => '0');
p2l_addr_start <= '0';
elsif rising_edge(clk_i) then
-- Indicate address cycle(s)
-- Address cycle comes just after the header.
-- Read completion packet doesn't have an address field, then addr_cycle is not asserted.
if (p2l_packet_start = '1' and des_p2l_data_i(26) = '0') then
p2l_addr_cycle <= '1';
elsif (p2l_addr_cycle = '1' and des_p2l_valid_i = '1') then
p2l_addr_cycle <= '0';
end if;
-- Generates address strobe
-- No address strobe for read completion packets
if ((target_mwr or target_mrd) = '1') then
p2l_addr_start <= p2l_addr_cycle and des_p2l_valid_i;
else
p2l_addr_start <= '0';
end if;
-- Put address on a dedicated bus
-- Bits 1-0 are coding the BAR for target read/write
-- "00" = BAR 0
-- "01" = BAR 2
-- "10" = Expansion ROM
-- "11" = Reserved
if (p2l_addr_cycle = '1' and des_p2l_valid_i = '1' and (target_mwr or target_mrd) = '1') then
-- Latch target address
p2l_addr <= unsigned(des_p2l_data_i);
elsif (p2l_d_valid = '1' and (target_mwr or target_mrd) = '1') then
-- Increment address with data (32-bit data word => increment = +4 bytes)
p2l_addr(31 downto 2) <= p2l_addr(31 downto 2) + 1;
end if;
end if;
end process p_addr_decode;
-----------------------------------------------------------------------------
-- Packet data decoding (data strobe)
-----------------------------------------------------------------------------
p_data_decode : process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_data_cycle <= '0';
p2l_d_valid <= '0';
p2l_d_last <= '0';
p2l_d <= (others => '0');
elsif rising_edge(clk_i) then
-- Indicates data cycle(s)
-- Data cycle comes after an address cycle, exept for read completion packet
-- in this case it comes just after the header.
if ((p2l_addr_cycle = '1' or (p2l_packet_start = '1' and des_p2l_data_i(26) = '1'))
and des_p2l_valid_i = '1' and des_p2l_dframe_i = '1') then
p2l_data_cycle <= '1';
elsif (des_p2l_dframe_i = '0') then
p2l_data_cycle <= '0';
end if;
-- Generates data strobe
-- For read completion, data are valid just after the header (no address)
--if (master_cpld = '1') then
-- p2l_d_valid <= des_p2l_valid_i;
--else
p2l_d_valid <= p2l_data_cycle and des_p2l_valid_i;
--end if;
-- Generates last data signal
p2l_d_last <= p2l_data_cycle and not(des_p2l_dframe_i);
-- Latch data on the bus
if(des_p2l_valid_i = '1') then
p2l_d <= des_p2l_data_i;
end if;
end if;
end process p_data_decode;
-----------------------------------------------------------------------------
-- Byte enable
-----------------------------------------------------------------------------
p_be_decode : process (clk_i, rst_n_i)
begin
if rst_n_i = c_RST_ACTIVE then
p2l_be <= (others => '0');
elsif rising_edge(clk_i) then
if (p2l_addr_start = '1') then
p2l_be <= p2l_hdr_fbe; -- First Byte Enable
elsif ((p2l_data_cycle and not(des_p2l_dframe_i)) = '1') then
p2l_be <= p2l_hdr_lbe; -- Last Byte Enable
elsif(p2l_data_cycle = '1') then
p2l_be <= (others => '1'); -- Intermediate Byte Enables
end if;
end if;
end process p_be_decode;
-----------------------------------------------------------------------------
-- Assigns signals to output ports
-----------------------------------------------------------------------------
p2l_hdr_start_o <= p2l_hdr_strobe;
p2l_hdr_length_o <= p2l_hdr_length;
p2l_hdr_cid_o <= p2l_hdr_cid;
p2l_hdr_last_o <= p2l_hdr_last;
p2l_hdr_stat_o <= p2l_hdr_stat;
p2l_addr_start_o <= p2l_addr_start;
p2l_addr_o <= std_logic_vector(p2l_addr);
p2l_d_valid_o <= p2l_d_valid;
p2l_d_last_o <= p2l_d_last;
p2l_d_o <= p2l_d;
p2l_be_o <= p2l_be;
p2l_target_mrd_o <= target_mrd;
p2l_target_mwr_o <= target_mwr;
p2l_master_cpld_o <= master_cpld;
p2l_master_cpln_o <= master_cpln;
end rtl;
| gpl-3.0 | 156121eb2b53d29c70f50db86649f781 | 0.465739 | 3.716223 | false | false | false | false |
jeremiah-c-leary/vhdl-style-guide | vsg/tests/whitespace/rule_004_test_input.fixed.vhd | 1 | 379 |
architecture RTL of FIFO is
signal sig1, sig2 : std_logic_vector(3 downto 0);
constant c_cons1, c_const2 : integer := 200;
constant c_cons2 : integer := 200;
begin
U_RAM : RAM_ARRAY
generic map (
G_WIDTH => 512,
G_DEPTH => 2048,
G_SIZE => 32
)
port map (
I_DATA_A => data_a,
I_DATA_B => data_b
);
end architecture RTL;
| gpl-3.0 | 37f78ee2b988ef8b52c0993a5016832a | 0.564644 | 3.106557 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/async_fifo.vhd | 2 | 33,343 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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`protect end_protected
| bsd-2-clause | f4aa0684fb74f07483242ca6169c62d6 | 0.946196 | 1.834957 | false | false | false | false |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/add_accum.vhd | 2 | 14,821 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9232)
`protect data_block
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`protect end_protected
| mit | f0886ea2162b1e20c7fc9c0733eabc3e | 0.935969 | 1.874178 | false | false | false | false |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/fifo_generator_v11_0/ramfifo/wr_status_flags_sshft.vhd | 2 | 23,122 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
| bsd-2-clause | ea16bd527ba5bb0d3a093dbcb355fc3d | 0.94222 | 1.855252 | false | false | false | false |
Yarr/Yarr-fw | rtl/spartan6/rx-core/decode_8b10b/decode_8b10b_rtl.vhd | 2 | 22,735 | ---------------------------------------------------------------------------
--
-- Module : decode_8b10b_rtl.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : Top-level, synthesizable 8b/10b decoder core file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-------------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
library work;
USE work.decode_8b10b_pkg.ALL;
-----------------------------------------------------------------------------
-- Entity Declaration
-----------------------------------------------------------------------------
ENTITY decode_8b10b_rtl IS
GENERIC (
C_DECODE_TYPE : INTEGER := 0;
C_ELABORATION_DIR : STRING := "./../../src/";
C_HAS_BPORTS : INTEGER := 0;
C_HAS_CE : INTEGER := 0;
C_HAS_CE_B : INTEGER := 0;
C_HAS_CODE_ERR : INTEGER := 0;
C_HAS_CODE_ERR_B : INTEGER := 0;
C_HAS_DISP_ERR : INTEGER := 0;
C_HAS_DISP_ERR_B : INTEGER := 0;
C_HAS_DISP_IN : INTEGER := 0;
C_HAS_DISP_IN_B : INTEGER := 0;
C_HAS_ND : INTEGER := 0;
C_HAS_ND_B : INTEGER := 0;
C_HAS_RUN_DISP : INTEGER := 0;
C_HAS_RUN_DISP_B : INTEGER := 0;
C_HAS_SINIT : INTEGER := 0;
C_HAS_SINIT_B : INTEGER := 0;
C_HAS_SYM_DISP : INTEGER := 0;
C_HAS_SYM_DISP_B : INTEGER := 0;
C_SINIT_DOUT : STRING := "00000000";
C_SINIT_DOUT_B : STRING := "00000000";
C_SINIT_KOUT : INTEGER := 0;
C_SINIT_KOUT_B : INTEGER := 0;
C_SINIT_RUN_DISP : INTEGER := 0;
C_SINIT_RUN_DISP_B : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC := '0';
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT : OUT STD_LOGIC ;
CE : IN STD_LOGIC := '0';
CE_B : IN STD_LOGIC := '0';
CLK_B : IN STD_LOGIC := '0';
DIN_B : IN STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DISP_IN : IN STD_LOGIC := '0';
DISP_IN_B : IN STD_LOGIC := '0';
SINIT : IN STD_LOGIC := '0';
SINIT_B : IN STD_LOGIC := '0';
CODE_ERR : OUT STD_LOGIC := '0';
CODE_ERR_B : OUT STD_LOGIC := '0';
DISP_ERR : OUT STD_LOGIC := '0';
DISP_ERR_B : OUT STD_LOGIC := '0';
DOUT_B : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
KOUT_B : OUT STD_LOGIC ;
ND : OUT STD_LOGIC := '0';
ND_B : OUT STD_LOGIC := '0';
RUN_DISP : OUT STD_LOGIC ;
RUN_DISP_B : OUT STD_LOGIC ;
SYM_DISP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
SYM_DISP_B : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END decode_8b10b_rtl;
--------------------------------------------------------------------------------
-- Generic Definitions:
--------------------------------------------------------------------------------
-- C_DECODE_TYPE : Implementation: 0=Slice based, 1=BlockRam
-- C_ELABORATION_DIR : Directory path for mif file
-- C_HAS_BPORTS : 1 indicates second decoder should be generated
-- C_HAS_CE : 1 indicates ce port is present
-- C_HAS_CE_B : 1 indicates ce_b port is present (if c_has_bports=1)
-- C_HAS_CODE_ERR : 1 indicates code_err port is present
-- C_HAS_CODE_ERR_B : 1 indicates code_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_ERR : 1 indicates disp_err port is present
-- C_HAS_DISP_ERR_B : 1 indicates disp_err_b port is present
-- (if c_has_bports=1)
-- C_HAS_DISP_IN : 1 indicates disp_in port is present
-- C_HAS_DISP_IN_B : 1 indicates disp_in_b port is present
-- (if c_has_bports=1)
-- C_HAS_ND : 1 indicates nd port is present
-- C_HAS_ND_B : 1 indicates nd_b port is present (if c_has_bports=1)
-- C_HAS_RUN_DISP : 1 indicates run_disp port is present
-- C_HAS_RUN_DISP_B : 1 indicates run_disp_b port is present
-- (if c_has_bports=1)
-- C_HAS_SINIT : 1 indicates sinit port is present
-- C_HAS_SINIT_B : 1 indicates sinit_b port is present
-- (if c_has_bports=1)
-- C_HAS_SYM_DISP : 1 indicates sym_disp port is present
-- C_HAS_SYM_DISP_B : 1 indicates sym_disp_b port is present
-- (if c_has_bports=1)
-- C_SINIT_DOUT : 8-bit binary string, dout value when sinit is active
-- C_SINIT_DOUT_B : 8-bit binary string, dout_b value when sinit_b is
-- active
-- C_SINIT_KOUT : controls kout output when sinit is active
-- C_SINIT_KOUT_B : controls kout_b output when sinit_b is active
-- C_SINIT_RUN_DISP : Initializes run_disp (and disp_in) value to
-- positive(1) or negative(0)
-- C_SINIT_RUN_DISP_B : Initializes run_disp_b (and disp_in_b) value to
-- positive(1) or negative(0)
--------------------------------------------------------------------------------
-- Port Definitions:
--------------------------------------------------------------------------------
-- Mandatory Pins
-- CLK : Clock Input
-- DIN : Encoded Symbol Input
-- DOUT : Data Output, decoded data byte
-- KOUT : Command Output
-------------------------------------------------------------------------
-- Optional Pins
-- CE : Clock Enable
-- CE_B : Clock Enable (B port)
-- CLK_B : Clock Input (B port)
-- DIN_B : Encoded Symbol Input (B port)
-- DISP_IN : Disparity Input (running disparity in)
-- DISP_IN_B : Disparity Input (running disparity in) (B port)
-- SINIT : Synchronous Initialization. Resets core to known state.
-- SINIT_B : Synchronous Initialization. Resets core to known state.
-- (B port)
-- CODE_ERR : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set.
-- CODE_ERR_B : Code Error, indicates that input symbol did not correspond
-- to a valid member of the code set. (B port)
-- DISP_ERR : Disparity Error
-- DISP_ERR_B : Disparity Error (B port)
-- DOUT_B : Data Output, decoded data byte (B port)
-- KOUT_B : Command Output (B port)
-- ND : New Data
-- ND_B : New Data (B port)
-- RUN_DISP : Running Disparity
-- RUN_DISP_B : Running Disparity (B port)
-- SYM_DISP : Symbol Disparity
-- SYM_DISP_B : Symbol Disparity (B port)
-------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE xilinx OF decode_8b10b_rtl IS
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
SIGNAL dout_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT,8);
--convert C_SINIT_DOUT string to 8bit std_logic_vector
SIGNAL kout_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT);
--convert C_SINIT_KOUT integer to std_logic
SIGNAL clk_b_i : STD_LOGIC := '0';
SIGNAL din_b_i : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ce_i : STD_LOGIC := '0';
SIGNAL ce_b_i : STD_LOGIC := '0';
SIGNAL disp_in_i : STD_LOGIC := '0';
SIGNAL disp_in_b_i : STD_LOGIC := '0';
SIGNAL sinit_i : STD_LOGIC := '0';
SIGNAL sinit_b_i : STD_LOGIC := '0';
SIGNAL code_err_i : STD_LOGIC := '0';
SIGNAL code_err_b_i : STD_LOGIC := '0';
SIGNAL disp_err_i : STD_LOGIC := '0';
SIGNAL disp_err_b_i : STD_LOGIC := '0';
SIGNAL dout_b_i : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
str_to_slv(C_SINIT_DOUT_B,8);
--convert C_SINIT_DOUT_B string to 8bit std_logic_vector
SIGNAL kout_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_KOUT_B);
--convert C_SINIT_KOUT_B integer to std_logic
SIGNAL nd_i : STD_LOGIC := '0';
SIGNAL nd_b_i : STD_LOGIC := '0';
SIGNAL run_disp_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP);
--convert C_SINIT_RUN_DISP integer to std logic
SIGNAL run_disp_b_i : STD_LOGIC :=
bint_2_sl(C_SINIT_RUN_DISP_B);
--convert C_SINIT_RUN_DISP_B integer to std logic
SIGNAL sym_disp_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP,2);
--convert C_SINIT_RUN_DISP integer to slv
SIGNAL sym_disp_b_i : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
conv_std_logic_vector(C_SINIT_RUN_DISP_B,2);
--convert C_SINIT_RUN_DISP_B integer to slv
-------------------------------------------------------------------------------
-- Begin Architecture
-------------------------------------------------------------------------------
BEGIN
-----------------------------------------------------------------------------
-- LUT-based decoder
-----------------------------------------------------------------------------
glut : IF (C_DECODE_TYPE = 0) GENERATE
ldec : entity work.decode_8b10b_lut
GENERIC MAP (
C_HAS_BPORTS => C_HAS_BPORTS,
C_HAS_CODE_ERR => C_HAS_CODE_ERR,
C_HAS_CODE_ERR_B => C_HAS_CODE_ERR_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_IN_B => C_HAS_DISP_IN_B,
C_HAS_ND => C_HAS_ND,
C_HAS_ND_B => C_HAS_ND_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B,
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_DOUT_B => C_SINIT_DOUT_B,
C_SINIT_KOUT => C_SINIT_KOUT,
C_SINIT_KOUT_B => C_SINIT_KOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP,
C_SINIT_RUN_DISP_B => C_SINIT_RUN_DISP_B
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => dout_i,
KOUT => kout_i,
CE => ce_i,
DISP_IN => disp_in_i,
SINIT => sinit_i,
CODE_ERR => code_err_i,
DISP_ERR => disp_err_i,
ND => nd_i,
RUN_DISP => run_disp_i,
SYM_DISP => sym_disp_i,
CLK_B => clk_b_i,
DIN_B => din_b_i,
DOUT_B => dout_b_i,
KOUT_B => kout_b_i,
CE_B => ce_b_i,
DISP_IN_B => disp_in_b_i,
SINIT_B => sinit_b_i,
CODE_ERR_B => code_err_b_i,
DISP_ERR_B => disp_err_b_i,
ND_B => nd_b_i,
RUN_DISP_B => run_disp_b_i,
SYM_DISP_B => sym_disp_b_i
);
END GENERATE glut;
-----------------------------------------------------------------------------
-- BRAM-based decoder
-----------------------------------------------------------------------------
gbram : IF (C_DECODE_TYPE /= 0) GENERATE
bdec : entity work.decode_8b10b_bram
GENERIC MAP (
C_ELABORATION_DIR => C_ELABORATION_DIR,
C_HAS_BPORTS => C_HAS_BPORTS,
C_HAS_DISP_IN => C_HAS_DISP_IN,
C_HAS_DISP_IN_B => C_HAS_DISP_IN_B,
C_HAS_DISP_ERR => C_HAS_DISP_ERR,
C_HAS_DISP_ERR_B => C_HAS_DISP_ERR_B,
C_HAS_RUN_DISP => C_HAS_RUN_DISP,
C_HAS_RUN_DISP_B => C_HAS_RUN_DISP_B,
C_HAS_SYM_DISP => C_HAS_SYM_DISP,
C_HAS_SYM_DISP_B => C_HAS_SYM_DISP_B,
C_HAS_ND => C_HAS_ND,
C_HAS_ND_B => C_HAS_ND_B,
C_SINIT_DOUT => C_SINIT_DOUT,
C_SINIT_DOUT_B => C_SINIT_DOUT_B,
C_SINIT_KOUT => C_SINIT_KOUT,
C_SINIT_KOUT_B => C_SINIT_KOUT_B,
C_SINIT_RUN_DISP => C_SINIT_RUN_DISP,
C_SINIT_RUN_DISP_B => C_SINIT_RUN_DISP_B
)
PORT MAP(
CLK => CLK,
DIN => DIN,
DOUT => dout_i,
KOUT => kout_i,
CE => ce_i,
DISP_IN => disp_in_i,
SINIT => sinit_i,
CODE_ERR => code_err_i,
DISP_ERR => disp_err_i,
ND => nd_i,
RUN_DISP => run_disp_i,
SYM_DISP => sym_disp_i,
CLK_B => clk_b_i,
DIN_B => din_b_i,
DOUT_B => dout_b_i,
KOUT_B => kout_b_i,
CE_B => ce_b_i,
DISP_IN_B => disp_in_b_i,
SINIT_B => sinit_b_i,
CODE_ERR_B => code_err_b_i,
DISP_ERR_B => disp_err_b_i,
ND_B => nd_b_i,
RUN_DISP_B => run_disp_b_i,
SYM_DISP_B => sym_disp_b_i
);
END GENERATE gbram;
---------------------------------------------------------------------------
-- Mandatory A Ports
---------------------------------------------------------------------------
DOUT <= dout_i;
KOUT <= kout_i;
---------------------------------------------------------------------------
-- Optional A Ports --tying off unused ports
---------------------------------------------------------------------------
--Inputs
--ce
gen : IF (C_HAS_CE/=0) GENERATE
ce_i <= CE;
END GENERATE gen;
ngen : IF (C_HAS_CE = 0) GENERATE
ce_i <= '1';
END GENERATE ngen;
--disp_in
gdi : IF (C_HAS_DISP_IN /= 0) GENERATE
disp_in_i <= DISP_IN;
END GENERATE gdi;
ngdi : IF (C_HAS_DISP_IN = 0) GENERATE
disp_in_i <= '0';
END GENERATE ngdi;
--sinit
gs : IF (C_HAS_SINIT /= 0) GENERATE
sinit_i <= SINIT;
END GENERATE gs;
ngs : IF (C_HAS_SINIT = 0) GENERATE
sinit_i <= '0';
END GENERATE ngs;
--Outputs
--nd
gnd : IF (C_HAS_ND /= 0) GENERATE
ASSERT (C_HAS_CE /= 0)
REPORT "Invalid configuration: ND port requires CE port"
SEVERITY WARNING;
ND <= nd_i;
END GENERATE gnd;
ngnd : IF (C_HAS_ND = 0) GENERATE
ND <= '0';
END GENERATE ngnd;
--code_err
gce : IF (C_HAS_CODE_ERR /= 0) GENERATE
CODE_ERR <= code_err_i;
END GENERATE gce;
ngce : IF (C_HAS_CODE_ERR = 0) GENERATE
CODE_ERR <= '0';
END GENERATE ngce;
--disp_err
gder : IF (C_HAS_DISP_ERR /= 0) GENERATE
DISP_ERR <= disp_err_i;
END GENERATE gder;
ngder : IF (C_HAS_DISP_ERR = 0) GENERATE
DISP_ERR <= '0';
END GENERATE ngder;
--run_disp
grd : IF (C_HAS_RUN_DISP /= 0) GENERATE
RUN_DISP <= run_disp_i;
END GENERATE grd;
ngrd : IF (C_HAS_RUN_DISP = 0) GENERATE
RUN_DISP <= '0';
END GENERATE ngrd;
--sym_disp
gsd : IF (C_HAS_SYM_DISP /= 0) GENERATE
SYM_DISP <= sym_disp_i;
END GENERATE gsd;
ngsd : IF (C_HAS_SYM_DISP = 0) GENERATE
SYM_DISP <= "00";
END GENERATE ngsd;
----------------------------------------------------------------------------
-- Optional B Ports -- tying off unused ports
----------------------------------------------------------------------------
--Mandatory B ports (if B ports are selected)
gbpt : IF (C_HAS_BPORTS /= 0) GENERATE
din_b_i <= DIN_B;
clk_b_i <= CLK_B;
DOUT_B <= dout_b_i;
KOUT_B <= kout_b_i;
END GENERATE gbpt;
ngbpt : IF (C_HAS_BPORTS = 0) GENERATE
din_b_i <= (OTHERS => '0');
clk_b_i <= '0';
DOUT_B <= (OTHERS => '0');
KOUT_B <= '0';
END GENERATE ngbpt;
--Inputs
--ce_b
genb : IF (C_HAS_CE_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
ce_b_i <= CE_B;
END GENERATE genb;
ngenb : IF (C_HAS_CE_B = 0 OR C_HAS_BPORTS = 0) GENERATE
ce_b_i <= '1';
END GENERATE ngenb;
ASSERT (NOT(C_HAS_CE_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate CE_B when C_HAS_BPORTS=0"
SEVERITY WARNING;
--disp_in_b
gdib : IF (C_HAS_DISP_IN_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
disp_in_b_i <= DISP_IN_B;
END GENERATE gdib;
ngdib : IF (C_HAS_DISP_IN_B = 0 OR C_HAS_BPORTS = 0) GENERATE
disp_in_b_i <= '0';
END GENERATE ngdib;
ASSERT (NOT(C_HAS_DISP_IN_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate DISP_IN_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--sinit_b
gsb : IF (C_HAS_SINIT_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
sinit_b_i <= SINIT_B;
END GENERATE gsb;
ngsb : IF (C_HAS_SINIT_B = 0 OR C_HAS_BPORTS = 0) GENERATE
sinit_b_i <= '0';
END GENERATE ngsb;
ASSERT (NOT(C_HAS_SINIT_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate SINIT_B when C_HAS_BPORTS=0"
SEVERITY WARNING;
--Outputs
--code_err_b
gceb : IF (C_HAS_CODE_ERR_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
CODE_ERR_B <= code_err_b_i;
END GENERATE gceb;
ngceb : IF (C_HAS_CODE_ERR_B = 0 OR C_HAS_BPORTS = 0) GENERATE
CODE_ERR_B <= '0';
END GENERATE ngceb;
ASSERT (NOT(C_HAS_CODE_ERR_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate CODE_ERR_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--disp_err_b
gdeb : IF (C_HAS_DISP_ERR_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
DISP_ERR_B <= disp_err_b_i;
END GENERATE gdeb;
ngdeb : IF (C_HAS_DISP_ERR_B = 0 OR C_HAS_BPORTS = 0) GENERATE
DISP_ERR_B <= '0';
END GENERATE ngdeb;
ASSERT (NOT(C_HAS_DISP_ERR_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate DISP_ERR_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--nd_b
gndb : IF (C_HAS_ND_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
ASSERT (C_HAS_CE_B /= 0)
REPORT "Invalid configuration: ND_B port requires CE_B port"
SEVERITY WARNING;
ND_B <= nd_b_i;
END GENERATE gndb;
ngndb : IF (C_HAS_ND_B = 0 OR C_HAS_BPORTS = 0) GENERATE
ND_B <= '0';
END GENERATE ngndb;
ASSERT (NOT(C_HAS_ND_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate ND_B when C_HAS_BPORTS=0"
SEVERITY WARNING;
--run_disp_b
grdb : IF (C_HAS_RUN_DISP_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
RUN_DISP_B <= run_disp_b_i;
END GENERATE grdb;
ngrdb : IF (C_HAS_RUN_DISP_B = 0 OR C_HAS_BPORTS = 0) GENERATE
RUN_DISP_B <= '0';
END GENERATE ngrdb;
ASSERT (NOT(C_HAS_RUN_DISP_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate RUN_DISP_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
--sym_disp_b
gsdb : IF (C_HAS_SYM_DISP_B /= 0 AND C_HAS_BPORTS /= 0) GENERATE
SYM_DISP_B <= sym_disp_b_i;
END GENERATE gsdb;
ngsdb : IF (C_HAS_SYM_DISP_B = 0 OR C_HAS_BPORTS = 0) GENERATE
SYM_DISP_B <= "00";
END GENERATE ngsdb;
ASSERT (NOT(C_HAS_SYM_DISP_B /= 0 AND C_HAS_BPORTS = 0))
REPORT "Invalid configuration: Will not generate SYM_DISP_B when " &
"C_HAS_BPORTS=0"
SEVERITY WARNING;
END xilinx;
| gpl-3.0 | e218b8cf1b71336ed09f965d3600fda5 | 0.471652 | 3.497154 | false | false | false | false |
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